OpenCores
URL https://opencores.org/ocsvn/systemcdes/systemcdes/trunk

Subversion Repositories systemcdes

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /
    from Rev 10 to Rev 11
    Reverse comparison

Rev 10 → Rev 11

/systemcdes/trunk/rtl/verilog/wb_descontroller.v
0,0 → 1,161
//////////////////////////////////////////////////////////////////////
//// ////
//// Wishbone Interface for DES coprocesor ////
//// ////
//// This file is part of the SystemC AES ////
//// ////
//// To Do: ////
//// - done ////
//// ////
//// Author(s): ////
//// - Javier Castillo, jcastilo@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
`include "timescale.v"
 
module des_top(clk,reset,wb_stb_i,wb_dat_o,wb_dat_i,wb_ack_o,
wb_adr_i,wb_we_i,wb_cyc_i,wb_sel_i);
 
input clk;
input reset;
input wb_stb_i;
output [31:0] wb_dat_o;
input [31:0] wb_dat_i;
output wb_ack_o;
input [7:0] wb_adr_i;
input wb_we_i;
input wb_cyc_i;
input [3:0] wb_sel_i;
 
reg [31:0] wb_dat_o;
reg wb_ack_o;
 
wire [63:0] data_i;
reg [63:0] data_o;
wire ready_i;
reg [63:0] key_o;
 
 
reg [31:0] control_reg;
reg [63:0] cypher_data_reg;
 
des des(.clk(clk),
.reset(~control_reg[0]),
.load_i(control_reg[1]),
.decrypt_i(control_reg[3]),
.ready_o(ready_i),
.data_o(data_i),
.data_i(data_o),
.key_i(key_o)
);
 
always @(posedge clk or posedge reset)
begin
if(reset==1)
begin
wb_ack_o<=#1 0;
wb_dat_o<=#1 0;
control_reg <= #1 32'h60;
cypher_data_reg <= #1 64'h0;
key_o <= #1 32'h0;
data_o <= #1 32'h0;
end
else
begin
 
control_reg[31:4]<= #1 28'h6;
 
if(ready_i)
begin
control_reg[2] <= #1 1'b1;
cypher_data_reg <= #1 data_i;
end
if(wb_stb_i && wb_cyc_i && wb_we_i && ~wb_ack_o)
begin
wb_ack_o<=#1 1;
case(wb_adr_i)
8'h0:
begin
//Writing control register
control_reg[3:0]<= #1 wb_dat_i[3:0];
end
8'h4:
begin
data_o[63:32]<= #1 wb_dat_i;
end
8'h8:
begin
data_o[31:0]<= #1 wb_dat_i;
end
8'hC:
begin
key_o[63:32]<= #1 wb_dat_i;
end
8'h10:
begin
key_o[31:0]<= #1 wb_dat_i;
end
endcase
end
else if(wb_stb_i && wb_cyc_i && ~wb_we_i && ~wb_ack_o)
begin
wb_ack_o<=#1 1;
case(wb_adr_i)
8'h0:
begin
wb_dat_o<= #1 control_reg;
control_reg[2]<=1'b0;
end
8'h14:
begin
wb_dat_o<= #1 cypher_data_reg[63:32];
end
8'h18:
begin
wb_dat_o<= #1 cypher_data_reg[31:0];
end
endcase
end
else
begin
wb_ack_o<=#1 0;
control_reg[1]<= #1 1'b0;
end
 
end
end
 
 
endmodule
 
/systemcdes/trunk/rtl/verilog/des.v
0,0 → 1,282
//////////////////////////////////////////////////////////////////////
//// ////
//// DES Top ////
//// ////
//// This file is part of the SystemC DES ////
//// ////
//// Description: ////
//// Top file of DES project ////
//// ////
//// Generated automatically using SystemC to Verilog translator ////
//// ////
//// To Do: ////
//// - done ////
//// ////
//// Author(s): ////
//// - Javier Castillo, jcastilo@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2004/07/05 17:31:17 jcastillo
// First import
//
 
 
module des(clk,reset,load_i,decrypt_i,data_i,key_i,data_o,ready_o);
input clk;
input reset;
input load_i;
input decrypt_i;
input [63:0] data_i;
input [63:0] key_i;
output [63:0] data_o;
output ready_o;
 
reg [63:0] data_o;
reg ready_o;
 
 
reg [3:0] stage1_iter;
 
reg [3:0] next_stage1_iter;
 
reg next_ready_o;
 
reg[63:0] next_data_o;
 
reg data_ready;
 
reg next_data_ready;
 
reg [31:0] stage1_L_i;
 
reg [31:0] stage1_R_i;
 
reg [55:0] stage1_round_key_i;
 
reg [3:0] stage1_iteration_i;
wire [31:0] stage1_R_o;
wire [31:0] stage1_L_o;
wire [55:0] stage1_round_key_o;
wire [5:0] s1_stag1_i;
wire [5:0] s2_stag1_i;
wire [5:0] s3_stag1_i;
wire [5:0] s4_stag1_i;
wire [5:0] s5_stag1_i;
wire [5:0] s6_stag1_i;
wire [5:0] s7_stag1_i;
wire [5:0] s8_stag1_i;
wire [3:0] s1_stag1_o;
wire [3:0] s2_stag1_o;
wire [3:0] s3_stag1_o;
wire [3:0] s4_stag1_o;
wire [3:0] s5_stag1_o;
wire [3:0] s6_stag1_o;
wire [3:0] s7_stag1_o;
wire [3:0] s8_stag1_o;
 
reg[31:0] L_i_var,R_i_var;
reg[63:0] data_i_var,data_o_var,data_o_var_t,key_i_var;
reg[55:0] key_var_perm;
 
 
desround rd1 (.clk(clk), .reset(reset), .iteration_i(stage1_iteration_i), .decrypt_i(decrypt_i), .R_i(stage1_R_i), .L_i(stage1_L_i), .Key_i(stage1_round_key_i), .R_o(stage1_R_o), .L_o(stage1_L_o), .Key_o(stage1_round_key_o), .s1_o(s1_stag1_i), .s2_o(s2_stag1_i), .s3_o(s3_stag1_i), .s4_o(s4_stag1_i), .s5_o(s5_stag1_i), .s6_o(s6_stag1_i), .s7_o(s7_stag1_i), .s8_o(s8_stag1_i), .s1_i(s1_stag1_o), .s2_i(s2_stag1_o), .s3_i(s3_stag1_o), .s4_i(s4_stag1_o), .s5_i(s5_stag1_o), .s6_i(s6_stag1_o), .s7_i(s7_stag1_o), .s8_i(s8_stag1_o));
s1 sbox1 (.stage1_input(s1_stag1_i), .stage1_output(s1_stag1_o));
s2 sbox2 (.stage1_input(s2_stag1_i), .stage1_output(s2_stag1_o));
s3 sbox3 (.stage1_input(s3_stag1_i), .stage1_output(s3_stag1_o));
s4 sbox4 (.stage1_input(s4_stag1_i), .stage1_output(s4_stag1_o));
s5 sbox5 (.stage1_input(s5_stag1_i), .stage1_output(s5_stag1_o));
s6 sbox6 (.stage1_input(s6_stag1_i), .stage1_output(s6_stag1_o));
s7 sbox7 (.stage1_input(s7_stag1_i), .stage1_output(s7_stag1_o));
s8 sbox8 (.stage1_input(s8_stag1_i), .stage1_output(s8_stag1_o));
 
always @(posedge clk or negedge reset)
 
begin
 
if(!reset)
begin
 
ready_o = (0);
data_o = (0);
stage1_iter = (0);
data_ready = (1);
end
else
begin
 
ready_o = (next_ready_o);
data_o = (next_data_o);
stage1_iter = (next_stage1_iter);
data_ready = (next_data_ready);
end
end
 
 
always @( data_i or key_i or load_i or stage1_iter or data_ready or stage1_R_o or stage1_L_o or stage1_round_key_o)
 
begin
 
L_i_var=0;
R_i_var=0;
data_i_var=0;
next_ready_o = (0);
next_data_ready = (data_ready);
next_stage1_iter = (stage1_iter);
 
stage1_L_i = (0);
stage1_R_i = (0);
stage1_round_key_i = (0);
 
key_i_var=key_i;
key_var_perm[55]=key_i_var[7];key_var_perm[54]=key_i_var[15];key_var_perm[53]=key_i_var[23];key_var_perm[52]=key_i_var[31];
key_var_perm[51]=key_i_var[39];key_var_perm[50]=key_i_var[47];key_var_perm[49]=key_i_var[55];key_var_perm[48]=key_i_var[63];
 
key_var_perm[47]=key_i_var[6];key_var_perm[46]=key_i_var[14];key_var_perm[45]=key_i_var[22];key_var_perm[44]=key_i_var[30];
key_var_perm[43]=key_i_var[38];key_var_perm[42]=key_i_var[46];key_var_perm[41]=key_i_var[54];key_var_perm[40]=key_i_var[62];
key_var_perm[39]=key_i_var[5];key_var_perm[38]=key_i_var[13];key_var_perm[37]=key_i_var[21];key_var_perm[36]=key_i_var[29];
key_var_perm[35]=key_i_var[37];key_var_perm[34]=key_i_var[45];key_var_perm[33]=key_i_var[53];key_var_perm[32]=key_i_var[61];
key_var_perm[31]=key_i_var[4];key_var_perm[30]=key_i_var[12];key_var_perm[29]=key_i_var[20];key_var_perm[28]=key_i_var[28];
key_var_perm[27]=key_i_var[1];key_var_perm[26]=key_i_var[9];key_var_perm[25]=key_i_var[17];key_var_perm[24]=key_i_var[25];
key_var_perm[23]=key_i_var[33];key_var_perm[22]=key_i_var[41];key_var_perm[21]=key_i_var[49];key_var_perm[20]=key_i_var[57];
key_var_perm[19]=key_i_var[2];key_var_perm[18]=key_i_var[10];key_var_perm[17]=key_i_var[18];key_var_perm[16]=key_i_var[26];
key_var_perm[15]=key_i_var[34];key_var_perm[14]=key_i_var[42];key_var_perm[13]=key_i_var[50];key_var_perm[12]=key_i_var[58];
key_var_perm[11]=key_i_var[3];key_var_perm[10]=key_i_var[11];key_var_perm[9]=key_i_var[19];key_var_perm[8]=key_i_var[27];
key_var_perm[7]=key_i_var[35];key_var_perm[6]=key_i_var[43];key_var_perm[5]=key_i_var[51];key_var_perm[4]=key_i_var[59];
key_var_perm[3]=key_i_var[36];key_var_perm[2]=key_i_var[44];key_var_perm[1]=key_i_var[52];key_var_perm[0]=key_i_var[60];
data_i_var=data_i;
L_i_var[31]=data_i_var[6];L_i_var[30]=data_i_var[14];L_i_var[29]=data_i_var[22];L_i_var[28]=data_i_var[30];
L_i_var[27]=data_i_var[38];L_i_var[26]=data_i_var[46];L_i_var[25]=data_i_var[54];L_i_var[24]=data_i_var[62];
 
L_i_var[23]=data_i_var[4];L_i_var[22]=data_i_var[12];L_i_var[21]=data_i_var[20];L_i_var[20]=data_i_var[28];
L_i_var[19]=data_i_var[36];L_i_var[18]=data_i_var[44];L_i_var[17]=data_i_var[52];L_i_var[16]=data_i_var[60];
 
L_i_var[15]=data_i_var[2];L_i_var[14]=data_i_var[10];L_i_var[13]=data_i_var[18];L_i_var[12]=data_i_var[26];
L_i_var[11]=data_i_var[34];L_i_var[10]=data_i_var[42];L_i_var[9]=data_i_var[50];L_i_var[8]=data_i_var[58];
 
L_i_var[7]=data_i_var[0];L_i_var[6]=data_i_var[8];L_i_var[5]=data_i_var[16];L_i_var[4]=data_i_var[24];
L_i_var[3]=data_i_var[32];L_i_var[2]=data_i_var[40];L_i_var[1]=data_i_var[48];L_i_var[0]=data_i_var[56];
R_i_var[31]=data_i_var[7];R_i_var[30]=data_i_var[15];R_i_var[29]=data_i_var[23];R_i_var[28]=data_i_var[31];
R_i_var[27]=data_i_var[39];R_i_var[26]=data_i_var[47];R_i_var[25]=data_i_var[55];R_i_var[24]=data_i_var[63];
 
R_i_var[23]=data_i_var[5];R_i_var[22]=data_i_var[13];R_i_var[21]=data_i_var[21];R_i_var[20]=data_i_var[29];
R_i_var[19]=data_i_var[37];R_i_var[18]=data_i_var[45];R_i_var[17]=data_i_var[53];R_i_var[16]=data_i_var[61];
 
R_i_var[15]=data_i_var[3];R_i_var[14]=data_i_var[11];R_i_var[13]=data_i_var[19];R_i_var[12]=data_i_var[27];
R_i_var[11]=data_i_var[35];R_i_var[10]=data_i_var[43];R_i_var[9]=data_i_var[51];R_i_var[8]=data_i_var[59];
 
R_i_var[7]=data_i_var[1];R_i_var[6]=data_i_var[9];R_i_var[5]=data_i_var[17];R_i_var[4]=data_i_var[25];
R_i_var[3]=data_i_var[33];R_i_var[2]=data_i_var[41];R_i_var[1]=data_i_var[49];R_i_var[0]=data_i_var[57];
 
 
data_o_var_t[63:32]=stage1_R_o;
data_o_var_t[31:0]=stage1_L_o;
data_o_var[63]=data_o_var_t[24];data_o_var[62]=data_o_var_t[56];data_o_var[61]=data_o_var_t[16];data_o_var[60]=data_o_var_t[48];
data_o_var[59]=data_o_var_t[8];data_o_var[58]=data_o_var_t[40];data_o_var[57]=data_o_var_t[0];data_o_var[56]=data_o_var_t[32];
data_o_var[55]=data_o_var_t[25];data_o_var[54]=data_o_var_t[57];data_o_var[53]=data_o_var_t[17];data_o_var[52]=data_o_var_t[49];
data_o_var[51]=data_o_var_t[9];data_o_var[50]=data_o_var_t[41];data_o_var[49]=data_o_var_t[1];data_o_var[48]=data_o_var_t[33];
data_o_var[47]=data_o_var_t[26];data_o_var[46]=data_o_var_t[58];data_o_var[45]=data_o_var_t[18];data_o_var[44]=data_o_var_t[50];
data_o_var[43]=data_o_var_t[10];data_o_var[42]=data_o_var_t[42];data_o_var[41]=data_o_var_t[2];data_o_var[40]=data_o_var_t[34];
data_o_var[39]=data_o_var_t[27];data_o_var[38]=data_o_var_t[59];data_o_var[37]=data_o_var_t[19];data_o_var[36]=data_o_var_t[51];
data_o_var[35]=data_o_var_t[11];data_o_var[34]=data_o_var_t[43];data_o_var[33]=data_o_var_t[3];data_o_var[32]=data_o_var_t[35];
data_o_var[31]=data_o_var_t[28];data_o_var[30]=data_o_var_t[60];data_o_var[29]=data_o_var_t[20];data_o_var[28]=data_o_var_t[52];
data_o_var[27]=data_o_var_t[12];data_o_var[26]=data_o_var_t[44];data_o_var[25]=data_o_var_t[4];data_o_var[24]=data_o_var_t[36];
data_o_var[23]=data_o_var_t[29];data_o_var[22]=data_o_var_t[61];data_o_var[21]=data_o_var_t[21];data_o_var[20]=data_o_var_t[53];
data_o_var[19]=data_o_var_t[13];data_o_var[18]=data_o_var_t[45];data_o_var[17]=data_o_var_t[5];data_o_var[16]=data_o_var_t[37];
data_o_var[15]=data_o_var_t[30];data_o_var[14]=data_o_var_t[62];data_o_var[13]=data_o_var_t[22];data_o_var[12]=data_o_var_t[54];
data_o_var[11]=data_o_var_t[14];data_o_var[10]=data_o_var_t[46];data_o_var[9]=data_o_var_t[6];data_o_var[8]=data_o_var_t[38];
data_o_var[7]=data_o_var_t[31];data_o_var[6]=data_o_var_t[63];data_o_var[5]=data_o_var_t[23];data_o_var[4]=data_o_var_t[55];
data_o_var[3]=data_o_var_t[15];data_o_var[2]=data_o_var_t[47];data_o_var[1]=data_o_var_t[7];data_o_var[0]=data_o_var_t[39];
next_data_o = (data_o_var);
stage1_iteration_i = (stage1_iter);
 
next_ready_o = (0);
stage1_L_i = (stage1_L_o);
stage1_R_i = (stage1_R_o);
stage1_round_key_i = (stage1_round_key_o);
case(stage1_iter)
0:
begin
if(load_i)
begin
next_stage1_iter = (1);
stage1_L_i = (L_i_var);
stage1_R_i = (R_i_var);
stage1_round_key_i = (key_var_perm);
next_data_ready = (0);
end
else if (!data_ready)
begin
 
next_stage1_iter = (0);
next_ready_o = (1);
next_data_ready = (1);
end
end
15:
next_stage1_iter = (0);
default:
next_stage1_iter = (stage1_iter+1);
endcase
end
 
endmodule
/systemcdes/trunk/rtl/verilog/key_gen.v
0,0 → 1,196
//////////////////////////////////////////////////////////////////////
//// ////
//// Key generator ////
//// ////
//// This file is part of the SystemC DES ////
//// ////
//// Description: ////
//// Generate the next key from the previous one ////
//// ////
//// Generated automatically using SystemC to Verilog translator ////
//// ////
//// To Do: ////
//// - done ////
//// ////
//// Author(s): ////
//// - Javier Castillo, jcastilo@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2004/07/05 17:31:17 jcastillo
// First import
//
 
 
module key_gen(previous_key,iteration,decrypt,non_perm_key,new_key);
 
input [55:0] previous_key;
input [3:0] iteration;
input decrypt;
output [55:0] non_perm_key;
output [47:0] new_key;
 
reg [55:0] non_perm_key;
reg [47:0] new_key;
 
 
reg prev0,prev1;
reg[55:0] prev_key_var,non_perm_key_var;
reg[47:0] new_key_var;
reg[27:0] semi_key;
 
 
always @( previous_key or iteration or decrypt)
 
begin
 
prev_key_var=previous_key;
new_key_var=0;
new_key = (0);
non_perm_key_var=0;
non_perm_key = (0);
if(!decrypt)
begin
 
case(iteration)
 
0, 1, 8, 15:
begin
semi_key=prev_key_var[55:28];
prev0=semi_key[27];
semi_key=semi_key<<1;
semi_key[0]=prev0;
non_perm_key_var[55:28]=semi_key;
semi_key=prev_key_var[27:0];
prev0=semi_key[27];
semi_key=semi_key<<1;
semi_key[0]=prev0;
non_perm_key_var[27:0]=semi_key;
end
default:
begin
semi_key=prev_key_var[55:28];
prev0=semi_key[27];
prev1=semi_key[26];
semi_key=semi_key<<2;
semi_key[1]=prev0;
semi_key[0]=prev1;
non_perm_key_var[55:28]=semi_key;
semi_key=prev_key_var[27:0];
prev0=semi_key[27];
prev1=semi_key[26];
semi_key=semi_key<<2;
semi_key[1]=prev0;
semi_key[0]=prev1;
non_perm_key_var[27:0]=semi_key;
end
endcase
end
else
begin
case(iteration)
 
0:
begin
semi_key=prev_key_var[55:28];
non_perm_key_var[55:28]=semi_key;
semi_key=prev_key_var[27:0];
non_perm_key_var[27:0]=semi_key;
end
1, 8, 15:
begin
semi_key=prev_key_var[55:28];
prev0=semi_key[0];
semi_key=semi_key>>1;
semi_key[27]=prev0;
non_perm_key_var[55:28]=semi_key;
semi_key=prev_key_var[27:0];
prev0=semi_key[0];
semi_key=semi_key>>1;
semi_key[27]=prev0;
non_perm_key_var[27:0]=semi_key;
end
default:
begin
semi_key=prev_key_var[55:28];
prev0=semi_key[0];
prev1=semi_key[1];
semi_key=semi_key>>2;
semi_key[26]=prev0;
semi_key[27]=prev1;
non_perm_key_var[55:28]=semi_key;
semi_key=prev_key_var[27:0];
prev0=semi_key[0];
prev1=semi_key[1];
semi_key=semi_key>>2;
semi_key[26]=prev0;
semi_key[27]=prev1;
non_perm_key_var[27:0]=semi_key;
end
endcase
end
 
non_perm_key = (non_perm_key_var);
 
new_key_var[47]=non_perm_key_var[42]; new_key_var[46]=non_perm_key_var[39]; new_key_var[45]=non_perm_key_var[45]; new_key_var[44]=non_perm_key_var[32];
new_key_var[43]=non_perm_key_var[55]; new_key_var[42]=non_perm_key_var[51]; new_key_var[41]=non_perm_key_var[53]; new_key_var[40]=non_perm_key_var[28];
new_key_var[39]=non_perm_key_var[41]; new_key_var[38]=non_perm_key_var[50]; new_key_var[37]=non_perm_key_var[35]; new_key_var[36]=non_perm_key_var[46];
new_key_var[35]=non_perm_key_var[33]; new_key_var[34]=non_perm_key_var[37]; new_key_var[33]=non_perm_key_var[44]; new_key_var[32]=non_perm_key_var[52];
new_key_var[31]=non_perm_key_var[30]; new_key_var[30]=non_perm_key_var[48]; new_key_var[29]=non_perm_key_var[40]; new_key_var[28]=non_perm_key_var[49];
new_key_var[27]=non_perm_key_var[29]; new_key_var[26]=non_perm_key_var[36]; new_key_var[25]=non_perm_key_var[43]; new_key_var[24]=non_perm_key_var[54];
 
new_key_var[23]=non_perm_key_var[15]; new_key_var[22]=non_perm_key_var[4]; new_key_var[21]=non_perm_key_var[25]; new_key_var[20]=non_perm_key_var[19];
new_key_var[19]=non_perm_key_var[9]; new_key_var[18]=non_perm_key_var[1]; new_key_var[17]=non_perm_key_var[26]; new_key_var[16]=non_perm_key_var[16];
 
new_key_var[15]=non_perm_key_var[5]; new_key_var[14]=non_perm_key_var[11]; new_key_var[13]=non_perm_key_var[23]; new_key_var[12]=non_perm_key_var[8];
new_key_var[11]=non_perm_key_var[12]; new_key_var[10]=non_perm_key_var[7]; new_key_var[9]=non_perm_key_var[17]; new_key_var[8]=non_perm_key_var[0];
new_key_var[7]=non_perm_key_var[22]; new_key_var[6]=non_perm_key_var[3]; new_key_var[5]=non_perm_key_var[10]; new_key_var[4]=non_perm_key_var[14];
new_key_var[3]=non_perm_key_var[6]; new_key_var[2]=non_perm_key_var[20]; new_key_var[1]=non_perm_key_var[27]; new_key_var[0]=non_perm_key_var[24];
 
new_key = (new_key_var);
 
end
 
endmodule
/systemcdes/trunk/rtl/verilog/desround.v
0,0 → 1,224
//////////////////////////////////////////////////////////////////////
//// ////
//// DES Round ////
//// ////
//// This file is part of the SystemC DES ////
//// ////
//// Description: ////
//// Performs a round of DES algorithm ////
//// ////
//// Generated automatically using SystemC to Verilog translator ////
//// ////
//// To Do: ////
//// - done ////
//// ////
//// Author(s): ////
//// - Javier Castillo, jcastilo@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2004/08/16 09:35:58 jcastillo
// Add timescale directive
//
// Revision 1.1.1.1 2004/07/05 17:31:16 jcastillo
// First import
//
 
`timescale 10ns/1ns
 
module desround(clk,reset,iteration_i,decrypt_i,R_i,L_i,Key_i,R_o,L_o,Key_o,s1_o,s2_o,s3_o,s4_o,s5_o,s6_o,s7_o,s8_o,s1_i,s2_i,s3_i,s4_i,s5_i,s6_i,s7_i,s8_i);
 
input clk;
input reset;
input [3:0] iteration_i;
input decrypt_i;
input [31:0] R_i;
input [31:0] L_i;
input [55:0] Key_i;
output [31:0] R_o;
output [31:0] L_o;
output [55:0] Key_o;
output [5:0] s1_o;
output [5:0] s2_o;
output [5:0] s3_o;
output [5:0] s4_o;
output [5:0] s5_o;
output [5:0] s6_o;
output [5:0] s7_o;
output [5:0] s8_o;
input [3:0] s1_i;
input [3:0] s2_i;
input [3:0] s3_i;
input [3:0] s4_i;
input [3:0] s5_i;
input [3:0] s6_i;
input [3:0] s7_i;
input [3:0] s8_i;
 
reg [31:0] R_o;
reg [31:0] L_o;
reg [55:0] Key_o;
reg [5:0] s1_o;
reg [5:0] s2_o;
reg [5:0] s3_o;
reg [5:0] s4_o;
reg [5:0] s5_o;
reg [5:0] s6_o;
reg [5:0] s7_o;
reg [5:0] s8_o;
 
 
reg [55:0] previous_key;
 
reg [3:0] iteration;
 
reg decrypt;
 
 
wire [55:0] non_perm_key;
 
 
wire [47:0] new_key;
 
reg [31:0] next_R;
 
reg [31:0] expanRSig;
 
reg[47:0] expandedR;
reg[47:0] round_key;
reg[47:0] KER;
reg[31:0] R_i_var;
reg[31:0] Soutput;
reg[31:0] f;
 
 
key_gen kg1 (.previous_key(previous_key), .iteration(iteration), .decrypt(decrypt), .new_key(new_key), .non_perm_key(non_perm_key));
 
always @(posedge clk or negedge reset)
 
begin
 
if(!reset)
begin
 
L_o = (0);
R_o = (0);
Key_o = (0);
end
else
begin
 
L_o = (R_i);
R_o = (next_R);
Key_o = (non_perm_key);
end
 
end
 
 
always @( R_i or L_i or Key_i or iteration_i or decrypt_i or new_key or s1_i or s2_i or s3_i or s4_i or s5_i or s6_i or s7_i or s8_i)
 
begin
 
R_i_var=R_i;
 
expandedR[47]=R_i_var[0]; expandedR[46]=R_i_var[31]; expandedR[45]=R_i_var[30]; expandedR[44]=R_i_var[29];
expandedR[43]=R_i_var[28]; expandedR[42]=R_i_var[27]; expandedR[41]=R_i_var[28]; expandedR[40]=R_i_var[27];
expandedR[39]=R_i_var[26]; expandedR[38]=R_i_var[25]; expandedR[37]=R_i_var[24]; expandedR[36]=R_i_var[23];
expandedR[35]=R_i_var[24]; expandedR[34]=R_i_var[23]; expandedR[33]=R_i_var[22]; expandedR[32]=R_i_var[21];
expandedR[31]=R_i_var[20]; expandedR[30]=R_i_var[19]; expandedR[29]=R_i_var[20]; expandedR[28]=R_i_var[19];
expandedR[27]=R_i_var[18]; expandedR[26]=R_i_var[17]; expandedR[25]=R_i_var[16]; expandedR[24]=R_i_var[15];
expandedR[23]=R_i_var[16]; expandedR[22]=R_i_var[15]; expandedR[21]=R_i_var[14]; expandedR[20]=R_i_var[13];
expandedR[19]=R_i_var[12]; expandedR[18]=R_i_var[11]; expandedR[17]=R_i_var[12]; expandedR[16]=R_i_var[11];
 
expandedR[15]=R_i_var[10]; expandedR[14]=R_i_var[9]; expandedR[13]=R_i_var[8]; expandedR[12]=R_i_var[7];
expandedR[11]=R_i_var[8]; expandedR[10]=R_i_var[7]; expandedR[9]=R_i_var[6]; expandedR[8]=R_i_var[5];
expandedR[7]=R_i_var[4]; expandedR[6]=R_i_var[3]; expandedR[5]=R_i_var[4]; expandedR[4]=R_i_var[3];
expandedR[3]=R_i_var[2]; expandedR[2]=R_i_var[1]; expandedR[1]=R_i_var[0]; expandedR[0]=R_i_var[31];
previous_key = (Key_i);
iteration = (iteration_i);
decrypt = (decrypt_i);
round_key=new_key;
KER=expandedR^round_key;
s1_o = (KER[47:42]);
s2_o = (KER[41:36]);
s3_o = (KER[35:30]);
s4_o = (KER[29:24]);
s5_o = (KER[23:18]);
s6_o = (KER[17:12]);
s7_o = (KER[11:6]);
s8_o = (KER[5:0]);
 
Soutput[31:28]=s1_i;
Soutput[27:24]=s2_i;
Soutput[23:20]=s3_i;
Soutput[19:16]=s4_i;
Soutput[15:12]=s5_i;
Soutput[11:8]=s6_i;
Soutput[7:4]=s7_i;
Soutput[3:0]=s8_i;
f[31]=Soutput[16]; f[30]=Soutput[25]; f[29]=Soutput[12]; f[28]=Soutput[11];
f[27]=Soutput[3]; f[26]=Soutput[20]; f[25]=Soutput[4]; f[24]=Soutput[15];
f[23]=Soutput[31]; f[22]=Soutput[17]; f[21]=Soutput[9]; f[20]=Soutput[6];
f[19]=Soutput[27]; f[18]=Soutput[14]; f[17]=Soutput[1]; f[16]=Soutput[22];
f[15]=Soutput[30]; f[14]=Soutput[24]; f[13]=Soutput[8]; f[12]=Soutput[18];
f[11]=Soutput[0]; f[10]=Soutput[5]; f[9]=Soutput[29]; f[8]=Soutput[23];
f[7]=Soutput[13]; f[6]=Soutput[19]; f[5]=Soutput[2]; f[4]=Soutput[26];
f[3]=Soutput[10]; f[2]=Soutput[21]; f[1]=Soutput[28]; f[0]=Soutput[7];
next_R = (L_i^f);
expanRSig = (L_i^f);
end
 
endmodule
/systemcdes/trunk/rtl/verilog/s1.v
0,0 → 1,135
//////////////////////////////////////////////////////////////////////
//// ////
//// SBOX 1 ////
//// ////
//// This file is part of the SystemC DES ////
//// ////
//// Description: ////
//// Sbox of DES algorithm ////
//// ////
//// Generated automatically using SystemC to Verilog translator ////
//// ////
//// To Do: ////
//// - done ////
//// ////
//// Author(s): ////
//// - Javier Castillo, jcastilo@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2004/07/05 17:31:17 jcastillo
// First import
//
 
 
module s1(stage1_input,stage1_output);
input [5:0] stage1_input;
output [3:0] stage1_output;
 
reg [3:0] stage1_output;
 
 
always @( stage1_input)
 
begin
 
case(stage1_input)
0: stage1_output = (14);
1: stage1_output = (0);
2: stage1_output = (4);
3: stage1_output = (15);
4: stage1_output = (13);
5: stage1_output = (7);
6: stage1_output = (1);
7: stage1_output = (4);
8: stage1_output = (2);
9: stage1_output = (14);
10: stage1_output = (15);
11: stage1_output = (2);
12: stage1_output = (11);
13: stage1_output = (13);
14: stage1_output = (8);
15: stage1_output = (1);
16: stage1_output = (3);
17: stage1_output = (10);
18: stage1_output = (10);
19: stage1_output = (6);
20: stage1_output = (6);
21: stage1_output = (12);
22: stage1_output = (12);
23: stage1_output = (11);
24: stage1_output = (5);
25: stage1_output = (9);
26: stage1_output = (9);
27: stage1_output = (5);
28: stage1_output = (0);
29: stage1_output = (3);
30: stage1_output = (7);
31: stage1_output = (8);
32: stage1_output = (4);
33: stage1_output = (15);
34: stage1_output = (1);
35: stage1_output = (12);
36: stage1_output = (14);
37: stage1_output = (8);
38: stage1_output = (8);
39: stage1_output = (2);
40: stage1_output = (13);
41: stage1_output = (4);
42: stage1_output = (6);
43: stage1_output = (9);
44: stage1_output = (2);
45: stage1_output = (1);
46: stage1_output = (11);
47: stage1_output = (7);
48: stage1_output = (15);
49: stage1_output = (5);
50: stage1_output = (12);
51: stage1_output = (11);
52: stage1_output = (9);
53: stage1_output = (3);
54: stage1_output = (7);
55: stage1_output = (14);
56: stage1_output = (3);
57: stage1_output = (10);
58: stage1_output = (10);
59: stage1_output = (0);
60: stage1_output = (5);
61: stage1_output = (6);
62: stage1_output = (0);
63: stage1_output = (13);
endcase
 
end
 
endmodule
/systemcdes/trunk/rtl/verilog/s2.v
0,0 → 1,135
//////////////////////////////////////////////////////////////////////
//// ////
//// SBOX 2 ////
//// ////
//// This file is part of the SystemC DES ////
//// ////
//// Description: ////
//// Sbox of DES algorithm ////
//// ////
//// Generated automatically using SystemC to Verilog translator ////
//// ////
//// To Do: ////
//// - done ////
//// ////
//// Author(s): ////
//// - Javier Castillo, jcastilo@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2004/07/05 17:31:17 jcastillo
// First import
//
 
 
module s2(stage1_input,stage1_output);
input [5:0] stage1_input;
output [3:0] stage1_output;
 
reg [3:0] stage1_output;
 
 
always @( stage1_input)
 
begin
 
 
case(stage1_input)
0: stage1_output = (15);
1: stage1_output = (3);
2: stage1_output = (1);
3: stage1_output = (13);
4: stage1_output = (8);
5: stage1_output = (4);
6: stage1_output = (14);
7: stage1_output = (7);
8: stage1_output = (6);
9: stage1_output = (15);
10: stage1_output = (11);
11: stage1_output = (2);
12: stage1_output = (3);
13: stage1_output = (8);
14: stage1_output = (4);
15: stage1_output = (14);
16: stage1_output = (9);
17: stage1_output = (12);
18: stage1_output = (7);
19: stage1_output = (0);
20: stage1_output = (2);
21: stage1_output = (1);
22: stage1_output = (13);
23: stage1_output = (10);
24: stage1_output = (12);
25: stage1_output = (6);
26: stage1_output = (0);
27: stage1_output = (9);
28: stage1_output = (5);
29: stage1_output = (11);
30: stage1_output = (10);
31: stage1_output = (5);
32: stage1_output = (0);
33: stage1_output = (13);
34: stage1_output = (14);
35: stage1_output = (8);
36: stage1_output = (7);
37: stage1_output = (10);
38: stage1_output = (11);
39: stage1_output = (1);
40: stage1_output = (10);
41: stage1_output = (3);
42: stage1_output = (4);
43: stage1_output = (15);
44: stage1_output = (13);
45: stage1_output = (4);
46: stage1_output = (1);
47: stage1_output = (2);
48: stage1_output = (5);
49: stage1_output = (11);
50: stage1_output = (8);
51: stage1_output = (6);
52: stage1_output = (12);
53: stage1_output = (7);
54: stage1_output = (6);
55: stage1_output = (12);
56: stage1_output = (9);
57: stage1_output = (0);
58: stage1_output = (3);
59: stage1_output = (5);
60: stage1_output = (2);
61: stage1_output = (14);
62: stage1_output = (15);
63: stage1_output = (9);
endcase
 
end
 
endmodule
/systemcdes/trunk/rtl/verilog/s3.v
0,0 → 1,135
//////////////////////////////////////////////////////////////////////
//// ////
//// SBOX 3 ////
//// ////
//// This file is part of the SystemC DES ////
//// ////
//// Description: ////
//// Sbox of DES algorithm ////
//// ////
//// Generated automatically using SystemC to Verilog translator ////
//// ////
//// To Do: ////
//// - done ////
//// ////
//// Author(s): ////
//// - Javier Castillo, jcastilo@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2004/07/05 17:31:17 jcastillo
// First import
//
 
 
module s3(stage1_input,stage1_output);
input [5:0] stage1_input;
output [3:0] stage1_output;
 
reg [3:0] stage1_output;
 
 
always @( stage1_input)
 
begin
 
case(stage1_input)
 
0: stage1_output = (10);
1: stage1_output = (13);
2: stage1_output = (0);
3: stage1_output = (7);
4: stage1_output = (9);
5: stage1_output = (0);
6: stage1_output = (14);
7: stage1_output = (9);
8: stage1_output = (6);
9: stage1_output = (3);
10: stage1_output = (3);
11: stage1_output = (4);
12: stage1_output = (15);
13: stage1_output = (6);
14: stage1_output = (5);
15: stage1_output = (10);
16: stage1_output = (1);
17: stage1_output = (2);
18: stage1_output = (13);
19: stage1_output = (8);
20: stage1_output = (12);
21: stage1_output = (5);
22: stage1_output = (7);
23: stage1_output = (14);
24: stage1_output = (11);
25: stage1_output = (12);
26: stage1_output = (4);
27: stage1_output = (11);
28: stage1_output = (2);
29: stage1_output = (15);
30: stage1_output = (8);
31: stage1_output = (1);
32: stage1_output = (13);
33: stage1_output = (1);
34: stage1_output = (6);
35: stage1_output = (10);
36: stage1_output = (4);
37: stage1_output = (13);
38: stage1_output = (9);
39: stage1_output = (0);
40: stage1_output = (8);
41: stage1_output = (6);
42: stage1_output = (15);
43: stage1_output = (9);
44: stage1_output = (3);
45: stage1_output = (8);
46: stage1_output = (0);
47: stage1_output = (7);
48: stage1_output = (11);
49: stage1_output = (4);
50: stage1_output = (1);
51: stage1_output = (15);
52: stage1_output = (2);
53: stage1_output = (14);
54: stage1_output = (12);
55: stage1_output = (3);
56: stage1_output = (5);
57: stage1_output = (11);
58: stage1_output = (10);
59: stage1_output = (5);
60: stage1_output = (14);
61: stage1_output = (2);
62: stage1_output = (7);
63: stage1_output = (12);
endcase
 
end
 
endmodule
/systemcdes/trunk/rtl/verilog/s4.v
0,0 → 1,135
//////////////////////////////////////////////////////////////////////
//// ////
//// SBOX 4 ////
//// ////
//// This file is part of the SystemC DES ////
//// ////
//// Description: ////
//// Sbox of DES algorithm ////
//// ////
//// Generated automatically using SystemC to Verilog translator ////
//// ////
//// To Do: ////
//// - done ////
//// ////
//// Author(s): ////
//// - Javier Castillo, jcastilo@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2004/07/05 17:31:17 jcastillo
// First import
//
 
 
module s4(stage1_input,stage1_output);
input [5:0] stage1_input;
output [3:0] stage1_output;
 
reg [3:0] stage1_output;
 
 
always @( stage1_input)
 
begin
 
case(stage1_input)
 
0: stage1_output = (7);
1: stage1_output = (13);
2: stage1_output = (13);
3: stage1_output = (8);
4: stage1_output = (14);
5: stage1_output = (11);
6: stage1_output = (3);
7: stage1_output = (5);
8: stage1_output = (0);
9: stage1_output = (6);
10: stage1_output = (6);
11: stage1_output = (15);
12: stage1_output = (9);
13: stage1_output = (0);
14: stage1_output = (10);
15: stage1_output = (3);
16: stage1_output = (1);
17: stage1_output = (4);
18: stage1_output = (2);
19: stage1_output = (7);
20: stage1_output = (8);
21: stage1_output = (2);
22: stage1_output = (5);
23: stage1_output = (12);
24: stage1_output = (11);
25: stage1_output = (1);
26: stage1_output = (12);
27: stage1_output = (10);
28: stage1_output = (4);
29: stage1_output = (14);
30: stage1_output = (15);
31: stage1_output = (9);
32: stage1_output = (10);
33: stage1_output = (3);
34: stage1_output = (6);
35: stage1_output = (15);
36: stage1_output = (9);
37: stage1_output = (0);
38: stage1_output = (0);
39: stage1_output = (6);
40: stage1_output = (12);
41: stage1_output = (10);
42: stage1_output = (11);
43: stage1_output = (1);
44: stage1_output = (7);
45: stage1_output = (13);
46: stage1_output = (13);
47: stage1_output = (8);
48: stage1_output = (15);
49: stage1_output = (9);
50: stage1_output = (1);
51: stage1_output = (4);
52: stage1_output = (3);
53: stage1_output = (5);
54: stage1_output = (14);
55: stage1_output = (11);
56: stage1_output = (5);
57: stage1_output = (12);
58: stage1_output = (2);
59: stage1_output = (7);
60: stage1_output = (8);
61: stage1_output = (2);
62: stage1_output = (4);
63: stage1_output = (14);
 
endcase
 
end
 
endmodule
/systemcdes/trunk/rtl/verilog/s5.v
0,0 → 1,136
//////////////////////////////////////////////////////////////////////
//// ////
//// SBOX 5 ////
//// ////
//// This file is part of the SystemC DES ////
//// ////
//// Description: ////
//// Sbox of DES algorithm ////
//// ////
//// Generated automatically using SystemC to Verilog translator ////
//// ////
//// To Do: ////
//// - done ////
//// ////
//// Author(s): ////
//// - Javier Castillo, jcastilo@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2004/07/05 17:31:17 jcastillo
// First import
//
 
 
module s5(stage1_input,stage1_output);
input [5:0] stage1_input;
output [3:0] stage1_output;
 
reg [3:0] stage1_output;
 
 
always @( stage1_input)
 
begin
 
case(stage1_input)
 
0: stage1_output = (2);
1: stage1_output = (14);
2: stage1_output = (12);
3: stage1_output = (11);
4: stage1_output = (4);
5: stage1_output = (2);
6: stage1_output = (1);
7: stage1_output = (12);
8: stage1_output = (7);
9: stage1_output = (4);
10: stage1_output = (10);
11: stage1_output = (7);
12: stage1_output = (11);
13: stage1_output = (13);
14: stage1_output = (6);
15: stage1_output = (1);
16: stage1_output = (8);
17: stage1_output = (5);
18: stage1_output = (5);
19: stage1_output = (0);
20: stage1_output = (3);
21: stage1_output = (15);
22: stage1_output = (15);
23: stage1_output = (10);
24: stage1_output = (13);
25: stage1_output = (3);
26: stage1_output = (0);
27: stage1_output = (9);
28: stage1_output = (14);
29: stage1_output = (8);
30: stage1_output = (9);
31: stage1_output = (6);
32: stage1_output = (4);
33: stage1_output = (11);
34: stage1_output = (2);
35: stage1_output = (8);
36: stage1_output = (1);
37: stage1_output = (12);
38: stage1_output = (11);
39: stage1_output = (7);
40: stage1_output = (10);
41: stage1_output = (1);
42: stage1_output = (13);
43: stage1_output = (14);
44: stage1_output = (7);
45: stage1_output = (2);
46: stage1_output = (8);
47: stage1_output = (13);
48: stage1_output = (15);
49: stage1_output = (6);
50: stage1_output = (9);
51: stage1_output = (15);
52: stage1_output = (12);
53: stage1_output = (0);
54: stage1_output = (5);
55: stage1_output = (9);
56: stage1_output = (6);
57: stage1_output = (10);
58: stage1_output = (3);
59: stage1_output = (4);
60: stage1_output = (0);
61: stage1_output = (5);
62: stage1_output = (14);
63: stage1_output = (3);
 
endcase
 
 
end
 
endmodule
/systemcdes/trunk/rtl/verilog/s6.v
0,0 → 1,136
//////////////////////////////////////////////////////////////////////
//// ////
//// SBOX 6 ////
//// ////
//// This file is part of the SystemC DES ////
//// ////
//// Description: ////
//// Sbox of DES algorithm ////
//// ////
//// Generated automatically using SystemC to Verilog translator ////
//// ////
//// To Do: ////
//// - done ////
//// ////
//// Author(s): ////
//// - Javier Castillo, jcastilo@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2004/07/05 17:31:17 jcastillo
// First import
//
 
 
module s6(stage1_input,stage1_output);
input [5:0] stage1_input;
output [3:0] stage1_output;
 
reg [3:0] stage1_output;
 
 
always @( stage1_input)
 
begin
 
case(stage1_input)
 
0: stage1_output = (12);
1: stage1_output = (10);
2: stage1_output = (1);
3: stage1_output = (15);
4: stage1_output = (10);
5: stage1_output = (4);
6: stage1_output = (15);
7: stage1_output = (2);
8: stage1_output = (9);
9: stage1_output = (7);
10: stage1_output = (2);
11: stage1_output = (12);
12: stage1_output = (6);
13: stage1_output = (9);
14: stage1_output = (8);
15: stage1_output = (5);
16: stage1_output = (0);
17: stage1_output = (6);
18: stage1_output = (13);
19: stage1_output = (1);
20: stage1_output = (3);
21: stage1_output = (13);
22: stage1_output = (4);
23: stage1_output = (14);
24: stage1_output = (14);
25: stage1_output = (0);
26: stage1_output = (7);
27: stage1_output = (11);
28: stage1_output = (5);
29: stage1_output = (3);
30: stage1_output = (11);
31: stage1_output = (8);
32: stage1_output = (9);
33: stage1_output = (4);
34: stage1_output = (14);
35: stage1_output = (3);
36: stage1_output = (15);
37: stage1_output = (2);
38: stage1_output = (5);
39: stage1_output = (12);
40: stage1_output = (2);
41: stage1_output = (9);
42: stage1_output = (8);
43: stage1_output = (5);
44: stage1_output = (12);
45: stage1_output = (15);
46: stage1_output = (3);
47: stage1_output = (10);
48: stage1_output = (7);
49: stage1_output = (11);
50: stage1_output = (0);
51: stage1_output = (14);
52: stage1_output = (4);
53: stage1_output = (1);
54: stage1_output = (10);
55: stage1_output = (7);
56: stage1_output = (1);
57: stage1_output = (6);
58: stage1_output = (13);
59: stage1_output = (0);
60: stage1_output = (11);
61: stage1_output = (8);
62: stage1_output = (6);
63: stage1_output = (13);
 
endcase
 
end
 
endmodule
/systemcdes/trunk/rtl/verilog/s7.v
0,0 → 1,135
//////////////////////////////////////////////////////////////////////
//// ////
//// SBOX 7 ////
//// ////
//// This file is part of the SystemC DES ////
//// ////
//// Description: ////
//// Sbox of DES algorithm ////
//// ////
//// Generated automatically using SystemC to Verilog translator ////
//// ////
//// To Do: ////
//// - done ////
//// ////
//// Author(s): ////
//// - Javier Castillo, jcastilo@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2004/07/05 17:31:17 jcastillo
// First import
//
 
module s7(stage1_input,stage1_output);
input [5:0] stage1_input;
output [3:0] stage1_output;
 
reg [3:0] stage1_output;
 
 
always @( stage1_input)
 
begin
 
case(stage1_input)
 
0: stage1_output = (4);
1: stage1_output = (13);
2: stage1_output = (11);
3: stage1_output = (0);
4: stage1_output = (2);
5: stage1_output = (11);
6: stage1_output = (14);
7: stage1_output = (7);
8: stage1_output = (15);
9: stage1_output = (4);
10: stage1_output = (0);
11: stage1_output = (9);
12: stage1_output = (8);
13: stage1_output = (1);
14: stage1_output = (13);
15: stage1_output = (10);
16: stage1_output = (3);
17: stage1_output = (14);
18: stage1_output = (12);
19: stage1_output = (3);
20: stage1_output = (9);
21: stage1_output = (5);
22: stage1_output = (7);
23: stage1_output = (12);
24: stage1_output = (5);
25: stage1_output = (2);
26: stage1_output = (10);
27: stage1_output = (15);
28: stage1_output = (6);
29: stage1_output = (8);
30: stage1_output = (1);
31: stage1_output = (6);
32: stage1_output = (1);
33: stage1_output = (6);
34: stage1_output = (4);
35: stage1_output = (11);
36: stage1_output = (11);
37: stage1_output = (13);
38: stage1_output = (13);
39: stage1_output = (8);
40: stage1_output = (12);
41: stage1_output = (1);
42: stage1_output = (3);
43: stage1_output = (4);
44: stage1_output = (7);
45: stage1_output = (10);
46: stage1_output = (14);
47: stage1_output = (7);
48: stage1_output = (10);
49: stage1_output = (9);
50: stage1_output = (15);
51: stage1_output = (5);
52: stage1_output = (6);
53: stage1_output = (0);
54: stage1_output = (8);
55: stage1_output = (15);
56: stage1_output = (0);
57: stage1_output = (14);
58: stage1_output = (5);
59: stage1_output = (2);
60: stage1_output = (9);
61: stage1_output = (3);
62: stage1_output = (2);
63: stage1_output = (12);
 
endcase
 
 
end
 
endmodule
/systemcdes/trunk/rtl/verilog/s8.v
0,0 → 1,135
//////////////////////////////////////////////////////////////////////
//// ////
//// SBOX 8 ////
//// ////
//// This file is part of the SystemC DES ////
//// ////
//// Description: ////
//// Sbox of DES algorithm ////
//// ////
//// Generated automatically using SystemC to Verilog translator ////
//// ////
//// To Do: ////
//// - done ////
//// ////
//// Author(s): ////
//// - Javier Castillo, jcastilo@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2004/07/05 17:31:17 jcastillo
// First import
//
 
module s8(stage1_input,stage1_output);
input [5:0] stage1_input;
output [3:0] stage1_output;
 
reg [3:0] stage1_output;
 
 
always @(stage1_input)
 
begin
 
case(stage1_input)
 
0: stage1_output = (13);
1: stage1_output = (1);
2: stage1_output = (2);
3: stage1_output = (15);
4: stage1_output = (8);
5: stage1_output = (13);
6: stage1_output = (4);
7: stage1_output = (8);
8: stage1_output = (6);
9: stage1_output = (10);
10: stage1_output = (15);
11: stage1_output = (3);
12: stage1_output = (11);
13: stage1_output = (7);
14: stage1_output = (1);
15: stage1_output = (4);
16: stage1_output = (10);
17: stage1_output = (12);
18: stage1_output = (9);
19: stage1_output = (5);
20: stage1_output = (3);
21: stage1_output = (6);
22: stage1_output = (14);
23: stage1_output = (11);
24: stage1_output = (5);
25: stage1_output = (0);
26: stage1_output = (0);
27: stage1_output = (14);
28: stage1_output = (12);
29: stage1_output = (9);
30: stage1_output = (7);
31: stage1_output = (2);
32: stage1_output = (7);
33: stage1_output = (2);
34: stage1_output = (11);
35: stage1_output = (1);
36: stage1_output = (4);
37: stage1_output = (14);
38: stage1_output = (1);
39: stage1_output = (7);
40: stage1_output = (9);
41: stage1_output = (4);
42: stage1_output = (12);
43: stage1_output = (10);
44: stage1_output = (14);
45: stage1_output = (8);
46: stage1_output = (2);
47: stage1_output = (13);
48: stage1_output = (0);
49: stage1_output = (15);
50: stage1_output = (6);
51: stage1_output = (12);
52: stage1_output = (10);
53: stage1_output = (9);
54: stage1_output = (13);
55: stage1_output = (0);
56: stage1_output = (15);
57: stage1_output = (3);
58: stage1_output = (3);
59: stage1_output = (5);
60: stage1_output = (5);
61: stage1_output = (6);
62: stage1_output = (8);
63: stage1_output = (11);
 
endcase
 
 
end
 
endmodule
/systemcdes/trunk/rtl/systemc/key_gen.cpp
0,0 → 1,213
//////////////////////////////////////////////////////////////////////
//// ////
//// Key generation module implementation ////
//// ////
//// This file is part of the SystemC DES ////
//// ////
//// Description: ////
//// Generate a key from the previous one ////
//// ////
//// To Do: ////
//// - nothing ////
//// ////
//// Author(s): ////
//// - Javier Castillo, jcastilo@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2004/08/30 16:55:54 jcastillo
// Used indent command on C code
//
// Revision 1.1.1.1 2004/07/05 17:31:17 jcastillo
// First import
//
 
#include "key_gen.h"
 
void
key_gen::generate_key ()
{
 
bool prev0, prev1;
 
 
sc_uint < 56 > prev_key_var, non_perm_key_var;
sc_uint < 48 > new_key_var;
sc_uint < 28 > semi_key;
 
prev_key_var = previous_key.read ();
new_key_var = 0;
new_key.write (0);
non_perm_key_var = 0;
non_perm_key.write (0);
 
if (!decrypt.read ())
{
//Rotate left
switch (iteration.read ())
{
case 0:
case 1:
case 8:
case 15:
semi_key = prev_key_var.range (55, 28);
prev0 = semi_key[27];
semi_key = semi_key << 1;
semi_key[0] = prev0;
non_perm_key_var.range (55, 28) = semi_key;
semi_key = prev_key_var.range (27, 0);
prev0 = semi_key[27];
semi_key = semi_key << 1;
semi_key[0] = prev0;
non_perm_key_var.range (27, 0) = semi_key;
break;
default:
semi_key = prev_key_var.range (55, 28);
prev0 = semi_key[27];
prev1 = semi_key[26];
semi_key = semi_key << 2;
semi_key[1] = prev0;
semi_key[0] = prev1;
non_perm_key_var.range (55, 28) = semi_key;
semi_key = prev_key_var.range (27, 0);
prev0 = semi_key[27];
prev1 = semi_key[26];
semi_key = semi_key << 2;
semi_key[1] = prev0;
semi_key[0] = prev1;
non_perm_key_var.range (27, 0) = semi_key;
}
}
else
{
//Rotate rigth
switch (iteration.read ())
{
case 0:
semi_key = prev_key_var.range (55, 28);
non_perm_key_var.range (55, 28) = semi_key;
semi_key = prev_key_var.range (27, 0);
non_perm_key_var.range (27, 0) = semi_key;
break;
case 1:
case 8:
case 15:
semi_key = prev_key_var.range (55, 28);
prev0 = semi_key[0];
semi_key = semi_key >> 1;
semi_key[27] = prev0;
non_perm_key_var.range (55, 28) = semi_key;
semi_key = prev_key_var.range (27, 0);
prev0 = semi_key[0];
semi_key = semi_key >> 1;
semi_key[27] = prev0;
non_perm_key_var.range (27, 0) = semi_key;
break;
default:
semi_key = prev_key_var.range (55, 28);
prev0 = semi_key[0];
prev1 = semi_key[1];
semi_key = semi_key >> 2;
semi_key[26] = prev0;
semi_key[27] = prev1;
non_perm_key_var.range (55, 28) = semi_key;
semi_key = prev_key_var.range (27, 0);
prev0 = semi_key[0];
prev1 = semi_key[1];
semi_key = semi_key >> 2;
semi_key[26] = prev0;
semi_key[27] = prev1;
non_perm_key_var.range (27, 0) = semi_key;
}
}
 
non_perm_key.write (non_perm_key_var);
 
//Apply PC_2 permutation
//Expand the data
new_key_var[47] = non_perm_key_var[42];
new_key_var[46] = non_perm_key_var[39];
new_key_var[45] = non_perm_key_var[45];
new_key_var[44] = non_perm_key_var[32];
new_key_var[43] = non_perm_key_var[55];
new_key_var[42] = non_perm_key_var[51];
new_key_var[41] = non_perm_key_var[53];
new_key_var[40] = non_perm_key_var[28];
 
new_key_var[39] = non_perm_key_var[41];
new_key_var[38] = non_perm_key_var[50];
new_key_var[37] = non_perm_key_var[35];
new_key_var[36] = non_perm_key_var[46];
new_key_var[35] = non_perm_key_var[33];
new_key_var[34] = non_perm_key_var[37];
new_key_var[33] = non_perm_key_var[44];
new_key_var[32] = non_perm_key_var[52];
 
new_key_var[31] = non_perm_key_var[30];
new_key_var[30] = non_perm_key_var[48];
new_key_var[29] = non_perm_key_var[40];
new_key_var[28] = non_perm_key_var[49];
new_key_var[27] = non_perm_key_var[29];
new_key_var[26] = non_perm_key_var[36];
new_key_var[25] = non_perm_key_var[43];
new_key_var[24] = non_perm_key_var[54];
 
new_key_var[23] = non_perm_key_var[15];
new_key_var[22] = non_perm_key_var[4];
new_key_var[21] = non_perm_key_var[25];
new_key_var[20] = non_perm_key_var[19];
new_key_var[19] = non_perm_key_var[9];
new_key_var[18] = non_perm_key_var[1];
new_key_var[17] = non_perm_key_var[26];
new_key_var[16] = non_perm_key_var[16];
 
new_key_var[15] = non_perm_key_var[5];
new_key_var[14] = non_perm_key_var[11];
new_key_var[13] = non_perm_key_var[23];
new_key_var[12] = non_perm_key_var[8];
new_key_var[11] = non_perm_key_var[12];
new_key_var[10] = non_perm_key_var[7];
new_key_var[9] = non_perm_key_var[17];
new_key_var[8] = non_perm_key_var[0];
 
new_key_var[7] = non_perm_key_var[22];
new_key_var[6] = non_perm_key_var[3];
new_key_var[5] = non_perm_key_var[10];
new_key_var[4] = non_perm_key_var[14];
new_key_var[3] = non_perm_key_var[6];
new_key_var[2] = non_perm_key_var[20];
new_key_var[1] = non_perm_key_var[27];
new_key_var[0] = non_perm_key_var[24];
 
new_key.write (new_key_var);
 
 
}
/systemcdes/trunk/rtl/systemc/desmodel.h
0,0 → 1,122
//////////////////////////////////////////////////////////////////////
//// ////
//// DES C behavioral model ////
//// ////
//// This file is part of the SystemC DES ////
//// ////
//// Description: ////
//// C behavioral model used as golden model ////
//// ////
//// To Do: ////
//// - done ////
//// ////
//// Author(s): ////
//// - Javier Castillo, jcastilo@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2004/07/05 17:31:18 jcastillo
// First import
//
 
#include "systemc.h"
 
void decrypt_des (unsigned char *block, unsigned char *block_o,
unsigned char *key);
void encrypt_des (unsigned char *block, unsigned char *block_o,
unsigned char *key);
 
SC_MODULE (desmodel)
{
 
sc_fifo_in < bool > decrypt;
sc_fifo_in < sc_uint < 64 > >des_key_i;
sc_fifo_in < sc_uint < 64 > >des_data_i;
 
sc_fifo_out < sc_uint < 64 > >des_data_o;
 
void des_thread ()
{
unsigned char des_key[8], des_data[8], des_out[8];
sc_uint < 64 > des_key_i_var, des_data_i_var, des_data_o_var;
 
while (1)
{
 
des_data_i_var = des_data_i.read ();
des_key_i_var = des_key_i.read ();
 
//Convert a sc_uint<64> to an array of 8 char
des_key[0] = des_key_i_var.range (63, 56);
des_key[1] = des_key_i_var.range (55, 48);
des_key[2] = des_key_i_var.range (47, 40);
des_key[3] = des_key_i_var.range (39, 32);
des_key[4] = des_key_i_var.range (31, 24);
des_key[5] = des_key_i_var.range (23, 16);
des_key[6] = des_key_i_var.range (15, 8);
des_key[7] = des_key_i_var.range (7, 0);
 
des_data[0] = des_data_i_var.range (63, 56);
des_data[1] = des_data_i_var.range (55, 48);
des_data[2] = des_data_i_var.range (47, 40);
des_data[3] = des_data_i_var.range (39, 32);
des_data[4] = des_data_i_var.range (31, 24);
des_data[5] = des_data_i_var.range (23, 16);
des_data[6] = des_data_i_var.range (15, 8);
des_data[7] = des_data_i_var.range (7, 0);
 
if (!decrypt.read ())
encrypt_des (des_data, des_out, des_key);
else
decrypt_des (des_data, des_out, des_key);
 
des_data_o_var.range (63, 56) = des_out[0];
des_data_o_var.range (55, 48) = des_out[1];
des_data_o_var.range (47, 40) = des_out[2];
des_data_o_var.range (39, 32) = des_out[3];
des_data_o_var.range (31, 24) = des_out[4];
des_data_o_var.range (23, 16) = des_out[5];
des_data_o_var.range (15, 8) = des_out[6];
des_data_o_var.range (7, 0) = des_out[7];
 
des_data_o.write (des_data_o_var);
}
}
 
 
 
SC_CTOR (desmodel)
{
 
SC_THREAD (des_thread);
 
}
};
/systemcdes/trunk/rtl/systemc/des.cpp
0,0 → 1,349
//////////////////////////////////////////////////////////////////////
//// ////
//// DES algorithm implementation ////
//// ////
//// This file is part of the SystemC DES ////
//// ////
//// Description: ////
//// Top file for DES algorithm ////
//// ////
//// To Do: ////
//// - nothing ////
//// ////
//// Author(s): ////
//// - Javier Castillo, jcastilo@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2004/07/05 17:31:17 jcastillo
// First import
//
 
#include "des.h"
 
void
des::reg_signal ()
{
if (!reset)
{
ready_o.write (0);
data_o.write (0);
stage1_iter.write (0);
data_ready.write (1);
}
else
{
ready_o.write (next_ready_o.read ());
data_o.write (next_data_o.read ());
stage1_iter.write (next_stage1_iter.read ());
data_ready.write (next_data_ready.read ());
}
 
}
 
void
des::des_proc ()
{
 
sc_uint < 32 > L_i_var, R_i_var;
sc_uint < 64 > data_i_var, data_o_var, data_o_var_t, key_i_var;
sc_uint < 56 > key_var_perm;
 
L_i_var = 0;
R_i_var = 0;
data_i_var = 0;
 
next_ready_o.write (0);
next_data_ready.write (data_ready.read ());
next_stage1_iter.write (stage1_iter.read ());
 
stage1_L_i.write (0);
stage1_R_i.write (0);
stage1_round_key_i.write (0);
 
//The permutations are always performed => less resources needed
 
key_i_var = key_i.read ();
 
key_var_perm[55] = key_i_var[7];
key_var_perm[54] = key_i_var[15];
key_var_perm[53] = key_i_var[23];
key_var_perm[52] = key_i_var[31];
key_var_perm[51] = key_i_var[39];
key_var_perm[50] = key_i_var[47];
key_var_perm[49] = key_i_var[55];
key_var_perm[48] = key_i_var[63];
 
key_var_perm[47] = key_i_var[6];
key_var_perm[46] = key_i_var[14];
key_var_perm[45] = key_i_var[22];
key_var_perm[44] = key_i_var[30];
key_var_perm[43] = key_i_var[38];
key_var_perm[42] = key_i_var[46];
key_var_perm[41] = key_i_var[54];
key_var_perm[40] = key_i_var[62];
 
key_var_perm[39] = key_i_var[5];
key_var_perm[38] = key_i_var[13];
key_var_perm[37] = key_i_var[21];
key_var_perm[36] = key_i_var[29];
key_var_perm[35] = key_i_var[37];
key_var_perm[34] = key_i_var[45];
key_var_perm[33] = key_i_var[53];
key_var_perm[32] = key_i_var[61];
 
key_var_perm[31] = key_i_var[4];
key_var_perm[30] = key_i_var[12];
key_var_perm[29] = key_i_var[20];
key_var_perm[28] = key_i_var[28];
key_var_perm[27] = key_i_var[1];
key_var_perm[26] = key_i_var[9];
key_var_perm[25] = key_i_var[17];
key_var_perm[24] = key_i_var[25];
 
key_var_perm[23] = key_i_var[33];
key_var_perm[22] = key_i_var[41];
key_var_perm[21] = key_i_var[49];
key_var_perm[20] = key_i_var[57];
key_var_perm[19] = key_i_var[2];
key_var_perm[18] = key_i_var[10];
key_var_perm[17] = key_i_var[18];
key_var_perm[16] = key_i_var[26];
 
key_var_perm[15] = key_i_var[34];
key_var_perm[14] = key_i_var[42];
key_var_perm[13] = key_i_var[50];
key_var_perm[12] = key_i_var[58];
key_var_perm[11] = key_i_var[3];
key_var_perm[10] = key_i_var[11];
key_var_perm[9] = key_i_var[19];
key_var_perm[8] = key_i_var[27];
 
key_var_perm[7] = key_i_var[35];
key_var_perm[6] = key_i_var[43];
key_var_perm[5] = key_i_var[51];
key_var_perm[4] = key_i_var[59];
key_var_perm[3] = key_i_var[36];
key_var_perm[2] = key_i_var[44];
key_var_perm[1] = key_i_var[52];
key_var_perm[0] = key_i_var[60];
 
 
//Apply data to round module with the IP
data_i_var = data_i.read ();
L_i_var[31] = data_i_var[6];
L_i_var[30] = data_i_var[14];
L_i_var[29] = data_i_var[22];
L_i_var[28] = data_i_var[30];
L_i_var[27] = data_i_var[38];
L_i_var[26] = data_i_var[46];
L_i_var[25] = data_i_var[54];
L_i_var[24] = data_i_var[62];
 
L_i_var[23] = data_i_var[4];
L_i_var[22] = data_i_var[12];
L_i_var[21] = data_i_var[20];
L_i_var[20] = data_i_var[28];
L_i_var[19] = data_i_var[36];
L_i_var[18] = data_i_var[44];
L_i_var[17] = data_i_var[52];
L_i_var[16] = data_i_var[60];
 
L_i_var[15] = data_i_var[2];
L_i_var[14] = data_i_var[10];
L_i_var[13] = data_i_var[18];
L_i_var[12] = data_i_var[26];
L_i_var[11] = data_i_var[34];
L_i_var[10] = data_i_var[42];
L_i_var[9] = data_i_var[50];
L_i_var[8] = data_i_var[58];
 
L_i_var[7] = data_i_var[0];
L_i_var[6] = data_i_var[8];
L_i_var[5] = data_i_var[16];
L_i_var[4] = data_i_var[24];
L_i_var[3] = data_i_var[32];
L_i_var[2] = data_i_var[40];
L_i_var[1] = data_i_var[48];
L_i_var[0] = data_i_var[56];
 
R_i_var[31] = data_i_var[7];
R_i_var[30] = data_i_var[15];
R_i_var[29] = data_i_var[23];
R_i_var[28] = data_i_var[31];
R_i_var[27] = data_i_var[39];
R_i_var[26] = data_i_var[47];
R_i_var[25] = data_i_var[55];
R_i_var[24] = data_i_var[63];
 
R_i_var[23] = data_i_var[5];
R_i_var[22] = data_i_var[13];
R_i_var[21] = data_i_var[21];
R_i_var[20] = data_i_var[29];
R_i_var[19] = data_i_var[37];
R_i_var[18] = data_i_var[45];
R_i_var[17] = data_i_var[53];
R_i_var[16] = data_i_var[61];
 
R_i_var[15] = data_i_var[3];
R_i_var[14] = data_i_var[11];
R_i_var[13] = data_i_var[19];
R_i_var[12] = data_i_var[27];
R_i_var[11] = data_i_var[35];
R_i_var[10] = data_i_var[43];
R_i_var[9] = data_i_var[51];
R_i_var[8] = data_i_var[59];
 
R_i_var[7] = data_i_var[1];
R_i_var[6] = data_i_var[9];
R_i_var[5] = data_i_var[17];
R_i_var[4] = data_i_var[25];
R_i_var[3] = data_i_var[33];
R_i_var[2] = data_i_var[41];
R_i_var[1] = data_i_var[49];
R_i_var[0] = data_i_var[57];
 
//IP-1 Permutation
 
data_o_var_t.range (63, 32) = stage1_R_o.read ();
data_o_var_t.range (31, 0) = stage1_L_o.read ();
 
data_o_var[63] = data_o_var_t[24];
data_o_var[62] = data_o_var_t[56];
data_o_var[61] = data_o_var_t[16];
data_o_var[60] = data_o_var_t[48];
data_o_var[59] = data_o_var_t[8];
data_o_var[58] = data_o_var_t[40];
data_o_var[57] = data_o_var_t[0];
data_o_var[56] = data_o_var_t[32];
 
data_o_var[55] = data_o_var_t[25];
data_o_var[54] = data_o_var_t[57];
data_o_var[53] = data_o_var_t[17];
data_o_var[52] = data_o_var_t[49];
data_o_var[51] = data_o_var_t[9];
data_o_var[50] = data_o_var_t[41];
data_o_var[49] = data_o_var_t[1];
data_o_var[48] = data_o_var_t[33];
 
data_o_var[47] = data_o_var_t[26];
data_o_var[46] = data_o_var_t[58];
data_o_var[45] = data_o_var_t[18];
data_o_var[44] = data_o_var_t[50];
data_o_var[43] = data_o_var_t[10];
data_o_var[42] = data_o_var_t[42];
data_o_var[41] = data_o_var_t[2];
data_o_var[40] = data_o_var_t[34];
 
data_o_var[39] = data_o_var_t[27];
data_o_var[38] = data_o_var_t[59];
data_o_var[37] = data_o_var_t[19];
data_o_var[36] = data_o_var_t[51];
data_o_var[35] = data_o_var_t[11];
data_o_var[34] = data_o_var_t[43];
data_o_var[33] = data_o_var_t[3];
data_o_var[32] = data_o_var_t[35];
 
data_o_var[31] = data_o_var_t[28];
data_o_var[30] = data_o_var_t[60];
data_o_var[29] = data_o_var_t[20];
data_o_var[28] = data_o_var_t[52];
data_o_var[27] = data_o_var_t[12];
data_o_var[26] = data_o_var_t[44];
data_o_var[25] = data_o_var_t[4];
data_o_var[24] = data_o_var_t[36];
 
data_o_var[23] = data_o_var_t[29];
data_o_var[22] = data_o_var_t[61];
data_o_var[21] = data_o_var_t[21];
data_o_var[20] = data_o_var_t[53];
data_o_var[19] = data_o_var_t[13];
data_o_var[18] = data_o_var_t[45];
data_o_var[17] = data_o_var_t[5];
data_o_var[16] = data_o_var_t[37];
 
data_o_var[15] = data_o_var_t[30];
data_o_var[14] = data_o_var_t[62];
data_o_var[13] = data_o_var_t[22];
data_o_var[12] = data_o_var_t[54];
data_o_var[11] = data_o_var_t[14];
data_o_var[10] = data_o_var_t[46];
data_o_var[9] = data_o_var_t[6];
data_o_var[8] = data_o_var_t[38];
 
data_o_var[7] = data_o_var_t[31];
data_o_var[6] = data_o_var_t[63];
data_o_var[5] = data_o_var_t[23];
data_o_var[4] = data_o_var_t[55];
data_o_var[3] = data_o_var_t[15];
data_o_var[2] = data_o_var_t[47];
data_o_var[1] = data_o_var_t[7];
data_o_var[0] = data_o_var_t[39];
 
//Assign data output
next_data_o.write (data_o_var);
 
//FSM to control the round datapath
stage1_iteration_i.write (stage1_iter.read ());
 
next_ready_o.write (0);
stage1_L_i.write (stage1_L_o.read ());
stage1_R_i.write (stage1_R_o.read ());
stage1_round_key_i.write (stage1_round_key_o.read ());
 
switch (stage1_iter.read ())
{
case 0:
if (load_i.read ())
{
next_stage1_iter.write (1);
stage1_L_i.write (L_i_var);
stage1_R_i.write (R_i_var);
stage1_round_key_i.write (key_var_perm);
next_data_ready.write (0);
}
else if (!data_ready.read ())
{
next_stage1_iter.write (0);
//Can accept data
next_ready_o.write (1);
next_data_ready.write (1);
}
break;
case 15:
next_stage1_iter.write (0);
break;
default:
next_stage1_iter.write (stage1_iter.read () + 1);
break;
}
 
}
/systemcdes/trunk/rtl/systemc/main.cpp
0,0 → 1,138
//////////////////////////////////////////////////////////////////////
//// ////
//// Main simulation file ////
//// ////
//// This file is part of the SystemC DES ////
//// ////
//// Description: ////
//// Simulation file for DES project ////
//// ////
//// To Do: ////
//// - nothing ////
//// ////
//// Author(s): ////
//// - Javier Castillo, jcastilo@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2004/07/05 17:31:18 jcastillo
// First import
//
 
 
#include "systemc.h"
#include "iostream.h"
#include "des.h"
#include "desfunctions.h"
#include "desmodel.h"
#include "stimulus.h"
#include "adapt.h"
#include "checker.h"
 
int
sc_main (int argc, char *argv[])
{
 
sc_clock clk ("clk", 20);
 
test *t;
des_transactor *tr;
des *de1;
desmodel *dm1;
adapter *ad1;
checker *ch1;
 
t = new test ("testbench");
tr = new des_transactor ("des_transactor");
dm1 = new desmodel ("des_C_model");
de1 = new des ("des");
ad1 = new adapter ("adapter");
ch1 = new checker ("checker");
 
t->transactor (*tr);
 
sc_signal < bool > reset;
sc_signal < bool > rt_load;
sc_signal < bool > rt_decrypt;
sc_signal < sc_uint < 64 > >rt_data_i;
sc_signal < sc_uint < 64 > >rt_key;
 
sc_signal < sc_uint < 64 > >rt_data_o;
sc_signal < bool > rt_ready;
 
sc_fifo < sc_uint < 64 > >rt_des_data_ck;
sc_fifo < sc_uint < 64 > >c_des_data_ck;
 
sc_fifo < bool > c_decrypt;
sc_fifo < sc_uint < 64 > >c_key;
sc_fifo < sc_uint < 64 > >c_data;
 
ch1->reset (reset);
ch1->rt_des_data_i (rt_des_data_ck);
ch1->c_des_data_i (c_des_data_ck);
 
ad1->clk (clk);
ad1->rt_ready_i (rt_ready);
ad1->rt_des_data_i (rt_data_o);
ad1->rt_des_data_o (rt_des_data_ck);
 
dm1->decrypt (c_decrypt);
dm1->des_key_i (c_key);
dm1->des_data_i (c_data);
dm1->des_data_o (c_des_data_ck);
 
de1->clk (clk);
de1->reset (reset);
de1->load_i (rt_load);
de1->decrypt_i (rt_decrypt);
de1->data_i (rt_data_i);
de1->key_i (rt_key);
de1->data_o (rt_data_o);
de1->ready_o (rt_ready);
 
tr->clk (clk);
tr->reset (reset);
//Ports to RT model
tr->rt_load_o (rt_load);
tr->rt_decrypt_o (rt_decrypt);
tr->rt_des_data_o (rt_data_i);
tr->rt_des_key_o (rt_key);
tr->rt_des_ready_i (rt_ready);
//Ports to C model
tr->c_decrypt_o (c_decrypt);
tr->c_des_key_o (c_key);
tr->c_des_data_o (c_data);
 
sc_start (-1);
 
return 0;
 
}
/systemcdes/trunk/rtl/systemc/transactor.h
0,0 → 1,162
//////////////////////////////////////////////////////////////////////
//// ////
//// Transactor for AES ramdom verification ////
//// ////
//// This file is part of the SystemC DES ////
//// ////
//// Description: ////
//// Transactor acording to TLM for SystemC DES project ////
//// ////
//// To Do: ////
//// - nothing ////
//// ////
//// Author(s): ////
//// - Javier Castillo, jcastilo@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2004/07/05 17:31:18 jcastillo
// First import
//
 
#include "systemc.h"
 
class transactor_ports:public sc_module
{
public:
 
// Ports
sc_in < bool > clk;
sc_out < bool > reset;
 
//Ports to RT model
sc_out < bool > rt_load_o;
sc_out < bool > rt_decrypt_o;
sc_out < sc_uint < 64 > >rt_des_data_o;
sc_out < sc_uint < 64 > >rt_des_key_o;
sc_in < bool > rt_des_ready_i;
 
//Ports to C model
sc_fifo_out < bool > c_decrypt_o;
sc_fifo_out < sc_uint < 64 > >c_des_key_o;
sc_fifo_out < sc_uint < 64 > >c_des_data_o;
 
};
 
 
class rw_task_if:virtual public sc_interface
{
 
public:
//Funciones para el transactor
virtual void resetea (void) = 0;
virtual void encrypt (sc_uint < 64 > data, sc_uint < 64 > key) = 0;
virtual void decrypt (sc_uint < 64 > data, sc_uint < 64 > key) = 0;
virtual void wait_cycles (int cycles) = 0;
 
};
 
 
//Transactor
class des_transactor:public rw_task_if, public transactor_ports
{
 
public:
 
SC_CTOR (des_transactor)
{
 
cout.unsetf (ios::dec);
cout.setf (ios::hex);
 
}
 
 
void resetea (void)
{
reset.write (0);
wait (clk->posedge_event ());
reset.write (1);
cout << "Reseted" << endl;
}
 
void encrypt (sc_uint < 64 > data, sc_uint < 64 > key)
{
 
wait (clk->posedge_event ());
 
//To RT model
rt_load_o.write (1);
rt_des_data_o.write (data);
rt_des_key_o.write (key);
rt_decrypt_o.write (0);
 
//To C model through fifos
c_des_data_o.write (data);
c_des_key_o.write (key);
c_decrypt_o.write (0);
 
wait (clk->posedge_event ());
rt_load_o.write (0);
wait (rt_des_ready_i->posedge_event ());
}
 
void decrypt (sc_uint < 64 > data, sc_uint < 64 > key)
{
 
wait (clk->posedge_event ());
 
//To RT model
rt_load_o.write (1);
rt_des_data_o.write (data);
rt_des_key_o.write (key);
rt_decrypt_o.write (1);
 
//To C model through fifos
c_des_data_o.write (data);
c_des_key_o.write (key);
c_decrypt_o.write (1);
 
wait (clk->posedge_event ());
rt_load_o.write (0);
wait (rt_des_ready_i->posedge_event ());
 
}
 
void wait_cycles (int cycles)
{
for (int i = 0; i < cycles; i++)
{
wait (clk->posedge_event ());
}
}
 
};
/systemcdes/trunk/rtl/systemc/key_gen.h
0,0 → 1,68
//////////////////////////////////////////////////////////////////////
//// ////
//// Key generation module header ////
//// ////
//// This file is part of the SystemC DES ////
//// ////
//// Description: ////
//// Generate a key from the previous one ////
//// ////
//// To Do: ////
//// - nothing ////
//// ////
//// Author(s): ////
//// - Javier Castillo, jcastilo@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2004/07/05 17:31:17 jcastillo
// First import
//
 
#include "systemc.h"
 
SC_MODULE (key_gen)
{
 
sc_in < sc_uint < 56 > >previous_key;
sc_in < sc_uint < 4 > >iteration;
sc_in < bool > decrypt; //When decrypting we rotate rigth instead of left
sc_out < sc_uint < 56 > >non_perm_key;
sc_out < sc_uint < 48 > >new_key;
 
void generate_key ();
 
SC_CTOR (key_gen)
{
SC_METHOD (generate_key);
sensitive << previous_key << iteration << decrypt;
}
};
/systemcdes/trunk/rtl/systemc/s1.h
0,0 → 1,67
//////////////////////////////////////////////////////////////////////
//// ////
//// SBOX 1 Header ////
//// ////
//// This file is part of the SystemC DES ////
//// ////
//// Description: ////
//// Sbox of DES algorithm ////
//// ////
//// To Do: ////
//// - done ////
//// ////
//// Author(s): ////
//// - Javier Castillo, jcastilo@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2004/07/05 17:31:17 jcastillo
// First import
//
 
#include "systemc.h"
 
 
SC_MODULE (s1)
{
 
sc_in < sc_uint < 6 > >stage1_input;
sc_out < sc_uint < 4 > >stage1_output;
 
void s1_box ();
 
SC_CTOR (s1)
{
 
SC_METHOD (s1_box);
sensitive << stage1_input;
}
};
/systemcdes/trunk/rtl/systemc/s2.h
0,0 → 1,67
//////////////////////////////////////////////////////////////////////
//// ////
//// SBOX 2 Header ////
//// ////
//// This file is part of the SystemC DES ////
//// ////
//// Description: ////
//// Sbox of DES algorithm ////
//// ////
//// To Do: ////
//// - done ////
//// ////
//// Author(s): ////
//// - Javier Castillo, jcastilo@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2004/07/05 17:31:17 jcastillo
// First import
//
 
#include "systemc.h"
 
SC_MODULE (s2)
{
 
sc_in < sc_uint < 6 > >stage1_input;
sc_out < sc_uint < 4 > >stage1_output;
 
void s2_box ();
 
SC_CTOR (s2)
{
 
SC_METHOD (s2_box);
sensitive << stage1_input;
 
}
};
/systemcdes/trunk/rtl/systemc/stimulus.h
0,0 → 1,83
//////////////////////////////////////////////////////////////////////
//// ////
//// Random testbench declation ////
//// ////
//// This file is part of the SystemC DES ////
//// ////
//// Description: ////
//// Declare ramdom testbench class and data ////
//// ////
//// To Do: ////
//// - done ////
//// ////
//// Author(s): ////
//// - Javier Castillo, jcastilo@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2004/07/05 17:31:18 jcastillo
// First import
//
 
 
 
#include "transactor.h"
#include "scv.h"
 
//Random number generator
 
class random_generator:virtual public scv_constraint_base
{
public:
 
scv_smart_ptr < sc_uint < 64 > >des_key;
scv_smart_ptr < sc_uint < 64 > >des_data;
 
scv_smart_ptr < bool > decrypt;
 
SCV_CONSTRAINT_CTOR (random_generator)
{
}
};
 
class test:public sc_module
{
public:
 
sc_port < rw_task_if > transactor;
 
void tb ();
 
SC_CTOR (test)
{
SC_THREAD (tb);
}
};
/systemcdes/trunk/rtl/systemc/s3.h
0,0 → 1,67
//////////////////////////////////////////////////////////////////////
//// ////
//// SBOX 3 Header ////
//// ////
//// This file is part of the SystemC DES ////
//// ////
//// Description: ////
//// Sbox of DES algorithm ////
//// ////
//// To Do: ////
//// - done ////
//// ////
//// Author(s): ////
//// - Javier Castillo, jcastilo@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2004/07/05 17:31:17 jcastillo
// First import
//
 
#include "systemc.h"
 
SC_MODULE (s3)
{
 
sc_in < sc_uint < 6 > >stage1_input;
sc_out < sc_uint < 4 > >stage1_output;
 
 
void s3_box ();
 
SC_CTOR (s3)
{
 
SC_METHOD (s3_box);
sensitive << stage1_input;
}
};
/systemcdes/trunk/rtl/systemc/s4.h
0,0 → 1,67
//////////////////////////////////////////////////////////////////////
//// ////
//// SBOX 4 Header ////
//// ////
//// This file is part of the SystemC DES ////
//// ////
//// Description: ////
//// Sbox of DES algorithm ////
//// ////
//// To Do: ////
//// - done ////
//// ////
//// Author(s): ////
//// - Javier Castillo, jcastilo@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2004/07/05 17:31:17 jcastillo
// First import
//
 
#include "systemc.h"
 
SC_MODULE (s4)
{
 
sc_in < sc_uint < 6 > >stage1_input;
sc_out < sc_uint < 4 > >stage1_output;
 
void s4_box ();
 
 
SC_CTOR (s4)
{
 
SC_METHOD (s4_box);
sensitive << stage1_input;
}
};
/systemcdes/trunk/rtl/systemc/s5.h
0,0 → 1,68
//////////////////////////////////////////////////////////////////////
//// ////
//// SBOX 5 Header ////
//// ////
//// This file is part of the SystemC DES ////
//// ////
//// Description: ////
//// Sbox of DES algorithm ////
//// ////
//// To Do: ////
//// - done ////
//// ////
//// Author(s): ////
//// - Javier Castillo, jcastilo@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2004/07/05 17:31:17 jcastillo
// First import
//
 
#include "systemc.h"
 
SC_MODULE (s5)
{
 
sc_in < sc_uint < 6 > >stage1_input;
sc_out < sc_uint < 4 > >stage1_output;
 
void s5_box ();
 
 
SC_CTOR (s5)
{
 
SC_METHOD (s5_box);
sensitive << stage1_input;
 
}
};
/systemcdes/trunk/rtl/systemc/round.h
0,0 → 1,110
//////////////////////////////////////////////////////////////////////
//// ////
//// Round of DES algorithm header ////
//// ////
//// This file is part of the SystemC DES ////
//// ////
//// Description: ////
//// This file perform a round of the DES algorithm ////
//// ////
//// To Do: ////
//// - nothing ////
//// ////
//// Author(s): ////
//// - Javier Castillo, jcastilo@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2004/07/05 17:31:17 jcastillo
// First import
//
 
#include "systemc.h"
 
#include "key_gen.h"
 
SC_MODULE (desround)
{
 
sc_in < bool > clk;
sc_in < bool > reset;
 
sc_in < sc_uint < 4 > >iteration_i;
sc_in < bool > decrypt_i;
sc_in < sc_uint < 32 > >R_i;
sc_in < sc_uint < 32 > >L_i;
sc_in < sc_uint < 56 > >Key_i;
 
sc_out < sc_uint < 32 > >R_o;
sc_out < sc_uint < 32 > >L_o;
sc_out < sc_uint < 56 > >Key_o;
 
sc_out < sc_uint < 6 > >s1_o, s2_o, s3_o, s4_o, s5_o, s6_o, s7_o, s8_o;
sc_in < sc_uint < 4 > >s1_i, s2_i, s3_i, s4_i, s5_i, s6_i, s7_i, s8_i;
 
void registers ();
void round_proc ();
 
sc_signal < sc_uint < 56 > >previous_key;
sc_signal < sc_uint < 4 > >iteration;
sc_signal < bool > decrypt; //When decrypting we rotate rigth instead of left
sc_signal < sc_uint < 56 > >non_perm_key;
sc_signal < sc_uint < 48 > >new_key;
 
sc_signal < sc_uint < 32 > >next_R;
 
sc_signal < sc_uint < 32 > >expanRSig;
 
//Round key generator
key_gen *kg1;
 
SC_CTOR (desround)
{
 
kg1 = new key_gen ("key_gen");
kg1->previous_key (previous_key);
kg1->iteration (iteration);
kg1->decrypt (decrypt);
kg1->new_key (new_key);
kg1->non_perm_key (non_perm_key);
 
SC_METHOD (registers);
sensitive_pos << clk;
sensitive_neg << reset;
 
SC_METHOD (round_proc);
sensitive << R_i << L_i << Key_i << iteration_i << decrypt_i;
sensitive << new_key << s1_i << s2_i << s3_i << s4_i << s5_i;
sensitive << s6_i << s7_i << s8_i;
 
 
}
};
/systemcdes/trunk/rtl/systemc/s6.h
0,0 → 1,67
//////////////////////////////////////////////////////////////////////
//// ////
//// SBOX 6 Header ////
//// ////
//// This file is part of the SystemC DES ////
//// ////
//// Description: ////
//// Sbox of DES algorithm ////
//// ////
//// To Do: ////
//// - done ////
//// ////
//// Author(s): ////
//// - Javier Castillo, jcastilo@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2004/07/05 17:31:17 jcastillo
// First import
//
 
#include "systemc.h"
 
SC_MODULE (s6)
{
 
sc_in < sc_uint < 6 > >stage1_input;
sc_out < sc_uint < 4 > >stage1_output;
 
void s6_box ();
 
SC_CTOR (s6)
{
 
SC_METHOD (s6_box);
sensitive << stage1_input;
 
}
};
/systemcdes/trunk/rtl/systemc/s7.h
0,0 → 1,67
//////////////////////////////////////////////////////////////////////
//// ////
//// SBOX 7 Header ////
//// ////
//// This file is part of the SystemC DES ////
//// ////
//// Description: ////
//// Sbox of DES algorithm ////
//// ////
//// To Do: ////
//// - done ////
//// ////
//// Author(s): ////
//// - Javier Castillo, jcastilo@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2004/07/05 17:31:17 jcastillo
// First import
//
 
#include "systemc.h"
 
SC_MODULE (s7)
{
 
sc_in < sc_uint < 6 > >stage1_input;
sc_out < sc_uint < 4 > >stage1_output;
 
void s7_box ();
 
 
SC_CTOR (s7)
{
 
SC_METHOD (s7_box);
sensitive << stage1_input;
}
};
/systemcdes/trunk/rtl/systemc/adapt.h
0,0 → 1,74
//////////////////////////////////////////////////////////////////////
//// ////
//// sc_fifo to sc_signal adapter ////
//// ////
//// This file is part of the SystemC DES ////
//// ////
//// To Do: ////
//// - done ////
//// ////
//// Author(s): ////
//// - Javier Castillo, jcastilo@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2004/07/05 17:31:18 jcastillo
// First import
//
 
#include "systemc.h"
 
SC_MODULE (adapter)
{
 
sc_in < bool > clk;
sc_in < bool > rt_ready_i;
sc_in < sc_uint < 64 > >rt_des_data_i;
 
sc_fifo_out < sc_uint < 64 > >rt_des_data_o;
 
void adapt ()
{
 
while (1)
{
wait (clk->posedge_event ());
if (rt_ready_i.read ())
rt_des_data_o.write (rt_des_data_i.read ());
}
 
}
 
SC_CTOR (adapter)
{
SC_THREAD (adapt);
}
};
/systemcdes/trunk/rtl/systemc/s8.h
0,0 → 1,68
//////////////////////////////////////////////////////////////////////
//// ////
//// SBOX 8 Header ////
//// ////
//// This file is part of the SystemC DES ////
//// ////
//// Description: ////
//// Sbox of DES algorithm ////
//// ////
//// To Do: ////
//// - done ////
//// ////
//// Author(s): ////
//// - Javier Castillo, jcastilo@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2004/07/05 17:31:17 jcastillo
// First import
//
 
#include "systemc.h"
 
SC_MODULE (s8)
{
 
sc_in < sc_uint < 6 > >stage1_input;
sc_out < sc_uint < 4 > >stage1_output;
 
void s8_box ();
 
 
SC_CTOR (s8)
{
 
SC_METHOD (s8_box);
sensitive << stage1_input;
 
}
};
/systemcdes/trunk/rtl/systemc/desfunctions.h
0,0 → 1,458
//////////////////////////////////////////////////////////////////////
//// ////
//// DES C encrypt and decrypt functions for C golden model ////
//// ////
//// This file is part of the SystemC DES ////
//// ////
//// Description: ////
//// DES C encrypt and decrypt functions for C golden model ////
//// ////
//// To Do: ////
//// - done ////
//// ////
//// Author(s): ////
//// - Javier Castillo, jcastilo@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2004/07/05 17:31:18 jcastillo
// First import
//
 
 
 
unsigned int P[] = { 16, 7, 20, 21,
29, 12, 28, 17,
1, 15, 23, 26,
5, 18, 31, 10,
2, 8, 24, 14,
32, 27, 3, 9,
19, 13, 30, 6,
22, 11, 4, 25
};
 
unsigned int IP[] = { 58, 50, 42, 34, 26, 18, 10, 2,
60, 52, 44, 36, 28, 20, 12, 4,
62, 54, 46, 38, 30, 22, 14, 6,
64, 56, 48, 40, 32, 24, 16, 8,
57, 49, 41, 33, 25, 17, 9, 1,
59, 51, 43, 35, 27, 19, 11, 3,
61, 53, 45, 37, 29, 21, 13, 5,
63, 55, 47, 39, 31, 23, 15, 7
};
 
unsigned int IP_1[] = { 40, 8, 48, 16, 56, 24, 64, 32,
39, 7, 47, 15, 55, 23, 63, 31,
38, 6, 46, 14, 54, 22, 62, 30,
37, 5, 45, 13, 53, 21, 61, 29,
36, 4, 44, 12, 52, 20, 60, 28,
35, 3, 43, 11, 51, 19, 59, 27,
34, 2, 42, 10, 50, 18, 58, 26,
33, 1, 41, 9, 49, 17, 57, 25
};
 
unsigned int PC_1[] = { 57, 49, 41, 33, 25, 17, 9,
1, 58, 50, 42, 34, 26, 18,
10, 2, 59, 51, 43, 35, 27,
19, 11, 3, 60, 52, 44, 36,
63, 55, 47, 39, 31, 23, 15,
7, 62, 54, 46, 38, 30, 22,
14, 6, 61, 53, 45, 37, 29,
21, 13, 5, 28, 20, 12, 4
};
 
unsigned int PC_2[] = { 14, 17, 11, 24, 1, 5,
3, 28, 15, 6, 21, 10,
23, 19, 12, 4, 26, 8,
16, 7, 27, 20, 13, 2,
41, 52, 31, 37, 47, 55,
30, 40, 51, 45, 33, 48,
44, 49, 39, 56, 34, 53,
46, 42, 50, 36, 29, 32
};
 
unsigned int E[] = { 32, 1, 2, 3, 4, 5,
4, 5, 6, 7, 8, 9,
8, 9, 10, 11, 12, 13,
12, 13, 14, 15, 16, 17,
16, 17, 18, 19, 20, 21,
20, 21, 22, 23, 24, 25,
24, 25, 26, 27, 28, 29,
28, 29, 30, 31, 32, 1
};
 
unsigned int key_shifts[] =
{ 1, 1, 2, 2, 2, 2, 2, 2, 1, 2, 2, 2, 2, 2, 2, 1 };
 
unsigned int rotate_C_1[] = { 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 1, 29, 30, 31, 32
};
 
unsigned int rotate_C_2[] = { 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 1, 2, 29, 30, 31, 32
};
 
unsigned int rotate_D_1[] =
{ 1, 2, 3, 4, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21,
22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 5
};
 
unsigned int rotate_D_2[] =
{ 1, 2, 3, 4, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21,
22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 5, 6
};
 
unsigned int S1[] = { 14, 4, 13, 1, 2, 15, 11, 8, 3, 10, 6, 12, 5, 9, 0, 7,
0, 15, 7, 4, 14, 2, 13, 1, 10, 6, 12, 11, 9, 5, 3, 8,
4, 1, 14, 8, 13, 6, 2, 11, 15, 12, 9, 7, 3, 10, 5, 0,
15, 12, 8, 2, 4, 9, 1, 7, 5, 11, 3, 14, 10, 0, 6, 13
};
 
unsigned int S2[] = { 15, 1, 8, 14, 6, 11, 3, 4, 9, 7, 2, 13, 12, 0, 5, 10,
3, 13, 4, 7, 15, 2, 8, 14, 12, 0, 1, 10, 6, 9, 11, 5,
0, 14, 7, 11, 10, 4, 13, 1, 5, 8, 12, 6, 9, 3, 2, 15,
13, 8, 10, 1, 3, 15, 4, 2, 11, 6, 7, 12, 0, 5, 14, 9
};
 
unsigned int S3[] = { 10, 0, 9, 14, 6, 3, 15, 5, 1, 13, 12, 7, 11, 4, 2, 8,
13, 7, 0, 9, 3, 4, 6, 10, 2, 8, 5, 14, 12, 11, 15, 1,
13, 6, 4, 9, 8, 15, 3, 0, 11, 1, 2, 12, 5, 10, 14, 7,
1, 10, 13, 0, 6, 9, 8, 7, 4, 15, 14, 3, 11, 5, 2, 12
};
 
unsigned int S4[] = { 7, 13, 14, 3, 0, 6, 9, 10, 1, 2, 8, 5, 11, 12, 4, 15,
13, 8, 11, 5, 6, 15, 0, 3, 4, 7, 2, 12, 1, 10, 14, 9,
10, 6, 9, 0, 12, 11, 7, 13, 15, 1, 3, 14, 5, 2, 8, 4,
3, 15, 0, 6, 10, 1, 13, 8, 9, 4, 5, 11, 12, 7, 2, 14
};
 
unsigned int S5[] = { 2, 12, 4, 1, 7, 10, 11, 6, 8, 5, 3, 15, 13, 0, 14, 9,
14, 11, 2, 12, 4, 7, 13, 1, 5, 0, 15, 10, 3, 9, 8, 6,
4, 2, 1, 11, 10, 13, 7, 8, 15, 9, 12, 5, 6, 3, 0, 14,
11, 8, 12, 7, 1, 14, 2, 13, 6, 15, 0, 9, 10, 4, 5, 3
};
 
unsigned int S6[] = { 12, 1, 10, 15, 9, 2, 6, 8, 0, 13, 3, 4, 14, 7, 5, 11,
10, 15, 4, 2, 7, 12, 9, 5, 6, 1, 13, 14, 0, 11, 3, 8,
9, 14, 15, 5, 2, 8, 12, 3, 7, 0, 4, 10, 1, 13, 11, 6,
4, 3, 2, 12, 9, 5, 15, 10, 11, 14, 1, 7, 6, 0, 8, 13
};
 
unsigned int S7[] = { 4, 11, 2, 14, 15, 0, 8, 13, 3, 12, 9, 7, 5, 10, 6, 1,
13, 0, 11, 7, 4, 9, 1, 10, 14, 3, 5, 12, 2, 15, 8, 6,
1, 4, 11, 13, 12, 3, 7, 14, 10, 15, 6, 8, 0, 5, 9, 2,
6, 11, 13, 8, 1, 4, 10, 7, 9, 5, 0, 15, 14, 2, 3, 12
};
 
unsigned int S8[] = { 13, 2, 8, 4, 6, 15, 11, 1, 10, 9, 3, 14, 5, 0, 12, 7,
1, 15, 13, 8, 10, 3, 7, 4, 12, 5, 6, 11, 0, 14, 9, 2,
7, 11, 4, 1, 9, 12, 14, 2, 0, 6, 10, 13, 15, 3, 5, 8,
2, 1, 14, 7, 4, 10, 8, 13, 15, 12, 9, 0, 3, 5, 6, 11
};
 
 
void
apply_table (unsigned char *block, unsigned char *block_t, unsigned int *perm,
int outlength)
{
unsigned int i, byte, bit;
 
for (i = 0; i < outlength >> 3; i++)
block_t[i] = 0;
 
for (i = 0; i < outlength; i++)
{
byte = ((perm[i] - 1) >> 3); /*In which byte of the original block is the bit to permute */
bit = ((perm[i] - 1) & 7); /*In which pos of the byte is the bit to permute */
if ((block[byte] >> (7 - bit)) & 1 == 1)
block_t[i >> 3] += (0x80 >> (i & 7));
}
}
 
void
generate_key (unsigned char *previous_key, unsigned char *new_key,
int iteration)
{
/*Generates the next iteration non permuted key from the previous non-permuted key */
 
unsigned char Cx_rotated[4], Dx_rotated[4];
unsigned char Cx[4], Dx[4];
unsigned int i;
 
for (i = 0; i < 7; i++)
new_key[i] = 0;
 
 
/*We split the 56 bit key in two parts */
Cx[0] = previous_key[0];
Cx[1] = previous_key[1];
Cx[2] = previous_key[2];
Cx[3] = previous_key[3];
Dx[0] = previous_key[3];
Dx[1] = previous_key[4];
Dx[2] = previous_key[5];
Dx[3] = previous_key[6];
 
/*Rotate Cx and Dx */
if (key_shifts[iteration - 1] == 1)
{
apply_table (Cx, Cx_rotated, rotate_C_1, 32);
apply_table (Dx, Dx_rotated, rotate_D_1, 32);
}
else if (key_shifts[iteration - 1] == 2)
{
apply_table (Cx, Cx_rotated, rotate_C_2, 32);
apply_table (Dx, Dx_rotated, rotate_D_2, 32);
}
 
//binary_print(previous_key,7);
//binary_print(Cx_rotated,4);
//binary_print(Dx_rotated,4);
 
/*Recompose key */
new_key[0] = Cx_rotated[0];
new_key[1] = Cx_rotated[1];
new_key[2] = Cx_rotated[2];
new_key[3] = (Cx_rotated[3] & 0xF0);
 
new_key[3] += Dx_rotated[0] & 0xF;
new_key[4] = Dx_rotated[1];
new_key[5] = Dx_rotated[2];
new_key[6] = Dx_rotated[3];
 
//binary_print(new_key,7);
}
 
void
applyS (unsigned char *KER, unsigned char *KERS)
{
 
unsigned char aux;
int i;
unsigned short int row, col;
 
for (i = 0; i < 4; i++)
KERS[i] = 0;
 
/*Transform KER with S matrix */
row = ((KER[0] >> 2) & 1) + ((KER[0] & 0x80) >> 6);
aux = KER[0] << 1;
col = aux >> 4;
KERS[0] = S1[16 * row + col];
 
row = (KER[0] & 2) + ((KER[1] >> 4) & 1);
col = ((KER[0] & 1) << 3) + (KER[1] >> 5);
KERS[0] = (KERS[0] << 4) + S2[16 * row + col];
 
row = ((KER[1] >> 2) & 2) + ((KER[2] >> 6) & 1);
col = ((KER[1] & 7) << 1) + ((KER[2] & 0x80) >> 7);
KERS[1] = S3[16 * row + col];
 
row = ((KER[2] >> 4) & 2) + (KER[2] & 1);
col = (KER[2] >> 1) & 0xF;
KERS[1] = (KERS[1] << 4) + S4[16 * row + col];
 
row = ((KER[3] >> 2) & 1) + ((KER[3] & 0x80) >> 6);
aux = KER[3] << 1;
col = aux >> 4;
KERS[2] = S5[16 * row + col];
 
row = (KER[3] & 2) + ((KER[4] >> 4) & 1);
col = ((KER[3] & 1) << 3) + (KER[4] >> 5);
KERS[2] = (KERS[2] << 4) + S6[16 * row + col];
 
row = ((KER[4] >> 2) & 2) + ((KER[5] >> 6) & 1);
col = ((KER[4] & 7) << 1) + ((KER[5] & 0x80) >> 7);
KERS[3] = S7[16 * row + col];
 
row = ((KER[5] >> 4) & 2) + (KER[5] & 1);
col = (KER[5] >> 1) & 0xF;
KERS[3] = (KERS[3] << 4) + S8[16 * row + col];
 
}
 
void
encrypt_des (unsigned char *block, unsigned char *block_o, unsigned char *key)
{
 
unsigned char block_t[8];
unsigned char new_key[7], permuted_key[6], ER[6], last_key[7];
unsigned char KER[6];
unsigned char KERS[4]; /*32 bits after apply the S matrix */
unsigned char fKERS[4]; /*32 bits after apply the P matrix */
 
int i, j;
unsigned char b0_t, b1_t, b2_t, b3_t;
 
/*This is the main DES encrypt function
encrypt one block of 64 bits with a key of 64 bits */
 
/*First we generate the permuted key of 56 bits from the 64 bits one */
apply_table (key, last_key, PC_1, 7 * 8);
/*Now we have the K+ key of 56 bits */
 
/*We generate the first permuted block */
apply_table (block, block_t, IP, 8 * 8);
 
 
/*16 iterations */
for (i = 1; i < 17; i++)
{
generate_key (last_key, new_key, i);
for (j = 0; j < 7; j++)
last_key[j] = new_key[j];
apply_table (new_key, permuted_key, PC_2, 6 * 8);
 
/*We now calculate f(R,K) */
/*Compute E(R0) */
apply_table (block_t + 4, ER, E, 6 * 8);
/*Key XOR ER */
for (j = 0; j < 6; j++)
KER[j] = ER[j] ^ permuted_key[j];
 
applyS (KER, KERS);
apply_table (KERS, fKERS, P, 4 * 8);
 
/*Make the aditions */
/*Li=Ri-1 */
b0_t = block_t[0];
b1_t = block_t[1];
b2_t = block_t[2];
b3_t = block_t[3];
block_t[0] = block_t[4];
block_t[1] = block_t[5];
block_t[2] = block_t[6];
block_t[3] = block_t[7];
/*Ri=Li-1+fKERS */
block_t[4] = b0_t ^ fKERS[0];
block_t[5] = b1_t ^ fKERS[1];
block_t[6] = b2_t ^ fKERS[2];
block_t[7] = b3_t ^ fKERS[3];
}
/*Recolocate L and R */
b0_t = block_t[0];
b1_t = block_t[1];
b2_t = block_t[2];
b3_t = block_t[3];
block_t[0] = block_t[4];
block_t[1] = block_t[5];
block_t[2] = block_t[6];
block_t[3] = block_t[7];
block_t[4] = b0_t;
block_t[5] = b1_t;
block_t[6] = b2_t;
block_t[7] = b3_t;
 
/*Final permutation */
apply_table (block_t, block_o, IP_1, 8 * 8);
 
}
 
void
decrypt_des (unsigned char *block, unsigned char *block_o, unsigned char *key)
{
unsigned char block_t[8];
unsigned char new_key[7], permuted_key[6], ER[6], last_key[7];
unsigned char KER[6];
unsigned char KERS[4]; /*32 bits after apply the S matrix */
unsigned char fKERS[4]; /*32 bits after apply the P matrix */
unsigned char keys[16][6];
 
int i, j;
unsigned char b0_t, b1_t, b2_t, b3_t;
 
/*This is the main DES decrypt function
encrypt one block of 64 bits with a key of 64 bits */
 
/*First we generate the permuted key of 56 bits from the 64 bits one */
apply_table (key, last_key, PC_1, 7 * 8);
/*Now we have the K+ key of 56 bits */
 
/*We generate the first permuted block */
apply_table (block, block_t, IP, 8 * 8);
 
for (i = 1; i < 17; i++)
{
generate_key (last_key, new_key, i);
for (j = 0; j < 7; j++)
last_key[j] = new_key[j];
apply_table (new_key, permuted_key, PC_2, 6 * 8);
for (j = 0; j < 6; j++)
keys[i - 1][j] = permuted_key[j];
}
 
/*16 iterations */
for (i = 1; i < 17; i++)
{
/*We now calculate f(R,K) */
/*Compute E(R0) */
apply_table (block_t + 4, ER, E, 6 * 8);
/*Key XOR ER */
for (j = 0; j < 6; j++)
KER[j] = ER[j] ^ keys[15 - (i - 1)][j];
 
applyS (KER, KERS);
apply_table (KERS, fKERS, P, 4 * 8);
 
/*Make the aditions */
/*Li=Ri-1 */
b0_t = block_t[0];
b1_t = block_t[1];
b2_t = block_t[2];
b3_t = block_t[3];
block_t[0] = block_t[4];
block_t[1] = block_t[5];
block_t[2] = block_t[6];
block_t[3] = block_t[7];
/*Ri=Li-1+fKERS */
block_t[4] = b0_t ^ fKERS[0];
block_t[5] = b1_t ^ fKERS[1];
block_t[6] = b2_t ^ fKERS[2];
block_t[7] = b3_t ^ fKERS[3];
}
/*Recolocate L and R */
b0_t = block_t[0];
b1_t = block_t[1];
b2_t = block_t[2];
b3_t = block_t[3];
block_t[0] = block_t[4];
block_t[1] = block_t[5];
block_t[2] = block_t[6];
block_t[3] = block_t[7];
block_t[4] = b0_t;
block_t[5] = b1_t;
block_t[6] = b2_t;
block_t[7] = b3_t;
 
/*Final permutation */
apply_table (block_t, block_o, IP_1, 8 * 8);
 
}
/systemcdes/trunk/rtl/systemc/checker.h
0,0 → 1,93
//////////////////////////////////////////////////////////////////////
//// ////
//// Checker ////
//// ////
//// This file is part of the SystemC DES ////
//// ////
//// Description: ////
//// Check that the outputs from the RTL model and the C model ////
//// used as golden model are the same ////
//// ////
//// To Do: ////
//// - done ////
//// ////
//// Author(s): ////
//// - Javier Castillo, jcastilo@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2004/07/05 17:31:18 jcastillo
// First import
//
 
 
#include "systemc.h"
 
SC_MODULE (checker)
{
 
sc_in < bool > reset;
 
sc_fifo_in < sc_uint < 64 > >rt_des_data_i;
sc_fifo_in < sc_uint < 64 > >c_des_data_i;
 
void check ()
{
sc_uint < 64 > rt_data_var, c_data_var;
 
wait (reset->posedge_event ());
 
while (1)
{
if (reset.read ())
{
rt_data_var = rt_des_data_i.read ();
c_data_var = c_des_data_i.read ();
if (rt_data_var != c_data_var)
{
cout << "Simulation mismatch: 0x" << (int) rt_data_var.range (63, 32) << (int) rt_data_var.range (31,0) << " 0x" << (int) c_data_var.range (63,32) << (int) c_data_var.range (31,0) <<" " << sc_time_stamp () << endl;
exit (0);
}
else
{
cout << "OK: 0x" << (int) rt_data_var.range (63,32) << (int)rt_data_var.range (31,0) << " 0x" << (int) c_data_var.range (63, 32) << (int) c_data_var.range (31,0) << " " << sc_time_stamp () << endl;
}
}
else
wait (reset->posedge_event ());
}
}
 
SC_CTOR (checker)
{
SC_THREAD (check);
}
};
/systemcdes/trunk/rtl/systemc/des.h
0,0 → 1,189
//////////////////////////////////////////////////////////////////////
//// ////
//// DES algorithm header ////
//// ////
//// This file is part of the SystemC DES ////
//// ////
//// Description: ////
//// Top file for DES algorithm ////
//// ////
//// To Do: ////
//// - nothing ////
//// ////
//// Author(s): ////
//// - Javier Castillo, jcastilo@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2004/07/05 17:31:17 jcastillo
// First import
//
 
#include "systemc.h"
 
#include "round.h"
//S boxes
#include "s1.h"
#include "s2.h"
#include "s3.h"
#include "s4.h"
#include "s5.h"
#include "s6.h"
#include "s7.h"
#include "s8.h"
 
 
SC_MODULE (des)
{
 
sc_in < bool > clk;
sc_in < bool > reset;
 
sc_in < bool > load_i;
sc_in < bool > decrypt_i;
sc_in < sc_uint < 64 > >data_i;
sc_in < sc_uint < 64 > >key_i;
 
sc_out < sc_uint < 64 > >data_o;
sc_out < bool > ready_o;
 
//Registers for iteration counters
sc_signal < sc_uint < 4 > >stage1_iter, next_stage1_iter;
sc_signal < bool > next_ready_o;
sc_signal < sc_uint < 64 > >next_data_o;
sc_signal < bool > data_ready, next_data_ready;
 
//Conections to desround stage1
sc_signal < sc_uint < 32 > >stage1_L_i;
sc_signal < sc_uint < 32 > >stage1_R_i;
sc_signal < sc_uint < 56 > >stage1_round_key_i;
 
sc_signal < sc_uint < 4 > >stage1_iteration_i;
sc_signal < sc_uint < 32 > >stage1_R_o;
sc_signal < sc_uint < 32 > >stage1_L_o;
sc_signal < sc_uint < 56 > >stage1_round_key_o;
 
sc_signal < sc_uint < 6 > >s1_stag1_i, s2_stag1_i, s3_stag1_i, s4_stag1_i,
s5_stag1_i, s6_stag1_i, s7_stag1_i, s8_stag1_i;
sc_signal < sc_uint < 4 > >s1_stag1_o, s2_stag1_o, s3_stag1_o, s4_stag1_o,
s5_stag1_o, s6_stag1_o, s7_stag1_o, s8_stag1_o;
 
void des_proc ();
void reg_signal ();
 
desround *rd1;
 
s1 *sbox1;
s2 *sbox2;
s3 *sbox3;
s4 *sbox4;
s5 *sbox5;
s6 *sbox6;
s7 *sbox7;
s8 *sbox8;
 
SC_CTOR (des)
{
 
SC_METHOD (reg_signal);
sensitive_pos << clk;
sensitive_neg << reset;
 
SC_METHOD (des_proc);
sensitive << data_i << key_i << load_i << stage1_iter << data_ready;
sensitive << stage1_L_o << stage1_R_o << stage1_round_key_o;
 
rd1 = new desround ("round1");
 
sbox1 = new s1 ("s1");
sbox2 = new s2 ("s2");
sbox3 = new s3 ("s3");
sbox4 = new s4 ("s4");
sbox5 = new s5 ("s5");
sbox6 = new s6 ("s6");
sbox7 = new s7 ("s7");
sbox8 = new s8 ("s8");
 
//For each stage in the pipe one instance
//First stage always present
rd1->clk (clk);
rd1->reset (reset);
rd1->iteration_i (stage1_iteration_i);
rd1->decrypt_i (decrypt_i);
rd1->R_i (stage1_R_i);
rd1->L_i (stage1_L_i);
rd1->Key_i (stage1_round_key_i);
rd1->R_o (stage1_R_o);
rd1->L_o (stage1_L_o);
rd1->Key_o (stage1_round_key_o);
rd1->s1_o (s1_stag1_i);
rd1->s2_o (s2_stag1_i);
rd1->s3_o (s3_stag1_i);
rd1->s4_o (s4_stag1_i);
rd1->s5_o (s5_stag1_i);
rd1->s6_o (s6_stag1_i);
rd1->s7_o (s7_stag1_i);
rd1->s8_o (s8_stag1_i);
rd1->s1_i (s1_stag1_o);
rd1->s2_i (s2_stag1_o);
rd1->s3_i (s3_stag1_o);
rd1->s4_i (s4_stag1_o);
rd1->s5_i (s5_stag1_o);
rd1->s6_i (s6_stag1_o);
rd1->s7_i (s7_stag1_o);
rd1->s8_i (s8_stag1_o);
 
sbox1->stage1_input (s1_stag1_i);
sbox1->stage1_output (s1_stag1_o);
 
sbox2->stage1_input (s2_stag1_i);
sbox2->stage1_output (s2_stag1_o);
 
sbox3->stage1_input (s3_stag1_i);
sbox3->stage1_output (s3_stag1_o);
 
sbox4->stage1_input (s4_stag1_i);
sbox4->stage1_output (s4_stag1_o);
 
sbox5->stage1_input (s5_stag1_i);
sbox5->stage1_output (s5_stag1_o);
 
sbox6->stage1_input (s6_stag1_i);
sbox6->stage1_output (s6_stag1_o);
 
sbox7->stage1_input (s7_stag1_i);
sbox7->stage1_output (s7_stag1_o);
 
sbox8->stage1_input (s8_stag1_i);
sbox8->stage1_output (s8_stag1_o);
 
}
};
/systemcdes/trunk/rtl/systemc/s1.cpp
0,0 → 1,252
//////////////////////////////////////////////////////////////////////
//// ////
//// SBOX 1 ////
//// ////
//// This file is part of the SystemC DES ////
//// ////
//// Description: ////
//// Sbox of DES algorithm ////
//// ////
//// To Do: ////
//// - done ////
//// ////
//// Author(s): ////
//// - Javier Castillo, jcastilo@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2004/07/05 17:31:17 jcastillo
// First import
//
 
#include "s1.h"
 
 
void
s1::s1_box ()
{
 
switch (stage1_input.read ())
{
case 0:
stage1_output.write (14);
break;
case 1:
stage1_output.write (0);
break;
case 2:
stage1_output.write (4);
break;
case 3:
stage1_output.write (15);
break;
case 4:
stage1_output.write (13);
break;
case 5:
stage1_output.write (7);
break;
case 6:
stage1_output.write (1);
break;
case 7:
stage1_output.write (4);
break;
case 8:
stage1_output.write (2);
break;
case 9:
stage1_output.write (14);
break;
case 10:
stage1_output.write (15);
break;
case 11:
stage1_output.write (2);
break;
case 12:
stage1_output.write (11);
break;
case 13:
stage1_output.write (13);
break;
case 14:
stage1_output.write (8);
break;
case 15:
stage1_output.write (1);
break;
case 16:
stage1_output.write (3);
break;
case 17:
stage1_output.write (10);
break;
case 18:
stage1_output.write (10);
break;
case 19:
stage1_output.write (6);
break;
case 20:
stage1_output.write (6);
break;
case 21:
stage1_output.write (12);
break;
case 22:
stage1_output.write (12);
break;
case 23:
stage1_output.write (11);
break;
case 24:
stage1_output.write (5);
break;
case 25:
stage1_output.write (9);
break;
case 26:
stage1_output.write (9);
break;
case 27:
stage1_output.write (5);
break;
case 28:
stage1_output.write (0);
break;
case 29:
stage1_output.write (3);
break;
case 30:
stage1_output.write (7);
break;
case 31:
stage1_output.write (8);
break;
case 32:
stage1_output.write (4);
break;
case 33:
stage1_output.write (15);
break;
case 34:
stage1_output.write (1);
break;
case 35:
stage1_output.write (12);
break;
case 36:
stage1_output.write (14);
break;
case 37:
stage1_output.write (8);
break;
case 38:
stage1_output.write (8);
break;
case 39:
stage1_output.write (2);
break;
case 40:
stage1_output.write (13);
break;
case 41:
stage1_output.write (4);
break;
case 42:
stage1_output.write (6);
break;
case 43:
stage1_output.write (9);
break;
case 44:
stage1_output.write (2);
break;
case 45:
stage1_output.write (1);
break;
case 46:
stage1_output.write (11);
break;
case 47:
stage1_output.write (7);
break;
case 48:
stage1_output.write (15);
break;
case 49:
stage1_output.write (5);
break;
case 50:
stage1_output.write (12);
break;
case 51:
stage1_output.write (11);
break;
case 52:
stage1_output.write (9);
break;
case 53:
stage1_output.write (3);
break;
case 54:
stage1_output.write (7);
break;
case 55:
stage1_output.write (14);
break;
case 56:
stage1_output.write (3);
break;
case 57:
stage1_output.write (10);
break;
case 58:
stage1_output.write (10);
break;
case 59:
stage1_output.write (0);
break;
case 60:
stage1_output.write (5);
break;
case 61:
stage1_output.write (6);
break;
case 62:
stage1_output.write (0);
break;
case 63:
stage1_output.write (13);
break;
}
}
/systemcdes/trunk/rtl/systemc/s2.cpp
0,0 → 1,253
//////////////////////////////////////////////////////////////////////
//// ////
//// SBOX 2 ////
//// ////
//// This file is part of the SystemC DES ////
//// ////
//// Description: ////
//// Sbox of DES algorithm ////
//// ////
//// To Do: ////
//// - done ////
//// ////
//// Author(s): ////
//// - Javier Castillo, jcastilo@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2004/07/05 17:31:17 jcastillo
// First import
//
 
#include "s2.h"
 
 
void
s2::s2_box ()
{
 
switch (stage1_input.read ())
{
case 0:
stage1_output.write (15);
break;
case 1:
stage1_output.write (3);
break;
case 2:
stage1_output.write (1);
break;
case 3:
stage1_output.write (13);
break;
case 4:
stage1_output.write (8);
break;
case 5:
stage1_output.write (4);
break;
case 6:
stage1_output.write (14);
break;
case 7:
stage1_output.write (7);
break;
case 8:
stage1_output.write (6);
break;
case 9:
stage1_output.write (15);
break;
case 10:
stage1_output.write (11);
break;
case 11:
stage1_output.write (2);
break;
case 12:
stage1_output.write (3);
break;
case 13:
stage1_output.write (8);
break;
case 14:
stage1_output.write (4);
break;
case 15:
stage1_output.write (14);
break;
case 16:
stage1_output.write (9);
break;
case 17:
stage1_output.write (12);
break;
case 18:
stage1_output.write (7);
break;
case 19:
stage1_output.write (0);
break;
case 20:
stage1_output.write (2);
break;
case 21:
stage1_output.write (1);
break;
case 22:
stage1_output.write (13);
break;
case 23:
stage1_output.write (10);
break;
case 24:
stage1_output.write (12);
break;
case 25:
stage1_output.write (6);
break;
case 26:
stage1_output.write (0);
break;
case 27:
stage1_output.write (9);
break;
case 28:
stage1_output.write (5);
break;
case 29:
stage1_output.write (11);
break;
case 30:
stage1_output.write (10);
break;
case 31:
stage1_output.write (5);
break;
case 32:
stage1_output.write (0);
break;
case 33:
stage1_output.write (13);
break;
case 34:
stage1_output.write (14);
break;
case 35:
stage1_output.write (8);
break;
case 36:
stage1_output.write (7);
break;
case 37:
stage1_output.write (10);
break;
case 38:
stage1_output.write (11);
break;
case 39:
stage1_output.write (1);
break;
case 40:
stage1_output.write (10);
break;
case 41:
stage1_output.write (3);
break;
case 42:
stage1_output.write (4);
break;
case 43:
stage1_output.write (15);
break;
case 44:
stage1_output.write (13);
break;
case 45:
stage1_output.write (4);
break;
case 46:
stage1_output.write (1);
break;
case 47:
stage1_output.write (2);
break;
case 48:
stage1_output.write (5);
break;
case 49:
stage1_output.write (11);
break;
case 50:
stage1_output.write (8);
break;
case 51:
stage1_output.write (6);
break;
case 52:
stage1_output.write (12);
break;
case 53:
stage1_output.write (7);
break;
case 54:
stage1_output.write (6);
break;
case 55:
stage1_output.write (12);
break;
case 56:
stage1_output.write (9);
break;
case 57:
stage1_output.write (0);
break;
case 58:
stage1_output.write (3);
break;
case 59:
stage1_output.write (5);
break;
case 60:
stage1_output.write (2);
break;
case 61:
stage1_output.write (14);
break;
case 62:
stage1_output.write (15);
break;
case 63:
stage1_output.write (9);
break;
 
}
}
/systemcdes/trunk/rtl/systemc/s3.cpp
0,0 → 1,252
//////////////////////////////////////////////////////////////////////
//// ////
//// SBOX 3 ////
//// ////
//// This file is part of the SystemC DES ////
//// ////
//// Description: ////
//// Sbox of DES algorithm ////
//// ////
//// To Do: ////
//// - done ////
//// ////
//// Author(s): ////
//// - Javier Castillo, jcastilo@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2004/07/05 17:31:17 jcastillo
// First import
//
 
#include "s3.h"
 
 
void
s3::s3_box ()
{
switch (stage1_input.read ())
{
case 0:
stage1_output.write (10);
break;
case 1:
stage1_output.write (13);
break;
case 2:
stage1_output.write (0);
break;
case 3:
stage1_output.write (7);
break;
case 4:
stage1_output.write (9);
break;
case 5:
stage1_output.write (0);
break;
case 6:
stage1_output.write (14);
break;
case 7:
stage1_output.write (9);
break;
case 8:
stage1_output.write (6);
break;
case 9:
stage1_output.write (3);
break;
case 10:
stage1_output.write (3);
break;
case 11:
stage1_output.write (4);
break;
case 12:
stage1_output.write (15);
break;
case 13:
stage1_output.write (6);
break;
case 14:
stage1_output.write (5);
break;
case 15:
stage1_output.write (10);
break;
case 16:
stage1_output.write (1);
break;
case 17:
stage1_output.write (2);
break;
case 18:
stage1_output.write (13);
break;
case 19:
stage1_output.write (8);
break;
case 20:
stage1_output.write (12);
break;
case 21:
stage1_output.write (5);
break;
case 22:
stage1_output.write (7);
break;
case 23:
stage1_output.write (14);
break;
case 24:
stage1_output.write (11);
break;
case 25:
stage1_output.write (12);
break;
case 26:
stage1_output.write (4);
break;
case 27:
stage1_output.write (11);
break;
case 28:
stage1_output.write (2);
break;
case 29:
stage1_output.write (15);
break;
case 30:
stage1_output.write (8);
break;
case 31:
stage1_output.write (1);
break;
case 32:
stage1_output.write (13);
break;
case 33:
stage1_output.write (1);
break;
case 34:
stage1_output.write (6);
break;
case 35:
stage1_output.write (10);
break;
case 36:
stage1_output.write (4);
break;
case 37:
stage1_output.write (13);
break;
case 38:
stage1_output.write (9);
break;
case 39:
stage1_output.write (0);
break;
case 40:
stage1_output.write (8);
break;
case 41:
stage1_output.write (6);
break;
case 42:
stage1_output.write (15);
break;
case 43:
stage1_output.write (9);
break;
case 44:
stage1_output.write (3);
break;
case 45:
stage1_output.write (8);
break;
case 46:
stage1_output.write (0);
break;
case 47:
stage1_output.write (7);
break;
case 48:
stage1_output.write (11);
break;
case 49:
stage1_output.write (4);
break;
case 50:
stage1_output.write (1);
break;
case 51:
stage1_output.write (15);
break;
case 52:
stage1_output.write (2);
break;
case 53:
stage1_output.write (14);
break;
case 54:
stage1_output.write (12);
break;
case 55:
stage1_output.write (3);
break;
case 56:
stage1_output.write (5);
break;
case 57:
stage1_output.write (11);
break;
case 58:
stage1_output.write (10);
break;
case 59:
stage1_output.write (5);
break;
case 60:
stage1_output.write (14);
break;
case 61:
stage1_output.write (2);
break;
case 62:
stage1_output.write (7);
break;
case 63:
stage1_output.write (12);
break;
}
 
}
/systemcdes/trunk/rtl/systemc/stimulus.cpp
0,0 → 1,92
//////////////////////////////////////////////////////////////////////
//// ////
//// Random stimulus generation ////
//// ////
//// This file is part of the SystemC DES ////
//// ////
//// Description: ////
//// DES random stimulus ////
//// ////
//// To Do: ////
//// - nothing ////
//// ////
//// Author(s): ////
//// - Javier Castillo, jcastilo@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2004/07/05 17:31:18 jcastillo
// First import
//
 
 
 
 
#include "stimulus.h"
 
void
test::tb ()
{
 
sc_uint < 64 > des_key_var, des_data_var;
bool decrypt_var;
 
scv_random::set_global_seed (53246);
 
random_generator rg ("random_generator");
 
transactor->resetea ();
 
while (1)
{
 
rg.des_key->next ();
rg.des_data->next ();
rg.decrypt->next ();
 
 
des_data_var = *(rg.des_data);
des_key_var = *(rg.des_key);
decrypt_var = *(rg.decrypt);
 
if (!decrypt_var)
{
cout << "Encrypt: 0x" << (int) des_data_var.range (63,32) << (int)des_data_var.range (31,0) << " 0x" << (int) des_key_var.range (63,32) << (int) des_key_var.range (31,0) << " " << sc_time_stamp () << endl;
transactor->encrypt (des_data_var, des_key_var);
}
else
{
cout << "Decrypt: 0x" << (int) des_data_var.range (63,32) << (int)des_data_var.range (31,0) << " 0x" << (int) des_key_var.range (63,32) << (int) des_key_var.range (31,0) << " " << sc_time_stamp () << endl;
transactor->decrypt (des_data_var, des_key_var);
}
}
 
}
/systemcdes/trunk/rtl/systemc/s4.cpp
0,0 → 1,252
//////////////////////////////////////////////////////////////////////
//// ////
//// SBOX 4 ////
//// ////
//// This file is part of the SystemC DES ////
//// ////
//// Description: ////
//// Sbox of DES algorithm ////
//// ////
//// To Do: ////
//// - done ////
//// ////
//// Author(s): ////
//// - Javier Castillo, jcastilo@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2004/07/05 17:31:18 jcastillo
// First import
//
 
#include "s4.h"
 
 
void
s4::s4_box ()
{
switch (stage1_input.read ())
{
case 0:
stage1_output.write (7);
break;
case 1:
stage1_output.write (13);
break;
case 2:
stage1_output.write (13);
break;
case 3:
stage1_output.write (8);
break;
case 4:
stage1_output.write (14);
break;
case 5:
stage1_output.write (11);
break;
case 6:
stage1_output.write (3);
break;
case 7:
stage1_output.write (5);
break;
case 8:
stage1_output.write (0);
break;
case 9:
stage1_output.write (6);
break;
case 10:
stage1_output.write (6);
break;
case 11:
stage1_output.write (15);
break;
case 12:
stage1_output.write (9);
break;
case 13:
stage1_output.write (0);
break;
case 14:
stage1_output.write (10);
break;
case 15:
stage1_output.write (3);
break;
case 16:
stage1_output.write (1);
break;
case 17:
stage1_output.write (4);
break;
case 18:
stage1_output.write (2);
break;
case 19:
stage1_output.write (7);
break;
case 20:
stage1_output.write (8);
break;
case 21:
stage1_output.write (2);
break;
case 22:
stage1_output.write (5);
break;
case 23:
stage1_output.write (12);
break;
case 24:
stage1_output.write (11);
break;
case 25:
stage1_output.write (1);
break;
case 26:
stage1_output.write (12);
break;
case 27:
stage1_output.write (10);
break;
case 28:
stage1_output.write (4);
break;
case 29:
stage1_output.write (14);
break;
case 30:
stage1_output.write (15);
break;
case 31:
stage1_output.write (9);
break;
case 32:
stage1_output.write (10);
break;
case 33:
stage1_output.write (3);
break;
case 34:
stage1_output.write (6);
break;
case 35:
stage1_output.write (15);
break;
case 36:
stage1_output.write (9);
break;
case 37:
stage1_output.write (0);
break;
case 38:
stage1_output.write (0);
break;
case 39:
stage1_output.write (6);
break;
case 40:
stage1_output.write (12);
break;
case 41:
stage1_output.write (10);
break;
case 42:
stage1_output.write (11);
break;
case 43:
stage1_output.write (1);
break;
case 44:
stage1_output.write (7);
break;
case 45:
stage1_output.write (13);
break;
case 46:
stage1_output.write (13);
break;
case 47:
stage1_output.write (8);
break;
case 48:
stage1_output.write (15);
break;
case 49:
stage1_output.write (9);
break;
case 50:
stage1_output.write (1);
break;
case 51:
stage1_output.write (4);
break;
case 52:
stage1_output.write (3);
break;
case 53:
stage1_output.write (5);
break;
case 54:
stage1_output.write (14);
break;
case 55:
stage1_output.write (11);
break;
case 56:
stage1_output.write (5);
break;
case 57:
stage1_output.write (12);
break;
case 58:
stage1_output.write (2);
break;
case 59:
stage1_output.write (7);
break;
case 60:
stage1_output.write (8);
break;
case 61:
stage1_output.write (2);
break;
case 62:
stage1_output.write (4);
break;
case 63:
stage1_output.write (14);
break;
}
 
}
/systemcdes/trunk/rtl/systemc/round.cpp
0,0 → 1,213
//////////////////////////////////////////////////////////////////////
//// ////
//// Round of DES algorithm implementation ////
//// ////
//// This file is part of the SystemC DES ////
//// ////
//// Description: ////
//// This file perform a round of the DES algorithm ////
//// ////
//// To Do: ////
//// - nothing ////
//// ////
//// Author(s): ////
//// - Javier Castillo, jcastilo@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2004/07/05 17:31:17 jcastillo
// First import
//
 
 
#include "round.h"
 
void
desround::registers ()
{
 
if (!reset.read ())
{
L_o.write (0);
R_o.write (0);
Key_o.write (0);
}
else
{
L_o.write (R_i.read ());
R_o.write (next_R.read ());
Key_o.write (non_perm_key.read ());
}
}
 
 
 
void
desround::round_proc ()
{
 
sc_uint < 48 > expandedR;
sc_uint < 48 > round_key;
sc_uint < 48 > KER;
sc_uint < 32 > R_i_var;
 
sc_uint < 32 > Soutput;
sc_uint < 32 > f;
 
R_i_var = R_i.read ();
 
//Expand the data
expandedR[47] = R_i_var[0];
expandedR[46] = R_i_var[31];
expandedR[45] = R_i_var[30];
expandedR[44] = R_i_var[29];
expandedR[43] = R_i_var[28];
expandedR[42] = R_i_var[27];
expandedR[41] = R_i_var[28];
expandedR[40] = R_i_var[27];
 
expandedR[39] = R_i_var[26];
expandedR[38] = R_i_var[25];
expandedR[37] = R_i_var[24];
expandedR[36] = R_i_var[23];
expandedR[35] = R_i_var[24];
expandedR[34] = R_i_var[23];
expandedR[33] = R_i_var[22];
expandedR[32] = R_i_var[21];
 
expandedR[31] = R_i_var[20];
expandedR[30] = R_i_var[19];
expandedR[29] = R_i_var[20];
expandedR[28] = R_i_var[19];
expandedR[27] = R_i_var[18];
expandedR[26] = R_i_var[17];
expandedR[25] = R_i_var[16];
expandedR[24] = R_i_var[15];
 
expandedR[23] = R_i_var[16];
expandedR[22] = R_i_var[15];
expandedR[21] = R_i_var[14];
expandedR[20] = R_i_var[13];
expandedR[19] = R_i_var[12];
expandedR[18] = R_i_var[11];
expandedR[17] = R_i_var[12];
expandedR[16] = R_i_var[11];
 
expandedR[15] = R_i_var[10];
expandedR[14] = R_i_var[9];
expandedR[13] = R_i_var[8];
expandedR[12] = R_i_var[7];
expandedR[11] = R_i_var[8];
expandedR[10] = R_i_var[7];
expandedR[9] = R_i_var[6];
expandedR[8] = R_i_var[5];
 
expandedR[7] = R_i_var[4];
expandedR[6] = R_i_var[3];
expandedR[5] = R_i_var[4];
expandedR[4] = R_i_var[3];
expandedR[3] = R_i_var[2];
expandedR[2] = R_i_var[1];
expandedR[1] = R_i_var[0];
expandedR[0] = R_i_var[31];
 
//Generate the Key
previous_key.write (Key_i.read ());
iteration.write (iteration_i.read ());
decrypt.write (decrypt_i.read ());
 
round_key = new_key.read ();
 
//XOR the key with the block
KER = expandedR ^ round_key;
 
//Apply Sboxes
s1_o.write (KER.range (47, 42));
s2_o.write (KER.range (41, 36));
s3_o.write (KER.range (35, 30));
s4_o.write (KER.range (29, 24));
s5_o.write (KER.range (23, 18));
s6_o.write (KER.range (17, 12));
s7_o.write (KER.range (11, 6));
s8_o.write (KER.range (5, 0));
 
Soutput.range (31, 28) = s1_i.read ();
Soutput.range (27, 24) = s2_i.read ();
Soutput.range (23, 20) = s3_i.read ();
Soutput.range (19, 16) = s4_i.read ();
Soutput.range (15, 12) = s5_i.read ();
Soutput.range (11, 8) = s6_i.read ();
Soutput.range (7, 4) = s7_i.read ();
Soutput.range (3, 0) = s8_i.read ();
 
//P permutation
 
f[31] = Soutput[16];
f[30] = Soutput[25];
f[29] = Soutput[12];
f[28] = Soutput[11];
f[27] = Soutput[3];
f[26] = Soutput[20];
f[25] = Soutput[4];
f[24] = Soutput[15];
 
f[23] = Soutput[31];
f[22] = Soutput[17];
f[21] = Soutput[9];
f[20] = Soutput[6];
f[19] = Soutput[27];
f[18] = Soutput[14];
f[17] = Soutput[1];
f[16] = Soutput[22];
 
f[15] = Soutput[30];
f[14] = Soutput[24];
f[13] = Soutput[8];
f[12] = Soutput[18];
f[11] = Soutput[0];
f[10] = Soutput[5];
f[9] = Soutput[29];
f[8] = Soutput[23];
 
f[7] = Soutput[13];
f[6] = Soutput[19];
f[5] = Soutput[2];
f[4] = Soutput[26];
f[3] = Soutput[10];
f[2] = Soutput[21];
f[1] = Soutput[28];
f[0] = Soutput[7];
 
next_R.write (L_i.read () ^ f);
 
expanRSig.write (L_i.read () ^ f);
 
}
/systemcdes/trunk/rtl/systemc/s5.cpp
0,0 → 1,252
//////////////////////////////////////////////////////////////////////
//// ////
//// SBOX 5 ////
//// ////
//// This file is part of the SystemC DES ////
//// ////
//// Description: ////
//// Sbox of DES algorithm ////
//// ////
//// To Do: ////
//// - done ////
//// ////
//// Author(s): ////
//// - Javier Castillo, jcastilo@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2004/07/05 17:31:18 jcastillo
// First import
//
 
#include "s5.h"
 
void
s5::s5_box ()
{
switch (stage1_input.read ())
{
case 0:
stage1_output.write (2);
break;
case 1:
stage1_output.write (14);
break;
case 2:
stage1_output.write (12);
break;
case 3:
stage1_output.write (11);
break;
case 4:
stage1_output.write (4);
break;
case 5:
stage1_output.write (2);
break;
case 6:
stage1_output.write (1);
break;
case 7:
stage1_output.write (12);
break;
case 8:
stage1_output.write (7);
break;
case 9:
stage1_output.write (4);
break;
case 10:
stage1_output.write (10);
break;
case 11:
stage1_output.write (7);
break;
case 12:
stage1_output.write (11);
break;
case 13:
stage1_output.write (13);
break;
case 14:
stage1_output.write (6);
break;
case 15:
stage1_output.write (1);
break;
case 16:
stage1_output.write (8);
break;
case 17:
stage1_output.write (5);
break;
case 18:
stage1_output.write (5);
break;
case 19:
stage1_output.write (0);
break;
case 20:
stage1_output.write (3);
break;
case 21:
stage1_output.write (15);
break;
case 22:
stage1_output.write (15);
break;
case 23:
stage1_output.write (10);
break;
case 24:
stage1_output.write (13);
break;
case 25:
stage1_output.write (3);
break;
case 26:
stage1_output.write (0);
break;
case 27:
stage1_output.write (9);
break;
case 28:
stage1_output.write (14);
break;
case 29:
stage1_output.write (8);
break;
case 30:
stage1_output.write (9);
break;
case 31:
stage1_output.write (6);
break;
case 32:
stage1_output.write (4);
break;
case 33:
stage1_output.write (11);
break;
case 34:
stage1_output.write (2);
break;
case 35:
stage1_output.write (8);
break;
case 36:
stage1_output.write (1);
break;
case 37:
stage1_output.write (12);
break;
case 38:
stage1_output.write (11);
break;
case 39:
stage1_output.write (7);
break;
case 40:
stage1_output.write (10);
break;
case 41:
stage1_output.write (1);
break;
case 42:
stage1_output.write (13);
break;
case 43:
stage1_output.write (14);
break;
case 44:
stage1_output.write (7);
break;
case 45:
stage1_output.write (2);
break;
case 46:
stage1_output.write (8);
break;
case 47:
stage1_output.write (13);
break;
case 48:
stage1_output.write (15);
break;
case 49:
stage1_output.write (6);
break;
case 50:
stage1_output.write (9);
break;
case 51:
stage1_output.write (15);
break;
case 52:
stage1_output.write (12);
break;
case 53:
stage1_output.write (0);
break;
case 54:
stage1_output.write (5);
break;
case 55:
stage1_output.write (9);
break;
case 56:
stage1_output.write (6);
break;
case 57:
stage1_output.write (10);
break;
case 58:
stage1_output.write (3);
break;
case 59:
stage1_output.write (4);
break;
case 60:
stage1_output.write (0);
break;
case 61:
stage1_output.write (5);
break;
case 62:
stage1_output.write (14);
break;
case 63:
stage1_output.write (3);
break;
}
 
 
}
/systemcdes/trunk/rtl/systemc/s6.cpp
0,0 → 1,252
//////////////////////////////////////////////////////////////////////
//// ////
//// SBOX 6 ////
//// ////
//// This file is part of the SystemC DES ////
//// ////
//// Description: ////
//// Sbox of DES algorithm ////
//// ////
//// To Do: ////
//// - done ////
//// ////
//// Author(s): ////
//// - Javier Castillo, jcastilo@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2004/07/05 17:31:18 jcastillo
// First import
//
 
#include "s6.h"
 
void
s6::s6_box ()
{
switch (stage1_input.read ())
{
case 0:
stage1_output.write (12);
break;
case 1:
stage1_output.write (10);
break;
case 2:
stage1_output.write (1);
break;
case 3:
stage1_output.write (15);
break;
case 4:
stage1_output.write (10);
break;
case 5:
stage1_output.write (4);
break;
case 6:
stage1_output.write (15);
break;
case 7:
stage1_output.write (2);
break;
case 8:
stage1_output.write (9);
break;
case 9:
stage1_output.write (7);
break;
case 10:
stage1_output.write (2);
break;
case 11:
stage1_output.write (12);
break;
case 12:
stage1_output.write (6);
break;
case 13:
stage1_output.write (9);
break;
case 14:
stage1_output.write (8);
break;
case 15:
stage1_output.write (5);
break;
case 16:
stage1_output.write (0);
break;
case 17:
stage1_output.write (6);
break;
case 18:
stage1_output.write (13);
break;
case 19:
stage1_output.write (1);
break;
case 20:
stage1_output.write (3);
break;
case 21:
stage1_output.write (13);
break;
case 22:
stage1_output.write (4);
break;
case 23:
stage1_output.write (14);
break;
case 24:
stage1_output.write (14);
break;
case 25:
stage1_output.write (0);
break;
case 26:
stage1_output.write (7);
break;
case 27:
stage1_output.write (11);
break;
case 28:
stage1_output.write (5);
break;
case 29:
stage1_output.write (3);
break;
case 30:
stage1_output.write (11);
break;
case 31:
stage1_output.write (8);
break;
case 32:
stage1_output.write (9);
break;
case 33:
stage1_output.write (4);
break;
case 34:
stage1_output.write (14);
break;
case 35:
stage1_output.write (3);
break;
case 36:
stage1_output.write (15);
break;
case 37:
stage1_output.write (2);
break;
case 38:
stage1_output.write (5);
break;
case 39:
stage1_output.write (12);
break;
case 40:
stage1_output.write (2);
break;
case 41:
stage1_output.write (9);
break;
case 42:
stage1_output.write (8);
break;
case 43:
stage1_output.write (5);
break;
case 44:
stage1_output.write (12);
break;
case 45:
stage1_output.write (15);
break;
case 46:
stage1_output.write (3);
break;
case 47:
stage1_output.write (10);
break;
case 48:
stage1_output.write (7);
break;
case 49:
stage1_output.write (11);
break;
case 50:
stage1_output.write (0);
break;
case 51:
stage1_output.write (14);
break;
case 52:
stage1_output.write (4);
break;
case 53:
stage1_output.write (1);
break;
case 54:
stage1_output.write (10);
break;
case 55:
stage1_output.write (7);
break;
case 56:
stage1_output.write (1);
break;
case 57:
stage1_output.write (6);
break;
case 58:
stage1_output.write (13);
break;
case 59:
stage1_output.write (0);
break;
case 60:
stage1_output.write (11);
break;
case 61:
stage1_output.write (8);
break;
case 62:
stage1_output.write (6);
break;
case 63:
stage1_output.write (13);
break;
}
 
 
}
/systemcdes/trunk/rtl/systemc/s7.cpp
0,0 → 1,252
//////////////////////////////////////////////////////////////////////
//// ////
//// SBOX 7 ////
//// ////
//// This file is part of the SystemC DES ////
//// ////
//// Description: ////
//// Sbox of DES algorithm ////
//// ////
//// To Do: ////
//// - done ////
//// ////
//// Author(s): ////
//// - Javier Castillo, jcastilo@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2004/07/05 17:31:18 jcastillo
// First import
//
 
#include "s7.h"
 
void
s7::s7_box ()
{
switch (stage1_input.read ())
{
case 0:
stage1_output.write (4);
break;
case 1:
stage1_output.write (13);
break;
case 2:
stage1_output.write (11);
break;
case 3:
stage1_output.write (0);
break;
case 4:
stage1_output.write (2);
break;
case 5:
stage1_output.write (11);
break;
case 6:
stage1_output.write (14);
break;
case 7:
stage1_output.write (7);
break;
case 8:
stage1_output.write (15);
break;
case 9:
stage1_output.write (4);
break;
case 10:
stage1_output.write (0);
break;
case 11:
stage1_output.write (9);
break;
case 12:
stage1_output.write (8);
break;
case 13:
stage1_output.write (1);
break;
case 14:
stage1_output.write (13);
break;
case 15:
stage1_output.write (10);
break;
case 16:
stage1_output.write (3);
break;
case 17:
stage1_output.write (14);
break;
case 18:
stage1_output.write (12);
break;
case 19:
stage1_output.write (3);
break;
case 20:
stage1_output.write (9);
break;
case 21:
stage1_output.write (5);
break;
case 22:
stage1_output.write (7);
break;
case 23:
stage1_output.write (12);
break;
case 24:
stage1_output.write (5);
break;
case 25:
stage1_output.write (2);
break;
case 26:
stage1_output.write (10);
break;
case 27:
stage1_output.write (15);
break;
case 28:
stage1_output.write (6);
break;
case 29:
stage1_output.write (8);
break;
case 30:
stage1_output.write (1);
break;
case 31:
stage1_output.write (6);
break;
case 32:
stage1_output.write (1);
break;
case 33:
stage1_output.write (6);
break;
case 34:
stage1_output.write (4);
break;
case 35:
stage1_output.write (11);
break;
case 36:
stage1_output.write (11);
break;
case 37:
stage1_output.write (13);
break;
case 38:
stage1_output.write (13);
break;
case 39:
stage1_output.write (8);
break;
case 40:
stage1_output.write (12);
break;
case 41:
stage1_output.write (1);
break;
case 42:
stage1_output.write (3);
break;
case 43:
stage1_output.write (4);
break;
case 44:
stage1_output.write (7);
break;
case 45:
stage1_output.write (10);
break;
case 46:
stage1_output.write (14);
break;
case 47:
stage1_output.write (7);
break;
case 48:
stage1_output.write (10);
break;
case 49:
stage1_output.write (9);
break;
case 50:
stage1_output.write (15);
break;
case 51:
stage1_output.write (5);
break;
case 52:
stage1_output.write (6);
break;
case 53:
stage1_output.write (0);
break;
case 54:
stage1_output.write (8);
break;
case 55:
stage1_output.write (15);
break;
case 56:
stage1_output.write (0);
break;
case 57:
stage1_output.write (14);
break;
case 58:
stage1_output.write (5);
break;
case 59:
stage1_output.write (2);
break;
case 60:
stage1_output.write (9);
break;
case 61:
stage1_output.write (3);
break;
case 62:
stage1_output.write (2);
break;
case 63:
stage1_output.write (12);
break;
}
 
 
}
/systemcdes/trunk/rtl/systemc/s8.cpp
0,0 → 1,253
//////////////////////////////////////////////////////////////////////
//// ////
//// SBOX 8 ////
//// ////
//// This file is part of the SystemC DES ////
//// ////
//// Description: ////
//// Sbox of DES algorithm ////
//// ////
//// To Do: ////
//// - done ////
//// ////
//// Author(s): ////
//// - Javier Castillo, jcastilo@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2004/07/05 17:31:18 jcastillo
// First import
//
 
 
#include "s8.h"
 
 
void
s8::s8_box ()
{
switch (stage1_input.read ())
{
case 0:
stage1_output.write (13);
break;
case 1:
stage1_output.write (1);
break;
case 2:
stage1_output.write (2);
break;
case 3:
stage1_output.write (15);
break;
case 4:
stage1_output.write (8);
break;
case 5:
stage1_output.write (13);
break;
case 6:
stage1_output.write (4);
break;
case 7:
stage1_output.write (8);
break;
case 8:
stage1_output.write (6);
break;
case 9:
stage1_output.write (10);
break;
case 10:
stage1_output.write (15);
break;
case 11:
stage1_output.write (3);
break;
case 12:
stage1_output.write (11);
break;
case 13:
stage1_output.write (7);
break;
case 14:
stage1_output.write (1);
break;
case 15:
stage1_output.write (4);
break;
case 16:
stage1_output.write (10);
break;
case 17:
stage1_output.write (12);
break;
case 18:
stage1_output.write (9);
break;
case 19:
stage1_output.write (5);
break;
case 20:
stage1_output.write (3);
break;
case 21:
stage1_output.write (6);
break;
case 22:
stage1_output.write (14);
break;
case 23:
stage1_output.write (11);
break;
case 24:
stage1_output.write (5);
break;
case 25:
stage1_output.write (0);
break;
case 26:
stage1_output.write (0);
break;
case 27:
stage1_output.write (14);
break;
case 28:
stage1_output.write (12);
break;
case 29:
stage1_output.write (9);
break;
case 30:
stage1_output.write (7);
break;
case 31:
stage1_output.write (2);
break;
case 32:
stage1_output.write (7);
break;
case 33:
stage1_output.write (2);
break;
case 34:
stage1_output.write (11);
break;
case 35:
stage1_output.write (1);
break;
case 36:
stage1_output.write (4);
break;
case 37:
stage1_output.write (14);
break;
case 38:
stage1_output.write (1);
break;
case 39:
stage1_output.write (7);
break;
case 40:
stage1_output.write (9);
break;
case 41:
stage1_output.write (4);
break;
case 42:
stage1_output.write (12);
break;
case 43:
stage1_output.write (10);
break;
case 44:
stage1_output.write (14);
break;
case 45:
stage1_output.write (8);
break;
case 46:
stage1_output.write (2);
break;
case 47:
stage1_output.write (13);
break;
case 48:
stage1_output.write (0);
break;
case 49:
stage1_output.write (15);
break;
case 50:
stage1_output.write (6);
break;
case 51:
stage1_output.write (12);
break;
case 52:
stage1_output.write (10);
break;
case 53:
stage1_output.write (9);
break;
case 54:
stage1_output.write (13);
break;
case 55:
stage1_output.write (0);
break;
case 56:
stage1_output.write (15);
break;
case 57:
stage1_output.write (3);
break;
case 58:
stage1_output.write (3);
break;
case 59:
stage1_output.write (5);
break;
case 60:
stage1_output.write (5);
break;
case 61:
stage1_output.write (6);
break;
case 62:
stage1_output.write (8);
break;
case 63:
stage1_output.write (11);
break;
}
 
}
/systemcdes/trunk/rtl/systemc/Makefile
0,0 → 1,14
TARGET_ARCH = linux
 
CC = g++
OPT = -O3
DEBUG = -g
OTHER = -Wall -Wno-deprecated
EXTRA_CFLAGS = $(OPT) $(OTHER)
# EXTRA_CFLAGS = $(DEBUG) $(OTHER)
 
MODULE = des
SRCS = s1.cpp s2.cpp s3.cpp s4.cpp s5.cpp s6.cpp s7.cpp s8.cpp key_gen.cpp round.cpp des.cpp stimulus.cpp main.cpp
OBJS = $(SRCS:.cpp=.o)
 
include Makefile.defs
/systemcdes/trunk/rtl/systemc/Makefile.defs
0,0 → 1,35
## Variable that points to SystemC installation path
SYSTEMC = $(SYSTEMC_HOME)
SCV = $(SCV_HOME)
INCDIR = -I. -I.. -I../../bench -I$(SYSTEMC)/include -I$(SCV)/include
LIBDIR = -L. -L.. -L$(SYSTEMC)/lib-$(TARGET_ARCH) -L$(SCV)/lib-$(TARGET_ARCH)
 
# Build with maximum gcc warning level
CFLAGS = $(PLATFORM_SPECIFIC_FLAGS) $(EXTRA_CFLAGS)
 
LIBS = -lm -lsystemc -lscv $(EXTRA_LIBS)
 
EXE = $(MODULE).x
 
.SUFFIXES: .cpp .cc .o .x
 
$(EXE): $(OBJS) $(SYSTEMC)/lib-$(TARGET_ARCH)/libsystemc.a $(SCV)/lib-$(TARGET_ARCH)/libscv.a
$(CC) $(CFLAGS) $(INCDIR) $(LIBDIR) -o $@ $(OBJS) $(LIBS) $(SYSTEMC)/lib-$(TARGET_ARCH)/libsystemc.a $(SCV)/lib-$(TARGET_ARCH)/libscv.a 2>&1 | c++filt
 
.cpp.o:
$(CC) $(CFLAGS) $(INCDIR) -c $< $(USB_FLAGS)
 
.cc.o:
$(CC) $(CFLAGS) $(INCDIR) -c $< $(USB_FLAGS)
 
clean::
rm -f $(OBJS) *~ $(EXE)
 
ultraclean: clean
rm -f Makefile.deps
 
Makefile.deps:
$(CC) $(CFLAGS) $(INCDIR) -M $(SRCS) >> Makefile.deps
 
#include Makefile.deps
/systemcdes/trunk/bench/systemc/adapt.h
0,0 → 1,77
//////////////////////////////////////////////////////////////////////
//// ////
//// sc_fifo to sc_signal adapter ////
//// ////
//// This file is part of the SystemC DES ////
//// ////
//// To Do: ////
//// - done ////
//// ////
//// Author(s): ////
//// - Javier Castillo, jcastilo@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2004/08/30 16:55:54 jcastillo
// Used indent command on C code
//
// Revision 1.1.1.1 2004/07/05 17:31:18 jcastillo
// First import
//
 
#include "systemc.h"
 
SC_MODULE (adapter)
{
 
sc_in < bool > clk;
sc_in < bool > rt_ready_i;
sc_in < sc_uint < 64 > >rt_des_data_i;
 
sc_fifo_out < sc_uint < 64 > >rt_des_data_o;
 
void adapt ()
{
 
while (1)
{
wait (clk->posedge_event ());
if (rt_ready_i.read ())
rt_des_data_o.write (rt_des_data_i.read ());
}
 
}
 
SC_CTOR (adapter)
{
SC_THREAD (adapt);
}
};
/systemcdes/trunk/bench/systemc/desmodel.h
0,0 → 1,125
//////////////////////////////////////////////////////////////////////
//// ////
//// DES C behavioral model ////
//// ////
//// This file is part of the SystemC DES ////
//// ////
//// Description: ////
//// C behavioral model used as golden model ////
//// ////
//// To Do: ////
//// - done ////
//// ////
//// Author(s): ////
//// - Javier Castillo, jcastilo@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2004/08/30 16:55:54 jcastillo
// Used indent command on C code
//
// Revision 1.1.1.1 2004/07/05 17:31:18 jcastillo
// First import
//
 
#include "systemc.h"
 
void decrypt_des (unsigned char *block, unsigned char *block_o,
unsigned char *key);
void encrypt_des (unsigned char *block, unsigned char *block_o,
unsigned char *key);
 
SC_MODULE (desmodel)
{
 
sc_fifo_in < bool > decrypt;
sc_fifo_in < sc_uint < 64 > >des_key_i;
sc_fifo_in < sc_uint < 64 > >des_data_i;
 
sc_fifo_out < sc_uint < 64 > >des_data_o;
 
void des_thread ()
{
unsigned char des_key[8], des_data[8], des_out[8];
sc_uint < 64 > des_key_i_var, des_data_i_var, des_data_o_var;
 
while (1)
{
 
des_data_i_var = des_data_i.read ();
des_key_i_var = des_key_i.read ();
 
//Convert a sc_uint<64> to an array of 8 char
des_key[0] = des_key_i_var.range (63, 56);
des_key[1] = des_key_i_var.range (55, 48);
des_key[2] = des_key_i_var.range (47, 40);
des_key[3] = des_key_i_var.range (39, 32);
des_key[4] = des_key_i_var.range (31, 24);
des_key[5] = des_key_i_var.range (23, 16);
des_key[6] = des_key_i_var.range (15, 8);
des_key[7] = des_key_i_var.range (7, 0);
 
des_data[0] = des_data_i_var.range (63, 56);
des_data[1] = des_data_i_var.range (55, 48);
des_data[2] = des_data_i_var.range (47, 40);
des_data[3] = des_data_i_var.range (39, 32);
des_data[4] = des_data_i_var.range (31, 24);
des_data[5] = des_data_i_var.range (23, 16);
des_data[6] = des_data_i_var.range (15, 8);
des_data[7] = des_data_i_var.range (7, 0);
 
if (!decrypt.read ())
encrypt_des (des_data, des_out, des_key);
else
decrypt_des (des_data, des_out, des_key);
 
des_data_o_var.range (63, 56) = des_out[0];
des_data_o_var.range (55, 48) = des_out[1];
des_data_o_var.range (47, 40) = des_out[2];
des_data_o_var.range (39, 32) = des_out[3];
des_data_o_var.range (31, 24) = des_out[4];
des_data_o_var.range (23, 16) = des_out[5];
des_data_o_var.range (15, 8) = des_out[6];
des_data_o_var.range (7, 0) = des_out[7];
 
des_data_o.write (des_data_o_var);
}
}
 
 
 
SC_CTOR (desmodel)
{
 
SC_THREAD (des_thread);
 
}
};
/systemcdes/trunk/bench/systemc/main.cpp
0,0 → 1,141
//////////////////////////////////////////////////////////////////////
//// ////
//// Main simulation file ////
//// ////
//// This file is part of the SystemC DES ////
//// ////
//// Description: ////
//// Simulation file for DES project ////
//// ////
//// To Do: ////
//// - nothing ////
//// ////
//// Author(s): ////
//// - Javier Castillo, jcastilo@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2004/08/30 16:55:54 jcastillo
// Used indent command on C code
//
// Revision 1.1.1.1 2004/07/05 17:31:18 jcastillo
// First import
//
 
 
#include "systemc.h"
#include "iostream.h"
#include "des.h"
#include "desfunctions.h"
#include "desmodel.h"
#include "stimulus.h"
#include "adapt.h"
#include "checker.h"
 
int
sc_main (int argc, char *argv[])
{
 
sc_clock clk ("clk", 20);
 
test *t;
des_transactor *tr;
des *de1;
desmodel *dm1;
adapter *ad1;
checker *ch1;
 
t = new test ("testbench");
tr = new des_transactor ("des_transactor");
dm1 = new desmodel ("des_C_model");
de1 = new des ("des");
ad1 = new adapter ("adapter");
ch1 = new checker ("checker");
 
t->transactor (*tr);
 
sc_signal < bool > reset;
sc_signal < bool > rt_load;
sc_signal < bool > rt_decrypt;
sc_signal < sc_uint < 64 > >rt_data_i;
sc_signal < sc_uint < 64 > >rt_key;
 
sc_signal < sc_uint < 64 > >rt_data_o;
sc_signal < bool > rt_ready;
 
sc_fifo < sc_uint < 64 > >rt_des_data_ck;
sc_fifo < sc_uint < 64 > >c_des_data_ck;
 
sc_fifo < bool > c_decrypt;
sc_fifo < sc_uint < 64 > >c_key;
sc_fifo < sc_uint < 64 > >c_data;
 
ch1->reset (reset);
ch1->rt_des_data_i (rt_des_data_ck);
ch1->c_des_data_i (c_des_data_ck);
 
ad1->clk (clk);
ad1->rt_ready_i (rt_ready);
ad1->rt_des_data_i (rt_data_o);
ad1->rt_des_data_o (rt_des_data_ck);
 
dm1->decrypt (c_decrypt);
dm1->des_key_i (c_key);
dm1->des_data_i (c_data);
dm1->des_data_o (c_des_data_ck);
 
de1->clk (clk);
de1->reset (reset);
de1->load_i (rt_load);
de1->decrypt_i (rt_decrypt);
de1->data_i (rt_data_i);
de1->key_i (rt_key);
de1->data_o (rt_data_o);
de1->ready_o (rt_ready);
 
tr->clk (clk);
tr->reset (reset);
//Ports to RT model
tr->rt_load_o (rt_load);
tr->rt_decrypt_o (rt_decrypt);
tr->rt_des_data_o (rt_data_i);
tr->rt_des_key_o (rt_key);
tr->rt_des_ready_i (rt_ready);
//Ports to C model
tr->c_decrypt_o (c_decrypt);
tr->c_des_key_o (c_key);
tr->c_des_data_o (c_data);
 
sc_start (-1);
 
return 0;
 
}
/systemcdes/trunk/bench/systemc/stimulus.cpp
0,0 → 1,95
//////////////////////////////////////////////////////////////////////
//// ////
//// Random stimulus generation ////
//// ////
//// This file is part of the SystemC DES ////
//// ////
//// Description: ////
//// DES random stimulus ////
//// ////
//// To Do: ////
//// - nothing ////
//// ////
//// Author(s): ////
//// - Javier Castillo, jcastilo@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2004/08/30 16:55:54 jcastillo
// Used indent command on C code
//
// Revision 1.1.1.1 2004/07/05 17:31:18 jcastillo
// First import
//
 
 
 
 
#include "stimulus.h"
 
void
test::tb ()
{
 
sc_uint < 64 > des_key_var, des_data_var;
bool decrypt_var;
 
scv_random::set_global_seed (53246);
 
random_generator rg ("random_generator");
 
transactor->resetea ();
 
while (1)
{
 
rg.des_key->next ();
rg.des_data->next ();
rg.decrypt->next ();
 
 
des_data_var = *(rg.des_data);
des_key_var = *(rg.des_key);
decrypt_var = *(rg.decrypt);
 
if (!decrypt_var)
{
cout << "Encrypt: 0x" << (int) des_data_var.range (63,32) << (int)des_data_var.range (31,0) << " 0x" << (int) des_key_var.range (63,32) << (int) des_key_var.range (31,0) << " " << sc_time_stamp () << endl;
transactor->encrypt (des_data_var, des_key_var);
}
else
{
cout << "Decrypt: 0x" << (int) des_data_var.range (63,32) << (int)des_data_var.range (31,0) << " 0x" << (int) des_key_var.range (63,32) << (int) des_key_var.range (31,0) << " " << sc_time_stamp () << endl;
transactor->decrypt (des_data_var, des_key_var);
}
}
 
}
/systemcdes/trunk/bench/systemc/transactor.h
0,0 → 1,165
//////////////////////////////////////////////////////////////////////
//// ////
//// Transactor for AES ramdom verification ////
//// ////
//// This file is part of the SystemC DES ////
//// ////
//// Description: ////
//// Transactor acording to TLM for SystemC DES project ////
//// ////
//// To Do: ////
//// - nothing ////
//// ////
//// Author(s): ////
//// - Javier Castillo, jcastilo@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2004/08/30 16:55:54 jcastillo
// Used indent command on C code
//
// Revision 1.1.1.1 2004/07/05 17:31:18 jcastillo
// First import
//
 
#include "systemc.h"
 
class transactor_ports:public sc_module
{
public:
 
// Ports
sc_in < bool > clk;
sc_out < bool > reset;
 
//Ports to RT model
sc_out < bool > rt_load_o;
sc_out < bool > rt_decrypt_o;
sc_out < sc_uint < 64 > >rt_des_data_o;
sc_out < sc_uint < 64 > >rt_des_key_o;
sc_in < bool > rt_des_ready_i;
 
//Ports to C model
sc_fifo_out < bool > c_decrypt_o;
sc_fifo_out < sc_uint < 64 > >c_des_key_o;
sc_fifo_out < sc_uint < 64 > >c_des_data_o;
 
};
 
 
class rw_task_if:virtual public sc_interface
{
 
public:
//Funciones para el transactor
virtual void resetea (void) = 0;
virtual void encrypt (sc_uint < 64 > data, sc_uint < 64 > key) = 0;
virtual void decrypt (sc_uint < 64 > data, sc_uint < 64 > key) = 0;
virtual void wait_cycles (int cycles) = 0;
 
};
 
 
//Transactor
class des_transactor:public rw_task_if, public transactor_ports
{
 
public:
 
SC_CTOR (des_transactor)
{
 
cout.unsetf (ios::dec);
cout.setf (ios::hex);
 
}
 
 
void resetea (void)
{
reset.write (0);
wait (clk->posedge_event ());
reset.write (1);
cout << "Reseted" << endl;
}
 
void encrypt (sc_uint < 64 > data, sc_uint < 64 > key)
{
 
wait (clk->posedge_event ());
 
//To RT model
rt_load_o.write (1);
rt_des_data_o.write (data);
rt_des_key_o.write (key);
rt_decrypt_o.write (0);
 
//To C model through fifos
c_des_data_o.write (data);
c_des_key_o.write (key);
c_decrypt_o.write (0);
 
wait (clk->posedge_event ());
rt_load_o.write (0);
wait (rt_des_ready_i->posedge_event ());
}
 
void decrypt (sc_uint < 64 > data, sc_uint < 64 > key)
{
 
wait (clk->posedge_event ());
 
//To RT model
rt_load_o.write (1);
rt_des_data_o.write (data);
rt_des_key_o.write (key);
rt_decrypt_o.write (1);
 
//To C model through fifos
c_des_data_o.write (data);
c_des_key_o.write (key);
c_decrypt_o.write (1);
 
wait (clk->posedge_event ());
rt_load_o.write (0);
wait (rt_des_ready_i->posedge_event ());
 
}
 
void wait_cycles (int cycles)
{
for (int i = 0; i < cycles; i++)
{
wait (clk->posedge_event ());
}
}
 
};
/systemcdes/trunk/bench/systemc/checker.h
0,0 → 1,96
//////////////////////////////////////////////////////////////////////
//// ////
//// Checker ////
//// ////
//// This file is part of the SystemC DES ////
//// ////
//// Description: ////
//// Check that the outputs from the RTL model and the C model ////
//// used as golden model are the same ////
//// ////
//// To Do: ////
//// - done ////
//// ////
//// Author(s): ////
//// - Javier Castillo, jcastilo@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2004/08/30 16:55:54 jcastillo
// Used indent command on C code
//
// Revision 1.1.1.1 2004/07/05 17:31:18 jcastillo
// First import
//
 
 
#include "systemc.h"
 
SC_MODULE (checker)
{
 
sc_in < bool > reset;
 
sc_fifo_in < sc_uint < 64 > >rt_des_data_i;
sc_fifo_in < sc_uint < 64 > >c_des_data_i;
 
void check ()
{
sc_uint < 64 > rt_data_var, c_data_var;
 
wait (reset->posedge_event ());
 
while (1)
{
if (reset.read ())
{
rt_data_var = rt_des_data_i.read ();
c_data_var = c_des_data_i.read ();
if (rt_data_var != c_data_var)
{
cout << "Simulation mismatch: 0x" << (int) rt_data_var.range (63, 32) << (int) rt_data_var.range (31,0) << " 0x" << (int) c_data_var.range (63,32) << (int) c_data_var.range (31,0) <<" " << sc_time_stamp () << endl;
exit (0);
}
else
{
cout << "OK: 0x" << (int) rt_data_var.range (63,32) << (int)rt_data_var.range (31,0) << " 0x" << (int) c_data_var.range (63, 32) << (int) c_data_var.range (31,0) << " " << sc_time_stamp () << endl;
}
}
else
wait (reset->posedge_event ());
}
}
 
SC_CTOR (checker)
{
SC_THREAD (check);
}
};
/systemcdes/trunk/bench/systemc/desfunctions.h
0,0 → 1,461
//////////////////////////////////////////////////////////////////////
//// ////
//// DES C encrypt and decrypt functions for C golden model ////
//// ////
//// This file is part of the SystemC DES ////
//// ////
//// Description: ////
//// DES C encrypt and decrypt functions for C golden model ////
//// ////
//// To Do: ////
//// - done ////
//// ////
//// Author(s): ////
//// - Javier Castillo, jcastilo@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2004/08/30 16:55:54 jcastillo
// Used indent command on C code
//
// Revision 1.1.1.1 2004/07/05 17:31:18 jcastillo
// First import
//
 
 
 
unsigned int P[] = { 16, 7, 20, 21,
29, 12, 28, 17,
1, 15, 23, 26,
5, 18, 31, 10,
2, 8, 24, 14,
32, 27, 3, 9,
19, 13, 30, 6,
22, 11, 4, 25
};
 
unsigned int IP[] = { 58, 50, 42, 34, 26, 18, 10, 2,
60, 52, 44, 36, 28, 20, 12, 4,
62, 54, 46, 38, 30, 22, 14, 6,
64, 56, 48, 40, 32, 24, 16, 8,
57, 49, 41, 33, 25, 17, 9, 1,
59, 51, 43, 35, 27, 19, 11, 3,
61, 53, 45, 37, 29, 21, 13, 5,
63, 55, 47, 39, 31, 23, 15, 7
};
 
unsigned int IP_1[] = { 40, 8, 48, 16, 56, 24, 64, 32,
39, 7, 47, 15, 55, 23, 63, 31,
38, 6, 46, 14, 54, 22, 62, 30,
37, 5, 45, 13, 53, 21, 61, 29,
36, 4, 44, 12, 52, 20, 60, 28,
35, 3, 43, 11, 51, 19, 59, 27,
34, 2, 42, 10, 50, 18, 58, 26,
33, 1, 41, 9, 49, 17, 57, 25
};
 
unsigned int PC_1[] = { 57, 49, 41, 33, 25, 17, 9,
1, 58, 50, 42, 34, 26, 18,
10, 2, 59, 51, 43, 35, 27,
19, 11, 3, 60, 52, 44, 36,
63, 55, 47, 39, 31, 23, 15,
7, 62, 54, 46, 38, 30, 22,
14, 6, 61, 53, 45, 37, 29,
21, 13, 5, 28, 20, 12, 4
};
 
unsigned int PC_2[] = { 14, 17, 11, 24, 1, 5,
3, 28, 15, 6, 21, 10,
23, 19, 12, 4, 26, 8,
16, 7, 27, 20, 13, 2,
41, 52, 31, 37, 47, 55,
30, 40, 51, 45, 33, 48,
44, 49, 39, 56, 34, 53,
46, 42, 50, 36, 29, 32
};
 
unsigned int E[] = { 32, 1, 2, 3, 4, 5,
4, 5, 6, 7, 8, 9,
8, 9, 10, 11, 12, 13,
12, 13, 14, 15, 16, 17,
16, 17, 18, 19, 20, 21,
20, 21, 22, 23, 24, 25,
24, 25, 26, 27, 28, 29,
28, 29, 30, 31, 32, 1
};
 
unsigned int key_shifts[] =
{ 1, 1, 2, 2, 2, 2, 2, 2, 1, 2, 2, 2, 2, 2, 2, 1 };
 
unsigned int rotate_C_1[] = { 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 1, 29, 30, 31, 32
};
 
unsigned int rotate_C_2[] = { 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 1, 2, 29, 30, 31, 32
};
 
unsigned int rotate_D_1[] =
{ 1, 2, 3, 4, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21,
22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 5
};
 
unsigned int rotate_D_2[] =
{ 1, 2, 3, 4, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21,
22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 5, 6
};
 
unsigned int S1[] = { 14, 4, 13, 1, 2, 15, 11, 8, 3, 10, 6, 12, 5, 9, 0, 7,
0, 15, 7, 4, 14, 2, 13, 1, 10, 6, 12, 11, 9, 5, 3, 8,
4, 1, 14, 8, 13, 6, 2, 11, 15, 12, 9, 7, 3, 10, 5, 0,
15, 12, 8, 2, 4, 9, 1, 7, 5, 11, 3, 14, 10, 0, 6, 13
};
 
unsigned int S2[] = { 15, 1, 8, 14, 6, 11, 3, 4, 9, 7, 2, 13, 12, 0, 5, 10,
3, 13, 4, 7, 15, 2, 8, 14, 12, 0, 1, 10, 6, 9, 11, 5,
0, 14, 7, 11, 10, 4, 13, 1, 5, 8, 12, 6, 9, 3, 2, 15,
13, 8, 10, 1, 3, 15, 4, 2, 11, 6, 7, 12, 0, 5, 14, 9
};
 
unsigned int S3[] = { 10, 0, 9, 14, 6, 3, 15, 5, 1, 13, 12, 7, 11, 4, 2, 8,
13, 7, 0, 9, 3, 4, 6, 10, 2, 8, 5, 14, 12, 11, 15, 1,
13, 6, 4, 9, 8, 15, 3, 0, 11, 1, 2, 12, 5, 10, 14, 7,
1, 10, 13, 0, 6, 9, 8, 7, 4, 15, 14, 3, 11, 5, 2, 12
};
 
unsigned int S4[] = { 7, 13, 14, 3, 0, 6, 9, 10, 1, 2, 8, 5, 11, 12, 4, 15,
13, 8, 11, 5, 6, 15, 0, 3, 4, 7, 2, 12, 1, 10, 14, 9,
10, 6, 9, 0, 12, 11, 7, 13, 15, 1, 3, 14, 5, 2, 8, 4,
3, 15, 0, 6, 10, 1, 13, 8, 9, 4, 5, 11, 12, 7, 2, 14
};
 
unsigned int S5[] = { 2, 12, 4, 1, 7, 10, 11, 6, 8, 5, 3, 15, 13, 0, 14, 9,
14, 11, 2, 12, 4, 7, 13, 1, 5, 0, 15, 10, 3, 9, 8, 6,
4, 2, 1, 11, 10, 13, 7, 8, 15, 9, 12, 5, 6, 3, 0, 14,
11, 8, 12, 7, 1, 14, 2, 13, 6, 15, 0, 9, 10, 4, 5, 3
};
 
unsigned int S6[] = { 12, 1, 10, 15, 9, 2, 6, 8, 0, 13, 3, 4, 14, 7, 5, 11,
10, 15, 4, 2, 7, 12, 9, 5, 6, 1, 13, 14, 0, 11, 3, 8,
9, 14, 15, 5, 2, 8, 12, 3, 7, 0, 4, 10, 1, 13, 11, 6,
4, 3, 2, 12, 9, 5, 15, 10, 11, 14, 1, 7, 6, 0, 8, 13
};
 
unsigned int S7[] = { 4, 11, 2, 14, 15, 0, 8, 13, 3, 12, 9, 7, 5, 10, 6, 1,
13, 0, 11, 7, 4, 9, 1, 10, 14, 3, 5, 12, 2, 15, 8, 6,
1, 4, 11, 13, 12, 3, 7, 14, 10, 15, 6, 8, 0, 5, 9, 2,
6, 11, 13, 8, 1, 4, 10, 7, 9, 5, 0, 15, 14, 2, 3, 12
};
 
unsigned int S8[] = { 13, 2, 8, 4, 6, 15, 11, 1, 10, 9, 3, 14, 5, 0, 12, 7,
1, 15, 13, 8, 10, 3, 7, 4, 12, 5, 6, 11, 0, 14, 9, 2,
7, 11, 4, 1, 9, 12, 14, 2, 0, 6, 10, 13, 15, 3, 5, 8,
2, 1, 14, 7, 4, 10, 8, 13, 15, 12, 9, 0, 3, 5, 6, 11
};
 
 
void
apply_table (unsigned char *block, unsigned char *block_t, unsigned int *perm,
int outlength)
{
unsigned int i, byte, bit;
 
for (i = 0; i < outlength >> 3; i++)
block_t[i] = 0;
 
for (i = 0; i < outlength; i++)
{
byte = ((perm[i] - 1) >> 3); /*In which byte of the original block is the bit to permute */
bit = ((perm[i] - 1) & 7); /*In which pos of the byte is the bit to permute */
if ((block[byte] >> (7 - bit)) & 1 == 1)
block_t[i >> 3] += (0x80 >> (i & 7));
}
}
 
void
generate_key (unsigned char *previous_key, unsigned char *new_key,
int iteration)
{
/*Generates the next iteration non permuted key from the previous non-permuted key */
 
unsigned char Cx_rotated[4], Dx_rotated[4];
unsigned char Cx[4], Dx[4];
unsigned int i;
 
for (i = 0; i < 7; i++)
new_key[i] = 0;
 
 
/*We split the 56 bit key in two parts */
Cx[0] = previous_key[0];
Cx[1] = previous_key[1];
Cx[2] = previous_key[2];
Cx[3] = previous_key[3];
Dx[0] = previous_key[3];
Dx[1] = previous_key[4];
Dx[2] = previous_key[5];
Dx[3] = previous_key[6];
 
/*Rotate Cx and Dx */
if (key_shifts[iteration - 1] == 1)
{
apply_table (Cx, Cx_rotated, rotate_C_1, 32);
apply_table (Dx, Dx_rotated, rotate_D_1, 32);
}
else if (key_shifts[iteration - 1] == 2)
{
apply_table (Cx, Cx_rotated, rotate_C_2, 32);
apply_table (Dx, Dx_rotated, rotate_D_2, 32);
}
 
//binary_print(previous_key,7);
//binary_print(Cx_rotated,4);
//binary_print(Dx_rotated,4);
 
/*Recompose key */
new_key[0] = Cx_rotated[0];
new_key[1] = Cx_rotated[1];
new_key[2] = Cx_rotated[2];
new_key[3] = (Cx_rotated[3] & 0xF0);
 
new_key[3] += Dx_rotated[0] & 0xF;
new_key[4] = Dx_rotated[1];
new_key[5] = Dx_rotated[2];
new_key[6] = Dx_rotated[3];
 
//binary_print(new_key,7);
}
 
void
applyS (unsigned char *KER, unsigned char *KERS)
{
 
unsigned char aux;
int i;
unsigned short int row, col;
 
for (i = 0; i < 4; i++)
KERS[i] = 0;
 
/*Transform KER with S matrix */
row = ((KER[0] >> 2) & 1) + ((KER[0] & 0x80) >> 6);
aux = KER[0] << 1;
col = aux >> 4;
KERS[0] = S1[16 * row + col];
 
row = (KER[0] & 2) + ((KER[1] >> 4) & 1);
col = ((KER[0] & 1) << 3) + (KER[1] >> 5);
KERS[0] = (KERS[0] << 4) + S2[16 * row + col];
 
row = ((KER[1] >> 2) & 2) + ((KER[2] >> 6) & 1);
col = ((KER[1] & 7) << 1) + ((KER[2] & 0x80) >> 7);
KERS[1] = S3[16 * row + col];
 
row = ((KER[2] >> 4) & 2) + (KER[2] & 1);
col = (KER[2] >> 1) & 0xF;
KERS[1] = (KERS[1] << 4) + S4[16 * row + col];
 
row = ((KER[3] >> 2) & 1) + ((KER[3] & 0x80) >> 6);
aux = KER[3] << 1;
col = aux >> 4;
KERS[2] = S5[16 * row + col];
 
row = (KER[3] & 2) + ((KER[4] >> 4) & 1);
col = ((KER[3] & 1) << 3) + (KER[4] >> 5);
KERS[2] = (KERS[2] << 4) + S6[16 * row + col];
 
row = ((KER[4] >> 2) & 2) + ((KER[5] >> 6) & 1);
col = ((KER[4] & 7) << 1) + ((KER[5] & 0x80) >> 7);
KERS[3] = S7[16 * row + col];
 
row = ((KER[5] >> 4) & 2) + (KER[5] & 1);
col = (KER[5] >> 1) & 0xF;
KERS[3] = (KERS[3] << 4) + S8[16 * row + col];
 
}
 
void
encrypt_des (unsigned char *block, unsigned char *block_o, unsigned char *key)
{
 
unsigned char block_t[8];
unsigned char new_key[7], permuted_key[6], ER[6], last_key[7];
unsigned char KER[6];
unsigned char KERS[4]; /*32 bits after apply the S matrix */
unsigned char fKERS[4]; /*32 bits after apply the P matrix */
 
int i, j;
unsigned char b0_t, b1_t, b2_t, b3_t;
 
/*This is the main DES encrypt function
encrypt one block of 64 bits with a key of 64 bits */
 
/*First we generate the permuted key of 56 bits from the 64 bits one */
apply_table (key, last_key, PC_1, 7 * 8);
/*Now we have the K+ key of 56 bits */
 
/*We generate the first permuted block */
apply_table (block, block_t, IP, 8 * 8);
 
 
/*16 iterations */
for (i = 1; i < 17; i++)
{
generate_key (last_key, new_key, i);
for (j = 0; j < 7; j++)
last_key[j] = new_key[j];
apply_table (new_key, permuted_key, PC_2, 6 * 8);
 
/*We now calculate f(R,K) */
/*Compute E(R0) */
apply_table (block_t + 4, ER, E, 6 * 8);
/*Key XOR ER */
for (j = 0; j < 6; j++)
KER[j] = ER[j] ^ permuted_key[j];
 
applyS (KER, KERS);
apply_table (KERS, fKERS, P, 4 * 8);
 
/*Make the aditions */
/*Li=Ri-1 */
b0_t = block_t[0];
b1_t = block_t[1];
b2_t = block_t[2];
b3_t = block_t[3];
block_t[0] = block_t[4];
block_t[1] = block_t[5];
block_t[2] = block_t[6];
block_t[3] = block_t[7];
/*Ri=Li-1+fKERS */
block_t[4] = b0_t ^ fKERS[0];
block_t[5] = b1_t ^ fKERS[1];
block_t[6] = b2_t ^ fKERS[2];
block_t[7] = b3_t ^ fKERS[3];
}
/*Recolocate L and R */
b0_t = block_t[0];
b1_t = block_t[1];
b2_t = block_t[2];
b3_t = block_t[3];
block_t[0] = block_t[4];
block_t[1] = block_t[5];
block_t[2] = block_t[6];
block_t[3] = block_t[7];
block_t[4] = b0_t;
block_t[5] = b1_t;
block_t[6] = b2_t;
block_t[7] = b3_t;
 
/*Final permutation */
apply_table (block_t, block_o, IP_1, 8 * 8);
 
}
 
void
decrypt_des (unsigned char *block, unsigned char *block_o, unsigned char *key)
{
unsigned char block_t[8];
unsigned char new_key[7], permuted_key[6], ER[6], last_key[7];
unsigned char KER[6];
unsigned char KERS[4]; /*32 bits after apply the S matrix */
unsigned char fKERS[4]; /*32 bits after apply the P matrix */
unsigned char keys[16][6];
 
int i, j;
unsigned char b0_t, b1_t, b2_t, b3_t;
 
/*This is the main DES decrypt function
encrypt one block of 64 bits with a key of 64 bits */
 
/*First we generate the permuted key of 56 bits from the 64 bits one */
apply_table (key, last_key, PC_1, 7 * 8);
/*Now we have the K+ key of 56 bits */
 
/*We generate the first permuted block */
apply_table (block, block_t, IP, 8 * 8);
 
for (i = 1; i < 17; i++)
{
generate_key (last_key, new_key, i);
for (j = 0; j < 7; j++)
last_key[j] = new_key[j];
apply_table (new_key, permuted_key, PC_2, 6 * 8);
for (j = 0; j < 6; j++)
keys[i - 1][j] = permuted_key[j];
}
 
/*16 iterations */
for (i = 1; i < 17; i++)
{
/*We now calculate f(R,K) */
/*Compute E(R0) */
apply_table (block_t + 4, ER, E, 6 * 8);
/*Key XOR ER */
for (j = 0; j < 6; j++)
KER[j] = ER[j] ^ keys[15 - (i - 1)][j];
 
applyS (KER, KERS);
apply_table (KERS, fKERS, P, 4 * 8);
 
/*Make the aditions */
/*Li=Ri-1 */
b0_t = block_t[0];
b1_t = block_t[1];
b2_t = block_t[2];
b3_t = block_t[3];
block_t[0] = block_t[4];
block_t[1] = block_t[5];
block_t[2] = block_t[6];
block_t[3] = block_t[7];
/*Ri=Li-1+fKERS */
block_t[4] = b0_t ^ fKERS[0];
block_t[5] = b1_t ^ fKERS[1];
block_t[6] = b2_t ^ fKERS[2];
block_t[7] = b3_t ^ fKERS[3];
}
/*Recolocate L and R */
b0_t = block_t[0];
b1_t = block_t[1];
b2_t = block_t[2];
b3_t = block_t[3];
block_t[0] = block_t[4];
block_t[1] = block_t[5];
block_t[2] = block_t[6];
block_t[3] = block_t[7];
block_t[4] = b0_t;
block_t[5] = b1_t;
block_t[6] = b2_t;
block_t[7] = b3_t;
 
/*Final permutation */
apply_table (block_t, block_o, IP_1, 8 * 8);
 
}
/systemcdes/trunk/bench/systemc/stimulus.h
0,0 → 1,86
//////////////////////////////////////////////////////////////////////
//// ////
//// Random testbench declation ////
//// ////
//// This file is part of the SystemC DES ////
//// ////
//// Description: ////
//// Declare ramdom testbench class and data ////
//// ////
//// To Do: ////
//// - done ////
//// ////
//// Author(s): ////
//// - Javier Castillo, jcastilo@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2004/08/30 16:55:54 jcastillo
// Used indent command on C code
//
// Revision 1.1.1.1 2004/07/05 17:31:18 jcastillo
// First import
//
 
 
 
#include "transactor.h"
#include "scv.h"
 
//Random number generator
 
class random_generator:virtual public scv_constraint_base
{
public:
 
scv_smart_ptr < sc_uint < 64 > >des_key;
scv_smart_ptr < sc_uint < 64 > >des_data;
 
scv_smart_ptr < bool > decrypt;
 
SCV_CONSTRAINT_CTOR (random_generator)
{
}
};
 
class test:public sc_module
{
public:
 
sc_port < rw_task_if > transactor;
 
void tb ();
 
SC_CTOR (test)
{
SC_THREAD (tb);
}
};
/systemcdes/trunk/bench/systemc/README
0,0 → 1,4
This files are replicated in /rtl/systemc
 
 
jcastillo@opencores.org
/systemcdes/trunk/bench/verilog/des_test.v
0,0 → 1,133
//////////////////////////////////////////////////////////////////////
//// ////
//// Testbench for Verilog translation of SystemC DES ////
//// ////
//// This file is part of the SystemC DES ////
//// ////
//// Description: ////
//// DES testbench ////
//// ////
//// ////
//// To Do: ////
//// - Add more test cases ////
//// ////
//// Author(s): ////
//// - Javier Castillo, jcastilo@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2004/07/05 17:31:18 jcastillo
// First import
//
 
`timescale 10ns/1ns
 
module top;
 
 
 
reg clk, reset, load_i, decrypt_i;
reg [63:0] data_i, key_i;
wire [63:0] data_o;
wire ready_o;
 
reg [191:0] tmp;
reg [191:0] x[6:0];
integer ZZZ;
integer select;
 
 
des d1(clk,reset,load_i,decrypt_i,data_i,key_i,data_o,ready_o);
 
initial
 
begin
$display("\n\n");
$display("******************************************");
$display("* DES core simulation started ... *");
$display("******************************************");
$display("\n");
$display("Running\n");
clk = 'b1;
reset = 'b0;
@(posedge clk);
@(posedge clk);
reset = 'b1;
ZZZ=0;
//Decrypt
// Key Data
x[ZZZ]=192'h0cb76ea9864252f4_34ffd445a8f4e555_a1971ff745ad8b38; ZZZ=ZZZ+1;
x[ZZZ]=192'h0123456789ABCDEF_0000000000000000_14AAD7F4DBB4E094; ZZZ=ZZZ+1;
x[ZZZ]=192'h0000000000000000_123456789ABCDEF0_9D2A73F6A9070648; ZZZ=ZZZ+1;
x[ZZZ]=192'h23FE536344578A49_123456789ABCDEF0_F4E5D5EFAA638C43; ZZZ=ZZZ+1;
//Encrypt
x[ZZZ]=192'h0123456789ABCDEF_0000000000000000_D5D44FF720683D0D; ZZZ=ZZZ+1;
x[ZZZ]=192'h0000000000000000_123456789ABCDEF0_9D2A73F6A9070648; ZZZ=ZZZ+1;
x[ZZZ]=192'h23FE536344578A49_123456789ABCDEF0_1862EC2AA88BA258; ZZZ=ZZZ+1;
 
for(select=0;select<ZZZ;select=select+1)
begin
@(posedge clk);
load_i = 1'b0;
decrypt_i = !(select>3);
tmp=x[select];
key_i=tmp[191:128];
data_i=tmp[127:64];
load_i = #1 1'b1;
@(posedge clk);
load_i = #1 1'b0;
while(!ready_o) @(posedge clk);
//$display("Got %x", data_o);
if(data_o!=tmp[63:0])
$display("ERROR: (%0d) Expected %x Got %x", select, tmp[63:0], data_o);
end
$display("");
$display("**************************************");
$display("* DES Test done ... *");
$display("**************************************");
$display("");
 
$finish;
end
always #5 clk = !clk;
 
endmodule
systemcdes/trunk Property changes : Added: svn:mergeinfo ## -0,0 +0,0 ## Index: systemcdes/web_uploads =================================================================== --- systemcdes/web_uploads (nonexistent) +++ systemcdes/web_uploads (revision 11)
systemcdes/web_uploads Property changes : Added: svn:mergeinfo ## -0,0 +0,0 ## Index: systemcdes/branches =================================================================== --- systemcdes/branches (nonexistent) +++ systemcdes/branches (revision 11)
systemcdes/branches Property changes : Added: svn:mergeinfo ## -0,0 +0,0 ## Index: systemcdes/tags/V10/bench/systemc/adapt.h =================================================================== --- systemcdes/tags/V10/bench/systemc/adapt.h (nonexistent) +++ systemcdes/tags/V10/bench/systemc/adapt.h (revision 11) @@ -0,0 +1,67 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// sc_fifo to sc_signal adapter //// +//// //// +//// This file is part of the SystemC DES //// +//// //// +//// To Do: //// +//// - done //// +//// //// +//// Author(s): //// +//// - Javier Castillo, jcastilo@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ + +#include "systemc.h" + +SC_MODULE(adapter){ + + sc_in clk; + sc_in rt_ready_i; + sc_in > rt_des_data_i; + + sc_fifo_out > rt_des_data_o; + + void adapt(){ + + while(1){ + wait(clk->posedge_event()); + if(rt_ready_i.read()) + rt_des_data_o.write(rt_des_data_i.read()); + } + + } + + SC_CTOR(adapter){ + SC_THREAD(adapt); + } + }; Index: systemcdes/tags/V10/bench/systemc/desmodel.h =================================================================== --- systemcdes/tags/V10/bench/systemc/desmodel.h (nonexistent) +++ systemcdes/tags/V10/bench/systemc/desmodel.h (revision 11) @@ -0,0 +1,95 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// DES C behavioral model //// +//// //// +//// This file is part of the SystemC DES //// +//// //// +//// Description: //// +//// C behavioral model used as golden model //// +//// //// +//// To Do: //// +//// - done //// +//// //// +//// Author(s): //// +//// - Javier Castillo, jcastilo@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ + +#include "systemc.h" + +void decrypt_des(unsigned char *block, unsigned char *block_o, unsigned char *key); +void encrypt_des(unsigned char *block, unsigned char *block_o, unsigned char *key); + +SC_MODULE(desmodel){ + + sc_fifo_in decrypt; + sc_fifo_in > des_key_i; + sc_fifo_in > des_data_i; + + sc_fifo_out > des_data_o; + + void des_thread(){ + unsigned char des_key[8],des_data[8],des_out[8]; + sc_uint<64> des_key_i_var,des_data_i_var,des_data_o_var; + + while(1){ + + des_data_i_var=des_data_i.read(); + des_key_i_var=des_key_i.read(); + + //Convert a sc_uint<64> to an array of 8 char + des_key[0]=des_key_i_var.range(63,56);des_key[1]=des_key_i_var.range(55,48);des_key[2]=des_key_i_var.range(47,40);des_key[3]=des_key_i_var.range(39,32); + des_key[4]=des_key_i_var.range(31,24);des_key[5]=des_key_i_var.range(23,16);des_key[6]=des_key_i_var.range(15,8);des_key[7]=des_key_i_var.range(7,0); + + des_data[0]=des_data_i_var.range(63,56);des_data[1]=des_data_i_var.range(55,48);des_data[2]=des_data_i_var.range(47,40);des_data[3]=des_data_i_var.range(39,32); + des_data[4]=des_data_i_var.range(31,24);des_data[5]=des_data_i_var.range(23,16);des_data[6]=des_data_i_var.range(15,8);des_data[7]=des_data_i_var.range(7,0); + + if(!decrypt.read()) + encrypt_des(des_data,des_out,des_key); + else + decrypt_des(des_data,des_out,des_key); + + des_data_o_var.range(63,56)=des_out[0];des_data_o_var.range(55,48)=des_out[1];des_data_o_var.range(47,40)=des_out[2];des_data_o_var.range(39,32)=des_out[3]; + des_data_o_var.range(31,24)=des_out[4];des_data_o_var.range(23,16)=des_out[5];des_data_o_var.range(15,8)=des_out[6];des_data_o_var.range(7,0)=des_out[7]; + + des_data_o.write(des_data_o_var); + } + } + + + + SC_CTOR(desmodel){ + + SC_THREAD(des_thread); + + } +}; Index: systemcdes/tags/V10/bench/systemc/main.cpp =================================================================== --- systemcdes/tags/V10/bench/systemc/main.cpp (nonexistent) +++ systemcdes/tags/V10/bench/systemc/main.cpp (revision 11) @@ -0,0 +1,133 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Main simulation file //// +//// //// +//// This file is part of the SystemC DES //// +//// //// +//// Description: //// +//// Simulation file for DES project //// +//// //// +//// To Do: //// +//// - nothing //// +//// //// +//// Author(s): //// +//// - Javier Castillo, jcastilo@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ + + +#include "systemc.h" +#include "iostream.h" +#include "des.h" +#include "desfunctions.h" +#include "desmodel.h" +#include "stimulus.h" +#include "adapt.h" +#include "checker.h" + +int sc_main(int argc, char* argv[]){ + + sc_clock clk("clk",20); + + test *t; + des_transactor *tr; + des *de1; + desmodel *dm1; + adapter *ad1; + checker *ch1; + + t=new test("testbench"); + tr=new des_transactor("des_transactor"); + dm1=new desmodel("des_C_model"); + de1=new des("des"); + ad1=new adapter("adapter"); + ch1=new checker("checker"); + + t->transactor(*tr); + + sc_signal reset; + sc_signal rt_load; + sc_signal rt_decrypt; + sc_signal > rt_data_i; + sc_signal > rt_key; + + sc_signal > rt_data_o; + sc_signal rt_ready; + + sc_fifo > rt_des_data_ck; + sc_fifo > c_des_data_ck; + + sc_fifo c_decrypt; + sc_fifo > c_key; + sc_fifo > c_data; + + ch1->reset(reset); + ch1->rt_des_data_i(rt_des_data_ck); + ch1->c_des_data_i(c_des_data_ck); + + ad1->clk(clk); + ad1->rt_ready_i(rt_ready); + ad1->rt_des_data_i(rt_data_o); + ad1->rt_des_data_o(rt_des_data_ck); + + dm1->decrypt(c_decrypt); + dm1->des_key_i(c_key); + dm1->des_data_i(c_data); + dm1->des_data_o(c_des_data_ck); + + de1->clk(clk); + de1->reset(reset); + de1->load_i(rt_load); + de1->decrypt_i(rt_decrypt); + de1->data_i(rt_data_i); + de1->key_i(rt_key); + de1->data_o(rt_data_o); + de1->ready_o(rt_ready); + + tr->clk(clk); + tr->reset(reset); + //Ports to RT model + tr->rt_load_o(rt_load); + tr->rt_decrypt_o(rt_decrypt); + tr->rt_des_data_o(rt_data_i); + tr->rt_des_key_o(rt_key); + tr->rt_des_ready_i(rt_ready); + //Ports to C model + tr->c_decrypt_o(c_decrypt); + tr->c_des_key_o(c_key); + tr->c_des_data_o(c_data); + + sc_start(-1); + + return 0; + + } Index: systemcdes/tags/V10/bench/systemc/stimulus.cpp =================================================================== --- systemcdes/tags/V10/bench/systemc/stimulus.cpp (nonexistent) +++ systemcdes/tags/V10/bench/systemc/stimulus.cpp (revision 11) @@ -0,0 +1,83 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Random stimulus generation //// +//// //// +//// This file is part of the SystemC DES //// +//// //// +//// Description: //// +//// DES random stimulus //// +//// //// +//// To Do: //// +//// - nothing //// +//// //// +//// Author(s): //// +//// - Javier Castillo, jcastilo@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ + + + + +#include "stimulus.h" + +void test::tb(){ + + sc_uint<64> des_key_var,des_data_var; + bool decrypt_var; + + scv_random::set_global_seed(53246); + + random_generator rg("random_generator"); + + transactor->resetea(); + + while(1){ + + rg.des_key->next(); + rg.des_data->next(); + rg.decrypt->next(); + + + des_data_var=*(rg.des_data); + des_key_var=*(rg.des_key); + decrypt_var=*(rg.decrypt); + + if(!decrypt_var){ + cout << "Encrypt: 0x" << (int)des_data_var.range(63,32) << (int)des_data_var.range(31,0) << " 0x" << (int)des_key_var.range(63,32) << (int)des_key_var.range(31,0) << " " << sc_time_stamp() << endl; + transactor->encrypt(des_data_var,des_key_var); + }else{ + cout << "Decrypt: 0x" << (int)des_data_var.range(63,32) << (int)des_data_var.range(31,0) << " 0x" << (int)des_key_var.range(63,32) << (int)des_key_var.range(31,0) << " " << sc_time_stamp() << endl; + transactor->decrypt(des_data_var,des_key_var); + } + } + +} Index: systemcdes/tags/V10/bench/systemc/transactor.h =================================================================== --- systemcdes/tags/V10/bench/systemc/transactor.h (nonexistent) +++ systemcdes/tags/V10/bench/systemc/transactor.h (revision 11) @@ -0,0 +1,150 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Transactor for AES ramdom verification //// +//// //// +//// This file is part of the SystemC DES //// +//// //// +//// Description: //// +//// Transactor acording to TLM for SystemC DES project //// +//// //// +//// To Do: //// +//// - nothing //// +//// //// +//// Author(s): //// +//// - Javier Castillo, jcastilo@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ + +#include "systemc.h" + +class transactor_ports:public sc_module{ + public: + + // Ports + sc_in clk; + sc_out reset; + + //Ports to RT model + sc_out rt_load_o; + sc_out rt_decrypt_o; + sc_out > rt_des_data_o; + sc_out > rt_des_key_o; + sc_in rt_des_ready_i; + + //Ports to C model + sc_fifo_out c_decrypt_o; + sc_fifo_out > c_des_key_o; + sc_fifo_out > c_des_data_o; + +}; + + +class rw_task_if : virtual public sc_interface { + + public: + //Funciones para el transactor + virtual void resetea(void)=0; + virtual void encrypt(sc_uint<64> data, sc_uint<64> key)=0; + virtual void decrypt(sc_uint<64> data, sc_uint<64> key)=0; + virtual void wait_cycles(int cycles)=0; + +}; + + +//Transactor +class des_transactor:public rw_task_if,public transactor_ports { + + public: + + SC_CTOR(des_transactor){ + + cout.unsetf(ios::dec); + cout.setf(ios::hex); + + } + + + void resetea(void){ + reset.write(0); + wait(clk->posedge_event()); + reset.write(1); + cout << "Reseted" << endl; + } + + void encrypt(sc_uint<64> data, sc_uint<64> key){ + + wait(clk->posedge_event()); + + //To RT model + rt_load_o.write(1); + rt_des_data_o.write(data); + rt_des_key_o.write(key); + rt_decrypt_o.write(0); + + //To C model through fifos + c_des_data_o.write(data); + c_des_key_o.write(key); + c_decrypt_o.write(0); + + wait(clk->posedge_event()); + rt_load_o.write(0); + wait(rt_des_ready_i->posedge_event()); + } + + void decrypt(sc_uint<64> data, sc_uint<64> key){ + + wait(clk->posedge_event()); + + //To RT model + rt_load_o.write(1); + rt_des_data_o.write(data); + rt_des_key_o.write(key); + rt_decrypt_o.write(1); + + //To C model through fifos + c_des_data_o.write(data); + c_des_key_o.write(key); + c_decrypt_o.write(1); + + wait(clk->posedge_event()); + rt_load_o.write(0); + wait(rt_des_ready_i->posedge_event()); + + } + + void wait_cycles(int cycles){ + for(int i=0;iposedge_event()); + } + } + +}; Index: systemcdes/tags/V10/bench/systemc/checker.h =================================================================== --- systemcdes/tags/V10/bench/systemc/checker.h (nonexistent) +++ systemcdes/tags/V10/bench/systemc/checker.h (revision 11) @@ -0,0 +1,81 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Checker //// +//// //// +//// This file is part of the SystemC DES //// +//// //// +//// Description: //// +//// Check that the outputs from the RTL model and the C model //// +//// used as golden model are the same //// +//// //// +//// To Do: //// +//// - done //// +//// //// +//// Author(s): //// +//// - Javier Castillo, jcastilo@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ + + +#include "systemc.h" + +SC_MODULE(checker){ + + sc_in reset; + + sc_fifo_in > rt_des_data_i; + sc_fifo_in > c_des_data_i; + + void check(){ + sc_uint<64> rt_data_var,c_data_var; + + wait(reset->posedge_event()); + + while(1){ + if(reset.read()){ + rt_data_var=rt_des_data_i.read(); + c_data_var=c_des_data_i.read(); + if(rt_data_var!=c_data_var){ + cout << "Simulation mismatch: 0x" << (int)rt_data_var.range(63,32) << (int)rt_data_var.range(31,0) << " 0x" << (int)c_data_var.range(63,32) << (int)c_data_var.range(31,0) << " " << sc_time_stamp() << endl; + exit(0); + }else{ + cout << "OK: 0x" << (int)rt_data_var.range(63,32) << (int)rt_data_var.range(31,0) << " 0x" << (int)c_data_var.range(63,32) << (int)c_data_var.range(31,0) << " " << sc_time_stamp() << endl; + } + }else + wait(reset->posedge_event()); + } + } + + SC_CTOR(checker){ + SC_THREAD(check); + } + }; Index: systemcdes/tags/V10/bench/systemc/desfunctions.h =================================================================== --- systemcdes/tags/V10/bench/systemc/desfunctions.h (nonexistent) +++ systemcdes/tags/V10/bench/systemc/desfunctions.h (revision 11) @@ -0,0 +1,412 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// DES C encrypt and decrypt functions for C golden model //// +//// //// +//// This file is part of the SystemC DES //// +//// //// +//// Description: //// +//// DES C encrypt and decrypt functions for C golden model //// +//// //// +//// To Do: //// +//// - done //// +//// //// +//// Author(s): //// +//// - Javier Castillo, jcastilo@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ + + + +unsigned int P[]={16,7,20,21, + 29,12,28,17, + 1,15,23,26, + 5,18,31,10, + 2,8,24,14, + 32,27,3,9, + 19,13,30,6, + 22,11,4,25}; + +unsigned int IP[]={58,50,42,34,26,18,10,2, + 60,52,44,36,28,20,12,4, + 62,54,46,38,30,22,14,6, + 64,56,48,40,32,24,16,8, + 57,49,41,33,25,17,9,1, + 59,51,43,35,27,19,11,3, + 61,53,45,37,29,21,13,5, + 63,55,47,39,31,23,15,7}; + +unsigned int IP_1[]={40,8,48,16,56,24,64,32, + 39,7,47,15,55,23,63,31, + 38,6,46,14,54,22,62,30, + 37,5,45,13,53,21,61,29, + 36,4,44,12,52,20,60,28, + 35,3,43,11,51,19,59,27, + 34,2,42,10,50,18,58,26, + 33,1,41,9,49,17,57,25}; + +unsigned int PC_1[]={57,49,41,33,25,17,9, + 1,58,50,42,34,26,18, + 10,2,59,51,43,35,27, + 19,11,3,60,52,44,36, + 63,55,47,39,31,23,15, + 7,62,54,46,38,30,22, + 14,6,61,53,45,37,29, + 21,13,5,28,20,12,4}; + +unsigned int PC_2[]={14,17,11,24,1,5, + 3,28,15,6,21,10, + 23,19,12,4,26,8, + 16,7,27,20,13,2, + 41,52,31,37,47,55, + 30,40,51,45,33,48, + 44,49,39,56,34,53, + 46,42,50,36,29,32}; + +unsigned int E[]={32,1,2,3,4,5, + 4,5,6,7,8,9, + 8,9,10,11,12,13, + 12,13,14,15,16,17, + 16,17,18,19,20,21, + 20,21,22,23,24,25, + 24,25,26,27,28,29, + 28,29,30,31,32,1}; + +unsigned int key_shifts[]={1,1,2,2,2,2,2,2,1,2,2,2,2,2,2,1}; + +unsigned int rotate_C_1[]={2,3,4,5,6,7,8,9,10,11,12,13,14, + 15,16,17,18,19,20,21,22,23,24,25,26,27,28,1,29,30,31,32}; + +unsigned int rotate_C_2[]={3,4,5,6,7,8,9,10,11,12,13,14,15, + 16,17,18,19,20,21,22,23,24,25,26,27,28,1,2,29,30,31,32}; + +unsigned int rotate_D_1[]={1,2,3,4,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21, + 22,23,24,25,26,27,28,29,30,31,32,5}; + +unsigned int rotate_D_2[]={1,2,3,4,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21, + 22,23,24,25,26,27,28,29,30,31,32,5,6}; + +unsigned int S1[]={14,4,13,1,2,15,11,8,3,10,6,12,5,9,0,7, + 0,15,7,4,14,2,13,1,10,6,12,11,9,5,3,8, + 4,1,14,8,13,6,2,11,15,12,9,7,3,10,5,0, + 15,12,8,2,4,9,1,7,5,11,3,14,10,0,6,13}; + +unsigned int S2[]={15,1,8,14,6,11,3,4,9,7,2,13,12,0,5,10, + 3,13,4,7,15,2,8,14,12,0,1,10,6,9,11,5, + 0,14,7,11,10,4,13,1,5,8,12,6,9,3,2,15, + 13,8,10,1,3,15,4,2,11,6,7,12,0,5,14,9}; + +unsigned int S3[]={10,0,9,14,6,3,15,5,1,13,12,7,11,4,2,8, + 13,7,0,9,3,4,6,10,2,8,5,14,12,11,15,1, + 13,6,4,9,8,15,3,0,11,1,2,12,5,10,14,7, + 1,10,13,0,6,9,8,7,4,15,14,3,11,5,2,12}; + +unsigned int S4[]={7,13,14,3,0,6,9,10,1,2,8,5,11,12,4,15, + 13,8,11,5,6,15,0,3,4,7,2,12,1,10,14,9, + 10,6,9,0,12,11,7,13,15,1,3,14,5,2,8,4, + 3,15,0,6,10,1,13,8,9,4,5,11,12,7,2,14}; + +unsigned int S5[]={2,12,4,1,7,10,11,6,8,5,3,15,13,0,14,9, + 14,11,2,12,4,7,13,1,5,0,15,10,3,9,8,6, + 4,2,1,11,10,13,7,8,15,9,12,5,6,3,0,14, + 11,8,12,7,1,14,2,13,6,15,0,9,10,4,5,3}; + +unsigned int S6[]={12,1,10,15,9,2,6,8,0,13,3,4,14,7,5,11, + 10,15,4,2,7,12,9,5,6,1,13,14,0,11,3,8, + 9,14,15,5,2,8,12,3,7,0,4,10,1,13,11,6, + 4,3,2,12,9,5,15,10,11,14,1,7,6,0,8,13}; + +unsigned int S7[]={4,11,2,14,15,0,8,13,3,12,9,7,5,10,6,1, + 13,0,11,7,4,9,1,10,14,3,5,12,2,15,8,6, + 1,4,11,13,12,3,7,14,10,15,6,8,0,5,9,2, + 6,11,13,8,1,4,10,7,9,5,0,15,14,2,3,12}; + +unsigned int S8[]={13,2,8,4,6,15,11,1,10,9,3,14,5,0,12,7, + 1,15,13,8,10,3,7,4,12,5,6,11,0,14,9,2, + 7,11,4,1,9,12,14,2,0,6,10,13,15,3,5,8, + 2,1,14,7,4,10,8,13,15,12,9,0,3,5,6,11}; + + +void apply_table(unsigned char *block,unsigned char *block_t,unsigned int *perm,int outlength){ + unsigned int i,byte,bit; + + for(i=0;i>3;i++) block_t[i]=0; + + for(i=0;i>3); /*In which byte of the original block is the bit to permute*/ + bit=((perm[i]-1)&7); /*In which pos of the byte is the bit to permute*/ + if((block[byte]>>(7-bit))&1==1) + block_t[i>>3]+=(0x80>>(i&7)); + } +} + +void generate_key(unsigned char *previous_key,unsigned char *new_key,int iteration){ + /*Generates the next iteration non permuted key from the previous non-permuted key*/ + + unsigned char Cx_rotated[4],Dx_rotated[4]; + unsigned char Cx[4],Dx[4]; + unsigned int i; + + for(i=0;i<7;i++) + new_key[i]=0; + + + /*We split the 56 bit key in two parts*/ + Cx[0]=previous_key[0]; + Cx[1]=previous_key[1]; + Cx[2]=previous_key[2]; + Cx[3]=previous_key[3]; + Dx[0]=previous_key[3]; + Dx[1]=previous_key[4]; + Dx[2]=previous_key[5]; + Dx[3]=previous_key[6]; + + /*Rotate Cx and Dx*/ + if(key_shifts[iteration-1]==1){ + apply_table(Cx,Cx_rotated,rotate_C_1,32); + apply_table(Dx,Dx_rotated,rotate_D_1,32); + }else if(key_shifts[iteration-1]==2){ + apply_table(Cx,Cx_rotated,rotate_C_2,32); + apply_table(Dx,Dx_rotated,rotate_D_2,32); + } + + //binary_print(previous_key,7); + //binary_print(Cx_rotated,4); + //binary_print(Dx_rotated,4); + + /*Recompose key*/ + new_key[0]=Cx_rotated[0]; + new_key[1]=Cx_rotated[1]; + new_key[2]=Cx_rotated[2]; + new_key[3]=(Cx_rotated[3]&0xF0); + + new_key[3]+=Dx_rotated[0]&0xF; + new_key[4]=Dx_rotated[1]; + new_key[5]=Dx_rotated[2]; + new_key[6]=Dx_rotated[3]; + + //binary_print(new_key,7); +} + +void applyS(unsigned char *KER, unsigned char *KERS){ + + unsigned char aux; + int i; + unsigned short int row,col; + + for(i=0;i<4;i++) + KERS[i]=0; + + /*Transform KER with S matrix*/ + row=((KER[0]>>2)&1)+((KER[0]&0x80)>>6); + aux=KER[0]<<1; + col=aux>>4; + KERS[0]=S1[16*row+col]; + + row=(KER[0]&2)+((KER[1]>>4)&1); + col=((KER[0]&1)<<3)+(KER[1]>>5); + KERS[0]=(KERS[0]<<4)+S2[16*row+col]; + + row=((KER[1]>>2)&2)+((KER[2]>>6)&1); + col=((KER[1]&7)<<1)+((KER[2]&0x80)>>7); + KERS[1]=S3[16*row+col]; + + row=((KER[2]>>4)&2)+(KER[2]&1); + col=(KER[2]>>1)&0xF; + KERS[1]=(KERS[1]<<4)+S4[16*row+col]; + + row=((KER[3]>>2)&1)+((KER[3]&0x80)>>6); + aux=KER[3]<<1; + col=aux>>4; + KERS[2]=S5[16*row+col]; + + row=(KER[3]&2)+((KER[4]>>4)&1); + col=((KER[3]&1)<<3)+(KER[4]>>5); + KERS[2]=(KERS[2]<<4)+S6[16*row+col]; + + row=((KER[4]>>2)&2)+((KER[5]>>6)&1); + col=((KER[4]&7)<<1)+((KER[5]&0x80)>>7); + KERS[3]=S7[16*row+col]; + + row=((KER[5]>>4)&2)+(KER[5]&1); + col=(KER[5]>>1)&0xF; + KERS[3]=(KERS[3]<<4)+S8[16*row+col]; + +} + +void encrypt_des(unsigned char *block, unsigned char *block_o, unsigned char *key){ + + unsigned char block_t[8]; + unsigned char new_key[7],permuted_key[6],ER[6],last_key[7]; + unsigned char KER[6]; + unsigned char KERS[4]; /*32 bits after apply the S matrix*/ + unsigned char fKERS[4]; /*32 bits after apply the P matrix*/ + + int i,j; + unsigned char b0_t,b1_t,b2_t,b3_t; + + /*This is the main DES encrypt function + encrypt one block of 64 bits with a key of 64 bits*/ + + /*First we generate the permuted key of 56 bits from the 64 bits one*/ + apply_table(key,last_key,PC_1,7*8); + /*Now we have the K+ key of 56 bits*/ + + /*We generate the first permuted block*/ + apply_table(block,block_t,IP,8*8); + + + /*16 iterations*/ + for(i=1;i<17;i++){ + generate_key(last_key,new_key,i); + for(j=0;j<7;j++) last_key[j]=new_key[j]; + apply_table(new_key,permuted_key,PC_2,6*8); + + /*We now calculate f(R,K)*/ + /*Compute E(R0)*/ + apply_table(block_t+4,ER,E,6*8); + /*Key XOR ER*/ + for(j=0;j<6;j++) + KER[j]=ER[j]^permuted_key[j]; + + applyS(KER,KERS); + apply_table(KERS,fKERS,P,4*8); + + /*Make the aditions*/ + /*Li=Ri-1*/ + b0_t=block_t[0]; + b1_t=block_t[1]; + b2_t=block_t[2]; + b3_t=block_t[3]; + block_t[0]=block_t[4]; + block_t[1]=block_t[5]; + block_t[2]=block_t[6]; + block_t[3]=block_t[7]; + /*Ri=Li-1+fKERS*/ + block_t[4]=b0_t^fKERS[0]; + block_t[5]=b1_t^fKERS[1]; + block_t[6]=b2_t^fKERS[2]; + block_t[7]=b3_t^fKERS[3]; + } + /*Recolocate L and R*/ + b0_t=block_t[0]; + b1_t=block_t[1]; + b2_t=block_t[2]; + b3_t=block_t[3]; + block_t[0]=block_t[4]; + block_t[1]=block_t[5]; + block_t[2]=block_t[6]; + block_t[3]=block_t[7]; + block_t[4]=b0_t; + block_t[5]=b1_t; + block_t[6]=b2_t; + block_t[7]=b3_t; + + /*Final permutation*/ + apply_table(block_t,block_o,IP_1,8*8); + +} + +void decrypt_des(unsigned char *block, unsigned char *block_o, unsigned char *key){ + unsigned char block_t[8]; + unsigned char new_key[7],permuted_key[6],ER[6],last_key[7]; + unsigned char KER[6]; + unsigned char KERS[4]; /*32 bits after apply the S matrix*/ + unsigned char fKERS[4]; /*32 bits after apply the P matrix*/ + unsigned char keys[16][6]; + + int i,j; + unsigned char b0_t,b1_t,b2_t,b3_t; + + /*This is the main DES decrypt function + encrypt one block of 64 bits with a key of 64 bits*/ + + /*First we generate the permuted key of 56 bits from the 64 bits one*/ + apply_table(key,last_key,PC_1,7*8); + /*Now we have the K+ key of 56 bits*/ + + /*We generate the first permuted block*/ + apply_table(block,block_t,IP,8*8); + + for(i=1;i<17;i++){ + generate_key(last_key,new_key,i); + for(j=0;j<7;j++) last_key[j]=new_key[j]; + apply_table(new_key,permuted_key,PC_2,6*8); + for(j=0;j<6;j++) + keys[i-1][j]=permuted_key[j]; + } + + /*16 iterations*/ + for(i=1;i<17;i++){ + /*We now calculate f(R,K)*/ + /*Compute E(R0)*/ + apply_table(block_t+4,ER,E,6*8); + /*Key XOR ER*/ + for(j=0;j<6;j++) + KER[j]=ER[j]^keys[15-(i-1)][j]; + + applyS(KER,KERS); + apply_table(KERS,fKERS,P,4*8); + + /*Make the aditions*/ + /*Li=Ri-1*/ + b0_t=block_t[0]; + b1_t=block_t[1]; + b2_t=block_t[2]; + b3_t=block_t[3]; + block_t[0]=block_t[4]; + block_t[1]=block_t[5]; + block_t[2]=block_t[6]; + block_t[3]=block_t[7]; + /*Ri=Li-1+fKERS*/ + block_t[4]=b0_t^fKERS[0]; + block_t[5]=b1_t^fKERS[1]; + block_t[6]=b2_t^fKERS[2]; + block_t[7]=b3_t^fKERS[3]; + } + /*Recolocate L and R*/ + b0_t=block_t[0]; + b1_t=block_t[1]; + b2_t=block_t[2]; + b3_t=block_t[3]; + block_t[0]=block_t[4]; + block_t[1]=block_t[5]; + block_t[2]=block_t[6]; + block_t[3]=block_t[7]; + block_t[4]=b0_t; + block_t[5]=b1_t; + block_t[6]=b2_t; + block_t[7]=b3_t; + + /*Final permutation*/ + apply_table(block_t,block_o,IP_1,8*8); + +} Index: systemcdes/tags/V10/bench/systemc/README~ =================================================================== --- systemcdes/tags/V10/bench/systemc/README~ (nonexistent) +++ systemcdes/tags/V10/bench/systemc/README~ (revision 11) @@ -0,0 +1,4 @@ +This filea are replicated in /rtl/systemc + + +jcastillo@opencores.org Index: systemcdes/tags/V10/bench/systemc/stimulus.h =================================================================== --- systemcdes/tags/V10/bench/systemc/stimulus.h (nonexistent) +++ systemcdes/tags/V10/bench/systemc/stimulus.h (revision 11) @@ -0,0 +1,75 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Random testbench declation //// +//// //// +//// This file is part of the SystemC DES //// +//// //// +//// Description: //// +//// Declare ramdom testbench class and data //// +//// //// +//// To Do: //// +//// - done //// +//// //// +//// Author(s): //// +//// - Javier Castillo, jcastilo@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ + + + +#include "transactor.h" +#include "scv.h" + +//Random number generator + +class random_generator:virtual public scv_constraint_base{ +public: + + scv_smart_ptr > des_key; + scv_smart_ptr > des_data; + + scv_smart_ptr decrypt; + + SCV_CONSTRAINT_CTOR(random_generator){ } +}; + +class test : public sc_module{ + public: + + sc_port transactor; + + void tb(); + + SC_CTOR(test){ + SC_THREAD(tb); + } +}; Index: systemcdes/tags/V10/bench/systemc/README =================================================================== --- systemcdes/tags/V10/bench/systemc/README (nonexistent) +++ systemcdes/tags/V10/bench/systemc/README (revision 11) @@ -0,0 +1,4 @@ +This files are replicated in /rtl/systemc + + +jcastillo@opencores.org Index: systemcdes/tags/V10/bench/verilog/des_test.v =================================================================== --- systemcdes/tags/V10/bench/verilog/des_test.v (nonexistent) +++ systemcdes/tags/V10/bench/verilog/des_test.v (revision 11) @@ -0,0 +1,130 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Testbench for Verilog translation of SystemC DES //// +//// //// +//// This file is part of the SystemC DES //// +//// //// +//// Description: //// +//// DES testbench //// +//// //// +//// //// +//// To Do: //// +//// - Add more test cases //// +//// //// +//// Author(s): //// +//// - Javier Castillo, jcastilo@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ + +`timescale 10ns/1ns + +module top; + + + +reg clk, reset, load_i, decrypt_i; +reg [63:0] data_i, key_i; +wire [63:0] data_o; +wire ready_o; + +reg [191:0] tmp; +reg [191:0] x[6:0]; +integer ZZZ; +integer select; + + +des d1(clk,reset,load_i,decrypt_i,data_i,key_i,data_o,ready_o); + + initial + + begin + $display("\n\n"); + $display("******************************************"); + $display("* DES core simulation started ... *"); + $display("******************************************"); + $display("\n"); + $display("Running\n"); + + + clk = 'b1; + reset = 'b0; + @(posedge clk); + @(posedge clk); + reset = 'b1; + + ZZZ=0; + + + //Decrypt + // Key Data + x[ZZZ]=192'h0cb76ea9864252f4_34ffd445a8f4e555_a1971ff745ad8b38; ZZZ=ZZZ+1; + x[ZZZ]=192'h0123456789ABCDEF_0000000000000000_14AAD7F4DBB4E094; ZZZ=ZZZ+1; + x[ZZZ]=192'h0000000000000000_123456789ABCDEF0_9D2A73F6A9070648; ZZZ=ZZZ+1; + x[ZZZ]=192'h23FE536344578A49_123456789ABCDEF0_F4E5D5EFAA638C43; ZZZ=ZZZ+1; + + //Encrypt + x[ZZZ]=192'h0123456789ABCDEF_0000000000000000_D5D44FF720683D0D; ZZZ=ZZZ+1; + x[ZZZ]=192'h0000000000000000_123456789ABCDEF0_9D2A73F6A9070648; ZZZ=ZZZ+1; + x[ZZZ]=192'h23FE536344578A49_123456789ABCDEF0_1862EC2AA88BA258; ZZZ=ZZZ+1; + + + for(select=0;select3); + tmp=x[select]; + key_i=tmp[191:128]; + data_i=tmp[127:64]; + load_i = 1'b1; + @(posedge clk); + load_i = 1'b0; + + while(!ready_o) @(posedge clk); + //$display("Got %x", data_o); + if(data_o!=tmp[63:0]) + $display("ERROR: (%0d) Expected %x Got %x", select, tmp[63:0], data_o); + + end + + $display(""); + $display("**************************************"); + $display("* DES Test done ... *"); + $display("**************************************"); + $display(""); + + $finish; + end + always #5 clk = !clk; + +endmodule Index: systemcdes/tags/V10/rtl/systemc/desmodel.h =================================================================== --- systemcdes/tags/V10/rtl/systemc/desmodel.h (nonexistent) +++ systemcdes/tags/V10/rtl/systemc/desmodel.h (revision 11) @@ -0,0 +1,95 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// DES C behavioral model //// +//// //// +//// This file is part of the SystemC DES //// +//// //// +//// Description: //// +//// C behavioral model used as golden model //// +//// //// +//// To Do: //// +//// - done //// +//// //// +//// Author(s): //// +//// - Javier Castillo, jcastilo@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ + +#include "systemc.h" + +void decrypt_des(unsigned char *block, unsigned char *block_o, unsigned char *key); +void encrypt_des(unsigned char *block, unsigned char *block_o, unsigned char *key); + +SC_MODULE(desmodel){ + + sc_fifo_in decrypt; + sc_fifo_in > des_key_i; + sc_fifo_in > des_data_i; + + sc_fifo_out > des_data_o; + + void des_thread(){ + unsigned char des_key[8],des_data[8],des_out[8]; + sc_uint<64> des_key_i_var,des_data_i_var,des_data_o_var; + + while(1){ + + des_data_i_var=des_data_i.read(); + des_key_i_var=des_key_i.read(); + + //Convert a sc_uint<64> to an array of 8 char + des_key[0]=des_key_i_var.range(63,56);des_key[1]=des_key_i_var.range(55,48);des_key[2]=des_key_i_var.range(47,40);des_key[3]=des_key_i_var.range(39,32); + des_key[4]=des_key_i_var.range(31,24);des_key[5]=des_key_i_var.range(23,16);des_key[6]=des_key_i_var.range(15,8);des_key[7]=des_key_i_var.range(7,0); + + des_data[0]=des_data_i_var.range(63,56);des_data[1]=des_data_i_var.range(55,48);des_data[2]=des_data_i_var.range(47,40);des_data[3]=des_data_i_var.range(39,32); + des_data[4]=des_data_i_var.range(31,24);des_data[5]=des_data_i_var.range(23,16);des_data[6]=des_data_i_var.range(15,8);des_data[7]=des_data_i_var.range(7,0); + + if(!decrypt.read()) + encrypt_des(des_data,des_out,des_key); + else + decrypt_des(des_data,des_out,des_key); + + des_data_o_var.range(63,56)=des_out[0];des_data_o_var.range(55,48)=des_out[1];des_data_o_var.range(47,40)=des_out[2];des_data_o_var.range(39,32)=des_out[3]; + des_data_o_var.range(31,24)=des_out[4];des_data_o_var.range(23,16)=des_out[5];des_data_o_var.range(15,8)=des_out[6];des_data_o_var.range(7,0)=des_out[7]; + + des_data_o.write(des_data_o_var); + } + } + + + + SC_CTOR(desmodel){ + + SC_THREAD(des_thread); + + } +}; Index: systemcdes/tags/V10/rtl/systemc/des.cpp =================================================================== --- systemcdes/tags/V10/rtl/systemc/des.cpp (nonexistent) +++ systemcdes/tags/V10/rtl/systemc/des.cpp (revision 11) @@ -0,0 +1,197 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// DES algorithm implementation //// +//// //// +//// This file is part of the SystemC DES //// +//// //// +//// Description: //// +//// Top file for DES algorithm //// +//// //// +//// To Do: //// +//// - nothing //// +//// //// +//// Author(s): //// +//// - Javier Castillo, jcastilo@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ + +#include "des.h" + +void des::reg_signal(){ + if(!reset){ + ready_o.write(0); + data_o.write(0); + stage1_iter.write(0); + data_ready.write(1); + }else{ + ready_o.write(next_ready_o.read()); + data_o.write(next_data_o.read()); + stage1_iter.write(next_stage1_iter.read()); + data_ready.write(next_data_ready.read()); + } + +} + +void des::des_proc(){ + + sc_uint<32> L_i_var,R_i_var; + sc_uint<64> data_i_var,data_o_var,data_o_var_t,key_i_var; + sc_uint<56> key_var_perm; + + L_i_var=0; + R_i_var=0; + data_i_var=0; + + next_ready_o.write(0); + next_data_ready.write(data_ready.read()); + next_stage1_iter.write(stage1_iter.read()); + + stage1_L_i.write(0); + stage1_R_i.write(0); + stage1_round_key_i.write(0); + + //The permutations are always performed => less resources needed + + key_i_var=key_i.read(); + + key_var_perm[55]=key_i_var[7];key_var_perm[54]=key_i_var[15];key_var_perm[53]=key_i_var[23];key_var_perm[52]=key_i_var[31]; + key_var_perm[51]=key_i_var[39];key_var_perm[50]=key_i_var[47];key_var_perm[49]=key_i_var[55];key_var_perm[48]=key_i_var[63]; + + key_var_perm[47]=key_i_var[6];key_var_perm[46]=key_i_var[14];key_var_perm[45]=key_i_var[22];key_var_perm[44]=key_i_var[30]; + key_var_perm[43]=key_i_var[38];key_var_perm[42]=key_i_var[46];key_var_perm[41]=key_i_var[54];key_var_perm[40]=key_i_var[62]; + + key_var_perm[39]=key_i_var[5];key_var_perm[38]=key_i_var[13];key_var_perm[37]=key_i_var[21];key_var_perm[36]=key_i_var[29]; + key_var_perm[35]=key_i_var[37];key_var_perm[34]=key_i_var[45];key_var_perm[33]=key_i_var[53];key_var_perm[32]=key_i_var[61]; + + key_var_perm[31]=key_i_var[4];key_var_perm[30]=key_i_var[12];key_var_perm[29]=key_i_var[20];key_var_perm[28]=key_i_var[28]; + key_var_perm[27]=key_i_var[1];key_var_perm[26]=key_i_var[9];key_var_perm[25]=key_i_var[17];key_var_perm[24]=key_i_var[25]; + + key_var_perm[23]=key_i_var[33];key_var_perm[22]=key_i_var[41];key_var_perm[21]=key_i_var[49];key_var_perm[20]=key_i_var[57]; + key_var_perm[19]=key_i_var[2];key_var_perm[18]=key_i_var[10];key_var_perm[17]=key_i_var[18];key_var_perm[16]=key_i_var[26]; + + key_var_perm[15]=key_i_var[34];key_var_perm[14]=key_i_var[42];key_var_perm[13]=key_i_var[50];key_var_perm[12]=key_i_var[58]; + key_var_perm[11]=key_i_var[3];key_var_perm[10]=key_i_var[11];key_var_perm[9]=key_i_var[19];key_var_perm[8]=key_i_var[27]; + + key_var_perm[7]=key_i_var[35];key_var_perm[6]=key_i_var[43];key_var_perm[5]=key_i_var[51];key_var_perm[4]=key_i_var[59]; + key_var_perm[3]=key_i_var[36];key_var_perm[2]=key_i_var[44];key_var_perm[1]=key_i_var[52];key_var_perm[0]=key_i_var[60]; + + + //Apply data to round module with the IP + data_i_var=data_i.read(); + L_i_var[31]=data_i_var[6];L_i_var[30]=data_i_var[14];L_i_var[29]=data_i_var[22];L_i_var[28]=data_i_var[30]; + L_i_var[27]=data_i_var[38];L_i_var[26]=data_i_var[46];L_i_var[25]=data_i_var[54];L_i_var[24]=data_i_var[62]; + + L_i_var[23]=data_i_var[4];L_i_var[22]=data_i_var[12];L_i_var[21]=data_i_var[20];L_i_var[20]=data_i_var[28]; + L_i_var[19]=data_i_var[36];L_i_var[18]=data_i_var[44];L_i_var[17]=data_i_var[52];L_i_var[16]=data_i_var[60]; + + L_i_var[15]=data_i_var[2];L_i_var[14]=data_i_var[10];L_i_var[13]=data_i_var[18];L_i_var[12]=data_i_var[26]; + L_i_var[11]=data_i_var[34];L_i_var[10]=data_i_var[42];L_i_var[9]=data_i_var[50];L_i_var[8]=data_i_var[58]; + + L_i_var[7]=data_i_var[0];L_i_var[6]=data_i_var[8];L_i_var[5]=data_i_var[16];L_i_var[4]=data_i_var[24]; + L_i_var[3]=data_i_var[32];L_i_var[2]=data_i_var[40];L_i_var[1]=data_i_var[48];L_i_var[0]=data_i_var[56]; + + R_i_var[31]=data_i_var[7];R_i_var[30]=data_i_var[15];R_i_var[29]=data_i_var[23];R_i_var[28]=data_i_var[31]; + R_i_var[27]=data_i_var[39];R_i_var[26]=data_i_var[47];R_i_var[25]=data_i_var[55];R_i_var[24]=data_i_var[63]; + + R_i_var[23]=data_i_var[5];R_i_var[22]=data_i_var[13];R_i_var[21]=data_i_var[21];R_i_var[20]=data_i_var[29]; + R_i_var[19]=data_i_var[37];R_i_var[18]=data_i_var[45];R_i_var[17]=data_i_var[53];R_i_var[16]=data_i_var[61]; + + R_i_var[15]=data_i_var[3];R_i_var[14]=data_i_var[11];R_i_var[13]=data_i_var[19];R_i_var[12]=data_i_var[27]; + R_i_var[11]=data_i_var[35];R_i_var[10]=data_i_var[43];R_i_var[9]=data_i_var[51];R_i_var[8]=data_i_var[59]; + + R_i_var[7]=data_i_var[1];R_i_var[6]=data_i_var[9];R_i_var[5]=data_i_var[17];R_i_var[4]=data_i_var[25]; + R_i_var[3]=data_i_var[33];R_i_var[2]=data_i_var[41];R_i_var[1]=data_i_var[49];R_i_var[0]=data_i_var[57]; + + //IP-1 Permutation + + data_o_var_t.range(63,32)=stage1_R_o.read(); + data_o_var_t.range(31,0)=stage1_L_o.read(); + + data_o_var[63]=data_o_var_t[24];data_o_var[62]=data_o_var_t[56];data_o_var[61]=data_o_var_t[16];data_o_var[60]=data_o_var_t[48]; + data_o_var[59]=data_o_var_t[8];data_o_var[58]=data_o_var_t[40];data_o_var[57]=data_o_var_t[0];data_o_var[56]=data_o_var_t[32]; + + data_o_var[55]=data_o_var_t[25];data_o_var[54]=data_o_var_t[57];data_o_var[53]=data_o_var_t[17];data_o_var[52]=data_o_var_t[49]; + data_o_var[51]=data_o_var_t[9];data_o_var[50]=data_o_var_t[41];data_o_var[49]=data_o_var_t[1];data_o_var[48]=data_o_var_t[33]; + + data_o_var[47]=data_o_var_t[26];data_o_var[46]=data_o_var_t[58];data_o_var[45]=data_o_var_t[18];data_o_var[44]=data_o_var_t[50]; + data_o_var[43]=data_o_var_t[10];data_o_var[42]=data_o_var_t[42];data_o_var[41]=data_o_var_t[2];data_o_var[40]=data_o_var_t[34]; + + data_o_var[39]=data_o_var_t[27];data_o_var[38]=data_o_var_t[59];data_o_var[37]=data_o_var_t[19];data_o_var[36]=data_o_var_t[51]; + data_o_var[35]=data_o_var_t[11];data_o_var[34]=data_o_var_t[43];data_o_var[33]=data_o_var_t[3];data_o_var[32]=data_o_var_t[35]; + + data_o_var[31]=data_o_var_t[28];data_o_var[30]=data_o_var_t[60];data_o_var[29]=data_o_var_t[20];data_o_var[28]=data_o_var_t[52]; + data_o_var[27]=data_o_var_t[12];data_o_var[26]=data_o_var_t[44];data_o_var[25]=data_o_var_t[4];data_o_var[24]=data_o_var_t[36]; + + data_o_var[23]=data_o_var_t[29];data_o_var[22]=data_o_var_t[61];data_o_var[21]=data_o_var_t[21];data_o_var[20]=data_o_var_t[53]; + data_o_var[19]=data_o_var_t[13];data_o_var[18]=data_o_var_t[45];data_o_var[17]=data_o_var_t[5];data_o_var[16]=data_o_var_t[37]; + + data_o_var[15]=data_o_var_t[30];data_o_var[14]=data_o_var_t[62];data_o_var[13]=data_o_var_t[22];data_o_var[12]=data_o_var_t[54]; + data_o_var[11]=data_o_var_t[14];data_o_var[10]=data_o_var_t[46];data_o_var[9]=data_o_var_t[6];data_o_var[8]=data_o_var_t[38]; + + data_o_var[7]=data_o_var_t[31];data_o_var[6]=data_o_var_t[63];data_o_var[5]=data_o_var_t[23];data_o_var[4]=data_o_var_t[55]; + data_o_var[3]=data_o_var_t[15];data_o_var[2]=data_o_var_t[47];data_o_var[1]=data_o_var_t[7];data_o_var[0]=data_o_var_t[39]; + + //Assign data output + next_data_o.write(data_o_var); + + //FSM to control the round datapath + stage1_iteration_i.write(stage1_iter.read()); + + next_ready_o.write(0); + stage1_L_i.write(stage1_L_o.read()); + stage1_R_i.write(stage1_R_o.read()); + stage1_round_key_i.write(stage1_round_key_o.read()); + + switch(stage1_iter.read()){ + case 0: + if(load_i.read()){ + next_stage1_iter.write(1); + stage1_L_i.write(L_i_var); + stage1_R_i.write(R_i_var); + stage1_round_key_i.write(key_var_perm); + next_data_ready.write(0); + }else if (!data_ready.read()){ + next_stage1_iter.write(0); + //Can accept data + next_ready_o.write(1); + next_data_ready.write(1); + } + break; + case 15: + next_stage1_iter.write(0); + break; + default: + next_stage1_iter.write(stage1_iter.read()+1); + break; + } + +} Index: systemcdes/tags/V10/rtl/systemc/main.cpp =================================================================== --- systemcdes/tags/V10/rtl/systemc/main.cpp (nonexistent) +++ systemcdes/tags/V10/rtl/systemc/main.cpp (revision 11) @@ -0,0 +1,133 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Main simulation file //// +//// //// +//// This file is part of the SystemC DES //// +//// //// +//// Description: //// +//// Simulation file for DES project //// +//// //// +//// To Do: //// +//// - nothing //// +//// //// +//// Author(s): //// +//// - Javier Castillo, jcastilo@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ + + +#include "systemc.h" +#include "iostream.h" +#include "des.h" +#include "desfunctions.h" +#include "desmodel.h" +#include "stimulus.h" +#include "adapt.h" +#include "checker.h" + +int sc_main(int argc, char* argv[]){ + + sc_clock clk("clk",20); + + test *t; + des_transactor *tr; + des *de1; + desmodel *dm1; + adapter *ad1; + checker *ch1; + + t=new test("testbench"); + tr=new des_transactor("des_transactor"); + dm1=new desmodel("des_C_model"); + de1=new des("des"); + ad1=new adapter("adapter"); + ch1=new checker("checker"); + + t->transactor(*tr); + + sc_signal reset; + sc_signal rt_load; + sc_signal rt_decrypt; + sc_signal > rt_data_i; + sc_signal > rt_key; + + sc_signal > rt_data_o; + sc_signal rt_ready; + + sc_fifo > rt_des_data_ck; + sc_fifo > c_des_data_ck; + + sc_fifo c_decrypt; + sc_fifo > c_key; + sc_fifo > c_data; + + ch1->reset(reset); + ch1->rt_des_data_i(rt_des_data_ck); + ch1->c_des_data_i(c_des_data_ck); + + ad1->clk(clk); + ad1->rt_ready_i(rt_ready); + ad1->rt_des_data_i(rt_data_o); + ad1->rt_des_data_o(rt_des_data_ck); + + dm1->decrypt(c_decrypt); + dm1->des_key_i(c_key); + dm1->des_data_i(c_data); + dm1->des_data_o(c_des_data_ck); + + de1->clk(clk); + de1->reset(reset); + de1->load_i(rt_load); + de1->decrypt_i(rt_decrypt); + de1->data_i(rt_data_i); + de1->key_i(rt_key); + de1->data_o(rt_data_o); + de1->ready_o(rt_ready); + + tr->clk(clk); + tr->reset(reset); + //Ports to RT model + tr->rt_load_o(rt_load); + tr->rt_decrypt_o(rt_decrypt); + tr->rt_des_data_o(rt_data_i); + tr->rt_des_key_o(rt_key); + tr->rt_des_ready_i(rt_ready); + //Ports to C model + tr->c_decrypt_o(c_decrypt); + tr->c_des_key_o(c_key); + tr->c_des_data_o(c_data); + + sc_start(-1); + + return 0; + + } Index: systemcdes/tags/V10/rtl/systemc/transactor.h =================================================================== --- systemcdes/tags/V10/rtl/systemc/transactor.h (nonexistent) +++ systemcdes/tags/V10/rtl/systemc/transactor.h (revision 11) @@ -0,0 +1,150 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Transactor for AES ramdom verification //// +//// //// +//// This file is part of the SystemC DES //// +//// //// +//// Description: //// +//// Transactor acording to TLM for SystemC DES project //// +//// //// +//// To Do: //// +//// - nothing //// +//// //// +//// Author(s): //// +//// - Javier Castillo, jcastilo@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ + +#include "systemc.h" + +class transactor_ports:public sc_module{ + public: + + // Ports + sc_in clk; + sc_out reset; + + //Ports to RT model + sc_out rt_load_o; + sc_out rt_decrypt_o; + sc_out > rt_des_data_o; + sc_out > rt_des_key_o; + sc_in rt_des_ready_i; + + //Ports to C model + sc_fifo_out c_decrypt_o; + sc_fifo_out > c_des_key_o; + sc_fifo_out > c_des_data_o; + +}; + + +class rw_task_if : virtual public sc_interface { + + public: + //Funciones para el transactor + virtual void resetea(void)=0; + virtual void encrypt(sc_uint<64> data, sc_uint<64> key)=0; + virtual void decrypt(sc_uint<64> data, sc_uint<64> key)=0; + virtual void wait_cycles(int cycles)=0; + +}; + + +//Transactor +class des_transactor:public rw_task_if,public transactor_ports { + + public: + + SC_CTOR(des_transactor){ + + cout.unsetf(ios::dec); + cout.setf(ios::hex); + + } + + + void resetea(void){ + reset.write(0); + wait(clk->posedge_event()); + reset.write(1); + cout << "Reseted" << endl; + } + + void encrypt(sc_uint<64> data, sc_uint<64> key){ + + wait(clk->posedge_event()); + + //To RT model + rt_load_o.write(1); + rt_des_data_o.write(data); + rt_des_key_o.write(key); + rt_decrypt_o.write(0); + + //To C model through fifos + c_des_data_o.write(data); + c_des_key_o.write(key); + c_decrypt_o.write(0); + + wait(clk->posedge_event()); + rt_load_o.write(0); + wait(rt_des_ready_i->posedge_event()); + } + + void decrypt(sc_uint<64> data, sc_uint<64> key){ + + wait(clk->posedge_event()); + + //To RT model + rt_load_o.write(1); + rt_des_data_o.write(data); + rt_des_key_o.write(key); + rt_decrypt_o.write(1); + + //To C model through fifos + c_des_data_o.write(data); + c_des_key_o.write(key); + c_decrypt_o.write(1); + + wait(clk->posedge_event()); + rt_load_o.write(0); + wait(rt_des_ready_i->posedge_event()); + + } + + void wait_cycles(int cycles){ + for(int i=0;iposedge_event()); + } + } + +}; Index: systemcdes/tags/V10/rtl/systemc/key_gen.h =================================================================== --- systemcdes/tags/V10/rtl/systemc/key_gen.h (nonexistent) +++ systemcdes/tags/V10/rtl/systemc/key_gen.h (revision 11) @@ -0,0 +1,63 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Key generation module header //// +//// //// +//// This file is part of the SystemC DES //// +//// //// +//// Description: //// +//// Generate a key from the previous one //// +//// //// +//// To Do: //// +//// - nothing //// +//// //// +//// Author(s): //// +//// - Javier Castillo, jcastilo@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ + +#include "systemc.h" + +SC_MODULE(key_gen){ + + sc_in > previous_key; + sc_in > iteration; + sc_in decrypt; //When decrypting we rotate rigth instead of left + sc_out > non_perm_key; + sc_out > new_key; + + void generate_key(); + + SC_CTOR(key_gen){ + SC_METHOD(generate_key); + sensitive << previous_key << iteration << decrypt; + } +}; Index: systemcdes/tags/V10/rtl/systemc/s1.h =================================================================== --- systemcdes/tags/V10/rtl/systemc/s1.h (nonexistent) +++ systemcdes/tags/V10/rtl/systemc/s1.h (revision 11) @@ -0,0 +1,62 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// SBOX 1 Header //// +//// //// +//// This file is part of the SystemC DES //// +//// //// +//// Description: //// +//// Sbox of DES algorithm //// +//// //// +//// To Do: //// +//// - done //// +//// //// +//// Author(s): //// +//// - Javier Castillo, jcastilo@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ + +#include "systemc.h" + + +SC_MODULE(s1){ + + sc_in > stage1_input; + sc_out > stage1_output; + + void s1_box(); + + SC_CTOR(s1){ + + SC_METHOD(s1_box); + sensitive << stage1_input; + } +}; Index: systemcdes/tags/V10/rtl/systemc/s2.h =================================================================== --- systemcdes/tags/V10/rtl/systemc/s2.h (nonexistent) +++ systemcdes/tags/V10/rtl/systemc/s2.h (revision 11) @@ -0,0 +1,62 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// SBOX 2 Header //// +//// //// +//// This file is part of the SystemC DES //// +//// //// +//// Description: //// +//// Sbox of DES algorithm //// +//// //// +//// To Do: //// +//// - done //// +//// //// +//// Author(s): //// +//// - Javier Castillo, jcastilo@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ + +#include "systemc.h" + +SC_MODULE(s2){ + + sc_in > stage1_input; + sc_out > stage1_output; + + void s2_box(); + + SC_CTOR(s2){ + + SC_METHOD(s2_box); + sensitive << stage1_input; + + } +}; Index: systemcdes/tags/V10/rtl/systemc/stimulus.h =================================================================== --- systemcdes/tags/V10/rtl/systemc/stimulus.h (nonexistent) +++ systemcdes/tags/V10/rtl/systemc/stimulus.h (revision 11) @@ -0,0 +1,75 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Random testbench declation //// +//// //// +//// This file is part of the SystemC DES //// +//// //// +//// Description: //// +//// Declare ramdom testbench class and data //// +//// //// +//// To Do: //// +//// - done //// +//// //// +//// Author(s): //// +//// - Javier Castillo, jcastilo@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ + + + +#include "transactor.h" +#include "scv.h" + +//Random number generator + +class random_generator:virtual public scv_constraint_base{ +public: + + scv_smart_ptr > des_key; + scv_smart_ptr > des_data; + + scv_smart_ptr decrypt; + + SCV_CONSTRAINT_CTOR(random_generator){ } +}; + +class test : public sc_module{ + public: + + sc_port transactor; + + void tb(); + + SC_CTOR(test){ + SC_THREAD(tb); + } +}; Index: systemcdes/tags/V10/rtl/systemc/s3.h =================================================================== --- systemcdes/tags/V10/rtl/systemc/s3.h (nonexistent) +++ systemcdes/tags/V10/rtl/systemc/s3.h (revision 11) @@ -0,0 +1,62 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// SBOX 3 Header //// +//// //// +//// This file is part of the SystemC DES //// +//// //// +//// Description: //// +//// Sbox of DES algorithm //// +//// //// +//// To Do: //// +//// - done //// +//// //// +//// Author(s): //// +//// - Javier Castillo, jcastilo@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ + +#include "systemc.h" + +SC_MODULE(s3){ + + sc_in > stage1_input; + sc_out > stage1_output; + + + void s3_box(); + + SC_CTOR(s3){ + + SC_METHOD(s3_box); + sensitive << stage1_input; + } +}; Index: systemcdes/tags/V10/rtl/systemc/s4.h =================================================================== --- systemcdes/tags/V10/rtl/systemc/s4.h (nonexistent) +++ systemcdes/tags/V10/rtl/systemc/s4.h (revision 11) @@ -0,0 +1,62 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// SBOX 4 Header //// +//// //// +//// This file is part of the SystemC DES //// +//// //// +//// Description: //// +//// Sbox of DES algorithm //// +//// //// +//// To Do: //// +//// - done //// +//// //// +//// Author(s): //// +//// - Javier Castillo, jcastilo@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ + +#include "systemc.h" + +SC_MODULE(s4){ + + sc_in > stage1_input; + sc_out > stage1_output; + + void s4_box(); + + + SC_CTOR(s4){ + + SC_METHOD(s4_box); + sensitive << stage1_input; + } +}; Index: systemcdes/tags/V10/rtl/systemc/s5.h =================================================================== --- systemcdes/tags/V10/rtl/systemc/s5.h (nonexistent) +++ systemcdes/tags/V10/rtl/systemc/s5.h (revision 11) @@ -0,0 +1,63 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// SBOX 5 Header //// +//// //// +//// This file is part of the SystemC DES //// +//// //// +//// Description: //// +//// Sbox of DES algorithm //// +//// //// +//// To Do: //// +//// - done //// +//// //// +//// Author(s): //// +//// - Javier Castillo, jcastilo@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ + +#include "systemc.h" + +SC_MODULE(s5){ + + sc_in > stage1_input; + sc_out > stage1_output; + + void s5_box(); + + + SC_CTOR(s5){ + + SC_METHOD(s5_box); + sensitive << stage1_input; + + } +}; Index: systemcdes/tags/V10/rtl/systemc/Makefile =================================================================== --- systemcdes/tags/V10/rtl/systemc/Makefile (nonexistent) +++ systemcdes/tags/V10/rtl/systemc/Makefile (revision 11) @@ -0,0 +1,14 @@ +TARGET_ARCH = linux + +CC = g++ +OPT = -O3 +DEBUG = -g +OTHER = -Wall -Wno-deprecated +EXTRA_CFLAGS = $(OPT) $(OTHER) +# EXTRA_CFLAGS = $(DEBUG) $(OTHER) + +MODULE = des +SRCS = s1.cpp s2.cpp s3.cpp s4.cpp s5.cpp s6.cpp s7.cpp s8.cpp key_gen.cpp round.cpp des.cpp stimulus.cpp main.cpp +OBJS = $(SRCS:.cpp=.o) + +include Makefile.defs Index: systemcdes/tags/V10/rtl/systemc/round.h =================================================================== --- systemcdes/tags/V10/rtl/systemc/round.h (nonexistent) +++ systemcdes/tags/V10/rtl/systemc/round.h (revision 11) @@ -0,0 +1,105 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Round of DES algorithm header //// +//// //// +//// This file is part of the SystemC DES //// +//// //// +//// Description: //// +//// This file perform a round of the DES algorithm //// +//// //// +//// To Do: //// +//// - nothing //// +//// //// +//// Author(s): //// +//// - Javier Castillo, jcastilo@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ + +#include "systemc.h" + +#include "key_gen.h" + +SC_MODULE(desround){ + + sc_in clk; + sc_in reset; + + sc_in > iteration_i; + sc_in decrypt_i; + sc_in > R_i; + sc_in > L_i; + sc_in > Key_i; + + sc_out > R_o; + sc_out > L_o; + sc_out > Key_o; + + sc_out > s1_o,s2_o,s3_o,s4_o,s5_o,s6_o,s7_o,s8_o; + sc_in > s1_i,s2_i,s3_i,s4_i,s5_i,s6_i,s7_i,s8_i; + + void registers(); + void round_proc(); + + sc_signal > previous_key; + sc_signal > iteration; + sc_signal decrypt; //When decrypting we rotate rigth instead of left + sc_signal > non_perm_key; + sc_signal > new_key; + + sc_signal > next_R; + + sc_signal > expanRSig; + + //Round key generator + key_gen *kg1; + + SC_CTOR(desround){ + + kg1=new key_gen("key_gen"); + kg1->previous_key(previous_key); + kg1->iteration(iteration); + kg1->decrypt(decrypt); + kg1->new_key(new_key); + kg1->non_perm_key(non_perm_key); + + SC_METHOD(registers); + sensitive_pos << clk; + sensitive_neg << reset; + + SC_METHOD(round_proc); + sensitive << R_i << L_i << Key_i << iteration_i << decrypt_i; + sensitive << new_key << s1_i << s2_i << s3_i << s4_i << s5_i; + sensitive << s6_i << s7_i << s8_i; + + + } + }; Index: systemcdes/tags/V10/rtl/systemc/s6.h =================================================================== --- systemcdes/tags/V10/rtl/systemc/s6.h (nonexistent) +++ systemcdes/tags/V10/rtl/systemc/s6.h (revision 11) @@ -0,0 +1,62 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// SBOX 6 Header //// +//// //// +//// This file is part of the SystemC DES //// +//// //// +//// Description: //// +//// Sbox of DES algorithm //// +//// //// +//// To Do: //// +//// - done //// +//// //// +//// Author(s): //// +//// - Javier Castillo, jcastilo@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ + +#include "systemc.h" + +SC_MODULE(s6){ + + sc_in > stage1_input; + sc_out > stage1_output; + + void s6_box(); + + SC_CTOR(s6){ + + SC_METHOD(s6_box); + sensitive << stage1_input; + + } +}; Index: systemcdes/tags/V10/rtl/systemc/s7.h =================================================================== --- systemcdes/tags/V10/rtl/systemc/s7.h (nonexistent) +++ systemcdes/tags/V10/rtl/systemc/s7.h (revision 11) @@ -0,0 +1,62 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// SBOX 7 Header //// +//// //// +//// This file is part of the SystemC DES //// +//// //// +//// Description: //// +//// Sbox of DES algorithm //// +//// //// +//// To Do: //// +//// - done //// +//// //// +//// Author(s): //// +//// - Javier Castillo, jcastilo@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ + +#include "systemc.h" + +SC_MODULE(s7){ + + sc_in > stage1_input; + sc_out > stage1_output; + + void s7_box(); + + + SC_CTOR(s7){ + + SC_METHOD(s7_box); + sensitive << stage1_input; + } +}; Index: systemcdes/tags/V10/rtl/systemc/adapt.h =================================================================== --- systemcdes/tags/V10/rtl/systemc/adapt.h (nonexistent) +++ systemcdes/tags/V10/rtl/systemc/adapt.h (revision 11) @@ -0,0 +1,67 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// sc_fifo to sc_signal adapter //// +//// //// +//// This file is part of the SystemC DES //// +//// //// +//// To Do: //// +//// - done //// +//// //// +//// Author(s): //// +//// - Javier Castillo, jcastilo@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ + +#include "systemc.h" + +SC_MODULE(adapter){ + + sc_in clk; + sc_in rt_ready_i; + sc_in > rt_des_data_i; + + sc_fifo_out > rt_des_data_o; + + void adapt(){ + + while(1){ + wait(clk->posedge_event()); + if(rt_ready_i.read()) + rt_des_data_o.write(rt_des_data_i.read()); + } + + } + + SC_CTOR(adapter){ + SC_THREAD(adapt); + } + }; Index: systemcdes/tags/V10/rtl/systemc/s8.h =================================================================== --- systemcdes/tags/V10/rtl/systemc/s8.h (nonexistent) +++ systemcdes/tags/V10/rtl/systemc/s8.h (revision 11) @@ -0,0 +1,63 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// SBOX 8 Header //// +//// //// +//// This file is part of the SystemC DES //// +//// //// +//// Description: //// +//// Sbox of DES algorithm //// +//// //// +//// To Do: //// +//// - done //// +//// //// +//// Author(s): //// +//// - Javier Castillo, jcastilo@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ + +#include "systemc.h" + +SC_MODULE(s8){ + + sc_in > stage1_input; + sc_out > stage1_output; + + void s8_box(); + + + SC_CTOR(s8){ + + SC_METHOD(s8_box); + sensitive << stage1_input; + + } +}; Index: systemcdes/tags/V10/rtl/systemc/desfunctions.h =================================================================== --- systemcdes/tags/V10/rtl/systemc/desfunctions.h (nonexistent) +++ systemcdes/tags/V10/rtl/systemc/desfunctions.h (revision 11) @@ -0,0 +1,412 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// DES C encrypt and decrypt functions for C golden model //// +//// //// +//// This file is part of the SystemC DES //// +//// //// +//// Description: //// +//// DES C encrypt and decrypt functions for C golden model //// +//// //// +//// To Do: //// +//// - done //// +//// //// +//// Author(s): //// +//// - Javier Castillo, jcastilo@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ + + + +unsigned int P[]={16,7,20,21, + 29,12,28,17, + 1,15,23,26, + 5,18,31,10, + 2,8,24,14, + 32,27,3,9, + 19,13,30,6, + 22,11,4,25}; + +unsigned int IP[]={58,50,42,34,26,18,10,2, + 60,52,44,36,28,20,12,4, + 62,54,46,38,30,22,14,6, + 64,56,48,40,32,24,16,8, + 57,49,41,33,25,17,9,1, + 59,51,43,35,27,19,11,3, + 61,53,45,37,29,21,13,5, + 63,55,47,39,31,23,15,7}; + +unsigned int IP_1[]={40,8,48,16,56,24,64,32, + 39,7,47,15,55,23,63,31, + 38,6,46,14,54,22,62,30, + 37,5,45,13,53,21,61,29, + 36,4,44,12,52,20,60,28, + 35,3,43,11,51,19,59,27, + 34,2,42,10,50,18,58,26, + 33,1,41,9,49,17,57,25}; + +unsigned int PC_1[]={57,49,41,33,25,17,9, + 1,58,50,42,34,26,18, + 10,2,59,51,43,35,27, + 19,11,3,60,52,44,36, + 63,55,47,39,31,23,15, + 7,62,54,46,38,30,22, + 14,6,61,53,45,37,29, + 21,13,5,28,20,12,4}; + +unsigned int PC_2[]={14,17,11,24,1,5, + 3,28,15,6,21,10, + 23,19,12,4,26,8, + 16,7,27,20,13,2, + 41,52,31,37,47,55, + 30,40,51,45,33,48, + 44,49,39,56,34,53, + 46,42,50,36,29,32}; + +unsigned int E[]={32,1,2,3,4,5, + 4,5,6,7,8,9, + 8,9,10,11,12,13, + 12,13,14,15,16,17, + 16,17,18,19,20,21, + 20,21,22,23,24,25, + 24,25,26,27,28,29, + 28,29,30,31,32,1}; + +unsigned int key_shifts[]={1,1,2,2,2,2,2,2,1,2,2,2,2,2,2,1}; + +unsigned int rotate_C_1[]={2,3,4,5,6,7,8,9,10,11,12,13,14, + 15,16,17,18,19,20,21,22,23,24,25,26,27,28,1,29,30,31,32}; + +unsigned int rotate_C_2[]={3,4,5,6,7,8,9,10,11,12,13,14,15, + 16,17,18,19,20,21,22,23,24,25,26,27,28,1,2,29,30,31,32}; + +unsigned int rotate_D_1[]={1,2,3,4,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21, + 22,23,24,25,26,27,28,29,30,31,32,5}; + +unsigned int rotate_D_2[]={1,2,3,4,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21, + 22,23,24,25,26,27,28,29,30,31,32,5,6}; + +unsigned int S1[]={14,4,13,1,2,15,11,8,3,10,6,12,5,9,0,7, + 0,15,7,4,14,2,13,1,10,6,12,11,9,5,3,8, + 4,1,14,8,13,6,2,11,15,12,9,7,3,10,5,0, + 15,12,8,2,4,9,1,7,5,11,3,14,10,0,6,13}; + +unsigned int S2[]={15,1,8,14,6,11,3,4,9,7,2,13,12,0,5,10, + 3,13,4,7,15,2,8,14,12,0,1,10,6,9,11,5, + 0,14,7,11,10,4,13,1,5,8,12,6,9,3,2,15, + 13,8,10,1,3,15,4,2,11,6,7,12,0,5,14,9}; + +unsigned int S3[]={10,0,9,14,6,3,15,5,1,13,12,7,11,4,2,8, + 13,7,0,9,3,4,6,10,2,8,5,14,12,11,15,1, + 13,6,4,9,8,15,3,0,11,1,2,12,5,10,14,7, + 1,10,13,0,6,9,8,7,4,15,14,3,11,5,2,12}; + +unsigned int S4[]={7,13,14,3,0,6,9,10,1,2,8,5,11,12,4,15, + 13,8,11,5,6,15,0,3,4,7,2,12,1,10,14,9, + 10,6,9,0,12,11,7,13,15,1,3,14,5,2,8,4, + 3,15,0,6,10,1,13,8,9,4,5,11,12,7,2,14}; + +unsigned int S5[]={2,12,4,1,7,10,11,6,8,5,3,15,13,0,14,9, + 14,11,2,12,4,7,13,1,5,0,15,10,3,9,8,6, + 4,2,1,11,10,13,7,8,15,9,12,5,6,3,0,14, + 11,8,12,7,1,14,2,13,6,15,0,9,10,4,5,3}; + +unsigned int S6[]={12,1,10,15,9,2,6,8,0,13,3,4,14,7,5,11, + 10,15,4,2,7,12,9,5,6,1,13,14,0,11,3,8, + 9,14,15,5,2,8,12,3,7,0,4,10,1,13,11,6, + 4,3,2,12,9,5,15,10,11,14,1,7,6,0,8,13}; + +unsigned int S7[]={4,11,2,14,15,0,8,13,3,12,9,7,5,10,6,1, + 13,0,11,7,4,9,1,10,14,3,5,12,2,15,8,6, + 1,4,11,13,12,3,7,14,10,15,6,8,0,5,9,2, + 6,11,13,8,1,4,10,7,9,5,0,15,14,2,3,12}; + +unsigned int S8[]={13,2,8,4,6,15,11,1,10,9,3,14,5,0,12,7, + 1,15,13,8,10,3,7,4,12,5,6,11,0,14,9,2, + 7,11,4,1,9,12,14,2,0,6,10,13,15,3,5,8, + 2,1,14,7,4,10,8,13,15,12,9,0,3,5,6,11}; + + +void apply_table(unsigned char *block,unsigned char *block_t,unsigned int *perm,int outlength){ + unsigned int i,byte,bit; + + for(i=0;i>3;i++) block_t[i]=0; + + for(i=0;i>3); /*In which byte of the original block is the bit to permute*/ + bit=((perm[i]-1)&7); /*In which pos of the byte is the bit to permute*/ + if((block[byte]>>(7-bit))&1==1) + block_t[i>>3]+=(0x80>>(i&7)); + } +} + +void generate_key(unsigned char *previous_key,unsigned char *new_key,int iteration){ + /*Generates the next iteration non permuted key from the previous non-permuted key*/ + + unsigned char Cx_rotated[4],Dx_rotated[4]; + unsigned char Cx[4],Dx[4]; + unsigned int i; + + for(i=0;i<7;i++) + new_key[i]=0; + + + /*We split the 56 bit key in two parts*/ + Cx[0]=previous_key[0]; + Cx[1]=previous_key[1]; + Cx[2]=previous_key[2]; + Cx[3]=previous_key[3]; + Dx[0]=previous_key[3]; + Dx[1]=previous_key[4]; + Dx[2]=previous_key[5]; + Dx[3]=previous_key[6]; + + /*Rotate Cx and Dx*/ + if(key_shifts[iteration-1]==1){ + apply_table(Cx,Cx_rotated,rotate_C_1,32); + apply_table(Dx,Dx_rotated,rotate_D_1,32); + }else if(key_shifts[iteration-1]==2){ + apply_table(Cx,Cx_rotated,rotate_C_2,32); + apply_table(Dx,Dx_rotated,rotate_D_2,32); + } + + //binary_print(previous_key,7); + //binary_print(Cx_rotated,4); + //binary_print(Dx_rotated,4); + + /*Recompose key*/ + new_key[0]=Cx_rotated[0]; + new_key[1]=Cx_rotated[1]; + new_key[2]=Cx_rotated[2]; + new_key[3]=(Cx_rotated[3]&0xF0); + + new_key[3]+=Dx_rotated[0]&0xF; + new_key[4]=Dx_rotated[1]; + new_key[5]=Dx_rotated[2]; + new_key[6]=Dx_rotated[3]; + + //binary_print(new_key,7); +} + +void applyS(unsigned char *KER, unsigned char *KERS){ + + unsigned char aux; + int i; + unsigned short int row,col; + + for(i=0;i<4;i++) + KERS[i]=0; + + /*Transform KER with S matrix*/ + row=((KER[0]>>2)&1)+((KER[0]&0x80)>>6); + aux=KER[0]<<1; + col=aux>>4; + KERS[0]=S1[16*row+col]; + + row=(KER[0]&2)+((KER[1]>>4)&1); + col=((KER[0]&1)<<3)+(KER[1]>>5); + KERS[0]=(KERS[0]<<4)+S2[16*row+col]; + + row=((KER[1]>>2)&2)+((KER[2]>>6)&1); + col=((KER[1]&7)<<1)+((KER[2]&0x80)>>7); + KERS[1]=S3[16*row+col]; + + row=((KER[2]>>4)&2)+(KER[2]&1); + col=(KER[2]>>1)&0xF; + KERS[1]=(KERS[1]<<4)+S4[16*row+col]; + + row=((KER[3]>>2)&1)+((KER[3]&0x80)>>6); + aux=KER[3]<<1; + col=aux>>4; + KERS[2]=S5[16*row+col]; + + row=(KER[3]&2)+((KER[4]>>4)&1); + col=((KER[3]&1)<<3)+(KER[4]>>5); + KERS[2]=(KERS[2]<<4)+S6[16*row+col]; + + row=((KER[4]>>2)&2)+((KER[5]>>6)&1); + col=((KER[4]&7)<<1)+((KER[5]&0x80)>>7); + KERS[3]=S7[16*row+col]; + + row=((KER[5]>>4)&2)+(KER[5]&1); + col=(KER[5]>>1)&0xF; + KERS[3]=(KERS[3]<<4)+S8[16*row+col]; + +} + +void encrypt_des(unsigned char *block, unsigned char *block_o, unsigned char *key){ + + unsigned char block_t[8]; + unsigned char new_key[7],permuted_key[6],ER[6],last_key[7]; + unsigned char KER[6]; + unsigned char KERS[4]; /*32 bits after apply the S matrix*/ + unsigned char fKERS[4]; /*32 bits after apply the P matrix*/ + + int i,j; + unsigned char b0_t,b1_t,b2_t,b3_t; + + /*This is the main DES encrypt function + encrypt one block of 64 bits with a key of 64 bits*/ + + /*First we generate the permuted key of 56 bits from the 64 bits one*/ + apply_table(key,last_key,PC_1,7*8); + /*Now we have the K+ key of 56 bits*/ + + /*We generate the first permuted block*/ + apply_table(block,block_t,IP,8*8); + + + /*16 iterations*/ + for(i=1;i<17;i++){ + generate_key(last_key,new_key,i); + for(j=0;j<7;j++) last_key[j]=new_key[j]; + apply_table(new_key,permuted_key,PC_2,6*8); + + /*We now calculate f(R,K)*/ + /*Compute E(R0)*/ + apply_table(block_t+4,ER,E,6*8); + /*Key XOR ER*/ + for(j=0;j<6;j++) + KER[j]=ER[j]^permuted_key[j]; + + applyS(KER,KERS); + apply_table(KERS,fKERS,P,4*8); + + /*Make the aditions*/ + /*Li=Ri-1*/ + b0_t=block_t[0]; + b1_t=block_t[1]; + b2_t=block_t[2]; + b3_t=block_t[3]; + block_t[0]=block_t[4]; + block_t[1]=block_t[5]; + block_t[2]=block_t[6]; + block_t[3]=block_t[7]; + /*Ri=Li-1+fKERS*/ + block_t[4]=b0_t^fKERS[0]; + block_t[5]=b1_t^fKERS[1]; + block_t[6]=b2_t^fKERS[2]; + block_t[7]=b3_t^fKERS[3]; + } + /*Recolocate L and R*/ + b0_t=block_t[0]; + b1_t=block_t[1]; + b2_t=block_t[2]; + b3_t=block_t[3]; + block_t[0]=block_t[4]; + block_t[1]=block_t[5]; + block_t[2]=block_t[6]; + block_t[3]=block_t[7]; + block_t[4]=b0_t; + block_t[5]=b1_t; + block_t[6]=b2_t; + block_t[7]=b3_t; + + /*Final permutation*/ + apply_table(block_t,block_o,IP_1,8*8); + +} + +void decrypt_des(unsigned char *block, unsigned char *block_o, unsigned char *key){ + unsigned char block_t[8]; + unsigned char new_key[7],permuted_key[6],ER[6],last_key[7]; + unsigned char KER[6]; + unsigned char KERS[4]; /*32 bits after apply the S matrix*/ + unsigned char fKERS[4]; /*32 bits after apply the P matrix*/ + unsigned char keys[16][6]; + + int i,j; + unsigned char b0_t,b1_t,b2_t,b3_t; + + /*This is the main DES decrypt function + encrypt one block of 64 bits with a key of 64 bits*/ + + /*First we generate the permuted key of 56 bits from the 64 bits one*/ + apply_table(key,last_key,PC_1,7*8); + /*Now we have the K+ key of 56 bits*/ + + /*We generate the first permuted block*/ + apply_table(block,block_t,IP,8*8); + + for(i=1;i<17;i++){ + generate_key(last_key,new_key,i); + for(j=0;j<7;j++) last_key[j]=new_key[j]; + apply_table(new_key,permuted_key,PC_2,6*8); + for(j=0;j<6;j++) + keys[i-1][j]=permuted_key[j]; + } + + /*16 iterations*/ + for(i=1;i<17;i++){ + /*We now calculate f(R,K)*/ + /*Compute E(R0)*/ + apply_table(block_t+4,ER,E,6*8); + /*Key XOR ER*/ + for(j=0;j<6;j++) + KER[j]=ER[j]^keys[15-(i-1)][j]; + + applyS(KER,KERS); + apply_table(KERS,fKERS,P,4*8); + + /*Make the aditions*/ + /*Li=Ri-1*/ + b0_t=block_t[0]; + b1_t=block_t[1]; + b2_t=block_t[2]; + b3_t=block_t[3]; + block_t[0]=block_t[4]; + block_t[1]=block_t[5]; + block_t[2]=block_t[6]; + block_t[3]=block_t[7]; + /*Ri=Li-1+fKERS*/ + block_t[4]=b0_t^fKERS[0]; + block_t[5]=b1_t^fKERS[1]; + block_t[6]=b2_t^fKERS[2]; + block_t[7]=b3_t^fKERS[3]; + } + /*Recolocate L and R*/ + b0_t=block_t[0]; + b1_t=block_t[1]; + b2_t=block_t[2]; + b3_t=block_t[3]; + block_t[0]=block_t[4]; + block_t[1]=block_t[5]; + block_t[2]=block_t[6]; + block_t[3]=block_t[7]; + block_t[4]=b0_t; + block_t[5]=b1_t; + block_t[6]=b2_t; + block_t[7]=b3_t; + + /*Final permutation*/ + apply_table(block_t,block_o,IP_1,8*8); + +} Index: systemcdes/tags/V10/rtl/systemc/checker.h =================================================================== --- systemcdes/tags/V10/rtl/systemc/checker.h (nonexistent) +++ systemcdes/tags/V10/rtl/systemc/checker.h (revision 11) @@ -0,0 +1,81 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Checker //// +//// //// +//// This file is part of the SystemC DES //// +//// //// +//// Description: //// +//// Check that the outputs from the RTL model and the C model //// +//// used as golden model are the same //// +//// //// +//// To Do: //// +//// - done //// +//// //// +//// Author(s): //// +//// - Javier Castillo, jcastilo@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ + + +#include "systemc.h" + +SC_MODULE(checker){ + + sc_in reset; + + sc_fifo_in > rt_des_data_i; + sc_fifo_in > c_des_data_i; + + void check(){ + sc_uint<64> rt_data_var,c_data_var; + + wait(reset->posedge_event()); + + while(1){ + if(reset.read()){ + rt_data_var=rt_des_data_i.read(); + c_data_var=c_des_data_i.read(); + if(rt_data_var!=c_data_var){ + cout << "Simulation mismatch: 0x" << (int)rt_data_var.range(63,32) << (int)rt_data_var.range(31,0) << " 0x" << (int)c_data_var.range(63,32) << (int)c_data_var.range(31,0) << " " << sc_time_stamp() << endl; + exit(0); + }else{ + cout << "OK: 0x" << (int)rt_data_var.range(63,32) << (int)rt_data_var.range(31,0) << " 0x" << (int)c_data_var.range(63,32) << (int)c_data_var.range(31,0) << " " << sc_time_stamp() << endl; + } + }else + wait(reset->posedge_event()); + } + } + + SC_CTOR(checker){ + SC_THREAD(check); + } + }; Index: systemcdes/tags/V10/rtl/systemc/Makefile.defs =================================================================== --- systemcdes/tags/V10/rtl/systemc/Makefile.defs (nonexistent) +++ systemcdes/tags/V10/rtl/systemc/Makefile.defs (revision 11) @@ -0,0 +1,35 @@ +## Variable that points to SystemC installation path +SYSTEMC = $(SYSTEMC_HOME) +SCV = $(SCV_HOME) + +INCDIR = -I. -I.. -I../../bench -I$(SYSTEMC)/include -I$(SCV)/include +LIBDIR = -L. -L.. -L$(SYSTEMC)/lib-$(TARGET_ARCH) -L$(SCV)/lib-$(TARGET_ARCH) + +# Build with maximum gcc warning level +CFLAGS = $(PLATFORM_SPECIFIC_FLAGS) $(EXTRA_CFLAGS) + +LIBS = -lm -lsystemc -lscv $(EXTRA_LIBS) + +EXE = $(MODULE).x + +.SUFFIXES: .cpp .cc .o .x + +$(EXE): $(OBJS) $(SYSTEMC)/lib-$(TARGET_ARCH)/libsystemc.a $(SCV)/lib-$(TARGET_ARCH)/libscv.a + $(CC) $(CFLAGS) $(INCDIR) $(LIBDIR) -o $@ $(OBJS) $(LIBS) $(SYSTEMC)/lib-$(TARGET_ARCH)/libsystemc.a $(SCV)/lib-$(TARGET_ARCH)/libscv.a 2>&1 | c++filt + +.cpp.o: + $(CC) $(CFLAGS) $(INCDIR) -c $< $(USB_FLAGS) + +.cc.o: + $(CC) $(CFLAGS) $(INCDIR) -c $< $(USB_FLAGS) + +clean:: + rm -f $(OBJS) *~ $(EXE) + +ultraclean: clean + rm -f Makefile.deps + +Makefile.deps: + $(CC) $(CFLAGS) $(INCDIR) -M $(SRCS) >> Makefile.deps + +#include Makefile.deps Index: systemcdes/tags/V10/rtl/systemc/des.h =================================================================== --- systemcdes/tags/V10/rtl/systemc/des.h (nonexistent) +++ systemcdes/tags/V10/rtl/systemc/des.h (revision 11) @@ -0,0 +1,182 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// DES algorithm header //// +//// //// +//// This file is part of the SystemC DES //// +//// //// +//// Description: //// +//// Top file for DES algorithm //// +//// //// +//// To Do: //// +//// - nothing //// +//// //// +//// Author(s): //// +//// - Javier Castillo, jcastilo@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ + +#include "systemc.h" + +#include "round.h" +//S boxes +#include "s1.h" +#include "s2.h" +#include "s3.h" +#include "s4.h" +#include "s5.h" +#include "s6.h" +#include "s7.h" +#include "s8.h" + + +SC_MODULE(des){ + + sc_in clk; + sc_in reset; + + sc_in load_i; + sc_in decrypt_i; + sc_in > data_i; + sc_in > key_i; + + sc_out > data_o; + sc_out ready_o; + + //Registers for iteration counters + sc_signal > stage1_iter,next_stage1_iter; + sc_signal next_ready_o; + sc_signal > next_data_o; + sc_signal data_ready,next_data_ready; + + //Conections to desround stage1 + sc_signal > stage1_L_i; + sc_signal > stage1_R_i; + sc_signal > stage1_round_key_i; + + sc_signal > stage1_iteration_i; + sc_signal > stage1_R_o; + sc_signal > stage1_L_o; + sc_signal > stage1_round_key_o; + + sc_signal > s1_stag1_i,s2_stag1_i,s3_stag1_i,s4_stag1_i,s5_stag1_i,s6_stag1_i,s7_stag1_i,s8_stag1_i; + sc_signal > s1_stag1_o,s2_stag1_o,s3_stag1_o,s4_stag1_o,s5_stag1_o,s6_stag1_o,s7_stag1_o,s8_stag1_o; + + void des_proc(); + void reg_signal(); + + desround *rd1; + + s1 *sbox1; + s2 *sbox2; + s3 *sbox3; + s4 *sbox4; + s5 *sbox5; + s6 *sbox6; + s7 *sbox7; + s8 *sbox8; + + SC_CTOR(des){ + + SC_METHOD(reg_signal); + sensitive_pos << clk; + sensitive_neg << reset; + + SC_METHOD(des_proc); + sensitive << data_i << key_i << load_i << stage1_iter << data_ready; + sensitive << stage1_L_o << stage1_R_o << stage1_round_key_o; + + rd1=new desround("round1"); + + sbox1=new s1("s1"); + sbox2=new s2("s2"); + sbox3=new s3("s3"); + sbox4=new s4("s4"); + sbox5=new s5("s5"); + sbox6=new s6("s6"); + sbox7=new s7("s7"); + sbox8=new s8("s8"); + + //For each stage in the pipe one instance + //First stage always present + rd1->clk(clk); + rd1->reset(reset); + rd1->iteration_i(stage1_iteration_i); + rd1->decrypt_i(decrypt_i); + rd1->R_i(stage1_R_i); + rd1->L_i(stage1_L_i); + rd1->Key_i(stage1_round_key_i); + rd1->R_o(stage1_R_o); + rd1->L_o(stage1_L_o); + rd1->Key_o(stage1_round_key_o); + rd1->s1_o(s1_stag1_i); + rd1->s2_o(s2_stag1_i); + rd1->s3_o(s3_stag1_i); + rd1->s4_o(s4_stag1_i); + rd1->s5_o(s5_stag1_i); + rd1->s6_o(s6_stag1_i); + rd1->s7_o(s7_stag1_i); + rd1->s8_o(s8_stag1_i); + rd1->s1_i(s1_stag1_o); + rd1->s2_i(s2_stag1_o); + rd1->s3_i(s3_stag1_o); + rd1->s4_i(s4_stag1_o); + rd1->s5_i(s5_stag1_o); + rd1->s6_i(s6_stag1_o); + rd1->s7_i(s7_stag1_o); + rd1->s8_i(s8_stag1_o); + + sbox1->stage1_input(s1_stag1_i); + sbox1->stage1_output(s1_stag1_o); + + sbox2->stage1_input(s2_stag1_i); + sbox2->stage1_output(s2_stag1_o); + + sbox3->stage1_input(s3_stag1_i); + sbox3->stage1_output(s3_stag1_o); + + sbox4->stage1_input(s4_stag1_i); + sbox4->stage1_output(s4_stag1_o); + + sbox5->stage1_input(s5_stag1_i); + sbox5->stage1_output(s5_stag1_o); + + sbox6->stage1_input(s6_stag1_i); + sbox6->stage1_output(s6_stag1_o); + + sbox7->stage1_input(s7_stag1_i); + sbox7->stage1_output(s7_stag1_o); + + sbox8->stage1_input(s8_stag1_i); + sbox8->stage1_output(s8_stag1_o); + + } +}; Index: systemcdes/tags/V10/rtl/systemc/key_gen.cpp =================================================================== --- systemcdes/tags/V10/rtl/systemc/key_gen.cpp (nonexistent) +++ systemcdes/tags/V10/rtl/systemc/key_gen.cpp (revision 11) @@ -0,0 +1,168 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Key generation module implementation //// +//// //// +//// This file is part of the SystemC DES //// +//// //// +//// Description: //// +//// Generate a key from the previous one //// +//// //// +//// To Do: //// +//// - nothing //// +//// //// +//// Author(s): //// +//// - Javier Castillo, jcastilo@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ + +#include "key_gen.h" + +void key_gen::generate_key(){ + + bool prev0,prev1; + + + sc_uint<56> prev_key_var,non_perm_key_var; + sc_uint<48> new_key_var; + sc_uint<28> semi_key; + + prev_key_var=previous_key.read(); + new_key_var=0; + new_key.write(0); + non_perm_key_var=0; + non_perm_key.write(0); + + if(!decrypt.read()){ + //Rotate left + switch(iteration.read()){ + case 0: + case 1: + case 8: + case 15: + //Rotate left one + semi_key=prev_key_var.range(55,28); + prev0=semi_key[27]; + semi_key=semi_key<<1; + semi_key[0]=prev0; + non_perm_key_var.range(55,28)=semi_key; + semi_key=prev_key_var.range(27,0); + prev0=semi_key[27]; + semi_key=semi_key<<1; + semi_key[0]=prev0; + non_perm_key_var.range(27,0)=semi_key; + break; + default: + //Rotate left two + semi_key=prev_key_var.range(55,28); + prev0=semi_key[27]; + prev1=semi_key[26]; + semi_key=semi_key<<2; + semi_key[1]=prev0; + semi_key[0]=prev1; + non_perm_key_var.range(55,28)=semi_key; + semi_key=prev_key_var.range(27,0); + prev0=semi_key[27]; + prev1=semi_key[26]; + semi_key=semi_key<<2; + semi_key[1]=prev0; + semi_key[0]=prev1; + non_perm_key_var.range(27,0)=semi_key; + } + }else{ + //Rotate rigth + switch(iteration.read()){ + case 0: + semi_key=prev_key_var.range(55,28); + non_perm_key_var.range(55,28)=semi_key; + semi_key=prev_key_var.range(27,0); + non_perm_key_var.range(27,0)=semi_key; + break; + case 1: + case 8: + case 15: + //Rotate rigth one + semi_key=prev_key_var.range(55,28); + prev0=semi_key[0]; + semi_key=semi_key>>1; + semi_key[27]=prev0; + non_perm_key_var.range(55,28)=semi_key; + semi_key=prev_key_var.range(27,0); + prev0=semi_key[0]; + semi_key=semi_key>>1; + semi_key[27]=prev0; + non_perm_key_var.range(27,0)=semi_key; + break; + default: + //Rotate left two + semi_key=prev_key_var.range(55,28); + prev0=semi_key[0]; + prev1=semi_key[1]; + semi_key=semi_key>>2; + semi_key[26]=prev0; + semi_key[27]=prev1; + non_perm_key_var.range(55,28)=semi_key; + semi_key=prev_key_var.range(27,0); + prev0=semi_key[0]; + prev1=semi_key[1]; + semi_key=semi_key>>2; + semi_key[26]=prev0; + semi_key[27]=prev1; + non_perm_key_var.range(27,0)=semi_key; + } + } + + non_perm_key.write(non_perm_key_var); + + //Apply PC_2 permutation + //Expand the data + new_key_var[47]=non_perm_key_var[42]; new_key_var[46]=non_perm_key_var[39]; new_key_var[45]=non_perm_key_var[45]; new_key_var[44]=non_perm_key_var[32]; + new_key_var[43]=non_perm_key_var[55]; new_key_var[42]=non_perm_key_var[51]; new_key_var[41]=non_perm_key_var[53]; new_key_var[40]=non_perm_key_var[28]; + + new_key_var[39]=non_perm_key_var[41]; new_key_var[38]=non_perm_key_var[50]; new_key_var[37]=non_perm_key_var[35]; new_key_var[36]=non_perm_key_var[46]; + new_key_var[35]=non_perm_key_var[33]; new_key_var[34]=non_perm_key_var[37]; new_key_var[33]=non_perm_key_var[44]; new_key_var[32]=non_perm_key_var[52]; + + new_key_var[31]=non_perm_key_var[30]; new_key_var[30]=non_perm_key_var[48]; new_key_var[29]=non_perm_key_var[40]; new_key_var[28]=non_perm_key_var[49]; + new_key_var[27]=non_perm_key_var[29]; new_key_var[26]=non_perm_key_var[36]; new_key_var[25]=non_perm_key_var[43]; new_key_var[24]=non_perm_key_var[54]; + + new_key_var[23]=non_perm_key_var[15]; new_key_var[22]=non_perm_key_var[4]; new_key_var[21]=non_perm_key_var[25]; new_key_var[20]=non_perm_key_var[19]; + new_key_var[19]=non_perm_key_var[9]; new_key_var[18]=non_perm_key_var[1]; new_key_var[17]=non_perm_key_var[26]; new_key_var[16]=non_perm_key_var[16]; + + new_key_var[15]=non_perm_key_var[5]; new_key_var[14]=non_perm_key_var[11]; new_key_var[13]=non_perm_key_var[23]; new_key_var[12]=non_perm_key_var[8]; + new_key_var[11]=non_perm_key_var[12]; new_key_var[10]=non_perm_key_var[7]; new_key_var[9]=non_perm_key_var[17]; new_key_var[8]=non_perm_key_var[0]; + + new_key_var[7]=non_perm_key_var[22]; new_key_var[6]=non_perm_key_var[3]; new_key_var[5]=non_perm_key_var[10]; new_key_var[4]=non_perm_key_var[14]; + new_key_var[3]=non_perm_key_var[6]; new_key_var[2]=non_perm_key_var[20]; new_key_var[1]=non_perm_key_var[27]; new_key_var[0]=non_perm_key_var[24]; + + new_key.write(new_key_var); + + +} Index: systemcdes/tags/V10/rtl/systemc/s1.cpp =================================================================== --- systemcdes/tags/V10/rtl/systemc/s1.cpp (nonexistent) +++ systemcdes/tags/V10/rtl/systemc/s1.cpp (revision 11) @@ -0,0 +1,118 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// SBOX 1 //// +//// //// +//// This file is part of the SystemC DES //// +//// //// +//// Description: //// +//// Sbox of DES algorithm //// +//// //// +//// To Do: //// +//// - done //// +//// //// +//// Author(s): //// +//// - Javier Castillo, jcastilo@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ + +#include "s1.h" + + +void s1::s1_box(){ + + switch(stage1_input.read()){ + case 0: stage1_output.write(14); break; + case 1: stage1_output.write(0); break; + case 2: stage1_output.write(4); break; + case 3: stage1_output.write(15); break; + case 4: stage1_output.write(13); break; + case 5: stage1_output.write(7); break; + case 6: stage1_output.write(1); break; + case 7: stage1_output.write(4); break; + case 8: stage1_output.write(2); break; + case 9: stage1_output.write(14); break; + case 10: stage1_output.write(15); break; + case 11: stage1_output.write(2); break; + case 12: stage1_output.write(11); break; + case 13: stage1_output.write(13); break; + case 14: stage1_output.write(8); break; + case 15: stage1_output.write(1); break; + case 16: stage1_output.write(3); break; + case 17: stage1_output.write(10); break; + case 18: stage1_output.write(10); break; + case 19: stage1_output.write(6); break; + case 20: stage1_output.write(6); break; + case 21: stage1_output.write(12); break; + case 22: stage1_output.write(12); break; + case 23: stage1_output.write(11); break; + case 24: stage1_output.write(5); break; + case 25: stage1_output.write(9); break; + case 26: stage1_output.write(9); break; + case 27: stage1_output.write(5); break; + case 28: stage1_output.write(0); break; + case 29: stage1_output.write(3); break; + case 30: stage1_output.write(7); break; + case 31: stage1_output.write(8); break; + case 32: stage1_output.write(4); break; + case 33: stage1_output.write(15); break; + case 34: stage1_output.write(1); break; + case 35: stage1_output.write(12); break; + case 36: stage1_output.write(14); break; + case 37: stage1_output.write(8); break; + case 38: stage1_output.write(8); break; + case 39: stage1_output.write(2); break; + case 40: stage1_output.write(13); break; + case 41: stage1_output.write(4); break; + case 42: stage1_output.write(6); break; + case 43: stage1_output.write(9); break; + case 44: stage1_output.write(2); break; + case 45: stage1_output.write(1); break; + case 46: stage1_output.write(11); break; + case 47: stage1_output.write(7); break; + case 48: stage1_output.write(15); break; + case 49: stage1_output.write(5); break; + case 50: stage1_output.write(12); break; + case 51: stage1_output.write(11); break; + case 52: stage1_output.write(9); break; + case 53: stage1_output.write(3); break; + case 54: stage1_output.write(7); break; + case 55: stage1_output.write(14); break; + case 56: stage1_output.write(3); break; + case 57: stage1_output.write(10); break; + case 58: stage1_output.write(10); break; + case 59: stage1_output.write(0); break; + case 60: stage1_output.write(5); break; + case 61: stage1_output.write(6); break; + case 62: stage1_output.write(0); break; + case 63: stage1_output.write(13); break; + } +} Index: systemcdes/tags/V10/rtl/systemc/s2.cpp =================================================================== --- systemcdes/tags/V10/rtl/systemc/s2.cpp (nonexistent) +++ systemcdes/tags/V10/rtl/systemc/s2.cpp (revision 11) @@ -0,0 +1,119 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// SBOX 2 //// +//// //// +//// This file is part of the SystemC DES //// +//// //// +//// Description: //// +//// Sbox of DES algorithm //// +//// //// +//// To Do: //// +//// - done //// +//// //// +//// Author(s): //// +//// - Javier Castillo, jcastilo@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ + +#include "s2.h" + + +void s2::s2_box(){ + + switch(stage1_input.read()){ + case 0: stage1_output.write(15); break; + case 1: stage1_output.write(3); break; + case 2: stage1_output.write(1); break; + case 3: stage1_output.write(13); break; + case 4: stage1_output.write(8); break; + case 5: stage1_output.write(4); break; + case 6: stage1_output.write(14); break; + case 7: stage1_output.write(7); break; + case 8: stage1_output.write(6); break; + case 9: stage1_output.write(15); break; + case 10: stage1_output.write(11); break; + case 11: stage1_output.write(2); break; + case 12: stage1_output.write(3); break; + case 13: stage1_output.write(8); break; + case 14: stage1_output.write(4); break; + case 15: stage1_output.write(14); break; + case 16: stage1_output.write(9); break; + case 17: stage1_output.write(12); break; + case 18: stage1_output.write(7); break; + case 19: stage1_output.write(0); break; + case 20: stage1_output.write(2); break; + case 21: stage1_output.write(1); break; + case 22: stage1_output.write(13); break; + case 23: stage1_output.write(10); break; + case 24: stage1_output.write(12); break; + case 25: stage1_output.write(6); break; + case 26: stage1_output.write(0); break; + case 27: stage1_output.write(9); break; + case 28: stage1_output.write(5); break; + case 29: stage1_output.write(11); break; + case 30: stage1_output.write(10); break; + case 31: stage1_output.write(5); break; + case 32: stage1_output.write(0); break; + case 33: stage1_output.write(13); break; + case 34: stage1_output.write(14); break; + case 35: stage1_output.write(8); break; + case 36: stage1_output.write(7); break; + case 37: stage1_output.write(10); break; + case 38: stage1_output.write(11); break; + case 39: stage1_output.write(1); break; + case 40: stage1_output.write(10); break; + case 41: stage1_output.write(3); break; + case 42: stage1_output.write(4); break; + case 43: stage1_output.write(15); break; + case 44: stage1_output.write(13); break; + case 45: stage1_output.write(4); break; + case 46: stage1_output.write(1); break; + case 47: stage1_output.write(2); break; + case 48: stage1_output.write(5); break; + case 49: stage1_output.write(11); break; + case 50: stage1_output.write(8); break; + case 51: stage1_output.write(6); break; + case 52: stage1_output.write(12); break; + case 53: stage1_output.write(7); break; + case 54: stage1_output.write(6); break; + case 55: stage1_output.write(12); break; + case 56: stage1_output.write(9); break; + case 57: stage1_output.write(0); break; + case 58: stage1_output.write(3); break; + case 59: stage1_output.write(5); break; + case 60: stage1_output.write(2); break; + case 61: stage1_output.write(14); break; + case 62: stage1_output.write(15); break; + case 63: stage1_output.write(9); break; + + } +} Index: systemcdes/tags/V10/rtl/systemc/s3.cpp =================================================================== --- systemcdes/tags/V10/rtl/systemc/s3.cpp (nonexistent) +++ systemcdes/tags/V10/rtl/systemc/s3.cpp (revision 11) @@ -0,0 +1,118 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// SBOX 3 //// +//// //// +//// This file is part of the SystemC DES //// +//// //// +//// Description: //// +//// Sbox of DES algorithm //// +//// //// +//// To Do: //// +//// - done //// +//// //// +//// Author(s): //// +//// - Javier Castillo, jcastilo@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ + +#include "s3.h" + + +void s3::s3_box(){ + switch(stage1_input.read()){ + case 0: stage1_output.write(10); break; + case 1: stage1_output.write(13); break; + case 2: stage1_output.write(0); break; + case 3: stage1_output.write(7); break; + case 4: stage1_output.write(9); break; + case 5: stage1_output.write(0); break; + case 6: stage1_output.write(14); break; + case 7: stage1_output.write(9); break; + case 8: stage1_output.write(6); break; + case 9: stage1_output.write(3); break; + case 10: stage1_output.write(3); break; + case 11: stage1_output.write(4); break; + case 12: stage1_output.write(15); break; + case 13: stage1_output.write(6); break; + case 14: stage1_output.write(5); break; + case 15: stage1_output.write(10); break; + case 16: stage1_output.write(1); break; + case 17: stage1_output.write(2); break; + case 18: stage1_output.write(13); break; + case 19: stage1_output.write(8); break; + case 20: stage1_output.write(12); break; + case 21: stage1_output.write(5); break; + case 22: stage1_output.write(7); break; + case 23: stage1_output.write(14); break; + case 24: stage1_output.write(11); break; + case 25: stage1_output.write(12); break; + case 26: stage1_output.write(4); break; + case 27: stage1_output.write(11); break; + case 28: stage1_output.write(2); break; + case 29: stage1_output.write(15); break; + case 30: stage1_output.write(8); break; + case 31: stage1_output.write(1); break; + case 32: stage1_output.write(13); break; + case 33: stage1_output.write(1); break; + case 34: stage1_output.write(6); break; + case 35: stage1_output.write(10); break; + case 36: stage1_output.write(4); break; + case 37: stage1_output.write(13); break; + case 38: stage1_output.write(9); break; + case 39: stage1_output.write(0); break; + case 40: stage1_output.write(8); break; + case 41: stage1_output.write(6); break; + case 42: stage1_output.write(15); break; + case 43: stage1_output.write(9); break; + case 44: stage1_output.write(3); break; + case 45: stage1_output.write(8); break; + case 46: stage1_output.write(0); break; + case 47: stage1_output.write(7); break; + case 48: stage1_output.write(11); break; + case 49: stage1_output.write(4); break; + case 50: stage1_output.write(1); break; + case 51: stage1_output.write(15); break; + case 52: stage1_output.write(2); break; + case 53: stage1_output.write(14); break; + case 54: stage1_output.write(12); break; + case 55: stage1_output.write(3); break; + case 56: stage1_output.write(5); break; + case 57: stage1_output.write(11); break; + case 58: stage1_output.write(10); break; + case 59: stage1_output.write(5); break; + case 60: stage1_output.write(14); break; + case 61: stage1_output.write(2); break; + case 62: stage1_output.write(7); break; + case 63: stage1_output.write(12); break; + } + +} Index: systemcdes/tags/V10/rtl/systemc/stimulus.cpp =================================================================== --- systemcdes/tags/V10/rtl/systemc/stimulus.cpp (nonexistent) +++ systemcdes/tags/V10/rtl/systemc/stimulus.cpp (revision 11) @@ -0,0 +1,83 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Random stimulus generation //// +//// //// +//// This file is part of the SystemC DES //// +//// //// +//// Description: //// +//// DES random stimulus //// +//// //// +//// To Do: //// +//// - nothing //// +//// //// +//// Author(s): //// +//// - Javier Castillo, jcastilo@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ + + + + +#include "stimulus.h" + +void test::tb(){ + + sc_uint<64> des_key_var,des_data_var; + bool decrypt_var; + + scv_random::set_global_seed(53246); + + random_generator rg("random_generator"); + + transactor->resetea(); + + while(1){ + + rg.des_key->next(); + rg.des_data->next(); + rg.decrypt->next(); + + + des_data_var=*(rg.des_data); + des_key_var=*(rg.des_key); + decrypt_var=*(rg.decrypt); + + if(!decrypt_var){ + cout << "Encrypt: 0x" << (int)des_data_var.range(63,32) << (int)des_data_var.range(31,0) << " 0x" << (int)des_key_var.range(63,32) << (int)des_key_var.range(31,0) << " " << sc_time_stamp() << endl; + transactor->encrypt(des_data_var,des_key_var); + }else{ + cout << "Decrypt: 0x" << (int)des_data_var.range(63,32) << (int)des_data_var.range(31,0) << " 0x" << (int)des_key_var.range(63,32) << (int)des_key_var.range(31,0) << " " << sc_time_stamp() << endl; + transactor->decrypt(des_data_var,des_key_var); + } + } + +} Index: systemcdes/tags/V10/rtl/systemc/s4.cpp =================================================================== --- systemcdes/tags/V10/rtl/systemc/s4.cpp (nonexistent) +++ systemcdes/tags/V10/rtl/systemc/s4.cpp (revision 11) @@ -0,0 +1,118 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// SBOX 4 //// +//// //// +//// This file is part of the SystemC DES //// +//// //// +//// Description: //// +//// Sbox of DES algorithm //// +//// //// +//// To Do: //// +//// - done //// +//// //// +//// Author(s): //// +//// - Javier Castillo, jcastilo@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ + +#include "s4.h" + + +void s4::s4_box(){ + switch(stage1_input.read()){ + case 0: stage1_output.write(7); break; + case 1: stage1_output.write(13); break; + case 2: stage1_output.write(13); break; + case 3: stage1_output.write(8); break; + case 4: stage1_output.write(14); break; + case 5: stage1_output.write(11); break; + case 6: stage1_output.write(3); break; + case 7: stage1_output.write(5); break; + case 8: stage1_output.write(0); break; + case 9: stage1_output.write(6); break; + case 10: stage1_output.write(6); break; + case 11: stage1_output.write(15); break; + case 12: stage1_output.write(9); break; + case 13: stage1_output.write(0); break; + case 14: stage1_output.write(10); break; + case 15: stage1_output.write(3); break; + case 16: stage1_output.write(1); break; + case 17: stage1_output.write(4); break; + case 18: stage1_output.write(2); break; + case 19: stage1_output.write(7); break; + case 20: stage1_output.write(8); break; + case 21: stage1_output.write(2); break; + case 22: stage1_output.write(5); break; + case 23: stage1_output.write(12); break; + case 24: stage1_output.write(11); break; + case 25: stage1_output.write(1); break; + case 26: stage1_output.write(12); break; + case 27: stage1_output.write(10); break; + case 28: stage1_output.write(4); break; + case 29: stage1_output.write(14); break; + case 30: stage1_output.write(15); break; + case 31: stage1_output.write(9); break; + case 32: stage1_output.write(10); break; + case 33: stage1_output.write(3); break; + case 34: stage1_output.write(6); break; + case 35: stage1_output.write(15); break; + case 36: stage1_output.write(9); break; + case 37: stage1_output.write(0); break; + case 38: stage1_output.write(0); break; + case 39: stage1_output.write(6); break; + case 40: stage1_output.write(12); break; + case 41: stage1_output.write(10); break; + case 42: stage1_output.write(11); break; + case 43: stage1_output.write(1); break; + case 44: stage1_output.write(7); break; + case 45: stage1_output.write(13); break; + case 46: stage1_output.write(13); break; + case 47: stage1_output.write(8); break; + case 48: stage1_output.write(15); break; + case 49: stage1_output.write(9); break; + case 50: stage1_output.write(1); break; + case 51: stage1_output.write(4); break; + case 52: stage1_output.write(3); break; + case 53: stage1_output.write(5); break; + case 54: stage1_output.write(14); break; + case 55: stage1_output.write(11); break; + case 56: stage1_output.write(5); break; + case 57: stage1_output.write(12); break; + case 58: stage1_output.write(2); break; + case 59: stage1_output.write(7); break; + case 60: stage1_output.write(8); break; + case 61: stage1_output.write(2); break; + case 62: stage1_output.write(4); break; + case 63: stage1_output.write(14); break; +} + +} Index: systemcdes/tags/V10/rtl/systemc/round.cpp =================================================================== --- systemcdes/tags/V10/rtl/systemc/round.cpp (nonexistent) +++ systemcdes/tags/V10/rtl/systemc/round.cpp (revision 11) @@ -0,0 +1,143 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Round of DES algorithm implementation //// +//// //// +//// This file is part of the SystemC DES //// +//// //// +//// Description: //// +//// This file perform a round of the DES algorithm //// +//// //// +//// To Do: //// +//// - nothing //// +//// //// +//// Author(s): //// +//// - Javier Castillo, jcastilo@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ + + +#include "round.h" + +void desround::registers(){ + + if(!reset.read()){ + L_o.write(0); + R_o.write(0); + Key_o.write(0); + }else{ + L_o.write(R_i.read()); + R_o.write(next_R.read()); + Key_o.write(non_perm_key.read()); + } +} + + + +void desround::round_proc(){ + + sc_uint<48> expandedR; + sc_uint<48> round_key; + sc_uint<48> KER; + sc_uint<32> R_i_var; + + sc_uint<32> Soutput; + sc_uint<32> f; + + R_i_var=R_i.read(); + + //Expand the data + expandedR[47]=R_i_var[0]; expandedR[46]=R_i_var[31]; expandedR[45]=R_i_var[30]; expandedR[44]=R_i_var[29]; + expandedR[43]=R_i_var[28]; expandedR[42]=R_i_var[27]; expandedR[41]=R_i_var[28]; expandedR[40]=R_i_var[27]; + + expandedR[39]=R_i_var[26]; expandedR[38]=R_i_var[25]; expandedR[37]=R_i_var[24]; expandedR[36]=R_i_var[23]; + expandedR[35]=R_i_var[24]; expandedR[34]=R_i_var[23]; expandedR[33]=R_i_var[22]; expandedR[32]=R_i_var[21]; + + expandedR[31]=R_i_var[20]; expandedR[30]=R_i_var[19]; expandedR[29]=R_i_var[20]; expandedR[28]=R_i_var[19]; + expandedR[27]=R_i_var[18]; expandedR[26]=R_i_var[17]; expandedR[25]=R_i_var[16]; expandedR[24]=R_i_var[15]; + + expandedR[23]=R_i_var[16]; expandedR[22]=R_i_var[15]; expandedR[21]=R_i_var[14]; expandedR[20]=R_i_var[13]; + expandedR[19]=R_i_var[12]; expandedR[18]=R_i_var[11]; expandedR[17]=R_i_var[12]; expandedR[16]=R_i_var[11]; + + expandedR[15]=R_i_var[10]; expandedR[14]=R_i_var[9]; expandedR[13]=R_i_var[8]; expandedR[12]=R_i_var[7]; + expandedR[11]=R_i_var[8]; expandedR[10]=R_i_var[7]; expandedR[9]=R_i_var[6]; expandedR[8]=R_i_var[5]; + + expandedR[7]=R_i_var[4]; expandedR[6]=R_i_var[3]; expandedR[5]=R_i_var[4]; expandedR[4]=R_i_var[3]; + expandedR[3]=R_i_var[2]; expandedR[2]=R_i_var[1]; expandedR[1]=R_i_var[0]; expandedR[0]=R_i_var[31]; + + //Generate the Key + previous_key.write(Key_i.read()); + iteration.write(iteration_i.read()); + decrypt.write(decrypt_i.read()); + + round_key=new_key.read(); + + //XOR the key with the block + KER=expandedR^round_key; + + //Apply Sboxes + s1_o.write(KER.range(47,42)); + s2_o.write(KER.range(41,36)); + s3_o.write(KER.range(35,30)); + s4_o.write(KER.range(29,24)); + s5_o.write(KER.range(23,18)); + s6_o.write(KER.range(17,12)); + s7_o.write(KER.range(11,6)); + s8_o.write(KER.range(5,0)); + + Soutput.range(31,28)=s1_i.read(); + Soutput.range(27,24)=s2_i.read(); + Soutput.range(23,20)=s3_i.read(); + Soutput.range(19,16)=s4_i.read(); + Soutput.range(15,12)=s5_i.read(); + Soutput.range(11,8)=s6_i.read(); + Soutput.range(7,4)=s7_i.read(); + Soutput.range(3,0)=s8_i.read(); + + //P permutation + + f[31]=Soutput[16]; f[30]=Soutput[25]; f[29]=Soutput[12]; f[28]=Soutput[11]; + f[27]=Soutput[3]; f[26]=Soutput[20]; f[25]=Soutput[4]; f[24]=Soutput[15]; + + f[23]=Soutput[31]; f[22]=Soutput[17]; f[21]=Soutput[9]; f[20]=Soutput[6]; + f[19]=Soutput[27]; f[18]=Soutput[14]; f[17]=Soutput[1]; f[16]=Soutput[22]; + + f[15]=Soutput[30]; f[14]=Soutput[24]; f[13]=Soutput[8]; f[12]=Soutput[18]; + f[11]=Soutput[0]; f[10]=Soutput[5]; f[9]=Soutput[29]; f[8]=Soutput[23]; + + f[7]=Soutput[13]; f[6]=Soutput[19]; f[5]=Soutput[2]; f[4]=Soutput[26]; + f[3]=Soutput[10]; f[2]=Soutput[21]; f[1]=Soutput[28]; f[0]=Soutput[7]; + + next_R.write(L_i.read()^f); + + expanRSig.write(L_i.read()^f); + + } Index: systemcdes/tags/V10/rtl/systemc/s5.cpp =================================================================== --- systemcdes/tags/V10/rtl/systemc/s5.cpp (nonexistent) +++ systemcdes/tags/V10/rtl/systemc/s5.cpp (revision 11) @@ -0,0 +1,118 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// SBOX 5 //// +//// //// +//// This file is part of the SystemC DES //// +//// //// +//// Description: //// +//// Sbox of DES algorithm //// +//// //// +//// To Do: //// +//// - done //// +//// //// +//// Author(s): //// +//// - Javier Castillo, jcastilo@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ + +#include "s5.h" + +void s5::s5_box(){ + switch(stage1_input.read()){ + case 0: stage1_output.write(2); break; + case 1: stage1_output.write(14); break; + case 2: stage1_output.write(12); break; + case 3: stage1_output.write(11); break; + case 4: stage1_output.write(4); break; + case 5: stage1_output.write(2); break; + case 6: stage1_output.write(1); break; + case 7: stage1_output.write(12); break; + case 8: stage1_output.write(7); break; + case 9: stage1_output.write(4); break; + case 10: stage1_output.write(10); break; + case 11: stage1_output.write(7); break; + case 12: stage1_output.write(11); break; + case 13: stage1_output.write(13); break; + case 14: stage1_output.write(6); break; + case 15: stage1_output.write(1); break; + case 16: stage1_output.write(8); break; + case 17: stage1_output.write(5); break; + case 18: stage1_output.write(5); break; + case 19: stage1_output.write(0); break; + case 20: stage1_output.write(3); break; + case 21: stage1_output.write(15); break; + case 22: stage1_output.write(15); break; + case 23: stage1_output.write(10); break; + case 24: stage1_output.write(13); break; + case 25: stage1_output.write(3); break; + case 26: stage1_output.write(0); break; + case 27: stage1_output.write(9); break; + case 28: stage1_output.write(14); break; + case 29: stage1_output.write(8); break; + case 30: stage1_output.write(9); break; + case 31: stage1_output.write(6); break; + case 32: stage1_output.write(4); break; + case 33: stage1_output.write(11); break; + case 34: stage1_output.write(2); break; + case 35: stage1_output.write(8); break; + case 36: stage1_output.write(1); break; + case 37: stage1_output.write(12); break; + case 38: stage1_output.write(11); break; + case 39: stage1_output.write(7); break; + case 40: stage1_output.write(10); break; + case 41: stage1_output.write(1); break; + case 42: stage1_output.write(13); break; + case 43: stage1_output.write(14); break; + case 44: stage1_output.write(7); break; + case 45: stage1_output.write(2); break; + case 46: stage1_output.write(8); break; + case 47: stage1_output.write(13); break; + case 48: stage1_output.write(15); break; + case 49: stage1_output.write(6); break; + case 50: stage1_output.write(9); break; + case 51: stage1_output.write(15); break; + case 52: stage1_output.write(12); break; + case 53: stage1_output.write(0); break; + case 54: stage1_output.write(5); break; + case 55: stage1_output.write(9); break; + case 56: stage1_output.write(6); break; + case 57: stage1_output.write(10); break; + case 58: stage1_output.write(3); break; + case 59: stage1_output.write(4); break; + case 60: stage1_output.write(0); break; + case 61: stage1_output.write(5); break; + case 62: stage1_output.write(14); break; + case 63: stage1_output.write(3); break; +} + + +} Index: systemcdes/tags/V10/rtl/systemc/s6.cpp =================================================================== --- systemcdes/tags/V10/rtl/systemc/s6.cpp (nonexistent) +++ systemcdes/tags/V10/rtl/systemc/s6.cpp (revision 11) @@ -0,0 +1,118 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// SBOX 6 //// +//// //// +//// This file is part of the SystemC DES //// +//// //// +//// Description: //// +//// Sbox of DES algorithm //// +//// //// +//// To Do: //// +//// - done //// +//// //// +//// Author(s): //// +//// - Javier Castillo, jcastilo@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ + +#include "s6.h" + +void s6::s6_box(){ + switch(stage1_input.read()){ + case 0: stage1_output.write(12); break; + case 1: stage1_output.write(10); break; + case 2: stage1_output.write(1); break; + case 3: stage1_output.write(15); break; + case 4: stage1_output.write(10); break; + case 5: stage1_output.write(4); break; + case 6: stage1_output.write(15); break; + case 7: stage1_output.write(2); break; + case 8: stage1_output.write(9); break; + case 9: stage1_output.write(7); break; + case 10: stage1_output.write(2); break; + case 11: stage1_output.write(12); break; + case 12: stage1_output.write(6); break; + case 13: stage1_output.write(9); break; + case 14: stage1_output.write(8); break; + case 15: stage1_output.write(5); break; + case 16: stage1_output.write(0); break; + case 17: stage1_output.write(6); break; + case 18: stage1_output.write(13); break; + case 19: stage1_output.write(1); break; + case 20: stage1_output.write(3); break; + case 21: stage1_output.write(13); break; + case 22: stage1_output.write(4); break; + case 23: stage1_output.write(14); break; + case 24: stage1_output.write(14); break; + case 25: stage1_output.write(0); break; + case 26: stage1_output.write(7); break; + case 27: stage1_output.write(11); break; + case 28: stage1_output.write(5); break; + case 29: stage1_output.write(3); break; + case 30: stage1_output.write(11); break; + case 31: stage1_output.write(8); break; + case 32: stage1_output.write(9); break; + case 33: stage1_output.write(4); break; + case 34: stage1_output.write(14); break; + case 35: stage1_output.write(3); break; + case 36: stage1_output.write(15); break; + case 37: stage1_output.write(2); break; + case 38: stage1_output.write(5); break; + case 39: stage1_output.write(12); break; + case 40: stage1_output.write(2); break; + case 41: stage1_output.write(9); break; + case 42: stage1_output.write(8); break; + case 43: stage1_output.write(5); break; + case 44: stage1_output.write(12); break; + case 45: stage1_output.write(15); break; + case 46: stage1_output.write(3); break; + case 47: stage1_output.write(10); break; + case 48: stage1_output.write(7); break; + case 49: stage1_output.write(11); break; + case 50: stage1_output.write(0); break; + case 51: stage1_output.write(14); break; + case 52: stage1_output.write(4); break; + case 53: stage1_output.write(1); break; + case 54: stage1_output.write(10); break; + case 55: stage1_output.write(7); break; + case 56: stage1_output.write(1); break; + case 57: stage1_output.write(6); break; + case 58: stage1_output.write(13); break; + case 59: stage1_output.write(0); break; + case 60: stage1_output.write(11); break; + case 61: stage1_output.write(8); break; + case 62: stage1_output.write(6); break; + case 63: stage1_output.write(13); break; +} + + +} Index: systemcdes/tags/V10/rtl/systemc/s7.cpp =================================================================== --- systemcdes/tags/V10/rtl/systemc/s7.cpp (nonexistent) +++ systemcdes/tags/V10/rtl/systemc/s7.cpp (revision 11) @@ -0,0 +1,118 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// SBOX 7 //// +//// //// +//// This file is part of the SystemC DES //// +//// //// +//// Description: //// +//// Sbox of DES algorithm //// +//// //// +//// To Do: //// +//// - done //// +//// //// +//// Author(s): //// +//// - Javier Castillo, jcastilo@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ + +#include "s7.h" + +void s7::s7_box(){ + switch(stage1_input.read()){ + case 0: stage1_output.write(4); break; + case 1: stage1_output.write(13); break; + case 2: stage1_output.write(11); break; + case 3: stage1_output.write(0); break; + case 4: stage1_output.write(2); break; + case 5: stage1_output.write(11); break; + case 6: stage1_output.write(14); break; + case 7: stage1_output.write(7); break; + case 8: stage1_output.write(15); break; + case 9: stage1_output.write(4); break; + case 10: stage1_output.write(0); break; + case 11: stage1_output.write(9); break; + case 12: stage1_output.write(8); break; + case 13: stage1_output.write(1); break; + case 14: stage1_output.write(13); break; + case 15: stage1_output.write(10); break; + case 16: stage1_output.write(3); break; + case 17: stage1_output.write(14); break; + case 18: stage1_output.write(12); break; + case 19: stage1_output.write(3); break; + case 20: stage1_output.write(9); break; + case 21: stage1_output.write(5); break; + case 22: stage1_output.write(7); break; + case 23: stage1_output.write(12); break; + case 24: stage1_output.write(5); break; + case 25: stage1_output.write(2); break; + case 26: stage1_output.write(10); break; + case 27: stage1_output.write(15); break; + case 28: stage1_output.write(6); break; + case 29: stage1_output.write(8); break; + case 30: stage1_output.write(1); break; + case 31: stage1_output.write(6); break; + case 32: stage1_output.write(1); break; + case 33: stage1_output.write(6); break; + case 34: stage1_output.write(4); break; + case 35: stage1_output.write(11); break; + case 36: stage1_output.write(11); break; + case 37: stage1_output.write(13); break; + case 38: stage1_output.write(13); break; + case 39: stage1_output.write(8); break; + case 40: stage1_output.write(12); break; + case 41: stage1_output.write(1); break; + case 42: stage1_output.write(3); break; + case 43: stage1_output.write(4); break; + case 44: stage1_output.write(7); break; + case 45: stage1_output.write(10); break; + case 46: stage1_output.write(14); break; + case 47: stage1_output.write(7); break; + case 48: stage1_output.write(10); break; + case 49: stage1_output.write(9); break; + case 50: stage1_output.write(15); break; + case 51: stage1_output.write(5); break; + case 52: stage1_output.write(6); break; + case 53: stage1_output.write(0); break; + case 54: stage1_output.write(8); break; + case 55: stage1_output.write(15); break; + case 56: stage1_output.write(0); break; + case 57: stage1_output.write(14); break; + case 58: stage1_output.write(5); break; + case 59: stage1_output.write(2); break; + case 60: stage1_output.write(9); break; + case 61: stage1_output.write(3); break; + case 62: stage1_output.write(2); break; + case 63: stage1_output.write(12); break; +} + + +} Index: systemcdes/tags/V10/rtl/systemc/s8.cpp =================================================================== --- systemcdes/tags/V10/rtl/systemc/s8.cpp (nonexistent) +++ systemcdes/tags/V10/rtl/systemc/s8.cpp (revision 11) @@ -0,0 +1,119 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// SBOX 8 //// +//// //// +//// This file is part of the SystemC DES //// +//// //// +//// Description: //// +//// Sbox of DES algorithm //// +//// //// +//// To Do: //// +//// - done //// +//// //// +//// Author(s): //// +//// - Javier Castillo, jcastilo@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ + + +#include "s8.h" + + +void s8::s8_box(){ + switch(stage1_input.read()){ + case 0: stage1_output.write(13); break; + case 1: stage1_output.write(1); break; + case 2: stage1_output.write(2); break; + case 3: stage1_output.write(15); break; + case 4: stage1_output.write(8); break; + case 5: stage1_output.write(13); break; + case 6: stage1_output.write(4); break; + case 7: stage1_output.write(8); break; + case 8: stage1_output.write(6); break; + case 9: stage1_output.write(10); break; + case 10: stage1_output.write(15); break; + case 11: stage1_output.write(3); break; + case 12: stage1_output.write(11); break; + case 13: stage1_output.write(7); break; + case 14: stage1_output.write(1); break; + case 15: stage1_output.write(4); break; + case 16: stage1_output.write(10); break; + case 17: stage1_output.write(12); break; + case 18: stage1_output.write(9); break; + case 19: stage1_output.write(5); break; + case 20: stage1_output.write(3); break; + case 21: stage1_output.write(6); break; + case 22: stage1_output.write(14); break; + case 23: stage1_output.write(11); break; + case 24: stage1_output.write(5); break; + case 25: stage1_output.write(0); break; + case 26: stage1_output.write(0); break; + case 27: stage1_output.write(14); break; + case 28: stage1_output.write(12); break; + case 29: stage1_output.write(9); break; + case 30: stage1_output.write(7); break; + case 31: stage1_output.write(2); break; + case 32: stage1_output.write(7); break; + case 33: stage1_output.write(2); break; + case 34: stage1_output.write(11); break; + case 35: stage1_output.write(1); break; + case 36: stage1_output.write(4); break; + case 37: stage1_output.write(14); break; + case 38: stage1_output.write(1); break; + case 39: stage1_output.write(7); break; + case 40: stage1_output.write(9); break; + case 41: stage1_output.write(4); break; + case 42: stage1_output.write(12); break; + case 43: stage1_output.write(10); break; + case 44: stage1_output.write(14); break; + case 45: stage1_output.write(8); break; + case 46: stage1_output.write(2); break; + case 47: stage1_output.write(13); break; + case 48: stage1_output.write(0); break; + case 49: stage1_output.write(15); break; + case 50: stage1_output.write(6); break; + case 51: stage1_output.write(12); break; + case 52: stage1_output.write(10); break; + case 53: stage1_output.write(9); break; + case 54: stage1_output.write(13); break; + case 55: stage1_output.write(0); break; + case 56: stage1_output.write(15); break; + case 57: stage1_output.write(3); break; + case 58: stage1_output.write(3); break; + case 59: stage1_output.write(5); break; + case 60: stage1_output.write(5); break; + case 61: stage1_output.write(6); break; + case 62: stage1_output.write(8); break; + case 63: stage1_output.write(11); break; +} + +} Index: systemcdes/tags/V10/rtl/verilog/des.v =================================================================== --- systemcdes/tags/V10/rtl/verilog/des.v (nonexistent) +++ systemcdes/tags/V10/rtl/verilog/des.v (revision 11) @@ -0,0 +1,281 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// DES Top //// +//// //// +//// This file is part of the SystemC DES //// +//// //// +//// Description: //// +//// Top file of DES project //// +//// //// +//// Generated automatically using SystemC to Verilog translator //// +//// //// +//// To Do: //// +//// - done //// +//// //// +//// Author(s): //// +//// - Javier Castillo, jcastilo@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ + + +module des(clk,reset,load_i,decrypt_i,data_i,key_i,data_o,ready_o); +input clk; +input reset; +input load_i; +input decrypt_i; +input [63:0] data_i; +input [63:0] key_i; +output [63:0] data_o; +output ready_o; + +reg [63:0] data_o; +reg ready_o; + + +reg [3:0] stage1_iter; + +reg [3:0] next_stage1_iter; + +reg next_ready_o; + +reg[63:0] next_data_o; + +reg data_ready; + +reg next_data_ready; + +reg [31:0] stage1_L_i; + +reg [31:0] stage1_R_i; + +reg [55:0] stage1_round_key_i; + +reg [3:0] stage1_iteration_i; +wire [31:0] stage1_R_o; +wire [31:0] stage1_L_o; +wire [55:0] stage1_round_key_o; +wire [5:0] s1_stag1_i; +wire [5:0] s2_stag1_i; +wire [5:0] s3_stag1_i; +wire [5:0] s4_stag1_i; +wire [5:0] s5_stag1_i; +wire [5:0] s6_stag1_i; +wire [5:0] s7_stag1_i; +wire [5:0] s8_stag1_i; +wire [3:0] s1_stag1_o; +wire [3:0] s2_stag1_o; +wire [3:0] s3_stag1_o; +wire [3:0] s4_stag1_o; +wire [3:0] s5_stag1_o; +wire [3:0] s6_stag1_o; +wire [3:0] s7_stag1_o; +wire [3:0] s8_stag1_o; + +reg[31:0] L_i_var,R_i_var; +reg[63:0] data_i_var,data_o_var,data_o_var_t,key_i_var; +reg[55:0] key_var_perm; + + +desround rd1 (.clk(clk), .reset(reset), .iteration_i(stage1_iteration_i), .decrypt_i(decrypt_i), .R_i(stage1_R_i), .L_i(stage1_L_i), .Key_i(stage1_round_key_i), .R_o(stage1_R_o), .L_o(stage1_L_o), .Key_o(stage1_round_key_o), .s1_o(s1_stag1_i), .s2_o(s2_stag1_i), .s3_o(s3_stag1_i), .s4_o(s4_stag1_i), .s5_o(s5_stag1_i), .s6_o(s6_stag1_i), .s7_o(s7_stag1_i), .s8_o(s8_stag1_i), .s1_i(s1_stag1_o), .s2_i(s2_stag1_o), .s3_i(s3_stag1_o), .s4_i(s4_stag1_o), .s5_i(s5_stag1_o), .s6_i(s6_stag1_o), .s7_i(s7_stag1_o), .s8_i(s8_stag1_o)); +s1 sbox1 (.stage1_input(s1_stag1_i), .stage1_output(s1_stag1_o)); +s2 sbox2 (.stage1_input(s2_stag1_i), .stage1_output(s2_stag1_o)); +s3 sbox3 (.stage1_input(s3_stag1_i), .stage1_output(s3_stag1_o)); +s4 sbox4 (.stage1_input(s4_stag1_i), .stage1_output(s4_stag1_o)); +s5 sbox5 (.stage1_input(s5_stag1_i), .stage1_output(s5_stag1_o)); +s6 sbox6 (.stage1_input(s6_stag1_i), .stage1_output(s6_stag1_o)); +s7 sbox7 (.stage1_input(s7_stag1_i), .stage1_output(s7_stag1_o)); +s8 sbox8 (.stage1_input(s8_stag1_i), .stage1_output(s8_stag1_o)); + +always @(posedge clk or negedge reset) + +begin + + if(!reset) + begin + + ready_o = (0); + data_o = (0); + stage1_iter = (0); + data_ready = (1); + + end + else + begin + + ready_o = (next_ready_o); + data_o = (next_data_o); + stage1_iter = (next_stage1_iter); + data_ready = (next_data_ready); + + end +end + + +always @( data_i or key_i or load_i or stage1_iter or data_ready or stage1_R_o or stage1_L_o or stage1_round_key_o) + +begin + + + + L_i_var=0; + R_i_var=0; + data_i_var=0; + + next_ready_o = (0); + next_data_ready = (data_ready); + next_stage1_iter = (stage1_iter); + + stage1_L_i = (0); + stage1_R_i = (0); + stage1_round_key_i = (0); + + + key_i_var=key_i; + + key_var_perm[55]=key_i_var[7];key_var_perm[54]=key_i_var[15];key_var_perm[53]=key_i_var[23];key_var_perm[52]=key_i_var[31]; + key_var_perm[51]=key_i_var[39];key_var_perm[50]=key_i_var[47];key_var_perm[49]=key_i_var[55];key_var_perm[48]=key_i_var[63]; + + key_var_perm[47]=key_i_var[6];key_var_perm[46]=key_i_var[14];key_var_perm[45]=key_i_var[22];key_var_perm[44]=key_i_var[30]; + key_var_perm[43]=key_i_var[38];key_var_perm[42]=key_i_var[46];key_var_perm[41]=key_i_var[54];key_var_perm[40]=key_i_var[62]; + + key_var_perm[39]=key_i_var[5];key_var_perm[38]=key_i_var[13];key_var_perm[37]=key_i_var[21];key_var_perm[36]=key_i_var[29]; + key_var_perm[35]=key_i_var[37];key_var_perm[34]=key_i_var[45];key_var_perm[33]=key_i_var[53];key_var_perm[32]=key_i_var[61]; + + key_var_perm[31]=key_i_var[4];key_var_perm[30]=key_i_var[12];key_var_perm[29]=key_i_var[20];key_var_perm[28]=key_i_var[28]; + key_var_perm[27]=key_i_var[1];key_var_perm[26]=key_i_var[9];key_var_perm[25]=key_i_var[17];key_var_perm[24]=key_i_var[25]; + + key_var_perm[23]=key_i_var[33];key_var_perm[22]=key_i_var[41];key_var_perm[21]=key_i_var[49];key_var_perm[20]=key_i_var[57]; + key_var_perm[19]=key_i_var[2];key_var_perm[18]=key_i_var[10];key_var_perm[17]=key_i_var[18];key_var_perm[16]=key_i_var[26]; + + key_var_perm[15]=key_i_var[34];key_var_perm[14]=key_i_var[42];key_var_perm[13]=key_i_var[50];key_var_perm[12]=key_i_var[58]; + key_var_perm[11]=key_i_var[3];key_var_perm[10]=key_i_var[11];key_var_perm[9]=key_i_var[19];key_var_perm[8]=key_i_var[27]; + + key_var_perm[7]=key_i_var[35];key_var_perm[6]=key_i_var[43];key_var_perm[5]=key_i_var[51];key_var_perm[4]=key_i_var[59]; + key_var_perm[3]=key_i_var[36];key_var_perm[2]=key_i_var[44];key_var_perm[1]=key_i_var[52];key_var_perm[0]=key_i_var[60]; + + + data_i_var=data_i; + L_i_var[31]=data_i_var[6];L_i_var[30]=data_i_var[14];L_i_var[29]=data_i_var[22];L_i_var[28]=data_i_var[30]; + L_i_var[27]=data_i_var[38];L_i_var[26]=data_i_var[46];L_i_var[25]=data_i_var[54];L_i_var[24]=data_i_var[62]; + + L_i_var[23]=data_i_var[4];L_i_var[22]=data_i_var[12];L_i_var[21]=data_i_var[20];L_i_var[20]=data_i_var[28]; + L_i_var[19]=data_i_var[36];L_i_var[18]=data_i_var[44];L_i_var[17]=data_i_var[52];L_i_var[16]=data_i_var[60]; + + L_i_var[15]=data_i_var[2];L_i_var[14]=data_i_var[10];L_i_var[13]=data_i_var[18];L_i_var[12]=data_i_var[26]; + L_i_var[11]=data_i_var[34];L_i_var[10]=data_i_var[42];L_i_var[9]=data_i_var[50];L_i_var[8]=data_i_var[58]; + + L_i_var[7]=data_i_var[0];L_i_var[6]=data_i_var[8];L_i_var[5]=data_i_var[16];L_i_var[4]=data_i_var[24]; + L_i_var[3]=data_i_var[32];L_i_var[2]=data_i_var[40];L_i_var[1]=data_i_var[48];L_i_var[0]=data_i_var[56]; + + R_i_var[31]=data_i_var[7];R_i_var[30]=data_i_var[15];R_i_var[29]=data_i_var[23];R_i_var[28]=data_i_var[31]; + R_i_var[27]=data_i_var[39];R_i_var[26]=data_i_var[47];R_i_var[25]=data_i_var[55];R_i_var[24]=data_i_var[63]; + + R_i_var[23]=data_i_var[5];R_i_var[22]=data_i_var[13];R_i_var[21]=data_i_var[21];R_i_var[20]=data_i_var[29]; + R_i_var[19]=data_i_var[37];R_i_var[18]=data_i_var[45];R_i_var[17]=data_i_var[53];R_i_var[16]=data_i_var[61]; + + R_i_var[15]=data_i_var[3];R_i_var[14]=data_i_var[11];R_i_var[13]=data_i_var[19];R_i_var[12]=data_i_var[27]; + R_i_var[11]=data_i_var[35];R_i_var[10]=data_i_var[43];R_i_var[9]=data_i_var[51];R_i_var[8]=data_i_var[59]; + + R_i_var[7]=data_i_var[1];R_i_var[6]=data_i_var[9];R_i_var[5]=data_i_var[17];R_i_var[4]=data_i_var[25]; + R_i_var[3]=data_i_var[33];R_i_var[2]=data_i_var[41];R_i_var[1]=data_i_var[49];R_i_var[0]=data_i_var[57]; + + + + data_o_var_t[63:32]=stage1_R_o; + data_o_var_t[31:0]=stage1_L_o; + + data_o_var[63]=data_o_var_t[24];data_o_var[62]=data_o_var_t[56];data_o_var[61]=data_o_var_t[16];data_o_var[60]=data_o_var_t[48]; + data_o_var[59]=data_o_var_t[8];data_o_var[58]=data_o_var_t[40];data_o_var[57]=data_o_var_t[0];data_o_var[56]=data_o_var_t[32]; + + data_o_var[55]=data_o_var_t[25];data_o_var[54]=data_o_var_t[57];data_o_var[53]=data_o_var_t[17];data_o_var[52]=data_o_var_t[49]; + data_o_var[51]=data_o_var_t[9];data_o_var[50]=data_o_var_t[41];data_o_var[49]=data_o_var_t[1];data_o_var[48]=data_o_var_t[33]; + + data_o_var[47]=data_o_var_t[26];data_o_var[46]=data_o_var_t[58];data_o_var[45]=data_o_var_t[18];data_o_var[44]=data_o_var_t[50]; + data_o_var[43]=data_o_var_t[10];data_o_var[42]=data_o_var_t[42];data_o_var[41]=data_o_var_t[2];data_o_var[40]=data_o_var_t[34]; + + data_o_var[39]=data_o_var_t[27];data_o_var[38]=data_o_var_t[59];data_o_var[37]=data_o_var_t[19];data_o_var[36]=data_o_var_t[51]; + data_o_var[35]=data_o_var_t[11];data_o_var[34]=data_o_var_t[43];data_o_var[33]=data_o_var_t[3];data_o_var[32]=data_o_var_t[35]; + + data_o_var[31]=data_o_var_t[28];data_o_var[30]=data_o_var_t[60];data_o_var[29]=data_o_var_t[20];data_o_var[28]=data_o_var_t[52]; + data_o_var[27]=data_o_var_t[12];data_o_var[26]=data_o_var_t[44];data_o_var[25]=data_o_var_t[4];data_o_var[24]=data_o_var_t[36]; + + data_o_var[23]=data_o_var_t[29];data_o_var[22]=data_o_var_t[61];data_o_var[21]=data_o_var_t[21];data_o_var[20]=data_o_var_t[53]; + data_o_var[19]=data_o_var_t[13];data_o_var[18]=data_o_var_t[45];data_o_var[17]=data_o_var_t[5];data_o_var[16]=data_o_var_t[37]; + + data_o_var[15]=data_o_var_t[30];data_o_var[14]=data_o_var_t[62];data_o_var[13]=data_o_var_t[22];data_o_var[12]=data_o_var_t[54]; + data_o_var[11]=data_o_var_t[14];data_o_var[10]=data_o_var_t[46];data_o_var[9]=data_o_var_t[6];data_o_var[8]=data_o_var_t[38]; + + data_o_var[7]=data_o_var_t[31];data_o_var[6]=data_o_var_t[63];data_o_var[5]=data_o_var_t[23];data_o_var[4]=data_o_var_t[55]; + data_o_var[3]=data_o_var_t[15];data_o_var[2]=data_o_var_t[47];data_o_var[1]=data_o_var_t[7];data_o_var[0]=data_o_var_t[39]; + + next_data_o = (data_o_var); + + stage1_iteration_i = (stage1_iter); + + next_ready_o = (0); + stage1_L_i = (stage1_L_o); + stage1_R_i = (stage1_R_o); + stage1_round_key_i = (stage1_round_key_o); + + case(stage1_iter) + + 0: + begin + if(load_i) + begin + next_stage1_iter = (1); + stage1_L_i = (L_i_var); + stage1_R_i = (R_i_var); + stage1_round_key_i = (key_var_perm); + next_data_ready = (0); + end + else if (!data_ready) + begin + + next_stage1_iter = (0); + next_ready_o = (1); + next_data_ready = (1); + end + end + + 15: + next_stage1_iter = (0); + + default: + next_stage1_iter = (stage1_iter+1); + +endcase + + +end + +endmodule Index: systemcdes/tags/V10/rtl/verilog/key_gen.v =================================================================== --- systemcdes/tags/V10/rtl/verilog/key_gen.v (nonexistent) +++ systemcdes/tags/V10/rtl/verilog/key_gen.v (revision 11) @@ -0,0 +1,189 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Key generator //// +//// //// +//// This file is part of the SystemC DES //// +//// //// +//// Description: //// +//// Generate the next key from the previous one //// +//// //// +//// Generated automatically using SystemC to Verilog translator //// +//// //// +//// To Do: //// +//// - done //// +//// //// +//// Author(s): //// +//// - Javier Castillo, jcastilo@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ + + +module key_gen(previous_key,iteration,decrypt,non_perm_key,new_key); + +input [55:0] previous_key; +input [3:0] iteration; +input decrypt; +output [55:0] non_perm_key; +output [47:0] new_key; + +reg [55:0] non_perm_key; +reg [47:0] new_key; + + +reg prev0,prev1; +reg[55:0] prev_key_var,non_perm_key_var; +reg[47:0] new_key_var; +reg[27:0] semi_key; + + +always @( previous_key or iteration or decrypt) + +begin + + + + prev_key_var=previous_key; + new_key_var=0; + new_key = (0); + non_perm_key_var=0; + non_perm_key = (0); + + if(!decrypt) + begin + case(iteration) + + 0, 1, 8, 15: + begin + semi_key=prev_key_var[55:28]; + prev0=semi_key[27]; + semi_key=semi_key<<1; + semi_key[0]=prev0; + non_perm_key_var[55:28]=semi_key; + semi_key=prev_key_var[27:0]; + prev0=semi_key[27]; + semi_key=semi_key<<1; + semi_key[0]=prev0; + non_perm_key_var[27:0]=semi_key; + end + default: + begin + semi_key=prev_key_var[55:28]; + prev0=semi_key[27]; + prev1=semi_key[26]; + semi_key=semi_key<<2; + semi_key[1]=prev0; + semi_key[0]=prev1; + non_perm_key_var[55:28]=semi_key; + semi_key=prev_key_var[27:0]; + prev0=semi_key[27]; + prev1=semi_key[26]; + semi_key=semi_key<<2; + semi_key[1]=prev0; + semi_key[0]=prev1; + non_perm_key_var[27:0]=semi_key; + end + + endcase + end + else + begin + case(iteration) + + 0: + begin + semi_key=prev_key_var[55:28]; + non_perm_key_var[55:28]=semi_key; + semi_key=prev_key_var[27:0]; + non_perm_key_var[27:0]=semi_key; + end + 1, 8, 15: + begin + semi_key=prev_key_var[55:28]; + prev0=semi_key[0]; + semi_key=semi_key>>1; + semi_key[27]=prev0; + non_perm_key_var[55:28]=semi_key; + semi_key=prev_key_var[27:0]; + prev0=semi_key[0]; + semi_key=semi_key>>1; + semi_key[27]=prev0; + non_perm_key_var[27:0]=semi_key; + end + default: + begin + semi_key=prev_key_var[55:28]; + prev0=semi_key[0]; + prev1=semi_key[1]; + semi_key=semi_key>>2; + semi_key[26]=prev0; + semi_key[27]=prev1; + non_perm_key_var[55:28]=semi_key; + semi_key=prev_key_var[27:0]; + prev0=semi_key[0]; + prev1=semi_key[1]; + semi_key=semi_key>>2; + semi_key[26]=prev0; + semi_key[27]=prev1; + non_perm_key_var[27:0]=semi_key; + end + + endcase + end + + + non_perm_key = (non_perm_key_var); + + + new_key_var[47]=non_perm_key_var[42]; new_key_var[46]=non_perm_key_var[39]; new_key_var[45]=non_perm_key_var[45]; new_key_var[44]=non_perm_key_var[32]; + new_key_var[43]=non_perm_key_var[55]; new_key_var[42]=non_perm_key_var[51]; new_key_var[41]=non_perm_key_var[53]; new_key_var[40]=non_perm_key_var[28]; + + new_key_var[39]=non_perm_key_var[41]; new_key_var[38]=non_perm_key_var[50]; new_key_var[37]=non_perm_key_var[35]; new_key_var[36]=non_perm_key_var[46]; + new_key_var[35]=non_perm_key_var[33]; new_key_var[34]=non_perm_key_var[37]; new_key_var[33]=non_perm_key_var[44]; new_key_var[32]=non_perm_key_var[52]; + + new_key_var[31]=non_perm_key_var[30]; new_key_var[30]=non_perm_key_var[48]; new_key_var[29]=non_perm_key_var[40]; new_key_var[28]=non_perm_key_var[49]; + new_key_var[27]=non_perm_key_var[29]; new_key_var[26]=non_perm_key_var[36]; new_key_var[25]=non_perm_key_var[43]; new_key_var[24]=non_perm_key_var[54]; + + new_key_var[23]=non_perm_key_var[15]; new_key_var[22]=non_perm_key_var[4]; new_key_var[21]=non_perm_key_var[25]; new_key_var[20]=non_perm_key_var[19]; + new_key_var[19]=non_perm_key_var[9]; new_key_var[18]=non_perm_key_var[1]; new_key_var[17]=non_perm_key_var[26]; new_key_var[16]=non_perm_key_var[16]; + + new_key_var[15]=non_perm_key_var[5]; new_key_var[14]=non_perm_key_var[11]; new_key_var[13]=non_perm_key_var[23]; new_key_var[12]=non_perm_key_var[8]; + new_key_var[11]=non_perm_key_var[12]; new_key_var[10]=non_perm_key_var[7]; new_key_var[9]=non_perm_key_var[17]; new_key_var[8]=non_perm_key_var[0]; + + new_key_var[7]=non_perm_key_var[22]; new_key_var[6]=non_perm_key_var[3]; new_key_var[5]=non_perm_key_var[10]; new_key_var[4]=non_perm_key_var[14]; + new_key_var[3]=non_perm_key_var[6]; new_key_var[2]=non_perm_key_var[20]; new_key_var[1]=non_perm_key_var[27]; new_key_var[0]=non_perm_key_var[24]; + + new_key = (new_key_var); + + +end + +endmodule Index: systemcdes/tags/V10/rtl/verilog/desround.v =================================================================== --- systemcdes/tags/V10/rtl/verilog/desround.v (nonexistent) +++ systemcdes/tags/V10/rtl/verilog/desround.v (revision 11) @@ -0,0 +1,220 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// DES Round //// +//// //// +//// This file is part of the SystemC DES //// +//// //// +//// Description: //// +//// Performs a round of DES algorithm //// +//// //// +//// Generated automatically using SystemC to Verilog translator //// +//// //// +//// To Do: //// +//// - done //// +//// //// +//// Author(s): //// +//// - Javier Castillo, jcastilo@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ + + +module desround(clk,reset,iteration_i,decrypt_i,R_i,L_i,Key_i,R_o,L_o,Key_o,s1_o,s2_o,s3_o,s4_o,s5_o,s6_o,s7_o,s8_o,s1_i,s2_i,s3_i,s4_i,s5_i,s6_i,s7_i,s8_i); + +input clk; +input reset; +input [3:0] iteration_i; +input decrypt_i; +input [31:0] R_i; +input [31:0] L_i; +input [55:0] Key_i; +output [31:0] R_o; +output [31:0] L_o; +output [55:0] Key_o; +output [5:0] s1_o; +output [5:0] s2_o; +output [5:0] s3_o; +output [5:0] s4_o; +output [5:0] s5_o; +output [5:0] s6_o; +output [5:0] s7_o; +output [5:0] s8_o; +input [3:0] s1_i; +input [3:0] s2_i; +input [3:0] s3_i; +input [3:0] s4_i; +input [3:0] s5_i; +input [3:0] s6_i; +input [3:0] s7_i; +input [3:0] s8_i; + +reg [31:0] R_o; +reg [31:0] L_o; +reg [55:0] Key_o; +reg [5:0] s1_o; +reg [5:0] s2_o; +reg [5:0] s3_o; +reg [5:0] s4_o; +reg [5:0] s5_o; +reg [5:0] s6_o; +reg [5:0] s7_o; +reg [5:0] s8_o; + + + +reg [55:0] previous_key; + +reg [3:0] iteration; + +reg decrypt; + + + +wire [55:0] non_perm_key; + + + +wire [47:0] new_key; + +reg [31:0] next_R; + +reg [31:0] expanRSig; + + reg[47:0] expandedR; + reg[47:0] round_key; + reg[47:0] KER; + reg[31:0] R_i_var; + + reg[31:0] Soutput; + reg[31:0] f; + + +key_gen kg1 (.previous_key(previous_key), .iteration(iteration), .decrypt(decrypt), .new_key(new_key), .non_perm_key(non_perm_key)); + +always @(posedge clk or negedge reset) + +begin + + + if(!reset) + begin + + L_o = (0); + R_o = (0); + Key_o = (0); + + end + else + begin + + L_o = (R_i); + R_o = (next_R); + Key_o = (non_perm_key); + + end + +end + +always @( R_i or L_i or Key_i or iteration_i or decrypt_i or new_key or s1_i or s2_i or s3_i or s4_i or s5_i or s6_i or s7_i or s8_i) + +begin + + R_i_var=R_i; + + + expandedR[47]=R_i_var[0]; expandedR[46]=R_i_var[31]; expandedR[45]=R_i_var[30]; expandedR[44]=R_i_var[29]; + expandedR[43]=R_i_var[28]; expandedR[42]=R_i_var[27]; expandedR[41]=R_i_var[28]; expandedR[40]=R_i_var[27]; + + expandedR[39]=R_i_var[26]; expandedR[38]=R_i_var[25]; expandedR[37]=R_i_var[24]; expandedR[36]=R_i_var[23]; + expandedR[35]=R_i_var[24]; expandedR[34]=R_i_var[23]; expandedR[33]=R_i_var[22]; expandedR[32]=R_i_var[21]; + + expandedR[31]=R_i_var[20]; expandedR[30]=R_i_var[19]; expandedR[29]=R_i_var[20]; expandedR[28]=R_i_var[19]; + expandedR[27]=R_i_var[18]; expandedR[26]=R_i_var[17]; expandedR[25]=R_i_var[16]; expandedR[24]=R_i_var[15]; + + expandedR[23]=R_i_var[16]; expandedR[22]=R_i_var[15]; expandedR[21]=R_i_var[14]; expandedR[20]=R_i_var[13]; + expandedR[19]=R_i_var[12]; expandedR[18]=R_i_var[11]; expandedR[17]=R_i_var[12]; expandedR[16]=R_i_var[11]; + + expandedR[15]=R_i_var[10]; expandedR[14]=R_i_var[9]; expandedR[13]=R_i_var[8]; expandedR[12]=R_i_var[7]; + expandedR[11]=R_i_var[8]; expandedR[10]=R_i_var[7]; expandedR[9]=R_i_var[6]; expandedR[8]=R_i_var[5]; + + expandedR[7]=R_i_var[4]; expandedR[6]=R_i_var[3]; expandedR[5]=R_i_var[4]; expandedR[4]=R_i_var[3]; + expandedR[3]=R_i_var[2]; expandedR[2]=R_i_var[1]; expandedR[1]=R_i_var[0]; expandedR[0]=R_i_var[31]; + + + previous_key = (Key_i); + iteration = (iteration_i); + decrypt = (decrypt_i); + + round_key=new_key; + + KER=expandedR^round_key; + + + s1_o = (KER[47:42]); + s2_o = (KER[41:36]); + s3_o = (KER[35:30]); + s4_o = (KER[29:24]); + s5_o = (KER[23:18]); + s6_o = (KER[17:12]); + s7_o = (KER[11:6]); + s8_o = (KER[5:0]); + + Soutput[31:28]=s1_i; + Soutput[27:24]=s2_i; + Soutput[23:20]=s3_i; + Soutput[19:16]=s4_i; + Soutput[15:12]=s5_i; + Soutput[11:8]=s6_i; + Soutput[7:4]=s7_i; + Soutput[3:0]=s8_i; + + + + f[31]=Soutput[16]; f[30]=Soutput[25]; f[29]=Soutput[12]; f[28]=Soutput[11]; + f[27]=Soutput[3]; f[26]=Soutput[20]; f[25]=Soutput[4]; f[24]=Soutput[15]; + + f[23]=Soutput[31]; f[22]=Soutput[17]; f[21]=Soutput[9]; f[20]=Soutput[6]; + f[19]=Soutput[27]; f[18]=Soutput[14]; f[17]=Soutput[1]; f[16]=Soutput[22]; + + f[15]=Soutput[30]; f[14]=Soutput[24]; f[13]=Soutput[8]; f[12]=Soutput[18]; + f[11]=Soutput[0]; f[10]=Soutput[5]; f[9]=Soutput[29]; f[8]=Soutput[23]; + + f[7]=Soutput[13]; f[6]=Soutput[19]; f[5]=Soutput[2]; f[4]=Soutput[26]; + f[3]=Soutput[10]; f[2]=Soutput[21]; f[1]=Soutput[28]; f[0]=Soutput[7]; + + next_R = (L_i^f); + + expanRSig = (L_i^f); + + +end + +endmodule Index: systemcdes/tags/V10/rtl/verilog/s1.v =================================================================== --- systemcdes/tags/V10/rtl/verilog/s1.v (nonexistent) +++ systemcdes/tags/V10/rtl/verilog/s1.v (revision 11) @@ -0,0 +1,134 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// SBOX 1 //// +//// //// +//// This file is part of the SystemC DES //// +//// //// +//// Description: //// +//// Sbox of DES algorithm //// +//// //// +//// Generated automatically using SystemC to Verilog translator //// +//// //// +//// To Do: //// +//// - done //// +//// //// +//// Author(s): //// +//// - Javier Castillo, jcastilo@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ + + +module s1(stage1_input,stage1_output); +input [5:0] stage1_input; +output [3:0] stage1_output; + +reg [3:0] stage1_output; + + + +always @( stage1_input) + +begin + + + case(stage1_input) + 0: stage1_output = (14); + 1: stage1_output = (0); + 2: stage1_output = (4); + 3: stage1_output = (15); + 4: stage1_output = (13); + 5: stage1_output = (7); + 6: stage1_output = (1); + 7: stage1_output = (4); + 8: stage1_output = (2); + 9: stage1_output = (14); + 10: stage1_output = (15); + 11: stage1_output = (2); + 12: stage1_output = (11); + 13: stage1_output = (13); + 14: stage1_output = (8); + 15: stage1_output = (1); + 16: stage1_output = (3); + 17: stage1_output = (10); + 18: stage1_output = (10); + 19: stage1_output = (6); + 20: stage1_output = (6); + 21: stage1_output = (12); + 22: stage1_output = (12); + 23: stage1_output = (11); + 24: stage1_output = (5); + 25: stage1_output = (9); + 26: stage1_output = (9); + 27: stage1_output = (5); + 28: stage1_output = (0); + 29: stage1_output = (3); + 30: stage1_output = (7); + 31: stage1_output = (8); + 32: stage1_output = (4); + 33: stage1_output = (15); + 34: stage1_output = (1); + 35: stage1_output = (12); + 36: stage1_output = (14); + 37: stage1_output = (8); + 38: stage1_output = (8); + 39: stage1_output = (2); + 40: stage1_output = (13); + 41: stage1_output = (4); + 42: stage1_output = (6); + 43: stage1_output = (9); + 44: stage1_output = (2); + 45: stage1_output = (1); + 46: stage1_output = (11); + 47: stage1_output = (7); + 48: stage1_output = (15); + 49: stage1_output = (5); + 50: stage1_output = (12); + 51: stage1_output = (11); + 52: stage1_output = (9); + 53: stage1_output = (3); + 54: stage1_output = (7); + 55: stage1_output = (14); + 56: stage1_output = (3); + 57: stage1_output = (10); + 58: stage1_output = (10); + 59: stage1_output = (0); + 60: stage1_output = (5); + 61: stage1_output = (6); + 62: stage1_output = (0); + 63: stage1_output = (13); + +endcase + + +end + +endmodule Index: systemcdes/tags/V10/rtl/verilog/s2.v =================================================================== --- systemcdes/tags/V10/rtl/verilog/s2.v (nonexistent) +++ systemcdes/tags/V10/rtl/verilog/s2.v (revision 11) @@ -0,0 +1,134 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// SBOX 2 //// +//// //// +//// This file is part of the SystemC DES //// +//// //// +//// Description: //// +//// Sbox of DES algorithm //// +//// //// +//// Generated automatically using SystemC to Verilog translator //// +//// //// +//// To Do: //// +//// - done //// +//// //// +//// Author(s): //// +//// - Javier Castillo, jcastilo@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ + + +module s2(stage1_input,stage1_output); +input [5:0] stage1_input; +output [3:0] stage1_output; + +reg [3:0] stage1_output; + + + +always @( stage1_input) + +begin + + + case(stage1_input) + 0: stage1_output = (15); + 1: stage1_output = (3); + 2: stage1_output = (1); + 3: stage1_output = (13); + 4: stage1_output = (8); + 5: stage1_output = (4); + 6: stage1_output = (14); + 7: stage1_output = (7); + 8: stage1_output = (6); + 9: stage1_output = (15); + 10: stage1_output = (11); + 11: stage1_output = (2); + 12: stage1_output = (3); + 13: stage1_output = (8); + 14: stage1_output = (4); + 15: stage1_output = (14); + 16: stage1_output = (9); + 17: stage1_output = (12); + 18: stage1_output = (7); + 19: stage1_output = (0); + 20: stage1_output = (2); + 21: stage1_output = (1); + 22: stage1_output = (13); + 23: stage1_output = (10); + 24: stage1_output = (12); + 25: stage1_output = (6); + 26: stage1_output = (0); + 27: stage1_output = (9); + 28: stage1_output = (5); + 29: stage1_output = (11); + 30: stage1_output = (10); + 31: stage1_output = (5); + 32: stage1_output = (0); + 33: stage1_output = (13); + 34: stage1_output = (14); + 35: stage1_output = (8); + 36: stage1_output = (7); + 37: stage1_output = (10); + 38: stage1_output = (11); + 39: stage1_output = (1); + 40: stage1_output = (10); + 41: stage1_output = (3); + 42: stage1_output = (4); + 43: stage1_output = (15); + 44: stage1_output = (13); + 45: stage1_output = (4); + 46: stage1_output = (1); + 47: stage1_output = (2); + 48: stage1_output = (5); + 49: stage1_output = (11); + 50: stage1_output = (8); + 51: stage1_output = (6); + 52: stage1_output = (12); + 53: stage1_output = (7); + 54: stage1_output = (6); + 55: stage1_output = (12); + 56: stage1_output = (9); + 57: stage1_output = (0); + 58: stage1_output = (3); + 59: stage1_output = (5); + 60: stage1_output = (2); + 61: stage1_output = (14); + 62: stage1_output = (15); + 63: stage1_output = (9); + +endcase + + +end + +endmodule Index: systemcdes/tags/V10/rtl/verilog/s3.v =================================================================== --- systemcdes/tags/V10/rtl/verilog/s3.v (nonexistent) +++ systemcdes/tags/V10/rtl/verilog/s3.v (revision 11) @@ -0,0 +1,135 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// SBOX 3 //// +//// //// +//// This file is part of the SystemC DES //// +//// //// +//// Description: //// +//// Sbox of DES algorithm //// +//// //// +//// Generated automatically using SystemC to Verilog translator //// +//// //// +//// To Do: //// +//// - done //// +//// //// +//// Author(s): //// +//// - Javier Castillo, jcastilo@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ + + +module s3(stage1_input,stage1_output); +input [5:0] stage1_input; +output [3:0] stage1_output; + +reg [3:0] stage1_output; + + + +always @( stage1_input) + +begin + + case(stage1_input) + + 0: stage1_output = (10); + 1: stage1_output = (13); + 2: stage1_output = (0); + 3: stage1_output = (7); + 4: stage1_output = (9); + 5: stage1_output = (0); + 6: stage1_output = (14); + 7: stage1_output = (9); + 8: stage1_output = (6); + 9: stage1_output = (3); + 10: stage1_output = (3); + 11: stage1_output = (4); + 12: stage1_output = (15); + 13: stage1_output = (6); + 14: stage1_output = (5); + 15: stage1_output = (10); + 16: stage1_output = (1); + 17: stage1_output = (2); + 18: stage1_output = (13); + 19: stage1_output = (8); + 20: stage1_output = (12); + 21: stage1_output = (5); + 22: stage1_output = (7); + 23: stage1_output = (14); + 24: stage1_output = (11); + 25: stage1_output = (12); + 26: stage1_output = (4); + 27: stage1_output = (11); + 28: stage1_output = (2); + 29: stage1_output = (15); + 30: stage1_output = (8); + 31: stage1_output = (1); + 32: stage1_output = (13); + 33: stage1_output = (1); + 34: stage1_output = (6); + 35: stage1_output = (10); + 36: stage1_output = (4); + 37: stage1_output = (13); + 38: stage1_output = (9); + 39: stage1_output = (0); + 40: stage1_output = (8); + 41: stage1_output = (6); + 42: stage1_output = (15); + 43: stage1_output = (9); + 44: stage1_output = (3); + 45: stage1_output = (8); + 46: stage1_output = (0); + 47: stage1_output = (7); + 48: stage1_output = (11); + 49: stage1_output = (4); + 50: stage1_output = (1); + 51: stage1_output = (15); + 52: stage1_output = (2); + 53: stage1_output = (14); + 54: stage1_output = (12); + 55: stage1_output = (3); + 56: stage1_output = (5); + 57: stage1_output = (11); + 58: stage1_output = (10); + 59: stage1_output = (5); + 60: stage1_output = (14); + 61: stage1_output = (2); + 62: stage1_output = (7); + 63: stage1_output = (12); + +endcase + + + +end + +endmodule Index: systemcdes/tags/V10/rtl/verilog/s4.v =================================================================== --- systemcdes/tags/V10/rtl/verilog/s4.v (nonexistent) +++ systemcdes/tags/V10/rtl/verilog/s4.v (revision 11) @@ -0,0 +1,135 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// SBOX 4 //// +//// //// +//// This file is part of the SystemC DES //// +//// //// +//// Description: //// +//// Sbox of DES algorithm //// +//// //// +//// Generated automatically using SystemC to Verilog translator //// +//// //// +//// To Do: //// +//// - done //// +//// //// +//// Author(s): //// +//// - Javier Castillo, jcastilo@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ + + +module s4(stage1_input,stage1_output); +input [5:0] stage1_input; +output [3:0] stage1_output; + +reg [3:0] stage1_output; + + + +always @( stage1_input) + +begin + + case(stage1_input) + + 0: stage1_output = (7); + 1: stage1_output = (13); + 2: stage1_output = (13); + 3: stage1_output = (8); + 4: stage1_output = (14); + 5: stage1_output = (11); + 6: stage1_output = (3); + 7: stage1_output = (5); + 8: stage1_output = (0); + 9: stage1_output = (6); + 10: stage1_output = (6); + 11: stage1_output = (15); + 12: stage1_output = (9); + 13: stage1_output = (0); + 14: stage1_output = (10); + 15: stage1_output = (3); + 16: stage1_output = (1); + 17: stage1_output = (4); + 18: stage1_output = (2); + 19: stage1_output = (7); + 20: stage1_output = (8); + 21: stage1_output = (2); + 22: stage1_output = (5); + 23: stage1_output = (12); + 24: stage1_output = (11); + 25: stage1_output = (1); + 26: stage1_output = (12); + 27: stage1_output = (10); + 28: stage1_output = (4); + 29: stage1_output = (14); + 30: stage1_output = (15); + 31: stage1_output = (9); + 32: stage1_output = (10); + 33: stage1_output = (3); + 34: stage1_output = (6); + 35: stage1_output = (15); + 36: stage1_output = (9); + 37: stage1_output = (0); + 38: stage1_output = (0); + 39: stage1_output = (6); + 40: stage1_output = (12); + 41: stage1_output = (10); + 42: stage1_output = (11); + 43: stage1_output = (1); + 44: stage1_output = (7); + 45: stage1_output = (13); + 46: stage1_output = (13); + 47: stage1_output = (8); + 48: stage1_output = (15); + 49: stage1_output = (9); + 50: stage1_output = (1); + 51: stage1_output = (4); + 52: stage1_output = (3); + 53: stage1_output = (5); + 54: stage1_output = (14); + 55: stage1_output = (11); + 56: stage1_output = (5); + 57: stage1_output = (12); + 58: stage1_output = (2); + 59: stage1_output = (7); + 60: stage1_output = (8); + 61: stage1_output = (2); + 62: stage1_output = (4); + 63: stage1_output = (14); + +endcase + + + +end + +endmodule Index: systemcdes/tags/V10/rtl/verilog/s5.v =================================================================== --- systemcdes/tags/V10/rtl/verilog/s5.v (nonexistent) +++ systemcdes/tags/V10/rtl/verilog/s5.v (revision 11) @@ -0,0 +1,136 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// SBOX 5 //// +//// //// +//// This file is part of the SystemC DES //// +//// //// +//// Description: //// +//// Sbox of DES algorithm //// +//// //// +//// Generated automatically using SystemC to Verilog translator //// +//// //// +//// To Do: //// +//// - done //// +//// //// +//// Author(s): //// +//// - Javier Castillo, jcastilo@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ + + +module s5(stage1_input,stage1_output); +input [5:0] stage1_input; +output [3:0] stage1_output; + +reg [3:0] stage1_output; + + + +always @( stage1_input) + +begin + + case(stage1_input) + + 0: stage1_output = (2); + 1: stage1_output = (14); + 2: stage1_output = (12); + 3: stage1_output = (11); + 4: stage1_output = (4); + 5: stage1_output = (2); + 6: stage1_output = (1); + 7: stage1_output = (12); + 8: stage1_output = (7); + 9: stage1_output = (4); + 10: stage1_output = (10); + 11: stage1_output = (7); + 12: stage1_output = (11); + 13: stage1_output = (13); + 14: stage1_output = (6); + 15: stage1_output = (1); + 16: stage1_output = (8); + 17: stage1_output = (5); + 18: stage1_output = (5); + 19: stage1_output = (0); + 20: stage1_output = (3); + 21: stage1_output = (15); + 22: stage1_output = (15); + 23: stage1_output = (10); + 24: stage1_output = (13); + 25: stage1_output = (3); + 26: stage1_output = (0); + 27: stage1_output = (9); + 28: stage1_output = (14); + 29: stage1_output = (8); + 30: stage1_output = (9); + 31: stage1_output = (6); + 32: stage1_output = (4); + 33: stage1_output = (11); + 34: stage1_output = (2); + 35: stage1_output = (8); + 36: stage1_output = (1); + 37: stage1_output = (12); + 38: stage1_output = (11); + 39: stage1_output = (7); + 40: stage1_output = (10); + 41: stage1_output = (1); + 42: stage1_output = (13); + 43: stage1_output = (14); + 44: stage1_output = (7); + 45: stage1_output = (2); + 46: stage1_output = (8); + 47: stage1_output = (13); + 48: stage1_output = (15); + 49: stage1_output = (6); + 50: stage1_output = (9); + 51: stage1_output = (15); + 52: stage1_output = (12); + 53: stage1_output = (0); + 54: stage1_output = (5); + 55: stage1_output = (9); + 56: stage1_output = (6); + 57: stage1_output = (10); + 58: stage1_output = (3); + 59: stage1_output = (4); + 60: stage1_output = (0); + 61: stage1_output = (5); + 62: stage1_output = (14); + 63: stage1_output = (3); + +endcase + + + + +end + +endmodule Index: systemcdes/tags/V10/rtl/verilog/s6.v =================================================================== --- systemcdes/tags/V10/rtl/verilog/s6.v (nonexistent) +++ systemcdes/tags/V10/rtl/verilog/s6.v (revision 11) @@ -0,0 +1,136 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// SBOX 6 //// +//// //// +//// This file is part of the SystemC DES //// +//// //// +//// Description: //// +//// Sbox of DES algorithm //// +//// //// +//// Generated automatically using SystemC to Verilog translator //// +//// //// +//// To Do: //// +//// - done //// +//// //// +//// Author(s): //// +//// - Javier Castillo, jcastilo@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ + + +module s6(stage1_input,stage1_output); +input [5:0] stage1_input; +output [3:0] stage1_output; + +reg [3:0] stage1_output; + + + +always @( stage1_input) + +begin + + case(stage1_input) + + 0: stage1_output = (12); + 1: stage1_output = (10); + 2: stage1_output = (1); + 3: stage1_output = (15); + 4: stage1_output = (10); + 5: stage1_output = (4); + 6: stage1_output = (15); + 7: stage1_output = (2); + 8: stage1_output = (9); + 9: stage1_output = (7); + 10: stage1_output = (2); + 11: stage1_output = (12); + 12: stage1_output = (6); + 13: stage1_output = (9); + 14: stage1_output = (8); + 15: stage1_output = (5); + 16: stage1_output = (0); + 17: stage1_output = (6); + 18: stage1_output = (13); + 19: stage1_output = (1); + 20: stage1_output = (3); + 21: stage1_output = (13); + 22: stage1_output = (4); + 23: stage1_output = (14); + 24: stage1_output = (14); + 25: stage1_output = (0); + 26: stage1_output = (7); + 27: stage1_output = (11); + 28: stage1_output = (5); + 29: stage1_output = (3); + 30: stage1_output = (11); + 31: stage1_output = (8); + 32: stage1_output = (9); + 33: stage1_output = (4); + 34: stage1_output = (14); + 35: stage1_output = (3); + 36: stage1_output = (15); + 37: stage1_output = (2); + 38: stage1_output = (5); + 39: stage1_output = (12); + 40: stage1_output = (2); + 41: stage1_output = (9); + 42: stage1_output = (8); + 43: stage1_output = (5); + 44: stage1_output = (12); + 45: stage1_output = (15); + 46: stage1_output = (3); + 47: stage1_output = (10); + 48: stage1_output = (7); + 49: stage1_output = (11); + 50: stage1_output = (0); + 51: stage1_output = (14); + 52: stage1_output = (4); + 53: stage1_output = (1); + 54: stage1_output = (10); + 55: stage1_output = (7); + 56: stage1_output = (1); + 57: stage1_output = (6); + 58: stage1_output = (13); + 59: stage1_output = (0); + 60: stage1_output = (11); + 61: stage1_output = (8); + 62: stage1_output = (6); + 63: stage1_output = (13); + +endcase + + + + +end + +endmodule Index: systemcdes/tags/V10/rtl/verilog/s7.v =================================================================== --- systemcdes/tags/V10/rtl/verilog/s7.v (nonexistent) +++ systemcdes/tags/V10/rtl/verilog/s7.v (revision 11) @@ -0,0 +1,135 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// SBOX 7 //// +//// //// +//// This file is part of the SystemC DES //// +//// //// +//// Description: //// +//// Sbox of DES algorithm //// +//// //// +//// Generated automatically using SystemC to Verilog translator //// +//// //// +//// To Do: //// +//// - done //// +//// //// +//// Author(s): //// +//// - Javier Castillo, jcastilo@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ + +module s7(stage1_input,stage1_output); +input [5:0] stage1_input; +output [3:0] stage1_output; + +reg [3:0] stage1_output; + + + +always @( stage1_input) + +begin + + case(stage1_input) + + 0: stage1_output = (4); + 1: stage1_output = (13); + 2: stage1_output = (11); + 3: stage1_output = (0); + 4: stage1_output = (2); + 5: stage1_output = (11); + 6: stage1_output = (14); + 7: stage1_output = (7); + 8: stage1_output = (15); + 9: stage1_output = (4); + 10: stage1_output = (0); + 11: stage1_output = (9); + 12: stage1_output = (8); + 13: stage1_output = (1); + 14: stage1_output = (13); + 15: stage1_output = (10); + 16: stage1_output = (3); + 17: stage1_output = (14); + 18: stage1_output = (12); + 19: stage1_output = (3); + 20: stage1_output = (9); + 21: stage1_output = (5); + 22: stage1_output = (7); + 23: stage1_output = (12); + 24: stage1_output = (5); + 25: stage1_output = (2); + 26: stage1_output = (10); + 27: stage1_output = (15); + 28: stage1_output = (6); + 29: stage1_output = (8); + 30: stage1_output = (1); + 31: stage1_output = (6); + 32: stage1_output = (1); + 33: stage1_output = (6); + 34: stage1_output = (4); + 35: stage1_output = (11); + 36: stage1_output = (11); + 37: stage1_output = (13); + 38: stage1_output = (13); + 39: stage1_output = (8); + 40: stage1_output = (12); + 41: stage1_output = (1); + 42: stage1_output = (3); + 43: stage1_output = (4); + 44: stage1_output = (7); + 45: stage1_output = (10); + 46: stage1_output = (14); + 47: stage1_output = (7); + 48: stage1_output = (10); + 49: stage1_output = (9); + 50: stage1_output = (15); + 51: stage1_output = (5); + 52: stage1_output = (6); + 53: stage1_output = (0); + 54: stage1_output = (8); + 55: stage1_output = (15); + 56: stage1_output = (0); + 57: stage1_output = (14); + 58: stage1_output = (5); + 59: stage1_output = (2); + 60: stage1_output = (9); + 61: stage1_output = (3); + 62: stage1_output = (2); + 63: stage1_output = (12); + +endcase + + + + +end + +endmodule Index: systemcdes/tags/V10/rtl/verilog/s8.v =================================================================== --- systemcdes/tags/V10/rtl/verilog/s8.v (nonexistent) +++ systemcdes/tags/V10/rtl/verilog/s8.v (revision 11) @@ -0,0 +1,134 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// SBOX 8 //// +//// //// +//// This file is part of the SystemC DES //// +//// //// +//// Description: //// +//// Sbox of DES algorithm //// +//// //// +//// Generated automatically using SystemC to Verilog translator //// +//// //// +//// To Do: //// +//// - done //// +//// //// +//// Author(s): //// +//// - Javier Castillo, jcastilo@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ + +module s8(stage1_input,stage1_output); +input [5:0] stage1_input; +output [3:0] stage1_output; + +reg [3:0] stage1_output; + + + +always @(stage1_input) + +begin + + case(stage1_input) + + 0: stage1_output = (13); + 1: stage1_output = (1); + 2: stage1_output = (2); + 3: stage1_output = (15); + 4: stage1_output = (8); + 5: stage1_output = (13); + 6: stage1_output = (4); + 7: stage1_output = (8); + 8: stage1_output = (6); + 9: stage1_output = (10); + 10: stage1_output = (15); + 11: stage1_output = (3); + 12: stage1_output = (11); + 13: stage1_output = (7); + 14: stage1_output = (1); + 15: stage1_output = (4); + 16: stage1_output = (10); + 17: stage1_output = (12); + 18: stage1_output = (9); + 19: stage1_output = (5); + 20: stage1_output = (3); + 21: stage1_output = (6); + 22: stage1_output = (14); + 23: stage1_output = (11); + 24: stage1_output = (5); + 25: stage1_output = (0); + 26: stage1_output = (0); + 27: stage1_output = (14); + 28: stage1_output = (12); + 29: stage1_output = (9); + 30: stage1_output = (7); + 31: stage1_output = (2); + 32: stage1_output = (7); + 33: stage1_output = (2); + 34: stage1_output = (11); + 35: stage1_output = (1); + 36: stage1_output = (4); + 37: stage1_output = (14); + 38: stage1_output = (1); + 39: stage1_output = (7); + 40: stage1_output = (9); + 41: stage1_output = (4); + 42: stage1_output = (12); + 43: stage1_output = (10); + 44: stage1_output = (14); + 45: stage1_output = (8); + 46: stage1_output = (2); + 47: stage1_output = (13); + 48: stage1_output = (0); + 49: stage1_output = (15); + 50: stage1_output = (6); + 51: stage1_output = (12); + 52: stage1_output = (10); + 53: stage1_output = (9); + 54: stage1_output = (13); + 55: stage1_output = (0); + 56: stage1_output = (15); + 57: stage1_output = (3); + 58: stage1_output = (3); + 59: stage1_output = (5); + 60: stage1_output = (5); + 61: stage1_output = (6); + 62: stage1_output = (8); + 63: stage1_output = (11); + +endcase + + + +end + +endmodule Index: systemcdes/tags =================================================================== --- systemcdes/tags (nonexistent) +++ systemcdes/tags (revision 11)
systemcdes/tags Property changes : Added: svn:mergeinfo ## -0,0 +0,0 ##

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.