URL
https://opencores.org/ocsvn/uart16750/uart16750/trunk
Subversion Repositories uart16750
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 10 to Rev 11
- ↔ Reverse comparison
Rev 10 → Rev 11
/trunk/rtl/vhdl/uart_receiver.vhd
23,7 → 23,6
|
LIBRARY IEEE; |
USE IEEE.std_logic_1164.all; |
USE IEEE.std_logic_unsigned.all; |
USE IEEE.numeric_std.all; |
|
-- Serial UART receiver |
/trunk/rtl/vhdl/uart_baudgen.vhd
3,7 → 3,7
-- |
-- Author: Sebastian Witt |
-- Date: 27.01.2008 |
-- Version: 1.0 |
-- Version: 1.1 |
-- |
-- This code is free software; you can redistribute it and/or |
-- modify it under the terms of the GNU Lesser General Public |
23,7 → 23,6
|
LIBRARY IEEE; |
USE IEEE.std_logic_1164.all; |
USE IEEE.std_logic_unsigned.all; |
USE IEEE.numeric_std.all; |
|
-- Serial UART baudrate generator |
40,7 → 39,7
|
architecture rtl of uart_baudgen is |
-- Signals |
signal iCounter : std_logic_vector(15 downto 0); |
signal iCounter : unsigned(15 downto 0); |
begin |
-- Baudrate counter |
BG_COUNT: process (CLK, RST) |
52,11 → 51,11
if (CLEAR = '1') then |
iCounter <= (others => '0'); |
elsif (CE = '1') then |
iCounter <= iCounter + '1'; |
iCounter <= iCounter + 1; |
end if; |
|
BAUDTICK <= '0'; |
if (iCounter = DIVIDER) then |
if (iCounter = unsigned(DIVIDER)) then |
iCounter <= (others => '0'); |
BAUDTICK <= '1'; |
end if; |
/trunk/rtl/vhdl/uart_transmitter.vhd
23,7 → 23,6
|
LIBRARY IEEE; |
USE IEEE.std_logic_1164.all; |
USE IEEE.std_logic_unsigned.all; |
USE IEEE.numeric_std.all; |
|
-- Serial UART transmitter |