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URL https://opencores.org/ocsvn/usb_phy/usb_phy/trunk

Subversion Repositories usb_phy

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Rev 10 → Rev 11

/trunk/rtl/verilog/usb_rx_phy.v
39,10 → 39,10
 
// CVS Log
//
// $Id: usb_rx_phy.v,v 1.4 2003-12-02 04:56:00 rudi Exp $
// $Id: usb_rx_phy.v,v 1.5 2004-10-19 09:29:07 rudi Exp $
//
// $Date: 2003-12-02 04:56:00 $
// $Revision: 1.4 $
// $Date: 2004-10-19 09:29:07 $
// $Revision: 1.5 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
49,6 → 49,9
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.4 2003/12/02 04:56:00 rudi
// Fixed a bug reported by Karl C. Posch from Graz University of Technology. Thanks Karl !
//
// Revision 1.3 2003/10/19 18:07:45 rudi
// - Fixed Sync Error to be only checked/generated during the sync phase
//
122,6 → 125,7
reg sync_err_d, sync_err;
reg bit_stuff_err;
reg se0_r, byte_err;
reg se0_s;
 
///////////////////////////////////////////////////////////////////
//
132,7 → 136,7
assign RxValid_o = rx_valid;
assign RxError_o = sync_err | bit_stuff_err | byte_err;
assign DataIn_o = hold_reg;
assign LineState = {rxdp_s1, rxdn_s1};
assign LineState = {rxdn_s1, rxdp_s1};
 
always @(posedge clk) rx_en <= RxEn_i;
always @(posedge clk) sync_err <= !rx_active & sync_err_d;
168,6 → 172,8
assign j = rxdp_s & !rxdn_s;
assign se0 = !rxdp_s & !rxdn_s;
 
always @(posedge clk) if(fs_ce) se0_s <= se0;
 
///////////////////////////////////////////////////////////////////
//
// DPLL
251,12 → 257,12
if(!rst) fs_state <= FS_IDLE;
else fs_state <= fs_next_state;
 
always @(fs_state or fs_ce or k or j or rx_en)
always @(fs_state or fs_ce or k or j or rx_en or rx_active or se0 or se0_s)
begin
synced_d = 1'b0;
sync_err_d = 1'b0;
fs_next_state = fs_state;
if(fs_ce)
if(fs_ce && !rx_active && !se0 && !se0_s)
case(fs_state) // synopsys full_case parallel_case
FS_IDLE:
begin
302,7 → 308,11
begin
if(j && rx_en) fs_next_state = J3;
else
if(k && rx_en) fs_next_state = K4; // Allow missing one J
if(k && rx_en)
begin
fs_next_state = FS_IDLE; // Allow missing first K-J
synced_d = 1'b1;
end
else
begin
sync_err_d = 1'b1;
388,8 → 398,7
 
assign drop_bit = (one_cnt==3'h6);
 
always @(posedge clk) // Bit Stuff Error
bit_stuff_err <= drop_bit & sd_nrzi & fs_ce & !se0 & rx_active;
always @(posedge clk) bit_stuff_err <= drop_bit & sd_nrzi & fs_ce & !se0 & rx_active; // Bit Stuff Error
 
///////////////////////////////////////////////////////////////////
//
430,12 → 439,11
else
if(rx_valid1 && fs_ce && !drop_bit) rx_valid1 <= 1'b0;
 
always @(posedge clk)
rx_valid <= !drop_bit & rx_valid1 & fs_ce;
always @(posedge clk) rx_valid <= !drop_bit & rx_valid1 & fs_ce;
 
always @(posedge clk) se0_r <= se0;
 
always @(posedge clk) byte_err <= se0 & !se0_r & (|bit_cnt);
always @(posedge clk) byte_err <= se0 & !se0_r & (|bit_cnt[2:1]) & rx_active;
 
endmodule
 
/trunk/rtl/verilog/usb_tx_phy.v
39,10 → 39,10
 
// CVS Log
//
// $Id: usb_tx_phy.v,v 1.3 2003-10-21 05:58:41 rudi Exp $
// $Id: usb_tx_phy.v,v 1.4 2004-10-19 09:29:07 rudi Exp $
//
// $Date: 2003-10-21 05:58:41 $
// $Revision: 1.3 $
// $Date: 2004-10-19 09:29:07 $
// $Revision: 1.4 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
49,6 → 49,11
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.3 2003/10/21 05:58:41 rudi
// usb_rst is no longer or'ed with the incomming reset internally.
// Now usb_rst is simply an output, the application can decide how
// to utilize it.
//
// Revision 1.2 2003/10/19 17:40:13 rudi
// - Made core more robust against line noise
// - Added Error Checking and Reporting
107,6 → 112,8
reg tx_ip_sync;
reg [2:0] bit_cnt;
reg [7:0] hold_reg;
reg [7:0] hold_reg_d;
 
reg sd_raw_o;
wire hold;
reg data_done;
123,6 → 130,7
reg append_eop_sync1;
reg append_eop_sync2;
reg append_eop_sync3;
reg append_eop_sync4;
reg txdp, txdn;
reg txoe_r1, txoe_r2;
reg txoe;
140,8 → 148,7
if(!rst) TxReady_o <= 1'b0;
else TxReady_o <= tx_ready_d & TxValid_i;
 
always @(posedge clk)
ld_data <= ld_data_d;
always @(posedge clk) ld_data <= ld_data_d;
 
///////////////////////////////////////////////////////////////////
//
177,11 → 184,11
`else
always @(posedge clk)
`endif
if(!rst) data_done <= 1'b0;
if(!rst) data_done <= 1'b0;
else
if(TxValid_i && ! tx_ip) data_done <= 1'b1;
else
if(!TxValid_i) data_done <= 1'b0;
if(!TxValid_i) data_done <= 1'b0;
 
///////////////////////////////////////////////////////////////////
//
205,14 → 212,14
if(!tx_ip_sync) sd_raw_o <= 1'b0;
else
case(bit_cnt) // synopsys full_case parallel_case
3'h0: sd_raw_o <= hold_reg[0];
3'h1: sd_raw_o <= hold_reg[1];
3'h2: sd_raw_o <= hold_reg[2];
3'h3: sd_raw_o <= hold_reg[3];
3'h4: sd_raw_o <= hold_reg[4];
3'h5: sd_raw_o <= hold_reg[5];
3'h6: sd_raw_o <= hold_reg[6];
3'h7: sd_raw_o <= hold_reg[7];
3'h0: sd_raw_o <= hold_reg_d[0];
3'h1: sd_raw_o <= hold_reg_d[1];
3'h2: sd_raw_o <= hold_reg_d[2];
3'h3: sd_raw_o <= hold_reg_d[3];
3'h4: sd_raw_o <= hold_reg_d[4];
3'h5: sd_raw_o <= hold_reg_d[5];
3'h6: sd_raw_o <= hold_reg_d[6];
3'h7: sd_raw_o <= hold_reg_d[7];
endcase
 
always @(posedge clk)
229,6 → 236,8
else
if(ld_data) hold_reg <= DataOut_i;
 
always @(posedge clk) hold_reg_d <= hold_reg;
 
///////////////////////////////////////////////////////////////////
//
// Bit Stuffer
317,8 → 326,18
`endif
if(!rst) append_eop_sync3 <= 1'b0;
else
if(fs_ce) append_eop_sync3 <= append_eop_sync2;
if(fs_ce) append_eop_sync3 <= append_eop_sync2 |
(append_eop_sync3 & !append_eop_sync4); // Make sure always 2 bit wide
 
`ifdef USB_ASYNC_REST
always @(posedge clk or negedge rst)
`else
always @(posedge clk)
`endif
if(!rst) append_eop_sync4 <= 1'b0;
else
if(fs_ce) append_eop_sync4 <= append_eop_sync3;
 
assign eop_done = append_eop_sync3;
 
///////////////////////////////////////////////////////////////////

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