URL
https://opencores.org/ocsvn/simple_spi/simple_spi/trunk
Subversion Repositories simple_spi
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 10 to Rev 9
- ↔ Reverse comparison
Rev 10 → Rev 9
/simple_spi/tags/initial/rtl/verilog/fifo4.v
File deleted
simple_spi/tags
Property changes :
Deleted: svn:mergeinfo
## -0,0 +0,0 ##
Index: simple_spi/trunk/bench/verilog/tst_bench_top.v
===================================================================
--- simple_spi/trunk/bench/verilog/tst_bench_top.v (revision 10)
+++ simple_spi/trunk/bench/verilog/tst_bench_top.v (nonexistent)
@@ -1,218 +0,0 @@
-/////////////////////////////////////////////////////////////////////
-//// ////
-//// simple_spi ('HC11 compatible) testbench ////
-//// ////
-//// Author: Richard Herveille ////
-//// richard@asics.ws ////
-//// www.asics.ws ////
-//// ////
-////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2004 Richard Herveille ////
-//// richard@asics.ws ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer.////
-//// ////
-//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
-//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
-//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
-//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
-//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
-//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
-//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
-//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
-//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
-//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
-//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
-//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
-//// POSSIBILITY OF SUCH DAMAGE. ////
-//// ////
-/////////////////////////////////////////////////////////////////////
-
-// CVS Log
-//
-// $Id: tst_bench_top.v,v 1.1 2004-02-28 16:01:47 rherveille Exp $
-//
-// $Date: 2004-02-28 16:01:47 $
-// $Revision: 1.1 $
-// $Author: rherveille $
-// $Locker: $
-// $State: Exp $
-//
-// Change History:
-// $Log: not supported by cvs2svn $
-//
-//
-
-`include "timescale.v"
-
-module tst_bench_top();
-
- //
- // wires && regs
- //
- reg clk;
- reg rstn;
-
- wire [31:0] adr;
- wire [ 7:0] dat_i, dat_o;
- wire we;
- wire stb;
- wire cyc;
- wire ack;
- wire inta;
-
- reg [1:0] cpol, cpha;
- reg [2:0] e;
-
- wire sck, mosi, miso;
- reg [7:0] q;
-
- parameter SPCR = 2'b00;
- parameter SPSR = 2'b01;
- parameter SPDR = 2'b10;
- parameter SPER = 2'b11;
-
- //
- // Module body
- //
- integer n;
-
- // generate clock
- always #5 clk = ~clk;
-
- // hookup wishbone master model
- wb_master_model #(8, 32) u0 (
- .clk (clk),
- .rst (rstn),
- .adr (adr),
- .din (dat_i),
- .dout(dat_o),
- .cyc (cyc),
- .stb (stb),
- .we (we),
- .sel (),
- .ack (ack),
- .err (1'b0),
- .rty (1'b0)
- );
-
- // hookup spi core
- simple_spi_top spi_top (
- // wishbone interface
- .clk_i (clk),
- .rst_i (rstn),
- .cyc_i (cyc),
- .stb_i (stb),
- .adr_i (adr[1:0]),
- .we_i (we),
- .dat_i (dat_o),
- .dat_o (dat_i),
- .ack_o (ack),
- .inta_o(inta),
-
- .sck_o (sck),
- .mosi_o(mosi),
- .miso_i(miso)
- );
-
- // hookup spi slave model
- spi_slave_model spi_slave (
- .csn(1'b0),
- .sck(sck),
- .di(mosi),
- .do(miso)
- );
-
- initial
- begin
- `ifdef WAVES
- $shm_open("waves");
- $shm_probe("AS",tst_bench_top,"AS");
- $display("INFO: Signal dump enabled ...\n\n");
- `endif
-
-// force spi_slave.debug = 1'b1; // enable spi_slave debug information
- force spi_slave.debug = 1'b0; // disable spi_slave debug information
-
- $display("\nstatus: %t Testbench started\n\n", $time);
-
-
- // initially values
- clk = 0;
-
- // reset system
- rstn = 1'b1; // negate reset
- #2;
- rstn = 1'b0; // assert reset
- repeat(1) @(posedge clk);
- rstn = 1'b1; // negate reset
-
- $display("status: %t done reset", $time);
-
- @(posedge clk);
-
- //
- // program core
- //
- for (cpol=0; cpol<=1; cpol=cpol+1)
- for (cpha=0; cpha<=1; cpha=cpha+1)
- for (e=0; e<=3; e=e+1)
- begin
- //set cpol/cpha in spi slave model
- force spi_slave.cpol=cpol[0];
- force spi_slave.cpha=cpha[0];
- $display("cpol:%b, cpha:%b, e:%b", cpol[0],cpha[0],e[1:0]);
-
- // program internal registers
-
- // load control register
- u0.wb_write(1, SPCR, {4'b0101,cpol[0],cpha[0],e[1:0]} );
- //verify control register
- u0.wb_cmp (0, SPCR, {4'b0101,cpol[0],cpha[0],e[1:0]} );
-
-
- // load extended control register
- u0.wb_write(1,SPER,8'h0);
- //verify extended control register
- u0.wb_cmp (0,SPER,8'h0);
-
- //fill memory
- for(n=0;n<8;n=n+1) begin
- u0.wb_write(1,SPDR,{cpol[0],cpha[0],e[1:0],n[3:0]});
- //wait for transfer to finish
- u0.wb_read(1,SPSR,q);
- while(~q[7]) u0.wb_read(1,SPSR,q);
- //clear 'spif' bit
- u0.wb_write(1,SPSR,8'h80);
- end
-
- //verify memory
- for(n=0;n<8;n=n+1) begin
- u0.wb_write(1,SPDR,~n);
- //wait for transfer to finish
- u0.wb_read(1,SPSR,q);
- while(~q[7]) u0.wb_read(1,SPSR,q);
- //clear 'spif' bit
- u0.wb_write(1,SPSR,8'h80);
- //verify memory content
- u0.wb_cmp(0,SPDR,{cpol[0],cpha[0],e[1:0],n[3:0]});
- end
- end
-
- // check tip bit
-// u0.wb_read(1, SR, q);
-// while(q[1])
-// u0.wb_read(1, SR, q); // poll it until it is zero
-// $display("status: %t tip==0", $time);
-
- #250000; // wait 250us
- $display("\n\nstatus: %t Testbench done", $time);
- $finish;
- end
-
-endmodule
-
Index: simple_spi/trunk/bench/verilog/wb_master_model.v
===================================================================
--- simple_spi/trunk/bench/verilog/wb_master_model.v (revision 10)
+++ simple_spi/trunk/bench/verilog/wb_master_model.v (nonexistent)
@@ -1,205 +0,0 @@
-///////////////////////////////////////////////////////////////////////
-//// ////
-//// WISHBONE rev.B2 Wishbone Master model ////
-//// ////
-//// ////
-//// Author: Richard Herveille ////
-//// richard@asics.ws ////
-//// www.asics.ws ////
-//// ////
-//// Downloaded from: http://www.opencores.org/projects/mem_ctrl ////
-//// ////
-///////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2001 Richard Herveille ////
-//// richard@asics.ws ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
-//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
-//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
-//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
-//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
-//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
-//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
-//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
-//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
-//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
-//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
-//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
-//// POSSIBILITY OF SUCH DAMAGE. ////
-//// ////
-///////////////////////////////////////////////////////////////////////
-
-// CVS Log
-//
-// $Id: wb_master_model.v,v 1.1 2004-02-28 16:01:47 rherveille Exp $
-//
-// $Date: 2004-02-28 16:01:47 $
-// $Revision: 1.1 $
-// $Author: rherveille $
-// $Locker: $
-// $State: Exp $
-//
-// Change History:
-//
-`include "timescale.v"
-
-module wb_master_model(clk, rst, adr, din, dout, cyc, stb, we, sel, ack, err, rty);
-
-parameter dwidth = 32;
-parameter awidth = 32;
-
-input clk, rst;
-output [awidth:1] adr;
-input [dwidth:1] din;
-output [dwidth:1] dout;
-output cyc, stb;
-output we;
-output [dwidth/8:1] sel;
-input ack, err, rty;
-
-////////////////////////////////////////////////////////////////////
-//
-// Local Wires
-//
-
-reg [awidth:1] adr;
-reg [dwidth:1] dout;
-reg cyc, stb;
-reg we;
-reg [dwidth/8:1] sel;
-
-reg [dwidth:1] q;
-
-////////////////////////////////////////////////////////////////////
-//
-// Memory Logic
-//
-
-initial
- begin
- //adr = 32'hxxxx_xxxx;
- //adr = 0;
- adr = {awidth{1'bx}};
- dout = {dwidth{1'bx}};
- cyc = 1'b0;
- stb = 1'bx;
- we = 1'hx;
- sel = {dwidth/8{1'bx}};
- #1;
- $display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)\n");
- end
-
-////////////////////////////////////////////////////////////////////
-//
-// Wishbone write cycle
-//
-
-task wb_write;
- input delay;
- integer delay;
-
- input [awidth:1] a;
- input [dwidth:1] d;
-
- begin
-
- // wait initial delay
- repeat(delay) @(posedge clk);
-
- // assert wishbone signal
- #1;
- adr = a;
- dout = d;
- cyc = 1'b1;
- stb = 1'b1;
- we = 1'b1;
- sel = {dwidth/8{1'b1}};
- @(posedge clk);
-
- // wait for acknowledge from slave
- while(~ack) @(posedge clk);
-
- // negate wishbone signals
- #1;
- cyc = 1'b0;
- stb = 1'bx;
- adr = {awidth{1'bx}};
- dout = {dwidth{1'bx}};
- we = 1'hx;
- sel = {dwidth/8{1'bx}};
-
- end
-endtask
-
-////////////////////////////////////////////////////////////////////
-//
-// Wishbone read cycle
-//
-
-task wb_read;
- input delay;
- integer delay;
-
- input [awidth:1] a;
- output [dwidth:1] d;
-
- begin
-
- // wait initial delay
- repeat(delay) @(posedge clk);
-
- // assert wishbone signals
- #1;
- adr = a;
- dout = {dwidth{1'bx}};
- cyc = 1'b1;
- stb = 1'b1;
- we = 1'b0;
- sel = {dwidth/8{1'b1}};
- @(posedge clk);
-
- // wait for acknowledge from slave
- while(~ack) @(posedge clk);
-
- // negate wishbone signals
- #1;
- cyc = 1'b0;
- stb = 1'bx;
- adr = {awidth{1'bx}};
- dout = {dwidth{1'bx}};
- we = 1'hx;
- sel = {dwidth/8{1'bx}};
- d = din;
-
- end
-endtask
-
-////////////////////////////////////////////////////////////////////
-//
-// Wishbone compare cycle (read data from location and compare with expected data)
-//
-
-task wb_cmp;
- input delay;
- integer delay;
-
- input [awidth:1] a;
- input [dwidth:1] d_exp;
-
- begin
- wb_read (delay, a, q);
-
- if (d_exp !== q)
- $display("Data compare error. Received %h, expected %h at time %t", q, d_exp, $time);
- end
-endtask
-
-endmodule
-
-
Index: simple_spi/trunk/bench/verilog/spi_slave_model.v
===================================================================
--- simple_spi/trunk/bench/verilog/spi_slave_model.v (revision 10)
+++ simple_spi/trunk/bench/verilog/spi_slave_model.v (nonexistent)
@@ -1,125 +0,0 @@
-/////////////////////////////////////////////////////////////////////
-//// ////
-//// SPI Slave Model ////
-//// ////
-//// Authors: Richard Herveille (richard@asics.ws) www.asics.ws ////
-//// ////
-//// http://www.opencores.org/projects/simple_spi/ ////
-//// ////
-/////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2004 Richard Herveille ////
-//// richard@asics.ws ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer.////
-//// ////
-//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
-//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
-//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
-//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
-//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
-//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
-//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
-//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
-//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
-//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
-//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
-//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
-//// POSSIBILITY OF SUCH DAMAGE. ////
-//// ////
-/////////////////////////////////////////////////////////////////////
-
-// CVS Log
-//
-// $Id: spi_slave_model.v,v 1.1 2004-02-28 16:01:47 rherveille Exp $
-//
-// $Date: 2004-02-28 16:01:47 $
-// $Revision: 1.1 $
-// $Author: rherveille $
-// $Locker: $
-// $State: Exp $
-//
-// Change History:
-// $Log: not supported by cvs2svn $
-//
-//
-//
-
-
-// Requires: Verilog2001
-
-`include "timescale.v"
-
-module spi_slave_model (
- input wire csn;
- input wire sck
- input wire di;
- output wire do
-);
-
- //
- // Variable declaration
- //
- wire debug = 1'b1;
-
- wire cpol = 1'b0;
- wire cpha = 1'b0;
-
- reg [7:0] mem [7:0]; // initiate memory
- reg [2:0] mem_adr; // memory address
- reg [7:0] mem_do; // memory data output
-
- reg [7:0] sri, sro; // 8bit shift register
-
- reg [2:0] bit_cnt;
- reg ld;
-
- wire clk;
-
- //
- // module body
- //
-
- assign clk = cpol ^ cpha ^ sck;
-
- // generate shift registers
- always @(posedge clk)
- sri <= #1 {sri[6:0],di};
-
- always @(posedge clk)
- if (&bit_cnt)
- sro <= #1 mem[mem_adr];
- else
- sro <= #1 {sro[6:0],1'bx};
-
- assign do = sro[7];
-
- //generate bit-counter
- always @(posedge clk, posedge csn)
- if(csn)
- bit_cnt <= #1 3'b111;
- else
- bit_cnt <= #1 bit_cnt - 3'h1;
-
- //generate access done signal
- always @(posedge clk)
- ld <= #1 ~(|bit_cnt);
-
- always @(negedge clk)
- if (ld) begin
- mem[mem_adr] <= #1 sri;
- mem_adr <= #1 mem_adr + 1'b1;
- end
-
- initial
- begin
- bit_cnt=3'b111;
- mem_adr = 0;
- sro = mem[mem_adr];
- end
-endmodule
-
-
Index: simple_spi/trunk/rtl/verilog/simple_spi_top.v
===================================================================
--- simple_spi/trunk/rtl/verilog/simple_spi_top.v (revision 10)
+++ simple_spi/trunk/rtl/verilog/simple_spi_top.v (nonexistent)
@@ -1,325 +0,0 @@
-/////////////////////////////////////////////////////////////////////
-//// ////
-//// OpenCores MC68HC11E based SPI interface ////
-//// ////
-//// Author: Richard Herveille ////
-//// richard@asics.ws ////
-//// www.asics.ws ////
-//// ////
-/////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2002 Richard Herveille ////
-//// richard@asics.ws ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer.////
-//// ////
-//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
-//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
-//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
-//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
-//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
-//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
-//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
-//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
-//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
-//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
-//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
-//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
-//// POSSIBILITY OF SUCH DAMAGE. ////
-//// ////
-/////////////////////////////////////////////////////////////////////
-
-// CVS Log
-//
-// $Id: simple_spi_top.v,v 1.5 2004-02-28 15:59:50 rherveille Exp $
-//
-// $Date: 2004-02-28 15:59:50 $
-// $Revision: 1.5 $
-// $Author: rherveille $
-// $Locker: $
-// $State: Exp $
-//
-// Change History:
-// $Log: not supported by cvs2svn $
-// Revision 1.4 2003/08/01 11:41:54 rherveille
-// Fixed some timing bugs.
-//
-// Revision 1.3 2003/01/09 16:47:59 rherveille
-// Updated clkcnt size and decoding due to new SPR bit assignments.
-//
-// Revision 1.2 2003/01/07 13:29:52 rherveille
-// Changed SPR bits coding.
-//
-// Revision 1.1.1.1 2002/12/22 16:07:15 rherveille
-// Initial release
-//
-//
-
-
-
-//
-// Motorola MC68HC11E based SPI interface
-//
-// Currently only MASTER mode is supported
-//
-
-// synopsys translate_off
-`include "timescale.v"
-// synopsys translate_on
-
-module simple_spi_top(
- // 8bit WISHBONE bus slave interface
- input wire clk_i, // clock
- input wire rst_i, // reset (asynchronous active low)
- input wire cyc_i, // cycle
- input wire stb_i, // strobe
- input wire [1:0] adr_i, // address
- input wire we_i, // write enable
- input wire [7:0] dat_i, // data input
- output reg [7:0] dat_o, // data output
- output reg ack_o, // normal bus termination
- output reg inta_o, // interrupt output
-
- // SPI port
- output reg sck_o, // serial clock output
- output wire mosi_o, // MasterOut SlaveIN
- input wire miso_i // MasterIn SlaveOut
-);
-
- //
- // Module body
- //
- reg [7:0] spcr; // Serial Peripheral Control Register ('HC11 naming)
- wire [7:0] spsr; // Serial Peripheral Status register ('HC11 naming)
- reg [7:0] sper; // Serial Peripheral Extension register
- reg [7:0] treg, rreg; // Transmit/Receive register
-
- // fifo signals
- wire [7:0] rfdout;
- reg wfre, rfwe;
- wire rfre, rffull, rfempty;
- wire [7:0] wfdout;
- wire wfwe, wffull, wfempty;
-
- // misc signals
- wire tirq; // transfer interrupt (selected number of transfers done)
- wire wfov; // write fifo overrun (writing while fifo full)
- reg [1:0] state; // statemachine state
- reg [2:0] bcnt;
-
- //
- // Wishbone interface
- wire wb_acc = cyc_i & stb_i; // WISHBONE access
- wire wb_wr = wb_acc & we_i; // WISHBONE write access
-
- // dat_i
- always @(posedge clk_i or negedge rst_i)
- if (~rst_i)
- begin
- spcr <= #1 8'h10; // set master bit
- sper <= #1 8'h00;
- end
- else if (wb_wr)
- begin
- if (adr_i == 2'b00)
- spcr <= #1 dat_i | 8'h10; // always set master bit
-
- if (adr_i == 2'b11)
- sper <= #1 dat_i;
- end
-
- // write fifo
- assign wfwe = wb_acc & (adr_i == 2'b10) & ack_o & we_i;
- assign wfov = wfwe & wffull;
-
- // dat_o
- always @(posedge clk_i)
- case(adr_i) // synopsys full_case parallel_case
- 2'b00: dat_o <= #1 spcr;
- 2'b01: dat_o <= #1 spsr;
- 2'b10: dat_o <= #1 rfdout;
- 2'b11: dat_o <= #1 sper;
- endcase
-
- // read fifo
- assign rfre = wb_acc & (adr_i == 2'b10) & ack_o & ~we_i;
-
- // ack_o
- always @(posedge clk_i or negedge rst_i)
- if (~rst_i)
- ack_o <= #1 1'b0;
- else
- ack_o <= #1 wb_acc & !ack_o;
-
- // decode Serial Peripheral Control Register
- wire spie = spcr[7]; // Interrupt enable bit
- wire spe = spcr[6]; // System Enable bit
- wire dwom = spcr[5]; // Port D Wired-OR Mode Bit
- wire mstr = spcr[4]; // Master Mode Select Bit
- wire cpol = spcr[3]; // Clock Polarity Bit
- wire cpha = spcr[2]; // Clock Phase Bit
- wire [1:0] spr = spcr[1:0]; // Clock Rate Select Bits
-
- // decode Serial Peripheral Extension Register
- wire [1:0] icnt = sper[7:6]; // interrupt on transfer count
- wire [1:0] spre = sper[1:0]; // extended clock rate select
-
- wire [3:0] espr = {spre, spr};
-
- // generate status register
- wire wr_spsr = wb_wr & (adr_i == 2'b01);
-
- reg spif;
- always @(posedge clk_i)
- if (~spe)
- spif <= #1 1'b0;
- else
- spif <= #1 (tirq | spif) & ~(wr_spsr & dat_i[7]);
-
- reg wcol;
- always @(posedge clk_i)
- if (~spe)
- wcol <= #1 1'b0;
- else
- wcol <= #1 (wfov | wcol) & ~(wr_spsr & dat_i[6]);
-
- assign spsr[7] = spif;
- assign spsr[6] = wcol;
- assign spsr[5:4] = 2'b00;
- assign spsr[3] = wffull;
- assign spsr[2] = wfempty;
- assign spsr[1] = rffull;
- assign spsr[0] = rfempty;
-
-
- // generate IRQ output (inta_o)
- always @(posedge clk_i)
- inta_o <= #1 spif & spie;
-
- //
- // hookup read/write buffer fifo
- fifo4 #(8)
- rfifo(
- .clk ( clk_i ),
- .rst ( rst_i ),
- .clr ( ~spe ),
- .din ( treg ),
- .we ( rfwe ),
- .dout ( rfdout ),
- .re ( rfre ),
- .full ( rffull ),
- .empty ( rfempty )
- ),
- wfifo(
- .clk ( clk_i ),
- .rst ( rst_i ),
- .clr ( ~spe ),
- .din ( dat_i ),
- .we ( wfwe ),
- .dout ( wfdout ),
- .re ( wfre ),
- .full ( wffull ),
- .empty ( wfempty )
- );
-
- //
- // generate clk divider
- reg [11:0] clkcnt;
- always @(posedge clk_i)
- if(spe & (|clkcnt & |state))
- clkcnt <= #1 clkcnt - 11'h1;
- else
- case (espr) // synopsys full_case parallel_case
- 4'b0000: clkcnt <= #1 12'h0; // 2 -- original M68HC11 coding
- 4'b0001: clkcnt <= #1 12'h1; // 4 -- original M68HC11 coding
- 4'b0010: clkcnt <= #1 12'h3; // 16 -- original M68HC11 coding
- 4'b0011: clkcnt <= #1 12'hf; // 32 -- original M68HC11 coding
- 4'b0100: clkcnt <= #1 12'h1f; // 8
- 4'b0101: clkcnt <= #1 12'h7; // 64
- 4'b0110: clkcnt <= #1 12'h3f; // 128
- 4'b0111: clkcnt <= #1 12'h7f; // 256
- 4'b1000: clkcnt <= #1 12'hff; // 512
- 4'b1001: clkcnt <= #1 12'h1ff; // 1024
- 4'b1010: clkcnt <= #1 12'h3ff; // 2048
- 4'b1011: clkcnt <= #1 12'h7ff; // 4096
- endcase
-
- // generate clock enable signal
- wire ena = ~|clkcnt;
-
- // transfer statemachine
- always @(posedge clk_i)
- if (~spe)
- begin
- state <= #1 2'b00; // idle
- bcnt <= #1 3'h0;
- treg <= #1 8'h00;
- wfre <= #1 1'b0;
- rfwe <= #1 1'b0;
- sck_o <= #1 1'b0;
- end
- else
- begin
- wfre <= #1 1'b0;
- rfwe <= #1 1'b0;
-
- case (state) //synopsys full_case parallel_case
- 2'b00: // idle state
- begin
- bcnt <= #1 3'h7; // set transfer counter
- treg <= #1 wfdout; // load transfer register
- sck_o <= #1 cpol; // set sck
-
- if (~wfempty) begin
- wfre <= #1 1'b1;
- state <= #1 2'b01;
- if (cpha) sck_o <= #1 ~sck_o;
- end
- end
-
- 2'b01: // clock-phase2, next data
- if (ena) begin
- sck_o <= #1 ~sck_o;
- state <= #1 2'b11;
- end
-
- 2'b11: // clock phase1
- if (ena) begin
- treg <= #1 {treg[6:0], miso_i};
- bcnt <= #1 bcnt -3'h1;
-
- if (~|bcnt) begin
- state <= #1 2'b00;
- sck_o <= #1 cpol;
- rfwe <= #1 1'b1;
- end else begin
- state <= #1 2'b01;
- sck_o <= #1 ~sck_o;
- end
- end
-
- 2'b10: state <= #1 2'b00;
- endcase
- end
-
- assign mosi_o = treg[7];
-
-
- // count number of transfers (for interrupt generation)
- reg [1:0] tcnt; // transfer count
- always @(posedge clk_i)
- if (~spe)
- tcnt <= #1 icnt;
- else if (rfwe) // rfwe gets asserted when all bits have been transfered
- if (|tcnt)
- tcnt <= #1 tcnt - 2'h1;
- else
- tcnt <= #1 icnt;
-
- assign tirq = ~|tcnt & rfwe;
-
-endmodule
-
Index: simple_spi/trunk/rtl/verilog/fifo4.v
===================================================================
--- simple_spi/trunk/rtl/verilog/fifo4.v (revision 10)
+++ simple_spi/trunk/rtl/verilog/fifo4.v (nonexistent)
@@ -1,131 +0,0 @@
-/////////////////////////////////////////////////////////////////////
-//// ////
-//// FIFO 4 entries deep ////
-//// ////
-//// Authors: Rudolf Usselmann, Richard Herveille ////
-//// rudi@asics.ws richard@asics.ws ////
-//// ////
-//// ////
-//// Download from: http://www.opencores.org/projects/sasc ////
-//// http://www.opencores.org/projects/simple_spi ////
-//// ////
-/////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2000-2002 Rudolf Usselmann, Richard Herveille ////
-//// www.asics.ws ////
-//// rudi@asics.ws, richard@asics.ws ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer.////
-//// ////
-//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
-//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
-//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
-//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
-//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
-//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
-//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
-//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
-//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
-//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
-//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
-//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
-//// POSSIBILITY OF SUCH DAMAGE. ////
-//// ////
-/////////////////////////////////////////////////////////////////////
-
-// CVS Log
-//
-// $Id: fifo4.v,v 1.1.1.1 2002-12-22 16:07:14 rherveille Exp $
-//
-// $Date: 2002-12-22 16:07:14 $
-// $Revision: 1.1.1.1 $
-// $Author: rherveille $
-// $Locker: $
-// $State: Exp $
-//
-// Change History:
-// $Log: not supported by cvs2svn $
-//
-
-// synopsys translate_off
-`include "timescale.v"
-// synopsys translate_on
-
-
-// 4 entry deep fast fifo
-module fifo4(clk, rst, clr, din, we, dout, re, full, empty);
-
-parameter dw = 8;
-
-input clk, rst;
-input clr;
-input [dw:1] din;
-input we;
-output [dw:1] dout;
-input re;
-output full, empty;
-
-
-////////////////////////////////////////////////////////////////////
-//
-// Local Wires
-//
-
-reg [dw:1] mem[0:3];
-reg [1:0] wp;
-reg [1:0] rp;
-wire [1:0] wp_p1;
-wire [1:0] wp_p2;
-wire [1:0] rp_p1;
-wire full, empty;
-reg gb;
-
-////////////////////////////////////////////////////////////////////
-//
-// Misc Logic
-//
-
-always @(posedge clk or negedge rst)
- if(!rst) wp <= #1 2'h0;
- else
- if(clr) wp <= #1 2'h0;
- else
- if(we) wp <= #1 wp_p1;
-
-assign wp_p1 = wp + 2'h1;
-assign wp_p2 = wp + 2'h2;
-
-always @(posedge clk or negedge rst)
- if(!rst) rp <= #1 2'h0;
- else
- if(clr) rp <= #1 2'h0;
- else
- if(re) rp <= #1 rp_p1;
-
-assign rp_p1 = rp + 2'h1;
-
-// Fifo Output
-assign dout = mem[ rp ];
-
-// Fifo Input
-always @(posedge clk)
- if(we) mem[ wp ] <= #1 din;
-
-// Status
-assign empty = (wp == rp) & !gb;
-assign full = (wp == rp) & gb;
-
-// Guard Bit ...
-always @(posedge clk)
- if(!rst) gb <= #1 1'b0;
- else
- if(clr) gb <= #1 1'b0;
- else
- if((wp_p1 == rp) & we) gb <= #1 1'b1;
- else
- if(re) gb <= #1 1'b0;
-
-endmodule
Index: simple_spi/trunk/doc/simple_spi.pdf
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: simple_spi/trunk/doc/simple_spi.pdf
===================================================================
--- simple_spi/trunk/doc/simple_spi.pdf (revision 10)
+++ simple_spi/trunk/doc/simple_spi.pdf (nonexistent)
simple_spi/trunk/doc/simple_spi.pdf
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Deleted: svn:mime-type
## -1 +0,0 ##
-application/octet-stream
\ No newline at end of property
Index: simple_spi/trunk/doc/src/simple_spi.doc
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: simple_spi/trunk/doc/src/simple_spi.doc
===================================================================
--- simple_spi/trunk/doc/src/simple_spi.doc (revision 10)
+++ simple_spi/trunk/doc/src/simple_spi.doc (nonexistent)
simple_spi/trunk/doc/src/simple_spi.doc
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Deleted: svn:mime-type
## -1 +0,0 ##
-application/octet-stream
\ No newline at end of property
Index: simple_spi/trunk/sim/rtl_sim/run/Makefile
===================================================================
--- simple_spi/trunk/sim/rtl_sim/run/Makefile (revision 10)
+++ simple_spi/trunk/sim/rtl_sim/run/Makefile (nonexistent)
@@ -1,124 +0,0 @@
-##########################################################################
-# #
-# Simple SPI controller testsuite #
-# (C) 2004 Richard Herveille richard@asics.ws #
-# #
-# v.0 #
-# #
-##########################################################################
-
-all: sim
-SHELL = /bin/sh
-MS="-s"
-
-##########################################################################
-#
-# DUT Sources
-#
-##########################################################################
-DUT_SRC_DIR=../../../rtl/verilog
-_TARGETS_= $(DUT_SRC_DIR)/fifo4.v \
- $(DUT_SRC_DIR)/simple_spi_top.v
-
-##########################################################################
-#
-# Test Bench Sources
-#
-##########################################################################
-_TOP_=tst_bench_top
-TB_SRC_DIR=../../../bench/verilog
-_TB_= $(TB_SRC_DIR)/tst_bench_top.v \
- $(TB_SRC_DIR)/spi_slave_model.v \
- $(TB_SRC_DIR)/wb_master_model.v
-
-##########################################################################
-#
-# Misc Variables
-#
-##########################################################################
-
-INCDIR="-INCDIR ./$(DUT_SRC_DIR)/ -INCDIR ./$(TB_SRC_DIR)/"
-LOGF=-LOGFILE .nclog
-NCCOMMON=-CDSLIB ncwork/cds.lib -HDLVAR ncwork/hdl.var -NOCOPYRIGHT
-
-##########################################################################
-#
-# Make Targets
-#
-##########################################################################
-simw:
- @$(MAKE) -s sim ACCESS="-ACCESS +r " WAVES="-DEFINE WAVES"
-
-ss:
- signalscan -do waves/waves.do -waves waves/waves.trn &
-
-simxl:
- verilog +incdir+$(DUT_SRC_DIR) +incdir+$(TB_SRC_DIR) \
- $(_TARGETS_) $(_TB_)
-
-sim:
- @echo ""
- @echo "----- Running NCVLOG ... ----------"
- @$(MAKE) $(MS) vlog \
- TARGETS="$(_TARGETS_)" \
- TB="$(_TB_)" \
- INCDIR=$(INCDIR) \
- WAVES="$(WAVES)"
- @echo ""
- @echo "----- Running NCELAB ... ----------"
- @$(MAKE) $(MS) elab \
- ACCESS="$(ACCESS)" TOP=$(_TOP_)
- @echo ""
- @echo "----- Running NCSIM ... ----------"
- @$(MAKE) $(MS) ncsim TOP=$(_TOP_)
- @echo ""
-
-hal:
- @echo ""
- @echo "----- Running HAL ... ----------"
- @hal +incdir+$(DUT_SRC_DIR)/ocidec-1/ \
- -NOP -NOS -nocheck STYVAL:USEPRT:NOBLKN:DLNBLK \
- $(_TARGETS_)
- @echo "----- DONE ... ----------"
-
-clean:
- rm -rf ./waves/*.dsn ./waves/*.trn \
- ncwork/.inc* ncwork/inc* \
- ./verilog.* .nclog hal.log
-
-##########################################################################
-#
-# NCVLOG
-#
-##########################################################################
-
-vhdl:
- ncvhdl $(NCCOMMON) $(LOGF) -APPEND_LOG \
- -WORK work -V93 $(TARGETS)
-
-vlog:
- ncvlog $(NCCOMMON) $(LOGF) \
- -WORK work $(WAVES) $(TB) $(TARGETS) $(INCDIR)
-
-##########################################################################
-#
-# NCELAB
-#
-##########################################################################
-
-elab:
- ncelab $(NCCOMMON) $(LOGF) -APPEND_LOG \
- -WORK work $(ACCESS) -NOTIMINGCHECKS \
- work.$(TOP)
-
-##########################################################################
-#
-# NCSIM
-#
-##########################################################################
-
-ncsim:
- ncsim $(NCCOMMON) $(LOGF) -APPEND_LOG \
- -EXIT -ERRORMAX 10 work.$(TOP)
-
-
simple_spi/trunk/sim/rtl_sim/run/Makefile
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: simple_spi/trunk/sim/rtl_sim/run/ncwork/cds.lib
===================================================================
--- simple_spi/trunk/sim/rtl_sim/run/ncwork/cds.lib (revision 10)
+++ simple_spi/trunk/sim/rtl_sim/run/ncwork/cds.lib (nonexistent)
@@ -1,3 +0,0 @@
-DEFINE work work
-INCLUDE /cds/tools/inca/files/cds.lib
-
simple_spi/trunk/sim/rtl_sim/run/ncwork/cds.lib
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: simple_spi/trunk/sim/rtl_sim/run/ncwork/hdl.var
===================================================================
--- simple_spi/trunk/sim/rtl_sim/run/ncwork/hdl.var (revision 10)
+++ simple_spi/trunk/sim/rtl_sim/run/ncwork/hdl.var (nonexistent)
@@ -1,29 +0,0 @@
-#*****************************************************************************
-# NCSIM hdl.var template *
-#*****************************************************************************
-
-#This file allows commonly used tool setups to be invoked automatically.
-#All the switches may be alternatively specifed on the command line.
-
-#reference the tool installation hdl.var - DO NOT REMOVE
-
-INCLUDE $CDS_INST_DIR/tools/inca/files/hdl.var
-
-# These are default settings for NCVLOG, NCVHDL, NCELAB, NCSIM
-# See below for commonly used switches.
-
-DEFINE NCVLOGOPTS -NOCOPYRIGHT -UPDATE
-DEFINE NCVHDLOPTS -NOCOPYRIGHT -UPDATE
-DEFINE NCELABOPTS -NOCOPYRIGHT
-DEFINE NCSIMOPTS -NOCOPYRIGHT -NOKEY -STATUS
-
-#Maps the work library to a logical library.
-#This library will contain the compiled design units
-#Can be overriden on the command line with -work
-DEFINE WORK work
-
-# Define valid Verilog file extensions
-DEFINE VERILOG_SUFFIX (.v, .vr, .vb, .vg)
-
-# Define valid VHDL file extensions
-DEFINE VHDL_SUFFIX (.vhd, .vhdl)
simple_spi/trunk/sim/rtl_sim/run/ncwork/hdl.var
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: simple_spi/trunk/sim/rtl_sim/run/ncwork/work/inca.linux.135.pak
===================================================================
--- simple_spi/trunk/sim/rtl_sim/run/ncwork/work/inca.linux.135.pak (revision 10)
+++ simple_spi/trunk/sim/rtl_sim/run/ncwork/work/inca.linux.135.pak (nonexistent)
@@ -1,2244 +0,0 @@
-çíïé”ÓµëòìôŽÈÀûÖÊÆÞÌõÆÃÉËÞüœÂÙÙЖԔ×ÕÓËÇîðñöê³µ³Â— 9ª¤[—ÊmpjDk pX¸ {U"M?Tz!Bncp/B-I,@n#
-#U9V1r\0Y7B:%#
-{||qkccN
-IV]]|]s\,^1[>])Zu.Mbx:H
kv2Q5Fhm.! C'Tz<0x
fuTuuX_XCCbCmB2@/E C7Dk0S|z9O*X1]2UtU{UzTzU{UzTzU{Uz|?I,^7[4SrSS:k4G+J