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Rev 10 → Rev 9

/yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/src/wb_top.files File deleted
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/src/run_modemsim File deleted
yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/src/run_modemsim Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_ipic.sv =================================================================== --- yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_ipic.sv (revision 10) +++ yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_ipic.sv (revision 9) @@ -100,6 +100,7 @@ function automatic type_scr1_search_one_16_s scr1_search_one_16( input logic [15:0] din ); +begin logic [7:0] stage1_vd; logic [3:0] stage2_vd; logic [1:0] stage3_vd; @@ -108,9 +109,7 @@ logic [1:0] stage2_idx [3:0]; logic [2:0] stage3_idx [1:0]; type_scr1_search_one_16_s result; - type_scr1_search_one_2_s tmp; integer i; // cp.17 -begin // Stage 1 for (i=0; i<8; i=i+1) begin tmp = scr1_search_one_2(din[(i+1)*2-1-:2]); Index: yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_csr.sv =================================================================== --- yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_csr.sv (revision 10) +++ yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_csr.sv (revision 9) @@ -78,7 +78,7 @@ input logic exu2csr_take_exc_i, // Take exception trap input logic exu2csr_mret_update_i, // MRET update CSR input logic exu2csr_mret_instr_i, // MRET instruction - input logic [SCR1_EXC_CODE_WIDTH_E-1:0] exu2csr_exc_code_i, // Exception code (see scr1_arch_types.svh) - cp.7 + input type_scr1_exc_code_e exu2csr_exc_code_i, // Exception code (see scr1_arch_types.svh) input logic [`SCR1_XLEN-1:0] exu2csr_trap_val_i, // Trap value output logic csr2exu_irq_o, // IRQ request output logic csr2exu_ip_ie_o, // Some IRQ pending and locally enabled @@ -181,9 +181,9 @@ logic csr_mcause_upd; // MCAUSE update enable logic csr_mcause_i_ff; // MCAUSE: Interrupt logic csr_mcause_i_next; // MCAUSE: Interrupt next value -logic [SCR1_EXC_CODE_WIDTH_E-1:0] csr_mcause_ec_ff; // MCAUSE: Exception code - cp.7 -logic [SCR1_EXC_CODE_WIDTH_E-1:0] csr_mcause_ec_next; // MCAUSE: Exception code next value - cp.7 -logic [SCR1_EXC_CODE_WIDTH_E-1:0] csr_mcause_ec_new; // MCAUSE: Exception code new value (IRQs) - cp.7 +type_scr1_exc_code_e csr_mcause_ec_ff; // MCAUSE: Exception code +type_scr1_exc_code_e csr_mcause_ec_next; // MCAUSE: Exception code next value +type_scr1_exc_code_e csr_mcause_ec_new; // MCAUSE: Exception code new value (IRQs) // MTVAL register logic csr_mtval_upd; // MTVAL update enable
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_exu.sv
94,7 → 94,7
output logic exu2csr_take_exc_o, // Take exception trap
output logic exu2csr_mret_update_o, // MRET update CSR
output logic exu2csr_mret_instr_o, // MRET instruction
output logic [SCR1_EXC_CODE_WIDTH_E-1:0] exu2csr_exc_code_o, // Exception code (see scr1_arch_types.svh) - cp.7
output type_scr1_exc_code_e exu2csr_exc_code_o, // Exception code (see scr1_arch_types.svh)
output logic [`SCR1_XLEN-1:0] exu2csr_trap_val_o, // Trap value
input logic [`SCR1_XLEN-1:0] csr2exu_new_pc_i, // Exception/IRQ/MRET new PC
input logic csr2exu_irq_i, // IRQ request
103,13 → 103,13
 
// EXU <-> DMEM interface
output logic exu2dmem_req_o, // Data memory request
output logic exu2dmem_cmd_o, // Data memory command - cp.7
output type_scr1_mem_cmd_e exu2dmem_cmd_o, // Data memory command
output type_scr1_mem_width_e exu2dmem_width_o, // Data memory width
output logic [`SCR1_DMEM_AWIDTH-1:0] exu2dmem_addr_o, // Data memory address
output logic [`SCR1_DMEM_DWIDTH-1:0] exu2dmem_wdata_o, // Data memory write data
input logic dmem2exu_req_ack_i, // Data memory request acknowledge
input logic [`SCR1_DMEM_DWIDTH-1:0] dmem2exu_rdata_i, // Data memory read data
input logic [1:0] dmem2exu_resp_i, // Data memory response - cp.7
input type_scr1_mem_resp_e dmem2exu_resp_i, // Data memory response
 
// EXU control
output logic exu2pipe_exc_req_o, // Exception on last instruction
219,7 → 219,7
logic exu_exc_req_ff;
logic exu_exc_req_next;
`endif // SCR1_DBG_EN
logic [SCR1_EXC_CODE_WIDTH_E-1:0] exc_code; // cp.7
type_scr1_exc_code_e exc_code;
logic [`SCR1_XLEN-1:0] exc_trap_val;
logic instr_fault_rvi_hi;
 
263,7 → 263,7
logic lsu_rdy;
logic [`SCR1_XLEN-1:0] lsu_l_data;
logic lsu_exc_req;
logic [SCR1_EXC_CODE_WIDTH_E-1:0] lsu_exc_code; // cp.7
type_scr1_exc_code_e lsu_exc_code;
 
// EXU status signals
//------------------------------------------------------------------------------
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_idu.sv
80,19 → 80,10
assign instr = ifu2idu_instr_i;
 
// RVI / RVC
`ifdef YOSYS
assign instr_type = 2'(instr[1:0]);
`else
assign instr_type = instr[1:0];
 
assign instr_type = type_scr1_instr_type_e'(instr[1:0]);
`endif
 
// RVI / RVC fields
`ifdef YOSYS
assign rvi_opcode = 5'(instr[6:2]); // RVI
`else
assign rvi_opcode = type_scr1_rvi_opcode_e'(instr[6:2]); // RVI
`endif
assign rvi_opcode = instr[6:2]; // RVI
assign funct3 = (instr_type == SCR1_INSTR_RVI) ? instr[14:12] : instr[15:13]; // RVI / RVC
assign funct7 = instr[31:25]; // RVI
assign funct12 = instr[31:20]; // RVI (SYSTEM)
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/src/includes/scr1_wb.svh File deleted
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/src/top/scr1_dmem_wb.sv File deleted
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/src/top/scr1_imem_wb.sv File deleted
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/src/top/scr1_top_wb.sv
1,12 → 1,12
//////////////////////////////////////////////////////////////////////
//// ////
//// yifive Wishbone interface for syntacore ////
//// Syntacore SCR1 interface map to westbone ////
//// ////
//// This file is part of the yifive cores project ////
//// This file is part of the yifive project ////
//// http://www.opencores.org/cores/yifive/ ////
//// ////
//// Description: ////
//// integrated wishbone i/f to instruction/data memory ////
//// Description ////
//// This module does the westbone interface to syntacore/scr1 ////
//// ////
//// To Do: ////
//// nothing ////
13,12 → 13,17
//// ////
//// Author(s): ////
//// - Dinesh Annayya, dinesha@opencores.org ////
//// Initial Author: syntacore
//// - https://github.com/syntacore/scr1
//// ////
//// Revision : ////
//// v0: June 7, 2021, Dinesh A ////
//// wishbone integration ////
//// ////
//////////////////////////////////////////////////////////////////////
//// Revision : 06-June- 2021 ////
//// v-0.0 - Dinesh.A, June 06, 2021 ////
//// 1. Initial Version picked from ////
//// https://github.com/syntacore/scr1 ////
//// 2. Added westone i/f towards instruction ////
//// and data memory ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
44,16 → 49,11
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// Orginal owner Details ////
//////////////////////////////////////////////////////////////////////
/// Copyright by Syntacore LLC © 2016-2020. See LICENSE for details///
/// @file <scr1_top_wb.sv> ///
/// @brief SCR1 AHB top ///
//////////////////////////////////////////////////////////////////////
 
 
`include "scr1_arch_description.svh"
`include "scr1_memif.svh"
`include "scr1_wb.svh"
`include "scr1_ahb.svh"
`ifdef SCR1_IPIC_EN
`include "scr1_ipic.svh"
`endif // SCR1_IPIC_EN
104,24 → 104,28
`endif // SCR1_DBG_EN
 
// Instruction Memory Interface
output logic wbd_imem_stb_o, // strobe/request
output logic [SCR1_WB_WIDTH-1:0] wbd_imem_adr_o, // address
output logic wbd_imem_we_o, // write
output logic [SCR1_WB_WIDTH-1:0] wbd_imem_dat_o, // data output
output logic [3:0] wbd_imem_sel_o, // byte enable
input logic [SCR1_WB_WIDTH-1:0] wbd_imem_dat_i, // data input
input logic wbd_imem_ack_i, // acknowlegement
input logic wbd_imem_err_i, // error
output logic [3:0] imem_hprot,
output logic [2:0] imem_hburst,
output logic [2:0] imem_hsize,
output logic [1:0] imem_htrans,
output logic imem_hmastlock,
output logic [SCR1_AHB_WIDTH-1:0] imem_haddr,
input logic imem_hready,
input logic [SCR1_AHB_WIDTH-1:0] imem_hrdata,
input logic imem_hresp,
 
// Data Memory Interface
output logic wbd_dmem_stb_o, // strobe/request
output logic [SCR1_WB_WIDTH-1:0] wbd_dmem_adr_o, // address
output logic wbd_dmem_we_o, // write
output logic [SCR1_WB_WIDTH-1:0] wbd_dmem_dat_o, // data output
output logic [3:0] wbd_dmem_sel_o, // byte enable
input logic [SCR1_WB_WIDTH-1:0] wbd_dmem_dat_i, // data input
input logic wbd_dmem_ack_i, // acknowlegement
input logic wbd_dmem_err_i // error
output logic [3:0] dmem_hprot,
output logic [2:0] dmem_hburst,
output logic [2:0] dmem_hsize,
output logic [1:0] dmem_htrans,
output logic dmem_hmastlock,
output logic [SCR1_AHB_WIDTH-1:0] dmem_haddr,
output logic dmem_hwrite,
output logic [SCR1_AHB_WIDTH-1:0] dmem_hwdata,
input logic dmem_hready,
input logic [SCR1_AHB_WIDTH-1:0] dmem_hrdata,
input logic dmem_hresp
);
 
//-------------------------------------------------------------------------------
159,23 → 163,23
logic [`SCR1_DMEM_DWIDTH-1:0] core_dmem_rdata;
type_scr1_mem_resp_e core_dmem_resp;
 
// Instruction memory interface from router to WB bridge
logic wb_imem_req_ack;
logic wb_imem_req;
type_scr1_mem_cmd_e wb_imem_cmd;
logic [`SCR1_IMEM_AWIDTH-1:0] wb_imem_addr;
logic [`SCR1_IMEM_DWIDTH-1:0] wb_imem_rdata;
type_scr1_mem_resp_e wb_imem_resp;
// Instruction memory interface from router to AHB bridge
logic ahb_imem_req_ack;
logic ahb_imem_req;
type_scr1_mem_cmd_e ahb_imem_cmd;
logic [`SCR1_IMEM_AWIDTH-1:0] ahb_imem_addr;
logic [`SCR1_IMEM_DWIDTH-1:0] ahb_imem_rdata;
type_scr1_mem_resp_e ahb_imem_resp;
 
// Data memory interface from router to WB bridge
logic wb_dmem_req_ack;
logic wb_dmem_req;
type_scr1_mem_cmd_e wb_dmem_cmd;
type_scr1_mem_width_e wb_dmem_width;
logic [`SCR1_DMEM_AWIDTH-1:0] wb_dmem_addr;
logic [`SCR1_DMEM_DWIDTH-1:0] wb_dmem_wdata;
logic [`SCR1_DMEM_DWIDTH-1:0] wb_dmem_rdata;
type_scr1_mem_resp_e wb_dmem_resp;
// Data memory interface from router to AHB bridge
logic ahb_dmem_req_ack;
logic ahb_dmem_req;
type_scr1_mem_cmd_e ahb_dmem_cmd;
type_scr1_mem_width_e ahb_dmem_width;
logic [`SCR1_DMEM_AWIDTH-1:0] ahb_dmem_addr;
logic [`SCR1_DMEM_DWIDTH-1:0] ahb_dmem_wdata;
logic [`SCR1_DMEM_DWIDTH-1:0] ahb_dmem_rdata;
type_scr1_mem_resp_e ahb_dmem_resp;
 
`ifdef SCR1_TCM_EN
// Instruction memory interface from router to TCM
400,13 → 404,13
.imem_addr (core_imem_addr ),
.imem_rdata (core_imem_rdata ),
.imem_resp (core_imem_resp ),
// Interface to WB bridge
.port0_req_ack (wb_imem_req_ack ),
.port0_req (wb_imem_req ),
.port0_cmd (wb_imem_cmd ),
.port0_addr (wb_imem_addr ),
.port0_rdata (wb_imem_rdata ),
.port0_resp (wb_imem_resp ),
// Interface to AHB bridge
.port0_req_ack (ahb_imem_req_ack ),
.port0_req (ahb_imem_req ),
.port0_cmd (ahb_imem_cmd ),
.port0_addr (ahb_imem_addr ),
.port0_rdata (ahb_imem_rdata ),
.port0_resp (ahb_imem_resp ),
`ifdef SCR1_TCM_EN
// Interface to TCM
.port1_req_ack (tcm_imem_req_ack ),
420,12 → 424,12
 
`else // SCR1_IMEM_ROUTER_EN
 
assign wb_imem_req = core_imem_req;
assign wb_imem_cmd = core_imem_cmd;
assign wb_imem_addr = core_imem_addr;
assign core_imem_req_ack = wb_imem_req_ack;
assign core_imem_resp = wb_imem_resp;
assign core_imem_rdata = wb_imem_rdata;
assign ahb_imem_req = core_imem_req;
assign ahb_imem_cmd = core_imem_cmd;
assign ahb_imem_addr = core_imem_addr;
assign core_imem_req_ack = ahb_imem_req_ack;
assign core_imem_resp = ahb_imem_resp;
assign core_imem_rdata = ahb_imem_rdata;
 
`endif // SCR1_IMEM_ROUTER_EN
 
486,68 → 490,72
.port2_wdata (timer_dmem_wdata ),
.port2_rdata (timer_dmem_rdata ),
.port2_resp (timer_dmem_resp ),
// Interface to WB bridge
.port0_req_ack (wb_dmem_req_ack ),
.port0_req (wb_dmem_req ),
.port0_cmd (wb_dmem_cmd ),
.port0_width (wb_dmem_width ),
.port0_addr (wb_dmem_addr ),
.port0_wdata (wb_dmem_wdata ),
.port0_rdata (wb_dmem_rdata ),
.port0_resp (wb_dmem_resp )
// Interface to AHB bridge
.port0_req_ack (ahb_dmem_req_ack ),
.port0_req (ahb_dmem_req ),
.port0_cmd (ahb_dmem_cmd ),
.port0_width (ahb_dmem_width ),
.port0_addr (ahb_dmem_addr ),
.port0_wdata (ahb_dmem_wdata ),
.port0_rdata (ahb_dmem_rdata ),
.port0_resp (ahb_dmem_resp )
);
 
 
//-------------------------------------------------------------------------------
// Instruction memory WB bridge
// Instruction memory AHB bridge
//-------------------------------------------------------------------------------
scr1_imem_wb i_imem_wb (
scr1_imem_ahb i_imem_ahb (
.rst_n (core_rst_n_local ),
.clk (clk ),
// Interface to imem router
.imem_req_ack (wb_imem_req_ack ),
.imem_req (wb_imem_req ),
.imem_addr (wb_imem_addr ),
.imem_rdata (wb_imem_rdata ),
.imem_resp (wb_imem_resp ),
// WB interface
.wbd_stb_o (wbd_imem_stb_o ),
.wbd_adr_o (wbd_imem_adr_o ),
.wbd_we_o (wbd_imem_we_o ),
.wbd_dat_o (wbd_imem_dat_o ),
.wbd_sel_o (wbd_imem_sel_o ),
.wbd_dat_i (wbd_imem_dat_i ),
.wbd_ack_i (wbd_imem_ack_i ),
.wbd_err_i (wbd_imem_err_i )
.imem_req_ack (ahb_imem_req_ack ),
.imem_req (ahb_imem_req ),
.imem_addr (ahb_imem_addr ),
.imem_rdata (ahb_imem_rdata ),
.imem_resp (ahb_imem_resp ),
// AHB interface
.hprot (imem_hprot ),
.hburst (imem_hburst ),
.hsize (imem_hsize ),
.htrans (imem_htrans ),
.hmastlock (imem_hmastlock ),
.haddr (imem_haddr ),
.hready (imem_hready ),
.hrdata (imem_hrdata ),
.hresp (imem_hresp )
);
 
 
//-------------------------------------------------------------------------------
// Data memory WB bridge
// Data memory AHB bridge
//-------------------------------------------------------------------------------
scr1_dmem_wb i_dmem_wb (
scr1_dmem_ahb i_dmem_ahb (
.rst_n (core_rst_n_local ),
.clk (clk ),
// Interface to dmem router
.dmem_req_ack (wb_dmem_req_ack ),
.dmem_req (wb_dmem_req ),
.dmem_cmd (wb_dmem_cmd ),
.dmem_width (wb_dmem_width ),
.dmem_addr (wb_dmem_addr ),
.dmem_wdata (wb_dmem_wdata ),
.dmem_rdata (wb_dmem_rdata ),
.dmem_resp (wb_dmem_resp ),
// WB interface
.wbd_stb_o (wbd_dmem_stb_o ),
.wbd_adr_o (wbd_dmem_adr_o ),
.wbd_we_o (wbd_dmem_we_o ),
.wbd_dat_o (wbd_dmem_dat_o ),
.wbd_sel_o (wbd_dmem_sel_o ),
.wbd_dat_i (wbd_dmem_dat_i ),
.wbd_ack_i (wbd_dmem_ack_i ),
.wbd_err_i (wbd_dmem_err_i )
.dmem_req_ack (ahb_dmem_req_ack ),
.dmem_req (ahb_dmem_req ),
.dmem_cmd (ahb_dmem_cmd ),
.dmem_width (ahb_dmem_width ),
.dmem_addr (ahb_dmem_addr ),
.dmem_wdata (ahb_dmem_wdata ),
.dmem_rdata (ahb_dmem_rdata ),
.dmem_resp (ahb_dmem_resp ),
// AHB interface
.hprot (dmem_hprot ),
.hburst (dmem_hburst ),
.hsize (dmem_hsize ),
.htrans (dmem_htrans ),
.hmastlock (dmem_hmastlock ),
.haddr (dmem_haddr ),
.hwrite (dmem_hwrite ),
.hwdata (dmem_hwdata ),
.hready (dmem_hready ),
.hrdata (dmem_hrdata ),
.hresp (dmem_hresp )
);
 
endmodule : scr1_top_wb
endmodule : scr1_top_ahb
 
 

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