URL
https://opencores.org/ocsvn/8051/8051/trunk
Subversion Repositories 8051
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 9 to Rev 10
- ↔ Reverse comparison
Rev 9 → Rev 10
/trunk/rtl/verilog/oc8051_alu.v
310,13 → 310,10
end |
//operation pcs Add |
`OC8051_ALU_PCS: begin |
case (src1[7]) |
1'b1: begin |
des1 = src2+src1; |
des2 = src3; |
end |
default: {des2, des1} = {src3,src2} + {8'h00, src1}; |
endcase |
if (src1[7]) begin |
des1 = src2+src1; |
des2 = src3; |
end else {des2, des1} = {src3,src2} + {8'h00, src1}; |
desCy = 1'b0; |
desAc = 1'b0; |
desOv = 1'b0; |
/trunk/rtl/verilog/oc8051_ram_sel.v
99,14 → 99,14
`OC8051_SFR_SCON: out_data = uart; |
`OC8051_SFR_SBUF: out_data = uart; |
`OC8051_SFR_PCON: out_data = uart; |
`OC8051_SFR_TH0: out_data = #1 tc; |
`OC8051_SFR_TH1: out_data = #1 tc; |
`OC8051_SFR_TL0: out_data = #1 tc; |
`OC8051_SFR_TL1: out_data = #1 tc; |
`OC8051_SFR_TMOD: out_data = #1 tc; |
`OC8051_SFR_IP: out_data = #1 int; |
`OC8051_SFR_IE: out_data = #1 int; |
`OC8051_SFR_TCON: out_data = #1 int; |
`OC8051_SFR_TH0: out_data = tc; |
`OC8051_SFR_TH1: out_data = tc; |
`OC8051_SFR_TL0: out_data = tc; |
`OC8051_SFR_TL1: out_data = tc; |
`OC8051_SFR_TMOD: out_data = tc; |
`OC8051_SFR_IP: out_data = int; |
`OC8051_SFR_IE: out_data = int; |
`OC8051_SFR_TCON: out_data = int; |
default: out_data = in_ram; |
endcase |
end |
/trunk/rtl/verilog/oc8051_comp.v
10,7 → 10,7
//// Is used for conditional jumps. //// |
//// //// |
//// To Do: //// |
//// nothing //// |
//// replace CSS_AZ with CSS_DES //// |
//// //// |
//// Author(s): //// |
//// - Simon Teran, simont@opencores.org //// |
/trunk/rtl/verilog/oc8051_pc.v
88,7 → 88,7
|
always @(pc or op1 or rd or int_buff or int_buff1) |
begin |
if (int_buff | int_buff1) |
if (int_buff || int_buff1) |
// |
//in case of interrupt hold valut, to be written to stack |
pc_out= pc; |
/trunk/rtl/verilog/oc8051_decoder.v
1,5 → 1,4
////////////////////////////////////////////////////////////////////// |
//// //// |
////////////////////////////////////////////////////////////////////// //// //// |
//// 8051 core decoder //// |
//// //// |
//// This file is part of the 8051 cores project //// |
/trunk/rtl/verilog/oc8051_uart.v
241,7 → 241,7
end else smod_cnt_r <= #1 1'b1; |
end else begin |
if (sam_cnt==3'b011) begin |
if ((sample[0] % sample[1]) | (sample[0] % sample[2])) |
if ((sample[0] ^ sample[1]) | (sample[0] ^ sample[2])) |
sbuf_rxd_tmp[re_count] <= #1 sample[0]; |
else |
sbuf_rxd_tmp[re_count] <= #1 sample[1]; |
274,7 → 274,7
r_int <= #1 1'b0; |
|
if (sam_cnt==3'b011) begin |
if ((sample[0] % sample[1]) | (sample[0] % sample[2])) |
if ((sample[0] ^ sample[1]) | (sample[0] ^ sample[2])) |
sbuf_rxd_tmp[re_count] <= #1 sample[0]; |
else |
sbuf_rxd_tmp[re_count] <= #1 sample[1]; |
306,13 → 306,13
end else begin |
r_int <= #1 1'b0; |
if (sam_cnt==3'b011) |
if ((sample[0] % sample[1]) | (sample[0] % sample[2])) |
if ((sample[0] ^ sample[1]) | (sample[0] ^ sample[2])) |
sbuf_rxd_tmp[re_count] <= #1 sample[0]; |
else |
sbuf_rxd_tmp[re_count] <= #1 sample[1]; |
else begin |
sample[sam_cnt[1:0]] <= #1 rxd; |
sam_cnt <= #1 sam_cnt +1'b1; |
sam_cnt <= #1 sam_cnt + 1'b1; |
end |
end |
end |