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Rev 9 → Rev 10

/trunk/bench/verilog/test_bench_top.v
37,10 → 37,10
 
// CVS Log
//
// $Id: test_bench_top.v,v 1.2 2001-08-10 08:16:21 rudi Exp $
// $Id: test_bench_top.v,v 1.3 2001-09-02 02:29:43 rudi Exp $
//
// $Date: 2001-08-10 08:16:21 $
// $Revision: 1.2 $
// $Date: 2001-09-02 02:29:43 $
// $Revision: 1.3 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
47,6 → 47,12
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.2 2001/08/10 08:16:21 rudi
//
// - Changed IO names to be more clear.
// - Uniquifyed define names to be core specific.
// - Removed "Refresh Early" configuration
//
// Revision 1.1 2001/07/29 07:34:40 rudi
//
//
119,6 → 125,7
integer verbose;
integer poc_mode;
reg wb_err_check_dis;
integer LVL;
 
integer cyc_cnt;
integer ack_cnt;
212,7 → 219,8
verbose = 1;
mc_br = 0;
 
repeat(10) @(posedge clk);
repeat(11) @(posedge clk);
#1;
rst = 1;
repeat(10) @(posedge clk);
 
296,6 → 304,7
sdram_wr5(2);
`endif
 
 
`ifdef FLASH
asc_rdwr1(2);
`endif
320,49 → 329,54
 
verbose = 0;
done = 0;
LVL = 1;
 
fork
 
begin
 
`ifdef FLASH
boot(2);
boot(LVL);
`endif
m0.wb_wr1(`REG_BASE + `CSC3, 4'hf, 32'h0000_0000);
 
while(susp_req | suspended) @(posedge clk);
sdram_rd1(2);
sdram_rd1(LVL);
while(susp_req | suspended) @(posedge clk);
sdram_wr1(2);
sdram_wr1(LVL);
while(susp_req | suspended) @(posedge clk);
sdram_rd2(2);
sdram_rd2(LVL);
 
 
while(susp_req | suspended) @(posedge clk);
sdram_wr2(2);
sdram_wr2(LVL);
 
while(susp_req | suspended) @(posedge clk);
sdram_rd3(2);
sdram_rd3(LVL);
while(susp_req | suspended) @(posedge clk);
sdram_wr3(2);
sdram_wr3(LVL);
while(susp_req | suspended) @(posedge clk);
sdram_rd4(2);
sdram_rd4(LVL);
while(susp_req | suspended) @(posedge clk);
sdram_wr4(2);
sdram_wr4(LVL);
 
while(susp_req | suspended) @(posedge clk);
sdram_wp(2);
 
sdram_wp(LVL);
while(susp_req | suspended) @(posedge clk);
sdram_rmw1(2);
 
sdram_rmw1(LVL);
while(susp_req | suspended) @(posedge clk);
sdram_rmw2(2);
sdram_rmw2(LVL);
 
`ifdef MULTI_SDRAM
while(susp_req | suspended) @(posedge clk);
sdram_rd5(2);
sdram_rd5(LVL);
while(susp_req | suspended) @(posedge clk);
sdram_wr5(2);
sdram_wr5(LVL);
`endif
 
`ifdef FLASH
while(susp_req | suspended) @(posedge clk);
asc_rdwr1(2);
asc_rdwr1(LVL);
`endif
 
`ifdef SRAM
373,13 → 387,19
while(susp_req | suspended) @(posedge clk);
sram_wp;
while(susp_req | suspended) @(posedge clk);
sram_wp;
while(susp_req | suspended) @(posedge clk);
sram_rmw1;
 
while(susp_req | suspended) @(posedge clk);
sram_rmw1;
while(susp_req | suspended) @(posedge clk);
sram_rmw2;
`endif
while(susp_req | suspended) @(posedge clk);
scs_rdwr1(2);
scs_rdwr1(LVL);
 
 
done = 1;
end
 
391,11 → 411,12
susp_res;
end
end
 
join
end
else
if(0) // Bus Request testing
//else
mc_reset;
 
if(1) // Bus Request testing
begin
$display(" ......................................................");
$display(" : :");
403,31 → 424,33
$display(" :....................................................:");
verbose = 0;
done = 0;
LVL = 1;
fork
 
begin
`ifdef FLASH
boot(2);
boot(LVL);
`endif
 
m0.wb_wr1(`REG_BASE + `CSC3, 4'hf, 32'h0000_0000);
sdram_rd1(2);
sdram_wr1(2);
sdram_rd3(2);
sdram_wr3(2);
sdram_rd4(2);
sdram_wr4(2);
sdram_wp(2);
sdram_rmw1(2);
sdram_rmw2(2);
sdram_rd1(LVL);
sdram_wr1(LVL);
sdram_rd1(LVL);
sdram_wr1(LVL);
sdram_rd3(LVL);
sdram_wr3(LVL);
sdram_rd4(LVL);
sdram_wr4(LVL);
sdram_wp(LVL);
sdram_rmw1(LVL);
sdram_rmw2(LVL);
 
`ifdef MULTI_SDRAM
sdram_rd5(2);
sdram_wr5(2);
sdram_rd5(LVL);
sdram_wr5(LVL);
`endif
 
`ifdef FLASH
asc_rdwr1(2);
asc_rdwr1(LVL);
`endif
 
`ifdef SRAM
437,7 → 460,7
sram_rmw1;
sram_rmw2;
`endif
scs_rdwr1(2);
scs_rdwr1(LVL);
 
done = 1;
end
460,6 → 483,7
$display(" : :");
$display(" : Test Debug Testing ... :");
$display(" :....................................................:");
//verbose = 0;
//boot(2);
 
`define CSR 8'h00
466,28 → 490,6
`define POC 8'h04
`define BA_MASK 8'h08
 
//m0.wb_wr1(`REG_BASE + `BA_MASK, 4'hf, 32'h0000_00ff);
//m0.wb_rd1(`REG_BASE + `BA_MASK, 4'hf, data );
//$display("rd ba_mask: %h", data);
//m0.wb_wr1(`REG_BASE + `CSR, 4'hf, 32'h6100_0400);
//m0.wb_rd1(`REG_BASE + `CSR, 4'hf, data );
//$display("rd csr: %h", data);
//m0.wb_rd1(`REG_BASE + `BA_MASK, 4'hf, data );
//$display("rd ba_mask: %h", data);
 
//sdram_rmw1(2);
//sram_rmw1;
//sdram_wp(2);
 
//verbose = 0;
 
//sdram_rd3(2);
//sdram_wr3(2);
//scs_rdwr1(2);
//sram_wp;
 
//boot(2);
 
m0.wb_wr1(`REG_BASE + `CSC3, 4'hf, 32'h0000_0000);
//sdram_rmw2(2);
 
505,43 → 507,33
//asc_rdwr1(2);
//asc_rdwr1_x(2);
 
sdram_rd1(2);
sdram_wr1(2);
sram_rd1;
sram_wr1;
 
//sdram_wp(2);
//sdram_rmw1(2);
//sdram_rmw2(2);
//sdram_rd5(2);
//sdram_wr5(2);
 
//sdram_rd1(2);
//sdram_wr1(2);
//sdram_rd2(2);
//sdram_wr2(2);
sdram_wr1(2);
/*
`ifdef FLASH
asc_rdwr1(2);
`endif
sdram_rd1(2);
sram_rd1;
sram_wr1;
*/
sdram_wr1(2);
sdram_rd2(2);
sdram_wr2(2);
sdram_rd3(2);
sdram_wr3(2);
sdram_rd4(2);
sdram_wr4(2);
 
//asc_rdwr1(2);
sdram_rd5(2);
sdram_wr5(2);
 
//sdram_rd1(2);
//sdram_rd2(2);
//sdram_rd3(2);
//sdram_rd4(2);
sdram_wp(2);
sdram_rmw1(2);
sdram_rmw2(2);
*/
 
//sdram_wr1(2);
//sdram_wr2(2);
//sdram_wr3(2);
//sdram_wr4(2);
//sdram_rmw2(2);
 
`ifdef MULTI_SDRAM
//sdram_rd5(2);
//sdram_wr5(2);
`endif
 
repeat(100) @(posedge clk);
$finish;
end
551,126 → 543,94
//
// TEST DEVELOPMENT AREA
//
$display("\n\n");
$display("*****************************************************");
$display("*** Test Development ... ***");
$display("*****************************************************\n");
 
$display("\n\n");
$display("*****************************************************");
$display("*** SDRAM Size, Delay & Mode XXX test ... ***");
$display("*****************************************************\n");
 
repeat(2500) @(posedge clk);
//m0.wb_rd_mult(`MEM_BASE, 4'hf, 0, 1);
//m0.wb_rd_mult(`MEM_BASE + 4, 4'hf, 0, 1);
repeat(25) @(posedge clk);
show_errors;
$display("*****************************************************");
$display("*** Test DONE ... ***");
$display("*****************************************************\n\n");
end
 
//m0.wb_wr1(`REG_BASE + `CSC3, 4'hf, 32'h0000_0000);
m0.wb_wr1(`REG_BASE + `CSR, 4'hf, 32'h6030_0200);
m0.wb_wr1(`REG_BASE + `BA_MASK, 4'hf, 32'h0000_00f0);
repeat(100) @(posedge clk);
$finish;
 
//m0.wb_wr1(`REG_BASE + `CSC0, 4'hf, 32'h0080_0000);
//m0.wb_wr1(`REG_BASE + `CSC1, 4'hf, 32'h0080_0000);
//m0.wb_wr1(`REG_BASE + `CSC2, 4'hf, 32'h0080_0000);
//m0.wb_wr1(`REG_BASE + `CSC3, 4'hf, 32'h0080_0000);
end // End of Initial
 
m0.wb_wr1(`REG_BASE + `TMS4, 4'hf, 32'hffff_ffff);
m0.wb_wr1(`REG_BASE + `CSC4, 4'hf, 32'h0080_0001);
 
repeat(800) @(posedge clk);
$finish;
/////////////////////////////////////////////////////////////////////
//
// Clock Generation
//
 
size = 4;
del = 4;
mode = 0;
read = 0;
write = 1;
always #2.5 clk = ~clk;
 
sram0a.mem_fill( 256 );
sram0b.mem_fill( 256 );
always @(posedge clk)
//#0.5 mc_clk <= ~mc_clk;
//#4.5 mc_clk <= ~mc_clk;
mc_clk <= ~mc_clk;
 
repeat(1) @(posedge clk);
/////////////////////////////////////////////////////////////////////
//
// IO Monitors
//
 
for(del=0;del<16;del=del+1)
for(size=1;size<18;size=size+1)
begin
m0.mem_fill;
`define STD 10
always @(posedge clk)
if((wb_ack_o === 1'bx) & ($time > `STD) )
begin
$display("ERROR: Wishbone ACK unknown (%t)", $time);
error_cnt = error_cnt + 1;
end
 
$display("Size: %0d, Delay: %0d", size, del);
//bw_clear;
always @(posedge clk)
if( (wb_err_o === 1'bx) & ($time > `STD) )
 
if(write) m0.wb_wr_mult(`MEM_BASE4 + 0*4, 4'hf, del, size);
if(read) m0.wb_rd_mult(`MEM_BASE4 + 0*4, 4'hf, del, size);
if(write) m0.wb_wr_mult(`MEM_BASE4 + 32*4, 4'hf, del, size);
if(read) m0.wb_rd_mult(`MEM_BASE4 + 32*4, 4'hf, del, size);
if(write) m0.wb_wr_mult(`MEM_BASE4 + 64*4, 4'hf, del, size);
if(read) m0.wb_rd_mult(`MEM_BASE4 + 64*4, 4'hf, del, size);
if(write) m0.wb_wr_mult(`MEM_BASE4 + 96*4, 4'hf, del, size);
if(read) m0.wb_rd_mult(`MEM_BASE4 + 96*4, 4'hf, del, size);
begin
$display("ERROR: Wishbone ERR unknown (%t)", $time);
error_cnt = error_cnt + 1;
end
 
always @(posedge clk)
if( (mc_ras_ === 1'bx) & ($time > `STD) )
 
//bw_report;
begin
$display("ERROR: MC RAS unknown (%t)", $time);
error_cnt = error_cnt + 1;
end
 
repeat(10) @(posedge clk);
always @(posedge clk)
if( (mc_cas_ === 1'bx) & ($time > `STD) )
 
for(m=0;m< 4;m=m+1)
for(n=0;n< size;n=n+1)
begin
$display("ERROR: MC CAS unknown (%t)", $time);
error_cnt = error_cnt + 1;
end
 
/*
data[07:00] = sram0a.memb1[(m*32)+n];
data[15:08] = sram0a.memb2[(m*32)+n];
data[23:16] = sram0b.memb1[(m*32)+n];
data[31:24] = sram0b.memb2[(m*32)+n];
always @(posedge clk)
if( (mc_we_ === 1'bx) & ($time > `STD) )
 
begin
$display("ERROR: MC WE unknown (%t)", $time);
error_cnt = error_cnt + 1;
end
 
data[07:00] = sram0a.bank0[(m*4)+n];
data[15:08] = sram0a.bank1[(m*4)+n];
data[23:16] = sram0b.bank0[(m*4)+n];
data[31:24] = sram0b.bank1[(m*4)+n];
*/
always @(posedge clk)
if( ((|mc_cs_) === 1'bx) & ($time > `STD) )
 
//$display("INFO: Data[%0d]: Expected: %x, Got: %x (%0t)",
// (m*4)+n, data, m0.wr_mem[(m*size)+n], $time);
 
if(data !== m0.wr_mem[(m*size)+n])
begin
$display("ERROR: Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)",
(m*32)+n, data, m0.wr_mem[(m*size)+n], $time);
error_cnt = error_cnt + 1;
end
 
begin
$display("ERROR: MC CS unknown (%t)", $time);
error_cnt = error_cnt + 1;
end
 
end
always @(error_cnt)
if(error_cnt > 25) #500 $finish;
 
show_errors;
$display("*****************************************************");
$display("*** Test DONE ... ***");
$display("*****************************************************\n\n");
 
 
repeat(100) @(posedge clk);
$finish;
 
end
 
repeat(100) @(posedge clk);
$finish;
end
 
 
/////////////////////////////////////////////////////////////////////
//
// Clock Generation
//
 
always #2.5 clk = ~clk;
 
always @(posedge clk)
//#0.5 mc_clk <= ~mc_clk;
//#4.5 mc_clk <= ~mc_clk;
mc_clk <= ~mc_clk;
 
/////////////////////////////////////////////////////////////////////
//
// IO Buffers
//
 
700,25 → 660,25
default: rst_dq_val = 32'hzzzz_zzzz;
endcase
 
assign mc_dq = mc_data_oe ? mc_data_o : (~rst ? rst_dq_val : 32'hzzzz_zzzz);
assign mc_data_i = mc_dq;
assign #1 mc_dq = mc_data_oe ? mc_data_o : (~rst ? rst_dq_val : 32'hzzzz_zzzz);
assign #1 mc_data_i = mc_dq;
 
assign mc_dqp = mc_data_oe ? mc_dp_o : 4'hz;
assign mc_dp_i = mc_dqp;
assign #1 mc_dqp = mc_data_oe ? mc_dp_o : 4'hz;
assign #1 mc_dp_i = mc_dqp;
 
assign mc_addr = mc_c_oe ? _mc_addr : 24'bz;
assign mc_dqm = mc_c_oe ? _mc_dqm : 4'bz;
assign mc_oe_ = mc_c_oe ? _mc_oe_ : 1'bz;
assign mc_we_ = mc_c_oe ? _mc_we_ : 1'bz;
assign mc_cas_ = mc_c_oe ? _mc_cas_ : 1'bz;
assign mc_ras_ = mc_c_oe ? _mc_ras_ : 1'bz;
assign mc_cke_ = mc_c_oe ? _mc_cke_ : 1'bz;
assign mc_cs_ = mc_c_oe ? _mc_cs_ : 8'bz;
assign mc_rp_ = mc_c_oe ? _mc_rp_ : 1'bz;
assign mc_vpen = mc_c_oe ? _mc_vpen : 1'bz;
assign mc_adsc_ = mc_c_oe ? _mc_adsc_ : 1'bz;
assign mc_adv_ = mc_c_oe ? _mc_adv_ : 1'bz;
assign mc_zz = mc_c_oe ? _mc_zz : 1'bz;
assign #1 mc_addr = mc_c_oe ? _mc_addr : 24'bz;
assign #1 mc_dqm = mc_c_oe ? _mc_dqm : 4'bz;
assign #1 mc_oe_ = mc_c_oe ? _mc_oe_ : 1'bz;
assign #1 mc_we_ = mc_c_oe ? _mc_we_ : 1'bz;
assign #1 mc_cas_ = mc_c_oe ? _mc_cas_ : 1'bz;
assign #1 mc_ras_ = mc_c_oe ? _mc_ras_ : 1'bz;
assign #1 mc_cke_ = mc_c_oe ? _mc_cke_ : 1'bz;
assign #1 mc_cs_ = mc_c_oe ? _mc_cs_ : 8'bz;
assign #1 mc_rp_ = mc_c_oe ? _mc_rp_ : 1'bz;
assign #1 mc_vpen = mc_c_oe ? _mc_vpen : 1'bz;
assign #1 mc_adsc_ = mc_c_oe ? _mc_adsc_ : 1'bz;
assign #1 mc_adv_ = mc_c_oe ? _mc_adv_ : 1'bz;
assign #1 mc_zz = mc_c_oe ? _mc_zz : 1'bz;
 
pullup p0(mc_cas_);
pullup p1(mc_ras_);
/trunk/bench/verilog/tests.v
37,10 → 37,10
 
// CVS Log
//
// $Id: tests.v,v 1.2 2001-08-10 08:16:21 rudi Exp $
// $Id: tests.v,v 1.3 2001-09-02 02:29:43 rudi Exp $
//
// $Date: 2001-08-10 08:16:21 $
// $Revision: 1.2 $
// $Date: 2001-09-02 02:29:43 $
// $Revision: 1.3 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
47,6 → 47,12
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.2 2001/08/10 08:16:21 rudi
//
// - Changed IO names to be more clear.
// - Uniquifyed define names to be core specific.
// - Removed "Refresh Early" configuration
//
// Revision 1.1 2001/07/29 07:34:40 rudi
//
//
82,7 → 88,14
m0.wb_wr1(`REG_BASE + `CSR, 4'hf, 32'h6030_0300);
m0.wb_wr1(`REG_BASE + `BA_MASK, 4'hf, 32'h0000_00f0);
 
m0.wb_wr1(`REG_BASE + `TMS0, 4'hf, {22'h3fff_ff,
m0.wb_wr1(`REG_BASE + `TMS0, 4'hf, {
4'd0, // RESERVED [31:28]
4'd7, // Trfc [27:24]
4'd2, // Trp [23:20]
3'd2, // Trcd [19:17]
2'd1, // Twr [16:15]
5'd0, // RESERVED [14:10]
 
1'd0, // Wr. Burst Len (1=Single)
2'd0, // Op Mode
3'd2, // CL
90,7 → 103,8
3'd3 // Burst Length
});
 
m0.wb_wr1(`REG_BASE + `CSC0, 4'hf, 32'h0000_0821);
//m0.wb_wr1(`REG_BASE + `CSC0, 4'hf, 32'h0000_0821);
m0.wb_wr1(`REG_BASE + `CSC0, 4'hf, 32'h0000_0021);
 
case(quick)
0: sz_max = 64;
104,15 → 118,16
2: del_max = 4;
endcase
 
size = 8;
del = 0;
mode = 8;
write = 1;
size = 4;
del = 1;
mode = 2;
write = 0;
//force sdram0.Debug = 1;
 
for(mode=0;mode<10;mode=mode+1)
begin
sdram0.mem_fill(1024);
//sdram0p.mem_fill(1024);
 
case(mode[3:1])
0: bs = 0;
130,7 → 145,13
4: sz_inc = 1;
endcase
 
m0.wb_wr1(`REG_BASE + `TMS0, 4'hf, {22'h3fff_ff,
m0.wb_wr1(`REG_BASE + `TMS0, 4'hf, {
4'd0, // RESERVED [31:28]
4'd7, // Trfc [27:24]
4'd2, // Trp [23:20]
3'd2, // Trcd [19:17]
2'd1, // Twr [16:15]
5'd0, // RESERVED [14:10]
1'd0, // Wr. Burst Len (1=Single)
2'd0, // Op Mode
3'd2+mode[0], // CL
203,7 → 224,13
m0.wb_wr1(`REG_BASE + `CSR, 4'hf, 32'h6030_0300);
m0.wb_wr1(`REG_BASE + `BA_MASK, 4'hf, 32'h0000_00f0);
 
m0.wb_wr1(`REG_BASE + `TMS0, 4'hf, {22'h3fff_ff,
m0.wb_wr1(`REG_BASE + `TMS0, 4'hf, {
4'd0, // RESERVED [31:28]
4'd7, // Trfc [27:24]
4'd2, // Trp [23:20]
3'd2, // Trcd [19:17]
2'd1, // Twr [16:15]
5'd0, // RESERVED [14:10]
1'd0, // Wr. Burst Len (1=Single)
2'd0, // Op Mode
3'd2, // CL
225,8 → 252,8
2: del_max = 4;
endcase
 
size = 2;
del = 2;
size = 1;
del = 0;
mode = 0;
read = 1;
//force sdram0.Debug = 1;
254,7 → 281,13
4: sz_inc = 1;
endcase
 
m0.wb_wr1(`REG_BASE + `TMS0, 4'hf, {22'h3fff_ff,
m0.wb_wr1(`REG_BASE + `TMS0, 4'hf, {
4'd0, // RESERVED [31:28]
4'd7, // Trfc [27:24]
4'd2, // Trp [23:20]
3'd2, // Trcd [19:17]
2'd1, // Twr [16:15]
5'd0, // RESERVED [14:10]
1'd0+mode[1], // Wr. Burst Len (1=Single)
2'd0, // Op Mode
3'd2+mode[0], // CL
347,7 → 380,13
m0.wb_wr1(`REG_BASE + `CSR, 4'hf, 32'h6030_0300);
m0.wb_wr1(`REG_BASE + `BA_MASK, 4'hf, 32'h0000_00f0);
 
m0.wb_wr1(`REG_BASE + `TMS0, 4'hf, {22'h3fff_ff,
m0.wb_wr1(`REG_BASE + `TMS0, 4'hf, {
4'd0, // RESERVED [31:28]
4'd7, // Trfc [27:24]
4'd2, // Trp [23:20]
3'd2, // Trcd [19:17]
2'd1, // Twr [16:15]
5'd0, // RESERVED [14:10]
1'd0, // Wr. Burst Len (1=Single)
2'd0, // Op Mode
3'd2, // CL
386,7 → 425,13
4: sz_inc = 1;
endcase
 
m0.wb_wr1(`REG_BASE + `TMS0, 4'hf, {22'h3fff_ff,
m0.wb_wr1(`REG_BASE + `TMS0, 4'hf, {
4'd0, // RESERVED [31:28]
4'd7, // Trfc [27:24]
4'd2, // Trp [23:20]
3'd2, // Trcd [19:17]
2'd1, // Twr [16:15]
5'd0, // RESERVED [14:10]
1'd0, // Wr. Burst Len (1=Single)
2'd0, // Op Mode
3'd2+mode[0], // CL
489,7 → 534,13
m0.wb_wr1(`REG_BASE + `CSR, 4'hf, 32'h6030_0300);
m0.wb_wr1(`REG_BASE + `BA_MASK, 4'hf, 32'h0000_00f0);
 
m0.wb_wr1(`REG_BASE + `TMS0, 4'hf, {22'h3fff_ff,
m0.wb_wr1(`REG_BASE + `TMS0, 4'hf, {
4'd0, // RESERVED [31:28]
4'd7, // Trfc [27:24]
4'd2, // Trp [23:20]
3'd2, // Trcd [19:17]
2'd1, // Twr [16:15]
5'd0, // RESERVED [14:10]
1'd0, // Wr. Burst Len (1=Single)
2'd0, // Op Mode
3'd2, // CL
501,7 → 552,8
for(bas=0;bas<2;bas=bas+1)
begin
 
m0.wb_wr1(`REG_BASE + `CSC0, 4'hf, 32'h0000_0821 | (bas[0]<<9));
//m0.wb_wr1(`REG_BASE + `CSC0, 4'hf, 32'h0000_0821 | (bas[0]<<9));
m0.wb_wr1(`REG_BASE + `CSC0, 4'hf, 32'h0000_0021 | (bas[0]<<9));
 
case(quick)
0: sz_max = 32;
515,9 → 567,9
2: del_max = 4;
endcase
 
size = 4;
del = 2;
mode = 4;
size = 3;
del = 0;
mode = 10;
read = 1;
//force sdram0.Debug = 1;
 
526,16 → 578,19
sdram0.mem_fill(1024);
 
case(mode[4:2])
0: bs = 0;
1: bs = 1;
2: bs = 2;
3: bs = 3;
4: bs = 7;
0: bs = 0; // 1 Transfer
1: bs = 1; // 2 Transfers
2: bs = 2; // 4 Transfers
3: bs = 3; // 8 Transfers
4: bs = 7; // Page Size Transfer
endcase
 
if(mode[1])
sz_inc = 1;
begin
sz_inc = 1;
end
else
begin
case(mode[4:2])
0: sz_inc = 1;
1: sz_inc = 2;
543,6 → 598,7
3: sz_inc = 8;
4: sz_inc = 1;
endcase
end
 
m0.wb_wr1(`REG_BASE + `TMS0, 4'hf, { // 22'h3fff_ff,
 
550,7 → 606,7
4'd7, // Trfc [27:24]
4'd2, // Trp [23:20]
3'd2, // Trcd [19:17]
2'd2, // Twr [16:15]
2'd1, // Twr [16:15]
5'd0, // RESERVED [14:10]
 
1'd0+mode[1], // Wr. Burst Len (1=Single)
606,6 → 662,16
3: data = sdram0.Bank3[n+3*size*2];
endcase
 
 
if(read & 0)
if((data !== m0.rd_mem[(m*size*2)+n]) | (|data === 1'bx) |
(|m0.rd_mem[(m*size*2)+n] === 1'bx) )
begin
$display("ERROR: RD Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)",
(m*size*2)+n, data, m0.rd_mem[(m*size*2)+n], $time);
error_cnt = error_cnt + 1;
end
 
if((data !== m0.wr_mem[(m*size*2)+n]) | (|data === 1'bx) |
(|m0.wr_mem[(m*size*2)+n] === 1'bx) )
begin
652,7 → 718,13
m0.wb_wr1(`REG_BASE + `CSR, 4'hf, 32'h6030_0300);
m0.wb_wr1(`REG_BASE + `BA_MASK, 4'hf, 32'h0000_00f0);
 
m0.wb_wr1(`REG_BASE + `TMS0, 4'hf, {22'h3fff_ff,
m0.wb_wr1(`REG_BASE + `TMS0, 4'hf, {
4'd0, // RESERVED [31:28]
4'd7, // Trfc [27:24]
4'd2, // Trp [23:20]
3'd2, // Trcd [19:17]
2'd1, // Twr [16:15]
5'd0, // RESERVED [14:10]
1'd0, // Wr. Burst Len (1=Single)
2'd0, // Op Mode
3'd2, // CL
708,16 → 780,6
4: sz_inc = 1;
endcase
 
/*
m0.wb_wr1(`REG_BASE + `TMS0, 4'hf, {22'h3fff_ff,
1'd0, // Wr. Burst Len (1=Single)
2'd0, // Op Mode
3'd2+mode[0], // CL
1'b0, // Burst Type (0=Seq;1=Inter)
3'd0+bs // Burst Length
});
*/
 
m0.wb_wr1(`REG_BASE + `TMS0, 4'hf, {
 
4'd0, // RESERVED [31:28]
736,10 → 798,7
 
 
if(!verbose) $display("Mode: %b", mode);
//repeat(200) @(posedge clk);
 
//$display("\n\n");
 
for(del=0;del<del_max;del=del+1)
for(size=sz_inc;size<sz_max;size=size+sz_inc)
begin
746,8 → 805,6
m0.mem_fill;
 
if(verbose) $display("Mode: %b, Size: %0d, Delay: %0d", mode, size, del);
//if(verbose) $display("Mode: %b, SDRAM BS: %0d, Tx Size: %0d, Delay: %0d",
// mode, sbs, size, del);
 
//bw_clear;
if(write) m0.wb_wr_mult(`MEM_BASE + 0, 4'hf, del, size);
811,7 → 868,13
m0.wb_wr1(`REG_BASE + `CSR, 4'hf, 32'h6030_0300);
m0.wb_wr1(`REG_BASE + `BA_MASK, 4'hf, 32'h0000_00f0);
 
m0.wb_wr1(`REG_BASE + `TMS0, 4'hf, {22'h3fff_ff,
m0.wb_wr1(`REG_BASE + `TMS0, 4'hf, {
4'd0, // RESERVED [31:28]
4'd7, // Trfc [27:24]
4'd2, // Trp [23:20]
3'd2, // Trcd [19:17]
2'd1, // Twr [16:15]
5'd0, // RESERVED [14:10]
1'd0, // Wr. Burst Len (1=Single)
2'd0, // Op Mode
3'd2, // CL
975,7 → 1038,13
m0.wb_wr1(`REG_BASE + `CSR, 4'hf, 32'h6030_0300);
m0.wb_wr1(`REG_BASE + `BA_MASK, 4'hf, 32'h0000_00f0);
 
m0.wb_wr1(`REG_BASE + `TMS0, 4'hf, {22'h3fff_ff,
m0.wb_wr1(`REG_BASE + `TMS0, 4'hf, {
4'd0, // RESERVED [31:28]
4'd7, // Trfc [27:24]
4'd2, // Trp [23:20]
3'd2, // Trcd [19:17]
2'd1, // Twr [16:15]
5'd0, // RESERVED [14:10]
1'd0, // Wr. Burst Len (1=Single)
2'd0, // Op Mode
3'd2, // CL
1014,7 → 1083,13
4: sz_inc = 1;
endcase
 
m0.wb_wr1(`REG_BASE + `TMS0, 4'hf, {22'h3fff_ff,
m0.wb_wr1(`REG_BASE + `TMS0, 4'hf, {
4'd0, // RESERVED [31:28]
4'd7, // Trfc [27:24]
4'd2, // Trp [23:20]
3'd2, // Trcd [19:17]
2'd1, // Twr [16:15]
5'd0, // RESERVED [14:10]
1'd0, // Wr. Burst Len (1=Single)
2'd0, // Op Mode
3'd2+mode[0], // CL
1126,7 → 1201,13
m0.wb_wr1(`REG_BASE + `CSR, 4'hf, 32'h6030_0300);
m0.wb_wr1(`REG_BASE + `BA_MASK, 4'hf, 32'h0000_00f0);
 
m0.wb_wr1(`REG_BASE + `TMS0, 4'hf, {22'h3fff_ff,
m0.wb_wr1(`REG_BASE + `TMS0, 4'hf, {
4'd0, // RESERVED [31:28]
4'd7, // Trfc [27:24]
4'd2, // Trp [23:20]
3'd2, // Trcd [19:17]
2'd1, // Twr [16:15]
5'd0, // RESERVED [14:10]
1'd0, // Wr. Burst Len (1=Single)
2'd0, // Op Mode
3'd2, // CL
1181,7 → 1262,13
4: sz_inc = 1;
endcase
 
m0.wb_wr1(`REG_BASE + `TMS0, 4'hf, {22'h3fff_ff,
m0.wb_wr1(`REG_BASE + `TMS0, 4'hf, {
4'd0, // RESERVED [31:28]
4'd7, // Trfc [27:24]
4'd2, // Trp [23:20]
3'd2, // Trcd [19:17]
2'd1, // Twr [16:15]
5'd0, // RESERVED [14:10]
1'd0+mode[1], // Wr. Burst Len (1=Single)
2'd0, // Op Mode
3'd2+mode[0], // CL
1294,13 → 1381,19
case(quick)
0: del_max = 16;
1: del_max = 8;
2: del_max = 4;
2: del_max = 8;
endcase
 
m0.wb_wr1(`REG_BASE + `CSR, 4'hf, 32'h6030_0300);
m0.wb_wr1(`REG_BASE + `BA_MASK, 4'hf, 32'h0000_00f0);
 
m0.wb_wr1(`REG_BASE + `TMS0, 4'hf, {22'h3fff_ff,
m0.wb_wr1(`REG_BASE + `TMS0, 4'hf, {
4'd0, // RESERVED [31:28]
4'd7, // Trfc [27:24]
4'd2, // Trp [23:20]
3'd2, // Trcd [19:17]
2'd1, // Twr [16:15]
5'd0, // RESERVED [14:10]
1'd0, // Wr. Burst Len (1=Single)
2'd0, // Op Mode
3'd2, // CL
1308,7 → 1401,13
3'd3 // Burst Length
});
 
m0.wb_wr1(`REG_BASE + `TMS1, 4'hf, {22'h3fff_ff,
m0.wb_wr1(`REG_BASE + `TMS1, 4'hf, {
4'd0, // RESERVED [31:28]
4'd7, // Trfc [27:24]
4'd2, // Trp [23:20]
3'd2, // Trcd [19:17]
2'd1, // Twr [16:15]
5'd0, // RESERVED [14:10]
1'd0, // Wr. Burst Len (1=Single)
2'd0, // Op Mode
3'd2, // CL
1316,7 → 1415,13
3'd3 // Burst Length
});
 
m0.wb_wr1(`REG_BASE + `TMS2, 4'hf, {22'h3fff_ff,
m0.wb_wr1(`REG_BASE + `TMS2, 4'hf, {
4'd0, // RESERVED [31:28]
4'd7, // Trfc [27:24]
4'd2, // Trp [23:20]
3'd2, // Trcd [19:17]
2'd1, // Twr [16:15]
5'd0, // RESERVED [14:10]
1'd0, // Wr. Burst Len (1=Single)
2'd0, // Op Mode
3'd2, // CL
1324,7 → 1429,7
3'd3 // Burst Length
});
 
bas = 1;
bas = 0;
for(bas=0;bas<2;bas=bas+1)
begin
m0.wb_wr1(`REG_BASE + `CSC0, 4'hf, 32'h0000_0421 | (bas[0]<<9));
1331,9 → 1436,9
m0.wb_wr1(`REG_BASE + `CSC1, 4'hf, 32'h0020_0021 | (bas[0]<<9));
m0.wb_wr1(`REG_BASE + `CSC2, 4'hf, 32'h0040_0421 | (bas[0]<<9));
 
size = 1;
del = 0;
mode = 0;
size = 15;
del = 3;
mode = 9;
write = 1;
if(0)
begin
1342,6 → 1447,7
force sdram2.Debug = 1;
end
 
//for(mode=0;mode<10;mode=mode+1)
for(mode=0;mode<10;mode=mode+1)
begin
sdram0.mem_fill(1024);
1355,7 → 1461,7
3: bs = 3;
4: bs = 7;
endcase
 
case(mode[3:1])
0: sz_inc = 1;
1: sz_inc = 2;
1364,7 → 1470,13
4: sz_inc = 1;
endcase
 
m0.wb_wr1(`REG_BASE + `TMS0, 4'hf, {22'h3fff_ff,
m0.wb_wr1(`REG_BASE + `TMS0, 4'hf, {
4'd0, // RESERVED [31:28]
4'd7, // Trfc [27:24]
4'd2, // Trp [23:20]
3'd2, // Trcd [19:17]
2'd1, // Twr [16:15]
5'd0, // RESERVED [14:10]
1'd0, // Wr. Burst Len (1=Single)
2'd0, // Op Mode
3'd2+mode[0], // CL
1372,7 → 1484,13
3'd0+bs // Burst Length
});
 
m0.wb_wr1(`REG_BASE + `TMS1, 4'hf, {22'h3fff_ff,
m0.wb_wr1(`REG_BASE + `TMS1, 4'hf, {
4'd0, // RESERVED [31:28]
4'd7, // Trfc [27:24]
4'd2, // Trp [23:20]
3'd2, // Trcd [19:17]
2'd1, // Twr [16:15]
5'd0, // RESERVED [14:10]
1'd0, // Wr. Burst Len (1=Single)
2'd0, // Op Mode
3'd2+mode[0], // CL
1380,7 → 1498,13
3'd0+bs // Burst Length
});
 
m0.wb_wr1(`REG_BASE + `TMS2, 4'hf, {22'h3fff_ff,
m0.wb_wr1(`REG_BASE + `TMS2, 4'hf, {
4'd0, // RESERVED [31:28]
4'd7, // Trfc [27:24]
4'd2, // Trp [23:20]
3'd2, // Trcd [19:17]
2'd1, // Twr [16:15]
5'd0, // RESERVED [14:10]
1'd0, // Wr. Burst Len (1=Single)
2'd0, // Op Mode
3'd3-mode[0], // CL
1513,6 → 1637,7
$display("ERROR: Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)",
(m*size*2)+n, data, m0.rd_mem[(m*size*2)+n], $time);
error_cnt = error_cnt + 1;
if(error_cnt > 25) $finish;
end
 
end
1555,10 → 1680,21
 
page_size = 256; // 64 mbit x 32 SDRAM
 
m0.wb_wr1(`REG_BASE + `CSC0, 4'hf, 32'h0000_0000);
m0.wb_wr1(`REG_BASE + `CSC1, 4'hf, 32'h0000_0000);
m0.wb_wr1(`REG_BASE + `CSC2, 4'hf, 32'h0000_0000);
repeat(10) @(posedge clk);
 
m0.wb_wr1(`REG_BASE + `CSR, 4'hf, 32'h6030_0300);
m0.wb_wr1(`REG_BASE + `BA_MASK, 4'hf, 32'h0000_00f0);
 
m0.wb_wr1(`REG_BASE + `TMS0, 4'hf, {22'h3fff_ff,
m0.wb_wr1(`REG_BASE + `TMS0, 4'hf, {
4'd0, // RESERVED [31:28]
4'd7, // Trfc [27:24]
4'd2, // Trp [23:20]
3'd2, // Trcd [19:17]
2'd1, // Twr [16:15]
5'd0, // RESERVED [14:10]
1'd0, // Wr. Burst Len (1=Single)
2'd0, // Op Mode
3'd2, // CL
1566,7 → 1702,13
3'd3 // Burst Length
});
 
m0.wb_wr1(`REG_BASE + `TMS1, 4'hf, {22'h3fff_ff,
m0.wb_wr1(`REG_BASE + `TMS1, 4'hf, {
4'd0, // RESERVED [31:28]
4'd7, // Trfc [27:24]
4'd2, // Trp [23:20]
3'd2, // Trcd [19:17]
2'd1, // Twr [16:15]
5'd0, // RESERVED [14:10]
1'd0, // Wr. Burst Len (1=Single)
2'd0, // Op Mode
3'd2, // CL
1574,7 → 1716,13
3'd3 // Burst Length
});
 
m0.wb_wr1(`REG_BASE + `TMS2, 4'hf, {22'h3fff_ff,
m0.wb_wr1(`REG_BASE + `TMS2, 4'hf, {
4'd0, // RESERVED [31:28]
4'd7, // Trfc [27:24]
4'd2, // Trp [23:20]
3'd2, // Trcd [19:17]
2'd1, // Twr [16:15]
5'd0, // RESERVED [14:10]
1'd0, // Wr. Burst Len (1=Single)
2'd0, // Op Mode
3'd2, // CL
1582,7 → 1730,7
3'd3 // Burst Length
});
 
bas = 1;
bas = 0;
for(bas=0;bas<2;bas=bas+1)
begin
 
1599,7 → 1747,7
case(quick)
0: del_max = 16;
1: del_max = 8;
2: del_max = 4;
2: del_max = 8;
endcase
 
size = 5;
1640,7 → 1788,13
4: sz_inc = 1;
endcase
 
m0.wb_wr1(`REG_BASE + `TMS0, 4'hf, {22'h3fff_ff,
m0.wb_wr1(`REG_BASE + `TMS0, 4'hf, {
4'd0, // RESERVED [31:28]
4'd7, // Trfc [27:24]
4'd2, // Trp [23:20]
3'd2, // Trcd [19:17]
2'd1, // Twr [16:15]
5'd0, // RESERVED [14:10]
1'd0+mode[1], // Wr. Burst Len (1=Single)
2'd0, // Op Mode
3'd2+mode[0], // CL
1649,7 → 1803,13
});
 
 
m0.wb_wr1(`REG_BASE + `TMS1, 4'hf, {22'h3fff_ff,
m0.wb_wr1(`REG_BASE + `TMS1, 4'hf, {
4'd0, // RESERVED [31:28]
4'd7, // Trfc [27:24]
4'd2, // Trp [23:20]
3'd2, // Trcd [19:17]
2'd1, // Twr [16:15]
5'd0, // RESERVED [14:10]
1'd0+mode[1], // Wr. Burst Len (1=Single)
2'd0, // Op Mode
3'd3-mode[0], // CL
1658,7 → 1818,13
});
 
 
m0.wb_wr1(`REG_BASE + `TMS2, 4'hf, {22'h3fff_ff,
m0.wb_wr1(`REG_BASE + `TMS2, 4'hf, {
4'd0, // RESERVED [31:28]
4'd7, // Trfc [27:24]
4'd2, // Trp [23:20]
3'd2, // Trcd [19:17]
2'd1, // Twr [16:15]
5'd0, // RESERVED [14:10]
1'd0+mode[1], // Wr. Burst Len (1=Single)
2'd0, // Op Mode
3'd2+mode[0], // CL
1668,7 → 1834,7
 
if(!verbose) $display("BAS: %0d, Mode: %b", bas, mode);
 
//for(del=0;del<del_max;del=del+1)
for(del=0;del<del_max;del=del+1)
for(size=sz_inc;size<sz_max;size=size+sz_inc)
begin
m0.mem_fill;
1737,7 → 1903,6
begin
adr = (m * page_size) + (m*size*2) + n;
 
/*
case(s)
0: if(bas[0]) data = sdram0.Bank0[adr];
else
1747,53 → 1912,6
2: data = sdram0.Bank2[n+2*size*2];
3: data = sdram0.Bank3[n+3*size*2];
endcase
1: if(bas[0]) data = {sdram1b.Bank0[adr],sdram1a.Bank0[adr]};
else
case(m)
0: data = {sdram1b.Bank0[n],sdram1a.Bank0[n]};
1: data = {sdram1b.Bank1[n+1*size*2],sdram1a.Bank1[n+1*size*2]};
2: data = {sdram1b.Bank2[n+2*size*2],sdram1a.Bank2[n+2*size*2]};
3: data = {sdram1b.Bank3[n+3*size*2],sdram1a.Bank3[n+3*size*2]};
endcase
2: if(bas[0]) data = {sdram2d.Bank0[adr],
sdram2c.Bank0[adr],
sdram2b.Bank0[adr],
sdram2a.Bank0[adr]};
else
case(m)
0: data = { sdram2a.Bank0[n],
sdram2b.Bank0[n],
sdram2c.Bank0[n],
sdram2d.Bank0[n] };
1: data = { sdram2a.Bank1[n+1*size*2],
sdram2b.Bank1[n+1*size*2],
sdram2c.Bank1[n+1*size*2],
sdram2d.Bank1[n+1*size*2] };
2: data = { sdram2a.Bank2[n+2*size*2],
sdram2b.Bank2[n+2*size*2],
sdram2c.Bank2[n+2*size*2],
sdram2d.Bank2[n+2*size*2] };
3: data = { sdram2a.Bank3[n+3*size*2],
sdram2b.Bank3[n+3*size*2],
sdram2c.Bank3[n+3*size*2],
sdram2d.Bank3[n+3*size*2] };
endcase
endcase
 
*/
 
 
 
 
case(s)
0: if(bas[0]) data = sdram0.Bank0[adr];
else
case(m)
0: data = sdram0.Bank0[n];
1: data = sdram0.Bank1[n+1*size*2];
2: data = sdram0.Bank2[n+2*size*2];
3: data = sdram0.Bank3[n+3*size*2];
endcase
1: if(bas[0]) data = sdram1.Bank0[adr];
else
case(m)
1812,9 → 1930,6
endcase
endcase
 
 
 
 
if((data !== m0.wr_mem[(m*size*6)+(s*size*2)+n]) | (|data === 1'bx) |
(|m0.wr_mem[(m*size*6)+(s*size*2)+n] === 1'bx) )
begin
1821,6 → 1936,8
$display("ERROR: WR Data[%0d-%0d] Mismatch: Expected: %x, Got: %x (%0t)",
s, (m*size*2)+n, data, m0.wr_mem[(m*size*2)+n], $time);
error_cnt = error_cnt + 1;
 
if(error_cnt > 25) $finish;
end
 
end
1852,10 → 1969,9
integer sz_max, del_max;
integer read;
reg [2:0] bas;
reg [31:0] data;
reg [31:0] data, exp;
 
begin
 
$display("\n\n");
$display("*****************************************************");
$display("*** ASC Read/Write Test 1 ... ***");
1866,10 → 1982,6
 
m0.wb_wr1(`REG_BASE + `TMS3, 4'hf, 32'hffff_f40a);
 
//m0.wb_wr1(`REG_BASE + `CSC3, 4'hf, 32'h0060_0025); // 32 bit bus
//m0.wb_wr1(`REG_BASE + `CSC3, 4'hf, 32'h0060_0005); // 8 bit bus
//m0.wb_wr1(`REG_BASE + `CSC3, 4'hf, 32'h0060_0015); // 16 bit bus
 
case(quick)
0: sz_max = 32;
1: sz_max = 32;
1894,7 → 2006,6
 
repeat(1) @(posedge clk);
 
 
case(mode)
0: m0.wb_wr1(`REG_BASE + `CSC3, 4'hf, 32'h0060_0025); // 32 bit bus
1: m0.wb_wr1(`REG_BASE + `CSC3, 4'hf, 32'h0060_0005); // 8 bit bus
1901,12 → 2012,11
2: m0.wb_wr1(`REG_BASE + `CSC3, 4'hf, 32'h0060_0015); // 16 bit bus
endcase
 
 
repeat(10) @(posedge clk);
if(!verbose) $display("Mode: %b", mode);
 
//for(del=0;del<del_max;del=del+1)
//for(size=1;size<sz_max;size=size+1)
for(del=0;del<del_max;del=del+1)
for(size=1;size<sz_max;size=size+1)
begin
m0.mem_fill;
for(n=0;n<1024;n=n+1)
1933,7 → 2043,7
begin
 
case(mode)
0: data = {16'hzzzz, n[15:0]};
0: data = {16'hxxxx, n[15:0]};
1:
begin
data[31:24] = x[7:0]+3;
1941,7 → 2051,6
data[15:08] = x[7:0]+1;
data[07:00] = x[7:0]+0;
end
 
2: begin
data[31:16] = x[15:0]+1;
data[15:00] = x[15:0]+0;
1954,13 → 2063,13
2: x = x + 2;
endcase
 
//$display("INFO: Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)",
// n, data, m0.rd_mem[n], $time);
exp = m0.rd_mem[n];
if(mode==0) exp[31:16] = data[31:16];
 
if(data !== m0.rd_mem[n])
if(data !== exp)
begin
$display("ERROR: Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)",
n, data, m0.rd_mem[n], $time);
n, data, exp, $time);
error_cnt = error_cnt + 1;
end
end
2005,10 → 2114,6
m0.wb_wr1(`REG_BASE + `TMS3, 4'hf, 32'h0005_2004);
m0.wb_wr1(`REG_BASE + `CSC3, 4'hf, 32'h0060_0005);
 
//m0.wb_wr1(`REG_BASE + `CSC3, 4'hf, 32'h0060_0025); // 32 bit bus
//m0.wb_wr1(`REG_BASE + `CSC3, 4'hf, 32'h0060_0005); // 8 bit bus
//m0.wb_wr1(`REG_BASE + `CSC3, 4'hf, 32'h0060_0015); // 16 bit bus
 
case(quick)
0: sz_max = 32;
1: sz_max = 32;
2117,8 → 2222,6
endtask
 
 
 
 
task boot;
input quick;
 
2131,7 → 2234,7
integer sz_max, del_max;
integer read;
reg [2:0] bas;
reg [31:0] data;
reg [31:0] data, exp;
 
begin
$display("\n\n");
2208,7 → 2311,7
begin
 
case(mode)
0: data = {16'hzzzz, n[15:0]};
0: data = {16'hxxxx, n[15:0]};
1:
begin
data[31:24] = x[7:0]+3;
2229,13 → 2332,13
2: x = x + 2;
endcase
 
//$display("INFO: Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)",
// n, data, m0.rd_mem[n], $time);
exp = m0.rd_mem[n];
if(mode==0) exp[31:16] = data[31:16];
 
if(data !== m0.rd_mem[n])
if(data !== exp)
begin
$display("ERROR: Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)",
n, data, m0.rd_mem[n], $time);
n, data, exp, $time);
error_cnt = error_cnt + 1;
end
end
2313,9 → 2416,6
data[31:24] = sram0b.memb2[(m*4)+n];
`endif
 
//$display("INFO: Data[%0d]: Expected: %x, Got: %x (%0t)",
// (m*4)+n, data, m0.rd_mem[(m*size)+n], $time);
 
if(data !== m0.rd_mem[(m*size)+n])
begin
$display("ERROR: Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)",
2335,10 → 2435,6
end
endtask
 
 
 
 
 
task sram_wr1;
 
integer n,m,read,write;
2358,7 → 2454,7
m0.wb_wr1(`REG_BASE + `CSC4, 4'hf, 32'h0080_0803);
 
size = 4;
del = 0;
del = 26;
mode = 0;
read = 1;
write = 1;
2405,9 → 2501,6
data[31:24] = sram0b.memb2[(m*32)+n];
`endif
 
//$display("INFO: Data[%0d]: Expected: %x, Got: %x (%0t)",
// (m*4)+n, data, m0.wr_mem[(m*size)+n], $time);
 
if(data !== m0.wr_mem[(m*size)+n])
begin
$display("ERROR: Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)",
2476,7 → 2569,6
read = 1;
write = 0;
 
 
s0.mem_fill;
 
repeat(5) @(posedge clk);
2506,33 → 2598,7
for(n=0;n<(size*4);n=n+1)
begin
 
/*
case(mode)
0: data = {16'hzzzz, n[15:0]};
1:
begin
data[31:24] = x[7:0]+3;
data[23:16] = x[7:0]+2;
data[15:08] = x[7:0]+1;
data[07:00] = x[7:0]+0;
end
 
2: begin
data[31:16] = x[15:0]+1;
data[15:00] = x[15:0]+0;
end
endcase
 
case(mode)
0: x = x + 1;
1: x = x + 4;
2: x = x + 2;
endcase
*/
 
data = s0.mem[n];
//$display("INFO: Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)",
// n, data, m0.rd_mem[n], $time);
 
if(data !== m0.rd_mem[n])
begin
2554,7 → 2620,6
endtask
 
 
 
task sdram_wp;
input quick;
 
2576,7 → 2641,13
m0.wb_wr1(`REG_BASE + `CSR, 4'hf, 32'h6020_0200);
m0.wb_wr1(`REG_BASE + `BA_MASK, 4'hf, 32'h0000_00f0);
 
m0.wb_wr1(`REG_BASE + `TMS0, 4'hf, {22'h3fff_ff,
m0.wb_wr1(`REG_BASE + `TMS0, 4'hf, {
4'd0, // RESERVED [31:28]
4'd7, // Trfc [27:24]
4'd2, // Trp [23:20]
3'd2, // Trcd [19:17]
2'd1, // Twr [16:15]
5'd0, // RESERVED [14:10]
1'd0, // Wr. Burst Len (1=Single)
2'd0, // Op Mode
3'd2, // CL
2600,8 → 2671,8
2: del_max = 4;
endcase
 
size = 1;
del = 0;
size = 4;
del = 4;
mode = 0;
read = 1;
//force sdram0.Debug = 1;
2629,7 → 2700,13
4: sz_inc = 1;
endcase
 
m0.wb_wr1(`REG_BASE + `TMS0, 4'hf, {22'h3fff_ff,
m0.wb_wr1(`REG_BASE + `TMS0, 4'hf, {
4'd0, // RESERVED [31:28]
4'd7, // Trfc [27:24]
4'd2, // Trp [23:20]
3'd2, // Trcd [19:17]
2'd1, // Twr [16:15]
5'd0, // RESERVED [14:10]
1'd0+mode[1], // Wr. Burst Len (1=Single)
2'd0, // Op Mode
3'd2+mode[0], // CL
2684,8 → 2761,6
endtask
 
 
 
 
task sram_wp;
 
integer n,m,read,write;
2704,8 → 2779,8
m0.wb_wr1(`REG_BASE + `TMS4, 4'hf, 32'hffff_ffff);
m0.wb_wr1(`REG_BASE + `CSC4, 4'hf, 32'h0080_0903);
 
size = 4;
del = 0;
size = 17;
del = 15;
mode = 0;
read = 1;
write = 1;
2753,9 → 2828,6
data[31:24] = sram0b.memb2[(m*32)+n];
`endif
 
//$display("INFO: Data[%0d]: Expected: %x, Got: %x (%0t)",
// (m*4)+n, data, m0.wr_mem[(m*size)+n], $time);
 
if(data == m0.wr_mem[(m*size)+n])
begin
$display("ERROR: Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)",
2778,7 → 2850,6
endtask
 
 
 
task sdram_rmw1;
input quick;
 
2822,7 → 2893,13
m0.wb_wr1(`REG_BASE + `CSR, 4'hf, 32'h6030_0300);
m0.wb_wr1(`REG_BASE + `BA_MASK, 4'hf, 32'h0000_00f0);
 
m0.wb_wr1(`REG_BASE + `TMS0, 4'hf, {22'h3fff_ff,
m0.wb_wr1(`REG_BASE + `TMS0, 4'hf, {
4'd0, // RESERVED [31:28]
4'd7, // Trfc [27:24]
4'd2, // Trp [23:20]
3'd2, // Trcd [19:17]
2'd1, // Twr [16:15]
5'd0, // RESERVED [14:10]
1'd0, // Wr. Burst Len (1=Single)
2'd0, // Op Mode
3'd2, // CL
2837,7 → 2914,7
 
size = 4;
del = 0;
mode = 4;
mode = 0;
 
//force sdram0.Debug = 1;
 
2860,7 → 2937,13
4: sz_inc = 1;
endcase
 
m0.wb_wr1(`REG_BASE + `TMS0, 4'hf, {22'h3fff_ff,
m0.wb_wr1(`REG_BASE + `TMS0, 4'hf, {
4'd0, // RESERVED [31:28]
4'd7, // Trfc [27:24]
4'd2, // Trp [23:20]
3'd2, // Trcd [19:17]
2'd1, // Twr [16:15]
5'd0, // RESERVED [14:10]
1'd0+mode[0], // Wr. Burst Len (1=Single)
2'd0, // Op Mode
3'd2, // CL
2971,10 → 3054,6
reg [2:0] kro;
reg [31:0] data, data1;
integer page_size;
//reg [31:0] mem0[0:1024];
//reg [31:0] mem1[0:1024];
//reg [31:0] mem2[0:1024];
//reg [31:0] mem3[0:1024];
 
begin
 
3001,7 → 3080,13
m0.wb_wr1(`REG_BASE + `CSR, 4'hf, 32'h6030_0300);
m0.wb_wr1(`REG_BASE + `BA_MASK, 4'hf, 32'h0000_00f0);
 
m0.wb_wr1(`REG_BASE + `TMS0, 4'hf, {22'h3fff_ff,
m0.wb_wr1(`REG_BASE + `TMS0, 4'hf, {
4'd0, // RESERVED [31:28]
4'd7, // Trfc [27:24]
4'd2, // Trp [23:20]
3'd2, // Trcd [19:17]
2'd1, // Twr [16:15]
5'd0, // RESERVED [14:10]
1'd0, // Wr. Burst Len (1=Single)
2'd0, // Op Mode
3'd2, // CL
3014,9 → 3099,9
begin
m0.wb_wr1(`REG_BASE + `CSC0, 4'hf, 32'h0000_0821 | (kro[0]<<10));
 
size = 4;
del = 2;
mode = 9;
size = 1;
del = 0;
mode = 0;
 
//force sdram0.Debug = 1;
 
3039,7 → 3124,15
4: sz_inc = 1;
endcase
 
m0.wb_wr1(`REG_BASE + `TMS0, 4'hf, {22'h3fff_ff,
m0.wb_wr1(`REG_BASE + `TMS0, 4'hf, {
 
4'd0, // RESERVED [31:28]
4'd7, // Trfc [27:24]
4'd2, // Trp [23:20]
3'd2, // Trcd [19:17]
2'd1, // Twr [16:15]
5'd0, // RESERVED [14:10]
 
1'd0+mode[0], // Wr. Burst Len (1=Single)
2'd0, // Op Mode
3'd2, // CL
3114,6 → 3207,7
$display("\n\n");
$display("*****************************************************");
$display("*** SRAM Size & Delay RMW Test 1 ... ***");
$display("*** Time: %t", $time);
$display("*****************************************************\n");
 
m0.wb_wr1(`REG_BASE + `CSR, 4'hf, 32'h6030_0300);
3174,6 → 3268,7
$display("ERROR: RD Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)",
(m*32)+n, data, m0.rd_mem[(m*size)+n], $time);
error_cnt = error_cnt + 1;
if(error_cnt > 10) $finish;
end
 
`ifdef MICRON
3193,12 → 3288,9
$display("ERROR: WR Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)",
(m*32)+n, data, m0.wr_mem[(m*size)+n], $time);
error_cnt = error_cnt + 1;
if(error_cnt > 10) $finish;
end
 
 
 
 
 
end
 
end
3278,7 → 3370,6
for(n=0;n< size;n=n+1)
begin
 
data = mem[(m*32)+n];
data = m0.wr_mem[(m*size)+n];
 
if(data !== m0.rd_mem[(m*size)+n])
3288,30 → 3379,6
error_cnt = error_cnt + 1;
end
 
/*
`ifdef MICRON
data[07:00] = sram0a.bank0[(m*32)+n];
data[15:08] = sram0a.bank1[(m*32)+n];
data[23:16] = sram0b.bank0[(m*32)+n];
data[31:24] = sram0b.bank1[(m*32)+n];
`else
data[07:00] = sram0a.memb1[(m*32)+n];
data[15:08] = sram0a.memb2[(m*32)+n];
data[23:16] = sram0b.memb1[(m*32)+n];
data[31:24] = sram0b.memb2[(m*32)+n];
`endif
 
if(data !== m0.wr_mem[(m*size)+n])
begin
$display("ERROR: WR Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)",
(m*32)+n, data, m0.wr_mem[(m*size)+n], $time);
error_cnt = error_cnt + 1;
end
*/
 
 
 
 
end
 
end
/trunk/bench/verilog/160b3ver/adv_bb.v
425,7 → 425,7
//$display("Initializing Memory to 'hFFFF");
//for (LoopCntr = 0; LoopCntr <= `MaxAddr; LoopCntr = LoopCntr + 1) begin
// MainArray [LoopCntr] = 16'hFFFF ;
$display("Initializing Memory data to address value (0, 1, 2 ...)");
$display("FLASH: Initializing Memory data to address value (0, 1, 2 ...)");
for (LoopCntr = 0; LoopCntr <= 1024; LoopCntr = LoopCntr + 1) begin
MainArray [LoopCntr] = LoopCntr ;
 
443,7 → 443,7
 
task LoadFromFile ;
begin
$display("Loading from file %s",LoadFileName);
$display("FLASH: Loading from file %s",LoadFileName);
$readmemh(LoadFileName,MainArray);
end
endtask
461,9 → 461,9
begin
outfile = $fopen(SaveFileName) ;
if (outfile == 0)
$display("Error, cannot open output file %s",SaveFileName) ;
$display("FLASH: Error, cannot open output file %s",SaveFileName) ;
else
$display("Saving data to file %s",SaveFileName);
$display("FLASH: Saving data to file %s",SaveFileName);
for (ArrayAddr = 0 ; ArrayAddr <= `MaxAddr; ArrayAddr = ArrayAddr + 1) begin
$fdisplay(outfile,"%h",MainArray[ArrayAddr]);
end
582,18 → 582,18
if ( (EraseSuspended == `TRUE) && (WriteSuspended == `FALSE)
&& (addr >= BlocksBegin[Algorithm[`OpBlock]])
&& (addr <= BlocksEnd[Algorithm[`OpBlock]]) && (oeb == `VIL) ) begin
$display("Error: Attempting to read from erase suspended block");
$display("FLASH: Error: Attempting to read from erase suspended block");
InternalOutput <= `MaxOutputs'hxxxx;
end
else if ( (WriteSuspended == `TRUE) && (EraseSuspended == `TRUE)
&& (addr >= BlocksBegin[SuspendedAlg[`OpBlock]])
&& (addr <= BlocksEnd[SuspendedAlg[`OpBlock]]) && (oeb == `VIL)) begin
$display("Error: Attempting to read from erase suspended block");
$display("FLASH: Error: Attempting to read from erase suspended block");
InternalOutput <= `MaxOutputs'hxxxx;
end
else if ( (WriteSuspended == `TRUE) && (addr == Algorithm[`CmdAdd_1])
&& (oeb == `VIL) ) begin
$display("Error: Attempting to read from write suspended address");
$display("FLASH: Error: Attempting to read from write suspended address");
InternalOutput = `MaxOutputs'hxxxx;
end
else
606,7 → 606,7
InternalOutput <= #ToOut IDOut ;
end
default : begin
$display("Error: illegal readmode");
$display("FLASH: Error: illegal readmode");
end
endcase
end
652,11 → 652,11
Cmd[`CmdAdd_2] = addr[`AddrSize-1:0];
end
else
$display("DataPtr out of range");
$display("FLASH: DataPtr out of range");
DataPtr <= #1 DataPtr - 1 ; // When DataPtr = 0 the command goes to Decode section
end
default : begin
$display("Error: Write To ? Cmd");
$display("FLASH: Error: Write To ? Cmd");
end
endcase
end
685,7 → 685,7
// READ INTELLIGENT IDENTIFIER COMMAND --
`ReadIDCmd : begin // Read Intelligent ID
if ((WriteSuspended == `TRUE) || (EraseSuspended == `TRUE))
$display("Invalid read ID command during suspend");
$display("FLASH: Invalid read ID command during suspend");
else
ReadMode <= `rdID ;
CmdValid <= `FALSE ;
702,7 → 702,7
// PROGRAM WORD COMMAND --
`ProgramCmd : begin // Program Word
if (WriteSuspended == `TRUE) begin
$display("Error: Program Command during Write Suspend");
$display("FLASH: Error: Program Command during Write Suspend");
CmdValid <= `FALSE;
end
else begin
719,7 → 719,7
// PROGRAM WORD COMMAND --
`Program2Cmd : begin // Program Word
if (WriteSuspended == `TRUE) begin
$display("Error: Program Command during Write Suspend");
$display("FLASH: Error: Program Command during Write Suspend");
CmdValid <= `FALSE;
end
else begin
737,7 → 737,7
// ERASE BLOCK COMMAND --
`EraseBlockCmd : begin // Single Block Erase
if ((WriteSuspended == `TRUE) || (EraseSuspended == `TRUE)) begin
$display("Attempted to erase block while suspended");
$display("FLASH: Attempted to erase block while suspended");
CmdValid <= `FALSE;
end
else begin
781,7 → 781,7
else if (Cmd [`Cmd] == `SuspendCmd) begin
if (ReadyBusy == `Ready) begin
ReadMode <= `rdARRAY;
$display("Algorithm finished; nothing to suspend");
$display("FLASH: Algorithm finished; nothing to suspend");
end
else begin
ReadMode <= `rdCSR;
791,7 → 791,7
end
else begin
CmdValid <= `FALSE;
$display("Warning:Illegal Command (%h)", Cmd [`Cmd]); // Added displaying command code,--- RU 9/10/99
$display("FLASH: Warning:Illegal Command (%h)", Cmd [`Cmd]); // Added displaying command code,--- RU 9/10/99
end
end //default
endcase
818,7 → 818,7
BlockUsed = LoopCntr;
end
if (BlockUsed == -1)
$display("Error: Invalid Command Address");
$display("FLASH: Error: Invalid Command Address");
else
Cmd [`OpBlock] = BlockUsed;
if (Cmd [`OpType] == `Erase ) begin
879,7 → 879,7
else begin
// Do ERASE to OpBlock
if ((BlocksType[Algorithm[`OpBlock]] == `LockBlock) && !InternalBoot_WE) begin
$display("Error: Attempted to erase locked block.");
$display("FLASH: Error: Attempted to erase locked block.");
EraseError <= `TRUE;
BlockLockStatus <= `TRUE;
end
888,7 → 888,7
LoopCntr <= BlocksEnd[Algorithm[`OpBlock]]; LoopCntr = LoopCntr + 1)
MainArray [LoopCntr] = 'hFFFF;
BlocksEraseCount[Algorithm[`OpBlock]] = BlocksEraseCount[Algorithm[`OpBlock]] + 1;
$display("Block %d Erase Count: %d",Algorithm[`OpBlock],BlocksEraseCount[Algorithm[`OpBlock]]);
$display("FLASH: Block %d Erase Count: %d",Algorithm[`OpBlock],BlocksEraseCount[Algorithm[`OpBlock]]);
end
end
end
900,7 → 900,7
end
else begin
if ((BlocksType[Algorithm[`OpBlock]] == `LockBlock) && !InternalBoot_WE) begin
$display("Error: Attempted to program locked boot block.");
$display("FLASH: Error: Attempted to program locked boot block.");
ProgramError <= `TRUE;
BlockLockStatus <= `TRUE;
end
933,7 → 933,7
always @(addr) begin
if ($time != 0) begin
if ((curr_addr_time + TAVAV) > $time & !ceb) //Read/Write Cycle Time --- Added "& !ceb" RU 9/9/99 9pm
$display("[",$time,"] Timing Violation: Read/Write Cycle Time (TAVAV), Last addr change: %d",curr_addr_time) ;
$display("FLASH: [",$time,"] Timing Violation: Read/Write Cycle Time (TAVAV), Last addr change: %d",curr_addr_time) ;
curr_addr_time = $time ;
end
end
1017,7 → 1017,7
if ((rpb != `VIH) || (vcc < 2500)) begin // Low Vcc protection
Reset <= `TRUE ;
if (!((vcc >= 2500) || StartUpFlag))
$display ("Low Vcc: Chip Resetting") ;
$display ("FLASH: Low Vcc: Chip Resetting") ;
end
else
// Coming out of reset takes time
1035,7 → 1035,7
if (vcc == 0 && SaveOnPowerdown)
StoreToFile;
if (vcc < 2700)
$display("Vcc is below minimum operating specs");
$display("FLASH: Vcc is below minimum operating specs");
else if ((vcc >= 2700) && (vcc <= 3600) && (`VccLevels & `Vcc2700)) begin
//$display ("Vcc is in operating range for 2.7 volt mode") ; // Commented out RU 9/11/99
/*
1070,7 → 1070,7
end
end
else
$display ("Vcc is out of operating range") ;
$display ("FLASH: Vcc is out of operating range") ;
end //$time
end
 
1092,7 → 1092,7
Program_Time_Word = `AC_ProgramTime_Word_27_27;
end
else begin
$display("Invalid Vcc level at Vpp change");
$display("FLASH: Invalid Vcc level at Vpp change");
VppErrFlag = `TRUE;
end
end
1103,7 → 1103,7
Program_Time_Word = `AC_ProgramTime_Word_27_12;
end
else begin
$display("Invalid Vcc level at Vpp change");
$display("FLASH: Invalid Vcc level at Vpp change");
VppErrFlag = `TRUE;
end
end
1144,11 → 1144,11
// pulse chk
if (Internal_WE) begin
if ((($time - curr_Internal_WE_time) < TWHWL) && (TWHWL > 0 )) begin
$display("[",$time,"] Timing Violation: Internal Write Enable Insufficient High Time") ;
$display("FLASH: [",$time,"] Timing Violation: Internal Write Enable Insufficient High Time") ;
end
end
else if ((($time - curr_Internal_WE_time) < TWLWH) && (TWLWH > 0 ))
$display("[",$time,"] Timing Violation: Internal Write Enable Insufficient Low Time") ;
$display("FLASH: [",$time,"] Timing Violation: Internal Write Enable Insufficient Low Time") ;
curr_Internal_WE_time = $time ;
// timing_chk - addr
last_dq_time = $time - curr_dq_time;
1156,11 → 1156,11
last_addr_time = $time - curr_addr_time;
if (Internal_WE == 0) begin
if ((last_addr_time < TAVWH) && (last_addr_time > 0))
$display("[",$time,"] Timing Violation: Address setup time during write, Last Event %d",last_addr_time) ;
$display("FLASH: [",$time,"] Timing Violation: Address setup time during write, Last Event %d",last_addr_time) ;
if ((last_rpb_time < TPHWL) && (last_rpb_time > 0))
$display("[",$time,"] Timing Violation: Writing while coming out of powerdown, Last Event %d",last_rpb_time) ;
$display("FLASH: [",$time,"] Timing Violation: Writing while coming out of powerdown, Last Event %d",last_rpb_time) ;
if ((last_dq_time < TDVWH) && (last_dq_time > 0))
$display("[",$time,"] Timing Violation: Data setup time during write, Last Event %d",last_dq_time) ;
$display("FLASH: [",$time,"] Timing Violation: Data setup time during write, Last Event %d",last_dq_time) ;
end
end
end
1169,7 → 1169,7
last_Internal_WE_time = $time - curr_Internal_WE_time;
if (($time > 0) && !Internal_WE) begin //timing chk
if ((last_Internal_WE_time < TWHAX) && (last_Internal_WE_time > 0))
$display("[",$time,"] Timing Violation:Address hold time after write, Last Event %d",last_Internal_WE_time) ;
$display("FLASH: [",$time,"] Timing Violation:Address hold time after write, Last Event %d",last_Internal_WE_time) ;
end
end
 
1184,7 → 1184,7
last_Internal_WE_time = $time - curr_Internal_WE_time;
if (($time > 0) && !Internal_WE) begin
if ((last_Internal_WE_time < TWHDX) && (last_Internal_WE_time > 0))
$display("[",$time,"] Timing Violation:Data hold time after write, Last Event %d",last_Internal_WE_time) ;
$display("FLASH: [",$time,"] Timing Violation:Data hold time after write, Last Event %d",last_Internal_WE_time) ;
end
end
 
/trunk/bench/verilog/test_lib.v
38,10 → 38,10
 
// CVS Log
//
// $Id: test_lib.v,v 1.1 2001-07-29 07:34:40 rudi Exp $
// $Id: test_lib.v,v 1.2 2001-09-02 02:29:43 rudi Exp $
//
// $Date: 2001-07-29 07:34:40 $
// $Revision: 1.1 $
// $Date: 2001-09-02 02:29:43 $
// $Revision: 1.2 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
48,6 → 48,12
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.1 2001/07/29 07:34:40 rudi
//
//
// 1) Changed Directory Structure
// 2) Fixed several minor bugs
//
// Revision 1.1.1.1 2001/05/13 09:36:38 rudi
// Created Directory Structure
//
94,12 → 100,16
task susp_res;
begin
 
#1;
susp_req = 1;
while(!suspended) @(posedge clk);
#1;
susp_req = 0;
repeat(20) @(posedge clk);
#1;
resume_req = 1;
while(suspended) @(posedge clk);
#1;
resume_req = 0;
repeat(1) @(posedge clk);
 
160,7 → 170,7
*/
 
always @(wd_cnt)
if(wd_cnt>5000)
if(wd_cnt>6000)
begin
$display("\n\n*************************************\n");
$display("ERROR: Watch Dog Counter Expired\n");
189,10 → 199,11
task mc_reset;
 
begin
repeat(10) @(posedge clk);
rst = 0;
repeat(10) @(posedge clk);
rst = 1;
repeat(10) @(posedge clk);
repeat(20) @(posedge clk);
end
endtask
 

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