Subversion Repositories raggedstone

/trunk/linuxdriver/Kbuild File deleted

/trunk/linuxdriver/pci_driver_7seg.c File deleted

/trunk/linuxdriver/userland/send_to_fpga File deleted \ No newline at end of file

trunk/linuxdriver/userland/send_to_fpga Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/linuxdriver/userland/send_to_fpga.c =================================================================== --- trunk/linuxdriver/userland/send_to_fpga.c (revision 9) +++ trunk/linuxdriver/userland/send_to_fpga.c (nonexistent) @@ -1,59 +0,0 @@ -/* - Interface Program for the Linux Driver for Enterpoint's Raggedstone1 FPGA PCI Board - This demo driver allows access to the Board's 7segment displays. - - License: GPL - See file "GPL" for details - -*/ - -#include -#include /* open */ -#include /* exit */ -#include /* ioctl */ -#include - -#define MAJOR_NUM 100 -#define IOCTL_SETDPY _IOR(MAJOR_NUM, 0, short int) -#define DEVICE_NAME "/dev/fpga" - - -int ioctl_setdpy(int file_desc, short int data) -{ - int ret_val; - - ret_val = ioctl(file_desc, IOCTL_SETDPY, data); - - if (ret_val < 0) - { - printf ("ioctl_set_msg failed:%d\n", ret_val); - exit(-1); - } - return(0); -} - -int main(int argc, char ** argv) -{ - int file_desc, ret_val; - char *msg = "Message passed by ioctl\n"; - short int val = 0x7733; - - file_desc = open(DEVICE_NAME, 0); - if (file_desc < 0) - { - printf ("Can't open device file: %s\n", DEVICE_NAME); - exit(-1); - } - - if(argc >= 2 ) - { -// sscanf(argv[1], "0x%x", &val); - val = atoi(argv[1]); -// val = htons(val); - } - else - val = htons(val); - ioctl_setdpy(file_desc, val); - close(file_desc); - exit(0); -} Index: trunk/linuxdriver/userland/Makefile =================================================================== --- trunk/linuxdriver/userland/Makefile (revision 9) +++ trunk/linuxdriver/userland/Makefile (nonexistent) @@ -1,8 +0,0 @@ -build: - cc send_to_fpga.c -o send_to_fpga - -clean: - -rm -f send_to_fpga - -install: - install send_to_fpga /usr/local/bin/ Index: trunk/linuxdriver/Makefile =================================================================== --- trunk/linuxdriver/Makefile (revision 9) +++ trunk/linuxdriver/Makefile (nonexistent) @@ -1,20 +0,0 @@ -ifneq ($(KERNELRELEASE),) -include Kbuild -else -# Normal Makefile -KERNELDIR := /lib/modules/`uname -r`/build - -modules:: - $(MAKE) -C $(KERNELDIR) M=`pwd` $@ - -clean: - $(MAKE) -C $(KERNELDIR) M=`pwd` $@ - -rm -f Module.symvers - -endif - -install: - -rmmod mod_pci_7seg - sleep 1 - insmod ./mod_pci_7seg.ko - -mknod /dev/fpga c 100 0 Index: trunk/pci_7seg.ucf =================================================================== --- trunk/pci_7seg.ucf (revision 9) +++ trunk/pci_7seg.ucf (nonexistent) @@ -1,68 +0,0 @@ -NET "DISP_LED<0>" LOC = "AB20" | IOSTANDARD = LVCMOS33 ; -NET "DISP_LED<1>" LOC = "AA20" | IOSTANDARD = LVCMOS33 ; -NET "DISP_LED<2>" LOC = "V18" | IOSTANDARD = LVCMOS33 ; -NET "DISP_LED<3>" LOC = "Y17" | IOSTANDARD = LVCMOS33 ; -NET "DISP_LED<4>" LOC = "AB18" | IOSTANDARD = LVCMOS33 ; -NET "DISP_LED<5>" LOC = "AA18" | IOSTANDARD = LVCMOS33 ; -NET "DISP_LED<6>" LOC = "W18" | IOSTANDARD = LVCMOS33 ; -NET "DISP_SEL<0>" LOC = "AA17" | IOSTANDARD = LVCMOS33 ; -NET "DISP_SEL<1>" LOC = "U17" | IOSTANDARD = LVCMOS33 ; -NET "DISP_SEL<2>" LOC = "U16" | IOSTANDARD = LVCMOS33 ; -NET "DISP_SEL<3>" LOC = "U14" | IOSTANDARD = LVCMOS33 ; -NET "LED_ACCESS" LOC = "AB5" | IOSTANDARD = LVCMOS33 ; -NET "LED_INIT" LOC = "AA5" | IOSTANDARD = LVCMOS33 ; -NET "PCI_AD<0>" LOC = "A5" | IOSTANDARD = PCI33_3 ; -NET "PCI_AD<10>" LOC = "E9" | IOSTANDARD = PCI33_3 ; -NET "PCI_AD<11>" LOC = "F11" | IOSTANDARD = PCI33_3 ; -NET "PCI_AD<12>" LOC = "E10" | IOSTANDARD = PCI33_3 ; -NET "PCI_AD<13>" LOC = "A8" | IOSTANDARD = PCI33_3 ; -NET "PCI_AD<14>" LOC = "B9" | IOSTANDARD = PCI33_3 ; -NET "PCI_AD<15>" LOC = "B10" | IOSTANDARD = PCI33_3 ; -NET "PCI_AD<16>" LOC = "F17" | IOSTANDARD = PCI33_3 ; -NET "PCI_AD<17>" LOC = "F16" | IOSTANDARD = PCI33_3 ; -NET "PCI_AD<18>" LOC = "A14" | IOSTANDARD = PCI33_3 ; -NET "PCI_AD<19>" LOC = "B14" | IOSTANDARD = PCI33_3 ; -NET "PCI_AD<1>" LOC = "B5" | IOSTANDARD = PCI33_3 ; -NET "PCI_AD<20>" LOC = "B15" | IOSTANDARD = PCI33_3 ; -NET "PCI_AD<21>" LOC = "A15" | IOSTANDARD = PCI33_3 ; -NET "PCI_AD<22>" LOC = "F12" | IOSTANDARD = PCI33_3 ; -NET "PCI_AD<23>" LOC = "F13" | IOSTANDARD = PCI33_3 ; -NET "PCI_AD<24>" LOC = "D15" | IOSTANDARD = PCI33_3 ; -NET "PCI_AD<25>" LOC = "E15" | IOSTANDARD = PCI33_3 ; -NET "PCI_AD<26>" LOC = "D17" | IOSTANDARD = PCI33_3 ; -NET "PCI_AD<27>" LOC = "C17" | IOSTANDARD = PCI33_3 ; -NET "PCI_AD<28>" LOC = "B17" | IOSTANDARD = PCI33_3 ; -NET "PCI_AD<29>" LOC = "E17" | IOSTANDARD = PCI33_3 ; -NET "PCI_AD<2>" LOC = "E6" | IOSTANDARD = PCI33_3 ; -NET "PCI_AD<30>" LOC = "A18" | IOSTANDARD = PCI33_3 ; -NET "PCI_AD<31>" LOC = "B18" | IOSTANDARD = PCI33_3 ; -NET "PCI_AD<3>" LOC = "D6" | IOSTANDARD = PCI33_3 ; -NET "PCI_AD<4>" LOC = "C6" | IOSTANDARD = PCI33_3 ; -NET "PCI_AD<5>" LOC = "B6" | IOSTANDARD = PCI33_3 ; -NET "PCI_AD<6>" LOC = "D7" | IOSTANDARD = PCI33_3 ; -NET "PCI_AD<7>" LOC = "E7" | IOSTANDARD = PCI33_3 ; -NET "PCI_AD<8>" LOC = "B8" | IOSTANDARD = PCI33_3 ; -NET "PCI_AD<9>" LOC = "F10" | IOSTANDARD = PCI33_3 ; -NET "PCI_CBE<0>" LOC = "F9" | IOSTANDARD = PCI33_3 ; -NET "PCI_CBE<1>" LOC = "C10" | IOSTANDARD = PCI33_3 ; -NET "PCI_CBE<2>" LOC = "D13" | IOSTANDARD = PCI33_3 ; -NET "PCI_CBE<3>" LOC = "E13" | IOSTANDARD = PCI33_3 ; -NET "PCI_CLK" LOC = "A11" | IOSTANDARD = PCI33_3 ; -NET "PCI_IDSEL" LOC = "D14" | IOSTANDARD = PCI33_3 ; -NET "PCI_nDEVSEL" LOC = "E12" | IOSTANDARD = PCI33_3 ; -NET "PCI_nFRAME" LOC = "C13" | IOSTANDARD = PCI33_3 ; -NET "PCI_nINT" LOC = "B19" | IOSTANDARD = PCI33_3 | SLEW = FAST ; -NET "PCI_nIRDY" LOC = "A13" | IOSTANDARD = PCI33_3 ; -NET "PCI_nPERR" LOC = "D12" | IOSTANDARD = PCI33_3 | SLEW = FAST ; -NET "PCI_nRES" LOC = "A19" | IOSTANDARD = PCI33_3 ; -NET "PCI_nSERR" LOC = "B12" | IOSTANDARD = PCI33_3 | SLEW = FAST ; -NET "PCI_nSTOP" LOC = "A12" | IOSTANDARD = PCI33_3 | SLEW = FAST ; -NET "PCI_nTRDY" LOC = "B13" | IOSTANDARD = PCI33_3 | SLEW = FAST ; -NET "PCI_PAR" LOC = "A9" | IOSTANDARD = PCI33_3 | SLEW = FAST ; -NET "LED_ALIVE" LOC = "AB4" | IOSTANDARD = LVCMOS33 ; -NET "mclk" LOC = "E22"; -NET "red" LOC = "E21"; -NET "grn" LOC = "F21"; -NET "blu" LOC = "F20"; -NET "hs" LOC = "F19"; -NET "vs" LOC = "G19"; Index: trunk/README =================================================================== --- trunk/README (revision 9) +++ trunk/README (nonexistent) @@ -1,46 +0,0 @@ -This logic is for the Enterpoint Spartan-3 based PCI fpga card. - -The code needs to be built with the Xilinx tools. You can -download the Xilinx tools for free from xilinx.com. It also -generates a bit of the VHDL by perl, so you need that installed -also. - -Steps to building & using this code: - -1) Install Linux (it should include perl) -2) Download and install the Xilinx WebPack for Linux - * It's about 1GB and Xilinx provides it for free - * The Xilinx tools include a settings.sh file - that you need to run to add the tools to your path -3) Run make to synthisize the image -4) program your card over jtag with XC3prog - xc3sprog pci_7seg.bit - - -This port of the OpenCores PCI core was originally done by Manuel Bessler. -http://projects.varxec.net/raggedstone1 - -If you get this core installed correctly on the Raggedstone1 card, you -can dump out the PCI config space and it should look something like this: - -root@sid:~# hexdump /proc/bus/pci/05/02.0 -0000000 10ee 0100 0102 0200 0037 0280 0000 0000 -0000010 0000 f800 0000 0000 0000 0000 0000 0000 -0000020 0000 0000 0000 0000 0000 0000 0480 1558 -0000030 0000 0000 0000 0000 0000 0000 0104 0000 -0000040 0000 0000 5671 1234 5672 1234 5673 1234 -0000050 5674 1234 5675 1234 5676 1234 5677 1234 -0000060 5678 1234 5679 1234 5680 1234 5681 1234 -0000070 5682 1234 5683 1234 5684 1234 5685 1234 -0000080 5686 1234 5687 1234 5688 1234 5689 1234 -0000090 5690 1234 5691 1234 5692 1234 5693 1234 -00000a0 5694 1234 5695 1234 5696 1234 5697 1234 -00000b0 5698 1234 5699 1234 5700 1234 5701 1234 -00000c0 5702 1234 5703 1234 5704 1234 5705 1234 -00000d0 5706 1234 5707 1234 5708 1234 5709 1234 -00000e0 5710 1234 5711 1234 5712 1234 0000 0000 -00000f0 0000 0000 0000 0000 0000 0000 0000 0000 -0000100 - --- Jeff Carr - Index: trunk/pci_7seg.xst =================================================================== --- trunk/pci_7seg.xst (revision 9) +++ trunk/pci_7seg.xst (nonexistent) @@ -1,51 +0,0 @@ -set -xsthdpdir ./xst -run --ifn pci_7seg.prj --ifmt mixed --ofn pci_7seg --ofmt NGC --p xc3s400-4-fg456 --top pci_7seg --opt_mode Speed --opt_level 1 --iuc NO --lso pci_7seg.lso --keep_hierarchy NO --glob_opt AllClockNets --rtlview Yes --read_cores YES --write_timing_constraints NO --cross_clock_analysis NO --hierarchy_separator / --bus_delimiter <> --case maintain --slice_utilization_ratio 100 --verilog2001 YES --fsm_extract YES -fsm_encoding Auto --safe_implementation No --fsm_style lut --ram_extract Yes --ram_style Auto --rom_extract Yes --rom_style Auto --mux_extract YES --decoder_extract YES --priority_extract YES --shreg_extract YES --shift_extract YES --xor_collapse YES --resource_sharing YES --mult_style auto --iobuf YES --max_fanout 500 --bufg 8 --register_duplication YES --equivalent_register_removal YES --register_balancing No --slice_packing YES --optimize_primitives NO --use_clock_enable Yes --use_sync_set Yes --use_sync_reset Yes --iob auto --slice_utilization_ratio_maxmargin 5 Index: trunk/Makefile =================================================================== --- trunk/Makefile (revision 9) +++ trunk/Makefile (nonexistent) @@ -1,81 +0,0 @@ -PWD := $(shell pwd) - -XST := $(shell which xst) - -TMP = tmp/ -$(shell mkdir tmp) - -PROJECT := pci_7seg - -all: gen_vhdl xst ngdbuild map par trace prom final - -gen_vhdl: - cd source/generate_pci32tlite/ && make - cd source/generate_pciregs/ && make - -log: - time make all &>build.log - -xst: $(PROJECT).ngc - -ngdbuild: $(PROJECT).ngc $(PROJECT).ngd - -$(PROJECT).ngc: - @# echo synclib > $(PROJECT).lso # hmm. things are different in ise 9.1 - echo work >> $(PROJECT).lso - xst -intstyle ise -ifn $(PROJECT).xst -ofn $(PROJECT).syr &> tmp/build.xst.log - #cat $(PROJECT).syr - mv $(PROJECT).syr $(TMP) - mv $(PROJECT).ngr $(PROJECT).lso $(TMP) - mv xst $(TMP) - -$(PROJECT).ngd: - ngdbuild -intstyle ise -dd "$(PWD)/_ngo" -nt timestamp -uc $(PROJECT).ucf -p xc3s400-fg456-4 $(PROJECT).ngc $(PROJECT).ngd &> tmp/build.ngdbuild.log - mv $(PROJECT).bld $(TMP) - mv _ngo $(TMP) - -map: - map -intstyle ise -p xc3s400-fg456-4 -cm area -pr b -k 4 -c 100 -o $(PROJECT)_map.ncd $(PROJECT).ngd $(PROJECT).pcf &> tmp/build.map.log - mv $(PROJECT)_map.mrp $(PROJECT)_map.ngm $(PROJECT).ngc $(TMP) - -par: - @#par -w -intstyle ise -ol std -n 4 -t 1 $(PROJECT)_map.ncd $(PROJECT).dir $(PROJECT).pcf &> tmp/build.par.log - par -w -intstyle ise -ol std -t 1 $(PROJECT)_map.ncd $(PROJECT).ncd $(PROJECT).pcf &> tmp/build.par.log - mv $(PROJECT).xpi $(PROJECT).par $(PROJECT).pad $(TMP) - mv $(PROJECT)_pad.csv $(PROJECT)_pad.txt $(TMP) - -trace: - trce -intstyle ise -e 3 -l 3 -s 4 -xml $(PROJECT) $(PROJECT).ncd -o $(PROJECT).twr $(PROJECT).pcf &> tmp/build.trce.log - #cat $(PROJECT).twr - mv $(PROJECT).twr $(TMP) - mv $(PROJECT).twx $(TMP) - mv $(PROJECT)_map.ncd $(PROJECT).ngd $(PROJECT).pcf $(TMP) - -prom: - bitgen -intstyle ise -f $(PROJECT).ut $(PROJECT).ncd &> tmp/build.bitgen.log - # cp $(PROJECT).bit ../jcarr_last.bit - #cat $(PROJECT).drc - mv $(PROJECT).drc $(TMP) - #cat $(PROJECT).bgn - mv $(PROJECT).bgn $(TMP) - -final: - -mv $(PROJECT).unroutes *.xml $(TMP) - -mv $(PROJECT)*.map $(TMP) - -mv $(PROJECT).ncd $(TMP) - -grep -A 8 -B 1 ^Selected\ Device tmp/build.xst.log - -grep -A 8 -B 1 ^Timing\ Summary tmp/build.xst.log - -grep -A 21 -B 1 ^Design\ Summary tmp/build.map.log - -burn: - xc3sprog $(PROJECT).bit - -clean: - rm -rf $(TMP) - rm -rf *.bit *.bgn *.mcs *.prm *.bld *.drc *.mcs *.ncd *.ngc *.ngd - rm -rf *.ngr *.pad *.par *.pcf *.prm *.syr *.twr *.twx *.xpi *.lso - rm -rf $(PROJECT)_map.* $(PROJECT)_pad.* - rm -rf _ngo xst - rm -rf build.log - rm -rf source/new_* - rm -rf $(PROJECT).unroutes *.xml Index: trunk/pci_7seg.bit =================================================================== --- trunk/pci_7seg.bit (revision 9) +++ trunk/pci_7seg.bit (nonexistent) @@ -1,165 +0,0 @@ - ðððð
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- \ No newline at end of file Index: trunk/source/vga_main.vhd =================================================================== --- trunk/source/vga_main.vhd (revision 9) +++ trunk/source/vga_main.vhd (nonexistent) @@ -1,103 +0,0 @@ ---------------------------------------------------------------------- --- vga_main.vhd Demo VGA configuration module. ---------------------------------------------------------------------- --- Author: Barron Barnett --- Copyright 2004 Digilent, Inc. ---------------------------------------------------------------------- --- --- This project is compatible with Xilinx ISE or Xilinx WebPack tools. --- --- Inputs: --- mclk - System Clock --- Outputs: --- hs - Horizontal Sync --- vs - Vertical Sync --- red - Red Output --- grn - Green Output --- blu - Blue Output --- --- This module creates a three line pattern on a vga display using a --- a vertical refresh rate of 60Hz. This is done by dividing the --- system clock in half and using that for the pixel clock. This in --- turn drives the vertical sync when the horizontal sync has reached --- its reset point. All data displayed is done by basic value --- comparisons. ------------------------------------------------------------------------- --- Revision History: --- 07/01/2004(BarronB): created ------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - - -entity vgaController is - Port ( mclk : in std_logic; - hs : out std_logic; - vs : out std_logic; - red : out std_logic; - grn : out std_logic; - blu : out std_logic); -end vgaController; - -architecture Behavioral of vgaController is - - - constant hpixels : std_logic_vector(9 downto 0) := "1100100000"; --Value of pixels in a horizontal line - constant vlines : std_logic_vector(9 downto 0) := "1000001001"; --Number of horizontal lines in the display - - constant hbp : std_logic_vector(9 downto 0) := "0010010000"; --Horizontal back porch - constant hfp : std_logic_vector(9 downto 0) := "1100010000"; --Horizontal front porch - constant vbp : std_logic_vector(9 downto 0) := "0000011111"; --Vertical back porch - constant vfp : std_logic_vector(9 downto 0) := "0111111111"; --Vertical front porch - - signal hc, vc : std_logic_vector(9 downto 0); --These are the Horizontal and Vertical counters - signal clkdiv : std_logic; --Clock divider - signal vidon : std_logic; --Tells whether or not its ok to display data - signal vsenable : std_logic; --Enable for the Vertical counter - -begin - --This cuts the 50Mhz clock in half - process(mclk) - begin - if(mclk = '1' and mclk'EVENT) then - clkdiv <= not clkdiv; - end if; - end process; - - --Runs the horizontal counter - process(clkdiv) - begin - if(clkdiv = '1' and clkdiv'EVENT) then - if hc = hpixels then --If the counter has reached the end of pixel count - hc <= "0000000000"; --reset the counter - vsenable <= '1'; --Enable the vertical counter to increment - else - hc <= hc + 1; --Increment the horizontal counter - vsenable <= '0'; --Leave the vsenable off - end if; - end if; - end process; - - hs <= '1' when hc(9 downto 7) = "000" else '0'; --Horizontal Sync Pulse - - process(clkdiv) - begin - if(clkdiv = '1' and clkdiv'EVENT and vsenable = '1') then --Increment when enabled - if vc = vlines then --Reset when the number of lines is reached - vc <= "0000000000"; - else vc <= vc + 1; --Increment the vertical counter - end if; - end if; - end process; - - vs <= '1' when vc(9 downto 1) = "000000000" else '0'; --Vertical Sync Pulse - - red <= '1' when (hc = "1010101100" and vidon ='1') else '0'; --Red pixel on at a specific horizontal count - grn <= '1' when (hc = "0100000100" and vidon ='1') else '0'; --Green pixel on at a specific horizontal count - blu <= '1' when (vc = "0100100001" and vidon ='1') else '0'; --Blue pixel on at a specific vertical count - - vidon <= '1' when (((hc < hfp) and (hc > hbp)) or ((vc < vfp) and (vc > vbp))) else '0'; --Enable video out when within the porches - -end Behavioral; Index: trunk/source/wb_7seg.v =================================================================== --- trunk/source/wb_7seg.v (revision 9) +++ trunk/source/wb_7seg.v (nonexistent) @@ -1,87 +0,0 @@ -module wb_7seg_new (clk_i, nrst_i, wb_adr_i, wb_dat_o, wb_dat_i, wb_sel_i, wb_we_i, - wb_stb_i, wb_cyc_i, wb_ack_o, wb_err_o, wb_int_o, DISP_SEL, DISP_LED); - - input clk_i; - input nrst_i; - input [24:1] wb_adr_i; - output [15:0] wb_dat_o; - input [15:0] wb_dat_i; - input [1:0] wb_sel_i; - input wb_we_i; - input wb_stb_i; - input wb_cyc_i; - output wb_ack_o; - output wb_err_o; - output wb_int_o; - output reg [3:0] DISP_SEL; - output reg [6:0] DISP_LED; - - reg [15:0] data_reg; - reg [6:0] disp_cnt; - reg [3:0] disp_data; - wire [6:0] disp_data_led; - reg [3:0] disp_pos; - - always @(posedge clk_i or negedge nrst_i) - begin - if (nrst_i == 0) - data_reg <= 16'hABCD; - else - if (wb_stb_i && wb_we_i) - data_reg <= wb_dat_i; - end - - assign wb_ack_o = wb_stb_i; - assign wb_err_o = 1'b0; - assign wb_int_o = 1'b0; - assign wb_dat_o = data_reg; - - always @(posedge clk_i or negedge nrst_i) - begin - if (nrst_i == 0) - disp_cnt <= 7'b0000000; - else - disp_cnt <= disp_cnt + 1; - end - - always @(posedge clk_i or negedge nrst_i) - begin - if (nrst_i == 0) - disp_pos <= 4'b0010; - else - if (disp_cnt == 7'b1111111) - disp_pos <= {DISP_SEL[2] , DISP_SEL[1] , DISP_SEL[0] , DISP_SEL[3]}; - end - - always @(posedge clk_i or negedge nrst_i) - begin - if (nrst_i == 0) - disp_data <= 4'b0000; - else - case (DISP_SEL) - 4'b1000: disp_data <= data_reg[3:0]; - 4'b0100: disp_data <= data_reg[7:4]; - 4'b0010: disp_data <= data_reg[11:8]; - 4'b0001: disp_data <= data_reg[15:12]; - endcase - end - - disp_dec u0 (disp_data, disp_data_led); - - always @(posedge clk_i or negedge nrst_i) - begin - if (nrst_i == 0) - DISP_LED <= 7'b0000000; - else - DISP_LED <= disp_data_led; - end - - always @(posedge clk_i or negedge nrst_i) - begin - if (nrst_i == 0) - DISP_SEL <= 0; - else - DISP_SEL <= disp_pos; - end - -endmodule Index: trunk/source/top_pci_7seg.vhd =================================================================== --- trunk/source/top_pci_7seg.vhd (revision 9) +++ trunk/source/top_pci_7seg.vhd (nonexistent) @@ -1,259 +0,0 @@ ---+-------------------------------------------------------------------------------------------------+ ---| | ---| File: top.vhd | ---| | ---| Components: pci32lite.vhd | ---| pciwbsequ.vhd | ---| pcidmux.vhd | ---| pciregs.vhd | ---| pcipargen.vhd | ---| -- Libs -- | ---| ona.vhd | ---| | ---| Description: RS1 PCI Demo : (TOP) Main file. | ---| | ---| | ---| | ---+-------------------------------------------------------------------------------------------------+ ---| | ---| Revision history : | ---| Date Version Author Description | ---| | ---| | ---| To do: | ---| | ---+-------------------------------------------------------------------------------------------------+ - - ---+-----------------------------------------------------------------------------+ ---| LIBRARIES | ---+-----------------------------------------------------------------------------+ - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; -use ieee.std_logic_unsigned.all; - ---+-----------------------------------------------------------------------------+ ---| ENTITY | ---+-----------------------------------------------------------------------------+ - -entity pci_7seg is -port ( - - -- General - PCI_CLK : in std_logic; - PCI_nRES : in std_logic; - - -- PCI target 32bits - PCI_AD : inout std_logic_vector(31 downto 0); - PCI_CBE : in std_logic_vector(3 downto 0); - PCI_PAR : out std_logic; - PCI_nFRAME : in std_logic; - PCI_nIRDY : in std_logic; - PCI_nTRDY : out std_logic; - PCI_nDEVSEL : out std_logic; - PCI_nSTOP : out std_logic; - PCI_IDSEL : in std_logic; - PCI_nPERR : out std_logic; - PCI_nSERR : out std_logic; - PCI_nINT : out std_logic; - - -- 7seg - DISP_SEL : inout std_logic_vector(3 downto 0); - DISP_LED : out std_logic_vector(6 downto 0); - - -- debug signals - LED_INIT : out std_logic; - LED_ACCESS : out std_logic; - LED_ALIVE : out std_logic; - - -- vga signals - hs : out std_logic; - vs : out std_logic; - red, grn, blu : out std_logic; - mclk : in std_logic - -); -end pci_7seg; - - ---+-----------------------------------------------------------------------------+ ---| ARCHITECTURE | ---+-----------------------------------------------------------------------------+ - -architecture pci_7seg_arch of pci_7seg is - - ---+-----------------------------------------------------------------------------+ ---| COMPONENTS | ---+-----------------------------------------------------------------------------+ - -component pci32tlite -port ( - - -- General - clk33 : in std_logic; - nrst : in std_logic; - - -- PCI target 32bits - ad : inout std_logic_vector(31 downto 0); - cbe : in std_logic_vector(3 downto 0); - par : out std_logic; - frame : in std_logic; - irdy : in std_logic; - trdy : out std_logic; - devsel : out std_logic; - stop : out std_logic; - idsel : in std_logic; - perr : out std_logic; - serr : out std_logic; - intb : out std_logic; - - -- Master whisbone - wb_adr_o : out std_logic_vector(24 downto 1); - wb_dat_i : in std_logic_vector(15 downto 0); - wb_dat_o : out std_logic_vector(15 downto 0); - wb_sel_o : out std_logic_vector(1 downto 0); - wb_we_o : out std_logic; - wb_stb_o : out std_logic; - wb_cyc_o : out std_logic; - wb_ack_i : in std_logic; - wb_err_i : in std_logic; - wb_int_i : in std_logic; - - -- debug signals - debug_init : out std_logic; - debug_access : out std_logic - - ); -end component; - - -component wb_7seg_new -port ( - - -- General - clk_i : in std_logic; - nrst_i : in std_logic; - - -- Master whisbone - wb_adr_i : in std_logic_vector(24 downto 1); - wb_dat_o : out std_logic_vector(15 downto 0); - wb_dat_i : in std_logic_vector(15 downto 0); - wb_sel_i : in std_logic_vector(1 downto 0); - wb_we_i : in std_logic; - wb_stb_i : in std_logic; - wb_cyc_i : in std_logic; - wb_ack_o : out std_logic; - wb_err_o : out std_logic; - wb_int_o : out std_logic; - - -- 7seg - DISP_SEL : inout std_logic_vector(3 downto 0); - DISP_LED : out std_logic_vector(6 downto 0) - - ); -end component; - - -component vgaController is - Port ( mclk : in std_logic; - hs : out std_logic; - vs : out std_logic; - red : out std_logic; - grn : out std_logic; - blu : out std_logic); -end component; - - ---+-----------------------------------------------------------------------------+ ---| CONSTANTS | ---+-----------------------------------------------------------------------------+ ---+-----------------------------------------------------------------------------+ ---| SIGNALS | ---+-----------------------------------------------------------------------------+ - - signal wb_adr : std_logic_vector(24 downto 1); - signal wb_dat_out : std_logic_vector(15 downto 0); - signal wb_dat_in : std_logic_vector(15 downto 0); - signal wb_sel : std_logic_vector(1 downto 0); - signal wb_we : std_logic; - signal wb_stb : std_logic; - signal wb_cyc : std_logic; - signal wb_ack : std_logic; - signal wb_err : std_logic; - signal wb_int : std_logic; - - -begin - - LED_ALIVE <= '1'; ---+-------------------------------------------------------------------------+ ---| Component instances | ---+-------------------------------------------------------------------------+ - - vga1: vgaController port map (mclk => mclk, - hs => hs, - vs => vs, - red => red, - grn => grn, - blu => blu); - ---+-----------------------------------------+ ---| PCI Target | ---+-----------------------------------------+ - -u_pci: component pci32tlite -port map( - clk33 => PCI_CLK, - nrst => PCI_nRES, - ad => PCI_AD, - cbe => PCI_CBE, - par => PCI_PAR, - frame => PCI_nFRAME, - irdy => PCI_nIRDY, - trdy => PCI_nTRDY, - devsel => PCI_nDEVSEL, - stop => PCI_nSTOP, - idsel => PCI_IDSEL, - perr => PCI_nPERR, - serr => PCI_nSERR, - intb => PCI_nINT, - wb_adr_o => wb_adr, - wb_dat_i => wb_dat_out, - wb_dat_o => wb_dat_in, - wb_sel_o => wb_sel, - wb_we_o => wb_we, - wb_stb_o => wb_stb, - wb_cyc_o => wb_cyc, - wb_ack_i => wb_ack, - wb_err_i => wb_err, - wb_int_i => wb_int, - debug_init => LED_INIT, - debug_access => LED_ACCESS - ); - ---+-----------------------------------------+ ---| WB-7seg | ---+-----------------------------------------+ - -u_wb: component wb_7seg_new -port map( - clk_i => PCI_CLK, - nrst_i => PCI_nRES, - wb_adr_i => wb_adr, - wb_dat_o => wb_dat_out, - wb_dat_i => wb_dat_in, - wb_sel_i => wb_sel, - wb_we_i => wb_we, - wb_stb_i => wb_stb, - wb_cyc_i => wb_cyc, - wb_ack_o => wb_ack, - wb_err_o => wb_err, - wb_int_o => wb_int, - DISP_SEL => DISP_SEL, - DISP_LED => DISP_LED -); - -end pci_7seg_arch; Index: trunk/source/generate_pciregs/Makefile =================================================================== --- trunk/source/generate_pciregs/Makefile (revision 9) +++ trunk/source/generate_pciregs/Makefile (nonexistent) @@ -1,4 +0,0 @@ -all: - ./gen_pciregs.pl > new_pciregs.vhd - unix2dos new_pciregs.vhd - cp new_pciregs.vhd .. Index: trunk/source/generate_pciregs/gen_pciregs.pl =================================================================== --- trunk/source/generate_pciregs/gen_pciregs.pl (revision 9) +++ trunk/source/generate_pciregs/gen_pciregs.pl (nonexistent) @@ -1,44 +0,0 @@ -#!/usr/bin/perl - -my $TOTAL = 42; -my $START = 0x11; - -%h2b = (0 => "0000", 1 => "0001", 2 => "0010", 3 => "0011", -4 => "0100", 5 => "0101", 6 => "0110", 7 => "0111", -8 => "1000", 9 => "1001", a => "1010", b => "1011", -c => "1100", d => "1101", e => "1110", f => "1111", -); - - -system ("cat pciregs.vhd.part1"); - -foreach $i ( 1 .. $TOTAL ) { - my $end = ";"; - $end = "" if $i eq $TOTAL; - print "\t\tjcarr$i" . "ID : std_logic_vector(31 downto 0)$end\n"; -} - -system ("cat pciregs.vhd.part2"); - -foreach $i ( 1 .. $TOTAL ) { - my $end = ";"; - # $end = "" if $i eq $TOTAL; - print "\tconstant JCARR$i" . "IDr : std_logic_vector(31 downto 0) := jcarr$i" . "ID$end\n"; -} - -system ("cat pciregs.vhd.part3"); - -foreach $i ( 1 .. $TOTAL ) { - my $binary, $hex; - $hex = sprintf("%03X", $START); - ($binary = $hex) =~ s/(.)/$h2b{lc $1}/g; - my $out = substr $binary, -6; - print "\t\t when b\"$out\" =>\n"; - my $end = ";"; - # $end = "" if $i eq $TOTAL; - print "\t\t\t\t dataout <= JCARR$i" . "IDr$end\n"; - ++$START; -} - -system ("cat pciregs.vhd.part4"); -

trunk/source/generate_pciregs/gen_pciregs.pl Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/source/generate_pciregs/pciregs.vhd.part1 =================================================================== --- trunk/source/generate_pciregs/pciregs.vhd.part1 (revision 9) +++ trunk/source/generate_pciregs/pciregs.vhd.part1 (nonexistent) @@ -1,189 +0,0 @@ ---+-------------------------------------------------------------------------------------------------+ ---| | ---| File: pciregs.vhd | ---| | ---| Project: pci32tlite_oc | ---| | ---| Description: Registros PCI | ---| BAR0 is used externally by decoder. | ---| | ---| +-----------------------------------------------------------------------+ | ---| | PCI CONFIGURATION SPACE REGISTERS | | ---| +-----------------------------------------------------------------------+ | ---| | ---| +-------------------------------------------------------------------+ | ---| | REGISTER | adr(7..2) | offset | Byte Enable | Size | | ---| +-------------------------------------------------------------------+ | ---| | VENDORID | 000000 (r) | 00 | 0/1 | 2 | | ---| +-------------------------------------------------------------------+ | ---| | DERVICEID | 000000 (r) | 02 | 2/3 | 2 | | ---| +-------------------------------------------------------------------+ | ---| | CMD | 000001 (r/w) | 04 | 0/1 | 2 | | ---| +-------------------------------------------------------------------+ | ---| | ST | 000001 (r/w*)| 06 | 2/3 | 2 | | ---| +-------------------------------------------------------------------+ | ---| | REVISIONID | 000010 (r) | 08 | 0 | 1 | | ---| +-------------------------------------------------------------------+ | ---| | CLASSCODE | 000010 (r) | 09 | 1/2/3 | 3 | | ---| +-------------------------------------------------------------------+ | ---| | HEADERTYPE | 000011 (r) | 0E | 2 | 1 | | ---| +-------------------------------------------------------------------+ | ---| | BAR0 | 000100 (r/w) | 10 | 0/1/2/3 | 4 | | ---| +-------------------------------------------------------------------+ | ---| | SUBSYSTEMID | 001011 (r) | 2C | 0/1 | 2 | | ---| +-------------------------------------------------------------------+ | ---| | SUBSYSTEMVID | 001011 (r) | 2E | 0/1 | 2 | | ---| +-------------------------------------------------------------------+ | ---| | INTLINE | 001111 (r/w) | 3C | 0 | 1 | | ---| +-------------------------------------------------------------------+ | ---| | INTPIN | 001111 (r) | 3D | 1 | 1 | | ---| +-------------------------------------------------------------------+ | ---| (w*) Reseteable | ---| | ---| +-----------------------------------------------+ | ---| | VENDORID (r) Vendor ID register | | ---| +-----------------------------------------------+-----------------------+ | ---| | Identifies manufacturer of device. | | ---| | VENDORIDr : vendorID (generic) | | ---| +-----------------------------------------------------------------------+ | ---| | ---| +-----------------------------------------------+ | ---| | DEVICEID (r) Device ID register | | ---| +-----------------------------------------------+-----------------------+ | ---| | Identifies the device. | | ---| | DEVICEIDr : deviceID (generic) | | ---| +-----------------------------------------------------------------------+ | ---| | ---| +-----------------------------------------------+ | ---| | CMD (r/w) CoMmanD register | | ---| +-----------------------------------------------+----------------------------+ | ---| | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SERRENb| (15-8) | ---| +----------------------------------------------------------------------------+ | ---| | 0 | PERRENb| 0 | 0 | 0 | 0 |MEMSPACEENb| 0 | (7-0) | ---| +----------------------------------------------------------------------------+ | ---| | SERRENb : System ERRor ENable (1 = Enabled) | | ---| | PERRENb : Parity ERRor ENable (1 = Enabled) | | ---| | MEMSPACEENb : MEMmory SPACE ENable (1 = Enabled) | | ---| +-----------------------------------------------------------------------+ | ---| | ---| +-----------------------------------------------+ | ---| | ST (r/w*) STatus register | | ---| +-----------------------------------------------+-------------------------+ | ---| | PERRDTb | SERRSIb| -- | -- |TABORTSIb| DEVSELTIMb(1..0)| -- | (15-8) | ---| +-------------------------------------------------------------------------+ | ---| | -- | -- | -- | -- | -- | -- | -- | -- | (7-0) | ---| +-------------------------------------------------------------------------+ | ---| | PERRDTb : Parity ERRor DeTected | | ---| | SERRSIb : System ERRor SIgnaled | | ---| | TABORTSIb : Target ABORT SIgnaled | | ---| +-----------------------------------------------------------------------+ | ---| | ---| +-----------------------------------------------+ | ---| | REVISIONID (r) Revision ID register | | ---| +-----------------------------------------------+-----------------------+ | ---| | Identifies a device revision. | | ---| +-----------------------------------------------------------------------+ | ---| +-----------------------------------------------+ | ---| | CLASSCODE (r) CLASS CODE register | | ---| +-----------------------------------------------+-----------------------+ | ---| | Identifies the generic funtion of the device. | | ---| +-----------------------------------------------------------------------+ | ---| +-----------------------------------------------+ | ---| | HEADERTYPE (r) Header Type register | | ---| +-----------------------------------------------+-----------------------+ | ---| | Identifies the layout of the second part of the predefined header. | | ---| +-----------------------------------------------------------------------+ | ---| | ---| +-----------------------------------------------+ | ---| | BAR0 (r/w) Base AddRess 0 register | | ---| +-----------------------------------------------+-----------------------+ | ---| | BAR032MBb(6..0) | -- | (31-24) | ---| +-----------------------------------------------------------------------+ | ---| | BAR032MBb : Base Address 32MBytes decode space (7 bits) | | ---| +-----------------------------------------------------------------------+ | ---| | ---| +-----------------------------------------------+ | ---| | SUBSYSTEMVID (r) SUBSYSTEM Vendor ID register | | ---| +-----------------------------------------------+-----------------------+ | ---| | Identifies vendor of add-in board or subsystem. | | ---| | SUBSYSTEMVIDr : subsystemvID (generic) | | ---| +-----------------------------------------------------------------------+ | ---| | ---| +-----------------------------------------------+ | ---| | SUBSYSTEMID (r) SUBSYSTEM ID register | | ---| +-----------------------------------------------+-----------------------+ | ---| | Vendor specific. | | ---| | SUBSYTEMIDr : subsytemID (generic) | | ---| +-----------------------------------------------------------------------+ | ---| | ---| +-----------------------------------------------+ | ---| | INTLINE (r/w) INTerrupt LINE register | | ---| +-----------------------------------------------+-----------------------+ | ---| | INTLINEr(7..0) | (7..0) | ---| +-----------------------------------------------------------------------+ | ---| | Interrupt Line routing information | | ---| +-----------------------------------------------------------------------+ | ---| | ---| +-----------------------------------------------+ | ---| | INTPIN (r) INTerrupt PIN register | | ---| +-----------------------------------------------+-----------------------+ | ---| | Tells which interrupt pin the device uses: 01=INTA | | ---| +-----------------------------------------------------------------------+ | ---| | ---+-------------------------------------------------------------------------------------------------+ ---| | ---| Revision history : | ---| Date Version Author Description | ---| 2005-05-13 R00A00 PAU First alfa revision (eng) | ---| | ---| To do: | ---| | ---+-------------------------------------------------------------------------------------------------+ ---+-----------------------------------------------------------------+ ---| | ---| Copyright (C) 2005 Peio Azkarate, peio@opencores.org | ---| | ---| This source file may be used and distributed without | ---| restriction provided that this copyright statement is not | ---| removed from the file and that any derivative work contains | ---| the original copyright notice and the associated disclaimer. | ---| | ---| This source file is free software; you can redistribute it | ---| and/or modify it under the terms of the GNU Lesser General | ---| Public License as published by the Free Software Foundation; | ---| either version 2.1 of the License, or (at your option) any | ---| later version. | ---| | ---| This source is distributed in the hope that it will be | ---| useful, but WITHOUT ANY WARRANTY; without even the implied | ---| warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR | ---| PURPOSE. See the GNU Lesser General Public License for more | ---| details. | ---| | ---| You should have received a copy of the GNU Lesser General | ---| Public License along with this source; if not, download it | ---| from http://www.opencores.org/lgpl.shtml | ---| | ---+-----------------------------------------------------------------+ - - ---+-----------------------------------------------------------------------------+ ---| LIBRARIES | ---+-----------------------------------------------------------------------------+ - -library ieee; -use ieee.std_logic_1164.all; - - ---+-----------------------------------------------------------------------------+ ---| ENTITY | ---+-----------------------------------------------------------------------------+ - -entity pciregs is -generic ( - - vendorID : std_logic_vector(15 downto 0); - deviceID : std_logic_vector(15 downto 0); - revisionID : std_logic_vector(7 downto 0); - subsystemID : std_logic_vector(15 downto 0); - subsystemvID : std_logic_vector(15 downto 0); Index: trunk/source/generate_pciregs/pciregs.vhd.part2 =================================================================== --- trunk/source/generate_pciregs/pciregs.vhd.part2 (revision 9) +++ trunk/source/generate_pciregs/pciregs.vhd.part2 (nonexistent) @@ -1,46 +0,0 @@ - -); -port ( - - -- General - clk_i : in std_logic; - nrst_i : in std_logic; - -- - adr_i : in std_logic_vector(5 downto 0); - cbe_i : in std_logic_vector(3 downto 0); - dat_i : in std_logic_vector(31 downto 0); - dat_o : out std_logic_vector(31 downto 0); - -- - wrcfg_i : in std_logic; - rdcfg_i : in std_logic; - perr_i : in std_logic; - serr_i : in std_logic; - tabort_i : in std_logic; - -- - bar0_o : out std_logic_vector(31 downto 25); - perrEN_o : out std_logic; - serrEN_o : out std_logic; - memEN_o : out std_logic - -); -end pciregs; - - -architecture rtl of pciregs is - - ---+-----------------------------------------------------------------------------+ ---| COMPONENTS | ---+-----------------------------------------------------------------------------+ ---+-----------------------------------------------------------------------------+ ---| CONSTANTS | ---+-----------------------------------------------------------------------------+ - - constant CLASSCODEr : std_logic_vector(23 downto 0) := X"028000"; -- Bridge-OtherBridgeDevice - constant REVISIONIDr : std_logic_vector(7 downto 0) := revisionID; -- PR00=80,PR1=81... - constant HEADERTYPEr : std_logic_vector(7 downto 0) := X"00"; - constant DEVSELTIMb : std_logic_vector(1 downto 0) := b"01"; -- DEVSEL TIMing (bits) medium speed - constant VENDORIDr : std_logic_vector(15 downto 0) := vendorID; - constant DEVICEIDr : std_logic_vector(15 downto 0) := deviceID; - constant SUBSYSTEMIDr : std_logic_vector(15 downto 0) := subsystemID; - constant SUBSYSTEMVIDr : std_logic_vector(15 downto 0) := subsystemvID; Index: trunk/source/generate_pciregs/pciregs.vhd.part3 =================================================================== --- trunk/source/generate_pciregs/pciregs.vhd.part3 (revision 9) +++ trunk/source/generate_pciregs/pciregs.vhd.part3 (nonexistent) @@ -1,245 +0,0 @@ - constant INTPINr : std_logic_vector(7 downto 0) := X"01"; -- INTA# - - ---+-----------------------------------------------------------------------------+ ---| SIGNALS | ---+-----------------------------------------------------------------------------+ - - signal dataout : std_logic_vector(31 downto 0); - signal tabortPFS : std_logic; - signal serrPFS : std_logic; - signal perrPFS : std_logic; - signal adrSTCMD : std_logic; - signal adrBAR0 : std_logic; - signal adrINT : std_logic; - signal we0CMD : std_logic; - signal we1CMD : std_logic; - signal we3ST : std_logic; - signal we3BAR0 : std_logic; - signal we0INT : std_logic; - signal we1INT : std_logic; - signal st11SEN : std_logic; - signal st11REN : std_logic; - signal st14SEN : std_logic; - signal st14REN : std_logic; - signal st15SEN : std_logic; - signal st15REN : std_logic; - - - --+---------------------------------------------------------+ - --| CONFIGURATION SPACE REGISTERS | - --+---------------------------------------------------------+ - - -- INTERRUPT LINE register - signal INTLINEr : std_logic_vector(7 downto 0); - -- COMMAND register bits - signal MEMSPACEENb : std_logic; -- Memory SPACE ENable (bit) - signal PERRENb : std_logic; -- Parity ERRor ENable (bit) - signal SERRENb : std_logic; -- SERR ENable (bit) - -- STATUS register bits - --signal DEVSELTIMb : std_logic_vector(1 downto 0); -- DEVSEL TIMing (bits) - signal TABORTSIb : std_logic; -- TarGet ABORT SIgnaling (bit) - signal SERRSIb : std_logic; -- System ERRor SIgnaling (bit) - signal PERRDTb : std_logic; -- Parity ERRor DeTected (bit) - -- BAR0 register bits - signal BAR032MBb : std_logic_vector(6 downto 0); -- BAR0 32MBytes Space (bits) - - -component pfs -port ( - clk : in std_logic; - a : in std_logic; - y : out std_logic -); - -end component; - -begin - - --+-------------------------------------------------------------------------+ - --| Component instances | - --+-------------------------------------------------------------------------+ - - u1: pfs port map ( clk => clk_i, a => tabort_i, y => tabortPFS ); - u2: pfs port map ( clk => clk_i, a => serr_i, y => serrPFS ); - u3: pfs port map ( clk => clk_i, a => perr_i, y => perrPFS ); - - - --+-------------------------------------------------------------------------+ - --| Registers Address Decoder | - --+-------------------------------------------------------------------------+ - - adrSTCMD <= '1' when ( adr_i(5 downto 0) = b"000001" ) else '0'; - adrBAR0 <= '1' when ( adr_i(5 downto 0) = b"000100" ) else '0'; - adrINT <= '1' when ( adr_i(5 downto 0) = b"001111" ) else '0'; - - - --+-------------------------------------------------------------------------+ - --| WRITE ENABLE REGISTERS | - --+-------------------------------------------------------------------------+ - - --+-----------------------------------------+ - --| Write Enable Registers | - --+-----------------------------------------+ - - we0CMD <= adrSTCMD and wrcfg_i and (not cbe_i(0)); - we1CMD <= adrSTCMD and wrcfg_i and (not cbe_i(1)); - --we2ST <= adrSTCMD and wrcfg_i and (not cbe_i(2)); - we3ST <= adrSTCMD and wrcfg_i and (not cbe_i(3)); - --we2BAR0 <= adrBAR0 and wrcfg_i and (not cbe_i(2)); - we3BAR0 <= adrBAR0 and wrcfg_i and (not cbe_i(3)); - we0INT <= adrINT and wrcfg_i and (not cbe_i(0)); - --we1INT <= adrINT and wrcfg_i and (not cbe_i(1)); - - --+-----------------------------------------+ - --| Set Enable & Reset Enable bits | - --+-----------------------------------------+ - st11SEN <= tabortPFS; - st11REN <= we3ST and dat_i(27); - st14SEN <= serrPFS; - st14REN <= we3ST and dat_i(30); - st15SEN <= perrPFS; - st15REN <= we3ST and dat_i(31); - - - --+-------------------------------------------------------------------------+ - --| WRITE REGISTERS | - --+-------------------------------------------------------------------------+ - - --+---------------------------------------------------------+ - --| COMMAND REGISTER Write | - --+---------------------------------------------------------+ - - REGCMDWR: process( clk_i, nrst_i, we0CMD, we1CMD, dat_i ) - begin - - if( nrst_i = '0' ) then - MEMSPACEENb <= '0'; - PERRENb <= '0'; - SERRENb <= '0'; - elsif( rising_edge( clk_i ) ) then - - -- Byte 0 - if( we0CMD = '1' ) then - MEMSPACEENb <= dat_i(1); - PERRENb <= dat_i(6); - end if; - - -- Byte 1 - if( we1CMD = '1' ) then - SERRENb <= dat_i(8); - end if; - - end if; - - end process REGCMDWR; - - - --+---------------------------------------------------------+ - --| STATUS REGISTER WRITE (Reset only) | - --+---------------------------------------------------------+ - - REGSTWR: process( clk_i, nrst_i, st11SEN, st11REN, st14SEN, st14REN, st15SEN, st15REN ) - begin - - if( nrst_i = '0' ) then - TABORTSIb <= '0'; - SERRSIb <= '0'; - PERRDTb <= '0'; - elsif( rising_edge( clk_i ) ) then - - -- TarGet ABORT SIgnaling bit - if( st11SEN = '1' ) then - TABORTSIb <= '1'; - elsif ( st11REN = '1' ) then - TABORTSIb <= '0'; - end if; - - -- System ERRor SIgnaling bit - if( st14SEN = '1' ) then - SERRSIb <= '1'; - elsif ( st14REN = '1' ) then - SERRSIb <= '0'; - end if; - - -- Parity ERRor DEtected bit - if( st15SEN = '1' ) then - PERRDTb <= '1'; - elsif ( st15REN = '1' ) then - PERRDTb <= '0'; - end if; - - end if; - - end process REGSTWR; - - - --+---------------------------------------------------------+ - --| INTERRUPT REGISTER Write | - --+---------------------------------------------------------+ - - REGINTWR: process( clk_i, nrst_i, we0INT, dat_i ) - begin - - if( nrst_i = '0' ) then - INTLINEr <= ( others => '0' ); - elsif( rising_edge( clk_i ) ) then - - -- Byte 0 - if( we0INT = '1' ) then - INTLINEr <= dat_i(7 downto 0); - end if; - - - end if; - - end process REGINTWR; - - - --+---------------------------------------------------------+ - --| BAR0 32MBytes address space (bits 31-25) | - --+---------------------------------------------------------+ - - REGBAR0WR: process( clk_i, nrst_i, we3BAR0, dat_i ) - begin - - if( nrst_i = '0' ) then - BAR032MBb <= ( others => '1' ); - elsif( rising_edge( clk_i ) ) then - - -- Byte 3 - if( we3BAR0 = '1' ) then - BAR032MBb <= dat_i(31 downto 25); - end if; - - end if; - - end process REGBAR0WR; - - - --+-------------------------------------------------------------------------+ - --| Registers MUX (READ) | - --+-------------------------------------------------------------------------+ ---+-------------------------------------------------------------------------------------------------+ - - RRMUX: process( adr_i, PERRDTb, SERRSIb, TABORTSIb, SERRENb, PERRENb, MEMSPACEENb, BAR032MBb, - INTLINEr, rdcfg_i ) - begin - - if ( rdcfg_i = '1' ) then - - case adr_i is - - when b"000000" => - dataout <= DEVICEIDr & VENDORIDr; - when b"000001" => - dataout <= PERRDTb & SERRSIb & b"00" & TABORTSIb & DEVSELTIMb & b"000000000" & - b"0000000" & SERRENb & b"0" & PERRENb & b"0000" & MEMSPACEENb & b"0"; - when b"000010" => - dataout <= CLASSCODEr & REVISIONIDr; - when b"000100" => - dataout <= BAR032MBb & b"0" & b"00000000" & b"00000000" & b"00000000"; - when b"001011" => - dataout <= SUBSYSTEMIDr & SUBSYSTEMVIDr; - when b"001111" => - dataout <= b"0000000000000000" & INTPINr & INTLINEr; Index: trunk/source/generate_pciregs/pciregs.vhd.part4 =================================================================== --- trunk/source/generate_pciregs/pciregs.vhd.part4 (revision 9) +++ trunk/source/generate_pciregs/pciregs.vhd.part4 (nonexistent) @@ -1,27 +0,0 @@ - when others => - dataout <= ( others => '0' ); - - end case; - - else - - dataout <= ( others => '0' ); - - end if; - - end process RRMUX; - - dat_o <= dataout; - - - --+-------------------------------------------------------------------------+ - --| BAR0 & COMMAND REGS bits outputs | - --+-------------------------------------------------------------------------+ - - bar0_o <= BAR032MBb; - perrEN_o <= PERRENb; - serrEN_o <= SERRENb; - memEN_o <= MEMSPACEENb; - - -end rtl; Index: trunk/source/generate_pciregs/new_pciregs.vhd =================================================================== --- trunk/source/generate_pciregs/new_pciregs.vhd (revision 9) +++ trunk/source/generate_pciregs/new_pciregs.vhd (nonexistent) @@ -1,675 +0,0 @@ ---+-------------------------------------------------------------------------------------------------+ ---| | ---| File: pciregs.vhd | ---| | ---| Project: pci32tlite_oc | ---| | ---| Description: Registros PCI | ---| BAR0 is used externally by decoder. | ---| | ---| +-----------------------------------------------------------------------+ | ---| | PCI CONFIGURATION SPACE REGISTERS | | ---| +-----------------------------------------------------------------------+ | ---| | ---| +-------------------------------------------------------------------+ | ---| | REGISTER | adr(7..2) | offset | Byte Enable | Size | | ---| +-------------------------------------------------------------------+ | ---| | VENDORID | 000000 (r) | 00 | 0/1 | 2 | | ---| +-------------------------------------------------------------------+ | ---| | DERVICEID | 000000 (r) | 02 | 2/3 | 2 | | ---| +-------------------------------------------------------------------+ | ---| | CMD | 000001 (r/w) | 04 | 0/1 | 2 | | ---| +-------------------------------------------------------------------+ | ---| | ST | 000001 (r/w*)| 06 | 2/3 | 2 | | ---| +-------------------------------------------------------------------+ | ---| | REVISIONID | 000010 (r) | 08 | 0 | 1 | | ---| +-------------------------------------------------------------------+ | ---| | CLASSCODE | 000010 (r) | 09 | 1/2/3 | 3 | | ---| +-------------------------------------------------------------------+ | ---| | HEADERTYPE | 000011 (r) | 0E | 2 | 1 | | ---| +-------------------------------------------------------------------+ | ---| | BAR0 | 000100 (r/w) | 10 | 0/1/2/3 | 4 | | ---| +-------------------------------------------------------------------+ | ---| | SUBSYSTEMID | 001011 (r) | 2C | 0/1 | 2 | | ---| +-------------------------------------------------------------------+ | ---| | SUBSYSTEMVID | 001011 (r) | 2E | 0/1 | 2 | | ---| +-------------------------------------------------------------------+ | ---| | INTLINE | 001111 (r/w) | 3C | 0 | 1 | | ---| +-------------------------------------------------------------------+ | ---| | INTPIN | 001111 (r) | 3D | 1 | 1 | | ---| +-------------------------------------------------------------------+ | ---| (w*) Reseteable | ---| | ---| +-----------------------------------------------+ | ---| | VENDORID (r) Vendor ID register | | ---| +-----------------------------------------------+-----------------------+ | ---| | Identifies manufacturer of device. | | ---| | VENDORIDr : vendorID (generic) | | ---| +-----------------------------------------------------------------------+ | ---| | ---| +-----------------------------------------------+ | ---| | DEVICEID (r) Device ID register | | ---| +-----------------------------------------------+-----------------------+ | ---| | Identifies the device. | | ---| | DEVICEIDr : deviceID (generic) | | ---| +-----------------------------------------------------------------------+ | ---| | ---| +-----------------------------------------------+ | ---| | CMD (r/w) CoMmanD register | | ---| +-----------------------------------------------+----------------------------+ | ---| | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SERRENb| (15-8) | ---| +----------------------------------------------------------------------------+ | ---| | 0 | PERRENb| 0 | 0 | 0 | 0 |MEMSPACEENb| 0 | (7-0) | ---| +----------------------------------------------------------------------------+ | ---| | SERRENb : System ERRor ENable (1 = Enabled) | | ---| | PERRENb : Parity ERRor ENable (1 = Enabled) | | ---| | MEMSPACEENb : MEMmory SPACE ENable (1 = Enabled) | | ---| +-----------------------------------------------------------------------+ | ---| | ---| +-----------------------------------------------+ | ---| | ST (r/w*) STatus register | | ---| +-----------------------------------------------+-------------------------+ | ---| | PERRDTb | SERRSIb| -- | -- |TABORTSIb| DEVSELTIMb(1..0)| -- | (15-8) | ---| +-------------------------------------------------------------------------+ | ---| | -- | -- | -- | -- | -- | -- | -- | -- | (7-0) | ---| +-------------------------------------------------------------------------+ | ---| | PERRDTb : Parity ERRor DeTected | | ---| | SERRSIb : System ERRor SIgnaled | | ---| | TABORTSIb : Target ABORT SIgnaled | | ---| +-----------------------------------------------------------------------+ | ---| | ---| +-----------------------------------------------+ | ---| | REVISIONID (r) Revision ID register | | ---| +-----------------------------------------------+-----------------------+ | ---| | Identifies a device revision. | | ---| +-----------------------------------------------------------------------+ | ---| +-----------------------------------------------+ | ---| | CLASSCODE (r) CLASS CODE register | | ---| +-----------------------------------------------+-----------------------+ | ---| | Identifies the generic funtion of the device. | | ---| +-----------------------------------------------------------------------+ | ---| +-----------------------------------------------+ | ---| | HEADERTYPE (r) Header Type register | | ---| +-----------------------------------------------+-----------------------+ | ---| | Identifies the layout of the second part of the predefined header. | | ---| +-----------------------------------------------------------------------+ | ---| | ---| +-----------------------------------------------+ | ---| | BAR0 (r/w) Base AddRess 0 register | | ---| +-----------------------------------------------+-----------------------+ | ---| | BAR032MBb(6..0) | -- | (31-24) | ---| +-----------------------------------------------------------------------+ | ---| | BAR032MBb : Base Address 32MBytes decode space (7 bits) | | ---| +-----------------------------------------------------------------------+ | ---| | ---| +-----------------------------------------------+ | ---| | SUBSYSTEMVID (r) SUBSYSTEM Vendor ID register | | ---| +-----------------------------------------------+-----------------------+ | ---| | Identifies vendor of add-in board or subsystem. | | ---| | SUBSYSTEMVIDr : subsystemvID (generic) | | ---| +-----------------------------------------------------------------------+ | ---| | ---| +-----------------------------------------------+ | ---| | SUBSYSTEMID (r) SUBSYSTEM ID register | | ---| +-----------------------------------------------+-----------------------+ | ---| | Vendor specific. | | ---| | SUBSYTEMIDr : subsytemID (generic) | | ---| +-----------------------------------------------------------------------+ | ---| | ---| +-----------------------------------------------+ | ---| | INTLINE (r/w) INTerrupt LINE register | | ---| +-----------------------------------------------+-----------------------+ | ---| | INTLINEr(7..0) | (7..0) | ---| +-----------------------------------------------------------------------+ | ---| | Interrupt Line routing information | | ---| +-----------------------------------------------------------------------+ | ---| | ---| +-----------------------------------------------+ | ---| | INTPIN (r) INTerrupt PIN register | | ---| +-----------------------------------------------+-----------------------+ | ---| | Tells which interrupt pin the device uses: 01=INTA | | ---| +-----------------------------------------------------------------------+ | ---| | ---+-------------------------------------------------------------------------------------------------+ ---| | ---| Revision history : | ---| Date Version Author Description | ---| 2005-05-13 R00A00 PAU First alfa revision (eng) | ---| | ---| To do: | ---| | ---+-------------------------------------------------------------------------------------------------+ ---+-----------------------------------------------------------------+ ---| | ---| Copyright (C) 2005 Peio Azkarate, peio@opencores.org | ---| | ---| This source file may be used and distributed without | ---| restriction provided that this copyright statement is not | ---| removed from the file and that any derivative work contains | ---| the original copyright notice and the associated disclaimer. | ---| | ---| This source file is free software; you can redistribute it | ---| and/or modify it under the terms of the GNU Lesser General | ---| Public License as published by the Free Software Foundation; | ---| either version 2.1 of the License, or (at your option) any | ---| later version. | ---| | ---| This source is distributed in the hope that it will be | ---| useful, but WITHOUT ANY WARRANTY; without even the implied | ---| warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR | ---| PURPOSE. See the GNU Lesser General Public License for more | ---| details. | ---| | ---| You should have received a copy of the GNU Lesser General | ---| Public License along with this source; if not, download it | ---| from http://www.opencores.org/lgpl.shtml | ---| | ---+-----------------------------------------------------------------+ - - ---+-----------------------------------------------------------------------------+ ---| LIBRARIES | ---+-----------------------------------------------------------------------------+ - -library ieee; -use ieee.std_logic_1164.all; - - ---+-----------------------------------------------------------------------------+ ---| ENTITY | ---+-----------------------------------------------------------------------------+ - -entity pciregs is -generic ( - - vendorID : std_logic_vector(15 downto 0); - deviceID : std_logic_vector(15 downto 0); - revisionID : std_logic_vector(7 downto 0); - subsystemID : std_logic_vector(15 downto 0); - subsystemvID : std_logic_vector(15 downto 0); - jcarr1ID : std_logic_vector(31 downto 0); - jcarr2ID : std_logic_vector(31 downto 0); - jcarr3ID : std_logic_vector(31 downto 0); - jcarr4ID : std_logic_vector(31 downto 0); - jcarr5ID : std_logic_vector(31 downto 0); - jcarr6ID : std_logic_vector(31 downto 0); - jcarr7ID : std_logic_vector(31 downto 0); - jcarr8ID : std_logic_vector(31 downto 0); - jcarr9ID : std_logic_vector(31 downto 0); - jcarr10ID : std_logic_vector(31 downto 0); - jcarr11ID : std_logic_vector(31 downto 0); - jcarr12ID : std_logic_vector(31 downto 0); - jcarr13ID : std_logic_vector(31 downto 0); - jcarr14ID : std_logic_vector(31 downto 0); - jcarr15ID : std_logic_vector(31 downto 0); - jcarr16ID : std_logic_vector(31 downto 0); - jcarr17ID : std_logic_vector(31 downto 0); - jcarr18ID : std_logic_vector(31 downto 0); - jcarr19ID : std_logic_vector(31 downto 0); - jcarr20ID : std_logic_vector(31 downto 0); - jcarr21ID : std_logic_vector(31 downto 0); - jcarr22ID : std_logic_vector(31 downto 0); - jcarr23ID : std_logic_vector(31 downto 0); - jcarr24ID : std_logic_vector(31 downto 0); - jcarr25ID : std_logic_vector(31 downto 0); - jcarr26ID : std_logic_vector(31 downto 0); - jcarr27ID : std_logic_vector(31 downto 0); - jcarr28ID : std_logic_vector(31 downto 0); - jcarr29ID : std_logic_vector(31 downto 0); - jcarr30ID : std_logic_vector(31 downto 0); - jcarr31ID : std_logic_vector(31 downto 0); - jcarr32ID : std_logic_vector(31 downto 0); - jcarr33ID : std_logic_vector(31 downto 0); - jcarr34ID : std_logic_vector(31 downto 0); - jcarr35ID : std_logic_vector(31 downto 0); - jcarr36ID : std_logic_vector(31 downto 0); - jcarr37ID : std_logic_vector(31 downto 0); - jcarr38ID : std_logic_vector(31 downto 0); - jcarr39ID : std_logic_vector(31 downto 0); - jcarr40ID : std_logic_vector(31 downto 0); - jcarr41ID : std_logic_vector(31 downto 0); - jcarr42ID : std_logic_vector(31 downto 0) - -); -port ( - - -- General - clk_i : in std_logic; - nrst_i : in std_logic; - -- - adr_i : in std_logic_vector(5 downto 0); - cbe_i : in std_logic_vector(3 downto 0); - dat_i : in std_logic_vector(31 downto 0); - dat_o : out std_logic_vector(31 downto 0); - -- - wrcfg_i : in std_logic; - rdcfg_i : in std_logic; - perr_i : in std_logic; - serr_i : in std_logic; - tabort_i : in std_logic; - -- - bar0_o : out std_logic_vector(31 downto 25); - perrEN_o : out std_logic; - serrEN_o : out std_logic; - memEN_o : out std_logic - -); -end pciregs; - - -architecture rtl of pciregs is - - ---+-----------------------------------------------------------------------------+ ---| COMPONENTS | ---+-----------------------------------------------------------------------------+ ---+-----------------------------------------------------------------------------+ ---| CONSTANTS | ---+-----------------------------------------------------------------------------+ - - constant CLASSCODEr : std_logic_vector(23 downto 0) := X"028000"; -- Bridge-OtherBridgeDevice - constant REVISIONIDr : std_logic_vector(7 downto 0) := revisionID; -- PR00=80,PR1=81... - constant HEADERTYPEr : std_logic_vector(7 downto 0) := X"00"; - constant DEVSELTIMb : std_logic_vector(1 downto 0) := b"01"; -- DEVSEL TIMing (bits) medium speed - constant VENDORIDr : std_logic_vector(15 downto 0) := vendorID; - constant DEVICEIDr : std_logic_vector(15 downto 0) := deviceID; - constant SUBSYSTEMIDr : std_logic_vector(15 downto 0) := subsystemID; - constant SUBSYSTEMVIDr : std_logic_vector(15 downto 0) := subsystemvID; - constant JCARR1IDr : std_logic_vector(31 downto 0) := jcarr1ID; - constant JCARR2IDr : std_logic_vector(31 downto 0) := jcarr2ID; - constant JCARR3IDr : std_logic_vector(31 downto 0) := jcarr3ID; - constant JCARR4IDr : std_logic_vector(31 downto 0) := jcarr4ID; - constant JCARR5IDr : std_logic_vector(31 downto 0) := jcarr5ID; - constant JCARR6IDr : std_logic_vector(31 downto 0) := jcarr6ID; - constant JCARR7IDr : std_logic_vector(31 downto 0) := jcarr7ID; - constant JCARR8IDr : std_logic_vector(31 downto 0) := jcarr8ID; - constant JCARR9IDr : std_logic_vector(31 downto 0) := jcarr9ID; - constant JCARR10IDr : std_logic_vector(31 downto 0) := jcarr10ID; - constant JCARR11IDr : std_logic_vector(31 downto 0) := jcarr11ID; - constant JCARR12IDr : std_logic_vector(31 downto 0) := jcarr12ID; - constant JCARR13IDr : std_logic_vector(31 downto 0) := jcarr13ID; - constant JCARR14IDr : std_logic_vector(31 downto 0) := jcarr14ID; - constant JCARR15IDr : std_logic_vector(31 downto 0) := jcarr15ID; - constant JCARR16IDr : std_logic_vector(31 downto 0) := jcarr16ID; - constant JCARR17IDr : std_logic_vector(31 downto 0) := jcarr17ID; - constant JCARR18IDr : std_logic_vector(31 downto 0) := jcarr18ID; - constant JCARR19IDr : std_logic_vector(31 downto 0) := jcarr19ID; - constant JCARR20IDr : std_logic_vector(31 downto 0) := jcarr20ID; - constant JCARR21IDr : std_logic_vector(31 downto 0) := jcarr21ID; - constant JCARR22IDr : std_logic_vector(31 downto 0) := jcarr22ID; - constant JCARR23IDr : std_logic_vector(31 downto 0) := jcarr23ID; - constant JCARR24IDr : std_logic_vector(31 downto 0) := jcarr24ID; - constant JCARR25IDr : std_logic_vector(31 downto 0) := jcarr25ID; - constant JCARR26IDr : std_logic_vector(31 downto 0) := jcarr26ID; - constant JCARR27IDr : std_logic_vector(31 downto 0) := jcarr27ID; - constant JCARR28IDr : std_logic_vector(31 downto 0) := jcarr28ID; - constant JCARR29IDr : std_logic_vector(31 downto 0) := jcarr29ID; - constant JCARR30IDr : std_logic_vector(31 downto 0) := jcarr30ID; - constant JCARR31IDr : std_logic_vector(31 downto 0) := jcarr31ID; - constant JCARR32IDr : std_logic_vector(31 downto 0) := jcarr32ID; - constant JCARR33IDr : std_logic_vector(31 downto 0) := jcarr33ID; - constant JCARR34IDr : std_logic_vector(31 downto 0) := jcarr34ID; - constant JCARR35IDr : std_logic_vector(31 downto 0) := jcarr35ID; - constant JCARR36IDr : std_logic_vector(31 downto 0) := jcarr36ID; - constant JCARR37IDr : std_logic_vector(31 downto 0) := jcarr37ID; - constant JCARR38IDr : std_logic_vector(31 downto 0) := jcarr38ID; - constant JCARR39IDr : std_logic_vector(31 downto 0) := jcarr39ID; - constant JCARR40IDr : std_logic_vector(31 downto 0) := jcarr40ID; - constant JCARR41IDr : std_logic_vector(31 downto 0) := jcarr41ID; - constant JCARR42IDr : std_logic_vector(31 downto 0) := jcarr42ID; - constant INTPINr : std_logic_vector(7 downto 0) := X"01"; -- INTA# - - ---+-----------------------------------------------------------------------------+ ---| SIGNALS | ---+-----------------------------------------------------------------------------+ - - signal dataout : std_logic_vector(31 downto 0); - signal tabortPFS : std_logic; - signal serrPFS : std_logic; - signal perrPFS : std_logic; - signal adrSTCMD : std_logic; - signal adrBAR0 : std_logic; - signal adrINT : std_logic; - signal we0CMD : std_logic; - signal we1CMD : std_logic; - signal we3ST : std_logic; - signal we3BAR0 : std_logic; - signal we0INT : std_logic; - signal we1INT : std_logic; - signal st11SEN : std_logic; - signal st11REN : std_logic; - signal st14SEN : std_logic; - signal st14REN : std_logic; - signal st15SEN : std_logic; - signal st15REN : std_logic; - - - --+---------------------------------------------------------+ - --| CONFIGURATION SPACE REGISTERS | - --+---------------------------------------------------------+ - - -- INTERRUPT LINE register - signal INTLINEr : std_logic_vector(7 downto 0); - -- COMMAND register bits - signal MEMSPACEENb : std_logic; -- Memory SPACE ENable (bit) - signal PERRENb : std_logic; -- Parity ERRor ENable (bit) - signal SERRENb : std_logic; -- SERR ENable (bit) - -- STATUS register bits - --signal DEVSELTIMb : std_logic_vector(1 downto 0); -- DEVSEL TIMing (bits) - signal TABORTSIb : std_logic; -- TarGet ABORT SIgnaling (bit) - signal SERRSIb : std_logic; -- System ERRor SIgnaling (bit) - signal PERRDTb : std_logic; -- Parity ERRor DeTected (bit) - -- BAR0 register bits - signal BAR032MBb : std_logic_vector(6 downto 0); -- BAR0 32MBytes Space (bits) - - -component pfs -port ( - clk : in std_logic; - a : in std_logic; - y : out std_logic -); - -end component; - -begin - - --+-------------------------------------------------------------------------+ - --| Component instances | - --+-------------------------------------------------------------------------+ - - u1: pfs port map ( clk => clk_i, a => tabort_i, y => tabortPFS ); - u2: pfs port map ( clk => clk_i, a => serr_i, y => serrPFS ); - u3: pfs port map ( clk => clk_i, a => perr_i, y => perrPFS ); - - - --+-------------------------------------------------------------------------+ - --| Registers Address Decoder | - --+-------------------------------------------------------------------------+ - - adrSTCMD <= '1' when ( adr_i(5 downto 0) = b"000001" ) else '0'; - adrBAR0 <= '1' when ( adr_i(5 downto 0) = b"000100" ) else '0'; - adrINT <= '1' when ( adr_i(5 downto 0) = b"001111" ) else '0'; - - - --+-------------------------------------------------------------------------+ - --| WRITE ENABLE REGISTERS | - --+-------------------------------------------------------------------------+ - - --+-----------------------------------------+ - --| Write Enable Registers | - --+-----------------------------------------+ - - we0CMD <= adrSTCMD and wrcfg_i and (not cbe_i(0)); - we1CMD <= adrSTCMD and wrcfg_i and (not cbe_i(1)); - --we2ST <= adrSTCMD and wrcfg_i and (not cbe_i(2)); - we3ST <= adrSTCMD and wrcfg_i and (not cbe_i(3)); - --we2BAR0 <= adrBAR0 and wrcfg_i and (not cbe_i(2)); - we3BAR0 <= adrBAR0 and wrcfg_i and (not cbe_i(3)); - we0INT <= adrINT and wrcfg_i and (not cbe_i(0)); - --we1INT <= adrINT and wrcfg_i and (not cbe_i(1)); - - --+-----------------------------------------+ - --| Set Enable & Reset Enable bits | - --+-----------------------------------------+ - st11SEN <= tabortPFS; - st11REN <= we3ST and dat_i(27); - st14SEN <= serrPFS; - st14REN <= we3ST and dat_i(30); - st15SEN <= perrPFS; - st15REN <= we3ST and dat_i(31); - - - --+-------------------------------------------------------------------------+ - --| WRITE REGISTERS | - --+-------------------------------------------------------------------------+ - - --+---------------------------------------------------------+ - --| COMMAND REGISTER Write | - --+---------------------------------------------------------+ - - REGCMDWR: process( clk_i, nrst_i, we0CMD, we1CMD, dat_i ) - begin - - if( nrst_i = '0' ) then - MEMSPACEENb <= '0'; - PERRENb <= '0'; - SERRENb <= '0'; - elsif( rising_edge( clk_i ) ) then - - -- Byte 0 - if( we0CMD = '1' ) then - MEMSPACEENb <= dat_i(1); - PERRENb <= dat_i(6); - end if; - - -- Byte 1 - if( we1CMD = '1' ) then - SERRENb <= dat_i(8); - end if; - - end if; - - end process REGCMDWR; - - - --+---------------------------------------------------------+ - --| STATUS REGISTER WRITE (Reset only) | - --+---------------------------------------------------------+ - - REGSTWR: process( clk_i, nrst_i, st11SEN, st11REN, st14SEN, st14REN, st15SEN, st15REN ) - begin - - if( nrst_i = '0' ) then - TABORTSIb <= '0'; - SERRSIb <= '0'; - PERRDTb <= '0'; - elsif( rising_edge( clk_i ) ) then - - -- TarGet ABORT SIgnaling bit - if( st11SEN = '1' ) then - TABORTSIb <= '1'; - elsif ( st11REN = '1' ) then - TABORTSIb <= '0'; - end if; - - -- System ERRor SIgnaling bit - if( st14SEN = '1' ) then - SERRSIb <= '1'; - elsif ( st14REN = '1' ) then - SERRSIb <= '0'; - end if; - - -- Parity ERRor DEtected bit - if( st15SEN = '1' ) then - PERRDTb <= '1'; - elsif ( st15REN = '1' ) then - PERRDTb <= '0'; - end if; - - end if; - - end process REGSTWR; - - - --+---------------------------------------------------------+ - --| INTERRUPT REGISTER Write | - --+---------------------------------------------------------+ - - REGINTWR: process( clk_i, nrst_i, we0INT, dat_i ) - begin - - if( nrst_i = '0' ) then - INTLINEr <= ( others => '0' ); - elsif( rising_edge( clk_i ) ) then - - -- Byte 0 - if( we0INT = '1' ) then - INTLINEr <= dat_i(7 downto 0); - end if; - - - end if; - - end process REGINTWR; - - - --+---------------------------------------------------------+ - --| BAR0 32MBytes address space (bits 31-25) | - --+---------------------------------------------------------+ - - REGBAR0WR: process( clk_i, nrst_i, we3BAR0, dat_i ) - begin - - if( nrst_i = '0' ) then - BAR032MBb <= ( others => '1' ); - elsif( rising_edge( clk_i ) ) then - - -- Byte 3 - if( we3BAR0 = '1' ) then - BAR032MBb <= dat_i(31 downto 25); - end if; - - end if; - - end process REGBAR0WR; - - - --+-------------------------------------------------------------------------+ - --| Registers MUX (READ) | - --+-------------------------------------------------------------------------+ ---+-------------------------------------------------------------------------------------------------+ - - RRMUX: process( adr_i, PERRDTb, SERRSIb, TABORTSIb, SERRENb, PERRENb, MEMSPACEENb, BAR032MBb, - INTLINEr, rdcfg_i ) - begin - - if ( rdcfg_i = '1' ) then - - case adr_i is - - when b"000000" => - dataout <= DEVICEIDr & VENDORIDr; - when b"000001" => - dataout <= PERRDTb & SERRSIb & b"00" & TABORTSIb & DEVSELTIMb & b"000000000" & - b"0000000" & SERRENb & b"0" & PERRENb & b"0000" & MEMSPACEENb & b"0"; - when b"000010" => - dataout <= CLASSCODEr & REVISIONIDr; - when b"000100" => - dataout <= BAR032MBb & b"0" & b"00000000" & b"00000000" & b"00000000"; - when b"001011" => - dataout <= SUBSYSTEMIDr & SUBSYSTEMVIDr; - when b"001111" => - dataout <= b"0000000000000000" & INTPINr & INTLINEr; - when b"010001" => - dataout <= JCARR1IDr; - when b"010010" => - dataout <= JCARR2IDr; - when b"010011" => - dataout <= JCARR3IDr; - when b"010100" => - dataout <= JCARR4IDr; - when b"010101" => - dataout <= JCARR5IDr; - when b"010110" => - dataout <= JCARR6IDr; - when b"010111" => - dataout <= JCARR7IDr; - when b"011000" => - dataout <= JCARR8IDr; - when b"011001" => - dataout <= JCARR9IDr; - when b"011010" => - dataout <= JCARR10IDr; - when b"011011" => - dataout <= JCARR11IDr; - when b"011100" => - dataout <= JCARR12IDr; - when b"011101" => - dataout <= JCARR13IDr; - when b"011110" => - dataout <= JCARR14IDr; - when b"011111" => - dataout <= JCARR15IDr; - when b"100000" => - dataout <= JCARR16IDr; - when b"100001" => - dataout <= JCARR17IDr; - when b"100010" => - dataout <= JCARR18IDr; - when b"100011" => - dataout <= JCARR19IDr; - when b"100100" => - dataout <= JCARR20IDr; - when b"100101" => - dataout <= JCARR21IDr; - when b"100110" => - dataout <= JCARR22IDr; - when b"100111" => - dataout <= JCARR23IDr; - when b"101000" => - dataout <= JCARR24IDr; - when b"101001" => - dataout <= JCARR25IDr; - when b"101010" => - dataout <= JCARR26IDr; - when b"101011" => - dataout <= JCARR27IDr; - when b"101100" => - dataout <= JCARR28IDr; - when b"101101" => - dataout <= JCARR29IDr; - when b"101110" => - dataout <= JCARR30IDr; - when b"101111" => - dataout <= JCARR31IDr; - when b"110000" => - dataout <= JCARR32IDr; - when b"110001" => - dataout <= JCARR33IDr; - when b"110010" => - dataout <= JCARR34IDr; - when b"110011" => - dataout <= JCARR35IDr; - when b"110100" => - dataout <= JCARR36IDr; - when b"110101" => - dataout <= JCARR37IDr; - when b"110110" => - dataout <= JCARR38IDr; - when b"110111" => - dataout <= JCARR39IDr; - when b"111000" => - dataout <= JCARR40IDr; - when b"111001" => - dataout <= JCARR41IDr; - when b"111010" => - dataout <= JCARR42IDr; - when others => - dataout <= ( others => '0' ); - - end case; - - else - - dataout <= ( others => '0' ); - - end if; - - end process RRMUX; - - dat_o <= dataout; - - - --+-------------------------------------------------------------------------+ - --| BAR0 & COMMAND REGS bits outputs | - --+-------------------------------------------------------------------------+ - - bar0_o <= BAR032MBb; - perrEN_o <= PERRENb; - serrEN_o <= SERRENb; - memEN_o <= MEMSPACEENb; - - -end rtl; Index: trunk/source/pciwbsequ.v =================================================================== --- trunk/source/pciwbsequ.v (revision 9) +++ trunk/source/pciwbsequ.v (nonexistent) @@ -1,295 +0,0 @@ -// Copyright (C) 2005 Peio Azkarate, peio@opencores.org -// -// This source file is free software; you can redistribute it -// and/or modify it under the terms of the GNU Lesser General -// Public License as published by the Free Software Foundation; -// either version 2.1 of the License, or (at your option) any -// later version. -// - -(* signal_encoding = "user" *) -(* safe_implementation = "yes" *) - -module pciwbsequ_new ( clk_i, nrst_i, cmd_i, cbe_i, frame_i, irdy_i, devsel_o, - trdy_o, adrcfg_i, adrmem_i, pciadrLD_o, pcidOE_o, parOE_o, wbdatLD_o, - wbrgdMX_o, wbd16MX_o, wrcfg_o, rdcfg_o, wb_sel_o, wb_we_o, wb_stb_o, - wb_cyc_o, wb_ack_i, wb_err_i, debug_init, debug_access ); - - // General - input clk_i; - input nrst_i; - // pci - // adr_i - input [3:0] cmd_i; - input [3:0] cbe_i; - input frame_i; - input irdy_i; - output devsel_o; - output trdy_o; - // control - input adrcfg_i; - input adrmem_i; - output pciadrLD_o; - output pcidOE_o; - output reg parOE_o; - output wbdatLD_o; - output wbrgdMX_o; - output wbd16MX_o; - output wrcfg_o; - output rdcfg_o; - // whisbone - output [1:0] wb_sel_o; - output wb_we_o; - inout wb_stb_o; - output wb_cyc_o; - input wb_ack_i; - input wb_err_i; - // debug signals - output reg debug_init; - output reg debug_access; - - //type PciFSM is ( PCIIDLE, B_BUSY, S_DATA1, S_DATA2, TURN_AR ); - //wire pst_pci : PciFSM; - //wire nxt_pci : PciFSM; - - // typedef enum reg [2:0] { - // RED, GREEN, BLUE, CYAN, MAGENTA, YELLOW - // } color_t; - // - // color_t my_color = GREEN; - - // parameter PCIIDLE = 2'b00; - // parameter B_BUSY = 2'b01; - // parameter S_DATA1 = 2'b10; - // parameter S_DATA2 = 2'b11; - // parameter TURN_AR = 3'b100; - - reg [2:0] pst_pci; - reg [2:0] nxt_pci; - - parameter [2:0] - PCIIDLE = 3'b000, - B_BUSY = 3'b001, - S_DATA1 = 3'b010, - S_DATA2 = 3'b011, - TURN_AR = 3'b100; - - - initial begin - pst_pci = 3'b000; - end - - initial begin - nxt_pci = 3'b000; - end - - wire sdata1; - wire sdata2; - wire idleNX; - wire sdata1NX; - wire sdata2NX; - wire turnarNX; - wire idle; - reg devselNX_n; - reg trdyNX_n; - reg devsel; - reg trdy; - wire adrpci; - wire acking; - wire rdcfg; - reg targOE; - reg pcidOE; - - // always @(nrst_i or clk_i or nxt_pci) - always @(negedge nrst_i or posedge clk_i) - begin - if( nrst_i == 0 ) - pst_pci <= PCIIDLE; - else - pst_pci <= nxt_pci; - end - - // always @(negedge nrst_i or posedge clk_i) - always @( pst_pci or frame_i or irdy_i or adrcfg_i or adrpci or acking ) - begin - devselNX_n <= 1'b1; - trdyNX_n <= 1'b1; - case (pst_pci) - PCIIDLE : - begin - if ( frame_i == 0 ) - nxt_pci <= B_BUSY; - else - nxt_pci <= PCIIDLE; - end - B_BUSY: - if ( adrpci == 0 ) - nxt_pci <= TURN_AR; - else - begin - nxt_pci <= S_DATA1; - devselNX_n <= 0; - end - S_DATA1: - if ( acking == 1 ) - begin - nxt_pci <= S_DATA2; - devselNX_n <= 0; - trdyNX_n <= 0; - end - else - begin - nxt_pci <= S_DATA1; - devselNX_n <= 0; - end - S_DATA2: - if ( frame_i == 1 && irdy_i == 0 ) - nxt_pci <= TURN_AR; - else - begin - nxt_pci <= S_DATA2; - devselNX_n <= 0; - trdyNX_n <= 0; - end - TURN_AR: - if ( frame_i == 1 ) - nxt_pci <= PCIIDLE; - else - nxt_pci <= TURN_AR; - endcase - end - - // FSM control signals - assign adrpci = adrmem_i; - - assign acking = ( - ( wb_ack_i == 1 || wb_err_i == 1 ) || - ( adrcfg_i == 1 && irdy_i == 0) - ) ? 1'b1 : 1'b0; - - // FSM derived Control signals - assign idle = ( pst_pci <= PCIIDLE ) ? 1'b1 : 1'b0; - assign sdata1 = ( pst_pci <= S_DATA1 ) ? 1'b1 : 1'b0; - assign sdata2 = ( pst_pci <= S_DATA2 ) ? 1'b1 : 1'b0; - assign idleNX = ( nxt_pci <= PCIIDLE ) ? 1'b1 : 1'b0; - assign sdata1NX = ( nxt_pci <= S_DATA1 ) ? 1'b1 : 1'b0; - assign sdata2NX = ( nxt_pci <= S_DATA2 ) ? 1'b1 : 1'b0; - assign turnarNX = ( nxt_pci <= TURN_AR ) ? 1'b1 : 1'b0; - - // PCI Data Output Enable - // always @( nrst_i or clk_i or cmd_i [0] or sdata1NX or turnarNX ) - always @(negedge nrst_i or posedge clk_i) - begin - if ( nrst_i == 0 ) - pcidOE <= 0; - else - if ( sdata1NX == 1 && cmd_i [0] == 0 ) - pcidOE <= 1; - else - if ( turnarNX == 1 ) - pcidOE <= 0; - end - - assign pcidOE_o = pcidOE; - - // PAR Output Enable - // PCI Read data phase - // PAR is valid 1 cicle after data is valid - // always @( nrst_i or clk_i or cmd_i [0] or sdata2NX or turnarNX ) - always @(negedge nrst_i or posedge clk_i) - begin - if ( nrst_i == 0 ) - parOE_o <= 0; - else - if ( ( sdata2NX == 1 || turnarNX == 1 ) && cmd_i [0] == 0 ) - parOE_o <= 1; - else - parOE_o <= 0; - end - - // Target s/t/s signals OE control - // targOE <= '1' when ( idle = '0' and adrpci = '1' ) else '0'; - // always @( nrst_i or clk_i or sdata1NX or idleNX ) - always @(negedge nrst_i or posedge clk_i) - begin - if ( nrst_i == 0 ) - targOE <= 0; - else - if ( sdata1NX == 1 ) - targOE <= 1; - else - if ( idleNX == 1 ) - targOE <= 0; - end - - // WHISBONE outs - assign wb_cyc_o = (adrmem_i == 1 && sdata1 == 1) ? 1'b1 : 1'b0; - assign wb_stb_o = (adrmem_i == 1 && sdata1 == 1 && irdy_i == 0 ) ? 1'b1 : 1'b0; - - // PCI(Little endian) to WB(Big endian) - assign wb_sel_o [1] = (! cbe_i [0]) || (! cbe_i [2]); - assign wb_sel_o [0] = (! cbe_i [1]) || (! cbe_i [3]); - - assign wb_we_o = cmd_i [0]; - - // Syncronized PCI outs - always @(negedge nrst_i or posedge clk_i) - begin - if( nrst_i == 0 ) - begin - devsel <= 1; - trdy <= 1; - end - else - begin - devsel <= devselNX_n; - trdy <= trdyNX_n; - end - end - - assign devsel_o = ( targOE == 1 ) ? devsel : 1'bZ; - assign trdy_o = ( targOE == 1 ) ? trdy : 1'bZ; - - // rd/wr Configuration Space Registers - assign wrcfg_o = ( - adrcfg_i == 1 && - cmd_i [0] == 1 && - sdata2 == 1 - ) ? 1'b1 : 1'b0; - - assign rdcfg = ( - adrcfg_i == 1 && - cmd_i [0] == 0 && - (sdata1 == 1 || sdata2 == 1) - ) ? 1'b1 : 1'b0; - - assign rdcfg_o = rdcfg; - - // LoaD enable signals - assign pciadrLD_o = ! frame_i; - assign wbdatLD_o = wb_ack_i; - - // Mux control signals - assign wbrgdMX_o = ! rdcfg; - assign wbd16MX_o = (cbe_i [3] == 0 || cbe_i [2] == 0) ? 1'b1 : 1'b0; - - // debug outs - always @(negedge nrst_i or posedge clk_i) - begin - if ( nrst_i == 0 ) - debug_init <= 0; - else - if (devsel == 0) - debug_init <= 1; - end - - always @(negedge nrst_i or posedge clk_i) - begin - if ( nrst_i == 0 ) - debug_access <= 0; - else - if (wb_stb_o == 1) - debug_access <= 1; - end - -endmodule Index: trunk/source/pfs.vhd =================================================================== --- trunk/source/pfs.vhd (revision 9) +++ trunk/source/pfs.vhd (nonexistent) @@ -1,35 +0,0 @@ ---+-----------------------------------------+ ---| pfs | ---+-----------------------------------------+ - -library ieee; -use ieee.std_logic_1164.all; - -entity pfs is -port ( - clk : in std_logic; - a : in std_logic; - y : out std_logic - -); -end pfs; - -architecture rtl of pfs is - - signal a_s : std_logic; - -begin - - SYNCP: process( clk, a ) - begin - - if ( rising_edge(clk) ) then - a_s <= a; - end if; - - end process SYNCP; - - y <= a and (not a_s); - -end rtl; - Index: trunk/source/pcipargen.v =================================================================== --- trunk/source/pcipargen.v (revision 9) +++ trunk/source/pcipargen.v (nonexistent) @@ -1,80 +0,0 @@ -// -// PCI Parity Generator. -// -// PCI Target generates PAR in the data phase of a read cycle. -// The 1's sum on AD, CBE and PAR is even. -// -// Date Version Author Description -// 2005-05-13 R00A00 PAU First alfa revision (eng) -// -// Copyright (C) 2005 Peio Azkarate, peio@opencores.org -// -// This source file is free software; you can redistribute it | -// and/or modify it under the terms of the GNU Lesser General | -// Public License as published by the Free Software Foundation; | -// either version 2.1 of the License, or (at your option) any | -// later version. | - - -module pcipargen_new (clk_i, pcidatout_i, cbe_i, parOE_i, par_o); - - input clk_i; - input [31:0] pcidatout_i; - input [3:0] cbe_i; - input parOE_i; - output par_o; - - - wire [31:0] d; - wire pardat; - wire parcbe; - wire par; - wire par_s; - - assign d = pcidatout_i; - - assign pardat = d[0] ^ d[1] ^ d[2] ^ d[3] ^ d[4] ^ d[5] ^ d[6] ^ d[7] ^ - d[8] ^ d[9] ^ d[10] ^ d[11] ^ d[12] ^ d[13] ^ d[14] ^ d[15] ^ - d[16] ^ d[17] ^ d[18] ^ d[19] ^ d[20] ^ d[21] ^ d[22] ^ d[23] ^ - d[24] ^ d[25] ^ d[26] ^ d[27] ^ d[28] ^ d[29] ^ d[30] ^ d[31]; - - assign parcbe = cbe_i[0] ^ cbe_i[1] ^ cbe_i[2] ^ cbe_i[3]; - - assign par = pardat ^ parcbe; - - // PAR - assign par_o = ( parOE_i == 1 ) ? par_s : 1'bZ; - -endmodule -/* -component sync -port ( - clk : in std_logic; - d : in std_logic; - q : out std_logic -); -end component; - -component sync2 -port ( - clk : in std_logic; - d : in std_logic; - q : out std_logic -); -end component; - -begin - - - - u1: sync2 port map ( - clk => clk_i, - d => par, - q => par_s - ); - - - - -end rtl; -*/ Index: trunk/source/pcidmux.v =================================================================== --- trunk/source/pcidmux.v (revision 9) +++ trunk/source/pcidmux.v (nonexistent) @@ -1,55 +0,0 @@ -// Copyright (C) 2005 Peio Azkarate, peio@opencores.org -// Copyright (C) 2006 Jeff Carr, jcarr@opencores.org -// -// I think what this does is handle 16 vs 32 bit pci accesses - -module pcidmux ( clk_i, nrst_i, d_io, pcidatout_o, pcidOE_i, wbdatLD_i, wbrgdMX_i, - wbd16MX_i, wb_dat_i, wb_dat_o, rg_dat_i, rg_dat_o); - - input clk_i; - input nrst_i; - - // d_io : inout std_logic_vector(31 downto 0); - inout [31:0] d_io; - output [31:0] pcidatout_o; - - input pcidOE_i; - input wbdatLD_i; - input wbrgdMX_i; - input wbd16MX_i; - - input [15:0] wb_dat_i; - output [15:0] wb_dat_o; - input [31:0] rg_dat_i; - output [31:0] rg_dat_o; - - wire [31:0] pcidatin; - wire [31:0] pcidatout; - - reg [15:0] wb_dat_is; - - // always @(negedge nrst_i or posedge clk_i or posedge wbdatLD_i or posedge wb_dat_i) - always @(negedge nrst_i or posedge clk_i) - begin - if ( nrst_i == 0 ) - wb_dat_is <= 16'b1111_1111_1111_1111; - else - if ( wbdatLD_i == 1 ) - wb_dat_is <= wb_dat_i; - end - - assign pcidatin = d_io; - assign d_io = (pcidOE_i == 1'b1 ) ? pcidatout : 32'bZ; - - assign pcidatout [31:24] = (wbrgdMX_i == 1'b1) ? wb_dat_is [7:0] : rg_dat_i [31:24]; - assign pcidatout [23:16] = (wbrgdMX_i == 1'b1) ? wb_dat_is [15:8] : rg_dat_i [23:16]; - assign pcidatout [15:8] = (wbrgdMX_i == 1'b1) ? wb_dat_is [7:0] : rg_dat_i [15:8]; - assign pcidatout [7:0] = (wbrgdMX_i == 1'b1) ? wb_dat_is [15:8] : rg_dat_i [7:0]; - - assign pcidatout_o = pcidatout; - assign rg_dat_o = pcidatin; - - assign wb_dat_o [15:8] = (wbd16MX_i == 1'b1) ? pcidatin [23:16] : pcidatin [7:0]; - assign wb_dat_o [7:0] = (wbd16MX_i == 1'b1) ? pcidatin [31:24] : pcidatin [15:8]; - -endmodule Index: trunk/source/disp_dec.v =================================================================== --- trunk/source/disp_dec.v (revision 9) +++ trunk/source/disp_dec.v (nonexistent) @@ -1,29 +0,0 @@ -module disp_dec(disp_dec_in, disp_dec_out); - input [3:0] disp_dec_in; - output reg [6:0] disp_dec_out; - - always @(disp_dec_in) - begin - case (disp_dec_in) - 4'b0000: disp_dec_out <= 7'b1000000; - 4'b0001: disp_dec_out <= 7'b1111001; - 4'b0010: disp_dec_out <= 7'b0100100; - 4'b0011: disp_dec_out <= 7'b0110000; - - 4'b0100: disp_dec_out <= 7'b0011001; - 4'b0101: disp_dec_out <= 7'b0010010; - 4'b0110: disp_dec_out <= 7'b0000010; - 4'b0111: disp_dec_out <= 7'b1111000; - - 4'b1000: disp_dec_out <= 7'b0000000; - 4'b1001: disp_dec_out <= 7'b0010000; - 4'b1010: disp_dec_out <= 7'b0001000; - 4'b1011: disp_dec_out <= 7'b0000011; - - 4'b1100: disp_dec_out <= 7'b1000110; - 4'b1101: disp_dec_out <= 7'b0100001; - 4'b1110: disp_dec_out <= 7'b0000110; - 4'b1111: disp_dec_out <= 7'b0001110; - endcase - end -endmodule Index: trunk/source/sync.v =================================================================== --- trunk/source/sync.v (revision 9) +++ trunk/source/sync.v (nonexistent) @@ -1,11 +0,0 @@ -module sync2 (clk, d, q); - input clk; - input d; - output q; - reg q; - - always @(posedge clk) - begin - q <= d; - end -endmodule Index: trunk/source/pciwbsequ.vhd =================================================================== --- trunk/source/pciwbsequ.vhd (revision 9) +++ trunk/source/pciwbsequ.vhd (nonexistent) @@ -1,382 +0,0 @@ ---+-------------------------------------------------------------------------------------------------+ ---| | ---| File: pciwbsequ.vhd | ---| | ---| Project: pci32tlite_oc | ---| | ---| Description: FSM controlling PCI to Whisbone sequence. | ---| | ---+-------------------------------------------------------------------------------------------------+ ---| | ---| Revision history : | ---| Date Version Author Description | ---| 2005-05-13 R00A00 PAU First alfa revision (eng) | ---| 2006-01-09 MS added debug signals debug_init, debug_access | | ---| | ---| To do: | ---| | ---+-------------------------------------------------------------------------------------------------+ ---+-----------------------------------------------------------------+ ---| | ---| Copyright (C) 2005 Peio Azkarate, peio@opencores.org | ---| | ---| This source file may be used and distributed without | ---| restriction provided that this copyright statement is not | ---| removed from the file and that any derivative work contains | ---| the original copyright notice and the associated disclaimer. | ---| | ---| This source file is free software; you can redistribute it | ---| and/or modify it under the terms of the GNU Lesser General | ---| Public License as published by the Free Software Foundation; | ---| either version 2.1 of the License, or (at your option) any | ---| later version. | ---| | ---| This source is distributed in the hope that it will be | ---| useful, but WITHOUT ANY WARRANTY; without even the implied | ---| warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR | ---| PURPOSE. See the GNU Lesser General Public License for more | ---| details. | ---| | ---| You should have received a copy of the GNU Lesser General | ---| Public License along with this source; if not, download it | ---| from http://www.opencores.org/lgpl.shtml | ---| | ---+-----------------------------------------------------------------+ - - ---+-----------------------------------------------------------------------------+ ---| LIBRARIES | ---+-----------------------------------------------------------------------------+ - -library ieee; -use ieee.std_logic_1164.all; - - ---+-----------------------------------------------------------------------------+ ---| ENTITY | ---+-----------------------------------------------------------------------------+ - -entity pciwbsequ is -port ( - - -- General - clk_i : in std_logic; - nrst_i : in std_logic; - -- pci - --adr_i - cmd_i : in std_logic_vector(3 downto 0); - cbe_i : in std_logic_vector(3 downto 0); - frame_i : in std_logic; - irdy_i : in std_logic; - devsel_o : out std_logic; - trdy_o : out std_logic; - -- control - adrcfg_i : in std_logic; - adrmem_i : in std_logic; - pciadrLD_o : out std_logic; - pcidOE_o : out std_logic; - parOE_o : out std_logic; - wbdatLD_o : out std_logic; - wbrgdMX_o : out std_logic; - wbd16MX_o : out std_logic; - wrcfg_o : out std_logic; - rdcfg_o : out std_logic; - -- whisbone - wb_sel_o : out std_logic_vector(1 downto 0); - wb_we_o : out std_logic; - wb_stb_o : inout std_logic; - wb_cyc_o : out std_logic; - wb_ack_i : in std_logic; - wb_err_i : in std_logic; - -- debug signals - debug_init : out std_logic; - debug_access : out std_logic -); -end pciwbsequ; - - -architecture rtl of pciwbsequ is - - ---+-----------------------------------------------------------------------------+ ---| COMPONENTS | ---+-----------------------------------------------------------------------------+ ---+-----------------------------------------------------------------------------+ ---| CONSTANTS | ---+-----------------------------------------------------------------------------+ ---+-----------------------------------------------------------------------------+ ---| SIGNALS | ---+-----------------------------------------------------------------------------+ - - type PciFSM is ( PCIIDLE, B_BUSY, S_DATA1, S_DATA2, TURN_AR ); - signal pst_pci : PciFSM; - signal nxt_pci : PciFSM; - - signal sdata1 : std_logic; - signal sdata2 : std_logic; - signal idleNX : std_logic; - signal sdata1NX : std_logic; - signal sdata2NX : std_logic; - signal turnarNX : std_logic; - signal idle : std_logic; - signal devselNX_n : std_logic; - signal trdyNX_n : std_logic; - signal devsel : std_logic; - signal trdy : std_logic; - signal adrpci : std_logic; - signal acking : std_logic; - signal rdcfg : std_logic; - signal targOE : std_logic; - signal pcidOE : std_logic; - - -begin - - --+-------------------------------------------------------------------------+ - --| PCI-Whisbone Sequencer | - --+-------------------------------------------------------------------------+ - - - --+-------------------------------------------------------------+ - --| FSM PCI-Whisbone | - --+-------------------------------------------------------------+ - - PCIFSM_CLOCKED: process( nrst_i, clk_i, nxt_pci ) - begin - - if( nrst_i = '0' ) then - pst_pci <= PCIIDLE; - elsif( rising_edge(clk_i) ) then - pst_pci <= nxt_pci; - end if; - - end process PCIFSM_CLOCKED; - - - PCIFSM_COMB: process( pst_pci, frame_i, irdy_i, adrcfg_i, adrpci, acking ) - begin - - devselNX_n <= '1'; - trdyNX_n <= '1'; - case pst_pci is - - when PCIIDLE => - if ( frame_i = '0' ) then - nxt_pci <= B_BUSY; - else - nxt_pci <= PCIIDLE; - end if; - - when B_BUSY => - if ( adrpci = '0' ) then - nxt_pci <= TURN_AR; - else - nxt_pci <= S_DATA1; - devselNX_n <= '0'; - end if; - - when S_DATA1 => - if ( acking = '1' ) then - nxt_pci <= S_DATA2; - devselNX_n <= '0'; - trdyNX_n <= '0'; - else - nxt_pci <= S_DATA1; - devselNX_n <= '0'; - end if; - - when S_DATA2 => - if ( frame_i = '1' and irdy_i = '0' ) then - nxt_pci <= TURN_AR; - else - nxt_pci <= S_DATA2; - devselNX_n <= '0'; - trdyNX_n <= '0'; - end if; - - when TURN_AR => - if ( frame_i = '1' ) then - nxt_pci <= PCIIDLE; - else - nxt_pci <= TURN_AR; - end if; - - end case; - - end process PCIFSM_COMB; - - - --+-------------------------------------------------------------+ - --| FSM control signals | - --+-------------------------------------------------------------+ - - adrpci <= adrmem_i or adrcfg_i; - acking <= '1' when ( wb_ack_i = '1' or wb_err_i = '1' ) or ( adrcfg_i = '1' and irdy_i = '0') - else '0'; - - - --+-------------------------------------------------------------+ - --| FSM derived Control signals | - --+-------------------------------------------------------------+ - idle <= '1' when ( pst_pci = PCIIDLE ) else '0'; - sdata1 <= '1' when ( pst_pci = S_DATA1 ) else '0'; - sdata2 <= '1' when ( pst_pci = S_DATA2 ) else '0'; - idleNX <= '1' when ( nxt_pci = PCIIDLE ) else '0'; - sdata1NX <= '1' when ( nxt_pci = S_DATA1 ) else '0'; - sdata2NX <= '1' when ( nxt_pci = S_DATA2 ) else '0'; - turnarNX <= '1' when ( nxt_pci = TURN_AR ) else '0'; - - - - --+-------------------------------------------------------------+ - --| PCI Data Output Enable | - --+-------------------------------------------------------------+ - - PCIDOE_P: process( nrst_i, clk_i, cmd_i(0), sdata1NX, turnarNX ) - begin - - if ( nrst_i = '0' ) then - pcidOE <= '0'; - elsif ( rising_edge(clk_i) ) then - - if ( sdata1NX = '1' and cmd_i(0) = '0' ) then - pcidOE <= '1'; - elsif ( turnarNX = '1' ) then - pcidOE <= '0'; - end if; - - end if; - - end process PCIDOE_P; - - pcidOE_o <= pcidOE; - - - --+-------------------------------------------------------------+ - --| PAR Output Enable | - --| PCI Read data phase | - --| PAR is valid 1 cicle after data is valid | - --+-------------------------------------------------------------+ - - PAROE_P: process( nrst_i, clk_i, cmd_i(0), sdata2NX, turnarNX ) - begin - - if ( nrst_i = '0' ) then - parOE_o <= '0'; - elsif ( rising_edge(clk_i) ) then - - if ( ( sdata2NX = '1' or turnarNX = '1' ) and cmd_i(0) = '0' ) then - parOE_o <= '1'; - else - parOE_o <= '0'; - end if; - - end if; - - end process PAROE_P; - - - --+-------------------------------------------------------------+ - --| Target s/t/s signals OE control | - --+-------------------------------------------------------------+ - --- targOE <= '1' when ( idle = '0' and adrpci = '1' ) else '0'; - TARGOE_P: process( nrst_i, clk_i, sdata1NX, idleNX ) - begin - - if ( nrst_i = '0' ) then - targOE <= '0'; - elsif ( rising_edge(clk_i) ) then - - if ( sdata1NX = '1' ) then - targOE <= '1'; - elsif ( idleNX = '1' ) then - targOE <= '0'; - end if; - - end if; - - end process TARGOE_P; - - - --+-------------------------------------------------------------------------+ - --| WHISBONE outs | - --+-------------------------------------------------------------------------+ - - wb_cyc_o <= '1' when ( adrmem_i = '1' and sdata1 = '1' ) else '0'; - wb_stb_o <= '1' when ( adrmem_i = '1' and sdata1 = '1' and irdy_i = '0' ) else '0'; - - -- PCI(Little endian) to WB(Big endian) - wb_sel_o(1) <= (not cbe_i(0)) or (not cbe_i(2)); - wb_sel_o(0) <= (not cbe_i(1)) or (not cbe_i(3)); - -- - wb_we_o <= cmd_i(0); - - - --+-------------------------------------------------------------------------+ - --| Syncronized PCI outs | - --+-------------------------------------------------------------------------+ - - PCISIG: process( nrst_i, clk_i, devselNX_n, trdyNX_n) - begin - - if( nrst_i = '0' ) then - devsel <= '1'; - trdy <= '1'; - elsif( rising_edge(clk_i) ) then - - devsel <= devselNX_n; - trdy <= trdyNX_n; - - end if; - - end process PCISIG; - - devsel_o <= devsel when ( targOE = '1' ) else 'Z'; - trdy_o <= trdy when ( targOE = '1' ) else 'Z'; - - - --+-------------------------------------------------------------------------+ - --| Other outs | - --+-------------------------------------------------------------------------+ - - -- rd/wr Configuration Space Registers - wrcfg_o <= '1' when ( adrcfg_i = '1' and cmd_i(0) = '1' and sdata2 = '1' ) else '0'; - rdcfg <= '1' when ( adrcfg_i = '1' and cmd_i(0) = '0' and ( sdata1 = '1' or sdata2 = '1' ) ) else '0'; - rdcfg_o <= rdcfg; - - -- LoaD enable signals - pciadrLD_o <= not frame_i; - wbdatLD_o <= wb_ack_i; - - -- Mux control signals - wbrgdMX_o <= not rdcfg; - wbd16MX_o <= '1' when ( cbe_i(3) = '0' or cbe_i(2) = '0' ) else '0'; - - --+-------------------------------------------------------------------------+ - --| debug outs | - --+-------------------------------------------------------------------------+ - - process (nrst_i, clk_i) - begin - if ( nrst_i = '0' ) then - debug_init <= '0'; - elsif clk_i'event and clk_i = '1' then - if devsel = '0' then - debug_init <= '1'; - end if; - end if; - end process; - - process (nrst_i, clk_i) - begin - if ( nrst_i = '0' ) then - debug_access <= '0'; - elsif clk_i'event and clk_i = '1' then - if wb_stb_o = '1' then - debug_access <= '1'; - end if; - end if; - end process; - -end rtl; Index: trunk/source/test.v =================================================================== --- trunk/source/test.v (revision 9) +++ trunk/source/test.v (nonexistent) @@ -1,14 +0,0 @@ -/* -`define PCIIDLE 1'h0; -`define B_BUSY 1'h1; -`define S_DATA1 1'h2; -`define S_DATA2 1'h3; -`define TURN_AR 1'h4; -*/ - -paramater PCIIDLE = 1'h0; -paramater B_BUSY = 1'h1; -paramater S_DATA1 = 1'h2; -paramater S_DATA2 = 1'h3; -paramater TURN_AR = 1'h4; - Index: trunk/source/pcipargen.vhd =================================================================== --- trunk/source/pcipargen.vhd (revision 9) +++ trunk/source/pcipargen.vhd (nonexistent) @@ -1,144 +0,0 @@ ---+-------------------------------------------------------------------------------------------------+ ---| | ---| File: pcipargen.vhd | ---| | ---| Project: pci32tlite_oc | ---| | ---| Description: PCI Parity Generator. | ---| PCI Target generates PAR in the data phase of a read cycle. The 1's sum on AD, | ---| CBE and PAR is even. | ---| | ---+-------------------------------------------------------------------------------------------------+ ---| | ---| Revision history : | ---| Date Version Author Description | ---| 2005-05-13 R00A00 PAU First alfa revision (eng) | ---| | ---| To do: | ---| | ---+-------------------------------------------------------------------------------------------------+ ---+-----------------------------------------------------------------+ ---| | ---| Copyright (C) 2005 Peio Azkarate, peio@opencores.org | ---| | ---| This source file may be used and distributed without | ---| restriction provided that this copyright statement is not | ---| removed from the file and that any derivative work contains | ---| the original copyright notice and the associated disclaimer. | ---| | ---| This source file is free software; you can redistribute it | ---| and/or modify it under the terms of the GNU Lesser General | ---| Public License as published by the Free Software Foundation; | ---| either version 2.1 of the License, or (at your option) any | ---| later version. | ---| | ---| This source is distributed in the hope that it will be | ---| useful, but WITHOUT ANY WARRANTY; without even the implied | ---| warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR | ---| PURPOSE. See the GNU Lesser General Public License for more | ---| details. | ---| | ---| You should have received a copy of the GNU Lesser General | ---| Public License along with this source; if not, download it | ---| from http://www.opencores.org/lgpl.shtml | ---| | ---+-----------------------------------------------------------------+ - - ---+-----------------------------------------------------------------------------+ ---| LIBRARIES | ---+-----------------------------------------------------------------------------+ - -library ieee; -use ieee.std_logic_1164.all; - - - ---+-----------------------------------------------------------------------------+ ---| ENTITY | ---+-----------------------------------------------------------------------------+ - -entity pcipargen is -port ( - - clk_i : in std_logic; - pcidatout_i : in std_logic_vector(31 downto 0); - cbe_i : in std_logic_vector(3 downto 0); - parOE_i : in std_logic; - par_o : out std_logic - -); -end pcipargen; - - -architecture rtl of pcipargen is - - ---+-----------------------------------------------------------------------------+ ---| COMPONENTS | ---+-----------------------------------------------------------------------------+ ---+-----------------------------------------------------------------------------+ ---| CONSTANTS | ---+-----------------------------------------------------------------------------+ ---+-----------------------------------------------------------------------------+ ---| SIGNALS | ---+-----------------------------------------------------------------------------+ - - signal d : std_logic_vector(31 downto 0); - signal pardat : std_logic; - signal parcbe : std_logic; - signal par : std_logic; - signal par_s : std_logic; - -component sync -port ( - clk : in std_logic; - d : in std_logic; - q : out std_logic -); -end component; - -component sync2 -port ( - clk : in std_logic; - d : in std_logic; - q : out std_logic -); -end component; - -begin - - - d <= pcidatout_i; - - - --+-------------------------------------------------------------------------+ - --| building parity | - --+-------------------------------------------------------------------------+ - - pardat <= d(0) xor d(1) xor d(2) xor d(3) xor d(4) xor d(5) xor d(6) xor d(7) xor - d(8) xor d(9) xor d(10) xor d(11) xor d(12) xor d(13) xor d(14) xor d(15) xor - d(16) xor d(17) xor d(18) xor d(19) xor d(20) xor d(21) xor d(22) xor d(23) xor - d(24) xor d(25) xor d(26) xor d(27) xor d(28) xor d(29) xor d(30) xor d(31); - - parcbe <= cbe_i(0) xor cbe_i(1) xor cbe_i(2) xor cbe_i(3); - - par <= pardat xor parcbe; - - -- u1: sync port map ( clk => clk_i, d => par, q => par_s ); - - u1: sync2 port map ( - clk => clk_i, - d => par, - q => par_s - ); - - - --+-------------------------------------------------------------------------+ - --| PAR | - --+-------------------------------------------------------------------------+ - - par_o <= par_s when ( parOE_i = '1' ) else 'Z'; - - -end rtl; Index: trunk/source/pcidec.v =================================================================== --- trunk/source/pcidec.v (revision 9) +++ trunk/source/pcidec.v (nonexistent) @@ -1,67 +0,0 @@ -// Copyright (C) 2005 Peio Azkarate, peio@opencores.org -// Copyright (C) 2006 Jeff Carr, jcarr@opencores.org -// Copyleft GPL v2 - -module pcidec_new (clk_i, nrst_i, ad_i, cbe_i, idsel_i, bar0_i, memEN_i, - pciadrLD_i, adrcfg_o, adrmem_o, adr_o, cmd_o); - - // General - input clk_i; - input nrst_i; - // pci - input [31:0] ad_i; - input [3:0] cbe_i; - input idsel_i; - // control - input [31:25] bar0_i; - input memEN_i; - input pciadrLD_i; - output adrcfg_o; - output adrmem_o; - output [24:1] adr_o; - output [3:0] cmd_o; - - reg [31:0] adr; - reg [3:0] cmd; - reg idsel_s; - wire a1; - - //+-------------------------------------------------------------------------+ - //| Load PCI Signals | - //+-------------------------------------------------------------------------+ - - always @( negedge nrst_i or posedge clk_i ) - begin - if( nrst_i == 0 ) - begin - adr <= 23'b1111_1111_1111_1111_1111_111; - cmd <= 3'b111; - idsel_s <= 1'b0; - end - else - if ( pciadrLD_i == 1 ) - begin - adr <= ad_i; - cmd <= cbe_i; - idsel_s <= idsel_i; - end - end - - assign adrmem_o = ( - ( memEN_i == 1'b1 ) && - ( adr [31:25] == bar0_i ) && - ( adr [1:0] == 2'b00 ) && - ( cmd [3:1] == 3'b011 ) - ) ? 1'b1 : 1'b0; - - assign adrcfg_o = ( - ( idsel_s == 1'b1 ) && - ( adr [1:0] == 2'b00 ) && - ( cmd [3:1] == 3'b101 ) - ) ? 1'b1 : 1'b0; - - assign a1 = ~ ( cbe_i [3] && cbe_i [2] ); - assign adr_o = {adr [24:2], a1}; - assign cmd_o = cmd; - -endmodule Index: trunk/source/pfs.v =================================================================== --- trunk/source/pfs.v (revision 9) +++ trunk/source/pfs.v (nonexistent) @@ -1,11 +0,0 @@ -module pfs2 (clk, a, b); - input clk; - input a; - output b; - reg b; - - always @(posedge clk) - begin - b <= a; - end -endmodule Index: trunk/source/generate_pci32tlite/gen_pci32tlite.pl =================================================================== --- trunk/source/generate_pci32tlite/gen_pci32tlite.pl (revision 9) +++ trunk/source/generate_pci32tlite/gen_pci32tlite.pl (nonexistent) @@ -1,31 +0,0 @@ -#!/usr/bin/perl -# - -$TOTAL = 42; - -system ("cat pci32tlite.vhd.part1"); - -foreach $i ( 1 .. $TOTAL ) { - my $j = 12345670 + $i; - my $end = ";"; - $end = "" if $i eq $TOTAL; - print "\t\tjcarr$i" . "ID : std_logic_vector(31 downto 0) := x\"$j\"$end\n"; -} - -system ("cat pci32tlite.vhd.part2"); - -foreach $i ( 1 .. $TOTAL ) { - my $end = ";"; - $end = "" if $i eq $TOTAL; - print "\t\tjcarr$i" . "ID : std_logic_vector(31 downto 0)$end\n"; -} - -system ("cat pci32tlite.vhd.part3"); - -foreach $i ( 1 .. $TOTAL ) { - my $end = ","; - $end = "" if $i eq $TOTAL; - print "\t\tjcarr$i" . "ID => jcarr$i" . "ID$end\n"; -} - -system ("cat pci32tlite.vhd.part4");

trunk/source/generate_pci32tlite/gen_pci32tlite.pl Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/source/generate_pci32tlite/pci32tlite.vhd.part1 =================================================================== --- trunk/source/generate_pci32tlite/pci32tlite.vhd.part1 (revision 9) +++ trunk/source/generate_pci32tlite/pci32tlite.vhd.part1 (nonexistent) @@ -1,75 +0,0 @@ ---+-------------------------------------------------------------------------------------------------+ ---| | ---| File: pci32tlite.vhd | ---| | ---| Components: pcidec_new.vhd | ---| pciwbsequ.vhd | ---| pcidmux.vhd | ---| pciregs.vhd | ---| pcipargen.vhd | ---| -- Libs -- | ---| ona.vhd | ---| | ---| Description: TARGET PCI : | ---| | ---| * PCI Target 32 Bits | ---| * BAR0 32MByte address space | ---| * Whisbone compatible: D16, 32MB address space | ---| | ---+-------------------------------------------------------------------------------------------------+ ---| | ---| Revision history : | ---| Date Version Author Description | ---| 2005-05-13 R00A00 PAU First alfa revision (eng) | ---| 2006-01-05 R00B00 MS inverted reset nres | ---| and added debug signals debug_init and debug_access | | ---| | ---| To do: | ---| | ---+-------------------------------------------------------------------------------------------------+ ---+-----------------------------------------------------------------+ ---| | ---| Copyright (C) 2005 Peio Azkarate, peio@opencores.org | ---| | ---| This source file may be used and distributed without | ---| restriction provided that this copyright statement is not | ---| removed from the file and that any derivative work contains | ---| the original copyright notice and the associated disclaimer. | ---| | ---| This source file is free software; you can redistribute it | ---| and/or modify it under the terms of the GNU Lesser General | ---| Public License as published by the Free Software Foundation; | ---| either version 2.1 of the License, or (at your option) any | ---| later version. | ---| | ---| This source is distributed in the hope that it will be | ---| useful, but WITHOUT ANY WARRANTY; without even the implied | ---| warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR | ---| PURPOSE. See the GNU Lesser General Public License for more | ---| details. | ---| | ---| You should have received a copy of the GNU Lesser General | ---| Public License along with this source; if not, download it | ---| from http://www.opencores.org/lgpl.shtml | ---| | ---+-----------------------------------------------------------------+ - ---+-----------------------------------------------------------------------------+ ---| LIBRARIES | ---+-----------------------------------------------------------------------------+ - -library ieee; -use ieee.std_logic_1164.all; - ---+-----------------------------------------------------------------------------+ ---| ENTITY | ---+-----------------------------------------------------------------------------+ - -entity pci32tlite is -generic ( - - vendorID : std_logic_vector(15 downto 0) := x"10EE"; - deviceID : std_logic_vector(15 downto 0) := x"0100"; - revisionID : std_logic_vector(7 downto 0) := x"37"; - subsystemID : std_logic_vector(15 downto 0) := x"1558"; - subsystemvID : std_logic_vector(15 downto 0) := x"0480"; Index: trunk/source/generate_pci32tlite/pci32tlite.vhd.part2 =================================================================== --- trunk/source/generate_pci32tlite/pci32tlite.vhd.part2 (revision 9) +++ trunk/source/generate_pci32tlite/pci32tlite.vhd.part2 (nonexistent) @@ -1,142 +0,0 @@ - -); -port ( - - -- General - clk33 : in std_logic; - nrst : in std_logic; - - -- PCI target 32bits - ad : inout std_logic_vector(31 downto 0); - cbe : in std_logic_vector(3 downto 0); - par : out std_logic; - frame : in std_logic; - irdy : in std_logic; - trdy : out std_logic; - devsel : out std_logic; - stop : out std_logic; - idsel : in std_logic; - perr : out std_logic; - serr : out std_logic; - intb : out std_logic; - - -- Master whisbone - wb_adr_o : out std_logic_vector(24 downto 1); - wb_dat_i : in std_logic_vector(15 downto 0); - wb_dat_o : out std_logic_vector(15 downto 0); - wb_sel_o : out std_logic_vector(1 downto 0); - wb_we_o : out std_logic; - wb_stb_o : inout std_logic; - wb_cyc_o : out std_logic; - wb_ack_i : in std_logic; - wb_err_i : in std_logic; - wb_int_i : in std_logic; - - -- debug signals - debug_init : out std_logic; - debug_access : out std_logic - -); -end pci32tlite; - - ---+-----------------------------------------------------------------------------+ ---| ARCHITECTURE | ---+-----------------------------------------------------------------------------+ - -architecture rtl of pci32tlite is - - ---+-----------------------------------------------------------------------------+ ---| COMPONENTS | ---+-----------------------------------------------------------------------------+ - - - component pcidec_new - port ( - - clk_i : in std_logic; - nrst_i : in std_logic; - -- - ad_i : in std_logic_vector(31 downto 0); - cbe_i : in std_logic_vector(3 downto 0); - idsel_i : in std_logic; - bar0_i : in std_logic_vector(31 downto 25); - memEN_i : in std_logic; - pciadrLD_i : in std_logic; - adrcfg_o : out std_logic; - adrmem_o : out std_logic; - adr_o : out std_logic_vector(24 downto 1); - cmd_o : out std_logic_vector(3 downto 0) - - ); - end component; - - - component pciwbsequ - port ( - - -- General - clk_i : in std_logic; - nrst_i : in std_logic; - -- pci - cmd_i : in std_logic_vector(3 downto 0); - cbe_i : in std_logic_vector(3 downto 0); - frame_i : in std_logic; - irdy_i : in std_logic; - devsel_o : out std_logic; - trdy_o : out std_logic; - -- control - adrcfg_i : in std_logic; - adrmem_i : in std_logic; - pciadrLD_o : out std_logic; - pcidOE_o : out std_logic; - parOE_o : out std_logic; - wbdatLD_o : out std_logic; - wbrgdMX_o : out std_logic; - wbd16MX_o : out std_logic; - wrcfg_o : out std_logic; - rdcfg_o : out std_logic; - -- whisbone - wb_sel_o : out std_logic_vector(1 downto 0); - wb_we_o : out std_logic; - wb_stb_o : inout std_logic; - wb_cyc_o : out std_logic; - wb_ack_i : in std_logic; - wb_err_i : in std_logic; - -- debug signals - debug_init : out std_logic; - debug_access : out std_logic - ); - end component; - - - component pcidmux - port ( - - clk_i : in std_logic; - nrst_i : in std_logic; - -- - d_io : inout std_logic_vector(31 downto 0); - pcidatout_o : out std_logic_vector(31 downto 0); - pcidOE_i : in std_logic; - wbdatLD_i : in std_logic; - wbrgdMX_i : in std_logic; - wbd16MX_i : in std_logic; - wb_dat_i : in std_logic_vector(15 downto 0); - wb_dat_o : out std_logic_vector(15 downto 0); - rg_dat_i : in std_logic_vector(31 downto 0); - rg_dat_o : out std_logic_vector(31 downto 0) - - ); - end component; - - - component pciregs - generic ( - - vendorID : std_logic_vector(15 downto 0); - deviceID : std_logic_vector(15 downto 0); - revisionID : std_logic_vector(7 downto 0); - subsystemID : std_logic_vector(15 downto 0); - subsystemvID : std_logic_vector(15 downto 0); Index: trunk/source/generate_pci32tlite/pci32tlite.vhd.part3 =================================================================== --- trunk/source/generate_pci32tlite/pci32tlite.vhd.part3 (revision 9) +++ trunk/source/generate_pci32tlite/pci32tlite.vhd.part3 (nonexistent) @@ -1,176 +0,0 @@ - - ); - port ( - - clk_i : in std_logic; - nrst_i : in std_logic; - -- - adr_i : in std_logic_vector(7 downto 2); - cbe_i : in std_logic_vector(3 downto 0); - dat_i : in std_logic_vector(31 downto 0); - dat_o : out std_logic_vector(31 downto 0); - wrcfg_i : in std_logic; - rdcfg_i : in std_logic; - perr_i : in std_logic; - serr_i : in std_logic; - tabort_i : in std_logic; - bar0_o : out std_logic_vector(31 downto 25); - perrEN_o : out std_logic; - serrEN_o : out std_logic; - memEN_o : out std_logic - - ); - end component; - - - component pcipargen - port ( - - clk_i : in std_logic; - pcidatout_i : in std_logic_vector(31 downto 0); - cbe_i : in std_logic_vector(3 downto 0); - parOE_i : in std_logic; - par_o : out std_logic - - ); - end component; - - ---+-----------------------------------------------------------------------------+ ---| CONSTANTS | ---+-----------------------------------------------------------------------------+ ---+-----------------------------------------------------------------------------+ ---| SIGNALS | ---+-----------------------------------------------------------------------------+ - - signal bar0 : std_logic_vector(31 downto 25); - signal memEN : std_logic; - signal pciadrLD : std_logic; - signal adrcfg : std_logic; - signal adrmem : std_logic; - signal adr : std_logic_vector(24 downto 1); - signal cmd : std_logic_vector(3 downto 0); - signal pcidOE : std_logic; - signal parOE : std_logic; - signal wbdatLD : std_logic; - signal wbrgdMX : std_logic; - signal wbd16MX : std_logic; - signal wrcfg : std_logic; - signal rdcfg : std_logic; - signal pcidatread : std_logic_vector(31 downto 0); - signal pcidatwrite : std_logic_vector(31 downto 0); - signal pcidatout : std_logic_vector(31 downto 0); - signal parerr : std_logic; - signal syserr : std_logic; - signal tabort : std_logic; - signal perrEN : std_logic; - signal serrEN : std_logic; - -begin - - - --+-------------------------------------------------------------------------+ - --| Component instances | - --+-------------------------------------------------------------------------+ - - --+-----------------------------------------+ - --| PCI decoder | - --+-----------------------------------------+ - - u1: component pcidec_new - port map ( - - clk_i => clk33, - nrst_i => nrst, - -- - ad_i => ad, - cbe_i => cbe, - idsel_i => idsel, - bar0_i => bar0, - memEN_i => memEN, - pciadrLD_i => pciadrLD, - adrcfg_o => adrcfg, - adrmem_o => adrmem, - adr_o => adr, - cmd_o => cmd - - ); - - - --+-----------------------------------------+ - --| PCI-WB Sequencer | - --+-----------------------------------------+ - - u2: component pciwbsequ - port map ( - - -- General - clk_i => clk33, - nrst_i => nrst, - -- pci - cmd_i => cmd, - cbe_i => cbe, - frame_i => frame, - irdy_i => irdy, - devsel_o => devsel, - trdy_o => trdy, - -- control - adrcfg_i => adrcfg, - adrmem_i => adrmem, - pciadrLD_o => pciadrLD, - pcidOE_o => pcidOE, - parOE_o => parOE, - wbdatLD_o => wbdatLD, - wbrgdMX_o => wbrgdMX, - wbd16MX_o => wbd16MX, - wrcfg_o => wrcfg, - rdcfg_o => rdcfg, - -- whisbone - wb_sel_o => wb_sel_o, - wb_we_o => wb_we_o, - wb_stb_o => wb_stb_o, - wb_cyc_o => wb_cyc_o, - wb_ack_i => wb_ack_i, - wb_err_i => wb_err_i, - -- debug signals - debug_init => debug_init, - debug_access => debug_access - ); - - - --+-----------------------------------------+ - --| PCI-wb datamultiplexer | - --+-----------------------------------------+ - - u3: component pcidmux - port map ( - - clk_i => clk33, - nrst_i => nrst, - -- - d_io => ad, - pcidatout_o => pcidatout, - pcidOE_i => pcidOE, - wbdatLD_i => wbdatLD, - wbrgdMX_i => wbrgdMX, - wbd16MX_i => wbd16MX, - wb_dat_i => wb_dat_i, - wb_dat_o => wb_dat_o, - rg_dat_i => pcidatread, - rg_dat_o => pcidatwrite - - ); - - - --+-----------------------------------------+ - --| PCI registers | - --+-----------------------------------------+ - - u4: component pciregs - generic map ( - - vendorID => vendorID, - deviceID => deviceID, - revisionID => revisionID, - subsystemID => subsystemID, - subsystemvID => subsystemvID, Index: trunk/source/generate_pci32tlite/pci32tlite.vhd.part4 =================================================================== --- trunk/source/generate_pci32tlite/pci32tlite.vhd.part4 (revision 9) +++ trunk/source/generate_pci32tlite/pci32tlite.vhd.part4 (nonexistent) @@ -1,71 +0,0 @@ - - ) - port map ( - - clk_i => clk33, - nrst_i => nrst, - -- - adr_i => adr(7 downto 2), - cbe_i => cbe, - dat_i => pcidatwrite, - dat_o => pcidatread, - wrcfg_i => wrcfg, - rdcfg_i => rdcfg, - perr_i => parerr, - serr_i => syserr, - tabort_i => tabort, - bar0_o => bar0, - perrEN_o => perrEN, - serrEN_o => serrEN, - memEN_o => memEN - - ); - - --+-----------------------------------------+ - --| PCI Parity Gnerator | - --+-----------------------------------------+ - - u5: component pcipargen - port map ( - - clk_i => clk33, - pcidatout_i => pcidatout, - cbe_i => cbe, - parOE_i => parOE, - par_o => par - - ); - - - --+-----------------------------------------+ - --| Whisbone Address bus | - --+-----------------------------------------+ - - wb_adr_o <= adr; - - - --+-----------------------------------------+ - --| unimplemented | - --+-----------------------------------------+ - - parerr <= '0'; - syserr <= '0'; - tabort <= '0'; - - - --+-----------------------------------------+ - --| unused outputs | - --+-----------------------------------------+ - -- #stop: Curret TARGET indicates to Master stop current transaction - -- #perr: - -- #serr: - - perr <= 'Z'; - serr <= 'Z'; - stop <= 'Z'; - intb <= '0' when ( wb_int_i = '1' ) else 'Z'; - - -end rtl; - - Index: trunk/source/generate_pci32tlite/new_pci32tlite.vhd =================================================================== --- trunk/source/generate_pci32tlite/new_pci32tlite.vhd (revision 9) +++ trunk/source/generate_pci32tlite/new_pci32tlite.vhd (nonexistent) @@ -1,590 +0,0 @@ ---+-------------------------------------------------------------------------------------------------+ ---| | ---| File: pci32tlite.vhd | ---| | ---| Components: pcidec_new.vhd | ---| pciwbsequ.vhd | ---| pcidmux.vhd | ---| pciregs.vhd | ---| pcipargen.vhd | ---| -- Libs -- | ---| ona.vhd | ---| | ---| Description: TARGET PCI : | ---| | ---| * PCI Target 32 Bits | ---| * BAR0 32MByte address space | ---| * Whisbone compatible: D16, 32MB address space | ---| | ---+-------------------------------------------------------------------------------------------------+ ---| | ---| Revision history : | ---| Date Version Author Description | ---| 2005-05-13 R00A00 PAU First alfa revision (eng) | ---| 2006-01-05 R00B00 MS inverted reset nres | ---| and added debug signals debug_init and debug_access | | ---| | ---| To do: | ---| | ---+-------------------------------------------------------------------------------------------------+ ---+-----------------------------------------------------------------+ ---| | ---| Copyright (C) 2005 Peio Azkarate, peio@opencores.org | ---| | ---| This source file may be used and distributed without | ---| restriction provided that this copyright statement is not | ---| removed from the file and that any derivative work contains | ---| the original copyright notice and the associated disclaimer. | ---| | ---| This source file is free software; you can redistribute it | ---| and/or modify it under the terms of the GNU Lesser General | ---| Public License as published by the Free Software Foundation; | ---| either version 2.1 of the License, or (at your option) any | ---| later version. | ---| | ---| This source is distributed in the hope that it will be | ---| useful, but WITHOUT ANY WARRANTY; without even the implied | ---| warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR | ---| PURPOSE. See the GNU Lesser General Public License for more | ---| details. | ---| | ---| You should have received a copy of the GNU Lesser General | ---| Public License along with this source; if not, download it | ---| from http://www.opencores.org/lgpl.shtml | ---| | ---+-----------------------------------------------------------------+ - ---+-----------------------------------------------------------------------------+ ---| LIBRARIES | ---+-----------------------------------------------------------------------------+ - -library ieee; -use ieee.std_logic_1164.all; - ---+-----------------------------------------------------------------------------+ ---| ENTITY | ---+-----------------------------------------------------------------------------+ - -entity pci32tlite is -generic ( - - vendorID : std_logic_vector(15 downto 0) := x"10EE"; - deviceID : std_logic_vector(15 downto 0) := x"0100"; - revisionID : std_logic_vector(7 downto 0) := x"37"; - subsystemID : std_logic_vector(15 downto 0) := x"1558"; - subsystemvID : std_logic_vector(15 downto 0) := x"0480"; - jcarr1ID : std_logic_vector(31 downto 0) := x"12345671"; - jcarr2ID : std_logic_vector(31 downto 0) := x"12345672"; - jcarr3ID : std_logic_vector(31 downto 0) := x"12345673"; - jcarr4ID : std_logic_vector(31 downto 0) := x"12345674"; - jcarr5ID : std_logic_vector(31 downto 0) := x"12345675"; - jcarr6ID : std_logic_vector(31 downto 0) := x"12345676"; - jcarr7ID : std_logic_vector(31 downto 0) := x"12345677"; - jcarr8ID : std_logic_vector(31 downto 0) := x"12345678"; - jcarr9ID : std_logic_vector(31 downto 0) := x"12345679"; - jcarr10ID : std_logic_vector(31 downto 0) := x"12345680"; - jcarr11ID : std_logic_vector(31 downto 0) := x"12345681"; - jcarr12ID : std_logic_vector(31 downto 0) := x"12345682"; - jcarr13ID : std_logic_vector(31 downto 0) := x"12345683"; - jcarr14ID : std_logic_vector(31 downto 0) := x"12345684"; - jcarr15ID : std_logic_vector(31 downto 0) := x"12345685"; - jcarr16ID : std_logic_vector(31 downto 0) := x"12345686"; - jcarr17ID : std_logic_vector(31 downto 0) := x"12345687"; - jcarr18ID : std_logic_vector(31 downto 0) := x"12345688"; - jcarr19ID : std_logic_vector(31 downto 0) := x"12345689"; - jcarr20ID : std_logic_vector(31 downto 0) := x"12345690"; - jcarr21ID : std_logic_vector(31 downto 0) := x"12345691"; - jcarr22ID : std_logic_vector(31 downto 0) := x"12345692"; - jcarr23ID : std_logic_vector(31 downto 0) := x"12345693"; - jcarr24ID : std_logic_vector(31 downto 0) := x"12345694"; - jcarr25ID : std_logic_vector(31 downto 0) := x"12345695"; - jcarr26ID : std_logic_vector(31 downto 0) := x"12345696"; - jcarr27ID : std_logic_vector(31 downto 0) := x"12345697"; - jcarr28ID : std_logic_vector(31 downto 0) := x"12345698"; - jcarr29ID : std_logic_vector(31 downto 0) := x"12345699"; - jcarr30ID : std_logic_vector(31 downto 0) := x"12345700"; - jcarr31ID : std_logic_vector(31 downto 0) := x"12345701"; - jcarr32ID : std_logic_vector(31 downto 0) := x"12345702"; - jcarr33ID : std_logic_vector(31 downto 0) := x"12345703"; - jcarr34ID : std_logic_vector(31 downto 0) := x"12345704"; - jcarr35ID : std_logic_vector(31 downto 0) := x"12345705"; - jcarr36ID : std_logic_vector(31 downto 0) := x"12345706"; - jcarr37ID : std_logic_vector(31 downto 0) := x"12345707"; - jcarr38ID : std_logic_vector(31 downto 0) := x"12345708"; - jcarr39ID : std_logic_vector(31 downto 0) := x"12345709"; - jcarr40ID : std_logic_vector(31 downto 0) := x"12345710"; - jcarr41ID : std_logic_vector(31 downto 0) := x"12345711"; - jcarr42ID : std_logic_vector(31 downto 0) := x"12345712" - -); -port ( - - -- General - clk33 : in std_logic; - nrst : in std_logic; - - -- PCI target 32bits - ad : inout std_logic_vector(31 downto 0); - cbe : in std_logic_vector(3 downto 0); - par : out std_logic; - frame : in std_logic; - irdy : in std_logic; - trdy : out std_logic; - devsel : out std_logic; - stop : out std_logic; - idsel : in std_logic; - perr : out std_logic; - serr : out std_logic; - intb : out std_logic; - - -- Master whisbone - wb_adr_o : out std_logic_vector(24 downto 1); - wb_dat_i : in std_logic_vector(15 downto 0); - wb_dat_o : out std_logic_vector(15 downto 0); - wb_sel_o : out std_logic_vector(1 downto 0); - wb_we_o : out std_logic; - wb_stb_o : inout std_logic; - wb_cyc_o : out std_logic; - wb_ack_i : in std_logic; - wb_err_i : in std_logic; - wb_int_i : in std_logic; - - -- debug signals - debug_init : out std_logic; - debug_access : out std_logic - -); -end pci32tlite; - - ---+-----------------------------------------------------------------------------+ ---| ARCHITECTURE | ---+-----------------------------------------------------------------------------+ - -architecture rtl of pci32tlite is - - ---+-----------------------------------------------------------------------------+ ---| COMPONENTS | ---+-----------------------------------------------------------------------------+ - - - component pcidec_new - port ( - - clk_i : in std_logic; - nrst_i : in std_logic; - -- - ad_i : in std_logic_vector(31 downto 0); - cbe_i : in std_logic_vector(3 downto 0); - idsel_i : in std_logic; - bar0_i : in std_logic_vector(31 downto 25); - memEN_i : in std_logic; - pciadrLD_i : in std_logic; - adrcfg_o : out std_logic; - adrmem_o : out std_logic; - adr_o : out std_logic_vector(24 downto 1); - cmd_o : out std_logic_vector(3 downto 0) - - ); - end component; - - - component pciwbsequ - port ( - - -- General - clk_i : in std_logic; - nrst_i : in std_logic; - -- pci - cmd_i : in std_logic_vector(3 downto 0); - cbe_i : in std_logic_vector(3 downto 0); - frame_i : in std_logic; - irdy_i : in std_logic; - devsel_o : out std_logic; - trdy_o : out std_logic; - -- control - adrcfg_i : in std_logic; - adrmem_i : in std_logic; - pciadrLD_o : out std_logic; - pcidOE_o : out std_logic; - parOE_o : out std_logic; - wbdatLD_o : out std_logic; - wbrgdMX_o : out std_logic; - wbd16MX_o : out std_logic; - wrcfg_o : out std_logic; - rdcfg_o : out std_logic; - -- whisbone - wb_sel_o : out std_logic_vector(1 downto 0); - wb_we_o : out std_logic; - wb_stb_o : inout std_logic; - wb_cyc_o : out std_logic; - wb_ack_i : in std_logic; - wb_err_i : in std_logic; - -- debug signals - debug_init : out std_logic; - debug_access : out std_logic - ); - end component; - - - component pcidmux - port ( - - clk_i : in std_logic; - nrst_i : in std_logic; - -- - d_io : inout std_logic_vector(31 downto 0); - pcidatout_o : out std_logic_vector(31 downto 0); - pcidOE_i : in std_logic; - wbdatLD_i : in std_logic; - wbrgdMX_i : in std_logic; - wbd16MX_i : in std_logic; - wb_dat_i : in std_logic_vector(15 downto 0); - wb_dat_o : out std_logic_vector(15 downto 0); - rg_dat_i : in std_logic_vector(31 downto 0); - rg_dat_o : out std_logic_vector(31 downto 0) - - ); - end component; - - - component pciregs - generic ( - - vendorID : std_logic_vector(15 downto 0); - deviceID : std_logic_vector(15 downto 0); - revisionID : std_logic_vector(7 downto 0); - subsystemID : std_logic_vector(15 downto 0); - subsystemvID : std_logic_vector(15 downto 0); - jcarr1ID : std_logic_vector(31 downto 0); - jcarr2ID : std_logic_vector(31 downto 0); - jcarr3ID : std_logic_vector(31 downto 0); - jcarr4ID : std_logic_vector(31 downto 0); - jcarr5ID : std_logic_vector(31 downto 0); - jcarr6ID : std_logic_vector(31 downto 0); - jcarr7ID : std_logic_vector(31 downto 0); - jcarr8ID : std_logic_vector(31 downto 0); - jcarr9ID : std_logic_vector(31 downto 0); - jcarr10ID : std_logic_vector(31 downto 0); - jcarr11ID : std_logic_vector(31 downto 0); - jcarr12ID : std_logic_vector(31 downto 0); - jcarr13ID : std_logic_vector(31 downto 0); - jcarr14ID : std_logic_vector(31 downto 0); - jcarr15ID : std_logic_vector(31 downto 0); - jcarr16ID : std_logic_vector(31 downto 0); - jcarr17ID : std_logic_vector(31 downto 0); - jcarr18ID : std_logic_vector(31 downto 0); - jcarr19ID : std_logic_vector(31 downto 0); - jcarr20ID : std_logic_vector(31 downto 0); - jcarr21ID : std_logic_vector(31 downto 0); - jcarr22ID : std_logic_vector(31 downto 0); - jcarr23ID : std_logic_vector(31 downto 0); - jcarr24ID : std_logic_vector(31 downto 0); - jcarr25ID : std_logic_vector(31 downto 0); - jcarr26ID : std_logic_vector(31 downto 0); - jcarr27ID : std_logic_vector(31 downto 0); - jcarr28ID : std_logic_vector(31 downto 0); - jcarr29ID : std_logic_vector(31 downto 0); - jcarr30ID : std_logic_vector(31 downto 0); - jcarr31ID : std_logic_vector(31 downto 0); - jcarr32ID : std_logic_vector(31 downto 0); - jcarr33ID : std_logic_vector(31 downto 0); - jcarr34ID : std_logic_vector(31 downto 0); - jcarr35ID : std_logic_vector(31 downto 0); - jcarr36ID : std_logic_vector(31 downto 0); - jcarr37ID : std_logic_vector(31 downto 0); - jcarr38ID : std_logic_vector(31 downto 0); - jcarr39ID : std_logic_vector(31 downto 0); - jcarr40ID : std_logic_vector(31 downto 0); - jcarr41ID : std_logic_vector(31 downto 0); - jcarr42ID : std_logic_vector(31 downto 0) - - ); - port ( - - clk_i : in std_logic; - nrst_i : in std_logic; - -- - adr_i : in std_logic_vector(7 downto 2); - cbe_i : in std_logic_vector(3 downto 0); - dat_i : in std_logic_vector(31 downto 0); - dat_o : out std_logic_vector(31 downto 0); - wrcfg_i : in std_logic; - rdcfg_i : in std_logic; - perr_i : in std_logic; - serr_i : in std_logic; - tabort_i : in std_logic; - bar0_o : out std_logic_vector(31 downto 25); - perrEN_o : out std_logic; - serrEN_o : out std_logic; - memEN_o : out std_logic - - ); - end component; - - - component pcipargen - port ( - - clk_i : in std_logic; - pcidatout_i : in std_logic_vector(31 downto 0); - cbe_i : in std_logic_vector(3 downto 0); - parOE_i : in std_logic; - par_o : out std_logic - - ); - end component; - - ---+-----------------------------------------------------------------------------+ ---| CONSTANTS | ---+-----------------------------------------------------------------------------+ ---+-----------------------------------------------------------------------------+ ---| SIGNALS | ---+-----------------------------------------------------------------------------+ - - signal bar0 : std_logic_vector(31 downto 25); - signal memEN : std_logic; - signal pciadrLD : std_logic; - signal adrcfg : std_logic; - signal adrmem : std_logic; - signal adr : std_logic_vector(24 downto 1); - signal cmd : std_logic_vector(3 downto 0); - signal pcidOE : std_logic; - signal parOE : std_logic; - signal wbdatLD : std_logic; - signal wbrgdMX : std_logic; - signal wbd16MX : std_logic; - signal wrcfg : std_logic; - signal rdcfg : std_logic; - signal pcidatread : std_logic_vector(31 downto 0); - signal pcidatwrite : std_logic_vector(31 downto 0); - signal pcidatout : std_logic_vector(31 downto 0); - signal parerr : std_logic; - signal syserr : std_logic; - signal tabort : std_logic; - signal perrEN : std_logic; - signal serrEN : std_logic; - -begin - - - --+-------------------------------------------------------------------------+ - --| Component instances | - --+-------------------------------------------------------------------------+ - - --+-----------------------------------------+ - --| PCI decoder | - --+-----------------------------------------+ - - u1: component pcidec_new - port map ( - - clk_i => clk33, - nrst_i => nrst, - -- - ad_i => ad, - cbe_i => cbe, - idsel_i => idsel, - bar0_i => bar0, - memEN_i => memEN, - pciadrLD_i => pciadrLD, - adrcfg_o => adrcfg, - adrmem_o => adrmem, - adr_o => adr, - cmd_o => cmd - - ); - - - --+-----------------------------------------+ - --| PCI-WB Sequencer | - --+-----------------------------------------+ - - u2: component pciwbsequ - port map ( - - -- General - clk_i => clk33, - nrst_i => nrst, - -- pci - cmd_i => cmd, - cbe_i => cbe, - frame_i => frame, - irdy_i => irdy, - devsel_o => devsel, - trdy_o => trdy, - -- control - adrcfg_i => adrcfg, - adrmem_i => adrmem, - pciadrLD_o => pciadrLD, - pcidOE_o => pcidOE, - parOE_o => parOE, - wbdatLD_o => wbdatLD, - wbrgdMX_o => wbrgdMX, - wbd16MX_o => wbd16MX, - wrcfg_o => wrcfg, - rdcfg_o => rdcfg, - -- whisbone - wb_sel_o => wb_sel_o, - wb_we_o => wb_we_o, - wb_stb_o => wb_stb_o, - wb_cyc_o => wb_cyc_o, - wb_ack_i => wb_ack_i, - wb_err_i => wb_err_i, - -- debug signals - debug_init => debug_init, - debug_access => debug_access - ); - - - --+-----------------------------------------+ - --| PCI-wb datamultiplexer | - --+-----------------------------------------+ - - u3: component pcidmux - port map ( - - clk_i => clk33, - nrst_i => nrst, - -- - d_io => ad, - pcidatout_o => pcidatout, - pcidOE_i => pcidOE, - wbdatLD_i => wbdatLD, - wbrgdMX_i => wbrgdMX, - wbd16MX_i => wbd16MX, - wb_dat_i => wb_dat_i, - wb_dat_o => wb_dat_o, - rg_dat_i => pcidatread, - rg_dat_o => pcidatwrite - - ); - - - --+-----------------------------------------+ - --| PCI registers | - --+-----------------------------------------+ - - u4: component pciregs - generic map ( - - vendorID => vendorID, - deviceID => deviceID, - revisionID => revisionID, - subsystemID => subsystemID, - subsystemvID => subsystemvID, - jcarr1ID => jcarr1ID, - jcarr2ID => jcarr2ID, - jcarr3ID => jcarr3ID, - jcarr4ID => jcarr4ID, - jcarr5ID => jcarr5ID, - jcarr6ID => jcarr6ID, - jcarr7ID => jcarr7ID, - jcarr8ID => jcarr8ID, - jcarr9ID => jcarr9ID, - jcarr10ID => jcarr10ID, - jcarr11ID => jcarr11ID, - jcarr12ID => jcarr12ID, - jcarr13ID => jcarr13ID, - jcarr14ID => jcarr14ID, - jcarr15ID => jcarr15ID, - jcarr16ID => jcarr16ID, - jcarr17ID => jcarr17ID, - jcarr18ID => jcarr18ID, - jcarr19ID => jcarr19ID, - jcarr20ID => jcarr20ID, - jcarr21ID => jcarr21ID, - jcarr22ID => jcarr22ID, - jcarr23ID => jcarr23ID, - jcarr24ID => jcarr24ID, - jcarr25ID => jcarr25ID, - jcarr26ID => jcarr26ID, - jcarr27ID => jcarr27ID, - jcarr28ID => jcarr28ID, - jcarr29ID => jcarr29ID, - jcarr30ID => jcarr30ID, - jcarr31ID => jcarr31ID, - jcarr32ID => jcarr32ID, - jcarr33ID => jcarr33ID, - jcarr34ID => jcarr34ID, - jcarr35ID => jcarr35ID, - jcarr36ID => jcarr36ID, - jcarr37ID => jcarr37ID, - jcarr38ID => jcarr38ID, - jcarr39ID => jcarr39ID, - jcarr40ID => jcarr40ID, - jcarr41ID => jcarr41ID, - jcarr42ID => jcarr42ID - - ) - port map ( - - clk_i => clk33, - nrst_i => nrst, - -- - adr_i => adr(7 downto 2), - cbe_i => cbe, - dat_i => pcidatwrite, - dat_o => pcidatread, - wrcfg_i => wrcfg, - rdcfg_i => rdcfg, - perr_i => parerr, - serr_i => syserr, - tabort_i => tabort, - bar0_o => bar0, - perrEN_o => perrEN, - serrEN_o => serrEN, - memEN_o => memEN - - ); - - --+-----------------------------------------+ - --| PCI Parity Gnerator | - --+-----------------------------------------+ - - u5: component pcipargen - port map ( - - clk_i => clk33, - pcidatout_i => pcidatout, - cbe_i => cbe, - parOE_i => parOE, - par_o => par - - ); - - - --+-----------------------------------------+ - --| Whisbone Address bus | - --+-----------------------------------------+ - - wb_adr_o <= adr; - - - --+-----------------------------------------+ - --| unimplemented | - --+-----------------------------------------+ - - parerr <= '0'; - syserr <= '0'; - tabort <= '0'; - - - --+-----------------------------------------+ - --| unused outputs | - --+-----------------------------------------+ - -- #stop: Curret TARGET indicates to Master stop current transaction - -- #perr: - -- #serr: - - perr <= 'Z'; - serr <= 'Z'; - stop <= 'Z'; - intb <= '0' when ( wb_int_i = '1' ) else 'Z'; - - -end rtl; - - Index: trunk/source/generate_pci32tlite/Makefile =================================================================== --- trunk/source/generate_pci32tlite/Makefile (revision 9) +++ trunk/source/generate_pci32tlite/Makefile (nonexistent) @@ -1,4 +0,0 @@ -all: - ./gen_pci32tlite.pl > new_pci32tlite.vhd - unix2dos new_pci32tlite.vhd - cp new_pci32tlite.vhd .. Index: trunk/pci_7seg.ut =================================================================== --- trunk/pci_7seg.ut (revision 9) +++ trunk/pci_7seg.ut (nonexistent) @@ -1,27 +0,0 @@ - --w --g DebugBitstream:No --g Binary:no --g CRC:Enable --g ConfigRate:6 --g CclkPin:PullUp --g M0Pin:PullUp --g M1Pin:PullUp --g M2Pin:PullUp --g ProgPin:PullUp --g DonePin:PullUp --g TckPin:PullUp --g TdiPin:PullUp --g TdoPin:PullUp --g TmsPin:PullUp --g UnusedPin:PullUp --g UserID:0xFFFFFFFF --g DCIUpdateMode:AsRequired --g StartUpClk:CClk --g DONE_cycle:4 --g GTS_cycle:5 --g GWE_cycle:6 --g LCK_cycle:NoWait --g Security:None --g DonePipe:No --g DriveDone:No Index: trunk/COPYING =================================================================== --- trunk/COPYING (revision 9) +++ trunk/COPYING (nonexistent) @@ -1,340 +0,0 @@ - GNU GENERAL PUBLIC LICENSE - Version 2, June 1991 - - Copyright (C) 1989, 1991 Free Software Foundation, Inc. - 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - Everyone is permitted to copy and distribute verbatim copies - of this license document, but changing it is not allowed. - - Preamble - - The licenses for most software are designed to take away your -freedom to share and change it. By contrast, the GNU General Public -License is intended to guarantee your freedom to share and change free -software--to make sure the software is free for all its users. This -General Public License applies to most of the Free Software -Foundation's software and to any other program whose authors commit to -using it. (Some other Free Software Foundation software is covered by -the GNU Library General Public License instead.) You can apply it to -your programs, too. - - When we speak of free software, we are referring to freedom, not -price. Our General Public Licenses are designed to make sure that you -have the freedom to distribute copies of free software (and charge for -this service if you wish), that you receive source code or can get it -if you want it, that you can change the software or use pieces of it -in new free programs; and that you know you can do these things. - - To protect your rights, we need to make restrictions that forbid -anyone to deny you these rights or to ask you to surrender the rights. -These restrictions translate to certain responsibilities for you if you -distribute copies of the software, or if you modify it. - - For example, if you distribute copies of such a program, whether -gratis or for a fee, you must give the recipients all the rights that -you have. You must make sure that they, too, receive or can get the -source code. And you must show them these terms so they know their -rights. - - We protect your rights with two steps: (1) copyright the software, and -(2) offer you this license which gives you legal permission to copy, -distribute and/or modify the software. - - Also, for each author's protection and ours, we want to make certain -that everyone understands that there is no warranty for this free -software. If the software is modified by someone else and passed on, we -want its recipients to know that what they have is not the original, so -that any problems introduced by others will not reflect on the original -authors' reputations. - - Finally, any free program is threatened constantly by software -patents. We wish to avoid the danger that redistributors of a free -program will individually obtain patent licenses, in effect making the -program proprietary. To prevent this, we have made it clear that any -patent must be licensed for everyone's free use or not licensed at all. - - The precise terms and conditions for copying, distribution and -modification follow. - - GNU GENERAL PUBLIC LICENSE - TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION - - 0. This License applies to any program or other work which contains -a notice placed by the copyright holder saying it may be distributed -under the terms of this General Public License. The "Program", below, -refers to any such program or work, and a "work based on the Program" -means either the Program or any derivative work under copyright law: -that is to say, a work containing the Program or a portion of it, -either verbatim or with modifications and/or translated into another -language. (Hereinafter, translation is included without limitation in -the term "modification".) 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You may copy and distribute verbatim copies of the Program's -source code as you receive it, in any medium, provided that you -conspicuously and appropriately publish on each copy an appropriate -copyright notice and disclaimer of warranty; keep intact all the -notices that refer to this License and to the absence of any warranty; -and give any other recipients of the Program a copy of this License -along with the Program. - -You may charge a fee for the physical act of transferring a copy, and -you may at your option offer warranty protection in exchange for a fee. - - 2. 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See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - -Also add information on how to contact you by electronic and paper mail. - -If the program is interactive, make it output a short notice like this -when it starts in an interactive mode: - - Gnomovision version 69, Copyright (C) year name of author - Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. - This is free software, and you are welcome to redistribute it - under certain conditions; type `show c' for details. - -The hypothetical commands `show w' and `show c' should show the appropriate -parts of the General Public License. Of course, the commands you use may -be called something other than `show w' and `show c'; they could even be -mouse-clicks or menu items--whatever suits your program. - -You should also get your employer (if you work as a programmer) or your -school, if any, to sign a "copyright disclaimer" for the program, if -necessary. Here is a sample; alter the names: - - Yoyodyne, Inc., hereby disclaims all copyright interest in the program - `Gnomovision' (which makes passes at compilers) written by James Hacker. - - , 1 April 1989 - Ty Coon, President of Vice - -This General Public License does not permit incorporating your program into -proprietary programs. If your program is a subroutine library, you may -consider it more useful to permit linking proprietary applications with the -library. If this is what you want to do, use the GNU Library General -Public License instead of this License. Index: trunk/pci_7seg.prj =================================================================== --- trunk/pci_7seg.prj (revision 9) +++ trunk/pci_7seg.prj (nonexistent) @@ -1,16 +0,0 @@ -verilog work "source/sync.v" -verilog work "source/disp_dec.v" -verilog work "source/wb_7seg.v" -verilog work "source/pcidec.v" -verilog work "source/pcidmux.v" - -verilog work "source/pciwbsequ.v" -verilog work "source/pcipargen.v" - -vhdl work "source/pciwbsequ.vhd" -vhdl work "source/pfs.vhd" -vhdl work "source/new_pciregs.vhd" -vhdl work "source/pcipargen.vhd" -vhdl work "source/new_pci32tlite.vhd" -vhdl work "source/vga_main.vhd" -vhdl work "source/top_pci_7seg.vhd" Index: raggedstone/trunk/linuxdriver/userland/send_to_fpga =================================================================== --- raggedstone/trunk/linuxdriver/userland/send_to_fpga (nonexistent) +++ raggedstone/trunk/linuxdriver/userland/send_to_fpga (revision 10) @@ -0,0 +1,23 @@ +ELF



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raggedstone/trunk/linuxdriver/userland/send_to_fpga Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: raggedstone/trunk/linuxdriver/userland/Makefile =================================================================== --- raggedstone/trunk/linuxdriver/userland/Makefile (nonexistent) +++ raggedstone/trunk/linuxdriver/userland/Makefile (revision 10) @@ -0,0 +1,8 @@ +build: + cc send_to_fpga.c -o send_to_fpga + +clean: + -rm -f send_to_fpga + +install: + install send_to_fpga /usr/local/bin/ Index: raggedstone/trunk/linuxdriver/userland/send_to_fpga.c =================================================================== --- raggedstone/trunk/linuxdriver/userland/send_to_fpga.c (nonexistent) +++ raggedstone/trunk/linuxdriver/userland/send_to_fpga.c (revision 10) @@ -0,0 +1,59 @@ +/* + Interface Program for the Linux Driver for Enterpoint's Raggedstone1 FPGA PCI Board + This demo driver allows access to the Board's 7segment displays. + + License: GPL + See file "GPL" for details + +*/ + +#include +#include /* open */ +#include /* exit */ +#include /* ioctl */ +#include + +#define MAJOR_NUM 100 +#define IOCTL_SETDPY _IOR(MAJOR_NUM, 0, short int) +#define DEVICE_NAME "/dev/fpga" + + +int ioctl_setdpy(int file_desc, short int data) +{ + int ret_val; + + ret_val = ioctl(file_desc, IOCTL_SETDPY, data); + + if (ret_val < 0) + { + printf ("ioctl_set_msg failed:%d\n", ret_val); + exit(-1); + } + return(0); +} + +int main(int argc, char ** argv) +{ + int file_desc, ret_val; + char *msg = "Message passed by ioctl\n"; + short int val = 0x7733; + + file_desc = open(DEVICE_NAME, 0); + if (file_desc < 0) + { + printf ("Can't open device file: %s\n", DEVICE_NAME); + exit(-1); + } + + if(argc >= 2 ) + { +// sscanf(argv[1], "0x%x", &val); + val = atoi(argv[1]); +// val = htons(val); + } + else + val = htons(val); + ioctl_setdpy(file_desc, val); + close(file_desc); + exit(0); +} Index: raggedstone/trunk/linuxdriver/Kbuild =================================================================== --- raggedstone/trunk/linuxdriver/Kbuild (nonexistent) +++ raggedstone/trunk/linuxdriver/Kbuild (revision 10) @@ -0,0 +1,3 @@ +obj-m := mod_pci_7seg.o +mod_pci_7seg-y := pci_driver_7seg.o + Index: raggedstone/trunk/linuxdriver/pci_driver_7seg.c =================================================================== --- raggedstone/trunk/linuxdriver/pci_driver_7seg.c (nonexistent) +++ raggedstone/trunk/linuxdriver/pci_driver_7seg.c (revision 10) @@ -0,0 +1,213 @@ +/* + Linux Driver for Enterpoint's Raggedstone1 FPGA PCI Board + This demo driver allows access to the Board's 7segment displays. + + License: GPL + See file "GPL" for details + +*/ + +#ifndef MODULE +#define MODULE +#endif + +#include /* >= 2.6.14 LINUX_VERSION_CODE */ +// #include /* needed to get LINUX_VERSION_CODE >= 2.6.13 */ +#include +#include +#include +#include +#include +#include + + + +MODULE_AUTHOR("Manuel Bessler"); +MODULE_DESCRIPTION("Raggedstone1 FPGA PCI Development Board Driver"); + +#ifdef MODULE_LICENSE +MODULE_LICENSE("GPL"); +#endif + +#define VENDOR_ID 0x10ee +#define DEVICE_ID 0x0100 + +#define MAJOR_NUM 100 +#define IOCTL_SETDPY _IOR(MAJOR_NUM, 0, u16) +#define DEVICE_NAME "fpga" + +#define SUCCESS 0 + +unsigned long memstart = 0, memlen = 0; +void * vaddr = 0; +u16 lastwrite = 0; +static int Device_Open = 0; + + +int device_ioctl( + struct inode *inode, + struct file *file, + unsigned int ioctl_num,/* The number of the ioctl */ + unsigned long ioctl_param) /* The parameter to it */ +{ + u16 display_val; + printk (KERN_INFO "device_ioctl(%p,%p,ioctl_param=0x%x)\n", inode, file, (u16)ioctl_param); + + switch (ioctl_num) + { + case IOCTL_SETDPY: + printk(KERN_INFO "executing IOCTL_SETDPY\n"); + display_val = (u16) ioctl_param; + writew(display_val, vaddr); + break; + } + return SUCCESS; +} + +/* This function is called whenever a process attempts + * to open the device file */ +static int device_open(struct inode *inode, + struct file *file) +{ + printk ("device_open(%p)\n", file); + /* We don't want to talk to two processes at the + * same time */ + if (Device_Open) + return -EBUSY; + Device_Open++; +//#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) +// MOD_INC_USE_COUNT; +//#endif + return SUCCESS; +} + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,2,0) +static int device_close(struct inode *inode, struct file *file) +#else +static void device_close(struct inode *inode, struct file *file) +#endif +{ + printk ("device_release(%p,%p)\n", inode, file); + Device_Open --; +//#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) +// MOD_DEC_USE_COUNT; +//#endif +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,2,0) + return 0; +#endif +} + +struct file_operations Fops = { + open: device_open, + release: device_close, + ioctl: device_ioctl +}; + + + + + + +static struct pci_device_id pci_device_id_DevicePCI[] = +{ + {VENDOR_ID, DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, + {} // end of list +}; + +int device_probe(struct pci_dev *dev, const struct pci_device_id *id) +{ + int ret; + ret = pci_enable_device(dev); + if (ret < 0) + { + printk(KERN_WARNING "DevicePCI: unable to initialize PCI device\n"); + return ret; + } + + ret = pci_request_regions(dev, "MyPCIDevice"); + if (ret < 0) + { + printk(KERN_WARNING "DevicePCI: unable to reserve PCI resources\n"); + pci_disable_device(dev); + return ret; + } + + memstart = pci_resource_start(dev, 0); // 0 for BAR0 + memlen = pci_resource_len(dev, 0); + printk(KERN_WARNING "DevicePCI: memstart=0x%lx memlen=0x%lx\n", memstart, memlen); + + vaddr = ioremap(memstart, memlen); + lastwrite = readw(vaddr); + printk(KERN_WARNING "DevicePCI: vaddr=0x%08X current=0x%08X\n", (u32) vaddr, (u32) lastwrite); +// writew(vaddr, ); +// writew(0xDEAD, vaddr+i); + + printk(KERN_INFO "DevicePCI: device_probe successful\n"); + + /* Register the character device (atleast try) */ + ret = register_chrdev(MAJOR_NUM, DEVICE_NAME, &Fops); + + /* Negative values signify an error */ + if (ret < 0) + { + printk (KERN_INFO "%s failed with %d\n", + "Sorry, registering the character device ", + ret); + return ret; + } + else + { + printk (KERN_INFO "%s The major device number is %d.\n", + "Registeration is a success", + MAJOR_NUM); + printk (KERN_INFO "If you want to talk to the device driver,\n"); + printk (KERN_INFO "you'll have to create a device file. \n"); + printk (KERN_INFO "We suggest you use:\n"); + printk (KERN_INFO "mknod /dev/%s c %d 0\n", DEVICE_NAME, + MAJOR_NUM); + printk (KERN_INFO "The device file name is important, because\n"); + printk (KERN_INFO "the ioctl program assumes that's the\n"); + printk (KERN_INFO "file you'll use.\n"); + } + + return ret; +} + +void device_remove(struct pci_dev *dev) +{ + unregister_chrdev(MAJOR_NUM, DEVICE_NAME); + + iounmap(vaddr); +// release_mem_region(memstart, memlen); + + pci_release_regions(dev); + pci_disable_device(dev); + printk(KERN_INFO "DevicePCI: device removed\n"); +} + +struct pci_driver pci_driver_DevicePCI = +{ + name: "MyPCIDevice", + id_table: pci_device_id_DevicePCI, + probe: device_probe, + remove: device_remove +}; + +static int init_module_DevicePCI(void) +{ + printk(KERN_INFO "DevicePCI: init\n"); + return pci_module_init(&pci_driver_DevicePCI); +} + +void cleanup_module_DevicePCI(void) +{ + printk(KERN_INFO "DevicePCI: cleanup\n"); + pci_unregister_driver(&pci_driver_DevicePCI); +} + +module_init(init_module_DevicePCI); +module_exit(cleanup_module_DevicePCI); + + + + Index: raggedstone/trunk/linuxdriver/Makefile =================================================================== --- raggedstone/trunk/linuxdriver/Makefile (nonexistent) +++ raggedstone/trunk/linuxdriver/Makefile (revision 10) @@ -0,0 +1,20 @@ +ifneq ($(KERNELRELEASE),) +include Kbuild +else +# Normal Makefile +KERNELDIR := /lib/modules/`uname -r`/build + +modules:: + $(MAKE) -C $(KERNELDIR) M=`pwd` $@ + +clean: + $(MAKE) -C $(KERNELDIR) M=`pwd` $@ + -rm -f Module.symvers + +endif + +install: + -rmmod mod_pci_7seg + sleep 1 + insmod ./mod_pci_7seg.ko + -mknod /dev/fpga c 100 0 Index: raggedstone/trunk/README =================================================================== --- raggedstone/trunk/README (nonexistent) +++ raggedstone/trunk/README (revision 10) @@ -0,0 +1,46 @@ +This logic is for the Enterpoint Spartan-3 based PCI fpga card. + +The code needs to be built with the Xilinx tools. You can +download the Xilinx tools for free from xilinx.com. It also +generates a bit of the VHDL by perl, so you need that installed +also. + +Steps to building & using this code: + +1) Install Linux (it should include perl) +2) Download and install the Xilinx WebPack for Linux + * It's about 1GB and Xilinx provides it for free + * The Xilinx tools include a settings.sh file + that you need to run to add the tools to your path +3) Run make to synthisize the image +4) program your card over jtag with XC3prog + xc3sprog pci_7seg.bit + + +This port of the OpenCores PCI core was originally done by Manuel Bessler. +http://projects.varxec.net/raggedstone1 + +If you get this core installed correctly on the Raggedstone1 card, you +can dump out the PCI config space and it should look something like this: + +root@sid:~# hexdump /proc/bus/pci/05/02.0 +0000000 10ee 0100 0102 0200 0037 0280 0000 0000 +0000010 0000 f800 0000 0000 0000 0000 0000 0000 +0000020 0000 0000 0000 0000 0000 0000 0480 1558 +0000030 0000 0000 0000 0000 0000 0000 0104 0000 +0000040 0000 0000 5671 1234 5672 1234 5673 1234 +0000050 5674 1234 5675 1234 5676 1234 5677 1234 +0000060 5678 1234 5679 1234 5680 1234 5681 1234 +0000070 5682 1234 5683 1234 5684 1234 5685 1234 +0000080 5686 1234 5687 1234 5688 1234 5689 1234 +0000090 5690 1234 5691 1234 5692 1234 5693 1234 +00000a0 5694 1234 5695 1234 5696 1234 5697 1234 +00000b0 5698 1234 5699 1234 5700 1234 5701 1234 +00000c0 5702 1234 5703 1234 5704 1234 5705 1234 +00000d0 5706 1234 5707 1234 5708 1234 5709 1234 +00000e0 5710 1234 5711 1234 5712 1234 0000 0000 +00000f0 0000 0000 0000 0000 0000 0000 0000 0000 +0000100 + +-- Jeff Carr + Index: raggedstone/trunk/COPYING =================================================================== --- raggedstone/trunk/COPYING (nonexistent) +++ raggedstone/trunk/COPYING (revision 10) @@ -0,0 +1,340 @@ + GNU GENERAL PUBLIC LICENSE + Version 2, June 1991 + + Copyright (C) 1989, 1991 Free Software Foundation, Inc. + 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The licenses for most software are designed to take away your +freedom to share and change it. By contrast, the GNU General Public +License is intended to guarantee your freedom to share and change free +software--to make sure the software is free for all its users. This +General Public License applies to most of the Free Software +Foundation's software and to any other program whose authors commit to +using it. (Some other Free Software Foundation software is covered by +the GNU Library General Public License instead.) You can apply it to +your programs, too. + + When we speak of free software, we are referring to freedom, not +price. Our General Public Licenses are designed to make sure that you +have the freedom to distribute copies of free software (and charge for +this service if you wish), that you receive source code or can get it +if you want it, that you can change the software or use pieces of it +in new free programs; and that you know you can do these things. + + To protect your rights, we need to make restrictions that forbid +anyone to deny you these rights or to ask you to surrender the rights. +These restrictions translate to certain responsibilities for you if you +distribute copies of the software, or if you modify it. + + For example, if you distribute copies of such a program, whether +gratis or for a fee, you must give the recipients all the rights that +you have. You must make sure that they, too, receive or can get the +source code. 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It is safest +to attach them to the start of each source file to most effectively +convey the exclusion of warranty; and each file should have at least +the "copyright" line and a pointer to where the full notice is found. + + + Copyright (C) + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + +Also add information on how to contact you by electronic and paper mail. + +If the program is interactive, make it output a short notice like this +when it starts in an interactive mode: + + Gnomovision version 69, Copyright (C) year name of author + Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. + This is free software, and you are welcome to redistribute it + under certain conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate +parts of the General Public License. Of course, the commands you use may +be called something other than `show w' and `show c'; they could even be +mouse-clicks or menu items--whatever suits your program. + +You should also get your employer (if you work as a programmer) or your +school, if any, to sign a "copyright disclaimer" for the program, if +necessary. Here is a sample; alter the names: + + Yoyodyne, Inc., hereby disclaims all copyright interest in the program + `Gnomovision' (which makes passes at compilers) written by James Hacker. + + , 1 April 1989 + Ty Coon, President of Vice + +This General Public License does not permit incorporating your program into +proprietary programs. If your program is a subroutine library, you may +consider it more useful to permit linking proprietary applications with the +library. If this is what you want to do, use the GNU Library General +Public License instead of this License. Index: raggedstone/trunk/pci_7seg.bit =================================================================== --- raggedstone/trunk/pci_7seg.bit (nonexistent) +++ raggedstone/trunk/pci_7seg.bit (revision 10) @@ -0,0 +1,165 @@ + ðððð
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+ \ No newline at end of file Index: raggedstone/trunk/source/sync.v =================================================================== --- raggedstone/trunk/source/sync.v (nonexistent) +++ raggedstone/trunk/source/sync.v (revision 10) @@ -0,0 +1,11 @@ +module sync2 (clk, d, q); + input clk; + input d; + output q; + reg q; + + always @(posedge clk) + begin + q <= d; + end +endmodule Index: raggedstone/trunk/source/pciwbsequ.vhd =================================================================== --- raggedstone/trunk/source/pciwbsequ.vhd (nonexistent) +++ raggedstone/trunk/source/pciwbsequ.vhd (revision 10) @@ -0,0 +1,382 @@ +--+-------------------------------------------------------------------------------------------------+ +--| | +--| File: pciwbsequ.vhd | +--| | +--| Project: pci32tlite_oc | +--| | +--| Description: FSM controlling PCI to Whisbone sequence. | +--| | +--+-------------------------------------------------------------------------------------------------+ +--| | +--| Revision history : | +--| Date Version Author Description | +--| 2005-05-13 R00A00 PAU First alfa revision (eng) | +--| 2006-01-09 MS added debug signals debug_init, debug_access | | +--| | +--| To do: | +--| | +--+-------------------------------------------------------------------------------------------------+ +--+-----------------------------------------------------------------+ +--| | +--| Copyright (C) 2005 Peio Azkarate, peio@opencores.org | +--| | +--| This source file may be used and distributed without | +--| restriction provided that this copyright statement is not | +--| removed from the file and that any derivative work contains | +--| the original copyright notice and the associated disclaimer. | +--| | +--| This source file is free software; you can redistribute it | +--| and/or modify it under the terms of the GNU Lesser General | +--| Public License as published by the Free Software Foundation; | +--| either version 2.1 of the License, or (at your option) any | +--| later version. | +--| | +--| This source is distributed in the hope that it will be | +--| useful, but WITHOUT ANY WARRANTY; without even the implied | +--| warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR | +--| PURPOSE. See the GNU Lesser General Public License for more | +--| details. | +--| | +--| You should have received a copy of the GNU Lesser General | +--| Public License along with this source; if not, download it | +--| from http://www.opencores.org/lgpl.shtml | +--| | +--+-----------------------------------------------------------------+ + + +--+-----------------------------------------------------------------------------+ +--| LIBRARIES | +--+-----------------------------------------------------------------------------+ + +library ieee; +use ieee.std_logic_1164.all; + + +--+-----------------------------------------------------------------------------+ +--| ENTITY | +--+-----------------------------------------------------------------------------+ + +entity pciwbsequ is +port ( + + -- General + clk_i : in std_logic; + nrst_i : in std_logic; + -- pci + --adr_i + cmd_i : in std_logic_vector(3 downto 0); + cbe_i : in std_logic_vector(3 downto 0); + frame_i : in std_logic; + irdy_i : in std_logic; + devsel_o : out std_logic; + trdy_o : out std_logic; + -- control + adrcfg_i : in std_logic; + adrmem_i : in std_logic; + pciadrLD_o : out std_logic; + pcidOE_o : out std_logic; + parOE_o : out std_logic; + wbdatLD_o : out std_logic; + wbrgdMX_o : out std_logic; + wbd16MX_o : out std_logic; + wrcfg_o : out std_logic; + rdcfg_o : out std_logic; + -- whisbone + wb_sel_o : out std_logic_vector(1 downto 0); + wb_we_o : out std_logic; + wb_stb_o : inout std_logic; + wb_cyc_o : out std_logic; + wb_ack_i : in std_logic; + wb_err_i : in std_logic; + -- debug signals + debug_init : out std_logic; + debug_access : out std_logic +); +end pciwbsequ; + + +architecture rtl of pciwbsequ is + + +--+-----------------------------------------------------------------------------+ +--| COMPONENTS | +--+-----------------------------------------------------------------------------+ +--+-----------------------------------------------------------------------------+ +--| CONSTANTS | +--+-----------------------------------------------------------------------------+ +--+-----------------------------------------------------------------------------+ +--| SIGNALS | +--+-----------------------------------------------------------------------------+ + + type PciFSM is ( PCIIDLE, B_BUSY, S_DATA1, S_DATA2, TURN_AR ); + signal pst_pci : PciFSM; + signal nxt_pci : PciFSM; + + signal sdata1 : std_logic; + signal sdata2 : std_logic; + signal idleNX : std_logic; + signal sdata1NX : std_logic; + signal sdata2NX : std_logic; + signal turnarNX : std_logic; + signal idle : std_logic; + signal devselNX_n : std_logic; + signal trdyNX_n : std_logic; + signal devsel : std_logic; + signal trdy : std_logic; + signal adrpci : std_logic; + signal acking : std_logic; + signal rdcfg : std_logic; + signal targOE : std_logic; + signal pcidOE : std_logic; + + +begin + + --+-------------------------------------------------------------------------+ + --| PCI-Whisbone Sequencer | + --+-------------------------------------------------------------------------+ + + + --+-------------------------------------------------------------+ + --| FSM PCI-Whisbone | + --+-------------------------------------------------------------+ + + PCIFSM_CLOCKED: process( nrst_i, clk_i, nxt_pci ) + begin + + if( nrst_i = '0' ) then + pst_pci <= PCIIDLE; + elsif( rising_edge(clk_i) ) then + pst_pci <= nxt_pci; + end if; + + end process PCIFSM_CLOCKED; + + + PCIFSM_COMB: process( pst_pci, frame_i, irdy_i, adrcfg_i, adrpci, acking ) + begin + + devselNX_n <= '1'; + trdyNX_n <= '1'; + case pst_pci is + + when PCIIDLE => + if ( frame_i = '0' ) then + nxt_pci <= B_BUSY; + else + nxt_pci <= PCIIDLE; + end if; + + when B_BUSY => + if ( adrpci = '0' ) then + nxt_pci <= TURN_AR; + else + nxt_pci <= S_DATA1; + devselNX_n <= '0'; + end if; + + when S_DATA1 => + if ( acking = '1' ) then + nxt_pci <= S_DATA2; + devselNX_n <= '0'; + trdyNX_n <= '0'; + else + nxt_pci <= S_DATA1; + devselNX_n <= '0'; + end if; + + when S_DATA2 => + if ( frame_i = '1' and irdy_i = '0' ) then + nxt_pci <= TURN_AR; + else + nxt_pci <= S_DATA2; + devselNX_n <= '0'; + trdyNX_n <= '0'; + end if; + + when TURN_AR => + if ( frame_i = '1' ) then + nxt_pci <= PCIIDLE; + else + nxt_pci <= TURN_AR; + end if; + + end case; + + end process PCIFSM_COMB; + + + --+-------------------------------------------------------------+ + --| FSM control signals | + --+-------------------------------------------------------------+ + + adrpci <= adrmem_i or adrcfg_i; + acking <= '1' when ( wb_ack_i = '1' or wb_err_i = '1' ) or ( adrcfg_i = '1' and irdy_i = '0') + else '0'; + + + --+-------------------------------------------------------------+ + --| FSM derived Control signals | + --+-------------------------------------------------------------+ + idle <= '1' when ( pst_pci = PCIIDLE ) else '0'; + sdata1 <= '1' when ( pst_pci = S_DATA1 ) else '0'; + sdata2 <= '1' when ( pst_pci = S_DATA2 ) else '0'; + idleNX <= '1' when ( nxt_pci = PCIIDLE ) else '0'; + sdata1NX <= '1' when ( nxt_pci = S_DATA1 ) else '0'; + sdata2NX <= '1' when ( nxt_pci = S_DATA2 ) else '0'; + turnarNX <= '1' when ( nxt_pci = TURN_AR ) else '0'; + + + + --+-------------------------------------------------------------+ + --| PCI Data Output Enable | + --+-------------------------------------------------------------+ + + PCIDOE_P: process( nrst_i, clk_i, cmd_i(0), sdata1NX, turnarNX ) + begin + + if ( nrst_i = '0' ) then + pcidOE <= '0'; + elsif ( rising_edge(clk_i) ) then + + if ( sdata1NX = '1' and cmd_i(0) = '0' ) then + pcidOE <= '1'; + elsif ( turnarNX = '1' ) then + pcidOE <= '0'; + end if; + + end if; + + end process PCIDOE_P; + + pcidOE_o <= pcidOE; + + + --+-------------------------------------------------------------+ + --| PAR Output Enable | + --| PCI Read data phase | + --| PAR is valid 1 cicle after data is valid | + --+-------------------------------------------------------------+ + + PAROE_P: process( nrst_i, clk_i, cmd_i(0), sdata2NX, turnarNX ) + begin + + if ( nrst_i = '0' ) then + parOE_o <= '0'; + elsif ( rising_edge(clk_i) ) then + + if ( ( sdata2NX = '1' or turnarNX = '1' ) and cmd_i(0) = '0' ) then + parOE_o <= '1'; + else + parOE_o <= '0'; + end if; + + end if; + + end process PAROE_P; + + + --+-------------------------------------------------------------+ + --| Target s/t/s signals OE control | + --+-------------------------------------------------------------+ + +-- targOE <= '1' when ( idle = '0' and adrpci = '1' ) else '0'; + TARGOE_P: process( nrst_i, clk_i, sdata1NX, idleNX ) + begin + + if ( nrst_i = '0' ) then + targOE <= '0'; + elsif ( rising_edge(clk_i) ) then + + if ( sdata1NX = '1' ) then + targOE <= '1'; + elsif ( idleNX = '1' ) then + targOE <= '0'; + end if; + + end if; + + end process TARGOE_P; + + + --+-------------------------------------------------------------------------+ + --| WHISBONE outs | + --+-------------------------------------------------------------------------+ + + wb_cyc_o <= '1' when ( adrmem_i = '1' and sdata1 = '1' ) else '0'; + wb_stb_o <= '1' when ( adrmem_i = '1' and sdata1 = '1' and irdy_i = '0' ) else '0'; + + -- PCI(Little endian) to WB(Big endian) + wb_sel_o(1) <= (not cbe_i(0)) or (not cbe_i(2)); + wb_sel_o(0) <= (not cbe_i(1)) or (not cbe_i(3)); + -- + wb_we_o <= cmd_i(0); + + + --+-------------------------------------------------------------------------+ + --| Syncronized PCI outs | + --+-------------------------------------------------------------------------+ + + PCISIG: process( nrst_i, clk_i, devselNX_n, trdyNX_n) + begin + + if( nrst_i = '0' ) then + devsel <= '1'; + trdy <= '1'; + elsif( rising_edge(clk_i) ) then + + devsel <= devselNX_n; + trdy <= trdyNX_n; + + end if; + + end process PCISIG; + + devsel_o <= devsel when ( targOE = '1' ) else 'Z'; + trdy_o <= trdy when ( targOE = '1' ) else 'Z'; + + + --+-------------------------------------------------------------------------+ + --| Other outs | + --+-------------------------------------------------------------------------+ + + -- rd/wr Configuration Space Registers + wrcfg_o <= '1' when ( adrcfg_i = '1' and cmd_i(0) = '1' and sdata2 = '1' ) else '0'; + rdcfg <= '1' when ( adrcfg_i = '1' and cmd_i(0) = '0' and ( sdata1 = '1' or sdata2 = '1' ) ) else '0'; + rdcfg_o <= rdcfg; + + -- LoaD enable signals + pciadrLD_o <= not frame_i; + wbdatLD_o <= wb_ack_i; + + -- Mux control signals + wbrgdMX_o <= not rdcfg; + wbd16MX_o <= '1' when ( cbe_i(3) = '0' or cbe_i(2) = '0' ) else '0'; + + --+-------------------------------------------------------------------------+ + --| debug outs | + --+-------------------------------------------------------------------------+ + + process (nrst_i, clk_i) + begin + if ( nrst_i = '0' ) then + debug_init <= '0'; + elsif clk_i'event and clk_i = '1' then + if devsel = '0' then + debug_init <= '1'; + end if; + end if; + end process; + + process (nrst_i, clk_i) + begin + if ( nrst_i = '0' ) then + debug_access <= '0'; + elsif clk_i'event and clk_i = '1' then + if wb_stb_o = '1' then + debug_access <= '1'; + end if; + end if; + end process; + +end rtl; Index: raggedstone/trunk/source/test.v =================================================================== --- raggedstone/trunk/source/test.v (nonexistent) +++ raggedstone/trunk/source/test.v (revision 10) @@ -0,0 +1,14 @@ +/* +`define PCIIDLE 1'h0; +`define B_BUSY 1'h1; +`define S_DATA1 1'h2; +`define S_DATA2 1'h3; +`define TURN_AR 1'h4; +*/ + +paramater PCIIDLE = 1'h0; +paramater B_BUSY = 1'h1; +paramater S_DATA1 = 1'h2; +paramater S_DATA2 = 1'h3; +paramater TURN_AR = 1'h4; + Index: raggedstone/trunk/source/pcipargen.vhd =================================================================== --- raggedstone/trunk/source/pcipargen.vhd (nonexistent) +++ raggedstone/trunk/source/pcipargen.vhd (revision 10) @@ -0,0 +1,144 @@ +--+-------------------------------------------------------------------------------------------------+ +--| | +--| File: pcipargen.vhd | +--| | +--| Project: pci32tlite_oc | +--| | +--| Description: PCI Parity Generator. | +--| PCI Target generates PAR in the data phase of a read cycle. The 1's sum on AD, | +--| CBE and PAR is even. | +--| | +--+-------------------------------------------------------------------------------------------------+ +--| | +--| Revision history : | +--| Date Version Author Description | +--| 2005-05-13 R00A00 PAU First alfa revision (eng) | +--| | +--| To do: | +--| | +--+-------------------------------------------------------------------------------------------------+ +--+-----------------------------------------------------------------+ +--| | +--| Copyright (C) 2005 Peio Azkarate, peio@opencores.org | +--| | +--| This source file may be used and distributed without | +--| restriction provided that this copyright statement is not | +--| removed from the file and that any derivative work contains | +--| the original copyright notice and the associated disclaimer. | +--| | +--| This source file is free software; you can redistribute it | +--| and/or modify it under the terms of the GNU Lesser General | +--| Public License as published by the Free Software Foundation; | +--| either version 2.1 of the License, or (at your option) any | +--| later version. | +--| | +--| This source is distributed in the hope that it will be | +--| useful, but WITHOUT ANY WARRANTY; without even the implied | +--| warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR | +--| PURPOSE. See the GNU Lesser General Public License for more | +--| details. | +--| | +--| You should have received a copy of the GNU Lesser General | +--| Public License along with this source; if not, download it | +--| from http://www.opencores.org/lgpl.shtml | +--| | +--+-----------------------------------------------------------------+ + + +--+-----------------------------------------------------------------------------+ +--| LIBRARIES | +--+-----------------------------------------------------------------------------+ + +library ieee; +use ieee.std_logic_1164.all; + + + +--+-----------------------------------------------------------------------------+ +--| ENTITY | +--+-----------------------------------------------------------------------------+ + +entity pcipargen is +port ( + + clk_i : in std_logic; + pcidatout_i : in std_logic_vector(31 downto 0); + cbe_i : in std_logic_vector(3 downto 0); + parOE_i : in std_logic; + par_o : out std_logic + +); +end pcipargen; + + +architecture rtl of pcipargen is + + +--+-----------------------------------------------------------------------------+ +--| COMPONENTS | +--+-----------------------------------------------------------------------------+ +--+-----------------------------------------------------------------------------+ +--| CONSTANTS | +--+-----------------------------------------------------------------------------+ +--+-----------------------------------------------------------------------------+ +--| SIGNALS | +--+-----------------------------------------------------------------------------+ + + signal d : std_logic_vector(31 downto 0); + signal pardat : std_logic; + signal parcbe : std_logic; + signal par : std_logic; + signal par_s : std_logic; + +component sync +port ( + clk : in std_logic; + d : in std_logic; + q : out std_logic +); +end component; + +component sync2 +port ( + clk : in std_logic; + d : in std_logic; + q : out std_logic +); +end component; + +begin + + + d <= pcidatout_i; + + + --+-------------------------------------------------------------------------+ + --| building parity | + --+-------------------------------------------------------------------------+ + + pardat <= d(0) xor d(1) xor d(2) xor d(3) xor d(4) xor d(5) xor d(6) xor d(7) xor + d(8) xor d(9) xor d(10) xor d(11) xor d(12) xor d(13) xor d(14) xor d(15) xor + d(16) xor d(17) xor d(18) xor d(19) xor d(20) xor d(21) xor d(22) xor d(23) xor + d(24) xor d(25) xor d(26) xor d(27) xor d(28) xor d(29) xor d(30) xor d(31); + + parcbe <= cbe_i(0) xor cbe_i(1) xor cbe_i(2) xor cbe_i(3); + + par <= pardat xor parcbe; + + -- u1: sync port map ( clk => clk_i, d => par, q => par_s ); + + u1: sync2 port map ( + clk => clk_i, + d => par, + q => par_s + ); + + + --+-------------------------------------------------------------------------+ + --| PAR | + --+-------------------------------------------------------------------------+ + + par_o <= par_s when ( parOE_i = '1' ) else 'Z'; + + +end rtl; Index: raggedstone/trunk/source/pcidec.v =================================================================== --- raggedstone/trunk/source/pcidec.v (nonexistent) +++ raggedstone/trunk/source/pcidec.v (revision 10) @@ -0,0 +1,67 @@ +// Copyright (C) 2005 Peio Azkarate, peio@opencores.org +// Copyright (C) 2006 Jeff Carr, jcarr@opencores.org +// Copyleft GPL v2 + +module pcidec_new (clk_i, nrst_i, ad_i, cbe_i, idsel_i, bar0_i, memEN_i, + pciadrLD_i, adrcfg_o, adrmem_o, adr_o, cmd_o); + + // General + input clk_i; + input nrst_i; + // pci + input [31:0] ad_i; + input [3:0] cbe_i; + input idsel_i; + // control + input [31:25] bar0_i; + input memEN_i; + input pciadrLD_i; + output adrcfg_o; + output adrmem_o; + output [24:1] adr_o; + output [3:0] cmd_o; + + reg [31:0] adr; + reg [3:0] cmd; + reg idsel_s; + wire a1; + + //+-------------------------------------------------------------------------+ + //| Load PCI Signals | + //+-------------------------------------------------------------------------+ + + always @( negedge nrst_i or posedge clk_i ) + begin + if( nrst_i == 0 ) + begin + adr <= 23'b1111_1111_1111_1111_1111_111; + cmd <= 3'b111; + idsel_s <= 1'b0; + end + else + if ( pciadrLD_i == 1 ) + begin + adr <= ad_i; + cmd <= cbe_i; + idsel_s <= idsel_i; + end + end + + assign adrmem_o = ( + ( memEN_i == 1'b1 ) && + ( adr [31:25] == bar0_i ) && + ( adr [1:0] == 2'b00 ) && + ( cmd [3:1] == 3'b011 ) + ) ? 1'b1 : 1'b0; + + assign adrcfg_o = ( + ( idsel_s == 1'b1 ) && + ( adr [1:0] == 2'b00 ) && + ( cmd [3:1] == 3'b101 ) + ) ? 1'b1 : 1'b0; + + assign a1 = ~ ( cbe_i [3] && cbe_i [2] ); + assign adr_o = {adr [24:2], a1}; + assign cmd_o = cmd; + +endmodule Index: raggedstone/trunk/source/generate_pci32tlite/gen_pci32tlite.pl =================================================================== --- raggedstone/trunk/source/generate_pci32tlite/gen_pci32tlite.pl (nonexistent) +++ raggedstone/trunk/source/generate_pci32tlite/gen_pci32tlite.pl (revision 10) @@ -0,0 +1,31 @@ +#!/usr/bin/perl +# + +$TOTAL = 42; + +system ("cat pci32tlite.vhd.part1"); + +foreach $i ( 1 .. $TOTAL ) { + my $j = 12345670 + $i; + my $end = ";"; + $end = "" if $i eq $TOTAL; + print "\t\tjcarr$i" . "ID : std_logic_vector(31 downto 0) := x\"$j\"$end\n"; +} + +system ("cat pci32tlite.vhd.part2"); + +foreach $i ( 1 .. $TOTAL ) { + my $end = ";"; + $end = "" if $i eq $TOTAL; + print "\t\tjcarr$i" . "ID : std_logic_vector(31 downto 0)$end\n"; +} + +system ("cat pci32tlite.vhd.part3"); + +foreach $i ( 1 .. $TOTAL ) { + my $end = ","; + $end = "" if $i eq $TOTAL; + print "\t\tjcarr$i" . "ID => jcarr$i" . "ID$end\n"; +} + +system ("cat pci32tlite.vhd.part4");

raggedstone/trunk/source/generate_pci32tlite/gen_pci32tlite.pl Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: raggedstone/trunk/source/generate_pci32tlite/pci32tlite.vhd.part1 =================================================================== --- raggedstone/trunk/source/generate_pci32tlite/pci32tlite.vhd.part1 (nonexistent) +++ raggedstone/trunk/source/generate_pci32tlite/pci32tlite.vhd.part1 (revision 10) @@ -0,0 +1,75 @@ +--+-------------------------------------------------------------------------------------------------+ +--| | +--| File: pci32tlite.vhd | +--| | +--| Components: pcidec_new.vhd | +--| pciwbsequ.vhd | +--| pcidmux.vhd | +--| pciregs.vhd | +--| pcipargen.vhd | +--| -- Libs -- | +--| ona.vhd | +--| | +--| Description: TARGET PCI : | +--| | +--| * PCI Target 32 Bits | +--| * BAR0 32MByte address space | +--| * Whisbone compatible: D16, 32MB address space | +--| | +--+-------------------------------------------------------------------------------------------------+ +--| | +--| Revision history : | +--| Date Version Author Description | +--| 2005-05-13 R00A00 PAU First alfa revision (eng) | +--| 2006-01-05 R00B00 MS inverted reset nres | +--| and added debug signals debug_init and debug_access | | +--| | +--| To do: | +--| | +--+-------------------------------------------------------------------------------------------------+ +--+-----------------------------------------------------------------+ +--| | +--| Copyright (C) 2005 Peio Azkarate, peio@opencores.org | +--| | +--| This source file may be used and distributed without | +--| restriction provided that this copyright statement is not | +--| removed from the file and that any derivative work contains | +--| the original copyright notice and the associated disclaimer. | +--| | +--| This source file is free software; you can redistribute it | +--| and/or modify it under the terms of the GNU Lesser General | +--| Public License as published by the Free Software Foundation; | +--| either version 2.1 of the License, or (at your option) any | +--| later version. | +--| | +--| This source is distributed in the hope that it will be | +--| useful, but WITHOUT ANY WARRANTY; without even the implied | +--| warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR | +--| PURPOSE. See the GNU Lesser General Public License for more | +--| details. | +--| | +--| You should have received a copy of the GNU Lesser General | +--| Public License along with this source; if not, download it | +--| from http://www.opencores.org/lgpl.shtml | +--| | +--+-----------------------------------------------------------------+ + +--+-----------------------------------------------------------------------------+ +--| LIBRARIES | +--+-----------------------------------------------------------------------------+ + +library ieee; +use ieee.std_logic_1164.all; + +--+-----------------------------------------------------------------------------+ +--| ENTITY | +--+-----------------------------------------------------------------------------+ + +entity pci32tlite is +generic ( + + vendorID : std_logic_vector(15 downto 0) := x"10EE"; + deviceID : std_logic_vector(15 downto 0) := x"0100"; + revisionID : std_logic_vector(7 downto 0) := x"37"; + subsystemID : std_logic_vector(15 downto 0) := x"1558"; + subsystemvID : std_logic_vector(15 downto 0) := x"0480"; Index: raggedstone/trunk/source/generate_pci32tlite/pci32tlite.vhd.part2 =================================================================== --- raggedstone/trunk/source/generate_pci32tlite/pci32tlite.vhd.part2 (nonexistent) +++ raggedstone/trunk/source/generate_pci32tlite/pci32tlite.vhd.part2 (revision 10) @@ -0,0 +1,142 @@ + +); +port ( + + -- General + clk33 : in std_logic; + nrst : in std_logic; + + -- PCI target 32bits + ad : inout std_logic_vector(31 downto 0); + cbe : in std_logic_vector(3 downto 0); + par : out std_logic; + frame : in std_logic; + irdy : in std_logic; + trdy : out std_logic; + devsel : out std_logic; + stop : out std_logic; + idsel : in std_logic; + perr : out std_logic; + serr : out std_logic; + intb : out std_logic; + + -- Master whisbone + wb_adr_o : out std_logic_vector(24 downto 1); + wb_dat_i : in std_logic_vector(15 downto 0); + wb_dat_o : out std_logic_vector(15 downto 0); + wb_sel_o : out std_logic_vector(1 downto 0); + wb_we_o : out std_logic; + wb_stb_o : inout std_logic; + wb_cyc_o : out std_logic; + wb_ack_i : in std_logic; + wb_err_i : in std_logic; + wb_int_i : in std_logic; + + -- debug signals + debug_init : out std_logic; + debug_access : out std_logic + +); +end pci32tlite; + + +--+-----------------------------------------------------------------------------+ +--| ARCHITECTURE | +--+-----------------------------------------------------------------------------+ + +architecture rtl of pci32tlite is + + +--+-----------------------------------------------------------------------------+ +--| COMPONENTS | +--+-----------------------------------------------------------------------------+ + + + component pcidec_new + port ( + + clk_i : in std_logic; + nrst_i : in std_logic; + -- + ad_i : in std_logic_vector(31 downto 0); + cbe_i : in std_logic_vector(3 downto 0); + idsel_i : in std_logic; + bar0_i : in std_logic_vector(31 downto 25); + memEN_i : in std_logic; + pciadrLD_i : in std_logic; + adrcfg_o : out std_logic; + adrmem_o : out std_logic; + adr_o : out std_logic_vector(24 downto 1); + cmd_o : out std_logic_vector(3 downto 0) + + ); + end component; + + + component pciwbsequ + port ( + + -- General + clk_i : in std_logic; + nrst_i : in std_logic; + -- pci + cmd_i : in std_logic_vector(3 downto 0); + cbe_i : in std_logic_vector(3 downto 0); + frame_i : in std_logic; + irdy_i : in std_logic; + devsel_o : out std_logic; + trdy_o : out std_logic; + -- control + adrcfg_i : in std_logic; + adrmem_i : in std_logic; + pciadrLD_o : out std_logic; + pcidOE_o : out std_logic; + parOE_o : out std_logic; + wbdatLD_o : out std_logic; + wbrgdMX_o : out std_logic; + wbd16MX_o : out std_logic; + wrcfg_o : out std_logic; + rdcfg_o : out std_logic; + -- whisbone + wb_sel_o : out std_logic_vector(1 downto 0); + wb_we_o : out std_logic; + wb_stb_o : inout std_logic; + wb_cyc_o : out std_logic; + wb_ack_i : in std_logic; + wb_err_i : in std_logic; + -- debug signals + debug_init : out std_logic; + debug_access : out std_logic + ); + end component; + + + component pcidmux + port ( + + clk_i : in std_logic; + nrst_i : in std_logic; + -- + d_io : inout std_logic_vector(31 downto 0); + pcidatout_o : out std_logic_vector(31 downto 0); + pcidOE_i : in std_logic; + wbdatLD_i : in std_logic; + wbrgdMX_i : in std_logic; + wbd16MX_i : in std_logic; + wb_dat_i : in std_logic_vector(15 downto 0); + wb_dat_o : out std_logic_vector(15 downto 0); + rg_dat_i : in std_logic_vector(31 downto 0); + rg_dat_o : out std_logic_vector(31 downto 0) + + ); + end component; + + + component pciregs + generic ( + + vendorID : std_logic_vector(15 downto 0); + deviceID : std_logic_vector(15 downto 0); + revisionID : std_logic_vector(7 downto 0); + subsystemID : std_logic_vector(15 downto 0); + subsystemvID : std_logic_vector(15 downto 0); Index: raggedstone/trunk/source/generate_pci32tlite/pci32tlite.vhd.part3 =================================================================== --- raggedstone/trunk/source/generate_pci32tlite/pci32tlite.vhd.part3 (nonexistent) +++ raggedstone/trunk/source/generate_pci32tlite/pci32tlite.vhd.part3 (revision 10) @@ -0,0 +1,176 @@ + + ); + port ( + + clk_i : in std_logic; + nrst_i : in std_logic; + -- + adr_i : in std_logic_vector(7 downto 2); + cbe_i : in std_logic_vector(3 downto 0); + dat_i : in std_logic_vector(31 downto 0); + dat_o : out std_logic_vector(31 downto 0); + wrcfg_i : in std_logic; + rdcfg_i : in std_logic; + perr_i : in std_logic; + serr_i : in std_logic; + tabort_i : in std_logic; + bar0_o : out std_logic_vector(31 downto 25); + perrEN_o : out std_logic; + serrEN_o : out std_logic; + memEN_o : out std_logic + + ); + end component; + + + component pcipargen + port ( + + clk_i : in std_logic; + pcidatout_i : in std_logic_vector(31 downto 0); + cbe_i : in std_logic_vector(3 downto 0); + parOE_i : in std_logic; + par_o : out std_logic + + ); + end component; + + +--+-----------------------------------------------------------------------------+ +--| CONSTANTS | +--+-----------------------------------------------------------------------------+ +--+-----------------------------------------------------------------------------+ +--| SIGNALS | +--+-----------------------------------------------------------------------------+ + + signal bar0 : std_logic_vector(31 downto 25); + signal memEN : std_logic; + signal pciadrLD : std_logic; + signal adrcfg : std_logic; + signal adrmem : std_logic; + signal adr : std_logic_vector(24 downto 1); + signal cmd : std_logic_vector(3 downto 0); + signal pcidOE : std_logic; + signal parOE : std_logic; + signal wbdatLD : std_logic; + signal wbrgdMX : std_logic; + signal wbd16MX : std_logic; + signal wrcfg : std_logic; + signal rdcfg : std_logic; + signal pcidatread : std_logic_vector(31 downto 0); + signal pcidatwrite : std_logic_vector(31 downto 0); + signal pcidatout : std_logic_vector(31 downto 0); + signal parerr : std_logic; + signal syserr : std_logic; + signal tabort : std_logic; + signal perrEN : std_logic; + signal serrEN : std_logic; + +begin + + + --+-------------------------------------------------------------------------+ + --| Component instances | + --+-------------------------------------------------------------------------+ + + --+-----------------------------------------+ + --| PCI decoder | + --+-----------------------------------------+ + + u1: component pcidec_new + port map ( + + clk_i => clk33, + nrst_i => nrst, + -- + ad_i => ad, + cbe_i => cbe, + idsel_i => idsel, + bar0_i => bar0, + memEN_i => memEN, + pciadrLD_i => pciadrLD, + adrcfg_o => adrcfg, + adrmem_o => adrmem, + adr_o => adr, + cmd_o => cmd + + ); + + + --+-----------------------------------------+ + --| PCI-WB Sequencer | + --+-----------------------------------------+ + + u2: component pciwbsequ + port map ( + + -- General + clk_i => clk33, + nrst_i => nrst, + -- pci + cmd_i => cmd, + cbe_i => cbe, + frame_i => frame, + irdy_i => irdy, + devsel_o => devsel, + trdy_o => trdy, + -- control + adrcfg_i => adrcfg, + adrmem_i => adrmem, + pciadrLD_o => pciadrLD, + pcidOE_o => pcidOE, + parOE_o => parOE, + wbdatLD_o => wbdatLD, + wbrgdMX_o => wbrgdMX, + wbd16MX_o => wbd16MX, + wrcfg_o => wrcfg, + rdcfg_o => rdcfg, + -- whisbone + wb_sel_o => wb_sel_o, + wb_we_o => wb_we_o, + wb_stb_o => wb_stb_o, + wb_cyc_o => wb_cyc_o, + wb_ack_i => wb_ack_i, + wb_err_i => wb_err_i, + -- debug signals + debug_init => debug_init, + debug_access => debug_access + ); + + + --+-----------------------------------------+ + --| PCI-wb datamultiplexer | + --+-----------------------------------------+ + + u3: component pcidmux + port map ( + + clk_i => clk33, + nrst_i => nrst, + -- + d_io => ad, + pcidatout_o => pcidatout, + pcidOE_i => pcidOE, + wbdatLD_i => wbdatLD, + wbrgdMX_i => wbrgdMX, + wbd16MX_i => wbd16MX, + wb_dat_i => wb_dat_i, + wb_dat_o => wb_dat_o, + rg_dat_i => pcidatread, + rg_dat_o => pcidatwrite + + ); + + + --+-----------------------------------------+ + --| PCI registers | + --+-----------------------------------------+ + + u4: component pciregs + generic map ( + + vendorID => vendorID, + deviceID => deviceID, + revisionID => revisionID, + subsystemID => subsystemID, + subsystemvID => subsystemvID, Index: raggedstone/trunk/source/generate_pci32tlite/new_pci32tlite.vhd =================================================================== --- raggedstone/trunk/source/generate_pci32tlite/new_pci32tlite.vhd (nonexistent) +++ raggedstone/trunk/source/generate_pci32tlite/new_pci32tlite.vhd (revision 10) @@ -0,0 +1,590 @@ +--+-------------------------------------------------------------------------------------------------+ +--| | +--| File: pci32tlite.vhd | +--| | +--| Components: pcidec_new.vhd | +--| pciwbsequ.vhd | +--| pcidmux.vhd | +--| pciregs.vhd | +--| pcipargen.vhd | +--| -- Libs -- | +--| ona.vhd | +--| | +--| Description: TARGET PCI : | +--| | +--| * PCI Target 32 Bits | +--| * BAR0 32MByte address space | +--| * Whisbone compatible: D16, 32MB address space | +--| | +--+-------------------------------------------------------------------------------------------------+ +--| | +--| Revision history : | +--| Date Version Author Description | +--| 2005-05-13 R00A00 PAU First alfa revision (eng) | +--| 2006-01-05 R00B00 MS inverted reset nres | +--| and added debug signals debug_init and debug_access | | +--| | +--| To do: | +--| | +--+-------------------------------------------------------------------------------------------------+ +--+-----------------------------------------------------------------+ +--| | +--| Copyright (C) 2005 Peio Azkarate, peio@opencores.org | +--| | +--| This source file may be used and distributed without | +--| restriction provided that this copyright statement is not | +--| removed from the file and that any derivative work contains | +--| the original copyright notice and the associated disclaimer. | +--| | +--| This source file is free software; you can redistribute it | +--| and/or modify it under the terms of the GNU Lesser General | +--| Public License as published by the Free Software Foundation; | +--| either version 2.1 of the License, or (at your option) any | +--| later version. | +--| | +--| This source is distributed in the hope that it will be | +--| useful, but WITHOUT ANY WARRANTY; without even the implied | +--| warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR | +--| PURPOSE. See the GNU Lesser General Public License for more | +--| details. | +--| | +--| You should have received a copy of the GNU Lesser General | +--| Public License along with this source; if not, download it | +--| from http://www.opencores.org/lgpl.shtml | +--| | +--+-----------------------------------------------------------------+ + +--+-----------------------------------------------------------------------------+ +--| LIBRARIES | +--+-----------------------------------------------------------------------------+ + +library ieee; +use ieee.std_logic_1164.all; + +--+-----------------------------------------------------------------------------+ +--| ENTITY | +--+-----------------------------------------------------------------------------+ + +entity pci32tlite is +generic ( + + vendorID : std_logic_vector(15 downto 0) := x"10EE"; + deviceID : std_logic_vector(15 downto 0) := x"0100"; + revisionID : std_logic_vector(7 downto 0) := x"37"; + subsystemID : std_logic_vector(15 downto 0) := x"1558"; + subsystemvID : std_logic_vector(15 downto 0) := x"0480"; + jcarr1ID : std_logic_vector(31 downto 0) := x"12345671"; + jcarr2ID : std_logic_vector(31 downto 0) := x"12345672"; + jcarr3ID : std_logic_vector(31 downto 0) := x"12345673"; + jcarr4ID : std_logic_vector(31 downto 0) := x"12345674"; + jcarr5ID : std_logic_vector(31 downto 0) := x"12345675"; + jcarr6ID : std_logic_vector(31 downto 0) := x"12345676"; + jcarr7ID : std_logic_vector(31 downto 0) := x"12345677"; + jcarr8ID : std_logic_vector(31 downto 0) := x"12345678"; + jcarr9ID : std_logic_vector(31 downto 0) := x"12345679"; + jcarr10ID : std_logic_vector(31 downto 0) := x"12345680"; + jcarr11ID : std_logic_vector(31 downto 0) := x"12345681"; + jcarr12ID : std_logic_vector(31 downto 0) := x"12345682"; + jcarr13ID : std_logic_vector(31 downto 0) := x"12345683"; + jcarr14ID : std_logic_vector(31 downto 0) := x"12345684"; + jcarr15ID : std_logic_vector(31 downto 0) := x"12345685"; + jcarr16ID : std_logic_vector(31 downto 0) := x"12345686"; + jcarr17ID : std_logic_vector(31 downto 0) := x"12345687"; + jcarr18ID : std_logic_vector(31 downto 0) := x"12345688"; + jcarr19ID : std_logic_vector(31 downto 0) := x"12345689"; + jcarr20ID : std_logic_vector(31 downto 0) := x"12345690"; + jcarr21ID : std_logic_vector(31 downto 0) := x"12345691"; + jcarr22ID : std_logic_vector(31 downto 0) := x"12345692"; + jcarr23ID : std_logic_vector(31 downto 0) := x"12345693"; + jcarr24ID : std_logic_vector(31 downto 0) := x"12345694"; + jcarr25ID : std_logic_vector(31 downto 0) := x"12345695"; + jcarr26ID : std_logic_vector(31 downto 0) := x"12345696"; + jcarr27ID : std_logic_vector(31 downto 0) := x"12345697"; + jcarr28ID : std_logic_vector(31 downto 0) := x"12345698"; + jcarr29ID : std_logic_vector(31 downto 0) := x"12345699"; + jcarr30ID : std_logic_vector(31 downto 0) := x"12345700"; + jcarr31ID : std_logic_vector(31 downto 0) := x"12345701"; + jcarr32ID : std_logic_vector(31 downto 0) := x"12345702"; + jcarr33ID : std_logic_vector(31 downto 0) := x"12345703"; + jcarr34ID : std_logic_vector(31 downto 0) := x"12345704"; + jcarr35ID : std_logic_vector(31 downto 0) := x"12345705"; + jcarr36ID : std_logic_vector(31 downto 0) := x"12345706"; + jcarr37ID : std_logic_vector(31 downto 0) := x"12345707"; + jcarr38ID : std_logic_vector(31 downto 0) := x"12345708"; + jcarr39ID : std_logic_vector(31 downto 0) := x"12345709"; + jcarr40ID : std_logic_vector(31 downto 0) := x"12345710"; + jcarr41ID : std_logic_vector(31 downto 0) := x"12345711"; + jcarr42ID : std_logic_vector(31 downto 0) := x"12345712" + +); +port ( + + -- General + clk33 : in std_logic; + nrst : in std_logic; + + -- PCI target 32bits + ad : inout std_logic_vector(31 downto 0); + cbe : in std_logic_vector(3 downto 0); + par : out std_logic; + frame : in std_logic; + irdy : in std_logic; + trdy : out std_logic; + devsel : out std_logic; + stop : out std_logic; + idsel : in std_logic; + perr : out std_logic; + serr : out std_logic; + intb : out std_logic; + + -- Master whisbone + wb_adr_o : out std_logic_vector(24 downto 1); + wb_dat_i : in std_logic_vector(15 downto 0); + wb_dat_o : out std_logic_vector(15 downto 0); + wb_sel_o : out std_logic_vector(1 downto 0); + wb_we_o : out std_logic; + wb_stb_o : inout std_logic; + wb_cyc_o : out std_logic; + wb_ack_i : in std_logic; + wb_err_i : in std_logic; + wb_int_i : in std_logic; + + -- debug signals + debug_init : out std_logic; + debug_access : out std_logic + +); +end pci32tlite; + + +--+-----------------------------------------------------------------------------+ +--| ARCHITECTURE | +--+-----------------------------------------------------------------------------+ + +architecture rtl of pci32tlite is + + +--+-----------------------------------------------------------------------------+ +--| COMPONENTS | +--+-----------------------------------------------------------------------------+ + + + component pcidec_new + port ( + + clk_i : in std_logic; + nrst_i : in std_logic; + -- + ad_i : in std_logic_vector(31 downto 0); + cbe_i : in std_logic_vector(3 downto 0); + idsel_i : in std_logic; + bar0_i : in std_logic_vector(31 downto 25); + memEN_i : in std_logic; + pciadrLD_i : in std_logic; + adrcfg_o : out std_logic; + adrmem_o : out std_logic; + adr_o : out std_logic_vector(24 downto 1); + cmd_o : out std_logic_vector(3 downto 0) + + ); + end component; + + + component pciwbsequ + port ( + + -- General + clk_i : in std_logic; + nrst_i : in std_logic; + -- pci + cmd_i : in std_logic_vector(3 downto 0); + cbe_i : in std_logic_vector(3 downto 0); + frame_i : in std_logic; + irdy_i : in std_logic; + devsel_o : out std_logic; + trdy_o : out std_logic; + -- control + adrcfg_i : in std_logic; + adrmem_i : in std_logic; + pciadrLD_o : out std_logic; + pcidOE_o : out std_logic; + parOE_o : out std_logic; + wbdatLD_o : out std_logic; + wbrgdMX_o : out std_logic; + wbd16MX_o : out std_logic; + wrcfg_o : out std_logic; + rdcfg_o : out std_logic; + -- whisbone + wb_sel_o : out std_logic_vector(1 downto 0); + wb_we_o : out std_logic; + wb_stb_o : inout std_logic; + wb_cyc_o : out std_logic; + wb_ack_i : in std_logic; + wb_err_i : in std_logic; + -- debug signals + debug_init : out std_logic; + debug_access : out std_logic + ); + end component; + + + component pcidmux + port ( + + clk_i : in std_logic; + nrst_i : in std_logic; + -- + d_io : inout std_logic_vector(31 downto 0); + pcidatout_o : out std_logic_vector(31 downto 0); + pcidOE_i : in std_logic; + wbdatLD_i : in std_logic; + wbrgdMX_i : in std_logic; + wbd16MX_i : in std_logic; + wb_dat_i : in std_logic_vector(15 downto 0); + wb_dat_o : out std_logic_vector(15 downto 0); + rg_dat_i : in std_logic_vector(31 downto 0); + rg_dat_o : out std_logic_vector(31 downto 0) + + ); + end component; + + + component pciregs + generic ( + + vendorID : std_logic_vector(15 downto 0); + deviceID : std_logic_vector(15 downto 0); + revisionID : std_logic_vector(7 downto 0); + subsystemID : std_logic_vector(15 downto 0); + subsystemvID : std_logic_vector(15 downto 0); + jcarr1ID : std_logic_vector(31 downto 0); + jcarr2ID : std_logic_vector(31 downto 0); + jcarr3ID : std_logic_vector(31 downto 0); + jcarr4ID : std_logic_vector(31 downto 0); + jcarr5ID : std_logic_vector(31 downto 0); + jcarr6ID : std_logic_vector(31 downto 0); + jcarr7ID : std_logic_vector(31 downto 0); + jcarr8ID : std_logic_vector(31 downto 0); + jcarr9ID : std_logic_vector(31 downto 0); + jcarr10ID : std_logic_vector(31 downto 0); + jcarr11ID : std_logic_vector(31 downto 0); + jcarr12ID : std_logic_vector(31 downto 0); + jcarr13ID : std_logic_vector(31 downto 0); + jcarr14ID : std_logic_vector(31 downto 0); + jcarr15ID : std_logic_vector(31 downto 0); + jcarr16ID : std_logic_vector(31 downto 0); + jcarr17ID : std_logic_vector(31 downto 0); + jcarr18ID : std_logic_vector(31 downto 0); + jcarr19ID : std_logic_vector(31 downto 0); + jcarr20ID : std_logic_vector(31 downto 0); + jcarr21ID : std_logic_vector(31 downto 0); + jcarr22ID : std_logic_vector(31 downto 0); + jcarr23ID : std_logic_vector(31 downto 0); + jcarr24ID : std_logic_vector(31 downto 0); + jcarr25ID : std_logic_vector(31 downto 0); + jcarr26ID : std_logic_vector(31 downto 0); + jcarr27ID : std_logic_vector(31 downto 0); + jcarr28ID : std_logic_vector(31 downto 0); + jcarr29ID : std_logic_vector(31 downto 0); + jcarr30ID : std_logic_vector(31 downto 0); + jcarr31ID : std_logic_vector(31 downto 0); + jcarr32ID : std_logic_vector(31 downto 0); + jcarr33ID : std_logic_vector(31 downto 0); + jcarr34ID : std_logic_vector(31 downto 0); + jcarr35ID : std_logic_vector(31 downto 0); + jcarr36ID : std_logic_vector(31 downto 0); + jcarr37ID : std_logic_vector(31 downto 0); + jcarr38ID : std_logic_vector(31 downto 0); + jcarr39ID : std_logic_vector(31 downto 0); + jcarr40ID : std_logic_vector(31 downto 0); + jcarr41ID : std_logic_vector(31 downto 0); + jcarr42ID : std_logic_vector(31 downto 0) + + ); + port ( + + clk_i : in std_logic; + nrst_i : in std_logic; + -- + adr_i : in std_logic_vector(7 downto 2); + cbe_i : in std_logic_vector(3 downto 0); + dat_i : in std_logic_vector(31 downto 0); + dat_o : out std_logic_vector(31 downto 0); + wrcfg_i : in std_logic; + rdcfg_i : in std_logic; + perr_i : in std_logic; + serr_i : in std_logic; + tabort_i : in std_logic; + bar0_o : out std_logic_vector(31 downto 25); + perrEN_o : out std_logic; + serrEN_o : out std_logic; + memEN_o : out std_logic + + ); + end component; + + + component pcipargen + port ( + + clk_i : in std_logic; + pcidatout_i : in std_logic_vector(31 downto 0); + cbe_i : in std_logic_vector(3 downto 0); + parOE_i : in std_logic; + par_o : out std_logic + + ); + end component; + + +--+-----------------------------------------------------------------------------+ +--| CONSTANTS | +--+-----------------------------------------------------------------------------+ +--+-----------------------------------------------------------------------------+ +--| SIGNALS | +--+-----------------------------------------------------------------------------+ + + signal bar0 : std_logic_vector(31 downto 25); + signal memEN : std_logic; + signal pciadrLD : std_logic; + signal adrcfg : std_logic; + signal adrmem : std_logic; + signal adr : std_logic_vector(24 downto 1); + signal cmd : std_logic_vector(3 downto 0); + signal pcidOE : std_logic; + signal parOE : std_logic; + signal wbdatLD : std_logic; + signal wbrgdMX : std_logic; + signal wbd16MX : std_logic; + signal wrcfg : std_logic; + signal rdcfg : std_logic; + signal pcidatread : std_logic_vector(31 downto 0); + signal pcidatwrite : std_logic_vector(31 downto 0); + signal pcidatout : std_logic_vector(31 downto 0); + signal parerr : std_logic; + signal syserr : std_logic; + signal tabort : std_logic; + signal perrEN : std_logic; + signal serrEN : std_logic; + +begin + + + --+-------------------------------------------------------------------------+ + --| Component instances | + --+-------------------------------------------------------------------------+ + + --+-----------------------------------------+ + --| PCI decoder | + --+-----------------------------------------+ + + u1: component pcidec_new + port map ( + + clk_i => clk33, + nrst_i => nrst, + -- + ad_i => ad, + cbe_i => cbe, + idsel_i => idsel, + bar0_i => bar0, + memEN_i => memEN, + pciadrLD_i => pciadrLD, + adrcfg_o => adrcfg, + adrmem_o => adrmem, + adr_o => adr, + cmd_o => cmd + + ); + + + --+-----------------------------------------+ + --| PCI-WB Sequencer | + --+-----------------------------------------+ + + u2: component pciwbsequ + port map ( + + -- General + clk_i => clk33, + nrst_i => nrst, + -- pci + cmd_i => cmd, + cbe_i => cbe, + frame_i => frame, + irdy_i => irdy, + devsel_o => devsel, + trdy_o => trdy, + -- control + adrcfg_i => adrcfg, + adrmem_i => adrmem, + pciadrLD_o => pciadrLD, + pcidOE_o => pcidOE, + parOE_o => parOE, + wbdatLD_o => wbdatLD, + wbrgdMX_o => wbrgdMX, + wbd16MX_o => wbd16MX, + wrcfg_o => wrcfg, + rdcfg_o => rdcfg, + -- whisbone + wb_sel_o => wb_sel_o, + wb_we_o => wb_we_o, + wb_stb_o => wb_stb_o, + wb_cyc_o => wb_cyc_o, + wb_ack_i => wb_ack_i, + wb_err_i => wb_err_i, + -- debug signals + debug_init => debug_init, + debug_access => debug_access + ); + + + --+-----------------------------------------+ + --| PCI-wb datamultiplexer | + --+-----------------------------------------+ + + u3: component pcidmux + port map ( + + clk_i => clk33, + nrst_i => nrst, + -- + d_io => ad, + pcidatout_o => pcidatout, + pcidOE_i => pcidOE, + wbdatLD_i => wbdatLD, + wbrgdMX_i => wbrgdMX, + wbd16MX_i => wbd16MX, + wb_dat_i => wb_dat_i, + wb_dat_o => wb_dat_o, + rg_dat_i => pcidatread, + rg_dat_o => pcidatwrite + + ); + + + --+-----------------------------------------+ + --| PCI registers | + --+-----------------------------------------+ + + u4: component pciregs + generic map ( + + vendorID => vendorID, + deviceID => deviceID, + revisionID => revisionID, + subsystemID => subsystemID, + subsystemvID => subsystemvID, + jcarr1ID => jcarr1ID, + jcarr2ID => jcarr2ID, + jcarr3ID => jcarr3ID, + jcarr4ID => jcarr4ID, + jcarr5ID => jcarr5ID, + jcarr6ID => jcarr6ID, + jcarr7ID => jcarr7ID, + jcarr8ID => jcarr8ID, + jcarr9ID => jcarr9ID, + jcarr10ID => jcarr10ID, + jcarr11ID => jcarr11ID, + jcarr12ID => jcarr12ID, + jcarr13ID => jcarr13ID, + jcarr14ID => jcarr14ID, + jcarr15ID => jcarr15ID, + jcarr16ID => jcarr16ID, + jcarr17ID => jcarr17ID, + jcarr18ID => jcarr18ID, + jcarr19ID => jcarr19ID, + jcarr20ID => jcarr20ID, + jcarr21ID => jcarr21ID, + jcarr22ID => jcarr22ID, + jcarr23ID => jcarr23ID, + jcarr24ID => jcarr24ID, + jcarr25ID => jcarr25ID, + jcarr26ID => jcarr26ID, + jcarr27ID => jcarr27ID, + jcarr28ID => jcarr28ID, + jcarr29ID => jcarr29ID, + jcarr30ID => jcarr30ID, + jcarr31ID => jcarr31ID, + jcarr32ID => jcarr32ID, + jcarr33ID => jcarr33ID, + jcarr34ID => jcarr34ID, + jcarr35ID => jcarr35ID, + jcarr36ID => jcarr36ID, + jcarr37ID => jcarr37ID, + jcarr38ID => jcarr38ID, + jcarr39ID => jcarr39ID, + jcarr40ID => jcarr40ID, + jcarr41ID => jcarr41ID, + jcarr42ID => jcarr42ID + + ) + port map ( + + clk_i => clk33, + nrst_i => nrst, + -- + adr_i => adr(7 downto 2), + cbe_i => cbe, + dat_i => pcidatwrite, + dat_o => pcidatread, + wrcfg_i => wrcfg, + rdcfg_i => rdcfg, + perr_i => parerr, + serr_i => syserr, + tabort_i => tabort, + bar0_o => bar0, + perrEN_o => perrEN, + serrEN_o => serrEN, + memEN_o => memEN + + ); + + --+-----------------------------------------+ + --| PCI Parity Gnerator | + --+-----------------------------------------+ + + u5: component pcipargen + port map ( + + clk_i => clk33, + pcidatout_i => pcidatout, + cbe_i => cbe, + parOE_i => parOE, + par_o => par + + ); + + + --+-----------------------------------------+ + --| Whisbone Address bus | + --+-----------------------------------------+ + + wb_adr_o <= adr; + + + --+-----------------------------------------+ + --| unimplemented | + --+-----------------------------------------+ + + parerr <= '0'; + syserr <= '0'; + tabort <= '0'; + + + --+-----------------------------------------+ + --| unused outputs | + --+-----------------------------------------+ + -- #stop: Curret TARGET indicates to Master stop current transaction + -- #perr: + -- #serr: + + perr <= 'Z'; + serr <= 'Z'; + stop <= 'Z'; + intb <= '0' when ( wb_int_i = '1' ) else 'Z'; + + +end rtl; + + Index: raggedstone/trunk/source/generate_pci32tlite/pci32tlite.vhd.part4 =================================================================== --- raggedstone/trunk/source/generate_pci32tlite/pci32tlite.vhd.part4 (nonexistent) +++ raggedstone/trunk/source/generate_pci32tlite/pci32tlite.vhd.part4 (revision 10) @@ -0,0 +1,71 @@ + + ) + port map ( + + clk_i => clk33, + nrst_i => nrst, + -- + adr_i => adr(7 downto 2), + cbe_i => cbe, + dat_i => pcidatwrite, + dat_o => pcidatread, + wrcfg_i => wrcfg, + rdcfg_i => rdcfg, + perr_i => parerr, + serr_i => syserr, + tabort_i => tabort, + bar0_o => bar0, + perrEN_o => perrEN, + serrEN_o => serrEN, + memEN_o => memEN + + ); + + --+-----------------------------------------+ + --| PCI Parity Gnerator | + --+-----------------------------------------+ + + u5: component pcipargen + port map ( + + clk_i => clk33, + pcidatout_i => pcidatout, + cbe_i => cbe, + parOE_i => parOE, + par_o => par + + ); + + + --+-----------------------------------------+ + --| Whisbone Address bus | + --+-----------------------------------------+ + + wb_adr_o <= adr; + + + --+-----------------------------------------+ + --| unimplemented | + --+-----------------------------------------+ + + parerr <= '0'; + syserr <= '0'; + tabort <= '0'; + + + --+-----------------------------------------+ + --| unused outputs | + --+-----------------------------------------+ + -- #stop: Curret TARGET indicates to Master stop current transaction + -- #perr: + -- #serr: + + perr <= 'Z'; + serr <= 'Z'; + stop <= 'Z'; + intb <= '0' when ( wb_int_i = '1' ) else 'Z'; + + +end rtl; + + Index: raggedstone/trunk/source/generate_pci32tlite/Makefile =================================================================== --- raggedstone/trunk/source/generate_pci32tlite/Makefile (nonexistent) +++ raggedstone/trunk/source/generate_pci32tlite/Makefile (revision 10) @@ -0,0 +1,4 @@ +all: + ./gen_pci32tlite.pl > new_pci32tlite.vhd + unix2dos new_pci32tlite.vhd + cp new_pci32tlite.vhd .. Index: raggedstone/trunk/source/pfs.v =================================================================== --- raggedstone/trunk/source/pfs.v (nonexistent) +++ raggedstone/trunk/source/pfs.v (revision 10) @@ -0,0 +1,11 @@ +module pfs2 (clk, a, b); + input clk; + input a; + output b; + reg b; + + always @(posedge clk) + begin + b <= a; + end +endmodule Index: raggedstone/trunk/source/vga_main.vhd =================================================================== --- raggedstone/trunk/source/vga_main.vhd (nonexistent) +++ raggedstone/trunk/source/vga_main.vhd (revision 10) @@ -0,0 +1,103 @@ +--------------------------------------------------------------------- +-- vga_main.vhd Demo VGA configuration module. +--------------------------------------------------------------------- +-- Author: Barron Barnett +-- Copyright 2004 Digilent, Inc. +--------------------------------------------------------------------- +-- +-- This project is compatible with Xilinx ISE or Xilinx WebPack tools. +-- +-- Inputs: +-- mclk - System Clock +-- Outputs: +-- hs - Horizontal Sync +-- vs - Vertical Sync +-- red - Red Output +-- grn - Green Output +-- blu - Blue Output +-- +-- This module creates a three line pattern on a vga display using a +-- a vertical refresh rate of 60Hz. This is done by dividing the +-- system clock in half and using that for the pixel clock. This in +-- turn drives the vertical sync when the horizontal sync has reached +-- its reset point. All data displayed is done by basic value +-- comparisons. +------------------------------------------------------------------------ +-- Revision History: +-- 07/01/2004(BarronB): created +------------------------------------------------------------------------ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + + +entity vgaController is + Port ( mclk : in std_logic; + hs : out std_logic; + vs : out std_logic; + red : out std_logic; + grn : out std_logic; + blu : out std_logic); +end vgaController; + +architecture Behavioral of vgaController is + + + constant hpixels : std_logic_vector(9 downto 0) := "1100100000"; --Value of pixels in a horizontal line + constant vlines : std_logic_vector(9 downto 0) := "1000001001"; --Number of horizontal lines in the display + + constant hbp : std_logic_vector(9 downto 0) := "0010010000"; --Horizontal back porch + constant hfp : std_logic_vector(9 downto 0) := "1100010000"; --Horizontal front porch + constant vbp : std_logic_vector(9 downto 0) := "0000011111"; --Vertical back porch + constant vfp : std_logic_vector(9 downto 0) := "0111111111"; --Vertical front porch + + signal hc, vc : std_logic_vector(9 downto 0); --These are the Horizontal and Vertical counters + signal clkdiv : std_logic; --Clock divider + signal vidon : std_logic; --Tells whether or not its ok to display data + signal vsenable : std_logic; --Enable for the Vertical counter + +begin + --This cuts the 50Mhz clock in half + process(mclk) + begin + if(mclk = '1' and mclk'EVENT) then + clkdiv <= not clkdiv; + end if; + end process; + + --Runs the horizontal counter + process(clkdiv) + begin + if(clkdiv = '1' and clkdiv'EVENT) then + if hc = hpixels then --If the counter has reached the end of pixel count + hc <= "0000000000"; --reset the counter + vsenable <= '1'; --Enable the vertical counter to increment + else + hc <= hc + 1; --Increment the horizontal counter + vsenable <= '0'; --Leave the vsenable off + end if; + end if; + end process; + + hs <= '1' when hc(9 downto 7) = "000" else '0'; --Horizontal Sync Pulse + + process(clkdiv) + begin + if(clkdiv = '1' and clkdiv'EVENT and vsenable = '1') then --Increment when enabled + if vc = vlines then --Reset when the number of lines is reached + vc <= "0000000000"; + else vc <= vc + 1; --Increment the vertical counter + end if; + end if; + end process; + + vs <= '1' when vc(9 downto 1) = "000000000" else '0'; --Vertical Sync Pulse + + red <= '1' when (hc = "1010101100" and vidon ='1') else '0'; --Red pixel on at a specific horizontal count + grn <= '1' when (hc = "0100000100" and vidon ='1') else '0'; --Green pixel on at a specific horizontal count + blu <= '1' when (vc = "0100100001" and vidon ='1') else '0'; --Blue pixel on at a specific vertical count + + vidon <= '1' when (((hc < hfp) and (hc > hbp)) or ((vc < vfp) and (vc > vbp))) else '0'; --Enable video out when within the porches + +end Behavioral; Index: raggedstone/trunk/source/wb_7seg.v =================================================================== --- raggedstone/trunk/source/wb_7seg.v (nonexistent) +++ raggedstone/trunk/source/wb_7seg.v (revision 10) @@ -0,0 +1,87 @@ +module wb_7seg_new (clk_i, nrst_i, wb_adr_i, wb_dat_o, wb_dat_i, wb_sel_i, wb_we_i, + wb_stb_i, wb_cyc_i, wb_ack_o, wb_err_o, wb_int_o, DISP_SEL, DISP_LED); + + input clk_i; + input nrst_i; + input [24:1] wb_adr_i; + output [15:0] wb_dat_o; + input [15:0] wb_dat_i; + input [1:0] wb_sel_i; + input wb_we_i; + input wb_stb_i; + input wb_cyc_i; + output wb_ack_o; + output wb_err_o; + output wb_int_o; + output reg [3:0] DISP_SEL; + output reg [6:0] DISP_LED; + + reg [15:0] data_reg; + reg [6:0] disp_cnt; + reg [3:0] disp_data; + wire [6:0] disp_data_led; + reg [3:0] disp_pos; + + always @(posedge clk_i or negedge nrst_i) + begin + if (nrst_i == 0) + data_reg <= 16'hABCD; + else + if (wb_stb_i && wb_we_i) + data_reg <= wb_dat_i; + end + + assign wb_ack_o = wb_stb_i; + assign wb_err_o = 1'b0; + assign wb_int_o = 1'b0; + assign wb_dat_o = data_reg; + + always @(posedge clk_i or negedge nrst_i) + begin + if (nrst_i == 0) + disp_cnt <= 7'b0000000; + else + disp_cnt <= disp_cnt + 1; + end + + always @(posedge clk_i or negedge nrst_i) + begin + if (nrst_i == 0) + disp_pos <= 4'b0010; + else + if (disp_cnt == 7'b1111111) + disp_pos <= {DISP_SEL[2] , DISP_SEL[1] , DISP_SEL[0] , DISP_SEL[3]}; + end + + always @(posedge clk_i or negedge nrst_i) + begin + if (nrst_i == 0) + disp_data <= 4'b0000; + else + case (DISP_SEL) + 4'b1000: disp_data <= data_reg[3:0]; + 4'b0100: disp_data <= data_reg[7:4]; + 4'b0010: disp_data <= data_reg[11:8]; + 4'b0001: disp_data <= data_reg[15:12]; + endcase + end + + disp_dec u0 (disp_data, disp_data_led); + + always @(posedge clk_i or negedge nrst_i) + begin + if (nrst_i == 0) + DISP_LED <= 7'b0000000; + else + DISP_LED <= disp_data_led; + end + + always @(posedge clk_i or negedge nrst_i) + begin + if (nrst_i == 0) + DISP_SEL <= 0; + else + DISP_SEL <= disp_pos; + end + +endmodule Index: raggedstone/trunk/source/top_pci_7seg.vhd =================================================================== --- raggedstone/trunk/source/top_pci_7seg.vhd (nonexistent) +++ raggedstone/trunk/source/top_pci_7seg.vhd (revision 10) @@ -0,0 +1,259 @@ +--+-------------------------------------------------------------------------------------------------+ +--| | +--| File: top.vhd | +--| | +--| Components: pci32lite.vhd | +--| pciwbsequ.vhd | +--| pcidmux.vhd | +--| pciregs.vhd | +--| pcipargen.vhd | +--| -- Libs -- | +--| ona.vhd | +--| | +--| Description: RS1 PCI Demo : (TOP) Main file. | +--| | +--| | +--| | +--+-------------------------------------------------------------------------------------------------+ +--| | +--| Revision history : | +--| Date Version Author Description | +--| | +--| | +--| To do: | +--| | +--+-------------------------------------------------------------------------------------------------+ + + +--+-----------------------------------------------------------------------------+ +--| LIBRARIES | +--+-----------------------------------------------------------------------------+ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +--+-----------------------------------------------------------------------------+ +--| ENTITY | +--+-----------------------------------------------------------------------------+ + +entity pci_7seg is +port ( + + -- General + PCI_CLK : in std_logic; + PCI_nRES : in std_logic; + + -- PCI target 32bits + PCI_AD : inout std_logic_vector(31 downto 0); + PCI_CBE : in std_logic_vector(3 downto 0); + PCI_PAR : out std_logic; + PCI_nFRAME : in std_logic; + PCI_nIRDY : in std_logic; + PCI_nTRDY : out std_logic; + PCI_nDEVSEL : out std_logic; + PCI_nSTOP : out std_logic; + PCI_IDSEL : in std_logic; + PCI_nPERR : out std_logic; + PCI_nSERR : out std_logic; + PCI_nINT : out std_logic; + + -- 7seg + DISP_SEL : inout std_logic_vector(3 downto 0); + DISP_LED : out std_logic_vector(6 downto 0); + + -- debug signals + LED_INIT : out std_logic; + LED_ACCESS : out std_logic; + LED_ALIVE : out std_logic; + + -- vga signals + hs : out std_logic; + vs : out std_logic; + red, grn, blu : out std_logic; + mclk : in std_logic + +); +end pci_7seg; + + +--+-----------------------------------------------------------------------------+ +--| ARCHITECTURE | +--+-----------------------------------------------------------------------------+ + +architecture pci_7seg_arch of pci_7seg is + + +--+-----------------------------------------------------------------------------+ +--| COMPONENTS | +--+-----------------------------------------------------------------------------+ + +component pci32tlite +port ( + + -- General + clk33 : in std_logic; + nrst : in std_logic; + + -- PCI target 32bits + ad : inout std_logic_vector(31 downto 0); + cbe : in std_logic_vector(3 downto 0); + par : out std_logic; + frame : in std_logic; + irdy : in std_logic; + trdy : out std_logic; + devsel : out std_logic; + stop : out std_logic; + idsel : in std_logic; + perr : out std_logic; + serr : out std_logic; + intb : out std_logic; + + -- Master whisbone + wb_adr_o : out std_logic_vector(24 downto 1); + wb_dat_i : in std_logic_vector(15 downto 0); + wb_dat_o : out std_logic_vector(15 downto 0); + wb_sel_o : out std_logic_vector(1 downto 0); + wb_we_o : out std_logic; + wb_stb_o : out std_logic; + wb_cyc_o : out std_logic; + wb_ack_i : in std_logic; + wb_err_i : in std_logic; + wb_int_i : in std_logic; + + -- debug signals + debug_init : out std_logic; + debug_access : out std_logic + + ); +end component; + + +component wb_7seg_new +port ( + + -- General + clk_i : in std_logic; + nrst_i : in std_logic; + + -- Master whisbone + wb_adr_i : in std_logic_vector(24 downto 1); + wb_dat_o : out std_logic_vector(15 downto 0); + wb_dat_i : in std_logic_vector(15 downto 0); + wb_sel_i : in std_logic_vector(1 downto 0); + wb_we_i : in std_logic; + wb_stb_i : in std_logic; + wb_cyc_i : in std_logic; + wb_ack_o : out std_logic; + wb_err_o : out std_logic; + wb_int_o : out std_logic; + + -- 7seg + DISP_SEL : inout std_logic_vector(3 downto 0); + DISP_LED : out std_logic_vector(6 downto 0) + + ); +end component; + + +component vgaController is + Port ( mclk : in std_logic; + hs : out std_logic; + vs : out std_logic; + red : out std_logic; + grn : out std_logic; + blu : out std_logic); +end component; + + +--+-----------------------------------------------------------------------------+ +--| CONSTANTS | +--+-----------------------------------------------------------------------------+ +--+-----------------------------------------------------------------------------+ +--| SIGNALS | +--+-----------------------------------------------------------------------------+ + + signal wb_adr : std_logic_vector(24 downto 1); + signal wb_dat_out : std_logic_vector(15 downto 0); + signal wb_dat_in : std_logic_vector(15 downto 0); + signal wb_sel : std_logic_vector(1 downto 0); + signal wb_we : std_logic; + signal wb_stb : std_logic; + signal wb_cyc : std_logic; + signal wb_ack : std_logic; + signal wb_err : std_logic; + signal wb_int : std_logic; + + +begin + + LED_ALIVE <= '1'; +--+-------------------------------------------------------------------------+ +--| Component instances | +--+-------------------------------------------------------------------------+ + + vga1: vgaController port map (mclk => mclk, + hs => hs, + vs => vs, + red => red, + grn => grn, + blu => blu); + +--+-----------------------------------------+ +--| PCI Target | +--+-----------------------------------------+ + +u_pci: component pci32tlite +port map( + clk33 => PCI_CLK, + nrst => PCI_nRES, + ad => PCI_AD, + cbe => PCI_CBE, + par => PCI_PAR, + frame => PCI_nFRAME, + irdy => PCI_nIRDY, + trdy => PCI_nTRDY, + devsel => PCI_nDEVSEL, + stop => PCI_nSTOP, + idsel => PCI_IDSEL, + perr => PCI_nPERR, + serr => PCI_nSERR, + intb => PCI_nINT, + wb_adr_o => wb_adr, + wb_dat_i => wb_dat_out, + wb_dat_o => wb_dat_in, + wb_sel_o => wb_sel, + wb_we_o => wb_we, + wb_stb_o => wb_stb, + wb_cyc_o => wb_cyc, + wb_ack_i => wb_ack, + wb_err_i => wb_err, + wb_int_i => wb_int, + debug_init => LED_INIT, + debug_access => LED_ACCESS + ); + +--+-----------------------------------------+ +--| WB-7seg | +--+-----------------------------------------+ + +u_wb: component wb_7seg_new +port map( + clk_i => PCI_CLK, + nrst_i => PCI_nRES, + wb_adr_i => wb_adr, + wb_dat_o => wb_dat_out, + wb_dat_i => wb_dat_in, + wb_sel_i => wb_sel, + wb_we_i => wb_we, + wb_stb_i => wb_stb, + wb_cyc_i => wb_cyc, + wb_ack_o => wb_ack, + wb_err_o => wb_err, + wb_int_o => wb_int, + DISP_SEL => DISP_SEL, + DISP_LED => DISP_LED +); + +end pci_7seg_arch; Index: raggedstone/trunk/source/generate_pciregs/gen_pciregs.pl =================================================================== --- raggedstone/trunk/source/generate_pciregs/gen_pciregs.pl (nonexistent) +++ raggedstone/trunk/source/generate_pciregs/gen_pciregs.pl (revision 10) @@ -0,0 +1,44 @@ +#!/usr/bin/perl + +my $TOTAL = 42; +my $START = 0x11; + +%h2b = (0 => "0000", 1 => "0001", 2 => "0010", 3 => "0011", +4 => "0100", 5 => "0101", 6 => "0110", 7 => "0111", +8 => "1000", 9 => "1001", a => "1010", b => "1011", +c => "1100", d => "1101", e => "1110", f => "1111", +); + + +system ("cat pciregs.vhd.part1"); + +foreach $i ( 1 .. $TOTAL ) { + my $end = ";"; + $end = "" if $i eq $TOTAL; + print "\t\tjcarr$i" . "ID : std_logic_vector(31 downto 0)$end\n"; +} + +system ("cat pciregs.vhd.part2"); + +foreach $i ( 1 .. $TOTAL ) { + my $end = ";"; + # $end = "" if $i eq $TOTAL; + print "\tconstant JCARR$i" . "IDr : std_logic_vector(31 downto 0) := jcarr$i" . "ID$end\n"; +} + +system ("cat pciregs.vhd.part3"); + +foreach $i ( 1 .. $TOTAL ) { + my $binary, $hex; + $hex = sprintf("%03X", $START); + ($binary = $hex) =~ s/(.)/$h2b{lc $1}/g; + my $out = substr $binary, -6; + print "\t\t when b\"$out\" =>\n"; + my $end = ";"; + # $end = "" if $i eq $TOTAL; + print "\t\t\t\t dataout <= JCARR$i" . "IDr$end\n"; + ++$START; +} + +system ("cat pciregs.vhd.part4"); +

raggedstone/trunk/source/generate_pciregs/gen_pciregs.pl Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: raggedstone/trunk/source/generate_pciregs/pciregs.vhd.part1 =================================================================== --- raggedstone/trunk/source/generate_pciregs/pciregs.vhd.part1 (nonexistent) +++ raggedstone/trunk/source/generate_pciregs/pciregs.vhd.part1 (revision 10) @@ -0,0 +1,189 @@ +--+-------------------------------------------------------------------------------------------------+ +--| | +--| File: pciregs.vhd | +--| | +--| Project: pci32tlite_oc | +--| | +--| Description: Registros PCI | +--| BAR0 is used externally by decoder. | +--| | +--| +-----------------------------------------------------------------------+ | +--| | PCI CONFIGURATION SPACE REGISTERS | | +--| +-----------------------------------------------------------------------+ | +--| | +--| +-------------------------------------------------------------------+ | +--| | REGISTER | adr(7..2) | offset | Byte Enable | Size | | +--| +-------------------------------------------------------------------+ | +--| | VENDORID | 000000 (r) | 00 | 0/1 | 2 | | +--| +-------------------------------------------------------------------+ | +--| | DERVICEID | 000000 (r) | 02 | 2/3 | 2 | | +--| +-------------------------------------------------------------------+ | +--| | CMD | 000001 (r/w) | 04 | 0/1 | 2 | | +--| +-------------------------------------------------------------------+ | +--| | ST | 000001 (r/w*)| 06 | 2/3 | 2 | | +--| +-------------------------------------------------------------------+ | +--| | REVISIONID | 000010 (r) | 08 | 0 | 1 | | +--| +-------------------------------------------------------------------+ | +--| | CLASSCODE | 000010 (r) | 09 | 1/2/3 | 3 | | +--| +-------------------------------------------------------------------+ | +--| | HEADERTYPE | 000011 (r) | 0E | 2 | 1 | | +--| +-------------------------------------------------------------------+ | +--| | BAR0 | 000100 (r/w) | 10 | 0/1/2/3 | 4 | | +--| +-------------------------------------------------------------------+ | +--| | SUBSYSTEMID | 001011 (r) | 2C | 0/1 | 2 | | +--| +-------------------------------------------------------------------+ | +--| | SUBSYSTEMVID | 001011 (r) | 2E | 0/1 | 2 | | +--| +-------------------------------------------------------------------+ | +--| | INTLINE | 001111 (r/w) | 3C | 0 | 1 | | +--| +-------------------------------------------------------------------+ | +--| | INTPIN | 001111 (r) | 3D | 1 | 1 | | +--| +-------------------------------------------------------------------+ | +--| (w*) Reseteable | +--| | +--| +-----------------------------------------------+ | +--| | VENDORID (r) Vendor ID register | | +--| +-----------------------------------------------+-----------------------+ | +--| | Identifies manufacturer of device. | | +--| | VENDORIDr : vendorID (generic) | | +--| +-----------------------------------------------------------------------+ | +--| | +--| +-----------------------------------------------+ | +--| | DEVICEID (r) Device ID register | | +--| +-----------------------------------------------+-----------------------+ | +--| | Identifies the device. | | +--| | DEVICEIDr : deviceID (generic) | | +--| +-----------------------------------------------------------------------+ | +--| | +--| +-----------------------------------------------+ | +--| | CMD (r/w) CoMmanD register | | +--| +-----------------------------------------------+----------------------------+ | +--| | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SERRENb| (15-8) | +--| +----------------------------------------------------------------------------+ | +--| | 0 | PERRENb| 0 | 0 | 0 | 0 |MEMSPACEENb| 0 | (7-0) | +--| +----------------------------------------------------------------------------+ | +--| | SERRENb : System ERRor ENable (1 = Enabled) | | +--| | PERRENb : Parity ERRor ENable (1 = Enabled) | | +--| | MEMSPACEENb : MEMmory SPACE ENable (1 = Enabled) | | +--| +-----------------------------------------------------------------------+ | +--| | +--| +-----------------------------------------------+ | +--| | ST (r/w*) STatus register | | +--| +-----------------------------------------------+-------------------------+ | +--| | PERRDTb | SERRSIb| -- | -- |TABORTSIb| DEVSELTIMb(1..0)| -- | (15-8) | +--| +-------------------------------------------------------------------------+ | +--| | -- | -- | -- | -- | -- | -- | -- | -- | (7-0) | +--| +-------------------------------------------------------------------------+ | +--| | PERRDTb : Parity ERRor DeTected | | +--| | SERRSIb : System ERRor SIgnaled | | +--| | TABORTSIb : Target ABORT SIgnaled | | +--| +-----------------------------------------------------------------------+ | +--| | +--| +-----------------------------------------------+ | +--| | REVISIONID (r) Revision ID register | | +--| +-----------------------------------------------+-----------------------+ | +--| | Identifies a device revision. | | +--| +-----------------------------------------------------------------------+ | +--| +-----------------------------------------------+ | +--| | CLASSCODE (r) CLASS CODE register | | +--| +-----------------------------------------------+-----------------------+ | +--| | Identifies the generic funtion of the device. | | +--| +-----------------------------------------------------------------------+ | +--| +-----------------------------------------------+ | +--| | HEADERTYPE (r) Header Type register | | +--| +-----------------------------------------------+-----------------------+ | +--| | Identifies the layout of the second part of the predefined header. | | +--| +-----------------------------------------------------------------------+ | +--| | +--| +-----------------------------------------------+ | +--| | BAR0 (r/w) Base AddRess 0 register | | +--| +-----------------------------------------------+-----------------------+ | +--| | BAR032MBb(6..0) | -- | (31-24) | +--| +-----------------------------------------------------------------------+ | +--| | BAR032MBb : Base Address 32MBytes decode space (7 bits) | | +--| +-----------------------------------------------------------------------+ | +--| | +--| +-----------------------------------------------+ | +--| | SUBSYSTEMVID (r) SUBSYSTEM Vendor ID register | | +--| +-----------------------------------------------+-----------------------+ | +--| | Identifies vendor of add-in board or subsystem. | | +--| | SUBSYSTEMVIDr : subsystemvID (generic) | | +--| +-----------------------------------------------------------------------+ | +--| | +--| +-----------------------------------------------+ | +--| | SUBSYSTEMID (r) SUBSYSTEM ID register | | +--| +-----------------------------------------------+-----------------------+ | +--| | Vendor specific. | | +--| | SUBSYTEMIDr : subsytemID (generic) | | +--| +-----------------------------------------------------------------------+ | +--| | +--| +-----------------------------------------------+ | +--| | INTLINE (r/w) INTerrupt LINE register | | +--| +-----------------------------------------------+-----------------------+ | +--| | INTLINEr(7..0) | (7..0) | +--| +-----------------------------------------------------------------------+ | +--| | Interrupt Line routing information | | +--| +-----------------------------------------------------------------------+ | +--| | +--| +-----------------------------------------------+ | +--| | INTPIN (r) INTerrupt PIN register | | +--| +-----------------------------------------------+-----------------------+ | +--| | Tells which interrupt pin the device uses: 01=INTA | | +--| +-----------------------------------------------------------------------+ | +--| | +--+-------------------------------------------------------------------------------------------------+ +--| | +--| Revision history : | +--| Date Version Author Description | +--| 2005-05-13 R00A00 PAU First alfa revision (eng) | +--| | +--| To do: | +--| | +--+-------------------------------------------------------------------------------------------------+ +--+-----------------------------------------------------------------+ +--| | +--| Copyright (C) 2005 Peio Azkarate, peio@opencores.org | +--| | +--| This source file may be used and distributed without | +--| restriction provided that this copyright statement is not | +--| removed from the file and that any derivative work contains | +--| the original copyright notice and the associated disclaimer. | +--| | +--| This source file is free software; you can redistribute it | +--| and/or modify it under the terms of the GNU Lesser General | +--| Public License as published by the Free Software Foundation; | +--| either version 2.1 of the License, or (at your option) any | +--| later version. | +--| | +--| This source is distributed in the hope that it will be | +--| useful, but WITHOUT ANY WARRANTY; without even the implied | +--| warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR | +--| PURPOSE. See the GNU Lesser General Public License for more | +--| details. | +--| | +--| You should have received a copy of the GNU Lesser General | +--| Public License along with this source; if not, download it | +--| from http://www.opencores.org/lgpl.shtml | +--| | +--+-----------------------------------------------------------------+ + + +--+-----------------------------------------------------------------------------+ +--| LIBRARIES | +--+-----------------------------------------------------------------------------+ + +library ieee; +use ieee.std_logic_1164.all; + + +--+-----------------------------------------------------------------------------+ +--| ENTITY | +--+-----------------------------------------------------------------------------+ + +entity pciregs is +generic ( + + vendorID : std_logic_vector(15 downto 0); + deviceID : std_logic_vector(15 downto 0); + revisionID : std_logic_vector(7 downto 0); + subsystemID : std_logic_vector(15 downto 0); + subsystemvID : std_logic_vector(15 downto 0); Index: raggedstone/trunk/source/generate_pciregs/pciregs.vhd.part2 =================================================================== --- raggedstone/trunk/source/generate_pciregs/pciregs.vhd.part2 (nonexistent) +++ raggedstone/trunk/source/generate_pciregs/pciregs.vhd.part2 (revision 10) @@ -0,0 +1,46 @@ + +); +port ( + + -- General + clk_i : in std_logic; + nrst_i : in std_logic; + -- + adr_i : in std_logic_vector(5 downto 0); + cbe_i : in std_logic_vector(3 downto 0); + dat_i : in std_logic_vector(31 downto 0); + dat_o : out std_logic_vector(31 downto 0); + -- + wrcfg_i : in std_logic; + rdcfg_i : in std_logic; + perr_i : in std_logic; + serr_i : in std_logic; + tabort_i : in std_logic; + -- + bar0_o : out std_logic_vector(31 downto 25); + perrEN_o : out std_logic; + serrEN_o : out std_logic; + memEN_o : out std_logic + +); +end pciregs; + + +architecture rtl of pciregs is + + +--+-----------------------------------------------------------------------------+ +--| COMPONENTS | +--+-----------------------------------------------------------------------------+ +--+-----------------------------------------------------------------------------+ +--| CONSTANTS | +--+-----------------------------------------------------------------------------+ + + constant CLASSCODEr : std_logic_vector(23 downto 0) := X"028000"; -- Bridge-OtherBridgeDevice + constant REVISIONIDr : std_logic_vector(7 downto 0) := revisionID; -- PR00=80,PR1=81... + constant HEADERTYPEr : std_logic_vector(7 downto 0) := X"00"; + constant DEVSELTIMb : std_logic_vector(1 downto 0) := b"01"; -- DEVSEL TIMing (bits) medium speed + constant VENDORIDr : std_logic_vector(15 downto 0) := vendorID; + constant DEVICEIDr : std_logic_vector(15 downto 0) := deviceID; + constant SUBSYSTEMIDr : std_logic_vector(15 downto 0) := subsystemID; + constant SUBSYSTEMVIDr : std_logic_vector(15 downto 0) := subsystemvID; Index: raggedstone/trunk/source/generate_pciregs/pciregs.vhd.part3 =================================================================== --- raggedstone/trunk/source/generate_pciregs/pciregs.vhd.part3 (nonexistent) +++ raggedstone/trunk/source/generate_pciregs/pciregs.vhd.part3 (revision 10) @@ -0,0 +1,245 @@ + constant INTPINr : std_logic_vector(7 downto 0) := X"01"; -- INTA# + + +--+-----------------------------------------------------------------------------+ +--| SIGNALS | +--+-----------------------------------------------------------------------------+ + + signal dataout : std_logic_vector(31 downto 0); + signal tabortPFS : std_logic; + signal serrPFS : std_logic; + signal perrPFS : std_logic; + signal adrSTCMD : std_logic; + signal adrBAR0 : std_logic; + signal adrINT : std_logic; + signal we0CMD : std_logic; + signal we1CMD : std_logic; + signal we3ST : std_logic; + signal we3BAR0 : std_logic; + signal we0INT : std_logic; + signal we1INT : std_logic; + signal st11SEN : std_logic; + signal st11REN : std_logic; + signal st14SEN : std_logic; + signal st14REN : std_logic; + signal st15SEN : std_logic; + signal st15REN : std_logic; + + + --+---------------------------------------------------------+ + --| CONFIGURATION SPACE REGISTERS | + --+---------------------------------------------------------+ + + -- INTERRUPT LINE register + signal INTLINEr : std_logic_vector(7 downto 0); + -- COMMAND register bits + signal MEMSPACEENb : std_logic; -- Memory SPACE ENable (bit) + signal PERRENb : std_logic; -- Parity ERRor ENable (bit) + signal SERRENb : std_logic; -- SERR ENable (bit) + -- STATUS register bits + --signal DEVSELTIMb : std_logic_vector(1 downto 0); -- DEVSEL TIMing (bits) + signal TABORTSIb : std_logic; -- TarGet ABORT SIgnaling (bit) + signal SERRSIb : std_logic; -- System ERRor SIgnaling (bit) + signal PERRDTb : std_logic; -- Parity ERRor DeTected (bit) + -- BAR0 register bits + signal BAR032MBb : std_logic_vector(6 downto 0); -- BAR0 32MBytes Space (bits) + + +component pfs +port ( + clk : in std_logic; + a : in std_logic; + y : out std_logic +); + +end component; + +begin + + --+-------------------------------------------------------------------------+ + --| Component instances | + --+-------------------------------------------------------------------------+ + + u1: pfs port map ( clk => clk_i, a => tabort_i, y => tabortPFS ); + u2: pfs port map ( clk => clk_i, a => serr_i, y => serrPFS ); + u3: pfs port map ( clk => clk_i, a => perr_i, y => perrPFS ); + + + --+-------------------------------------------------------------------------+ + --| Registers Address Decoder | + --+-------------------------------------------------------------------------+ + + adrSTCMD <= '1' when ( adr_i(5 downto 0) = b"000001" ) else '0'; + adrBAR0 <= '1' when ( adr_i(5 downto 0) = b"000100" ) else '0'; + adrINT <= '1' when ( adr_i(5 downto 0) = b"001111" ) else '0'; + + + --+-------------------------------------------------------------------------+ + --| WRITE ENABLE REGISTERS | + --+-------------------------------------------------------------------------+ + + --+-----------------------------------------+ + --| Write Enable Registers | + --+-----------------------------------------+ + + we0CMD <= adrSTCMD and wrcfg_i and (not cbe_i(0)); + we1CMD <= adrSTCMD and wrcfg_i and (not cbe_i(1)); + --we2ST <= adrSTCMD and wrcfg_i and (not cbe_i(2)); + we3ST <= adrSTCMD and wrcfg_i and (not cbe_i(3)); + --we2BAR0 <= adrBAR0 and wrcfg_i and (not cbe_i(2)); + we3BAR0 <= adrBAR0 and wrcfg_i and (not cbe_i(3)); + we0INT <= adrINT and wrcfg_i and (not cbe_i(0)); + --we1INT <= adrINT and wrcfg_i and (not cbe_i(1)); + + --+-----------------------------------------+ + --| Set Enable & Reset Enable bits | + --+-----------------------------------------+ + st11SEN <= tabortPFS; + st11REN <= we3ST and dat_i(27); + st14SEN <= serrPFS; + st14REN <= we3ST and dat_i(30); + st15SEN <= perrPFS; + st15REN <= we3ST and dat_i(31); + + + --+-------------------------------------------------------------------------+ + --| WRITE REGISTERS | + --+-------------------------------------------------------------------------+ + + --+---------------------------------------------------------+ + --| COMMAND REGISTER Write | + --+---------------------------------------------------------+ + + REGCMDWR: process( clk_i, nrst_i, we0CMD, we1CMD, dat_i ) + begin + + if( nrst_i = '0' ) then + MEMSPACEENb <= '0'; + PERRENb <= '0'; + SERRENb <= '0'; + elsif( rising_edge( clk_i ) ) then + + -- Byte 0 + if( we0CMD = '1' ) then + MEMSPACEENb <= dat_i(1); + PERRENb <= dat_i(6); + end if; + + -- Byte 1 + if( we1CMD = '1' ) then + SERRENb <= dat_i(8); + end if; + + end if; + + end process REGCMDWR; + + + --+---------------------------------------------------------+ + --| STATUS REGISTER WRITE (Reset only) | + --+---------------------------------------------------------+ + + REGSTWR: process( clk_i, nrst_i, st11SEN, st11REN, st14SEN, st14REN, st15SEN, st15REN ) + begin + + if( nrst_i = '0' ) then + TABORTSIb <= '0'; + SERRSIb <= '0'; + PERRDTb <= '0'; + elsif( rising_edge( clk_i ) ) then + + -- TarGet ABORT SIgnaling bit + if( st11SEN = '1' ) then + TABORTSIb <= '1'; + elsif ( st11REN = '1' ) then + TABORTSIb <= '0'; + end if; + + -- System ERRor SIgnaling bit + if( st14SEN = '1' ) then + SERRSIb <= '1'; + elsif ( st14REN = '1' ) then + SERRSIb <= '0'; + end if; + + -- Parity ERRor DEtected bit + if( st15SEN = '1' ) then + PERRDTb <= '1'; + elsif ( st15REN = '1' ) then + PERRDTb <= '0'; + end if; + + end if; + + end process REGSTWR; + + + --+---------------------------------------------------------+ + --| INTERRUPT REGISTER Write | + --+---------------------------------------------------------+ + + REGINTWR: process( clk_i, nrst_i, we0INT, dat_i ) + begin + + if( nrst_i = '0' ) then + INTLINEr <= ( others => '0' ); + elsif( rising_edge( clk_i ) ) then + + -- Byte 0 + if( we0INT = '1' ) then + INTLINEr <= dat_i(7 downto 0); + end if; + + + end if; + + end process REGINTWR; + + + --+---------------------------------------------------------+ + --| BAR0 32MBytes address space (bits 31-25) | + --+---------------------------------------------------------+ + + REGBAR0WR: process( clk_i, nrst_i, we3BAR0, dat_i ) + begin + + if( nrst_i = '0' ) then + BAR032MBb <= ( others => '1' ); + elsif( rising_edge( clk_i ) ) then + + -- Byte 3 + if( we3BAR0 = '1' ) then + BAR032MBb <= dat_i(31 downto 25); + end if; + + end if; + + end process REGBAR0WR; + + + --+-------------------------------------------------------------------------+ + --| Registers MUX (READ) | + --+-------------------------------------------------------------------------+ +--+-------------------------------------------------------------------------------------------------+ + + RRMUX: process( adr_i, PERRDTb, SERRSIb, TABORTSIb, SERRENb, PERRENb, MEMSPACEENb, BAR032MBb, + INTLINEr, rdcfg_i ) + begin + + if ( rdcfg_i = '1' ) then + + case adr_i is + + when b"000000" => + dataout <= DEVICEIDr & VENDORIDr; + when b"000001" => + dataout <= PERRDTb & SERRSIb & b"00" & TABORTSIb & DEVSELTIMb & b"000000000" & + b"0000000" & SERRENb & b"0" & PERRENb & b"0000" & MEMSPACEENb & b"0"; + when b"000010" => + dataout <= CLASSCODEr & REVISIONIDr; + when b"000100" => + dataout <= BAR032MBb & b"0" & b"00000000" & b"00000000" & b"00000000"; + when b"001011" => + dataout <= SUBSYSTEMIDr & SUBSYSTEMVIDr; + when b"001111" => + dataout <= b"0000000000000000" & INTPINr & INTLINEr; Index: raggedstone/trunk/source/generate_pciregs/new_pciregs.vhd =================================================================== --- raggedstone/trunk/source/generate_pciregs/new_pciregs.vhd (nonexistent) +++ raggedstone/trunk/source/generate_pciregs/new_pciregs.vhd (revision 10) @@ -0,0 +1,675 @@ +--+-------------------------------------------------------------------------------------------------+ +--| | +--| File: pciregs.vhd | +--| | +--| Project: pci32tlite_oc | +--| | +--| Description: Registros PCI | +--| BAR0 is used externally by decoder. | +--| | +--| +-----------------------------------------------------------------------+ | +--| | PCI CONFIGURATION SPACE REGISTERS | | +--| +-----------------------------------------------------------------------+ | +--| | +--| +-------------------------------------------------------------------+ | +--| | REGISTER | adr(7..2) | offset | Byte Enable | Size | | +--| +-------------------------------------------------------------------+ | +--| | VENDORID | 000000 (r) | 00 | 0/1 | 2 | | +--| +-------------------------------------------------------------------+ | +--| | DERVICEID | 000000 (r) | 02 | 2/3 | 2 | | +--| +-------------------------------------------------------------------+ | +--| | CMD | 000001 (r/w) | 04 | 0/1 | 2 | | +--| +-------------------------------------------------------------------+ | +--| | ST | 000001 (r/w*)| 06 | 2/3 | 2 | | +--| +-------------------------------------------------------------------+ | +--| | REVISIONID | 000010 (r) | 08 | 0 | 1 | | +--| +-------------------------------------------------------------------+ | +--| | CLASSCODE | 000010 (r) | 09 | 1/2/3 | 3 | | +--| +-------------------------------------------------------------------+ | +--| | HEADERTYPE | 000011 (r) | 0E | 2 | 1 | | +--| +-------------------------------------------------------------------+ | +--| | BAR0 | 000100 (r/w) | 10 | 0/1/2/3 | 4 | | +--| +-------------------------------------------------------------------+ | +--| | SUBSYSTEMID | 001011 (r) | 2C | 0/1 | 2 | | +--| +-------------------------------------------------------------------+ | +--| | SUBSYSTEMVID | 001011 (r) | 2E | 0/1 | 2 | | +--| +-------------------------------------------------------------------+ | +--| | INTLINE | 001111 (r/w) | 3C | 0 | 1 | | +--| +-------------------------------------------------------------------+ | +--| | INTPIN | 001111 (r) | 3D | 1 | 1 | | +--| +-------------------------------------------------------------------+ | +--| (w*) Reseteable | +--| | +--| +-----------------------------------------------+ | +--| | VENDORID (r) Vendor ID register | | +--| +-----------------------------------------------+-----------------------+ | +--| | Identifies manufacturer of device. | | +--| | VENDORIDr : vendorID (generic) | | +--| +-----------------------------------------------------------------------+ | +--| | +--| +-----------------------------------------------+ | +--| | DEVICEID (r) Device ID register | | +--| +-----------------------------------------------+-----------------------+ | +--| | Identifies the device. | | +--| | DEVICEIDr : deviceID (generic) | | +--| +-----------------------------------------------------------------------+ | +--| | +--| +-----------------------------------------------+ | +--| | CMD (r/w) CoMmanD register | | +--| +-----------------------------------------------+----------------------------+ | +--| | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SERRENb| (15-8) | +--| +----------------------------------------------------------------------------+ | +--| | 0 | PERRENb| 0 | 0 | 0 | 0 |MEMSPACEENb| 0 | (7-0) | +--| +----------------------------------------------------------------------------+ | +--| | SERRENb : System ERRor ENable (1 = Enabled) | | +--| | PERRENb : Parity ERRor ENable (1 = Enabled) | | +--| | MEMSPACEENb : MEMmory SPACE ENable (1 = Enabled) | | +--| +-----------------------------------------------------------------------+ | +--| | +--| +-----------------------------------------------+ | +--| | ST (r/w*) STatus register | | +--| +-----------------------------------------------+-------------------------+ | +--| | PERRDTb | SERRSIb| -- | -- |TABORTSIb| DEVSELTIMb(1..0)| -- | (15-8) | +--| +-------------------------------------------------------------------------+ | +--| | -- | -- | -- | -- | -- | -- | -- | -- | (7-0) | +--| +-------------------------------------------------------------------------+ | +--| | PERRDTb : Parity ERRor DeTected | | +--| | SERRSIb : System ERRor SIgnaled | | +--| | TABORTSIb : Target ABORT SIgnaled | | +--| +-----------------------------------------------------------------------+ | +--| | +--| +-----------------------------------------------+ | +--| | REVISIONID (r) Revision ID register | | +--| +-----------------------------------------------+-----------------------+ | +--| | Identifies a device revision. | | +--| +-----------------------------------------------------------------------+ | +--| +-----------------------------------------------+ | +--| | CLASSCODE (r) CLASS CODE register | | +--| +-----------------------------------------------+-----------------------+ | +--| | Identifies the generic funtion of the device. | | +--| +-----------------------------------------------------------------------+ | +--| +-----------------------------------------------+ | +--| | HEADERTYPE (r) Header Type register | | +--| +-----------------------------------------------+-----------------------+ | +--| | Identifies the layout of the second part of the predefined header. | | +--| +-----------------------------------------------------------------------+ | +--| | +--| +-----------------------------------------------+ | +--| | BAR0 (r/w) Base AddRess 0 register | | +--| +-----------------------------------------------+-----------------------+ | +--| | BAR032MBb(6..0) | -- | (31-24) | +--| +-----------------------------------------------------------------------+ | +--| | BAR032MBb : Base Address 32MBytes decode space (7 bits) | | +--| +-----------------------------------------------------------------------+ | +--| | +--| +-----------------------------------------------+ | +--| | SUBSYSTEMVID (r) SUBSYSTEM Vendor ID register | | +--| +-----------------------------------------------+-----------------------+ | +--| | Identifies vendor of add-in board or subsystem. | | +--| | SUBSYSTEMVIDr : subsystemvID (generic) | | +--| +-----------------------------------------------------------------------+ | +--| | +--| +-----------------------------------------------+ | +--| | SUBSYSTEMID (r) SUBSYSTEM ID register | | +--| +-----------------------------------------------+-----------------------+ | +--| | Vendor specific. | | +--| | SUBSYTEMIDr : subsytemID (generic) | | +--| +-----------------------------------------------------------------------+ | +--| | +--| +-----------------------------------------------+ | +--| | INTLINE (r/w) INTerrupt LINE register | | +--| +-----------------------------------------------+-----------------------+ | +--| | INTLINEr(7..0) | (7..0) | +--| +-----------------------------------------------------------------------+ | +--| | Interrupt Line routing information | | +--| +-----------------------------------------------------------------------+ | +--| | +--| +-----------------------------------------------+ | +--| | INTPIN (r) INTerrupt PIN register | | +--| +-----------------------------------------------+-----------------------+ | +--| | Tells which interrupt pin the device uses: 01=INTA | | +--| +-----------------------------------------------------------------------+ | +--| | +--+-------------------------------------------------------------------------------------------------+ +--| | +--| Revision history : | +--| Date Version Author Description | +--| 2005-05-13 R00A00 PAU First alfa revision (eng) | +--| | +--| To do: | +--| | +--+-------------------------------------------------------------------------------------------------+ +--+-----------------------------------------------------------------+ +--| | +--| Copyright (C) 2005 Peio Azkarate, peio@opencores.org | +--| | +--| This source file may be used and distributed without | +--| restriction provided that this copyright statement is not | +--| removed from the file and that any derivative work contains | +--| the original copyright notice and the associated disclaimer. | +--| | +--| This source file is free software; you can redistribute it | +--| and/or modify it under the terms of the GNU Lesser General | +--| Public License as published by the Free Software Foundation; | +--| either version 2.1 of the License, or (at your option) any | +--| later version. | +--| | +--| This source is distributed in the hope that it will be | +--| useful, but WITHOUT ANY WARRANTY; without even the implied | +--| warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR | +--| PURPOSE. See the GNU Lesser General Public License for more | +--| details. | +--| | +--| You should have received a copy of the GNU Lesser General | +--| Public License along with this source; if not, download it | +--| from http://www.opencores.org/lgpl.shtml | +--| | +--+-----------------------------------------------------------------+ + + +--+-----------------------------------------------------------------------------+ +--| LIBRARIES | +--+-----------------------------------------------------------------------------+ + +library ieee; +use ieee.std_logic_1164.all; + + +--+-----------------------------------------------------------------------------+ +--| ENTITY | +--+-----------------------------------------------------------------------------+ + +entity pciregs is +generic ( + + vendorID : std_logic_vector(15 downto 0); + deviceID : std_logic_vector(15 downto 0); + revisionID : std_logic_vector(7 downto 0); + subsystemID : std_logic_vector(15 downto 0); + subsystemvID : std_logic_vector(15 downto 0); + jcarr1ID : std_logic_vector(31 downto 0); + jcarr2ID : std_logic_vector(31 downto 0); + jcarr3ID : std_logic_vector(31 downto 0); + jcarr4ID : std_logic_vector(31 downto 0); + jcarr5ID : std_logic_vector(31 downto 0); + jcarr6ID : std_logic_vector(31 downto 0); + jcarr7ID : std_logic_vector(31 downto 0); + jcarr8ID : std_logic_vector(31 downto 0); + jcarr9ID : std_logic_vector(31 downto 0); + jcarr10ID : std_logic_vector(31 downto 0); + jcarr11ID : std_logic_vector(31 downto 0); + jcarr12ID : std_logic_vector(31 downto 0); + jcarr13ID : std_logic_vector(31 downto 0); + jcarr14ID : std_logic_vector(31 downto 0); + jcarr15ID : std_logic_vector(31 downto 0); + jcarr16ID : std_logic_vector(31 downto 0); + jcarr17ID : std_logic_vector(31 downto 0); + jcarr18ID : std_logic_vector(31 downto 0); + jcarr19ID : std_logic_vector(31 downto 0); + jcarr20ID : std_logic_vector(31 downto 0); + jcarr21ID : std_logic_vector(31 downto 0); + jcarr22ID : std_logic_vector(31 downto 0); + jcarr23ID : std_logic_vector(31 downto 0); + jcarr24ID : std_logic_vector(31 downto 0); + jcarr25ID : std_logic_vector(31 downto 0); + jcarr26ID : std_logic_vector(31 downto 0); + jcarr27ID : std_logic_vector(31 downto 0); + jcarr28ID : std_logic_vector(31 downto 0); + jcarr29ID : std_logic_vector(31 downto 0); + jcarr30ID : std_logic_vector(31 downto 0); + jcarr31ID : std_logic_vector(31 downto 0); + jcarr32ID : std_logic_vector(31 downto 0); + jcarr33ID : std_logic_vector(31 downto 0); + jcarr34ID : std_logic_vector(31 downto 0); + jcarr35ID : std_logic_vector(31 downto 0); + jcarr36ID : std_logic_vector(31 downto 0); + jcarr37ID : std_logic_vector(31 downto 0); + jcarr38ID : std_logic_vector(31 downto 0); + jcarr39ID : std_logic_vector(31 downto 0); + jcarr40ID : std_logic_vector(31 downto 0); + jcarr41ID : std_logic_vector(31 downto 0); + jcarr42ID : std_logic_vector(31 downto 0) + +); +port ( + + -- General + clk_i : in std_logic; + nrst_i : in std_logic; + -- + adr_i : in std_logic_vector(5 downto 0); + cbe_i : in std_logic_vector(3 downto 0); + dat_i : in std_logic_vector(31 downto 0); + dat_o : out std_logic_vector(31 downto 0); + -- + wrcfg_i : in std_logic; + rdcfg_i : in std_logic; + perr_i : in std_logic; + serr_i : in std_logic; + tabort_i : in std_logic; + -- + bar0_o : out std_logic_vector(31 downto 25); + perrEN_o : out std_logic; + serrEN_o : out std_logic; + memEN_o : out std_logic + +); +end pciregs; + + +architecture rtl of pciregs is + + +--+-----------------------------------------------------------------------------+ +--| COMPONENTS | +--+-----------------------------------------------------------------------------+ +--+-----------------------------------------------------------------------------+ +--| CONSTANTS | +--+-----------------------------------------------------------------------------+ + + constant CLASSCODEr : std_logic_vector(23 downto 0) := X"028000"; -- Bridge-OtherBridgeDevice + constant REVISIONIDr : std_logic_vector(7 downto 0) := revisionID; -- PR00=80,PR1=81... + constant HEADERTYPEr : std_logic_vector(7 downto 0) := X"00"; + constant DEVSELTIMb : std_logic_vector(1 downto 0) := b"01"; -- DEVSEL TIMing (bits) medium speed + constant VENDORIDr : std_logic_vector(15 downto 0) := vendorID; + constant DEVICEIDr : std_logic_vector(15 downto 0) := deviceID; + constant SUBSYSTEMIDr : std_logic_vector(15 downto 0) := subsystemID; + constant SUBSYSTEMVIDr : std_logic_vector(15 downto 0) := subsystemvID; + constant JCARR1IDr : std_logic_vector(31 downto 0) := jcarr1ID; + constant JCARR2IDr : std_logic_vector(31 downto 0) := jcarr2ID; + constant JCARR3IDr : std_logic_vector(31 downto 0) := jcarr3ID; + constant JCARR4IDr : std_logic_vector(31 downto 0) := jcarr4ID; + constant JCARR5IDr : std_logic_vector(31 downto 0) := jcarr5ID; + constant JCARR6IDr : std_logic_vector(31 downto 0) := jcarr6ID; + constant JCARR7IDr : std_logic_vector(31 downto 0) := jcarr7ID; + constant JCARR8IDr : std_logic_vector(31 downto 0) := jcarr8ID; + constant JCARR9IDr : std_logic_vector(31 downto 0) := jcarr9ID; + constant JCARR10IDr : std_logic_vector(31 downto 0) := jcarr10ID; + constant JCARR11IDr : std_logic_vector(31 downto 0) := jcarr11ID; + constant JCARR12IDr : std_logic_vector(31 downto 0) := jcarr12ID; + constant JCARR13IDr : std_logic_vector(31 downto 0) := jcarr13ID; + constant JCARR14IDr : std_logic_vector(31 downto 0) := jcarr14ID; + constant JCARR15IDr : std_logic_vector(31 downto 0) := jcarr15ID; + constant JCARR16IDr : std_logic_vector(31 downto 0) := jcarr16ID; + constant JCARR17IDr : std_logic_vector(31 downto 0) := jcarr17ID; + constant JCARR18IDr : std_logic_vector(31 downto 0) := jcarr18ID; + constant JCARR19IDr : std_logic_vector(31 downto 0) := jcarr19ID; + constant JCARR20IDr : std_logic_vector(31 downto 0) := jcarr20ID; + constant JCARR21IDr : std_logic_vector(31 downto 0) := jcarr21ID; + constant JCARR22IDr : std_logic_vector(31 downto 0) := jcarr22ID; + constant JCARR23IDr : std_logic_vector(31 downto 0) := jcarr23ID; + constant JCARR24IDr : std_logic_vector(31 downto 0) := jcarr24ID; + constant JCARR25IDr : std_logic_vector(31 downto 0) := jcarr25ID; + constant JCARR26IDr : std_logic_vector(31 downto 0) := jcarr26ID; + constant JCARR27IDr : std_logic_vector(31 downto 0) := jcarr27ID; + constant JCARR28IDr : std_logic_vector(31 downto 0) := jcarr28ID; + constant JCARR29IDr : std_logic_vector(31 downto 0) := jcarr29ID; + constant JCARR30IDr : std_logic_vector(31 downto 0) := jcarr30ID; + constant JCARR31IDr : std_logic_vector(31 downto 0) := jcarr31ID; + constant JCARR32IDr : std_logic_vector(31 downto 0) := jcarr32ID; + constant JCARR33IDr : std_logic_vector(31 downto 0) := jcarr33ID; + constant JCARR34IDr : std_logic_vector(31 downto 0) := jcarr34ID; + constant JCARR35IDr : std_logic_vector(31 downto 0) := jcarr35ID; + constant JCARR36IDr : std_logic_vector(31 downto 0) := jcarr36ID; + constant JCARR37IDr : std_logic_vector(31 downto 0) := jcarr37ID; + constant JCARR38IDr : std_logic_vector(31 downto 0) := jcarr38ID; + constant JCARR39IDr : std_logic_vector(31 downto 0) := jcarr39ID; + constant JCARR40IDr : std_logic_vector(31 downto 0) := jcarr40ID; + constant JCARR41IDr : std_logic_vector(31 downto 0) := jcarr41ID; + constant JCARR42IDr : std_logic_vector(31 downto 0) := jcarr42ID; + constant INTPINr : std_logic_vector(7 downto 0) := X"01"; -- INTA# + + +--+-----------------------------------------------------------------------------+ +--| SIGNALS | +--+-----------------------------------------------------------------------------+ + + signal dataout : std_logic_vector(31 downto 0); + signal tabortPFS : std_logic; + signal serrPFS : std_logic; + signal perrPFS : std_logic; + signal adrSTCMD : std_logic; + signal adrBAR0 : std_logic; + signal adrINT : std_logic; + signal we0CMD : std_logic; + signal we1CMD : std_logic; + signal we3ST : std_logic; + signal we3BAR0 : std_logic; + signal we0INT : std_logic; + signal we1INT : std_logic; + signal st11SEN : std_logic; + signal st11REN : std_logic; + signal st14SEN : std_logic; + signal st14REN : std_logic; + signal st15SEN : std_logic; + signal st15REN : std_logic; + + + --+---------------------------------------------------------+ + --| CONFIGURATION SPACE REGISTERS | + --+---------------------------------------------------------+ + + -- INTERRUPT LINE register + signal INTLINEr : std_logic_vector(7 downto 0); + -- COMMAND register bits + signal MEMSPACEENb : std_logic; -- Memory SPACE ENable (bit) + signal PERRENb : std_logic; -- Parity ERRor ENable (bit) + signal SERRENb : std_logic; -- SERR ENable (bit) + -- STATUS register bits + --signal DEVSELTIMb : std_logic_vector(1 downto 0); -- DEVSEL TIMing (bits) + signal TABORTSIb : std_logic; -- TarGet ABORT SIgnaling (bit) + signal SERRSIb : std_logic; -- System ERRor SIgnaling (bit) + signal PERRDTb : std_logic; -- Parity ERRor DeTected (bit) + -- BAR0 register bits + signal BAR032MBb : std_logic_vector(6 downto 0); -- BAR0 32MBytes Space (bits) + + +component pfs +port ( + clk : in std_logic; + a : in std_logic; + y : out std_logic +); + +end component; + +begin + + --+-------------------------------------------------------------------------+ + --| Component instances | + --+-------------------------------------------------------------------------+ + + u1: pfs port map ( clk => clk_i, a => tabort_i, y => tabortPFS ); + u2: pfs port map ( clk => clk_i, a => serr_i, y => serrPFS ); + u3: pfs port map ( clk => clk_i, a => perr_i, y => perrPFS ); + + + --+-------------------------------------------------------------------------+ + --| Registers Address Decoder | + --+-------------------------------------------------------------------------+ + + adrSTCMD <= '1' when ( adr_i(5 downto 0) = b"000001" ) else '0'; + adrBAR0 <= '1' when ( adr_i(5 downto 0) = b"000100" ) else '0'; + adrINT <= '1' when ( adr_i(5 downto 0) = b"001111" ) else '0'; + + + --+-------------------------------------------------------------------------+ + --| WRITE ENABLE REGISTERS | + --+-------------------------------------------------------------------------+ + + --+-----------------------------------------+ + --| Write Enable Registers | + --+-----------------------------------------+ + + we0CMD <= adrSTCMD and wrcfg_i and (not cbe_i(0)); + we1CMD <= adrSTCMD and wrcfg_i and (not cbe_i(1)); + --we2ST <= adrSTCMD and wrcfg_i and (not cbe_i(2)); + we3ST <= adrSTCMD and wrcfg_i and (not cbe_i(3)); + --we2BAR0 <= adrBAR0 and wrcfg_i and (not cbe_i(2)); + we3BAR0 <= adrBAR0 and wrcfg_i and (not cbe_i(3)); + we0INT <= adrINT and wrcfg_i and (not cbe_i(0)); + --we1INT <= adrINT and wrcfg_i and (not cbe_i(1)); + + --+-----------------------------------------+ + --| Set Enable & Reset Enable bits | + --+-----------------------------------------+ + st11SEN <= tabortPFS; + st11REN <= we3ST and dat_i(27); + st14SEN <= serrPFS; + st14REN <= we3ST and dat_i(30); + st15SEN <= perrPFS; + st15REN <= we3ST and dat_i(31); + + + --+-------------------------------------------------------------------------+ + --| WRITE REGISTERS | + --+-------------------------------------------------------------------------+ + + --+---------------------------------------------------------+ + --| COMMAND REGISTER Write | + --+---------------------------------------------------------+ + + REGCMDWR: process( clk_i, nrst_i, we0CMD, we1CMD, dat_i ) + begin + + if( nrst_i = '0' ) then + MEMSPACEENb <= '0'; + PERRENb <= '0'; + SERRENb <= '0'; + elsif( rising_edge( clk_i ) ) then + + -- Byte 0 + if( we0CMD = '1' ) then + MEMSPACEENb <= dat_i(1); + PERRENb <= dat_i(6); + end if; + + -- Byte 1 + if( we1CMD = '1' ) then + SERRENb <= dat_i(8); + end if; + + end if; + + end process REGCMDWR; + + + --+---------------------------------------------------------+ + --| STATUS REGISTER WRITE (Reset only) | + --+---------------------------------------------------------+ + + REGSTWR: process( clk_i, nrst_i, st11SEN, st11REN, st14SEN, st14REN, st15SEN, st15REN ) + begin + + if( nrst_i = '0' ) then + TABORTSIb <= '0'; + SERRSIb <= '0'; + PERRDTb <= '0'; + elsif( rising_edge( clk_i ) ) then + + -- TarGet ABORT SIgnaling bit + if( st11SEN = '1' ) then + TABORTSIb <= '1'; + elsif ( st11REN = '1' ) then + TABORTSIb <= '0'; + end if; + + -- System ERRor SIgnaling bit + if( st14SEN = '1' ) then + SERRSIb <= '1'; + elsif ( st14REN = '1' ) then + SERRSIb <= '0'; + end if; + + -- Parity ERRor DEtected bit + if( st15SEN = '1' ) then + PERRDTb <= '1'; + elsif ( st15REN = '1' ) then + PERRDTb <= '0'; + end if; + + end if; + + end process REGSTWR; + + + --+---------------------------------------------------------+ + --| INTERRUPT REGISTER Write | + --+---------------------------------------------------------+ + + REGINTWR: process( clk_i, nrst_i, we0INT, dat_i ) + begin + + if( nrst_i = '0' ) then + INTLINEr <= ( others => '0' ); + elsif( rising_edge( clk_i ) ) then + + -- Byte 0 + if( we0INT = '1' ) then + INTLINEr <= dat_i(7 downto 0); + end if; + + + end if; + + end process REGINTWR; + + + --+---------------------------------------------------------+ + --| BAR0 32MBytes address space (bits 31-25) | + --+---------------------------------------------------------+ + + REGBAR0WR: process( clk_i, nrst_i, we3BAR0, dat_i ) + begin + + if( nrst_i = '0' ) then + BAR032MBb <= ( others => '1' ); + elsif( rising_edge( clk_i ) ) then + + -- Byte 3 + if( we3BAR0 = '1' ) then + BAR032MBb <= dat_i(31 downto 25); + end if; + + end if; + + end process REGBAR0WR; + + + --+-------------------------------------------------------------------------+ + --| Registers MUX (READ) | + --+-------------------------------------------------------------------------+ +--+-------------------------------------------------------------------------------------------------+ + + RRMUX: process( adr_i, PERRDTb, SERRSIb, TABORTSIb, SERRENb, PERRENb, MEMSPACEENb, BAR032MBb, + INTLINEr, rdcfg_i ) + begin + + if ( rdcfg_i = '1' ) then + + case adr_i is + + when b"000000" => + dataout <= DEVICEIDr & VENDORIDr; + when b"000001" => + dataout <= PERRDTb & SERRSIb & b"00" & TABORTSIb & DEVSELTIMb & b"000000000" & + b"0000000" & SERRENb & b"0" & PERRENb & b"0000" & MEMSPACEENb & b"0"; + when b"000010" => + dataout <= CLASSCODEr & REVISIONIDr; + when b"000100" => + dataout <= BAR032MBb & b"0" & b"00000000" & b"00000000" & b"00000000"; + when b"001011" => + dataout <= SUBSYSTEMIDr & SUBSYSTEMVIDr; + when b"001111" => + dataout <= b"0000000000000000" & INTPINr & INTLINEr; + when b"010001" => + dataout <= JCARR1IDr; + when b"010010" => + dataout <= JCARR2IDr; + when b"010011" => + dataout <= JCARR3IDr; + when b"010100" => + dataout <= JCARR4IDr; + when b"010101" => + dataout <= JCARR5IDr; + when b"010110" => + dataout <= JCARR6IDr; + when b"010111" => + dataout <= JCARR7IDr; + when b"011000" => + dataout <= JCARR8IDr; + when b"011001" => + dataout <= JCARR9IDr; + when b"011010" => + dataout <= JCARR10IDr; + when b"011011" => + dataout <= JCARR11IDr; + when b"011100" => + dataout <= JCARR12IDr; + when b"011101" => + dataout <= JCARR13IDr; + when b"011110" => + dataout <= JCARR14IDr; + when b"011111" => + dataout <= JCARR15IDr; + when b"100000" => + dataout <= JCARR16IDr; + when b"100001" => + dataout <= JCARR17IDr; + when b"100010" => + dataout <= JCARR18IDr; + when b"100011" => + dataout <= JCARR19IDr; + when b"100100" => + dataout <= JCARR20IDr; + when b"100101" => + dataout <= JCARR21IDr; + when b"100110" => + dataout <= JCARR22IDr; + when b"100111" => + dataout <= JCARR23IDr; + when b"101000" => + dataout <= JCARR24IDr; + when b"101001" => + dataout <= JCARR25IDr; + when b"101010" => + dataout <= JCARR26IDr; + when b"101011" => + dataout <= JCARR27IDr; + when b"101100" => + dataout <= JCARR28IDr; + when b"101101" => + dataout <= JCARR29IDr; + when b"101110" => + dataout <= JCARR30IDr; + when b"101111" => + dataout <= JCARR31IDr; + when b"110000" => + dataout <= JCARR32IDr; + when b"110001" => + dataout <= JCARR33IDr; + when b"110010" => + dataout <= JCARR34IDr; + when b"110011" => + dataout <= JCARR35IDr; + when b"110100" => + dataout <= JCARR36IDr; + when b"110101" => + dataout <= JCARR37IDr; + when b"110110" => + dataout <= JCARR38IDr; + when b"110111" => + dataout <= JCARR39IDr; + when b"111000" => + dataout <= JCARR40IDr; + when b"111001" => + dataout <= JCARR41IDr; + when b"111010" => + dataout <= JCARR42IDr; + when others => + dataout <= ( others => '0' ); + + end case; + + else + + dataout <= ( others => '0' ); + + end if; + + end process RRMUX; + + dat_o <= dataout; + + + --+-------------------------------------------------------------------------+ + --| BAR0 & COMMAND REGS bits outputs | + --+-------------------------------------------------------------------------+ + + bar0_o <= BAR032MBb; + perrEN_o <= PERRENb; + serrEN_o <= SERRENb; + memEN_o <= MEMSPACEENb; + + +end rtl; Index: raggedstone/trunk/source/generate_pciregs/pciregs.vhd.part4 =================================================================== --- raggedstone/trunk/source/generate_pciregs/pciregs.vhd.part4 (nonexistent) +++ raggedstone/trunk/source/generate_pciregs/pciregs.vhd.part4 (revision 10) @@ -0,0 +1,27 @@ + when others => + dataout <= ( others => '0' ); + + end case; + + else + + dataout <= ( others => '0' ); + + end if; + + end process RRMUX; + + dat_o <= dataout; + + + --+-------------------------------------------------------------------------+ + --| BAR0 & COMMAND REGS bits outputs | + --+-------------------------------------------------------------------------+ + + bar0_o <= BAR032MBb; + perrEN_o <= PERRENb; + serrEN_o <= SERRENb; + memEN_o <= MEMSPACEENb; + + +end rtl; Index: raggedstone/trunk/source/generate_pciregs/Makefile =================================================================== --- raggedstone/trunk/source/generate_pciregs/Makefile (nonexistent) +++ raggedstone/trunk/source/generate_pciregs/Makefile (revision 10) @@ -0,0 +1,4 @@ +all: + ./gen_pciregs.pl > new_pciregs.vhd + unix2dos new_pciregs.vhd + cp new_pciregs.vhd .. Index: raggedstone/trunk/source/pciwbsequ.v =================================================================== --- raggedstone/trunk/source/pciwbsequ.v (nonexistent) +++ raggedstone/trunk/source/pciwbsequ.v (revision 10) @@ -0,0 +1,295 @@ +// Copyright (C) 2005 Peio Azkarate, peio@opencores.org +// +// This source file is free software; you can redistribute it +// and/or modify it under the terms of the GNU Lesser General +// Public License as published by the Free Software Foundation; +// either version 2.1 of the License, or (at your option) any +// later version. +// + +(* signal_encoding = "user" *) +(* safe_implementation = "yes" *) + +module pciwbsequ_new ( clk_i, nrst_i, cmd_i, cbe_i, frame_i, irdy_i, devsel_o, + trdy_o, adrcfg_i, adrmem_i, pciadrLD_o, pcidOE_o, parOE_o, wbdatLD_o, + wbrgdMX_o, wbd16MX_o, wrcfg_o, rdcfg_o, wb_sel_o, wb_we_o, wb_stb_o, + wb_cyc_o, wb_ack_i, wb_err_i, debug_init, debug_access ); + + // General + input clk_i; + input nrst_i; + // pci + // adr_i + input [3:0] cmd_i; + input [3:0] cbe_i; + input frame_i; + input irdy_i; + output devsel_o; + output trdy_o; + // control + input adrcfg_i; + input adrmem_i; + output pciadrLD_o; + output pcidOE_o; + output reg parOE_o; + output wbdatLD_o; + output wbrgdMX_o; + output wbd16MX_o; + output wrcfg_o; + output rdcfg_o; + // whisbone + output [1:0] wb_sel_o; + output wb_we_o; + inout wb_stb_o; + output wb_cyc_o; + input wb_ack_i; + input wb_err_i; + // debug signals + output reg debug_init; + output reg debug_access; + + //type PciFSM is ( PCIIDLE, B_BUSY, S_DATA1, S_DATA2, TURN_AR ); + //wire pst_pci : PciFSM; + //wire nxt_pci : PciFSM; + + // typedef enum reg [2:0] { + // RED, GREEN, BLUE, CYAN, MAGENTA, YELLOW + // } color_t; + // + // color_t my_color = GREEN; + + // parameter PCIIDLE = 2'b00; + // parameter B_BUSY = 2'b01; + // parameter S_DATA1 = 2'b10; + // parameter S_DATA2 = 2'b11; + // parameter TURN_AR = 3'b100; + + reg [2:0] pst_pci; + reg [2:0] nxt_pci; + + parameter [2:0] + PCIIDLE = 3'b000, + B_BUSY = 3'b001, + S_DATA1 = 3'b010, + S_DATA2 = 3'b011, + TURN_AR = 3'b100; + + + initial begin + pst_pci = 3'b000; + end + + initial begin + nxt_pci = 3'b000; + end + + wire sdata1; + wire sdata2; + wire idleNX; + wire sdata1NX; + wire sdata2NX; + wire turnarNX; + wire idle; + reg devselNX_n; + reg trdyNX_n; + reg devsel; + reg trdy; + wire adrpci; + wire acking; + wire rdcfg; + reg targOE; + reg pcidOE; + + // always @(nrst_i or clk_i or nxt_pci) + always @(negedge nrst_i or posedge clk_i) + begin + if( nrst_i == 0 ) + pst_pci <= PCIIDLE; + else + pst_pci <= nxt_pci; + end + + // always @(negedge nrst_i or posedge clk_i) + always @( pst_pci or frame_i or irdy_i or adrcfg_i or adrpci or acking ) + begin + devselNX_n <= 1'b1; + trdyNX_n <= 1'b1; + case (pst_pci) + PCIIDLE : + begin + if ( frame_i == 0 ) + nxt_pci <= B_BUSY; + else + nxt_pci <= PCIIDLE; + end + B_BUSY: + if ( adrpci == 0 ) + nxt_pci <= TURN_AR; + else + begin + nxt_pci <= S_DATA1; + devselNX_n <= 0; + end + S_DATA1: + if ( acking == 1 ) + begin + nxt_pci <= S_DATA2; + devselNX_n <= 0; + trdyNX_n <= 0; + end + else + begin + nxt_pci <= S_DATA1; + devselNX_n <= 0; + end + S_DATA2: + if ( frame_i == 1 && irdy_i == 0 ) + nxt_pci <= TURN_AR; + else + begin + nxt_pci <= S_DATA2; + devselNX_n <= 0; + trdyNX_n <= 0; + end + TURN_AR: + if ( frame_i == 1 ) + nxt_pci <= PCIIDLE; + else + nxt_pci <= TURN_AR; + endcase + end + + // FSM control signals + assign adrpci = adrmem_i; + + assign acking = ( + ( wb_ack_i == 1 || wb_err_i == 1 ) || + ( adrcfg_i == 1 && irdy_i == 0) + ) ? 1'b1 : 1'b0; + + // FSM derived Control signals + assign idle = ( pst_pci <= PCIIDLE ) ? 1'b1 : 1'b0; + assign sdata1 = ( pst_pci <= S_DATA1 ) ? 1'b1 : 1'b0; + assign sdata2 = ( pst_pci <= S_DATA2 ) ? 1'b1 : 1'b0; + assign idleNX = ( nxt_pci <= PCIIDLE ) ? 1'b1 : 1'b0; + assign sdata1NX = ( nxt_pci <= S_DATA1 ) ? 1'b1 : 1'b0; + assign sdata2NX = ( nxt_pci <= S_DATA2 ) ? 1'b1 : 1'b0; + assign turnarNX = ( nxt_pci <= TURN_AR ) ? 1'b1 : 1'b0; + + // PCI Data Output Enable + // always @( nrst_i or clk_i or cmd_i [0] or sdata1NX or turnarNX ) + always @(negedge nrst_i or posedge clk_i) + begin + if ( nrst_i == 0 ) + pcidOE <= 0; + else + if ( sdata1NX == 1 && cmd_i [0] == 0 ) + pcidOE <= 1; + else + if ( turnarNX == 1 ) + pcidOE <= 0; + end + + assign pcidOE_o = pcidOE; + + // PAR Output Enable + // PCI Read data phase + // PAR is valid 1 cicle after data is valid + // always @( nrst_i or clk_i or cmd_i [0] or sdata2NX or turnarNX ) + always @(negedge nrst_i or posedge clk_i) + begin + if ( nrst_i == 0 ) + parOE_o <= 0; + else + if ( ( sdata2NX == 1 || turnarNX == 1 ) && cmd_i [0] == 0 ) + parOE_o <= 1; + else + parOE_o <= 0; + end + + // Target s/t/s signals OE control + // targOE <= '1' when ( idle = '0' and adrpci = '1' ) else '0'; + // always @( nrst_i or clk_i or sdata1NX or idleNX ) + always @(negedge nrst_i or posedge clk_i) + begin + if ( nrst_i == 0 ) + targOE <= 0; + else + if ( sdata1NX == 1 ) + targOE <= 1; + else + if ( idleNX == 1 ) + targOE <= 0; + end + + // WHISBONE outs + assign wb_cyc_o = (adrmem_i == 1 && sdata1 == 1) ? 1'b1 : 1'b0; + assign wb_stb_o = (adrmem_i == 1 && sdata1 == 1 && irdy_i == 0 ) ? 1'b1 : 1'b0; + + // PCI(Little endian) to WB(Big endian) + assign wb_sel_o [1] = (! cbe_i [0]) || (! cbe_i [2]); + assign wb_sel_o [0] = (! cbe_i [1]) || (! cbe_i [3]); + + assign wb_we_o = cmd_i [0]; + + // Syncronized PCI outs + always @(negedge nrst_i or posedge clk_i) + begin + if( nrst_i == 0 ) + begin + devsel <= 1; + trdy <= 1; + end + else + begin + devsel <= devselNX_n; + trdy <= trdyNX_n; + end + end + + assign devsel_o = ( targOE == 1 ) ? devsel : 1'bZ; + assign trdy_o = ( targOE == 1 ) ? trdy : 1'bZ; + + // rd/wr Configuration Space Registers + assign wrcfg_o = ( + adrcfg_i == 1 && + cmd_i [0] == 1 && + sdata2 == 1 + ) ? 1'b1 : 1'b0; + + assign rdcfg = ( + adrcfg_i == 1 && + cmd_i [0] == 0 && + (sdata1 == 1 || sdata2 == 1) + ) ? 1'b1 : 1'b0; + + assign rdcfg_o = rdcfg; + + // LoaD enable signals + assign pciadrLD_o = ! frame_i; + assign wbdatLD_o = wb_ack_i; + + // Mux control signals + assign wbrgdMX_o = ! rdcfg; + assign wbd16MX_o = (cbe_i [3] == 0 || cbe_i [2] == 0) ? 1'b1 : 1'b0; + + // debug outs + always @(negedge nrst_i or posedge clk_i) + begin + if ( nrst_i == 0 ) + debug_init <= 0; + else + if (devsel == 0) + debug_init <= 1; + end + + always @(negedge nrst_i or posedge clk_i) + begin + if ( nrst_i == 0 ) + debug_access <= 0; + else + if (wb_stb_o == 1) + debug_access <= 1; + end + +endmodule Index: raggedstone/trunk/source/pfs.vhd =================================================================== --- raggedstone/trunk/source/pfs.vhd (nonexistent) +++ raggedstone/trunk/source/pfs.vhd (revision 10) @@ -0,0 +1,35 @@ +--+-----------------------------------------+ +--| pfs | +--+-----------------------------------------+ + +library ieee; +use ieee.std_logic_1164.all; + +entity pfs is +port ( + clk : in std_logic; + a : in std_logic; + y : out std_logic + +); +end pfs; + +architecture rtl of pfs is + + signal a_s : std_logic; + +begin + + SYNCP: process( clk, a ) + begin + + if ( rising_edge(clk) ) then + a_s <= a; + end if; + + end process SYNCP; + + y <= a and (not a_s); + +end rtl; + Index: raggedstone/trunk/source/pcipargen.v =================================================================== --- raggedstone/trunk/source/pcipargen.v (nonexistent) +++ raggedstone/trunk/source/pcipargen.v (revision 10) @@ -0,0 +1,80 @@ +// +// PCI Parity Generator. +// +// PCI Target generates PAR in the data phase of a read cycle. +// The 1's sum on AD, CBE and PAR is even. +// +// Date Version Author Description +// 2005-05-13 R00A00 PAU First alfa revision (eng) +// +// Copyright (C) 2005 Peio Azkarate, peio@opencores.org +// +// This source file is free software; you can redistribute it | +// and/or modify it under the terms of the GNU Lesser General | +// Public License as published by the Free Software Foundation; | +// either version 2.1 of the License, or (at your option) any | +// later version. | + + +module pcipargen_new (clk_i, pcidatout_i, cbe_i, parOE_i, par_o); + + input clk_i; + input [31:0] pcidatout_i; + input [3:0] cbe_i; + input parOE_i; + output par_o; + + + wire [31:0] d; + wire pardat; + wire parcbe; + wire par; + wire par_s; + + assign d = pcidatout_i; + + assign pardat = d[0] ^ d[1] ^ d[2] ^ d[3] ^ d[4] ^ d[5] ^ d[6] ^ d[7] ^ + d[8] ^ d[9] ^ d[10] ^ d[11] ^ d[12] ^ d[13] ^ d[14] ^ d[15] ^ + d[16] ^ d[17] ^ d[18] ^ d[19] ^ d[20] ^ d[21] ^ d[22] ^ d[23] ^ + d[24] ^ d[25] ^ d[26] ^ d[27] ^ d[28] ^ d[29] ^ d[30] ^ d[31]; + + assign parcbe = cbe_i[0] ^ cbe_i[1] ^ cbe_i[2] ^ cbe_i[3]; + + assign par = pardat ^ parcbe; + + // PAR + assign par_o = ( parOE_i == 1 ) ? par_s : 1'bZ; + +endmodule +/* +component sync +port ( + clk : in std_logic; + d : in std_logic; + q : out std_logic +); +end component; + +component sync2 +port ( + clk : in std_logic; + d : in std_logic; + q : out std_logic +); +end component; + +begin + + + + u1: sync2 port map ( + clk => clk_i, + d => par, + q => par_s + ); + + + + +end rtl; +*/ Index: raggedstone/trunk/source/pcidmux.v =================================================================== --- raggedstone/trunk/source/pcidmux.v (nonexistent) +++ raggedstone/trunk/source/pcidmux.v (revision 10) @@ -0,0 +1,55 @@ +// Copyright (C) 2005 Peio Azkarate, peio@opencores.org +// Copyright (C) 2006 Jeff Carr, jcarr@opencores.org +// +// I think what this does is handle 16 vs 32 bit pci accesses + +module pcidmux ( clk_i, nrst_i, d_io, pcidatout_o, pcidOE_i, wbdatLD_i, wbrgdMX_i, + wbd16MX_i, wb_dat_i, wb_dat_o, rg_dat_i, rg_dat_o); + + input clk_i; + input nrst_i; + + // d_io : inout std_logic_vector(31 downto 0); + inout [31:0] d_io; + output [31:0] pcidatout_o; + + input pcidOE_i; + input wbdatLD_i; + input wbrgdMX_i; + input wbd16MX_i; + + input [15:0] wb_dat_i; + output [15:0] wb_dat_o; + input [31:0] rg_dat_i; + output [31:0] rg_dat_o; + + wire [31:0] pcidatin; + wire [31:0] pcidatout; + + reg [15:0] wb_dat_is; + + // always @(negedge nrst_i or posedge clk_i or posedge wbdatLD_i or posedge wb_dat_i) + always @(negedge nrst_i or posedge clk_i) + begin + if ( nrst_i == 0 ) + wb_dat_is <= 16'b1111_1111_1111_1111; + else + if ( wbdatLD_i == 1 ) + wb_dat_is <= wb_dat_i; + end + + assign pcidatin = d_io; + assign d_io = (pcidOE_i == 1'b1 ) ? pcidatout : 32'bZ; + + assign pcidatout [31:24] = (wbrgdMX_i == 1'b1) ? wb_dat_is [7:0] : rg_dat_i [31:24]; + assign pcidatout [23:16] = (wbrgdMX_i == 1'b1) ? wb_dat_is [15:8] : rg_dat_i [23:16]; + assign pcidatout [15:8] = (wbrgdMX_i == 1'b1) ? wb_dat_is [7:0] : rg_dat_i [15:8]; + assign pcidatout [7:0] = (wbrgdMX_i == 1'b1) ? wb_dat_is [15:8] : rg_dat_i [7:0]; + + assign pcidatout_o = pcidatout; + assign rg_dat_o = pcidatin; + + assign wb_dat_o [15:8] = (wbd16MX_i == 1'b1) ? pcidatin [23:16] : pcidatin [7:0]; + assign wb_dat_o [7:0] = (wbd16MX_i == 1'b1) ? pcidatin [31:24] : pcidatin [15:8]; + +endmodule Index: raggedstone/trunk/source/disp_dec.v =================================================================== --- raggedstone/trunk/source/disp_dec.v (nonexistent) +++ raggedstone/trunk/source/disp_dec.v (revision 10) @@ -0,0 +1,29 @@ +module disp_dec(disp_dec_in, disp_dec_out); + input [3:0] disp_dec_in; + output reg [6:0] disp_dec_out; + + always @(disp_dec_in) + begin + case (disp_dec_in) + 4'b0000: disp_dec_out <= 7'b1000000; + 4'b0001: disp_dec_out <= 7'b1111001; + 4'b0010: disp_dec_out <= 7'b0100100; + 4'b0011: disp_dec_out <= 7'b0110000; + + 4'b0100: disp_dec_out <= 7'b0011001; + 4'b0101: disp_dec_out <= 7'b0010010; + 4'b0110: disp_dec_out <= 7'b0000010; + 4'b0111: disp_dec_out <= 7'b1111000; + + 4'b1000: disp_dec_out <= 7'b0000000; + 4'b1001: disp_dec_out <= 7'b0010000; + 4'b1010: disp_dec_out <= 7'b0001000; + 4'b1011: disp_dec_out <= 7'b0000011; + + 4'b1100: disp_dec_out <= 7'b1000110; + 4'b1101: disp_dec_out <= 7'b0100001; + 4'b1110: disp_dec_out <= 7'b0000110; + 4'b1111: disp_dec_out <= 7'b0001110; + endcase + end +endmodule Index: raggedstone/trunk/pci_7seg.ut =================================================================== --- raggedstone/trunk/pci_7seg.ut (nonexistent) +++ raggedstone/trunk/pci_7seg.ut (revision 10) @@ -0,0 +1,27 @@ + +-w +-g DebugBitstream:No +-g Binary:no +-g CRC:Enable +-g ConfigRate:6 +-g CclkPin:PullUp +-g M0Pin:PullUp +-g M1Pin:PullUp +-g M2Pin:PullUp +-g ProgPin:PullUp +-g DonePin:PullUp +-g TckPin:PullUp +-g TdiPin:PullUp +-g TdoPin:PullUp +-g TmsPin:PullUp +-g UnusedPin:PullUp +-g UserID:0xFFFFFFFF +-g DCIUpdateMode:AsRequired +-g StartUpClk:CClk +-g DONE_cycle:4 +-g GTS_cycle:5 +-g GWE_cycle:6 +-g LCK_cycle:NoWait +-g Security:None +-g DonePipe:No +-g DriveDone:No Index: raggedstone/trunk/pci_7seg.prj =================================================================== --- raggedstone/trunk/pci_7seg.prj (nonexistent) +++ raggedstone/trunk/pci_7seg.prj (revision 10) @@ -0,0 +1,16 @@ +verilog work "source/sync.v" +verilog work "source/disp_dec.v" +verilog work "source/wb_7seg.v" +verilog work "source/pcidec.v" +verilog work "source/pcidmux.v" + +verilog work "source/pciwbsequ.v" +verilog work "source/pcipargen.v" + +vhdl work "source/pciwbsequ.vhd" +vhdl work "source/pfs.vhd" +vhdl work "source/new_pciregs.vhd" +vhdl work "source/pcipargen.vhd" +vhdl work "source/new_pci32tlite.vhd" +vhdl work "source/vga_main.vhd" +vhdl work "source/top_pci_7seg.vhd" Index: raggedstone/trunk/pci_7seg.ucf =================================================================== --- raggedstone/trunk/pci_7seg.ucf (nonexistent) +++ raggedstone/trunk/pci_7seg.ucf (revision 10) @@ -0,0 +1,68 @@ +NET "DISP_LED<0>" LOC = "AB20" | IOSTANDARD = LVCMOS33 ; +NET "DISP_LED<1>" LOC = "AA20" | IOSTANDARD = LVCMOS33 ; +NET "DISP_LED<2>" LOC = "V18" | IOSTANDARD = LVCMOS33 ; +NET "DISP_LED<3>" LOC = "Y17" | IOSTANDARD = LVCMOS33 ; +NET "DISP_LED<4>" LOC = "AB18" | IOSTANDARD = LVCMOS33 ; +NET "DISP_LED<5>" LOC = "AA18" | IOSTANDARD = LVCMOS33 ; +NET "DISP_LED<6>" LOC = "W18" | IOSTANDARD = LVCMOS33 ; +NET "DISP_SEL<0>" LOC = "AA17" | IOSTANDARD = LVCMOS33 ; +NET "DISP_SEL<1>" LOC = "U17" | IOSTANDARD = LVCMOS33 ; +NET "DISP_SEL<2>" LOC = "U16" | IOSTANDARD = LVCMOS33 ; +NET "DISP_SEL<3>" LOC = "U14" | IOSTANDARD = LVCMOS33 ; +NET "LED_ACCESS" LOC = "AB5" | IOSTANDARD = LVCMOS33 ; +NET "LED_INIT" LOC = "AA5" | IOSTANDARD = LVCMOS33 ; +NET "PCI_AD<0>" LOC = "A5" | IOSTANDARD = PCI33_3 ; +NET "PCI_AD<10>" LOC = "E9" | IOSTANDARD = PCI33_3 ; +NET "PCI_AD<11>" LOC = "F11" | IOSTANDARD = PCI33_3 ; +NET "PCI_AD<12>" LOC = "E10" | IOSTANDARD = PCI33_3 ; +NET "PCI_AD<13>" LOC = "A8" | IOSTANDARD = PCI33_3 ; +NET "PCI_AD<14>" LOC = "B9" | IOSTANDARD = PCI33_3 ; +NET "PCI_AD<15>" LOC = "B10" | IOSTANDARD = PCI33_3 ; +NET "PCI_AD<16>" LOC = "F17" | IOSTANDARD = PCI33_3 ; +NET "PCI_AD<17>" LOC = "F16" | IOSTANDARD = PCI33_3 ; +NET "PCI_AD<18>" LOC = "A14" | IOSTANDARD = PCI33_3 ; +NET "PCI_AD<19>" LOC = "B14" | IOSTANDARD = PCI33_3 ; +NET "PCI_AD<1>" LOC = "B5" | IOSTANDARD = PCI33_3 ; +NET "PCI_AD<20>" LOC = "B15" | IOSTANDARD = PCI33_3 ; +NET "PCI_AD<21>" LOC = "A15" | IOSTANDARD = PCI33_3 ; +NET "PCI_AD<22>" LOC = "F12" | IOSTANDARD = PCI33_3 ; +NET "PCI_AD<23>" LOC = "F13" | IOSTANDARD = PCI33_3 ; +NET "PCI_AD<24>" LOC = "D15" | IOSTANDARD = PCI33_3 ; +NET "PCI_AD<25>" LOC = "E15" | IOSTANDARD = PCI33_3 ; +NET "PCI_AD<26>" LOC = "D17" | IOSTANDARD = PCI33_3 ; +NET "PCI_AD<27>" LOC = "C17" | IOSTANDARD = PCI33_3 ; +NET "PCI_AD<28>" LOC = "B17" | IOSTANDARD = PCI33_3 ; +NET "PCI_AD<29>" LOC = "E17" | IOSTANDARD = PCI33_3 ; +NET "PCI_AD<2>" LOC = "E6" | IOSTANDARD = PCI33_3 ; +NET "PCI_AD<30>" LOC = "A18" | IOSTANDARD = PCI33_3 ; +NET "PCI_AD<31>" LOC = "B18" | IOSTANDARD = PCI33_3 ; +NET "PCI_AD<3>" LOC = "D6" | IOSTANDARD = PCI33_3 ; +NET "PCI_AD<4>" LOC = "C6" | IOSTANDARD = PCI33_3 ; +NET "PCI_AD<5>" LOC = "B6" | IOSTANDARD = PCI33_3 ; +NET "PCI_AD<6>" LOC = "D7" | IOSTANDARD = PCI33_3 ; +NET "PCI_AD<7>" LOC = "E7" | IOSTANDARD = PCI33_3 ; +NET "PCI_AD<8>" LOC = "B8" | IOSTANDARD = PCI33_3 ; +NET "PCI_AD<9>" LOC = "F10" | IOSTANDARD = PCI33_3 ; +NET "PCI_CBE<0>" LOC = "F9" | IOSTANDARD = PCI33_3 ; +NET "PCI_CBE<1>" LOC = "C10" | IOSTANDARD = PCI33_3 ; +NET "PCI_CBE<2>" LOC = "D13" | IOSTANDARD = PCI33_3 ; +NET "PCI_CBE<3>" LOC = "E13" | IOSTANDARD = PCI33_3 ; +NET "PCI_CLK" LOC = "A11" | IOSTANDARD = PCI33_3 ; +NET "PCI_IDSEL" LOC = "D14" | IOSTANDARD = PCI33_3 ; +NET "PCI_nDEVSEL" LOC = "E12" | IOSTANDARD = PCI33_3 ; +NET "PCI_nFRAME" LOC = "C13" | IOSTANDARD = PCI33_3 ; +NET "PCI_nINT" LOC = "B19" | IOSTANDARD = PCI33_3 | SLEW = FAST ; +NET "PCI_nIRDY" LOC = "A13" | IOSTANDARD = PCI33_3 ; +NET "PCI_nPERR" LOC = "D12" | IOSTANDARD = PCI33_3 | SLEW = FAST ; +NET "PCI_nRES" LOC = "A19" | IOSTANDARD = PCI33_3 ; +NET "PCI_nSERR" LOC = "B12" | IOSTANDARD = PCI33_3 | SLEW = FAST ; +NET "PCI_nSTOP" LOC = "A12" | IOSTANDARD = PCI33_3 | SLEW = FAST ; +NET "PCI_nTRDY" LOC = "B13" | IOSTANDARD = PCI33_3 | SLEW = FAST ; +NET "PCI_PAR" LOC = "A9" | IOSTANDARD = PCI33_3 | SLEW = FAST ; +NET "LED_ALIVE" LOC = "AB4" | IOSTANDARD = LVCMOS33 ; +NET "mclk" LOC = "E22"; +NET "red" LOC = "E21"; +NET "grn" LOC = "F21"; +NET "blu" LOC = "F20"; +NET "hs" LOC = "F19"; +NET "vs" LOC = "G19"; Index: raggedstone/trunk/Makefile =================================================================== --- raggedstone/trunk/Makefile (nonexistent) +++ raggedstone/trunk/Makefile (revision 10) @@ -0,0 +1,81 @@ +PWD := $(shell pwd) + +XST := $(shell which xst) + +TMP = tmp/ +$(shell mkdir tmp) + +PROJECT := pci_7seg + +all: gen_vhdl xst ngdbuild map par trace prom final + +gen_vhdl: + cd source/generate_pci32tlite/ && make + cd source/generate_pciregs/ && make + +log: + time make all &>build.log + +xst: $(PROJECT).ngc + +ngdbuild: $(PROJECT).ngc $(PROJECT).ngd + +$(PROJECT).ngc: + @# echo synclib > $(PROJECT).lso # hmm. things are different in ise 9.1 + echo work >> $(PROJECT).lso + xst -intstyle ise -ifn $(PROJECT).xst -ofn $(PROJECT).syr &> tmp/build.xst.log + #cat $(PROJECT).syr + mv $(PROJECT).syr $(TMP) + mv $(PROJECT).ngr $(PROJECT).lso $(TMP) + mv xst $(TMP) + +$(PROJECT).ngd: + ngdbuild -intstyle ise -dd "$(PWD)/_ngo" -nt timestamp -uc $(PROJECT).ucf -p xc3s400-fg456-4 $(PROJECT).ngc $(PROJECT).ngd &> tmp/build.ngdbuild.log + mv $(PROJECT).bld $(TMP) + mv _ngo $(TMP) + +map: + map -intstyle ise -p xc3s400-fg456-4 -cm area -pr b -k 4 -c 100 -o $(PROJECT)_map.ncd $(PROJECT).ngd $(PROJECT).pcf &> tmp/build.map.log + mv $(PROJECT)_map.mrp $(PROJECT)_map.ngm $(PROJECT).ngc $(TMP) + +par: + @#par -w -intstyle ise -ol std -n 4 -t 1 $(PROJECT)_map.ncd $(PROJECT).dir $(PROJECT).pcf &> tmp/build.par.log + par -w -intstyle ise -ol std -t 1 $(PROJECT)_map.ncd $(PROJECT).ncd $(PROJECT).pcf &> tmp/build.par.log + mv $(PROJECT).xpi $(PROJECT).par $(PROJECT).pad $(TMP) + mv $(PROJECT)_pad.csv $(PROJECT)_pad.txt $(TMP) + +trace: + trce -intstyle ise -e 3 -l 3 -s 4 -xml $(PROJECT) $(PROJECT).ncd -o $(PROJECT).twr $(PROJECT).pcf &> tmp/build.trce.log + #cat $(PROJECT).twr + mv $(PROJECT).twr $(TMP) + mv $(PROJECT).twx $(TMP) + mv $(PROJECT)_map.ncd $(PROJECT).ngd $(PROJECT).pcf $(TMP) + +prom: + bitgen -intstyle ise -f $(PROJECT).ut $(PROJECT).ncd &> tmp/build.bitgen.log + # cp $(PROJECT).bit ../jcarr_last.bit + #cat $(PROJECT).drc + mv $(PROJECT).drc $(TMP) + #cat $(PROJECT).bgn + mv $(PROJECT).bgn $(TMP) + +final: + -mv $(PROJECT).unroutes *.xml $(TMP) + -mv $(PROJECT)*.map $(TMP) + -mv $(PROJECT).ncd $(TMP) + -grep -A 8 -B 1 ^Selected\ Device tmp/build.xst.log + -grep -A 8 -B 1 ^Timing\ Summary tmp/build.xst.log + -grep -A 21 -B 1 ^Design\ Summary tmp/build.map.log + +burn: + xc3sprog $(PROJECT).bit + +clean: + rm -rf $(TMP) + rm -rf *.bit *.bgn *.mcs *.prm *.bld *.drc *.mcs *.ncd *.ngc *.ngd + rm -rf *.ngr *.pad *.par *.pcf *.prm *.syr *.twr *.twx *.xpi *.lso + rm -rf $(PROJECT)_map.* $(PROJECT)_pad.* + rm -rf _ngo xst + rm -rf build.log + rm -rf source/new_* + rm -rf $(PROJECT).unroutes *.xml Index: raggedstone/trunk/pci_7seg.xst =================================================================== --- raggedstone/trunk/pci_7seg.xst (nonexistent) +++ raggedstone/trunk/pci_7seg.xst (revision 10) @@ -0,0 +1,51 @@ +set -xsthdpdir ./xst +run +-ifn pci_7seg.prj +-ifmt mixed +-ofn pci_7seg +-ofmt NGC +-p xc3s400-4-fg456 +-top pci_7seg +-opt_mode Speed +-opt_level 1 +-iuc NO +-lso pci_7seg.lso +-keep_hierarchy NO +-glob_opt AllClockNets +-rtlview Yes +-read_cores YES +-write_timing_constraints NO +-cross_clock_analysis NO +-hierarchy_separator / +-bus_delimiter <> +-case maintain +-slice_utilization_ratio 100 +-verilog2001 YES +-fsm_extract YES -fsm_encoding Auto +-safe_implementation No +-fsm_style lut +-ram_extract Yes +-ram_style Auto +-rom_extract Yes +-rom_style Auto +-mux_extract YES +-decoder_extract YES +-priority_extract YES +-shreg_extract YES +-shift_extract YES +-xor_collapse YES +-resource_sharing YES +-mult_style auto +-iobuf YES +-max_fanout 500 +-bufg 8 +-register_duplication YES +-equivalent_register_removal YES +-register_balancing No +-slice_packing YES +-optimize_primitives NO +-use_clock_enable Yes +-use_sync_set Yes +-use_sync_reset Yes +-iob auto +-slice_utilization_ratio_maxmargin 5 Index: raggedstone/trunk =================================================================== --- raggedstone/trunk (nonexistent) +++ raggedstone/trunk (revision 10)

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