URL
https://opencores.org/ocsvn/rise/rise/trunk
Subversion Repositories rise
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- This comparison shows the changes necessary to convert path
/
- from Rev 9 to Rev 10
- ↔ Reverse comparison
Rev 9 → Rev 10
/trunk/vhdl/tb_id_stage_unit.vhd
53,10 → 53,10
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signal stall_in : std_logic := '0'; |
signal clear_in : std_logic := '0'; |
signal rx : REGISTER_T := (others => '0'); |
signal ry : REGISTER_T := (others => '0'); |
signal rz : REGISTER_T := (others => '0'); |
signal sr : SR_REGISTER_T := (others => '0'); |
signal rx : REGISTER_T; |
signal ry : REGISTER_T; |
signal rz : REGISTER_T; |
signal sr : SR_REGISTER_T; |
signal lock_register : LOCK_REGISTER_T; |
--Outputs |
signal id_ex_register : ID_EX_REGISTER_T; |
67,6 → 67,14
signal lock_reg_addr : std_logic_vector(REGISTER_ADDR_WIDTH - 1 downto 0); |
signal stall_out : std_logic; |
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constant TB_RX_ADDR_TEST_VALUE : REGISTER_ADDR_T := x"1"; |
constant TB_RX_TEST_VALUE : REGISTER_T := x"0001"; |
constant TB_RY_TEST_VALUE : REGISTER_T := x"0002"; |
constant TB_RZ_TEST_VALUE : REGISTER_T := x"0003"; |
constant TB_SR_TEST_VALUE : SR_REGISTER_T := x"A55A"; |
constant TB_PC_TEST_VALUE : SR_REGISTER_T := x"1234"; |
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constant TB_CLOCK : time := 20 ns; |
begin |
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-- instantiate the Unit Under Test (UUT) |
93,9 → 101,9
cg : process |
begin |
clk <= '0'; |
wait for 10 ns; |
wait for TB_CLOCK/2; |
clk <= '1'; |
wait for 10 ns; |
wait for TB_CLOCK/2; |
end process; |
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tb : process |
104,10 → 112,35
wait for 100 ns; |
reset <= '1'; |
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-- stimulus |
if_id_register.pc <= x"1234"; |
if_id_register.ir <= "100"& "0" & "0001" & x"55"; |
-- test case: basic functionallity |
if_id_register.pc <= TB_PC_TEST_VALUE; |
sr <= TB_SR_TEST_VALUE; |
rx <= TB_RX_TEST_VALUE; |
ry <= TB_RY_TEST_VALUE; |
rz <= TB_RZ_TEST_VALUE; |
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wait for TB_CLOCK; |
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-- test case: OPCODE_LD_IMM |
if_id_register.ir <= "100"& "0" & TB_RX_ADDR_TEST_VALUE & x"55"; |
wait for TB_CLOCK; |
assert id_ex_register.opcode = OPCODE_LD_IMM; |
assert id_ex_register.immediate = x"0055"; |
assert id_ex_register.cond = COND_UNCONDITIONAL; |
assert rx_addr = TB_RX_ADDR_TEST_VALUE; |
assert id_ex_register.rX_addr = TB_RX_ADDR_TEST_VALUE; |
assert id_ex_register.rX = TB_RX_TEST_VALUE; |
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-- test case: OPCODE_LD_IMM_HB |
if_id_register.ir <= "100"& "1" & TB_RX_ADDR_TEST_VALUE & x"55"; |
wait for TB_CLOCK; |
assert id_ex_register.opcode = OPCODE_LD_IMM_HB; |
assert id_ex_register.immediate = x"5500"; |
assert id_ex_register.cond = COND_UNCONDITIONAL; |
assert rx_addr = TB_RX_ADDR_TEST_VALUE; |
assert id_ex_register.rX_addr = TB_RX_ADDR_TEST_VALUE; |
assert id_ex_register.rX = TB_RX_TEST_VALUE; |
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wait; -- will wait forever |
end process; |
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