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URL https://opencores.org/ocsvn/srdydrdy_lib/srdydrdy_lib/trunk

Subversion Repositories srdydrdy_lib

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    from Rev 9 to Rev 10
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Rev 9 → Rev 10

/srdydrdy_lib/trunk/rtl/verilog/forks/sd_rrslow.v
61,6 → 61,7
reg [$clog2(inputs)-1:0] data_ind;
 
wire [width-1:0] rr_mux_grid [0:inputs-1];
reg rr_locked;
genvar i;
integer j;
wire trig_pattern;
75,7 → 76,7
 
if (mode == 2)
begin : tp_gen
reg rr_locked, nxt_rr_locked;
reg nxt_rr_locked;
assign trig_pattern = (rr_mux_grid[data_ind] & eod_mask) == eod_pattern;
always @*
125,7 → 126,7
nxt_rr_state = rr_state;
else if ((mode == 0) & !p_drdy)
nxt_rr_state = rr_state;
else if ((mode == 2) & (locked | (c_srdy & rr_state)))
else if ((mode == 2) & (rr_locked | (c_srdy & rr_state)))
nxt_rr_state = rr_state;
else
nxt_rr_state = { rr_state[0], rr_state[inputs-1:1] };

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