OpenCores
URL https://opencores.org/ocsvn/storm_core/storm_core/trunk

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Rev 9 → Rev 10

/storm_core/trunk/arm asm/test.s
0,0 → 1,39
/* ### DEMO PROGRAM: FIBONACCI NUMBERS ###
---------------------------------------------
Calculates and stores the first 30 Fibonacci
numbers and stores them in the internal memory,
starting at word location 25 (byte loaction 100). */
 
/*-----------------------------------------------------
Exception Vectors
-----------------------------------------------------*/
 
Vectors: BAL Reset /* Hardware Reset */
NOP /* Undef Instruction */
NOP /* Software INT */
NOP /* Prefetch Abort */
NOP /* Data Abort */
NOP /* Reserved */
NOP /* HW INT req */
NOP /* Fast HW INT req */
 
/*-----------------------------------------------------
Reset Handler
-----------------------------------------------------*/
 
Reset: MOV R0, #0 /* A */
MOV R1, #1 /* B */
MOV R2, #0 /* C */
MOV R3, #100 /* mem area to place results */
 
LOOP: CMP R3, #220
BEQ WAYNE
 
STR R0, [R3], #4
ADD R2, R0, R1
MOV R0, R1
MOV R1, R2
 
BAL LOOP
 
WAYNE: BAL WAYNE
/storm_core/trunk/arm asm/mnemonic.txt
0,0 → 1,21
000000 => x"EA000006",
000001 => x"E1A00000",
000002 => x"E1A00000",
000003 => x"E1A00000",
000004 => x"E1A00000",
000005 => x"E1A00000",
000006 => x"E1A00000",
000007 => x"E1A00000",
000008 => x"E3A00000",
000009 => x"E3A01001",
000010 => x"E3A02000",
000011 => x"E3A03064",
000012 => x"E35300DC",
000013 => x"0A000004",
000014 => x"E4830004",
000015 => x"E0802001",
000016 => x"E1A00001",
000017 => x"E1A01002",
000018 => x"EAFFFFF8",
000019 => x"EAFFFFFE",
others => x"F0013007"
/storm_core/trunk/arm asm/arm-elf-as.exe Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/storm_core/trunk/arm asm/arm-elf-as.exe
storm_core/trunk/arm asm/arm-elf-as.exe Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: storm_core/trunk/arm asm/a.out =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: storm_core/trunk/arm asm/a.out =================================================================== --- storm_core/trunk/arm asm/a.out (nonexistent) +++ storm_core/trunk/arm asm/a.out (revision 10)
storm_core/trunk/arm asm/a.out Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: storm_core/trunk/arm asm/extract.exe =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: storm_core/trunk/arm asm/extract.exe =================================================================== --- storm_core/trunk/arm asm/extract.exe (nonexistent) +++ storm_core/trunk/arm asm/extract.exe (revision 10)
storm_core/trunk/arm asm/extract.exe Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: storm_core/trunk/arm asm/mnemonic.dat =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: storm_core/trunk/arm asm/mnemonic.dat =================================================================== --- storm_core/trunk/arm asm/mnemonic.dat (nonexistent) +++ storm_core/trunk/arm asm/mnemonic.dat (revision 10)
storm_core/trunk/arm asm/mnemonic.dat Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: storm_core/trunk/arm asm/compile.bat =================================================================== --- storm_core/trunk/arm asm/compile.bat (nonexistent) +++ storm_core/trunk/arm asm/compile.bat (revision 10) @@ -0,0 +1,4 @@ +@echo off +color 0a +arm-elf-as.exe -EB -mapcs-32 -mcpu=arm7tdmi test.s +extract.exe \ No newline at end of file Index: storm_core/trunk/rtl/ARITHMETICAL_UNIT.vhd =================================================================== --- storm_core/trunk/rtl/ARITHMETICAL_UNIT.vhd (nonexistent) +++ storm_core/trunk/rtl/ARITHMETICAL_UNIT.vhd (revision 10) @@ -0,0 +1,158 @@ +-- ####################################################### +-- # < STORM CORE PROCESSOR by Stephan Nolting > # +-- # *************************************************** # +-- # Arithmetical Operation Unit # +-- # *************************************************** # +-- # Version 1.5.0, 19.03.2011 # +-- ####################################################### + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +library work; +use work.STORM_core_package.all; + +entity ARITHMETICAL_UNIT is + port ( + -- Function Operands -- + -------------------------------------------------- + OP_A : in STD_LOGIC_VECTOR(31 downto 00); + OP_B : in STD_LOGIC_VECTOR(31 downto 00); + RESULT : out STD_LOGIC_VECTOR(31 downto 00); + + -- Flag Operands -- + -------------------------------------------------- + BS_OVF_IN : in STD_LOGIC; + A_CARRY_IN : in STD_LOGIC; + FLAG_OUT : out STD_LOGIC_VECTOR(03 downto 00); + + -- Operation Control -- + -------------------------------------------------- + CTRL : in STD_LOGIC_VECTOR(02 downto 00) + ); +end ARITHMETICAL_UNIT; + +architecture Behavioral of ARITHMETICAL_UNIT is + + -- local signals -- + signal ADD_MODE : STD_LOGIC_VECTOR(02 downto 00); -- adder mode control + signal ADDER_RES : STD_LOGIC_VECTOR(32 downto 00); -- adder/subtractor result + signal CARRY_OUT : STD_LOGIC; -- internal carry output + + +begin + + -- Arithmetical Unit ----------------------------------------------------------------------------------- + -- -------------------------------------------------------------------------------------------------------- + ARITHMETICAL_CORE: process(CTRL, ADDER_RES, OP_A, OP_B) + begin + case(ARITHMETICAL_OP & CTRL) is -- Arithmetic Function Set + + -- ADD: result = OP_A + OP_B -- + when A_ADD => + ADD_MODE <= "000"; + RESULT <= ADDER_RES(31 downto 0); + + -- ADC: result = OP_A + OP_B + Carry-Flag -- + when A_ADC => + ADD_MODE <= "100"; + RESULT <= ADDER_RES(31 downto 0); + + -- SUB: result = OP_A - OP_B -- + when A_SUB => + ADD_MODE <= "001"; + RESULT <= ADDER_RES(31 downto 0); + + -- SBC: result = OP_A - OP_B - Carry-Flag -- + when A_SBC => + ADD_MODE <= "101"; + RESULT <= ADDER_RES(31 downto 0); + + -- RSB: result = OP_B - OP_A -- + when A_RSB => + ADD_MODE <= "010"; + RESULT <= ADDER_RES(31 downto 0); + + -- RSC: result = OP_B - OP_A - Carry-Flag -- + when A_RSC => + ADD_MODE <= "110"; + RESULT <= ADDER_RES(31 downto 0); + + -- CMP: result = OP_B, compares by F = OP_A - OP_B -- + when A_CMP => + ADD_MODE <= "001"; + RESULT <= OP_B; + + -- CMN: result = OP_A, compares by F = OP_A + OP_B -- + when A_CMN => + ADD_MODE <= "000"; + RESULT <= OP_A; + + -- Undefined -- + when others => + ADD_MODE <= (others => '0'); + RESULT <= (others => '0'); + + end case; + end process ARITHMETICAL_CORE; + + + + -- Adder/Subtractor ------------------------------------------------------------------------------------ + -- -------------------------------------------------------------------------------------------------------- + ADDER_SUBTRACTOR: process(ADD_MODE, OP_A, OP_B, A_CARRY_IN, ADDER_RES) + variable ADDER_A, ADDER_B : std_logic_vector(32 downto 00); + variable CARRY_IN : std_logic_vector(00 downto 00); + begin + ADDER_A(32) := '0'; + ADDER_B(32) := '0'; + case (ADD_MODE(1 downto 0)) is + + when "00" => -- (+OP_A) + (+OP_B) + ADDER_A(31 downto 0) := OP_A; + ADDER_B(31 downto 0) := OP_B; + + when "01" => -- (+OP_A) + (-OP_B) + ADDER_A(31 downto 0) := OP_A; + ADDER_B(31 downto 0) := not OP_B; + + when "10" => -- (-OP_A) + (+OP_B) + ADDER_A(31 downto 0) := not OP_A; + ADDER_B(31 downto 0) := OP_B; + + when others => -- invalid + ADDER_A(32 downto 0) := (others => '-'); + ADDER_B(32 downto 0) := (others => '-'); + + end case; + + -- carry input logic -- + CARRY_IN(0) := (ADD_MODE(2) and A_CARRY_IN) xor (ADD_MODE(0) or ADD_MODE(1)); + + -- adder/subtractor -- + ADDER_RES <= std_logic_vector(unsigned(ADDER_A) + unsigned(ADDER_B) + unsigned(CARRY_IN(0 downto 0))); + + -- carry output logic -- + CARRY_OUT <= ADDER_RES(32) xor (ADD_MODE(0) or ADD_MODE(1)); + + end process ADDER_SUBTRACTOR; + + + + -- FLAG Logic ------------------------------------------------------------------------------------------ + -- -------------------------------------------------------------------------------------------------------- + -- carry flag -- + FLAG_OUT(0) <= CARRY_OUT; + + -- zero flag -- + FLAG_OUT(1) <= '1' when (ADDER_RES(31 downto 0) = x"00000000") else '0'; + + -- negative flag -- + FLAG_OUT(2) <= ADDER_RES(31); -- negative flag + + -- overflow flag -- + FLAG_OUT(3) <= (ADDER_RES(31) and (OP_A(31) xnor OP_B(31)));-- or BS_OVF_IN; + + +end Behavioral; \ No newline at end of file Index: storm_core/trunk/rtl/WISHBONE_IO.vhd =================================================================== --- storm_core/trunk/rtl/WISHBONE_IO.vhd (nonexistent) +++ storm_core/trunk/rtl/WISHBONE_IO.vhd (revision 10) @@ -0,0 +1,116 @@ +-- ###################################################### +-- # < STORM CORE SYSTEM by Stephan Nolting > # +-- # ************************************************** # +-- # Wihbone Interface Unit # +-- # -------------------------------------------------- # +-- # # +-- # ************************************************** # +-- # Version 1.0.0, 19.07.2011 # +-- ###################################################### + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +library work; +use work.STORM_core_package.all; + +entity WISHBONE_IO is + port ( +-- ############################################################################################### +-- ## Global Control ## +-- ############################################################################################### + + CLK_I : in STD_LOGIC; -- clock signal, rising edge + RST_I : in STD_LOGIC; -- reset signal, sync, active high + +-- ############################################################################################### +-- ## Access Port ## +-- ############################################################################################### + + AP_ADR_I : in STD_LOGIC_VECTOR(31 downto 00); -- address + AP_WR_DATA_I : in STD_LOGIC_VECTOR(31 downto 00); -- write data + AP_RD_DATA_O : out STD_LOGIC_VECTOR(31 downto 00); -- read data + AP_BYTE_SEL_I : in STD_LOGIC_VECTOR(03 downto 00); -- byte select + AP_RW_I : in STD_LOGIC; -- read/write + AP_CS_I : in STD_LOGIC; -- chip select + AP_DONE_O : out STD_LOGIC; -- device is busy + +-- ############################################################################################### +-- ## Wishbone Port ## +-- ############################################################################################### + + WB_DATA_I : in STD_LOGIC_VECTOR(31 downto 0); + WB_DATA_O : out STD_LOGIC_VECTOR(31 downto 0); + WB_ADR_O : out STD_LOGIC_VECTOR(31 downto 0); + WB_ACK_I : in STD_LOGIC; + WB_SEL_O : out STD_LOGIC_VECTOR(03 downto 0); + WB_WE_O : out STD_LOGIC; + WB_STB_O : out STD_LOGIC; + WB_CYC_O : out STD_LOGIC + + ); +end WISHBONE_IO; + +architecture Structure of WISHBONE_IO is + + -- use data isolation when not using WB -- + constant use_isolation : boolean := FALSE; + + -- ready flag -- + signal RDY_FLAG : STD_LOGIC; + +begin + + -- WISHBONE Interface Arbiter ------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + WB_ARBITER: process (CLK_I, RST_I, AP_CS_I, WB_ACK_I, WB_DATA_I) + begin + if rising_edge(CLK_I) then + if (RST_I = '1') then + RDY_FLAG <= '1'; -- ready as default + AP_RD_DATA_O <= (others => '0'); + elsif (AP_CS_I = '1') then + RDY_FLAG <= WB_ACK_I; + AP_RD_DATA_O <= WB_DATA_I; + end if; + end if; + end process WB_ARBITER; + + + -- ready output -- + AP_DONE_O <= RDY_FLAG; + + -- wb cycle ctrl -- + WB_STB_O <= AP_CS_I and RDY_FLAG; + WB_CYC_O <= AP_CS_I and RDY_FLAG; + + + + -- WISHBONE Interface Operant Output ------------------------------------------------------ + -- ------------------------------------------------------------------------------------------- + WB_OPERAND_OUT: process(AP_CS_I, AP_ADR_I, AP_WR_DATA_I, AP_BYTE_SEL_I, AP_RW_I) + begin + if (use_isolation = true) then + if (AP_CS_I = '1') then + WB_ADR_O <= AP_ADR_I; + WB_DATA_O <= AP_WR_DATA_I; + WB_SEL_O <= AP_BYTE_SEL_I; + WB_WE_O <= AP_RW_I; + else + WB_ADR_O <= (others => '0'); + WB_DATA_O <= (others => '0'); + WB_SEL_O <= (others => '0'); + WB_WE_O <= '0'; + end if; + else + WB_ADR_O <= AP_ADR_I; + WB_DATA_O <= AP_WR_DATA_I; + WB_SEL_O <= AP_BYTE_SEL_I; + WB_WE_O <= AP_RW_I; + end if; + end process WB_OPERAND_OUT; + + + +end Structure; \ No newline at end of file Index: storm_core/trunk/rtl/X1_OPCODE_DECODER.vhd =================================================================== --- storm_core/trunk/rtl/X1_OPCODE_DECODER.vhd (nonexistent) +++ storm_core/trunk/rtl/X1_OPCODE_DECODER.vhd (revision 10) @@ -0,0 +1,589 @@ +-- ####################################################### +-- # < STORM CORE PROCESSOR by Stephan Nolting > # +-- # *************************************************** # +-- # ARM-Native OPCODE Decoding Unit # +-- # *************************************************** # +-- # Version 2.4.6, 01.09.2011 # +-- ####################################################### + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +library work; +use work.STORM_core_package.all; + +-- ############################################################################################### +-- ## Interface ## +-- ############################################################################################### + +entity X1_OPCODE_DECODER is + Port ( + OPCODE_DATA_IN : in STD_LOGIC_VECTOR(31 downto 0); + OPCODE_CTRL_IN : in STD_LOGIC_VECTOR(15 downto 0); + OPCODE_CTRL_OUT : out STD_LOGIC_VECTOR(99 downto 0) + ); +end X1_OPCODE_DECODER; + +architecture instruction_decoder of X1_OPCODE_DECODER is + +-- ############################################################################################### +-- ## Local Signals ## +-- ############################################################################################### + + -- INPUTS -- + signal INSTR_REG : STD_LOGIC_VECTOR(31 downto 00); + signal DUAL_OP : STD_LOGIC; + + -- OUTPUTS -- + signal DEC_CTRL : STD_LOGIC_VECTOR(31 downto 00); + signal OP_ADR_OUT : STD_LOGIC_VECTOR(11 downto 00); + signal IMM_OUT : STD_LOGIC_VECTOR(31 downto 00); + signal SHIFT_M_OUT : STD_LOGIC_VECTOR(01 downto 00); + signal SHIFT_C_OUT : STD_LOGIC_VECTOR(04 downto 00); + signal NEXT_DUAL_OP : STD_LOGIC; + signal REG_SEL : STD_LOGIC_VECTOR(14 downto 12); -- weird, huh!? ^^ + +begin + + -- ############################################################################################### + -- ## Internal Signal Connection ## + -- ############################################################################################### + + INSTR_REG <= OPCODE_DATA_IN; + DUAL_OP <= OPCODE_CTRL_IN(0); + + OPCODE_CTRL_OUT(31 downto 00) <= DEC_CTRL; + OPCODE_CTRL_OUT(43 downto 32) <= OP_ADR_OUT; + OPCODE_CTRL_OUT(46 downto 44) <= REG_SEL; + OPCODE_CTRL_OUT(78 downto 47) <= IMM_OUT; + OPCODE_CTRL_OUT(80 downto 79) <= SHIFT_M_OUT; + OPCODE_CTRL_OUT(85 downto 81) <= SHIFT_C_OUT; + OPCODE_CTRL_OUT(86) <= NEXT_DUAL_OP; + OPCODE_CTRL_OUT(99 downto 87) <= (others => '0'); -- unused + + + -- ############################################################################################### + -- ## ARM COMPATIBLE OPCODE DECODER ## + -- ############################################################################################### + + OPCODE_DECODER: process (INSTR_REG, DUAL_OP) + variable temp_3, temp_4, temp_5 : std_logic_vector(2 downto 0); + variable B_TEMP_1, B_TEMP_2 : std_logic_vector(1 downto 0); + begin + + --- DEFAULT CONTROL --- + DEC_CTRL <= (others => '0'); + DEC_CTRL(CTRL_RD_3 downto CTRL_RD_0) <= INSTR_REG(15 downto 12); -- R_DEST + DEC_CTRL(CTRL_COND_3 downto CTRL_COND_0) <= INSTR_REG(31 downto 28); -- Condition + + OP_ADR_OUT(OP_A_ADR_3 downto OP_A_ADR_0) <= INSTR_REG(19 downto 16); + OP_ADR_OUT(OP_B_ADR_3 downto OP_B_ADR_0) <= INSTR_REG(03 downto 00); + OP_ADR_OUT(OP_C_ADR_3 downto OP_C_ADR_0) <= INSTR_REG(11 downto 08); + REG_SEL <= (others => '0'); -- all operands are anything but registers + IMM_OUT <= (others => '0'); + SHIFT_C_OUT <= (others => '0'); + SHIFT_M_OUT <= (others => '0'); + NEXT_DUAL_OP <= '0'; + + --- INSTRUCTION CLASS DECODER --- + case INSTR_REG(27 downto 26) is + + when "00" => -- ALU DATA PROCESSING / SREG ACCESS / MUL(MAC) / (S/U/HW/B) MEM ACCESS + -- =================================================================================== + DEC_CTRL(CTRL_AF) <= INSTR_REG(20); -- ALTER_FLAGS + DEC_CTRL(CTRL_WB_EN) <= '1'; -- WB_ENABLE + DEC_CTRL(CTRL_CONST) <= INSTR_REG(25); -- IS_CONST + DEC_CTRL(CTRL_MREG_M) <= INSTR_REG(22); -- CMSR/SMSR access + DEC_CTRL(CTRL_MREG_RW) <= INSTR_REG(21); -- read/write access + DEC_CTRL(CTRL_MREG_FA) <= not INSTR_REG(16); -- only flag access? + + if ((INSTR_REG(27 downto 22) = "000000") and (INSTR_REG(7 downto 4) = "1001")) then + -- MUL/MAC + ---------------------------------------------------------------------------------- + DEC_CTRL(CTRL_MS) <= '1'; -- select multiplicator + DEC_CTRL(CTRL_RD_3 downto CTRL_RD_0) <= INSTR_REG(19 downto 16); + OP_ADR_OUT(OP_A_ADR_3 downto OP_A_ADR_0) <= INSTR_REG(15 downto 12); + OP_ADR_OUT(OP_B_ADR_3 downto OP_B_ADR_0) <= INSTR_REG(11 downto 08); + OP_ADR_OUT(OP_C_ADR_3 downto OP_C_ADR_0) <= INSTR_REG(03 downto 00); + REG_SEL(OP_B_IS_REG) <= '1'; -- OP B is always reg + REG_SEL(OP_C_IS_REG) <= '1'; -- OP C is always reg + if (INSTR_REG(21) = '1') then -- perform MAC operation + DEC_CTRL(CTRL_ALU_FS_3 downto CTRL_ALU_FS_0) <= A_ADD; + REG_SEL(OP_A_IS_REG) <= '1'; + else -- perform MUL operation + DEC_CTRL(CTRL_ALU_FS_3 downto CTRL_ALU_FS_0) <= PassB; + REG_SEL(OP_A_IS_REG) <= '0'; + end if; + + elsif (INSTR_REG(27 downto 25) = "000") and (INSTR_REG(7) = '1') and (INSTR_REG(4) = '1') then + -- Halfword / Signed Data Transfer / Data Swap + ---------------------------------------------------------------------------------- + DEC_CTRL(CTRL_RD_3 downto CTRL_RD_0) <= INSTR_REG(15 downto 12); -- R_DATA + OP_ADR_OUT(OP_A_ADR_3 downto OP_A_ADR_0) <= INSTR_REG(19 downto 16); -- BASE + OP_ADR_OUT(OP_B_ADR_3 downto OP_B_ADR_0) <= INSTR_REG(03 downto 00); -- Offset + OP_ADR_OUT(OP_C_ADR_3 downto OP_C_ADR_0) <= INSTR_REG(15 downto 12); -- W_DATA + IMM_OUT <= x"000000" & INSTR_REG(11 downto 08) & INSTR_REG(03 downto 00); -- IMMEDIATE + DEC_CTRL(CTRL_CONST) <= not INSTR_REG(22); -- IS_CONST + + case (INSTR_REG(5 downto 4)) is + when "00" => -- WORD + DEC_CTRL(CTRL_MEM_DQ_1 downto CTRL_MEM_DQ_0) <= DQ_WORD; + DEC_CTRL(CTRL_MEM_SE) <= '0'; + when "01" => -- unsigned HALFWORD + DEC_CTRL(CTRL_MEM_DQ_1 downto CTRL_MEM_DQ_0) <= DQ_HALFWORD; + DEC_CTRL(CTRL_MEM_SE) <= '0'; + when "10" => -- signed BYTE + DEC_CTRL(CTRL_MEM_DQ_1 downto CTRL_MEM_DQ_0) <= DQ_BYTE; + DEC_CTRL(CTRL_MEM_SE) <= '1'; + when others => -- signed HALFWORD + DEC_CTRL(CTRL_MEM_DQ_1 downto CTRL_MEM_DQ_0) <= DQ_HALFWORD; + DEC_CTRL(CTRL_MEM_SE) <= '1'; + end case; + + if (INSTR_REG(23) = '0') then -- sub index + DEC_CTRL(CTRL_ALU_FS_3 downto CTRL_ALU_FS_0) <= A_SUB; -- ALU_CTRL = SUB + else -- add index + DEC_CTRL(CTRL_ALU_FS_3 downto CTRL_ALU_FS_0) <= A_ADD; -- ALU_CTRL = ADD + end if; + + temp_5 := INSTR_REG(20) & INSTR_REG(24) & INSTR_REG(21); + case temp_5 is -- L_P_W + + when "110" => -- load, pre indexing, no write back + ---------------------------------------------------------------------------------- + DEC_CTRL(CTRL_RD_3 downto CTRL_RD_0) <= INSTR_REG(15 downto 12); -- R_DEST + DEC_CTRL(CTRL_MEM_ACC) <= '1'; -- MEM_ACCESS + DEC_CTRL(CTRL_MEM_RW) <= '0'; -- MEM_READ + DEC_CTRL(CTRL_WB_EN) <= '1'; -- WB EN + NEXT_DUAL_OP <= '0'; + REG_SEL(OP_A_IS_REG) <= '1'; + REG_SEL(OP_B_IS_REG) <= not INSTR_REG(22); + REG_SEL(OP_C_IS_REG) <= '0'; + + when "111" => -- load, pre indexing, write back + ---------------------------------------------------------------------------------- + if (DUAL_OP = '0') then -- ADD/SUB Ra,Ra,Op_B + DEC_CTRL(CTRL_RD_3 downto CTRL_RD_0) <= INSTR_REG(19 downto 16); -- R_DEST + DEC_CTRL(CTRL_MEM_ACC) <= '0'; -- MEM_ACCESS + DEC_CTRL(CTRL_WB_EN) <= '1'; -- WB EN + NEXT_DUAL_OP <= '1'; + REG_SEL(OP_A_IS_REG) <= '1'; + REG_SEL(OP_B_IS_REG) <= not INSTR_REG(22); + REG_SEL(OP_C_IS_REG) <= '0'; + + else -- LD Rd, Ra + DEC_CTRL(CTRL_RD_3 downto CTRL_RD_0) <= INSTR_REG(15 downto 12); -- R_DEST + DEC_CTRL(CTRL_MEM_ACC) <= '1'; -- MEM_ACCESS + DEC_CTRL(CTRL_WB_EN) <= '1'; -- WB EN + NEXT_DUAL_OP <= '0'; + DEC_CTRL(CTRL_ALU_FS_3 downto CTRL_ALU_FS_0) <= PassA; -- ALU_CTRL = PassA + REG_SEL(OP_A_IS_REG) <= '1'; + REG_SEL(OP_B_IS_REG) <= '0'; + REG_SEL(OP_C_IS_REG) <= '0'; + end if; + + + when "100" | "101" => -- load, post indexing, allways write back + ---------------------------------------------------------------------------------- + if (DUAL_OP = '0') then -- LD Rd,Ra + DEC_CTRL(CTRL_RD_3 downto CTRL_RD_0) <= INSTR_REG(15 downto 12); -- R_DEST + DEC_CTRL(CTRL_MEM_ACC) <= '1'; -- MEM_ACCESS + DEC_CTRL(CTRL_MEM_RW) <= '0'; -- MEM_READ + DEC_CTRL(CTRL_WB_EN) <= '1'; -- WB EN + DEC_CTRL(CTRL_MEM_USER) <= INSTR_REG(21); -- access in pseudo-user-mode + NEXT_DUAL_OP <= '1'; + DEC_CTRL(CTRL_ALU_FS_3 downto CTRL_ALU_FS_0) <= PassA; -- ALU_CTRL = PassA + REG_SEL(OP_A_IS_REG) <= '1'; + REG_SEL(OP_B_IS_REG) <= '0'; + REG_SEL(OP_C_IS_REG) <= '0'; + + else -- ADD/SUB Ra,Ra,Op_B + DEC_CTRL(CTRL_RD_3 downto CTRL_RD_0) <= INSTR_REG(19 downto 16); -- R_DEST + DEC_CTRL(CTRL_MEM_ACC) <= '0'; -- MEM_ACCESS + DEC_CTRL(CTRL_WB_EN) <= '1'; -- WB EN + NEXT_DUAL_OP <= '0'; + REG_SEL(OP_A_IS_REG) <= '1'; + REG_SEL(OP_B_IS_REG) <= not INSTR_REG(22); + REG_SEL(OP_C_IS_REG) <= '0'; + end if; + + + when "010" => -- store, pre indexing, no write back + ---------------------------------------------------------------------------------- + DEC_CTRL(CTRL_RD_3 downto CTRL_RD_0) <= "0000"; -- R_DEST wayne + DEC_CTRL(CTRL_MEM_ACC) <= '1'; -- MEM_ACCESS + DEC_CTRL(CTRL_MEM_RW) <= '1'; -- MEM_WRITE + DEC_CTRL(CTRL_WB_EN) <= '0'; -- WB EN + NEXT_DUAL_OP <= '0'; + REG_SEL(OP_A_IS_REG) <= '1'; + REG_SEL(OP_B_IS_REG) <= not INSTR_REG(22); + REG_SEL(OP_C_IS_REG) <= '1'; + + + when "011" => -- store, pre indexing, write back + ---------------------------------------------------------------------------------- + DEC_CTRL(CTRL_RD_3 downto CTRL_RD_0) <= INSTR_REG(19 downto 16); -- R_DEST + DEC_CTRL(CTRL_MEM_ACC) <= '1'; -- MEM_ACCESS + DEC_CTRL(CTRL_MEM_RW) <= '1'; -- MEM_WRITE + DEC_CTRL(CTRL_WB_EN) <= '1'; -- WB EN + NEXT_DUAL_OP <= '0'; + REG_SEL(OP_A_IS_REG) <= '1'; + REG_SEL(OP_B_IS_REG) <= not INSTR_REG(22); + REG_SEL(OP_C_IS_REG) <= '1'; + + + when others => -- store, post indexing, allways write back + ---------------------------------------------------------------------------------- + if (DUAL_OP = '0') then -- ST Ra, Rd + DEC_CTRL(CTRL_RD_3 downto CTRL_RD_0) <= INSTR_REG(15 downto 12); -- R_DEST + DEC_CTRL(CTRL_MEM_ACC) <= '1'; -- MEM_ACCESS + DEC_CTRL(CTRL_MEM_RW) <= '1'; -- MEM_WRITE + DEC_CTRL(CTRL_WB_EN) <= '0'; -- WB EN + DEC_CTRL(CTRL_MEM_USER) <= INSTR_REG(21); -- access in pseudo-user-mode + NEXT_DUAL_OP <= '1'; + DEC_CTRL(CTRL_ALU_FS_3 downto CTRL_ALU_FS_0) <= PassA; -- ALU_CTRL = PassA + REG_SEL(OP_A_IS_REG) <= '1'; + REG_SEL(OP_B_IS_REG) <= '0'; + REG_SEL(OP_C_IS_REG) <= '1'; + + else -- ADD/SUB Ra,Ra,Op_B + DEC_CTRL(CTRL_RD_3 downto CTRL_RD_0) <= INSTR_REG(19 downto 16); -- R_DEST + DEC_CTRL(CTRL_MEM_ACC) <= '0'; -- MEM_ACCESS + DEC_CTRL(CTRL_MEM_RW) <= '0'; -- MEM_WRITE + DEC_CTRL(CTRL_WB_EN) <= '1'; -- WB EN + NEXT_DUAL_OP <= '0'; + REG_SEL(OP_A_IS_REG) <= '1'; + REG_SEL(OP_B_IS_REG) <= not INSTR_REG(22); + REG_SEL(OP_C_IS_REG) <= '0'; + end if; + + end case; + + elsif (INSTR_REG(27 downto 23) = "00010") and (INSTR_REG(21 downto 20) = "00") and (INSTR_REG(11 downto 4) = "00001001") then + -- Single Data Swap SWP + ---------------------------------------------------------------------------------- + OP_ADR_OUT(OP_A_ADR_3 downto OP_A_ADR_0) <= INSTR_REG(19 downto 16); -- BASE + OP_ADR_OUT(OP_C_ADR_3 downto OP_C_ADR_0) <= INSTR_REG(03 downto 00); -- W_DATA + REG_SEL(OP_A_IS_REG) <= '1'; + REG_SEL(OP_B_IS_REG) <= '0'; + REG_SEL(OP_C_IS_REG) <= '1'; + + DEC_CTRL(CTRL_ALU_FS_3 downto CTRL_ALU_FS_0) <= PassA; -- ALU_CTRL = PassA + DEC_CTRL(CTRL_MEM_DQ_1 downto CTRL_MEM_DQ_0) <= '0' & INSTR_REG(22); -- DATA QUANTITY + DEC_CTRL(CTRL_MEM_ACC) <= '1'; -- MEM_ACCESS + NEXT_DUAL_OP <= '0'; + if (DUAL_OP = '0') then + NEXT_DUAL_OP <= '1'; + DEC_CTRL(CTRL_MEM_RW) <= '0'; -- MEM_READ + DEC_CTRL(CTRL_WB_EN) <= '1'; -- WB EN + else + NEXT_DUAL_OP <= '0'; + DEC_CTRL(CTRL_MEM_RW) <= '1'; -- MEM_WRITE + DEC_CTRL(CTRL_WB_EN) <= '0'; -- WB EN + end if; + + + else -- ALU operation / MCR access + ---------------------------------------------------------------------------------- + B_TEMP_1 := INSTR_REG(25) & INSTR_REG(04); + case B_TEMP_1 is + when "10" | "11" => -- IS_CONST + REG_SEL(OP_A_IS_REG) <= '1'; + REG_SEL(OP_B_IS_REG) <= '0'; + REG_SEL(OP_C_IS_REG) <= '0'; + SHIFT_C_OUT <= INSTR_REG(11 downto 08) & '0'; -- SHIFT_POS x2 + if (INSTR_REG(11 downto 08) = "0000") then + SHIFT_M_OUT <= S_LSL; -- SHIFT MODE = anything but ROR + else + SHIFT_M_OUT <= S_ROR; -- SHIFT MODE = ROR + end if; + IMM_OUT <= x"000000" & INSTR_REG(07 downto 00); -- IMMEDIATE + DEC_CTRL(CTRL_SHIFTR) <= '0'; -- SHIFT WITH IMMEDIATE + + when "00" => -- shift REG_B direct + REG_SEL(OP_A_IS_REG) <= '1'; + REG_SEL(OP_B_IS_REG) <= '1'; + REG_SEL(OP_C_IS_REG) <= '0'; + SHIFT_C_OUT <= INSTR_REG(11 downto 07); -- SHIFT POS + SHIFT_M_OUT <= INSTR_REG(06 downto 05); -- SHIFT MODE + IMM_OUT <= (others => '0'); -- IMMEDIATE + DEC_CTRL(CTRL_SHIFTR) <= '0'; -- SHIFT WITH IMMEDIATE + + when others => -- shift REG_B with REG_C + REG_SEL(OP_A_IS_REG) <= '1'; + REG_SEL(OP_B_IS_REG) <= '1'; + REG_SEL(OP_C_IS_REG) <= '1'; + SHIFT_C_OUT <= (others => '0'); -- SHIFT POS + SHIFT_M_OUT <= INSTR_REG(06 downto 05); -- SHIFT MODE + IMM_OUT <= (others => '0'); -- IMMEDIATE + DEC_CTRL(CTRL_SHIFTR) <= '1'; -- SHIFT_REG + end case; + + case (INSTR_REG(24 downto 21)) is -- ALU FUNCTION SET + when "0000" => DEC_CTRL(CTRL_ALU_FS_3 downto CTRL_ALU_FS_0) <= L_AND; + when "0001" => DEC_CTRL(CTRL_ALU_FS_3 downto CTRL_ALU_FS_0) <= L_XOR; + when "0010" => DEC_CTRL(CTRL_ALU_FS_3 downto CTRL_ALU_FS_0) <= A_SUB; + when "0011" => DEC_CTRL(CTRL_ALU_FS_3 downto CTRL_ALU_FS_0) <= A_RSB; + when "0100" => DEC_CTRL(CTRL_ALU_FS_3 downto CTRL_ALU_FS_0) <= A_ADD; + when "0101" => DEC_CTRL(CTRL_ALU_FS_3 downto CTRL_ALU_FS_0) <= A_ADC; + when "0110" => DEC_CTRL(CTRL_ALU_FS_3 downto CTRL_ALU_FS_0) <= A_SBC; + when "0111" => DEC_CTRL(CTRL_ALU_FS_3 downto CTRL_ALU_FS_0) <= A_RSC; + + -- ALU-Operations / MCR Access -- + when "1000" => DEC_CTRL(CTRL_ALU_FS_3 downto CTRL_ALU_FS_0) <= L_TST; -- read SREG + DEC_CTRL(CTRL_WB_EN) <= '0'; -- disable register write back + if (INSTR_REG(20) = '0') then -- ALTER FLAGS ? + DEC_CTRL(CTRL_MREG_ACC) <= '1'; -- access MREG + DEC_CTRL(CTRL_WB_EN) <= '1'; -- re-enable register write back + REG_SEL(OP_A_IS_REG) <= '0'; + REG_SEL(OP_B_IS_REG) <= '0'; + REG_SEL(OP_C_IS_REG) <= '0'; + end if; + + when "1001" => DEC_CTRL(CTRL_ALU_FS_3 downto CTRL_ALU_FS_0) <= L_TEQ; -- write SREG + DEC_CTRL(CTRL_WB_EN) <= '0'; -- disable register write back + if (INSTR_REG(20) = '0') then -- ALTER FLAGS ? + DEC_CTRL(CTRL_ALU_FS_3 downto CTRL_ALU_FS_0) <= PassB; -- write SREG + DEC_CTRL(CTRL_MREG_ACC) <= '1'; -- access MREG + REG_SEL(OP_A_IS_REG) <= '0'; + REG_SEL(OP_B_IS_REG) <= '1'; + REG_SEL(OP_C_IS_REG) <= '0'; + end if; + + when "1010" => DEC_CTRL(CTRL_ALU_FS_3 downto CTRL_ALU_FS_0) <= A_CMP; -- read SREG + DEC_CTRL(CTRL_WB_EN) <= '0'; -- disable register write back + if (INSTR_REG(20) = '0') then -- ALTER FLAGS ? + DEC_CTRL(CTRL_MREG_ACC) <= '1'; -- access MREG + DEC_CTRL(CTRL_WB_EN) <= '1'; -- re-enable register write back + REG_SEL(OP_A_IS_REG) <= '0'; + REG_SEL(OP_B_IS_REG) <= '0'; + REG_SEL(OP_C_IS_REG) <= '0'; + end if; + + when "1011" => DEC_CTRL(CTRL_ALU_FS_3 downto CTRL_ALU_FS_0) <= A_CMN; -- write SREG + DEC_CTRL(CTRL_WB_EN) <= '0'; -- disable register write back + if (INSTR_REG(20) = '0') then -- ALTER FLAGS ? + DEC_CTRL(CTRL_ALU_FS_3 downto CTRL_ALU_FS_0) <= PassB; -- write SREG + DEC_CTRL(CTRL_MREG_ACC) <= '1'; -- access MREG + REG_SEL(OP_A_IS_REG) <= '0'; + REG_SEL(OP_B_IS_REG) <= '1'; + REG_SEL(OP_C_IS_REG) <= '0'; + end if; + + when "1100" => DEC_CTRL(CTRL_ALU_FS_3 downto CTRL_ALU_FS_0) <= L_OR; + when "1101" => DEC_CTRL(CTRL_ALU_FS_3 downto CTRL_ALU_FS_0) <= L_MOV; + when "1110" => DEC_CTRL(CTRL_ALU_FS_3 downto CTRL_ALU_FS_0) <= L_BIC; + when "1111" => DEC_CTRL(CTRL_ALU_FS_3 downto CTRL_ALU_FS_0) <= L_NOT; + when others => DEC_CTRL(CTRL_ALU_FS_3 downto CTRL_ALU_FS_0) <= (others => '0'); + end case; + + end if; + + + + when "01" => -- UNDEFINED INSTRUCTION INTERRUPT / SINGLE MEMORY ACCESS + -- ============================================================================================ + if (INSTR_REG(25) = '1') and (INSTR_REG(4) = '1') then -- UDI + ---------------------------------------------------------------------------------- + DEC_CTRL(CTRL_UND) <= '1'; --undefined instruction + + else -- Single Data Transfer + ---------------------------------------------------------------------------------- + + OP_ADR_OUT(OP_A_ADR_3 downto OP_A_ADR_0) <= INSTR_REG(19 downto 16); -- BASE + OP_ADR_OUT(OP_B_ADR_3 downto OP_B_ADR_0) <= INSTR_REG(03 downto 00); -- OFFSET + OP_ADR_OUT(OP_C_ADR_3 downto OP_C_ADR_0) <= INSTR_REG(15 downto 12); -- DATA + NEXT_DUAL_OP <= '0'; + DEC_CTRL(CTRL_CONST) <= not INSTR_REG(25); -- IS_CONST + if (INSTR_REG(22) = '0') then -- W/B quantity + DEC_CTRL(CTRL_MEM_DQ_1 downto CTRL_MEM_DQ_0) <= DQ_WORD; + else + DEC_CTRL(CTRL_MEM_DQ_1 downto CTRL_MEM_DQ_0) <= DQ_BYTE; + end if; + + B_TEMP_2 := INSTR_REG(25) & INSTR_REG(04); + case B_TEMP_2 is + when "00" | "01" => -- IS_CONST + SHIFT_C_OUT <= (others => '0'); -- SHIFT POS + SHIFT_M_OUT <= S_LSL; -- SHIFT MODE = wayne + IMM_OUT(31 downto 00) <= x"00000" & INSTR_REG(11 downto 00); -- unsigned IMMEDIATE + DEC_CTRL(CTRL_SHIFTR) <= '0'; -- SHIFT_REG + + when "10" => -- shift REG_B direct + SHIFT_C_OUT <= INSTR_REG(11 downto 07); -- SHIFT POS + SHIFT_M_OUT <= INSTR_REG(06 downto 05); -- SHIFT MODE + IMM_OUT(31 downto 00) <= (others => '0'); -- IMMEDIATE + DEC_CTRL(CTRL_SHIFTR) <= '0'; -- SHIFT_REG + + when others => -- shift REG_B with REG_C + SHIFT_C_OUT <= (others => '0'); -- SHIFT POS + SHIFT_M_OUT <= INSTR_REG(06 downto 05); -- SHIFT MODE + IMM_OUT(31 downto 00) <= (others => '0'); -- IMMEDIATE + DEC_CTRL(CTRL_SHIFTR) <= '1'; -- SHIFT_REG + end case; + + if (INSTR_REG(23) = '0') then -- sub index + DEC_CTRL(CTRL_ALU_FS_3 downto CTRL_ALU_FS_0) <= A_SUB; -- ALU_CTRL = SUB + else -- add index + DEC_CTRL(CTRL_ALU_FS_3 downto CTRL_ALU_FS_0) <= A_ADD; -- ALU_CTRL = ADD + end if; + + temp_3 := INSTR_REG(20) & INSTR_REG(24) & INSTR_REG(21); + case temp_3 is -- L_P_W + + when "110" => -- load, pre indexing, no write back + ---------------------------------------------------------------------------------- + DEC_CTRL(CTRL_RD_3 downto CTRL_RD_0) <= INSTR_REG(15 downto 12); -- R_DEST + DEC_CTRL(CTRL_MEM_ACC) <= '1'; -- MEM_ACCESS + DEC_CTRL(CTRL_MEM_RW) <= '0'; -- MEM_READ + DEC_CTRL(CTRL_WB_EN) <= '1'; -- WB EN + NEXT_DUAL_OP <= '0'; + REG_SEL(OP_A_IS_REG) <= '1'; + REG_SEL(OP_B_IS_REG) <= INSTR_REG(25); + REG_SEL(OP_C_IS_REG) <= '0'; + + + when "111" => -- load, pre indexing, write back + ---------------------------------------------------------------------------------- + if (DUAL_OP = '0') then -- ADD/SUB Ra,Ra,Op_B + DEC_CTRL(CTRL_RD_3 downto CTRL_RD_0) <= INSTR_REG(19 downto 16); -- R_DEST + DEC_CTRL(CTRL_MEM_ACC) <= '0'; -- MEM_ACCESS + DEC_CTRL(CTRL_WB_EN) <= '1'; -- WB EN + NEXT_DUAL_OP <= '1'; + REG_SEL(OP_A_IS_REG) <= '1'; + REG_SEL(OP_B_IS_REG) <= INSTR_REG(25); + REG_SEL(OP_C_IS_REG) <= '0'; + + else -- LD Rd, Ra + DEC_CTRL(CTRL_RD_3 downto CTRL_RD_0) <= INSTR_REG(15 downto 12); -- R_DEST + DEC_CTRL(CTRL_MEM_ACC) <= '1'; -- MEM_ACCESS + DEC_CTRL(CTRL_WB_EN) <= '1'; -- WB EN + NEXT_DUAL_OP <= '0'; + DEC_CTRL(CTRL_ALU_FS_3 downto CTRL_ALU_FS_0) <= PassA; -- ALU_CTRL = PassA + REG_SEL(OP_A_IS_REG) <= '1'; + REG_SEL(OP_B_IS_REG) <= '0'; + REG_SEL(OP_C_IS_REG) <= '0'; + end if; + + + when "100" | "101" => -- load, post indexing, allways write back + ---------------------------------------------------------------------------------- + if (DUAL_OP = '0') then -- LD Rd,Ra + DEC_CTRL(CTRL_RD_3 downto CTRL_RD_0) <= INSTR_REG(15 downto 12); -- R_DEST + DEC_CTRL(CTRL_MEM_ACC) <= '1'; -- MEM_ACCESS + DEC_CTRL(CTRL_MEM_RW) <= '0'; -- MEM_READ + DEC_CTRL(CTRL_WB_EN) <= '1'; -- WB EN + DEC_CTRL(CTRL_MEM_USER) <= INSTR_REG(21); -- access in pseudo-user-mode + NEXT_DUAL_OP <= '1'; + DEC_CTRL(CTRL_ALU_FS_3 downto CTRL_ALU_FS_0) <= PassA; -- ALU_CTRL = PassA + REG_SEL(OP_A_IS_REG) <= '1'; + REG_SEL(OP_B_IS_REG) <= '0'; + REG_SEL(OP_C_IS_REG) <= '0'; + + else -- ADD/SUB Ra,Ra,Op_B + DEC_CTRL(CTRL_RD_3 downto CTRL_RD_0) <= INSTR_REG(19 downto 16); -- R_DEST + DEC_CTRL(CTRL_MEM_ACC) <= '0'; -- MEM_ACCESS + DEC_CTRL(CTRL_WB_EN) <= '1'; -- WB EN + NEXT_DUAL_OP <= '0'; + REG_SEL(OP_A_IS_REG) <= '1'; + REG_SEL(OP_B_IS_REG) <= INSTR_REG(25); + REG_SEL(OP_C_IS_REG) <= '0'; + end if; + + + when "010" => -- store, pre indexing, no write back + ---------------------------------------------------------------------------------- + DEC_CTRL(CTRL_RD_3 downto CTRL_RD_0) <= "0000"; -- R_DEST + DEC_CTRL(CTRL_MEM_ACC) <= '1'; -- MEM_ACCESS + DEC_CTRL(CTRL_MEM_RW) <= '1'; -- MEM_WRITE + DEC_CTRL(CTRL_WB_EN) <= '0'; -- WB EN + NEXT_DUAL_OP <= '0'; + REG_SEL(OP_A_IS_REG) <= '1'; + REG_SEL(OP_B_IS_REG) <= INSTR_REG(25); + REG_SEL(OP_C_IS_REG) <= '1'; + + + when "011" => -- store, pre indexing, write back + ---------------------------------------------------------------------------------- + DEC_CTRL(CTRL_RD_3 downto CTRL_RD_0) <= INSTR_REG(19 downto 16); -- R_DEST + DEC_CTRL(CTRL_MEM_ACC) <= '1'; -- MEM_ACCESS + DEC_CTRL(CTRL_MEM_RW) <= '1'; -- MEM_WRITE + DEC_CTRL(CTRL_WB_EN) <= '1'; -- WB EN + NEXT_DUAL_OP <= '0'; + REG_SEL(OP_A_IS_REG) <= '1'; + REG_SEL(OP_B_IS_REG) <= INSTR_REG(25); + REG_SEL(OP_C_IS_REG) <= '1'; + + + when others => -- store, post indexing, allways write back + ---------------------------------------------------------------------------------- + if (DUAL_OP = '0') then -- ST Ra, Rd + DEC_CTRL(CTRL_RD_3 downto CTRL_RD_0) <= INSTR_REG(15 downto 12); -- R_DEST + DEC_CTRL(CTRL_MEM_ACC) <= '1'; -- MEM_ACCESS + DEC_CTRL(CTRL_MEM_RW) <= '1'; -- MEM_WRITE + DEC_CTRL(CTRL_WB_EN) <= '0'; -- WB EN + DEC_CTRL(CTRL_MEM_USER) <= INSTR_REG(21); -- access in pseudo-user-mode + NEXT_DUAL_OP <= '1'; + DEC_CTRL(CTRL_ALU_FS_3 downto CTRL_ALU_FS_0) <= PassA; -- ALU_CTRL = PassA + REG_SEL(OP_A_IS_REG) <= '1'; + REG_SEL(OP_B_IS_REG) <= '0'; + REG_SEL(OP_C_IS_REG) <= '1'; + + else -- ADD/SUB Ra,Ra,Op_B + DEC_CTRL(CTRL_RD_3 downto CTRL_RD_0) <= INSTR_REG(19 downto 16); -- R_DEST + DEC_CTRL(CTRL_MEM_ACC) <= '0'; -- MEM_ACCESS + DEC_CTRL(CTRL_MEM_RW) <= '0'; -- MEM_WRITE + DEC_CTRL(CTRL_WB_EN) <= '1'; -- WB EN + NEXT_DUAL_OP <= '0'; + REG_SEL(OP_A_IS_REG) <= '1'; + REG_SEL(OP_B_IS_REG) <= INSTR_REG(25); + REG_SEL(OP_C_IS_REG) <= '0'; + end if; + + end case; + end if; + + + when "10" => -- BRANCH OPERATIONS / BLOCK DATA TRANSFER + -- ============================================================================================ + if (INSTR_REG(25) = '1') then -- Branch (and Link) + ---------------------------------------------------------------------------------- + DEC_CTRL(CTRL_LINK) <= INSTR_REG(24); -- LINK + DEC_CTRL(CTRL_WB_EN) <= INSTR_REG(24); -- WB_EN + DEC_CTRL(CTRL_CONST) <= '1'; -- IS_CONST + DEC_CTRL(CTRL_BRANCH) <= '1'; -- BRANCH_INSTR + SHIFT_C_OUT <= "00010"; -- SHIFT POS = 2 => x4 + SHIFT_M_OUT <= S_LSL; -- SHIFT MODE + DEC_CTRL(CTRL_ALU_FS_3 downto CTRL_ALU_FS_0) <= A_ADD; -- ALU.ADD + IMM_OUT(23 downto 0) <= INSTR_REG(23 downto 0); + for i in 24 to 31 loop + IMM_OUT(i) <= INSTR_REG(23); -- IMMEDIATE sign extension + end loop; + + else -- Block Data Transfer + ---------------------------------------------------------------------------------- + DEC_CTRL(CTRL_UND) <= '1'; -- undefined instruction, since block data transfers are not implemented + + end if; + + + + when others => -- COPROCESSOR INTERFACE / SOFTWARE INTERRUPT + -- ============================================================================================ + if (INSTR_REG(25 downto 24) = "11") then -- SOFTWARE INTERRUPT + ---------------------------------------------------------------------------------- + DEC_CTRL(CTRL_SWI) <= '1'; -- 24-bit tag is ignored by processor + + else -- COPROCESSOR OPERATION + ---------------------------------------------------------------------------------- + DEC_CTRL(CTRL_UND) <= '1'; -- undefined instruction, since coprocessor operations are not implemented + + end if; + + end case; + + end process OPCODE_DECODER; + + +end instruction_decoder; \ No newline at end of file Index: storm_core/trunk/rtl/WB_UNIT.vhd =================================================================== --- storm_core/trunk/rtl/WB_UNIT.vhd (nonexistent) +++ storm_core/trunk/rtl/WB_UNIT.vhd (revision 10) @@ -0,0 +1,194 @@ +-- ####################################################### +-- # < STORM CORE PROCESSOR by Stephan Nolting > # +-- # *************************************************** # +-- # Data Write Back Selector & MEM Read Input # +-- # *************************************************** # +-- # Version 1.2, 14.07.2011 # +-- ####################################################### + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +library work; +use work.STORM_core_package.all; + +entity WB_UNIT is + port ( +-- ############################################################################################### +-- ## Global Control ## +-- ############################################################################################### + + CLK : in STD_LOGIC; -- global clock network + G_HALT : in STD_LOGIC; -- global halt line + RES : in STD_LOGIC; -- global reset network + CTRL_IN : in STD_LOGIC_VECTOR(31 downto 0); -- stage control + +-- ############################################################################################### +-- ## Operand Connection ## +-- ############################################################################################### + + ALU_DATA_IN : in STD_LOGIC_VECTOR(31 downto 0); -- alu data input + ADR_BUFF_IN : in STD_LOGIC_VECTOR(31 downto 0); -- alu address input + + WB_DATA_OUT : out STD_LOGIC_VECTOR(31 downto 0); -- write back data output + XMEM_RD_DATA : in STD_LOGIC_VECTOR(31 downto 0); -- memory data input + +-- ############################################################################################### +-- ## Forwarding Path ## +-- ############################################################################################### + + WB_FW_OUT : out STD_LOGIC_VECTOR(40 downto 0) -- forwarding data & ctrl + + ); +end WB_UNIT; + +architecture Structure of WB_UNIT is + + -- Pipeline Buffers -- + signal ALU_DATA : STD_LOGIC_VECTOR(31 downto 0); + signal ADR_BUFF : STD_LOGIC_VECTOR(01 downto 0); + + -- MEM RD Buffer -- + signal MEM_DATA : STD_LOGIC_VECTOR(31 downto 0); + + -- Local Signals -- + signal REG_WB_DATA : STD_LOGIC_VECTOR(31 downto 0); + +begin + + -- Pipeline Registers ----------------------------------------------------------------------------- + -- --------------------------------------------------------------------------------------------------- + PIPE_REG: process(CLK, RES, XMEM_RD_DATA) + begin + --- ALU Data --- + if rising_edge(CLK) then + if (RES = '1') then + ALU_DATA <= (others => '0'); + ADR_BUFF <= (others => '0'); + elsif (G_HALT = '0') then + ALU_DATA <= ALU_DATA_IN; + ADR_BUFF <= ADR_BUFF_IN(1 downto 0); -- we only need the 2 LSBs + end if; + end if; + + --- MEM Data --- + MEM_DATA <= XMEM_RD_DATA; + + end process PIPE_REG; + + + + -- Write Back Data Selector ----------------------------------------------------------------------- + -- --------------------------------------------------------------------------------------------------- + WB_DATA_MUX: process(CTRL_IN, MEM_DATA, ALU_DATA, ADR_BUFF) + variable TEMP : STD_LOGIC_VECTOR(04 downto 00); + variable ENDIAN_TMP : STD_LOGIC_VECTOR(31 downto 00); + variable RD_DATA_TMP : STD_LOGIC_VECTOR(31 downto 00); + begin + + --- Endianess Converter --- + if (USE_BIG_ENDIAN = FALSE) then -- Little Endian + ENDIAN_TMP := MEM_DATA(07 downto 00) & MEM_DATA(15 downto 08) & + MEM_DATA(23 downto 16) & MEM_DATA(31 downto 24); + else -- Big Endian + ENDIAN_TMP := MEM_DATA(31 downto 24) & MEM_DATA(23 downto 16) & + MEM_DATA(15 downto 08) & MEM_DATA(07 downto 00); + end if; + + --- Input Data Alignment --- + TEMP := CTRL_IN(CTRL_MEM_DQ_1 downto CTRL_MEM_DQ_0) & ADR_BUFF & CTRL_IN(CTRL_MEM_SE); + -- TEMP = Quantity(2) & LSB_ADR(2) & Sign_extension(1) + case (TEMP) is + -- WORD TRANSFER -- + when "00000" | "00001" => -- word transfer, no offset, SE not possible + RD_DATA_TMP := ENDIAN_TMP(31 downto 00); + when "00010" | "00011" => -- word transfer, one byte offset, SE not possible + RD_DATA_TMP := ENDIAN_TMP(23 downto 00) & ENDIAN_TMP(31 downto 24); + when "00100" | "00101" => -- word transfer, two bytes offset, SE not possible + RD_DATA_TMP := ENDIAN_TMP(15 downto 00) & ENDIAN_TMP(31 downto 16); + when "00110" | "00111" => -- word transfer, three bytes offset, SE not possible + RD_DATA_TMP := ENDIAN_TMP(07 downto 00) & ENDIAN_TMP(31 downto 08); + + -- BYTE TRANSFER -- + when "01000" => -- byte transfer, no offset, no sign extension + RD_DATA_TMP := x"000000" & ENDIAN_TMP(31 downto 24); + when "01001" => -- byte transfer, no offset, sign extension + RD_DATA_TMP(7 downto 0) := ENDIAN_TMP(31 downto 24); + for i in 8 to 31 loop + RD_DATA_TMP(i) := ENDIAN_TMP(31); + end loop; + when "01010" => -- byte transfer, one byte offset, no sign extension + RD_DATA_TMP := x"000000" & ENDIAN_TMP(23 downto 16); + when "01011" => -- byte transfer, one byte offset, sign extension + RD_DATA_TMP(7 downto 0) := ENDIAN_TMP(23 downto 16); + for i in 8 to 31 loop + RD_DATA_TMP(i) := ENDIAN_TMP(23); + end loop; + when "01100" => -- byte transfer, two bytes offset, no sign extension + RD_DATA_TMP := x"000000" & ENDIAN_TMP(15 downto 08); + when "01101" => -- byte transfer, two bytes offset, sign extension + RD_DATA_TMP(7 downto 0) := ENDIAN_TMP(15 downto 08); + for i in 8 to 31 loop + RD_DATA_TMP(i) := ENDIAN_TMP(15); + end loop; + when "01110" => -- byte transfer, three bytes offset, no sign extension + RD_DATA_TMP := x"000000" & ENDIAN_TMP(07 downto 00); + when "01111" => -- byte transfer, three bytes offset, sign extension + RD_DATA_TMP(7 downto 0) := ENDIAN_TMP(07 downto 00); + for i in 8 to 31 loop + RD_DATA_TMP(i) := ENDIAN_TMP(07); + end loop; + + -- HALFWORD TRANSFER -- + when "10000" | "11000" => -- halfword transfer, no offset, no sign extension + RD_DATA_TMP := x"0000" & ENDIAN_TMP(31 downto 16); + when "10001" | "11001" => -- halfword transfer, no offset, sign extension + RD_DATA_TMP(15 downto 00) := ENDIAN_TMP(31 downto 16); + for i in 16 to 31 loop + RD_DATA_TMP(i) := ENDIAN_TMP(31); + end loop; + when "10010" | "11010" => -- halfword transfer, one byte offset, no sign extension + RD_DATA_TMP := x"0000" & ENDIAN_TMP(23 downto 08); + when "10011" | "11011" => -- halfword transfer, one byte offset, sign extension + RD_DATA_TMP(15 downto 00) := ENDIAN_TMP(23 downto 08); + for i in 16 to 31 loop + RD_DATA_TMP(i) := ENDIAN_TMP(23); + end loop; + when "10100" | "11100" => -- halfword transfer, two bytes offset, no sign extension + RD_DATA_TMP := x"0000" & ENDIAN_TMP(15 downto 00); + when "10101" | "11101" => -- halfword transfer, two bytes offset, sign extension + RD_DATA_TMP(15 downto 00) := ENDIAN_TMP(15 downto 00); + for i in 16 to 31 loop + RD_DATA_TMP(i) := ENDIAN_TMP(15); + end loop; + when "10110" | "11110" => -- halfword transfer, three bytes offset, no sign extension + RD_DATA_TMP := x"0000" & ENDIAN_TMP(07 downto 00) & ENDIAN_TMP(31 downto 24); + when others => -- halfword transfer, three bytes offset, sign extension + RD_DATA_TMP(15 downto 00) := ENDIAN_TMP(07 downto 00) & ENDIAN_TMP(31 downto 24); + for i in 16 to 31 loop + RD_DATA_TMP(i) := ENDIAN_TMP(07); + end loop; + end case; + + --- Write Back Selector --- + if (CTRL_IN(CTRL_MEM_ACC) = '1') and (CTRL_IN(CTRL_MEM_RW) = RD) then + REG_WB_DATA <= RD_DATA_TMP; -- Memory read data + else + REG_WB_DATA <= ALU_DATA; -- ALU Operation + end if; + end process WB_DATA_MUX; + + -- Result Output -- + WB_DATA_OUT <= REG_WB_DATA; + + + + -- Forwarding Path -------------------------------------------------------------------------------- + -- --------------------------------------------------------------------------------------------------- + WB_FW_OUT(FWD_DATA_MSB downto FWD_DATA_LSB) <= REG_WB_DATA; + WB_FW_OUT(FWD_RD_MSB downto FWD_RD_LSB) <= CTRL_IN(CTRL_RD_3 downto CTRL_RD_0); + WB_FW_OUT(FWD_WB) <= CTRL_IN(CTRL_EN) and CTRL_IN(CTRL_WB_EN); + + +end Structure; \ No newline at end of file Index: storm_core/trunk/rtl/MEMORY.vhd =================================================================== --- storm_core/trunk/rtl/MEMORY.vhd (nonexistent) +++ storm_core/trunk/rtl/MEMORY.vhd (revision 10) @@ -0,0 +1,135 @@ +-- ###################################################### +-- # < STORM CORE SYSTEM by Stephan Nolting > # +-- # ************************************************** # +-- # Internal Working Memory # +-- # ************************************************** # +-- # Version 2.8, 31.08.2011 # +-- ###################################################### + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +library work; +use work.STORM_core_package.all; + +entity MEMORY is + generic ( + MEM_SIZE : natural; -- memory cells + LOG2_MEM_SIZE : natural -- log2(memory cells) + ); + port ( + CLK : in STD_LOGIC; -- memory master clock + RES : in STD_LOGIC; -- reset, sync, high active + + DATA_IN : in STD_LOGIC_VECTOR(31 downto 0); -- write data + DATA_OUT : out STD_LOGIC_VECTOR(31 downto 0); -- read data + ADR_IN : in STD_LOGIC_VECTOR(31 downto 0); -- adr in + SEL_IN : in STD_LOGIC_VECTOR(03 downto 0); -- data quantity + + CS : in STD_LOGIC; -- chip select + RW : in STD_LOGIC -- read/write + ); +end MEMORY; + +architecture Behavioral of MEMORY is + + --- Memory Type --- + type RAM_8 is array(0 to MEM_SIZE - 1) of STD_LOGIC_VECTOR(7 downto 0); + type RAM_32 is array(3 downto 0) of RAM_8; + type RAM_IMAGE_TYPE is array (0 to MEM_SIZE - 1) of STD_LOGIC_VECTOR(31 downto 0); + + --- INIT MEMORY IMAGE --- + -- can be used for debugging or to implement a start-up + -- program, like a bootloader + ----------------------------------------------------------------- + constant RAM_IMAGE : RAM_IMAGE_TYPE := + ( + 000000 => x"EA000006", -- demo program: fibonacci numbers + 000001 => x"E1A00000", + 000002 => x"E1A00000", + 000003 => x"E1A00000", + 000004 => x"E1A00000", + 000005 => x"E1A00000", + 000006 => x"E1A00000", + 000007 => x"E1A00000", + 000008 => x"E3A00000", + 000009 => x"E3A01001", + 000010 => x"E3A02000", + 000011 => x"E3A03064", + 000012 => x"E35300DC", + 000013 => x"0A000004", + 000014 => x"E4830004", + 000015 => x"E0802001", + 000016 => x"E1A00001", + 000017 => x"E1A01002", + 000018 => x"EAFFFFF8", + 000019 => x"EAFFFFFE", + others => x"F0013007" + ); + ----------------------------------------------------------------- + + --- Init RAM function --- + function load_mem(IMAGE : RAM_IMAGE_TYPE) return RAM_32 is + variable TEMP_MEM : RAM_32; + begin + for j in 0 to 3 loop + for i in 0 to MEM_SIZE - 1 loop + TEMP_MEM(j)(i) := IMAGE(i)(j*8+7 downto j*8); + end loop; + end loop; + return TEMP_MEM; + end load_mem; + + --- Internal Working Memory (Preloaded) --- + signal MEM_FILE : RAM_32 := load_mem(RAM_IMAGE); + + --- Dummy memory for simulation --- + signal SIM_MEM : RAM_IMAGE_TYPE; + +begin + + -- STORM data/instruction memory ----------------------------------------------------------------------- + -- -------------------------------------------------------------------------------------------------------- + MEM_FILE_ACCESS: process(CLK, CS, RW, DATA_IN, ADR_IN, SEL_IN, MEM_FILE) + variable ADR_TEMP, ADR_BUFFER : integer range 0 to MEM_SIZE - 1; + begin + --- RW Address --- + ADR_TEMP := to_integer(unsigned(ADR_IN(LOG2_MEM_SIZE-1+2 downto 0+2))); -- word access + + --- Sync Write --- + if rising_edge(CLK) then + for i in 0 to 3 loop + if (CS = '1') then + if (RW = '1') then -- byte access + if (SEL_IN(i) = '1') then -- subword select + MEM_FILE(i)(ADR_TEMP) <= DATA_IN(8*i+7 downto 8*i); + end if; + end if; + ADR_BUFFER := ADR_TEMP; + end if; + end loop; + --ADR_BUFFER := ADR_TEMP; + end if; + + --- Sync Read --- + for i in 0 to 3 loop + DATA_OUT(8*i+7 downto 8*i) <= MEM_FILE(i)(ADR_BUFFER); + end loop; + + end process MEM_FILE_ACCESS; + + + + -- Dummy memory for simulation ----------------------------------------------------------------------- + -- -------------------------------------------------------------------------------------------------------- + DUMMY_MEM_PROC: process (MEM_FILE(3), MEM_FILE(2), MEM_FILE(1), MEM_FILE(0)) + begin + -- use this memory dummy for simulation output + -- -> its easier to analyse ;) + for i in 0 to MEM_SIZE - 1 loop + SIM_MEM(i) <= MEM_FILE(3)(i) & MEM_FILE(2)(i) & MEM_FILE(1)(i) & MEM_FILE(0)(i); + end loop; + end process DUMMY_MEM_PROC; + +end Behavioral; \ No newline at end of file Index: storm_core/trunk/rtl/ACCESS_ARBITER.vhd =================================================================== --- storm_core/trunk/rtl/ACCESS_ARBITER.vhd (nonexistent) +++ storm_core/trunk/rtl/ACCESS_ARBITER.vhd (revision 10) @@ -0,0 +1,441 @@ +-- ###################################################### +-- # < STORM CORE SYSTEM by Stephan Nolting > # +-- # ************************************************** # +-- # Resource Access Arbiter # +-- # -------------------------------------------------- # +-- # This access arbiter can coordinate the resource # +-- # requests of two clients for two resources. # +-- # If a resource does not acknowledge the acces, # +-- # an interrupt to the corresponding client will be # +-- # transmitted. # +-- # If you want to disable resource 1, set the # +-- # switch address to 0x00000000. # +-- # ************************************************** # +-- # Version 1.1.0, 30.08.2011 # +-- ###################################################### + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +library work; +use work.STORM_core_package.all; + +entity ACCESS_ARBITER is + generic ( + SWITCH_ADR : natural; -- address border resource1/resource2 + RE1_TO_CNT : natural; -- resource 1 time out value + RE2_TO_CNT : natural; -- resource 2 time out value + CL1_INT_EN : boolean; -- allow interrupts for client 1 + CL2_INT_EN : boolean -- allow interrupts for client 2 + ); + port ( +-- ############################################################################################### +-- ## Global Control ## +-- ############################################################################################### + + CLK_I : in STD_LOGIC; -- clock signal, rising edge + RST_I : in STD_LOGIC; -- reset signal, sync, active high + HALT_CLIENTS_O : out STD_LOGIC; -- halt both clients + +-- ############################################################################################### +-- ## Client Port 1 ## +-- ############################################################################################### + + CL1_ACC_REQ_I : in STD_LOGIC; -- access request + CL1_ADR_I : in STD_LOGIC_VECTOR(31 downto 00); -- address input + CL1_WR_DATA_I : in STD_LOGIC_VECTOR(31 downto 00); -- write data + CL1_RD_DATA_O : out STD_LOGIC_VECTOR(31 downto 00); -- read data + CL1_DQ_I : in STD_LOGIC_VECTOR(01 downto 00); -- data quantity + CL1_RW_I : in STD_LOGIC; -- read/write select + CL1_TAG_I : in STD_LOGIC_VECTOR(04 downto 00); -- tag input, here: mode + CL1_ABORT_O : out STD_LOGIC; -- access abort error + +-- ############################################################################################### +-- ## Client Port 2 ## +-- ############################################################################################### + + CL2_ACC_REQ_I : in STD_LOGIC; -- access request + CL2_ADR_I : in STD_LOGIC_VECTOR(31 downto 00); -- address input + CL2_WR_DATA_I : in STD_LOGIC_VECTOR(31 downto 00); -- write data + CL2_RD_DATA_O : out STD_LOGIC_VECTOR(31 downto 00); -- read data + CL2_DQ_I : in STD_LOGIC_VECTOR(01 downto 00); -- data quantity + CL2_RW_I : in STD_LOGIC; -- read/write select + CL2_TAG_I : in STD_LOGIC_VECTOR(04 downto 00); -- tag input, here: mode + CL2_ABORT_O : out STD_LOGIC; -- access abort error + +-- ############################################################################################### +-- ## Resource Port 1 ## +-- ############################################################################################### + + RE1_ADR_O : out STD_LOGIC_VECTOR(31 downto 00); -- address + RE1_WR_DATA_O : out STD_LOGIC_VECTOR(31 downto 00); -- write data + RE1_RD_DATA_I : in STD_LOGIC_VECTOR(31 downto 00); -- read data + RE1_BYTE_SEL_O : out STD_LOGIC_VECTOR(03 downto 00); -- byte select + RE1_RW_O : out STD_LOGIC; -- read/write + RE1_CS_O : out STD_LOGIC; -- chip select + RE1_DONE_I : in STD_LOGIC; -- transfer done + +-- ############################################################################################### +-- ## Resource Port 2 ## +-- ############################################################################################### + + RE2_ADR_O : out STD_LOGIC_VECTOR(31 downto 00); -- address + RE2_WR_DATA_O : out STD_LOGIC_VECTOR(31 downto 00); -- write data + RE2_RD_DATA_I : in STD_LOGIC_VECTOR(31 downto 00); -- read data + RE2_BYTE_SEL_O : out STD_LOGIC_VECTOR(03 downto 00); -- byte select + RE2_RW_O : out STD_LOGIC; -- read/write + RE2_CS_O : out STD_LOGIC; -- chip select + RE2_DONE_I : in STD_LOGIC -- transfer done + + ); +end ACCESS_ARBITER; + +architecture Structure of ACCESS_ARBITER is + + -- local signals -- + signal CL1_BYTE_SEL, CL2_BYTE_SEL : STD_LOGIC_VECTOR(03 downto 0); + signal CL1_O_INT, CL2_O_INT : STD_LOGIC_VECTOR(31 downto 0); + signal CL1_RE1_REQ, CL1_RE2_REQ : STD_LOGIC; + signal CL2_RE1_REQ, CL2_RE2_REQ : STD_LOGIC; + signal CL1_RE1_REQ_FF, CL1_RE2_REQ_FF : STD_LOGIC; + signal CL2_RE1_REQ_FF, CL2_RE2_REQ_FF : STD_LOGIC; + signal RE_NOT_RDY : STD_LOGIC; + signal COLLISION, COLL_FLAG : STD_LOGIC; + signal RE_ACC_SWITCH, RE_ACC_SWITCH_NXT : STD_LOGIC; + signal CL_RB_SEL, CL_RB_SEL_NXT : STD_LOGIC; + signal CL1_DELAY_EN, CL1_DELAY_EN_NXT : STD_LOGIC; + signal CL2_DELAY_EN, CL2_DELAY_EN_NXT : STD_LOGIC; + signal SAH_EN, SAH_EN_NXT : STD_LOGIC; + + -- Debug -- + signal buff1, buff2 : STD_LOGIC_VECTOR(31 downto 0); + signal sbuff1, sbuff2 : STD_LOGIC_VECTOR(31 downto 0); + +begin + + -- Data Quantity Decoder ------------------------------------------------------------------ + -- ------------------------------------------------------------------------------------------- + CLIENT1_DQ_DECODER: process(CL1_DQ_I, CL1_ADR_I(1 downto 0)) + variable TEMP : STD_LOGIC_VECTOR(03 downto 00); + begin + TEMP := CL1_DQ_I & CL1_ADR_I(1 downto 0); + case (TEMP) is + when "0000" | "0001" | "0010" | "0011" => -- WORD with any offset + CL1_BYTE_SEL <= "1111"; + when "0100" => -- BYTE with no offset + CL1_BYTE_SEL <= "0001"; + when "0101" => -- BYTE with one byte offset + CL1_BYTE_SEL <= "0010"; + when "0110" => -- BYTE with two bytes offset + CL1_BYTE_SEL <= "0100"; + when "0111" => -- BYTE with three bytes offset + CL1_BYTE_SEL <= "1000"; + when "1000" | "1100" => -- HALFWORD with no offset + CL1_BYTE_SEL <= "0011"; + when "1001" | "1101" => -- HALFWORD with one byte offset + CL1_BYTE_SEL <= "0110"; + when "1010" | "1110" => -- HALFWORD with two bytes offset + CL1_BYTE_SEL <= "1100"; + when others => -- HALFWORD with three bytes offset + CL1_BYTE_SEL <= "1001"; + end case; + end process CLIENT1_DQ_DECODER; + + + CLIENT2_DQ_DECODER: process(CL2_DQ_I, CL2_ADR_I(1 downto 0)) + variable TEMP : STD_LOGIC_VECTOR(03 downto 00); + begin + TEMP := CL2_DQ_I & CL2_ADR_I(1 downto 0); + case (TEMP) is + when "0000" | "0001" | "0010" | "0011" => -- WORD with any offset + CL2_BYTE_SEL <= "1111"; + when "0100" => -- BYTE with no offset + CL2_BYTE_SEL <= "0001"; + when "0101" => -- BYTE with one byte offset + CL2_BYTE_SEL <= "0010"; + when "0110" => -- BYTE with two bytes offset + CL2_BYTE_SEL <= "0100"; + when "0111" => -- BYTE with three bytes offset + CL2_BYTE_SEL <= "1000"; + when "1000" | "1100" => -- HALFWORD with no offset + CL2_BYTE_SEL <= "0011"; + when "1001" | "1101" => -- HALFWORD with one byte offset + CL2_BYTE_SEL <= "0110"; + when "1010" | "1110" => -- HALFWORD with two bytes offset + CL2_BYTE_SEL <= "1100"; + when others => -- HALFWORD with three bytes offset + CL2_BYTE_SEL <= "1001"; + end case; + end process CLIENT2_DQ_DECODER; + + + + -- Access Identification ------------------------------------------------------------------ + -- ------------------------------------------------------------------------------------------- + ACCESS_ID: process(CL1_ADR_I, CL2_ADR_I, CL1_ACC_REQ_I, CL2_ACC_REQ_I) + begin + --- Client 1 Access --- + if (to_integer(unsigned(CL1_ADR_I)) < SWITCH_ADR) then + CL1_RE1_REQ <= CL1_ACC_REQ_I; + CL1_RE2_REQ <= '0'; + else + CL1_RE1_REQ <= '0'; + CL1_RE2_REQ <= CL1_ACC_REQ_I; + end if; + + --- Client 2 Access --- + if (to_integer(unsigned(CL2_ADR_I)) < SWITCH_ADR) then + CL2_RE1_REQ <= CL2_ACC_REQ_I; + CL2_RE2_REQ <= '0'; + else + CL2_RE1_REQ <= '0'; + CL2_RE2_REQ <= CL2_ACC_REQ_I; + end if; + end process ACCESS_ID; + + --- Collision Detector --- + COLLISION <= (CL1_RE1_REQ and CL2_RE1_REQ) or (CL1_RE2_REQ and CL2_RE2_REQ); + + + + -- Collion HIStory Flag ------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + COLL_FLAG_SYNC: process(CLK_I, RST_I, COLLISION) + variable F_INT : STD_LOGIC; + begin + if rising_edge(CLK_I) then + if (RST_I = '1') then + F_INT := '0'; + else + F_INT := COLLISION and (not F_INT); + end if; + end if; + --- Collision HIStory Flag --- + COLL_FLAG <= F_INT; + end process COLL_FLAG_SYNC; + + --- Sample & Hold enable --- + SAH_EN_NXT <= (CL1_DELAY_EN or CL2_DELAY_EN) and (not COLL_FLAG) and (not SAH_EN) and COLLISION; + + --- Freeze Clients --- + HALT_CLIENTS_O <= COLLISION and (not COLL_FLAG); + + + + -- Access Arbiter ------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + lcars_de_command: process(COLLISION, COLL_FLAG, CL1_RE2_REQ, CL2_RE1_REQ) + variable TEMP : STD_LOGIC_VECTOR(1 downto 0); + begin + TEMP := COLLISION & COLL_FLAG; + case TEMP is + + when "00" => + RE_ACC_SWITCH <= CL1_RE2_REQ or CL2_RE1_REQ; -- 0: CL1 -> RE1, CL2 -> RE2 + + when "10" => + RE_ACC_SWITCH <= CL1_RE2_REQ or CL2_RE1_REQ; -- 0: CL1 -> RE1, CL2 -> RE2 + + when "11" => + RE_ACC_SWITCH <= not (CL1_RE2_REQ or CL2_RE1_REQ); -- 0: CL1 -> RE1, CL2 -> RE2 + + when others => + RE_ACC_SWITCH <= CL1_RE2_REQ or CL2_RE1_REQ; -- 0: CL1 -> RE1, CL2 -> RE2 + + end case; + end process lcars_de_command; + + + CL1_DELAY_EN_NXT <= '0';--COLLISION and (CL1_RE1_REQ_FF or CL1_RE2_REQ_FF); + CL2_DELAY_EN_NXT <= COLLISION and (CL2_RE1_REQ_FF or CL2_RE2_REQ_FF); + + + CTRL_UNIT: process(CLK_I, RST_I) + begin + --- Buffer FF's --- + if rising_edge(CLK_I) then + if (RST_I = '1') then + CL1_RE1_REQ_FF <= '0'; + CL1_RE2_REQ_FF <= '0'; + CL2_RE1_REQ_FF <= '0'; + CL2_RE2_REQ_FF <= '0'; + CL_RB_SEL <= '0'; + CL1_DELAY_EN <= '0'; + CL2_DELAY_EN <= '0'; + SAH_EN <= '0'; + else + CL_RB_SEL <= RE_ACC_SWITCH; + CL1_DELAY_EN <= CL1_DELAY_EN_NXT; + CL2_DELAY_EN <= CL2_DELAY_EN_NXT; + SAH_EN <= SAH_EN_NXT; + if ((COLLISION and (not COLL_FLAG)) = '0') then + CL1_RE1_REQ_FF <= CL1_RE1_REQ; + CL1_RE2_REQ_FF <= CL1_RE2_REQ; + CL2_RE1_REQ_FF <= CL2_RE1_REQ; + CL2_RE2_REQ_FF <= CL2_RE2_REQ; + end if; + end if; + end if; + end process CTRL_UNIT; + + + + -- Access Control Output Switch ----------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + RE1_ADR_O <= CL1_ADR_I when (RE_ACC_SWITCH = '0') else CL2_ADR_I; + RE1_WR_DATA_O <= CL1_WR_DATA_I when (RE_ACC_SWITCH = '0') else CL2_WR_DATA_I; + RE1_BYTE_SEL_O <= CL1_BYTE_SEL when (RE_ACC_SWITCH = '0') else CL2_BYTE_SEL; + RE1_RW_O <= CL1_RW_I when (RE_ACC_SWITCH = '0') else CL2_RW_I; + RE1_CS_O <= CL1_RE1_REQ or CL2_RE1_REQ; + + RE2_ADR_O <= CL1_ADR_I when (RE_ACC_SWITCH = '1') else CL2_ADR_I; + RE2_WR_DATA_O <= CL1_WR_DATA_I when (RE_ACC_SWITCH = '1') else CL2_WR_DATA_I; + RE2_BYTE_SEL_O <= CL1_BYTE_SEL when (RE_ACC_SWITCH = '1') else CL2_BYTE_SEL; + RE2_RW_O <= CL1_RW_I when (RE_ACC_SWITCH = '1') else CL2_RW_I; + RE2_CS_O <= CL1_RE2_REQ or CL2_RE2_REQ; + + + + -- Read-Back Control ---------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + RB_CTRL: process(CLK_I, RST_I, CL_RB_SEL, CL1_DELAY_EN, SAH_EN, RE1_RD_DATA_I, RE2_RD_DATA_I, CL2_DELAY_EN) + variable CL1_INT, CL2_INT : STD_LOGIC_VECTOR(31 downto 0); + variable CL1_BUFFER, CL2_BUFFER : STD_LOGIC_VECTOR(31 downto 0); + begin + --- Client RB select --- + if (CL_RB_SEL = '0') then + CL1_INT := RE1_RD_DATA_I; + CL2_INT := RE2_RD_DATA_I; + else + CL1_INT := RE2_RD_DATA_I; + CL2_INT := RE1_RD_DATA_I; + end if; + + --- Client 1 buffer --- + if rising_edge(CLK_I) then + if (RST_I = '1') then + CL1_BUFFER := (others => '0'); + CL2_BUFFER := (others => '0'); + else + CL1_BUFFER := CL1_INT; + CL2_BUFFER := CL2_INT; + end if; + end if; + buff1 <= CL1_BUFFER; + buff2 <= CL2_BUFFER; + if (CL1_DELAY_EN = '1') then + CL1_O_INT <= CL1_BUFFER; + else + CL1_O_INT <= CL1_INT; + end if; + if (CL2_DELAY_EN = '1') then + CL2_O_INT <= CL2_BUFFER; + else + CL2_O_INT <= CL2_INT; + end if; + end process RB_CTRL; + + + SAMPLE_AND_HOLD: process(CLK_I, RST_I, CL1_O_INT, CL2_O_INT, SAH_EN) + variable CL1_SAH, CL2_SAH : STD_LOGIC_VECTOR(31 downto 0); + begin + --- Sample & Hold --- + if rising_edge(CLK_I) then + if (RST_I = '1') then + CL1_SAH := (others => '0'); + CL2_SAH := (others => '0'); + else + CL1_SAH := CL1_O_INT; + CL2_SAH := CL2_O_INT; + end if; + end if; + sbuff1 <= CL1_SAH; + sbuff2 <= CL2_SAH; + if (MEM_RB_SYNC_FF_EN = FALSE) then + if (SAH_EN = '1') then + CL1_RD_DATA_O <= CL1_SAH; + CL2_RD_DATA_O <= CL2_SAH; + else + CL1_RD_DATA_O <= CL1_O_INT; + CL2_RD_DATA_O <= CL2_O_INT; + end if; + else + if falling_edge(CLK_I) then + if (SAH_EN = '1') then + CL1_RD_DATA_O <= CL1_SAH; + CL2_RD_DATA_O <= CL2_SAH; + else + CL1_RD_DATA_O <= CL1_O_INT; + CL2_RD_DATA_O <= CL2_O_INT; + end if; + end if; + end if; + end process SAMPLE_AND_HOLD; + + + + -- Resource Timeout Counter --------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + TIMEOUT_CNT: process(CLK_I, RST_I, RE1_DONE_I, CL1_RE1_REQ, CL2_RE1_REQ, RE2_DONE_I, CL1_RE2_REQ, CL2_RE2_REQ) + variable CNT_RE1 : integer range 0 to RE1_TO_CNT; + variable CL1_RE1, CL2_RE1 : std_logic; + variable CNT_RE2 : integer range 0 to RE2_TO_CNT; + variable CL1_RE2, CL2_RE2 : std_logic; + begin + --- Timeout Resource 1 Counter --- + if rising_edge(CLK_I) then + if (RST_I = '1') or (RE1_DONE_I = '1') then + CNT_RE1 := 0; + CL1_RE1 := '0'; + CL2_RE1 := '0'; + elsif (CL1_RE1_REQ = '1') or (CL2_RE1_REQ = '1') then + CNT_RE1 := RE1_TO_CNT; + CL1_RE1 := CL1_RE1_REQ; + CL2_RE1 := CL2_RE1_REQ; + elsif (CNT_RE1 /= 0) then + CNT_RE1 := CNT_RE1 - 1; + CL1_RE1 := CL1_RE1; + CL2_RE1 := CL2_RE1; + end if; + end if; + + --- Timeout Resource 2 Counter --- + if rising_edge(CLK_I) then + if (RST_I = '1') or (RE2_DONE_I = '1') then + CNT_RE2 := 0; + CL1_RE2 := '0'; + CL2_RE2 := '0'; + elsif (CL1_RE2_REQ = '1') or (CL2_RE2_REQ = '1') then + CNT_RE2 := RE2_TO_CNT; + CL1_RE2 := CL1_RE2_REQ; + CL2_RE2 := CL2_RE2_REQ; + elsif (CNT_RE2 /= 0) then + CNT_RE2 := CNT_RE2 - 1; + CL1_RE2 := CL1_RE2; + CL2_RE2 := CL2_RE2; + end if; + end if; + + --- Interrupt for client 1 when time out --- + if (CNT_RE2 = 1) and (CL1_INT_EN = TRUE) then + CL1_ABORT_O <= CL1_RE1 or CL1_RE2; + else + CL1_ABORT_O <= '0'; + end if; + + --- Interrupt for client 2 when time out --- + if (CNT_RE2 = 1) and (CL2_INT_EN = TRUE) then + CL2_ABORT_O <= CL2_RE1 or CL2_RE2; + else + CL2_ABORT_O <= '0'; + end if; + + end process TIMEOUT_CNT; + + -- resource not ready signal -- + RE_NOT_RDY <= not (RE1_DONE_I and RE2_DONE_I); + + + +end Structure; \ No newline at end of file Index: storm_core/trunk/rtl/LOGICAL_UNIT.vhd =================================================================== --- storm_core/trunk/rtl/LOGICAL_UNIT.vhd (nonexistent) +++ storm_core/trunk/rtl/LOGICAL_UNIT.vhd (revision 10) @@ -0,0 +1,120 @@ +-- ####################################################### +-- # < STORM CORE PROCESSOR by Stephan Nolting > # +-- # *************************************************** # +-- # Logical Operation Unit # +-- # *************************************************** # +-- # Version 1.5, 18.03.2011 # +-- ####################################################### + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +library work; +use work.STORM_core_package.all; + +entity LOGICAL_UNIT is + port ( + -- Function Operands -- + -------------------------------------------------- + OP_A : in STD_LOGIC_VECTOR(31 downto 0); + OP_B : in STD_LOGIC_VECTOR(31 downto 0); + RESULT : out STD_LOGIC_VECTOR(31 downto 0); + + -- Flag Operands -- + -------------------------------------------------- + BS_CRY_IN : in STD_LOGIC; + BS_OVF_IN : in STD_LOGIC; + L_CARRY_IN : in STD_LOGIC; + FLAG_OUT : out STD_LOGIC_VECTOR(03 downto 0); + + -- Operation Control -- + -------------------------------------------------- + CTRL : in STD_LOGIC_VECTOR(02 downto 0) + ); +end LOGICAL_UNIT; + +architecture Behavioral of LOGICAL_UNIT is + + -- local signals -- + signal RESULT_TMP : STD_LOGIC_VECTOR(31 downto 0); -- internal result bus + signal TEMP_ZERO : STD_LOGIC_VECTOR(31 downto 0); -- zero result + +begin + + + -- Logical Unit ---------------------------------------------------------------------------------------- + -- -------------------------------------------------------------------------------------------------------- + LOGICAL_CORE: process(CTRL, OP_A, OP_B, L_CARRY_IN) + begin + case(LOGICAL_OP & CTRL) is -- ALU_FS + + -- AND: result = OP_A AND OP_B -- + when L_AND => + RESULT_TMP <= OP_A and OP_B; + + -- OR: result = OP_A OR OP_B -- + when L_OR => + RESULT_TMP <= OP_A or OP_B; + + -- XOR: result = OP_A XOR OP_B -- + when L_XOR => + RESULT_TMP <= OP_A xor OP_B; + + -- NOT: result = not(OP_A AND OP_B) -- + when L_NOT => + if (STORM_MODE = TRUE) then + RESULT_TMP <= not(OP_A and OP_B); + else + RESULT_TMP <= not OP_B; -- ARM_OP: MVN + end if; + + -- BIC: result = OP_A and (not OP_B) -- + when L_BIC => + RESULT_TMP <= OP_A and (not OP_B); + + -- MOV: result = OP_B -- + when L_MOV => + RESULT_TMP <= OP_B; -- boring, huh? + + -- TST: result = OP_B, compares by F = OP_A and OP_B -- + when L_TST => + RESULT_TMP <= OP_B; + + -- TEQ: result = OP_A, compares by F = OP_A xor OP_B -- + when L_TEQ => + RESULT_TMP <= OP_A; + + -- Undefined -- + when others => + RESULT_TMP <= (others => '0'); + + end case; + end process LOGICAL_CORE; + + RESULT <= RESULT_TMP; + + + + -- FLAG Logic ------------------------------------------------------------------------------------------ + -- -------------------------------------------------------------------------------------------------------- + + -- carry flag -- + FLAG_OUT(0) <= BS_CRY_IN when (CTRL = "110") else + BS_CRY_IN when (CTRL = "111") else L_CARRY_IN; + + -- zero flag -- + TEMP_ZERO <= (OP_A and OP_B) when (CTRL = "110") else + (OP_A xor OP_B) when (CTRL = "111") else RESULT_TMP; + + FLAG_OUT(1) <= '1' when (TEMP_ZERO = x"00000000") else '0'; + + -- negative flag -- + FLAG_OUT(2) <= (OP_A(31) and OP_B(31)) when (CTRL = "110") else + (OP_A(31) xor OP_B(31)) when (CTRL = "111") else RESULT_TMP(31); + + -- overflow flag -- + FLAG_OUT(3) <= BS_OVF_IN; -- keep barrelsshifter's overflow flag + + + +end Behavioral; \ No newline at end of file Index: storm_core/trunk/rtl/STORM_TOP_TB.vhd =================================================================== --- storm_core/trunk/rtl/STORM_TOP_TB.vhd (nonexistent) +++ storm_core/trunk/rtl/STORM_TOP_TB.vhd (revision 10) @@ -0,0 +1,91 @@ +-- ###################################################### +-- # < STORM CORE SYSTEM by Stephan Nolting > # +-- # ************************************************** # +-- # STORM CORE SYSTEM Testbench # +-- # ************************************************** # +-- # Version 1.0, 20.07.2011 # +-- ###################################################### + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity STORM_TOP_TB is +end STORM_TOP_TB; + +architecture Structure of STORM_TOP_TB is + + -- clock/reset -- + signal CLK, RES : STD_LOGIC := '0'; + + -- wishbone interface -- + signal WB_DATA_I : std_logic_vector(31 downto 0); + signal WB_DATA_O : std_logic_vector(31 downto 0); + signal WB_ADR_O : std_logic_vector(31 downto 0); + signal WB_ACK_I : std_logic; + signal WB_SEL_O : std_logic_vector(03 downto 0); + signal WB_WE_O : std_logic; + signal WB_STB_O : std_logic; + signal WB_CYC_O : std_logic; + + -- debug signals -- + signal IN32, OUT32 : std_logic_vector(31 downto 0); + + -- STORM SYSTEM TOP ENTITY -------------------- + -- ----------------------------------------------- + component STORM_TOP + port ( + CLK_I : in std_logic; + RST_I : in std_logic; + WB_DATA_I : in std_logic_vector(31 downto 0); + WB_DATA_O : out std_logic_vector(31 downto 0); + WB_ADR_O : out std_logic_vector(31 downto 0); + WB_ACK_I : in std_logic; + WB_SEL_O : out std_logic_vector(03 downto 0); + WB_WE_O : out std_logic; + WB_STB_O : out std_logic; + WB_CYC_O : out std_logic; + MODE_O : out std_logic_vector(04 downto 0); + D_ABT_I : in std_logic; + I_ABT_I : in std_logic; + IRQ_I : in std_logic; + FIQ_I : in std_logic + ); + end component; + +begin + + -- STORM CORE SYSTEM ---------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + STORM_TOP_INST: STORM_TOP + port map ( + CLK_I => CLK, + RST_I => RES, + WB_DATA_I => WB_DATA_I, + WB_DATA_O => WB_DATA_O, + WB_ADR_O => WB_ADR_O, + WB_ACK_I => WB_ACK_I, + WB_SEL_O => WB_SEL_O, + WB_WE_O => WB_WE_O, + WB_STB_O => WB_STB_O, + WB_CYC_O => WB_CYC_O, + MODE_O => open, + D_ABT_I => '0', + I_ABT_I => '0', + IRQ_I => '0', + FIQ_I => '0' + ); + + -- Clock/Reset Generator ------------------------------------------------------------------ + -- ------------------------------------------------------------------------------------------- + CLK <= not CLK after 20 ns; + RES <= '1', '0' after 170 ns; + + + -- Wishbone simulation -------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + WB_DATA_I <= (others => '0'); + WB_ACK_I <= '1'; + + +end Structure; \ No newline at end of file Index: storm_core/trunk/rtl/REG_FILE.vhd =================================================================== --- storm_core/trunk/rtl/REG_FILE.vhd (nonexistent) +++ storm_core/trunk/rtl/REG_FILE.vhd (revision 10) @@ -0,0 +1,301 @@ +-- ####################################################### +-- # < STORM CORE PROCESSOR by Stephan Nolting > # +-- # *************************************************** # +-- # 30x32-Bit Banked 1w3r Register File # +-- # (+ address translation unit) # +-- # *************************************************** # +-- # Version 2.3, 28.05.2011 # +-- ####################################################### + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +library work; +use work.STORM_core_package.all; + +entity REG_FILE is + port ( +-- ############################################################################################### +-- ## Global Control ## +-- ############################################################################################### + + CLK : in STD_LOGIC; -- global clock network + G_HALT : in STD_LOGIC; -- global halt line + RES : in STD_LOGIC; -- global reset network + +-- ############################################################################################### +-- ## Local Control ## +-- ############################################################################################### + + CTRL_IN : in STD_LOGIC_VECTOR(31 downto 0); -- control lines + OP_ADR_IN : in STD_LOGIC_VECTOR(14 downto 0); -- operand addresses + MODE_IN : in STD_LOGIC_VECTOR(04 downto 0); -- current operation mode + +-- ############################################################################################### +-- ## Operand Connection ## +-- ############################################################################################### + + WB_DATA_IN : in STD_LOGIC_VECTOR(31 downto 0); -- write back data path + REG_PC_IN : in STD_LOGIC_VECTOR(31 downto 0); -- current program counter + + OP_A_OUT : out STD_LOGIC_VECTOR(31 downto 0); -- register A output + OP_B_OUT : out STD_LOGIC_VECTOR(31 downto 0); -- register B output + OP_C_OUT : out STD_LOGIC_VECTOR(31 downto 0) -- register C output + + ); +end REG_FILE; + +architecture REG_FILE_STRUCTURE of REG_FILE is + + -- Data Register File -- + type REG_FILE_TYPE is array (0 to 31) of STD_LOGIC_VECTOR(31 downto 0); + signal REG_FILE : REG_FILE_TYPE := + ( + x"00000000", x"00000000", x"00000000", x"00000000", + x"00000000", x"00000000", x"00000000", x"00000000", + x"00000000", x"00000000", x"00000000", x"00000000", + x"00000000", x"00000000", x"00000000", x"00000000", + x"00000000", x"00000000", x"00000000", x"00000000", + x"00000000", x"00000000", x"00000000", x"00000000", + x"00000000", x"00000000", x"00000000", x"00000000", + x"00000000", x"00000000", x"00000000", x"00000000" + ); + + -- Memory <-> Register Allocation Map + -- ------------------------------------------------------------------------ + -- 00: USR32 R0 10: USR32 R10 20: FIQ32 R13 30: Dummy Reg + -- 01: USR32 R1 11: USR32 R11 21: FIQ32 R14 LR 31: Dummy Reg + -- 02: USR32 R2 12: USR32 R12 22: SVP32 R13 + -- 03: USR32 R3 13: USR32 R13 23: SVP32 R14 LR + -- 04: USR32 R4 14: USR32 R14 LR 24: ABT32 R13 + -- 05: USR32 R5 15: FIQ32 R8 25: ABT32 R14 LR + -- 06: USR32 R6 16: FIQ32 R9 26: IRQ32 R13 + -- 07: USR32 R7 17: FIQ32 R10 27: IRQ32 R14 LR + -- 08: USR32 R8 18: FIQ32 R11 28: UND32 R13 + -- 09: USR32 R9 19: FIQ32 R12 29: UND32 R14 LR + + -- Address Busses -- + signal R_ADR_PORT_A, R_ADR_PORT_B, R_ADR_PORT_C : STD_LOGIC_VECTOR(4 downto 0); + signal W_ADR_PORT : STD_LOGIC_VECTOR(4 downto 0); + + -- Address Translator -- + component ADR_TRANSLATION_UNIT + port ( + REG_ADR_IN : in STD_LOGIC_VECTOR(3 downto 0); + MODE_IN : in STD_LOGIC_VECTOR(4 downto 0); + ADR_OUT : out STD_LOGIC_VECTOR(4 downto 0) + ); + end component; + +begin + + -- Register File Write Access --------------------------------------------------------------------- + -- --------------------------------------------------------------------------------------------------- + + --- Write Access Data Port --- + write_access_data_port: + ADR_TRANSLATION_UNIT + port map ( + REG_ADR_IN => CTRL_IN(CTRL_RD_3 downto CTRL_RD_0), + MODE_IN => CTRL_IN(CTRL_MODE_4 downto CTRL_MODE_0), + ADR_OUT => W_ADR_PORT + ); + + --- Clock Triggered Write --- + SYNCHRONOUS_MEM_WRITE: process(CLK, W_ADR_PORT, WB_DATA_IN, CTRL_IN) + begin + if rising_edge(CLK) then + if ((CTRL_IN(CTRL_EN) = '1') and (CTRL_IN(CTRL_WB_EN)) = '1') and (G_HALT = '0') then + REG_FILE(to_integer(unsigned(W_ADR_PORT))) <= WB_DATA_IN; + end if; + end if; + end process SYNCHRONOUS_MEM_WRITE; + + + + -- Register File Read Access ---------------------------------------------------------------------- + -- --------------------------------------------------------------------------------------------------- + + --- Read Access Port A --- + read_access_port_a: + ADR_TRANSLATION_UNIT + port map ( + REG_ADR_IN => OP_ADR_IN(OP_A_ADR_3 downto OP_A_ADR_0), + MODE_IN => MODE_IN, + ADR_OUT => R_ADR_PORT_A + ); + + --- Read Access Port B --- + read_access_port_b: + ADR_TRANSLATION_UNIT + port map ( + REG_ADR_IN => OP_ADR_IN(OP_B_ADR_3 downto OP_B_ADR_0), + MODE_IN => MODE_IN, + ADR_OUT => R_ADR_PORT_B + ); + + --- Read Access Port C --- + read_access_port_c: + ADR_TRANSLATION_UNIT + port map ( + REG_ADR_IN => OP_ADR_IN(OP_C_ADR_3 downto OP_C_ADR_0), + MODE_IN => MODE_IN, + ADR_OUT => R_ADR_PORT_C + ); + + + --- Memory Read Access --- + OP_A_OUT <= REG_FILE(to_integer(unsigned(R_ADR_PORT_A))) when + (OP_ADR_IN(OP_A_ADR_3 downto OP_A_ADR_0) /= C_PC_ADR) else REG_PC_IN; + OP_B_OUT <= REG_FILE(to_integer(unsigned(R_ADR_PORT_B))) when + (OP_ADR_IN(OP_B_ADR_3 downto OP_B_ADR_0) /= C_PC_ADR) else REG_PC_IN; + OP_C_OUT <= REG_FILE(to_integer(unsigned(R_ADR_PORT_C))) when + (OP_ADR_IN(OP_C_ADR_3 downto OP_C_ADR_0) /= C_PC_ADR) else REG_PC_IN; + + +end REG_FILE_STRUCTURE; + + +---------------------------------------------------------------------------------------------------------------- +---------------------------------------------------------------------------------------------------------------- + + +-- ####################################################### +-- # < STORM CORE PROCESSOR by Stephan Nolting > # +-- # *************************************************** # +-- # REG-FILE Address Translation Unit # +-- # *************************************************** # +-- # Version 1.1, 28.05.2011 # +-- ####################################################### + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +library work; +use work.STORM_core_package.all; + +entity ADR_TRANSLATION_UNIT is + port ( + -- Register Address Input -- + -------------------------------------------------- + REG_ADR_IN : in STD_LOGIC_VECTOR(3 downto 0); + + -- MODE Input -- + -------------------------------------------------- + MODE_IN : in STD_LOGIC_VECTOR(4 downto 0); + + -- Memory Address Output -- + -------------------------------------------------- + ADR_OUT : out STD_LOGIC_VECTOR(4 downto 0) + ); +end ADR_TRANSLATION_UNIT; + +architecture ADRTU_STRUCTURE of ADR_TRANSLATION_UNIT is + +begin + + -- Address Translator ----------------------------------------------------------------------------- + -- --------------------------------------------------------------------------------------------------- + ADR_TRANSLATOR: process(REG_ADR_IN, MODE_IN) + variable VIRT_REG_SEL : STD_LOGIC_VECTOR(15 downto 0); + variable REAL_REG_SEL : STD_LOGIC_VECTOR(31 downto 0); + begin + + --- One-Hot Virtual Register Select --- + case (REG_ADR_IN) is + when "0000" => VIRT_REG_SEL := "0000000000000001"; -- R0_ + when "0001" => VIRT_REG_SEL := "0000000000000010"; -- R1_ + when "0010" => VIRT_REG_SEL := "0000000000000100"; -- R2_ + when "0011" => VIRT_REG_SEL := "0000000000001000"; -- R3_ + when "0100" => VIRT_REG_SEL := "0000000000010000"; -- R4_ + when "0101" => VIRT_REG_SEL := "0000000000100000"; -- R5_ + when "0110" => VIRT_REG_SEL := "0000000001000000"; -- R6_ + when "0111" => VIRT_REG_SEL := "0000000010000000"; -- R7_ + when "1000" => VIRT_REG_SEL := "0000000100000000"; -- R8_ + when "1001" => VIRT_REG_SEL := "0000001000000000"; -- R9_ + when "1010" => VIRT_REG_SEL := "0000010000000000"; -- R10_ + when "1011" => VIRT_REG_SEL := "0000100000000000"; -- R11_ + when "1100" => VIRT_REG_SEL := "0001000000000000"; -- R12_ + when "1101" => VIRT_REG_SEL := "0010000000000000"; -- R13_ + when "1110" => VIRT_REG_SEL := "0100000000000000"; -- R14_ + when "1111" => VIRT_REG_SEL := "1000000000000000"; -- DUMMY PC + when others => VIRT_REG_SEL := "0000000000000000"; -- undefined + end case; + + --- Address Mapping: Virtual Register -> Real Register --- + REAL_REG_SEL := (others => '0'); + REAL_REG_SEL(07 downto 00) := VIRT_REG_SEL(07 downto 00); -- R0-R7 are always the same + REAL_REG_SEL(31) := VIRT_REG_SEL(15); -- PC access = dummy access + + case (MODE_IN) is + + when User32_MODE => + REAL_REG_SEL(14 downto 08) := VIRT_REG_SEL(14 downto 08); + + when FIQ32_MODE => + REAL_REG_SEL(21 downto 15) := VIRT_REG_SEL(14 downto 08); + + when Supervisor32_MODE => + REAL_REG_SEL(12 downto 08) := VIRT_REG_SEL(12 downto 08); + REAL_REG_SEL(23 downto 22) := VIRT_REG_SEL(14 downto 13); + + when Abort32_MODE => + REAL_REG_SEL(12 downto 08) := VIRT_REG_SEL(12 downto 08); + REAL_REG_SEL(25 downto 24) := VIRT_REG_SEL(14 downto 13); + + when IRQ32_MODE => + REAL_REG_SEL(12 downto 08) := VIRT_REG_SEL(12 downto 08); + REAL_REG_SEL(27 downto 26) := VIRT_REG_SEL(14 downto 13); + + when Undefined32_MODE => + REAL_REG_SEL(12 downto 08) := VIRT_REG_SEL(12 downto 08); + REAL_REG_SEL(29 downto 28) := VIRT_REG_SEL(14 downto 13); + + when others => + REAL_REG_SEL(29 downto 00) := (others => '0'); + + end case; + + --- Address Encoder --- + case (REAL_REG_SEL) is + when "00000000000000000000000000000001" => ADR_OUT <= "00000"; + when "00000000000000000000000000000010" => ADR_OUT <= "00001"; + when "00000000000000000000000000000100" => ADR_OUT <= "00010"; + when "00000000000000000000000000001000" => ADR_OUT <= "00011"; + when "00000000000000000000000000010000" => ADR_OUT <= "00100"; + when "00000000000000000000000000100000" => ADR_OUT <= "00101"; + when "00000000000000000000000001000000" => ADR_OUT <= "00110"; + when "00000000000000000000000010000000" => ADR_OUT <= "00111"; + when "00000000000000000000000100000000" => ADR_OUT <= "01000"; + when "00000000000000000000001000000000" => ADR_OUT <= "01001"; + when "00000000000000000000010000000000" => ADR_OUT <= "01010"; + when "00000000000000000000100000000000" => ADR_OUT <= "01011"; + when "00000000000000000001000000000000" => ADR_OUT <= "01100"; + when "00000000000000000010000000000000" => ADR_OUT <= "01101"; + when "00000000000000000100000000000000" => ADR_OUT <= "01110"; + when "00000000000000001000000000000000" => ADR_OUT <= "01111"; + when "00000000000000010000000000000000" => ADR_OUT <= "10000"; + when "00000000000000100000000000000000" => ADR_OUT <= "10001"; + when "00000000000001000000000000000000" => ADR_OUT <= "10010"; + when "00000000000010000000000000000000" => ADR_OUT <= "10011"; + when "00000000000100000000000000000000" => ADR_OUT <= "10100"; + when "00000000001000000000000000000000" => ADR_OUT <= "10101"; + when "00000000010000000000000000000000" => ADR_OUT <= "10110"; + when "00000000100000000000000000000000" => ADR_OUT <= "10111"; + when "00000001000000000000000000000000" => ADR_OUT <= "11000"; + when "00000010000000000000000000000000" => ADR_OUT <= "11001"; + when "00000100000000000000000000000000" => ADR_OUT <= "11010"; + when "00001000000000000000000000000000" => ADR_OUT <= "11011"; + when "00010000000000000000000000000000" => ADR_OUT <= "11100"; + when "00100000000000000000000000000000" => ADR_OUT <= "11101"; + when "01000000000000000000000000000000" => ADR_OUT <= "11110"; + when "10000000000000000000000000000000" => ADR_OUT <= "11111"; + when others => ADR_OUT <= "11111"; + end case; + + end process ADR_TRANSLATOR; + + +end ADRTU_STRUCTURE; \ No newline at end of file Index: storm_core/trunk/rtl/STORM_core.vhd =================================================================== --- storm_core/trunk/rtl/STORM_core.vhd (nonexistent) +++ storm_core/trunk/rtl/STORM_core.vhd (revision 10) @@ -0,0 +1,502 @@ +-- ####################################################### +-- # STORM core system package # +-- # Created by Stephan Nolting (4788) # +-- # +-------------------------------------------------+ # +-- # Core Components Hierarchy: # +-- # - STORM_TOP.vhd # +-- # + STORM_CORE.vhd (this file) # +-- # - SYSTEM_BRIDGE.vhd # +-- # - MEMORY.vhd # +-- # - WISHBONE_IO.vhd # +-- # - CORE.vhd # +-- # - REG_FILE.vhd # +-- # - ADR_TRANSLATOR (same file) # +-- # - OPERANT_UNIT.vhd # +-- # - MS_UNIT.vhd # +-- # - MULTIPLICATION_UNIT.vhd # +-- # - BARREL_SHIFTER.vhd # +-- # - ALU.vhd # +-- # - ARITHMETICAL_UNIT.vhd # +-- # - LOGICAL_UNIT.vhd # +-- # - FLOW_CTRL.vhd # +-- # - WB_UNIT.vhd # +-- # - MCR_SYS.vhd # +-- # - LOAD_STORE_UNIT.vhd # +-- # - X1_OPCODE_DECODER.vhd # +-- # +-------------------------------------------------+ # +-- # Version 2.4.3, 19.07.2011 # +-- ####################################################### + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +package STORM_core_package is + + -- ARCHITECTURE CONSTANTS ----------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + constant STORM_MODE : boolean := FALSE; -- use STORM extension architecture + constant USE_BIG_ENDIAN : boolean := TRUE; -- use big endian memory + constant MEM_RB_SYNC_FF_EN : boolean := TRUE; -- memory readback sync (only for simulation?!) + constant NOP_CMD : STD_LOGIC_VECTOR(31 downto 00) := x"F0013007"; -- Dummy OPCODE + + -- DUMMY CYCLES FOR TEMPORAL PIPELINE CONFLICTS ------------------------------------------- + -- ------------------------------------------------------------------------------------------- + constant DC_TAKEN_BRANCH : natural := 2; -- empty cycles after taken branch + constant OF_MS_REG_DD : natural := 1; -- of-ms reg/reg conflict + constant OF_WB_MEM_DD : natural := 1; -- of-wb reg/mem conflict + constant OF_EX_MEM_DD : natural := 2; -- of-ex reg/mem conflict + constant OF_MS_MEM_DD : natural := 3; -- of-ms reg/mem conflict + + -- ADDRESS CONSTANTS ---------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + constant C_SP_ADR : STD_LOGIC_VECTOR(3 downto 0) := "1101"; -- Stack Pointer = R13 + constant C_LR_ADR : STD_LOGIC_VECTOR(3 downto 0) := "1110"; -- Link Register = R14 + constant C_PC_ADR : STD_LOGIC_VECTOR(3 downto 0) := "1111"; -- Prog. Counter = R15 + + -- OPERAND ADR BUS LOCATIONS -------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + constant OP_A_ADR_0 : natural := 0; -- OP A ADR LSB + constant OP_A_ADR_3 : natural := 3; -- OP A ADR MSB + constant OP_B_ADR_0 : natural := 4; -- OP B ADR LSB + constant OP_B_ADR_3 : natural := 7; -- OP B ADR MSB + constant OP_C_ADR_0 : natural := 8; -- OP C ADR LSB + constant OP_C_ADR_3 : natural := 11; -- OP C ADR MSB + constant OP_A_IS_REG : natural := 12; -- OP A is a reg adr + constant OP_B_IS_REG : natural := 13; -- OP B is a reg adr + constant OP_C_IS_REG : natural := 14; -- OP C is a reg adr + + -- OPERAND CONSTANTS ---------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + constant RD : STD_LOGIC := '0'; + constant WR : STD_LOGIC := '1'; + constant DQ_WORD : STD_LOGIC_VECTOR(1 downto 0) := "00"; + constant DQ_BYTE : STD_LOGIC_VECTOR(1 downto 0) := "01"; + constant DQ_HALFWORD : STD_LOGIC_VECTOR(1 downto 0) := "10"; -- "11" + + -- FORWARDING BUS LOCATIONS --------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + constant FWD_DATA_LSB : natural := 0; -- Forwardind Data Bit 0 + constant FWD_DATA_MSB : natural := 31; -- Forwarding Data Bit 31 + constant FWD_RD_LSB : natural := 32; -- Destination Adr Bit 0 + constant FWD_RD_MSB : natural := 35; -- Destination Adr Bit 3 + constant FWD_WB : natural := 36; -- Data in stage will be written back to reg + constant FWD_CY_NEED : natural := 37; -- Carry flag is needed + constant FWD_MCR_ACC : natural := 38; -- MCR Access + constant FWD_MEM_R_ACC : natural := 40; -- Memory Read Access + constant FWD_MEM_ACC : natural := 41; -- Memory Access + + -- CTRL BUS LOCATIONS --------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + constant CTRL_EN : natural := 0; -- stage enable + constant CTRL_CONST : natural := 1; -- is immediate value + constant CTRL_BRANCH : natural := 2; -- branch control + constant CTRL_LINK : natural := 3; -- link + constant CTRL_SHIFTR : natural := 4; -- use register shift offset + constant CTRL_WB_EN : natural := 5; -- write back enable + + constant CTRL_RD_0 : natural := 6; -- destination register adr bit 0 + constant CTRL_RD_1 : natural := 7; -- destination register adr bit 1 + constant CTRL_RD_2 : natural := 8; -- destination register adr bit 2 + constant CTRL_RD_3 : natural := 9; -- destination register adr bit 3 + + constant CTRL_SWI : natural := 10; -- software interrup + constant CTRL_UND : natural := 11; -- undefined instruction interrupt + + constant CTRL_COND_0 : natural := 12; -- condition code bit 0 + constant CTRL_COND_1 : natural := 13; -- condition code bit 1 + constant CTRL_COND_2 : natural := 14; -- condition code bit 2 + constant CTRL_COND_3 : natural := 15; -- condition code bit 3 + + constant CTRL_MS : natural := 16; -- '0' = shift, '1' = multiply + constant CTRL_AF : natural := 17; -- alter alu flags + constant CTRL_ALU_FS_0 : natural := 18; -- alu function set bit 0 + constant CTRL_ALU_FS_1 : natural := 19; -- alu function set bit 1 + constant CTRL_ALU_FS_2 : natural := 20; -- alu function set bit 2 + constant CTRL_ALU_FS_3 : natural := 21; -- alu function set bit 3 + + constant CTRL_MEM_ACC : natural := 22; -- '1' = Access memory + constant CTRL_MEM_DQ_0 : natural := 23; -- '0' = word, '1' = byte + constant CTRL_MEM_DQ_1 : natural := 24; -- '0' = see above, '1' = halfword + constant CTRL_MEM_SE : natural := 25; -- '0' = no sign extension, '1' = sign extension + constant CTRL_MEM_RW : natural := 26; -- '0' = read, '1' = write + constant CTRL_MEM_USER : natural := 27; -- '1' = acceess memory with "user_mode" output + + constant CTRL_MREG_ACC : natural := 28; -- '1' = Access machine register file + constant CTRL_MREG_M : natural := 29; -- '0' = CMSR, '1' = SMSR + constant CTRL_MREG_RW : natural := 30; -- '0' = read, '1' = write + constant CTRL_MREG_FA : natural := 31; -- '0' = whole access, '1' = flag access + + -- Progress Redefinitions -- + constant CTRL_MODE_0 : natural := CTRL_AF; -- mode bit 0 + constant CTRL_MODE_1 : natural := CTRL_ALU_FS_0; -- mode bit 1 + constant CTRL_MODE_2 : natural := CTRL_ALU_FS_1; -- mode bit 2 + constant CTRL_MODE_3 : natural := CTRL_ALU_FS_2; -- mode bit 3 + constant CTRL_MODE_4 : natural := CTRL_ALU_FS_3; -- mode bit 4 + + -- SREG BIT LOCATIONS --------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + constant SREG_MODE_0 : natural := 0; -- mode bit 0 + constant SREG_MODE_1 : natural := 1; -- mode bit 1 + constant SREG_MODE_2 : natural := 2; -- mode bit 2 + constant SREG_MODE_3 : natural := 3; -- mode bit 3 + constant SREG_MODE_4 : natural := 4; -- mode bit 4 + constant SREG_THUMB : natural := 5; -- execute thumb instructions + constant SREG_FIQ_DIS : natural := 6; -- disable FIQ + constant SREG_IRQ_DIS : natural := 7; -- disable IRQ + + constant SREG_O_FLAG : natural := 28; -- overflow flag + constant SREG_C_FLAG : natural := 29; -- carry flag + constant SREG_Z_FLAG : natural := 30; -- zero flag + constant SREG_N_FLAG : natural := 31; -- negative flag + + -- INTERRUPT VECTORS ---------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + constant RES_INT_VEC : STD_LOGIC_VECTOR(4 downto 0) := "00000"; -- hardware reset + constant UND_INT_VEC : STD_LOGIC_VECTOR(4 downto 0) := "00100"; -- going to Undefined32_MODE + constant SWI_INT_VEC : STD_LOGIC_VECTOR(4 downto 0) := "01000"; -- going to Supervisor32_MODE + constant PRF_INT_VEC : STD_LOGIC_VECTOR(4 downto 0) := "01100"; -- going to Abort32_MODE + constant DAT_INT_VEC : STD_LOGIC_VECTOR(4 downto 0) := "10000"; -- going to Abort32_MODE + constant IRQ_INT_VEC : STD_LOGIC_VECTOR(4 downto 0) := "11000"; -- going to IRQ32_MODE + constant FIQ_INT_VEC : STD_LOGIC_VECTOR(4 downto 0) := "11100"; -- going to FIQ32_MODE + + -- PROCESSOR MODE CONSTANTS --------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + constant User32_MODE : STD_LOGIC_VECTOR(4 downto 0) := "10000"; + constant FIQ32_MODE : STD_LOGIC_VECTOR(4 downto 0) := "10001"; + constant IRQ32_MODE : STD_LOGIC_VECTOR(4 downto 0) := "10010"; + constant Supervisor32_MODE : STD_LOGIC_VECTOR(4 downto 0) := "10011"; + constant Abort32_MODE : STD_LOGIC_VECTOR(4 downto 0) := "10111"; + constant Undefined32_MODE : STD_LOGIC_VECTOR(4 downto 0) := "11011"; + + -- CONDITION OPCODES ---------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + constant COND_EQ : STD_LOGIC_VECTOR(3 downto 0) := "0000"; + constant COND_NE : STD_LOGIC_VECTOR(3 downto 0) := "0001"; + constant COND_CS : STD_LOGIC_VECTOR(3 downto 0) := "0010"; + constant COND_CC : STD_LOGIC_VECTOR(3 downto 0) := "0011"; + constant COND_MI : STD_LOGIC_VECTOR(3 downto 0) := "0100"; + constant COND_PL : STD_LOGIC_VECTOR(3 downto 0) := "0101"; + constant COND_VS : STD_LOGIC_VECTOR(3 downto 0) := "0110"; + constant COND_VC : STD_LOGIC_VECTOR(3 downto 0) := "0111"; + constant COND_HI : STD_LOGIC_VECTOR(3 downto 0) := "1000"; + constant COND_LS : STD_LOGIC_VECTOR(3 downto 0) := "1001"; + constant COND_GE : STD_LOGIC_VECTOR(3 downto 0) := "1010"; + constant COND_LT : STD_LOGIC_VECTOR(3 downto 0) := "1011"; + constant COND_GT : STD_LOGIC_VECTOR(3 downto 0) := "1100"; + constant COND_LE : STD_LOGIC_VECTOR(3 downto 0) := "1101"; + constant COND_AL : STD_LOGIC_VECTOR(3 downto 0) := "1110"; + constant COND_NV : STD_LOGIC_VECTOR(3 downto 0) := "1111"; + + -- COOL WORKING MUSIC --------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + -- Carrie Underwood - Last Name + -- Sugarland - Something More + -- Taylor Swift - Today Was A Fairy Tale + -- Montgomery Gentry - One In Every Crowd + -- Tim McGraw - Something Like That + -- Trace Adkins - You're Gonna Miss This + -- Rascal Flatts - These Days + -- Coldwater Jane - Bring On The Love + -- Reba McEntire - The Night The Lights Went Out In Georgia + -- Laura Bell Bundy - Giddy Up On + -- Jerrod Niemann - Lover, Lover + -- Craig Morgan - Redneck Yacht Club + -- Travis Tritt - I'm Gonna Be Somebody + -- Nickelback - Never Gonna Be Alone + -- Montgomery Gentry - Oughta Be More Songs About + -- Jason Aldean - She's Country + -- Crystal Shawanda - You Can Let Go + -- Dixie Chicks - Wide Open Spaces + -- Collin Raye - I Can Still Feel You + -- Jason Aldean - Dirt Road Anthem (amazing!!!) + -- Rodney Atkins - Take a Back Road + -- Jason Aldean - She's Country + -- Tracy Lawrence - For the Love + + -- Joe Nichols - The Shape Im In + -- INTERNAL MNEMONICS --------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + constant LOGICAL_OP : STD_LOGIC := '0'; + constant ARITHMETICAL_OP : STD_LOGIC := '1'; + + constant L_AND : STD_LOGIC_VECTOR(3 downto 0) := "0000"; -- logical and + constant L_OR : STD_LOGIC_VECTOR(3 downto 0) := "0001"; -- logical or + constant L_XOR : STD_LOGIC_VECTOR(3 downto 0) := "0010"; -- logical exclusive or + constant L_NOT : STD_LOGIC_VECTOR(3 downto 0) := "0011"; -- logical not (-and) + constant L_BIC : STD_LOGIC_VECTOR(3 downto 0) := "0100"; -- bit clear + constant L_MOV : STD_LOGIC_VECTOR(3 downto 0) := "0101"; -- pass operant B + constant L_TST : STD_LOGIC_VECTOR(3 downto 0) := "0110"; -- compare by logical and + constant L_TEQ : STD_LOGIC_VECTOR(3 downto 0) := "0111"; -- compare by logical xor + + constant A_ADD : STD_LOGIC_VECTOR(3 downto 0) := "1000"; -- add + constant A_ADC : STD_LOGIC_VECTOR(3 downto 0) := "1001"; -- add with carry + constant A_SUB : STD_LOGIC_VECTOR(3 downto 0) := "1010"; -- sub + constant A_SBC : STD_LOGIC_VECTOR(3 downto 0) := "1011"; -- sub with carry + constant A_RSB : STD_LOGIC_VECTOR(3 downto 0) := "1100"; -- reverse sub + constant A_RSC : STD_LOGIC_VECTOR(3 downto 0) := "1101"; -- reverse sub with carry + constant A_CMP : STD_LOGIC_VECTOR(3 downto 0) := "1110"; -- compare by subtraction + constant A_CMN : STD_LOGIC_VECTOR(3 downto 0) := "1111"; -- compare by addition + + constant PassA : STD_LOGIC_VECTOR(3 downto 0) := L_TEQ; -- pass operant A + constant PassB : STD_LOGIC_VECTOR(3 downto 0) := L_MOV; -- pass operant B + + constant S_LSL : STD_LOGIC_VECTOR(1 downto 0) := "00"; -- logical shift left + constant S_LSR : STD_LOGIC_VECTOR(1 downto 0) := "01"; -- logical shift right + constant S_ASR : STD_LOGIC_VECTOR(1 downto 0) := "10"; -- arithmetical shift right + constant S_ROR : STD_LOGIC_VECTOR(1 downto 0) := "11"; -- rotate right + constant S_RRX : STD_LOGIC_VECTOR(1 downto 0) := "11"; -- rotate right extended + + -- COMPONENT Machine Control System ------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + component MCR_SYS + port ( + CLK : in STD_LOGIC; + G_HALT : in STD_LOGIC; + RES : in STD_LOGIC; + CTRL : in STD_LOGIC_VECTOR(31 downto 0); + HALT_IN : in STD_LOGIC; + INT_TKN_OUT : out STD_LOGIC; + FLAG_IN : in STD_LOGIC_VECTOR(03 downto 0); + CMSR_OUT : out STD_LOGIC_VECTOR(31 downto 0); + REG_PC_OUT : out STD_LOGIC_VECTOR(31 downto 0); + JMP_PC_OUT : out STD_LOGIC_VECTOR(31 downto 0); + LNK_PC_OUT : out STD_LOGIC_VECTOR(31 downto 0); + INF_PC_OUT : out STD_LOGIC_VECTOR(31 downto 0); + EXC_PC_OUT : out STD_LOGIC_VECTOR(31 downto 0); + MCR_DATA_IN : in STD_LOGIC_VECTOR(31 downto 0); + MCR_DATA_OUT : out STD_LOGIC_VECTOR(31 downto 0); + EX_FIQ_IN : in STD_LOGIC; + EX_IRQ_IN : in STD_LOGIC; + EX_ABT_IN : in STD_LOGIC; + EX_PRF_IN : in STD_LOGIC + ); + end component; + + -- COMPONENT Operant Unit ----------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + component OPERAND_UNIT + port ( + CTRL_IN : in STD_LOGIC_VECTOR(31 downto 0); + OP_ADR_IN : in STD_LOGIC_VECTOR(14 downto 0); + OP_A_IN : in STD_LOGIC_VECTOR(31 downto 0); + OP_B_IN : in STD_LOGIC_VECTOR(31 downto 0); + OP_C_IN : in STD_LOGIC_VECTOR(31 downto 0); + SHIFT_VAL_IN : in STD_LOGIC_VECTOR(04 downto 0); + REG_PC_IN : in STD_LOGIC_VECTOR(31 downto 0); + JMP_PC_IN : in STD_LOGIC_VECTOR(31 downto 0); + LNK_PC_IN : in STD_LOGIC_VECTOR(31 downto 0); + IMM_IN : in STD_LOGIC_VECTOR(31 downto 0); + OP_A_OUT : out STD_LOGIC_VECTOR(31 downto 0); + OP_B_OUT : out STD_LOGIC_VECTOR(31 downto 0); + SHIFT_VAL_OUT : out STD_LOGIC_VECTOR(04 downto 0); + BP1_OUT : out STD_LOGIC_VECTOR(31 downto 0); + HOLD_BUS_OUT : out STD_LOGIC_VECTOR(02 downto 0); + MSU_FW_IN : in STD_LOGIC_VECTOR(40 downto 0); + ALU_FW_IN : in STD_LOGIC_VECTOR(41 downto 0); + MEM_FW_IN : in STD_LOGIC_VECTOR(40 downto 0); + WB_FW_IN : in STD_LOGIC_VECTOR(40 downto 0) + ); + end component; + + -- COMPONENT Register File ---------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + component REG_FILE + port ( + CLK : in STD_LOGIC; + G_HALT : in STD_LOGIC; + RES : in STD_LOGIC; + CTRL_IN : in STD_LOGIC_VECTOR(31 downto 0); + OP_ADR_IN : in STD_LOGIC_VECTOR(14 downto 0); + MODE_IN : in STD_LOGIC_VECTOR(04 downto 0); + WB_DATA_IN : in STD_LOGIC_VECTOR(31 downto 0); + REG_PC_IN : in STD_LOGIC_VECTOR(31 downto 0); + OP_A_OUT : out STD_LOGIC_VECTOR(31 downto 0); + OP_B_OUT : out STD_LOGIC_VECTOR(31 downto 0); + OP_C_OUT : out STD_LOGIC_VECTOR(31 downto 0) + ); + end component; + + -- COMPONENT Memory Interface ------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + component LOAD_STORE_UNIT + port ( + CLK : in STD_LOGIC; + G_HALT : in STD_LOGIC; + RES : in STD_LOGIC; + CTRL_IN : in STD_LOGIC_VECTOR(31 downto 0); + MEM_DATA_IN : in STD_LOGIC_VECTOR(31 downto 0); + MEM_ADR_IN : in STD_LOGIC_VECTOR(31 downto 0); + MEM_BP_IN : in STD_LOGIC_VECTOR(31 downto 0); + MODE_IN : in STD_LOGIC_VECTOR(04 downto 0); + ADR_OUT : out STD_LOGIC_VECTOR(31 downto 0); + BP_OUT : out STD_LOGIC_VECTOR(31 downto 0); + LDST_FW_OUT : out STD_LOGIC_VECTOR(40 downto 0); + XMEM_MODE : out STD_LOGIC_VECTOR(04 downto 0); + XMEM_ADR : out STD_LOGIC_VECTOR(31 downto 0); + XMEM_WR_DTA : out STD_LOGIC_VECTOR(31 downto 0); + XMEM_ACC_REQ : out STD_LOGIC; + XMEM_RW : out STD_LOGIC; + XMEM_DQ : out STD_LOGIC_VECTOR(01 downto 0) + ); + end component; + + -- COMPONENT Opcode Decoder --------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + component X1_OPCODE_DECODER + port ( + OPCODE_DATA_IN : in STD_LOGIC_VECTOR(31 downto 0); + OPCODE_CTRL_IN : in STD_LOGIC_VECTOR(15 downto 0); + OPCODE_CTRL_OUT : out STD_LOGIC_VECTOR(99 downto 0) + ); + end component; + + -- COMPONENT Operation Control System ----------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + component FLOW_CTRL + port ( + RES : in STD_LOGIC; + CLK : in STD_LOGIC; + G_HALT : in STD_LOGIC; + INSTR_IN : in STD_LOGIC_VECTOR(31 downto 0); + INST_MREQ_OUT : out STD_LOGIC; + OPCODE_DATA_OUT : out STD_LOGIC_VECTOR(31 downto 0); + OPCODE_CTRL_IN : in STD_LOGIC_VECTOR(99 downto 0); + OPCODE_CTRL_OUT : out STD_LOGIC_VECTOR(15 downto 0); + PC_HALT_OUT : out STD_LOGIC; + SREG_IN : in STD_LOGIC_VECTOR(31 downto 0); + EXECUTE_INT_IN : in STD_LOGIC; + HOLD_BUS_IN : in STD_LOGIC_VECTOR(02 downto 0); + OP_ADR_OUT : out STD_LOGIC_VECTOR(14 downto 0); + IMM_OUT : out STD_LOGIC_VECTOR(31 downto 0); + SHIFT_M_OUT : out STD_LOGIC_VECTOR(01 downto 0); + SHIFT_C_OUT : out STD_LOGIC_VECTOR(04 downto 0); + OF_CTRL_OUT : out STD_LOGIC_VECTOR(31 downto 0); + MS_CTRL_OUT : out STD_LOGIC_VECTOR(31 downto 0); + EX1_CTRL_OUT : out STD_LOGIC_VECTOR(31 downto 0); + MEM_CTRL_OUT : out STD_LOGIC_VECTOR(31 downto 0); + WB_CTRL_OUT : out STD_LOGIC_VECTOR(31 downto 0) + ); + end component; + + -- COMPONENT Multiplication/Shift Unit ---------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + component MS_UNIT + port ( + CLK : in STD_LOGIC; + G_HALT : in STD_LOGIC; + RES : in STD_LOGIC; + CTRL : in STD_LOGIC_VECTOR(31 downto 0); + OP_A_IN : in STD_LOGIC_VECTOR(31 downto 0); + OP_B_IN : in STD_LOGIC_VECTOR(31 downto 0); + BP_IN : in STD_LOGIC_VECTOR(31 downto 0); + CARRY_IN : in STD_LOGIC; + SHIFT_V_IN : in STD_LOGIC_VECTOR(04 downto 0); + SHIFT_M_IN : in STD_LOGIC_VECTOR(01 downto 0); + OP_A_OUT : out STD_LOGIC_VECTOR(31 downto 0); + BP_OUT : out STD_LOGIC_VECTOR(31 downto 0); + RESULT_OUT : out STD_LOGIC_VECTOR(31 downto 0); + CARRY_OUT : out STD_LOGIC; + OVFL_OUT : out STD_LOGIC; + MSU_FW_OUT : out STD_LOGIC_VECTOR(40 downto 0) + ); + end component; + + + -- COMPONENT MS_UNIT/Multiplication Unit -------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + component MULTIPLY_UNIT + port ( + OP_B : in STD_LOGIC_VECTOR(31 downto 0); + OP_C : in STD_LOGIC_VECTOR(31 downto 0); + RESULT : out STD_LOGIC_VECTOR(31 downto 0); + CARRY_OUT : out STD_LOGIC; + OVFL_OUT : out STD_LOGIC + ); + end component; + + -- COMPONENT MS_UNIT/Barrel Shifter Unit -------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + component BARREL_SHIFTER + port ( + SHIFT_DATA_IN : in STD_LOGIC_VECTOR(31 downto 0); + SHIFT_DATA_OUT : out STD_LOGIC_VECTOR(31 downto 0); + CARRY_IN : in STD_LOGIC; + CARRY_OUT : out STD_LOGIC; + OVERFLOW_OUT : out STD_LOGIC; + SHIFT_MODE : in STD_LOGIC_VECTOR(01 downto 0); + SHIFT_POS : in STD_LOGIC_VECTOR(04 downto 0) + ); + end component; + + -- COMPONENT Data Operation Unit ---------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + component ALU + port ( + CLK : in STD_LOGIC; + G_HALT : in STD_LOGIC; + RES : in STD_LOGIC; + CTRL : in STD_LOGIC_VECTOR(31 downto 0); + OP_A_IN : in STD_LOGIC_VECTOR(31 downto 0); + OP_B_IN : in STD_LOGIC_VECTOR(31 downto 0); + BP1_IN : in STD_LOGIC_VECTOR(31 downto 0); + BP1_OUT : out STD_LOGIC_VECTOR(31 downto 0); + ADR_OUT : out STD_LOGIC_VECTOR(31 downto 0); + RESULT_OUT : out STD_LOGIC_VECTOR(31 downto 0); + FLAG_IN : in STD_LOGIC_VECTOR(03 downto 0); + FLAG_OUT : out STD_LOGIC_VECTOR(03 downto 0); + EXC_PC_IN : in STD_LOGIC_VECTOR(31 downto 0); + INT_CALL_IN : in STD_LOGIC; + MS_CARRY_IN : in STD_LOGIC; + MS_OVFL_IN : in STD_LOGIC; + MCR_DTA_OUT : out STD_LOGIC_VECTOR(31 downto 0); + MCR_DTA_IN : in STD_LOGIC_VECTOR(31 downto 0); + ALU_FW_OUT : out STD_LOGIC_VECTOR(41 downto 0) + ); + end component; + + -- COMPONENT ALU/Arithmetical Unit -------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + component ARITHMETICAL_UNIT + port ( + OP_A : in STD_LOGIC_VECTOR(31 downto 0); + OP_B : in STD_LOGIC_VECTOR(31 downto 0); + RESULT : out STD_LOGIC_VECTOR(31 downto 0); + BS_OVF_IN : in STD_LOGIC; + A_CARRY_IN : in STD_LOGIC; + FLAG_OUT : out STD_LOGIC_VECTOR(03 downto 0); + CTRL : in STD_LOGIC_VECTOR(02 downto 0) + ); + end component; + + -- COMPONENT ALU/Logical Unit ------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + component LOGICAL_UNIT + port ( + OP_A : in STD_LOGIC_VECTOR(31 downto 0); + OP_B : in STD_LOGIC_VECTOR(31 downto 0); + RESULT : out STD_LOGIC_VECTOR(31 downto 0); + BS_CRY_IN : in STD_LOGIC; + BS_OVF_IN : in STD_LOGIC; + L_CARRY_IN : in STD_LOGIC; + FLAG_OUT : out STD_LOGIC_VECTOR(03 downto 0); + CTRL : in STD_LOGIC_VECTOR(02 downto 0) + ); + end component; + + -- Write Back Unit ------------------------------------------------------------------------ + -- ------------------------------------------------------------------------------------------- + component WB_UNIT + port ( + CLK : in STD_LOGIC; + G_HALT : in STD_LOGIC; + RES : in STD_LOGIC; + CTRL_IN : in STD_LOGIC_VECTOR(31 downto 0); + ALU_DATA_IN : in STD_LOGIC_VECTOR(31 downto 0); + ADR_BUFF_IN : in STD_LOGIC_VECTOR(31 downto 0); + WB_DATA_OUT : out STD_LOGIC_VECTOR(31 downto 0); + XMEM_RD_DATA : in STD_LOGIC_VECTOR(31 downto 0); + WB_FW_OUT : out STD_LOGIC_VECTOR(40 downto 0) + ); + end component; + +end STORM_core_package; \ No newline at end of file Index: storm_core/trunk/rtl/MS_UNIT.vhd =================================================================== --- storm_core/trunk/rtl/MS_UNIT.vhd (nonexistent) +++ storm_core/trunk/rtl/MS_UNIT.vhd (revision 10) @@ -0,0 +1,163 @@ +-- ####################################################### +-- # < STORM CORE PROCESSOR by Stephan Nolting > # +-- # *************************************************** # +-- # Multiply/Shift Unit # +-- # *************************************************** # +-- # Version 1.0.0, 21.03.2011 # +-- ####################################################### + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +library work; +use work.STORM_core_package.all; + +entity MS_UNIT is + port ( +-- ############################################################################################### +-- ## Global Control ## +-- ############################################################################################### + + CLK : in STD_LOGIC; -- global clock line + G_HALT : in STD_LOGIC; -- global halt line + RES : in STD_LOGIC; -- global reset line + CTRL : in STD_LOGIC_VECTOR(31 downto 0); -- stage control lines + +-- ############################################################################################### +-- ## Operant Connection ## +-- ############################################################################################### + + OP_A_IN : in STD_LOGIC_VECTOR(31 downto 0); -- operant a input + OP_B_IN : in STD_LOGIC_VECTOR(31 downto 0); -- operant b input + BP_IN : in STD_LOGIC_VECTOR(31 downto 0); -- bypass input + CARRY_IN : in STD_LOGIC; -- carry input + + SHIFT_V_IN : in STD_LOGIC_VECTOR(04 downto 0); -- shift value in + SHIFT_M_IN : in STD_LOGIC_VECTOR(01 downto 0); -- shift mode in + + OP_A_OUT : out STD_LOGIC_VECTOR(31 downto 0); -- operant a bypass + BP_OUT : out STD_LOGIC_VECTOR(31 downto 0); -- bypass output + RESULT_OUT : out STD_LOGIC_VECTOR(31 downto 0); -- operation result + CARRY_OUT : out STD_LOGIC; -- operation carry signal + OVFL_OUT : out STD_LOGIC; -- operation overflow signal + +-- ############################################################################################### +-- ## Forwarding Path ## +-- ############################################################################################### + + MSU_FW_OUT : out STD_LOGIC_VECTOR(40 downto 0) -- forwarding path + + ); +end MS_UNIT; + +architecture Structural of MS_UNIT is + + -- Pipeline Registers -- + signal OP_A_REG : STD_LOGIC_VECTOR(31 downto 0); + signal OP_B_REG : STD_LOGIC_VECTOR(31 downto 0); + signal BP_REG : STD_LOGIC_VECTOR(31 downto 0); + signal SHIFT_V_TEMP : STD_LOGIC_VECTOR(04 downto 0); + signal SHIFT_M_TEMP : STD_LOGIC_VECTOR(01 downto 0); + + -- Local Signals -- + signal OP_RESULT : STD_LOGIC_VECTOR(31 downto 0); + signal SFT_DATA : STD_LOGIC_VECTOR(31 downto 0); + signal MUL_DATA : STD_LOGIC_VECTOR(31 downto 0); + signal SFT_CARRY : STD_LOGIC; + signal MUL_CARRY : STD_LOGIC; + signal SFT_OVFL : STD_LOGIC; + signal MUL_OVFL : STD_LOGIC; + +begin + + -- Pipeline-Buffers ------------------------------------------------------------------------------------ + -- -------------------------------------------------------------------------------------------------------- + MS_BUFFER: process(CLK, RES) + begin + if rising_edge (CLK) then + if (RES = '1') then + OP_A_REG <= (others => '0'); + OP_B_REG <= (others => '0'); + BP_REG <= (others => '0'); + SHIFT_V_TEMP <= (others => '0'); + SHIFT_M_TEMP <= (others => '0'); + elsif (G_HALT = '0') then + OP_A_REG <= OP_A_IN; + OP_B_REG <= OP_B_IN; + BP_REG <= BP_IN; + SHIFT_V_TEMP <= SHIFT_V_IN; + SHIFT_M_TEMP <= SHIFT_M_IN; + end if; + end if; + end process MS_BUFFER; + + + + -- Multiplicator --------------------------------------------------------------------------------------- + -- -------------------------------------------------------------------------------------------------------- + Multiplicator: + MULTIPLY_UNIT + port map ( + OP_B => OP_B_REG, -- operand B input + OP_C => BP_REG, -- operand C input + RESULT => MUL_DATA, -- multiplication data result + CARRY_OUT => MUL_CARRY, -- multiplication carry result + OVFL_OUT => MUL_OVFL -- multiplication overflow result + ); + + + -- Barrelshifter --------------------------------------------------------------------------------------- + -- -------------------------------------------------------------------------------------------------------- + Barrelshifter: + BARREL_SHIFTER + port map ( + SHIFT_DATA_IN => OP_B_REG, -- data getting shifted + SHIFT_DATA_OUT => SFT_DATA, -- shift data result + CARRY_IN => CARRY_IN, -- carry input + CARRY_OUT => SFT_CARRY, -- carry output + OVERFLOW_OUT => SFT_OVFL, -- overflow output + SHIFT_MODE => SHIFT_M_TEMP, -- shift mode + SHIFT_POS => SHIFT_V_TEMP -- shift positions + ); + + + -- Operation Result Selector --------------------------------------------------------------------------- + -- -------------------------------------------------------------------------------------------------------- + OP_RESULT <= MUL_DATA when (CTRL(CTRL_MS) = '1') else SFT_DATA; -- result data + CARRY_OUT <= MUL_CARRY when (CTRL(CTRL_MS) = '1') else SFT_CARRY; -- carry flag + OVFL_OUT <= MUL_OVFL when (CTRL(CTRL_MS) = '1') else SFT_OVFL; -- overflow flag + + + + -- Module Data Output ---------------------------------------------------------------------------------- + -- -------------------------------------------------------------------------------------------------------- + RESULT_OUT <= OP_RESULT; -- Operation Data Result + OP_A_OUT <= OP_A_REG; -- Operant A Output + BP_OUT <= BP_REG; -- Bypass Output + + + + -- Forwarding Path ----------------------------------------------------------------------------------- + -- -------------------------------------------------------------------------------------------------------- + -- Operation Data Result -- + MSU_FW_OUT(FWD_DATA_MSB downto FWD_DATA_LSB) <= OP_RESULT; + + -- Destination Register Address -- + MSU_FW_OUT(FWD_RD_MSB downto FWD_RD_LSB) <= CTRL(CTRL_RD_3 downto CTRL_RD_0); + + -- Data Write Back Enabled -- + MSU_FW_OUT(FWD_WB) <= CTRL(CTRL_EN) and CTRL(CTRL_WB_EN); + + -- Carry-Need For Rotate Right Extended Shift -- + MSU_FW_OUT(FWD_CY_NEED) <= '1' when ((CTRL(CTRL_EN) = '1') and (SHIFT_M_TEMP = S_RRX) and (SHIFT_V_TEMP = "00000")) else '0'; + + -- MCR Access -- + MSU_FW_OUT(FWD_MCR_ACC) <= CTRL(CTRL_EN) and CTRL(CTRL_MREG_ACC); + + -- Memory Read Access -- + MSU_FW_OUT(FWD_MEM_R_ACC) <= CTRL(CTRL_EN) and CTRL(CTRL_MEM_ACC) and (not CTRL(CTRL_MEM_RW)); + + + +end Structural; \ No newline at end of file Index: storm_core/trunk/rtl/MULTIPLY_UNIT.vhd =================================================================== --- storm_core/trunk/rtl/MULTIPLY_UNIT.vhd (nonexistent) +++ storm_core/trunk/rtl/MULTIPLY_UNIT.vhd (revision 10) @@ -0,0 +1,51 @@ +-- ####################################################### +-- # < STORM CORE PROCESSOR by Stephan Nolting > # +-- # *************************************************** # +-- # Multiplication Unit # +-- # *************************************************** # +-- # Version 1.0.0, 19.03.2011 # +-- ####################################################### + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +library work; +use work.STORM_core_package.all; + +entity MULTIPLY_UNIT is + port ( + -- Function Operands -- + -------------------------------------------------- + OP_B : in STD_LOGIC_VECTOR(31 downto 0); + OP_C : in STD_LOGIC_VECTOR(31 downto 0); + RESULT : out STD_LOGIC_VECTOR(31 downto 0); + + -- Flag Results -- + -------------------------------------------------- + CARRY_OUT : out STD_LOGIC; + OVFL_OUT : out STD_LOGIC + ); +end MULTIPLY_UNIT; + +architecture Behavioral of MULTIPLY_UNIT is + + -- local signals -- + signal TEMP : STD_LOGIC_VECTOR(63 downto 0); + +begin + + -- Multiplication Unit --------------------------------------------------------------------------------- + -- -------------------------------------------------------------------------------------------------------- + TEMP <= std_logic_vector(unsigned(OP_B) * unsigned(OP_C)); + + RESULT <= TEMP(31 downto 0); + + CARRY_OUT <= '0'; + OVFL_OUT <= '0'; + + --CARRY_OUT <= '1' when (TEMP(63 downto 32) = x"00000001") else '0'; + --OVFL_OUT <= '0' when (TEMP(63 downto 33) = (x"0000000" & "000")) else '1'; + + +end Behavioral; \ No newline at end of file Index: storm_core/trunk/rtl/MCR_SYS.vhd =================================================================== --- storm_core/trunk/rtl/MCR_SYS.vhd (nonexistent) +++ storm_core/trunk/rtl/MCR_SYS.vhd (revision 10) @@ -0,0 +1,406 @@ +-- ####################################################### +-- # < STORM CORE PROCESSOR by Stephan Nolting > # +-- # *************************************************** # +-- # Machine Control Register System # +-- # *************************************************** # +-- # Version 3.0, 18.07.2011 # +-- ####################################################### + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +library work; +use work.STORM_core_package.all; + +entity MCR_SYS is + port ( +-- ############################################################################################### +-- ## Global Control ## +-- ############################################################################################### + + CLK : in STD_LOGIC; -- global clock line + G_HALT : in STD_LOGIC; -- global halt line + RES : in STD_LOGIC; -- global reset line, high active + +-- ############################################################################################### +-- ## Global Control ## +-- ############################################################################################### + + CTRL : in STD_LOGIC_VECTOR(31 downto 0); -- ctrl lines + HALT_IN : in STD_LOGIC; -- halt request + INT_TKN_OUT : out STD_LOGIC; -- int taken signal + +-- ############################################################################################### +-- ## Operand Connection ## +-- ############################################################################################### + + FLAG_IN : in STD_LOGIC_VECTOR(03 downto 0); -- ALU flag input + CMSR_OUT : out STD_LOGIC_VECTOR(31 downto 0); -- sreg output + + REG_PC_OUT : out STD_LOGIC_VECTOR(31 downto 0); -- PC value for manual ops + JMP_PC_OUT : out STD_LOGIC_VECTOR(31 downto 0); -- PC value for branches + LNK_PC_OUT : out STD_LOGIC_VECTOR(31 downto 0); -- PC value for linking + INF_PC_OUT : out STD_LOGIC_VECTOR(31 downto 0); -- PC value for instr fetch + EXC_PC_OUT : out STD_LOGIC_VECTOR(31 downto 0); -- PC value for exceptions + + MCR_DATA_IN : in STD_LOGIC_VECTOR(31 downto 0); -- mcr data input + MCR_DATA_OUT : out STD_LOGIC_VECTOR(31 downto 0); -- mcr data output + +-- ############################################################################################### +-- ## External Interrupt Lines ## +-- ############################################################################################### + + EX_FIQ_IN : in STD_LOGIC; -- fast int request + EX_IRQ_IN : in STD_LOGIC; -- normal int request + EX_ABT_IN : in STD_LOGIC; -- data abort int request + EX_PRF_IN : in STD_LOGIC -- instr abort int request + + ); +end MCR_SYS; + +architecture MCR_SYS_STRUCTURE of MCR_SYS is + + -- Internal Machine Control Registers -- + signal MCR_CMSR : STD_LOGIC_VECTOR(31 downto 0); -- Current Machine Status Register + signal MCR_PC : STD_LOGIC_VECTOR(31 downto 0); -- Program Counter + signal SMSR_FIQ : STD_LOGIC_VECTOR(31 downto 0); -- Fast Interrupt Status Reg + signal SMSR_SVC : STD_LOGIC_VECTOR(31 downto 0); -- Supervisor Status Reg + signal SMSR_ABT : STD_LOGIC_VECTOR(31 downto 0); -- Prefetch Abort Status Reg + signal SMSR_IRQ : STD_LOGIC_VECTOR(31 downto 0); -- Normal Interrupt Status Reg + signal SMSR_UND : STD_LOGIC_VECTOR(31 downto 0); -- Undefined Instruction Status Reg + + -- Flag Construction Bus -- + signal FLAG_BUS : STD_LOGIC_VECTOR(31 downto 0); + + -- Context CTRL -- + signal CONT_EXE : STD_LOGIC; + signal NEW_MODE : STD_LOGIC_VECTOR(04 downto 0); + signal INT_VEC : STD_LOGIC_VECTOR(04 downto 0); + + -- External Interrupt Sync FF -- + signal FIQ_SYNC : STD_LOGIC; + signal IRQ_SYNC : STD_LOGIC; + signal D_AB_SYNC : STD_LOGIC; + signal P_AB_SYNC : STD_LOGIC; + +begin + + -- External Interrupt Signal Synchronizer --------------------------------------------------------- + -- --------------------------------------------------------------------------------------------------- + EXT_INT_SYNC: process(CLK) + begin + if rising_edge(CLK) then + if (RES = '1') then + FIQ_SYNC <= '0'; + IRQ_SYNC <= '0'; + D_AB_SYNC <= '0'; + P_AB_SYNC <= '0'; + elsif (G_HALT = '0') then + FIQ_SYNC <= EX_FIQ_IN; + IRQ_SYNC <= EX_IRQ_IN; + D_AB_SYNC <= EX_ABT_IN; + P_AB_SYNC <= EX_PRF_IN; + end if; + end if; + end process EXT_INT_SYNC; + + + + -- Interrupt Handler System ----------------------------------------------------------------------- + -- --------------------------------------------------------------------------------------------------- + INT_HANDLER: process(MCR_CMSR, CTRL, IRQ_SYNC, FIQ_SYNC, D_AB_SYNC, P_AB_SYNC, FLAG_IN) + variable FIQ_TAKEN, IRQ_TAKEN : STD_LOGIC; -- external int handler + variable UND_TAKEN, SWI_TAKEN : STD_LOGIC; -- software int handler + variable PRF_TAKEN, DAT_TAKEN : STD_LOGIC; -- mem abort int handler + begin + -- FIQ Trap taken -- + FIQ_TAKEN := FIQ_SYNC and (not MCR_CMSR(SREG_FIQ_DIS)); + -- IRQ Trap taken -- + IRQ_TAKEN := IRQ_SYNC and (not MCR_CMSR(SREG_IRQ_DIS)); + -- Data Abort Trap taken -- + DAT_TAKEN := D_AB_SYNC; + -- Prefetch Abort Trap taken -- + PRF_TAKEN := P_AB_SYNC; + -- Software Interrupt Trap taken -- + SWI_TAKEN := CTRL(CTRL_EN) and CTRL(CTRL_SWI); + -- Undefined Instruction Trap taken -- + UND_TAKEN := CTRL(CTRL_EN) and CTRL(CTRL_UND); + + -- default values -- + FLAG_BUS <= MCR_CMSR; + FLAG_BUS(SREG_C_FLAG) <= FLAG_IN(0); -- Carry Flag + FLAG_BUS(SREG_Z_FLAG) <= FLAG_IN(1); -- Zero Flag + FLAG_BUS(SREG_N_FLAG) <= FLAG_IN(2); -- Negative Flag + FLAG_BUS(SREG_O_FLAG) <= FLAG_IN(3); -- Overflow Flag + CONT_EXE <= '1'; + FLAG_BUS(SREG_FIQ_DIS) <= MCR_CMSR(SREG_FIQ_DIS); -- keep current interrupt settings + FLAG_BUS(SREG_IRQ_DIS) <= MCR_CMSR(SREG_IRQ_DIS); -- keep current interrupt settings + + -- interrupt hirarchie / priority list -- + if (DAT_TAKEN = '1') then -- data abort + INT_VEC <= DAT_INT_VEC; + FLAG_BUS(SREG_MODE_4 downto SREG_MODE_0) <= Abort32_MODE; + NEW_MODE <= Abort32_MODE; + elsif (FIQ_TAKEN = '1') then -- fast interrupt request + INT_VEC <= FIQ_INT_VEC; + FLAG_BUS(SREG_MODE_4 downto SREG_MODE_0) <= FIQ32_MODE; + NEW_MODE <= FIQ32_MODE; + FLAG_BUS(SREG_FIQ_DIS) <= '1'; -- disable FIQ + elsif (IRQ_TAKEN = '1') then -- interrupt request + INT_VEC <= IRQ_INT_VEC; + FLAG_BUS(SREG_MODE_4 downto SREG_MODE_0) <= IRQ32_MODE; + NEW_MODE <= IRQ32_MODE; + FLAG_BUS(SREG_IRQ_DIS) <= '1'; -- disable IRQ + elsif (PRF_TAKEN = '1') then -- prefetch abort + INT_VEC <= PRF_INT_VEC; + FLAG_BUS(SREG_MODE_4 downto SREG_MODE_0) <= Abort32_MODE; + NEW_MODE <= Abort32_MODE; + elsif (UND_TAKEN = '1') then -- undefined instruction + INT_VEC <= UND_INT_VEC; + FLAG_BUS(SREG_MODE_4 downto SREG_MODE_0) <= Undefined32_MODE; + NEW_MODE <= Undefined32_MODE; + elsif (SWI_TAKEN = '1') then -- software interrupt + INT_VEC <= SWI_INT_VEC; + FLAG_BUS(SREG_MODE_4 downto SREG_MODE_0) <= Supervisor32_MODE; + NEW_MODE <= Supervisor32_MODE; + else -- normal operation + CONT_EXE <= '0'; + INT_VEC <= (others => '0'); + NEW_MODE <= MCR_CMSR(SREG_MODE_4 downto SREG_MODE_0); -- keep current mode + end if; + + end process INT_HANDLER; + + + + -- Machine Control Registers ---------------------------------------------------------------------- + -- --------------------------------------------------------------------------------------------------- + MREG_WRITE_ACCESS: process(CLK, RES, CTRL, MCR_CMSR, MCR_PC, SMSR_FIQ, SMSR_SVC, SMSR_ABT, + SMSR_IRQ, SMSR_UND, CONT_EXE, HALT_IN, NEW_MODE) + variable MWR_SMSR, MWR_CMSR : STD_LOGIC; + variable CURRENT_MODE : STD_LOGIC_VECTOR(4 downto 0); + variable CONT_RET : STD_LOGIC; + variable CMSR_ACC_CASE : STD_LOGIC_VECTOR(2 downto 0); + variable PC_ACC_CASE : STD_LOGIC_VECTOR(3 downto 0); + begin + -- manual SMSR write access -- + MWR_SMSR := CTRL(CTRL_MREG_ACC) and CTRL(CTRL_MREG_M) and CTRL(CTRL_MREG_RW); + + -- manual CMSR write access -- + MWR_CMSR := CTRL(CTRL_MREG_ACC) and (not CTRL(CTRL_MREG_M)) and CTRL(CTRL_MREG_RW); + -- current operating mode -- + CURRENT_MODE := MCR_CMSR(SREG_MODE_4 downto SREG_MODE_0); + + -- return from interrupt -- + CONT_RET := '0'; + if ((CTRL(CTRL_RD_3 downto CTRL_RD_0) = C_PC_ADR) and (CTRL(CTRL_AF) = '1') and + (CURRENT_MODE /= User32_MODE)) then + CONT_RET := '1'; + end if; + + -- synchronous write -- + if rising_edge(CLK) then + if (RES = '1') then + MCR_PC <= (others => '0'); -- start at 0 + MCR_CMSR <= (others => '0'); + MCR_CMSR(SREG_MODE_4 downto SREG_MODE_0) <= Supervisor32_MODE; -- we're the boss after rest + SMSR_FIQ <= x"ACABBAAF"; -- setup value + SMSR_SVC <= x"00000013"; -- setup value + SMSR_ABT <= x"B1B0B3AB"; -- setup value + SMSR_IRQ <= x"B7BEB1DF"; -- setup value + SMSR_UND <= x"B6B1B8FF"; -- setup value + + elsif (G_HALT = '0') then + ---- PROGRAM COUNTERS -------------------------------------------------------------- + +-- PC_ACC_CASE := CONT_EXE & CTRL(CTRL_BRANCH) & HALT_IN & MCR_CMSR(SREG_THUMB); +-- case PC_ACC_CASE is +-- -- load PC with interrupt vector +-- when "1000" | "1001" | "1010" | "1011" | "1100" | "1101" | "1110" | "1111" => +-- MCR_PC <= x"000000" & "000" & INT_VEC; +-- -- load PC with brnach destination +-- when "0100" | "0101" | "0110" | "0111" => +-- MCR_PC <= MCR_DATA_IN; +-- -- normal ARM operation +-- when "0000" => +-- MCR_PC <= Std_Logic_Vector(unsigned(MCR_PC) + 4); +-- -- normal THUMB operation +-- when "0001" => +-- MCR_PC <= Std_Logic_Vector(unsigned(MCR_PC) + 2); +-- -- keep value +-- when others => +-- MCR_PC <= MCR_PC; +-- end case; + + if (CONT_EXE = '1') then -- load PC with interrupt vector + MCR_PC <= x"000000" & "000" & INT_VEC; + elsif (CTRL(CTRL_BRANCH) = '1') then -- taken branch + MCR_PC <= MCR_DATA_IN; + elsif (HALT_IN = '0') then -- no hold request -> normal operation + if (MCR_CMSR(SREG_THUMB) = '1') then + -- THUMB MODE -- + MCR_PC <= Std_Logic_Vector(unsigned(MCR_PC) + 2); + else + -- ARM MODE -- + MCR_PC <= Std_Logic_Vector(unsigned(MCR_PC) + 4); + end if; + end if; + + ---- CURRENT MACHINE STATUS REGISTER ----------------------------------------------- + CMSR_ACC_CASE := CTRL(CTRL_EN) & CONT_RET & MWR_CMSR; + case CMSR_ACC_CASE is + when "110" | "111" => -- context down change + case (CURRENT_MODE) is -- current mode + when FIQ32_MODE => MCR_CMSR <= SMSR_FIQ; + when Supervisor32_MODE => MCR_CMSR <= SMSR_SVC; + when Abort32_MODE => MCR_CMSR <= SMSR_ABT; + when IRQ32_MODE => MCR_CMSR <= SMSR_IRQ; + when Undefined32_MODE => MCR_CMSR <= SMSR_UND; + when others => MCR_CMSR <= MCR_CMSR; + end case; + when "101" => -- manual write + if (CURRENT_MODE = User32_MODE) or (CTRL(CTRL_MREG_FA) = '1') then -- restricted access for user mode + MCR_CMSR <= MCR_DATA_IN(31 downto 28) & MCR_CMSR(27 downto 0); + else + MCR_CMSR <= MCR_DATA_IN(31 downto 0); -- full sreg access + end if; + when "100" => -- automatic access + if (CTRL(CTRL_AF) = '1') then -- alter flags + MCR_CMSR <= FLAG_BUS(31 downto 0); -- update whole sreg + else + MCR_CMSR <= MCR_CMSR(31 downto 28) & FLAG_BUS(27 downto 0); -- update without flags + end if; + when others => -- keep CMSR + MCR_CMSR <= MCR_CMSR; + end case; + +-- if (CTRL(CTRL_EN) and CONT_RET) = '1' then -- context down change +-- case (CURRENT_MODE) is -- current mode +-- when FIQ32_MODE => MCR_CMSR <= SMSR_FIQ; +-- when Supervisor32_MODE => MCR_CMSR <= SMSR_SVC; +-- when Abort32_MODE => MCR_CMSR <= SMSR_ABT; +-- when IRQ32_MODE => MCR_CMSR <= SMSR_IRQ; +-- when Undefined32_MODE => MCR_CMSR <= SMSR_UND; +-- when others => MCR_CMSR <= MCR_CMSR; +-- end case; +-- elsif (CTRL(CTRL_EN) and MWR_CMSR) = '1' then -- manual write +-- if (CURRENT_MODE = User32_MODE) or (CTRL(CTRL_MREG_FA) = '1') then -- restricted access for user mode +-- MCR_CMSR <= MCR_DATA_IN(31 downto 28) & MCR_CMSR(27 downto 0); +-- else +-- MCR_CMSR <= MCR_DATA_IN(31 downto 0); -- full sreg access +-- end if; +-- elsif (CTRL(CTRL_EN) = '1') then -- automatic access +-- if (CTRL(CTRL_AF) = '1') then -- alter flags +-- MCR_CMSR <= FLAG_BUS(31 downto 0); -- update whole sreg +-- else +-- MCR_CMSR <= MCR_CMSR(31 downto 28) & FLAG_BUS(27 downto 0); -- update without flags +-- end if; +-- end if; + + ---- SAVED MACHINE STATUS REGISTER ------------------------------------------------- + if (CONT_EXE = '1') then -- context up change + case (NEW_MODE) is + when FIQ32_MODE => SMSR_FIQ <= MCR_CMSR; + when Supervisor32_MODE => SMSR_SVC <= MCR_CMSR; + when Abort32_MODE => SMSR_ABT <= MCR_CMSR; + when IRQ32_MODE => SMSR_IRQ <= MCR_CMSR; + when Undefined32_MODE => SMSR_UND <= MCR_CMSR; + when others => NULL; + end case; + elsif (CTRL(CTRL_EN) and MWR_SMSR) = '1' then -- manual data write + if (CTRL(CTRL_MREG_FA) = '1') then + -- flag access only -- + case (CURRENT_MODE) is + when FIQ32_MODE => SMSR_FIQ <= MCR_DATA_IN(31 downto 28) & SMSR_FIQ(27 downto 0); + when Supervisor32_MODE => SMSR_SVC <= MCR_DATA_IN(31 downto 28) & SMSR_SVC(27 downto 0); + when Abort32_MODE => SMSR_ABT <= MCR_DATA_IN(31 downto 28) & SMSR_ABT(27 downto 0); + when IRQ32_MODE => SMSR_IRQ <= MCR_DATA_IN(31 downto 28) & SMSR_IRQ(27 downto 0); + when Undefined32_MODE => SMSR_UND <= MCR_DATA_IN(31 downto 28) & SMSR_UND(27 downto 0); + when others => NULL; + end case; + else + -- full SMSR access -- + case (CURRENT_MODE) is + when FIQ32_MODE => SMSR_FIQ <= MCR_DATA_IN; + when Supervisor32_MODE => SMSR_SVC <= MCR_DATA_IN; + when Abort32_MODE => SMSR_ABT <= MCR_DATA_IN; + when IRQ32_MODE => SMSR_IRQ <= MCR_DATA_IN; + when Undefined32_MODE => SMSR_UND <= MCR_DATA_IN; + when others => NULL; + end case; + end if; + end if; + + end if; + end if; + end process MREG_WRITE_ACCESS; + + + + -- MCR Read Access -------------------------------------------------------------------------------- + -- --------------------------------------------------------------------------------------------------- + MREG_READ_ACCESS: process(CTRL, MCR_CMSR, SMSR_FIQ, SMSR_SVC, SMSR_ABT, SMSR_IRQ, SMSR_UND) + variable MRD_SMSR, MRD_CMSR : STD_LOGIC; + begin + -- manual SMSR_mode read access request -- + MRD_SMSR := CTRL(CTRL_MREG_ACC) and CTRL(CTRL_MREG_M) and (not CTRL(CTRL_MREG_RW)); + -- manual CMSR read access request -- + MRD_CMSR := CTRL(CTRL_MREG_ACC) and (not CTRL(CTRL_MREG_M)) and (not CTRL(CTRL_MREG_RW)); + + if (MRD_CMSR and CTRL(CTRL_EN)) = '1' then + MCR_DATA_OUT <= MCR_CMSR; + elsif (MRD_SMSR and CTRL(CTRL_EN)) = '1' then + case (MCR_CMSR(SREG_MODE_4 downto SREG_MODE_0)) is + when FIQ32_MODE => MCR_DATA_OUT <= SMSR_FIQ; + when Supervisor32_MODE => MCR_DATA_OUT <= SMSR_SVC; + when Abort32_MODE => MCR_DATA_OUT <= SMSR_ABT; + when IRQ32_MODE => MCR_DATA_OUT <= SMSR_IRQ; + when Undefined32_MODE => MCR_DATA_OUT <= SMSR_UND; + when others => MCR_DATA_OUT <= (others => '0'); + end case; + else + MCR_DATA_OUT <= (others => '0'); + end if; + end process MREG_READ_ACCESS; + + + + -- MCR PC Output ---------------------------------------------------------------------------------- + -- --------------------------------------------------------------------------------------------------- + PC_DELAY_UNIT: process(CLK, RES, HALT_IN, MCR_PC) + variable PC_A, PC_B, PC_C, PC_D : STD_LOGIC_VECTOR(31 downto 00); + begin + --- PC delay chain --- + if rising_edge(CLK) then + if (RES = '1') then + PC_A := (others => '0'); + PC_B := (others => '0'); + PC_C := (others => '0'); + PC_D := (others => '0'); + elsif (HALT_IN = '0') and (G_HALT = '0') then -- really conditional to halt_in? + PC_D := PC_C; + PC_C := PC_B; + PC_B := PC_A; + PC_A := MCR_PC; + end if; + end if; + + --- PC output --- + INF_PC_OUT <= MCR_PC; -- PC value for instruction fetch + JMP_PC_OUT <= PC_A; -- PC value for branch operations + LNK_PC_OUT <= PC_B; -- PC value for link operations + REG_PC_OUT <= PC_A; -- PC value for manual operations + EXC_PC_OUT <= PC_D; -- PC value for exceptions + + end process PC_DELAY_UNIT; + + + + -- MCR Data Output -------------------------------------------------------------------------------- + -- --------------------------------------------------------------------------------------------------- + CMSR_OUT <= MCR_CMSR; -- current status register + INT_TKN_OUT <= CONT_EXE; -- interrupt was taken + + +end MCR_SYS_STRUCTURE; \ No newline at end of file Index: storm_core/trunk/rtl/ALU.vhd =================================================================== --- storm_core/trunk/rtl/ALU.vhd (nonexistent) +++ storm_core/trunk/rtl/ALU.vhd (revision 10) @@ -0,0 +1,188 @@ +-- ####################################################### +-- # < STORM CORE PROCESSOR by Stephan Nolting > # +-- # *************************************************** # +-- # Arithmetical/Logical/MCR_Access Unit # +-- # *************************************************** # +-- # Version 2.4, 18.03.2011 # +-- ####################################################### + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +library work; +use work.STORM_core_package.all; + +entity ALU is + port ( +-- ############################################################################################### +-- ## Global Control ## +-- ############################################################################################### + + CLK : in STD_LOGIC; -- global clock line + G_HALT : in STD_LOGIC; -- global halt line + RES : in STD_LOGIC; -- global reset line + CTRL : in STD_LOGIC_VECTOR(31 downto 0); -- stage control lines + +-- ############################################################################################### +-- ## Operand Connection ## +-- ############################################################################################### + + OP_A_IN : in STD_LOGIC_VECTOR(31 downto 0); -- operant a input + OP_B_IN : in STD_LOGIC_VECTOR(31 downto 0); -- operant b input + BP1_IN : in STD_LOGIC_VECTOR(31 downto 0); -- bypass input + BP1_OUT : out STD_LOGIC_VECTOR(31 downto 0); -- bypass output + ADR_OUT : out STD_LOGIC_VECTOR(31 downto 0); -- alu address output + RESULT_OUT : out STD_LOGIC_VECTOR(31 downto 0); -- EX result output + + FLAG_IN : in STD_LOGIC_VECTOR(03 downto 0); -- alu flags input + FLAG_OUT : out STD_LOGIC_VECTOR(03 downto 0); -- alu flgas output + + EXC_PC_IN : in STD_LOGIC_VECTOR(31 downto 0); -- program counter input + INT_CALL_IN : in STD_LOGIC; -- this is an interrupt call + + MS_CARRY_IN : in STD_LOGIC; -- multiply/shift carry + MS_OVFL_IN : in STD_LOGIC; -- multiply/shift overflow + + MCR_DTA_OUT : out STD_LOGIC_VECTOR(31 downto 0); -- mcr write data output + MCR_DTA_IN : in STD_LOGIC_VECTOR(31 downto 0); -- mcr read data input + +-- ############################################################################################### +-- ## Forwarding Path ## +-- ############################################################################################### + + ALU_FW_OUT : out STD_LOGIC_VECTOR(41 downto 0) -- forwarding path + + ); +end ALU; + +architecture ALU_STRUCTURE of ALU is + + -- Pipeline Register -- + signal OP_B, OP_A, BP1 : STD_LOGIC_VECTOR(31 downto 0); + signal MS_CARRY_REG, MS_OVFL_REG : STD_LOGIC; + + -- Local Signals -- + signal ALU_OUT : STD_LOGIC_VECTOR(31 downto 0); + signal ARITH_RES, LOGIC_RES : STD_LOGIC_VECTOR(31 downto 0); + signal ARITH_FLAG_OUT : STD_LOGIC_VECTOR(03 downto 0); + signal LOGIC_FLAG_OUT : STD_LOGIC_VECTOR(03 downto 0); + +begin + + -- Pipeline-Buffers ------------------------------------------------------------------------------------ + -- -------------------------------------------------------------------------------------------------------- + ALU_BUFFER: process(CLK, RES) + begin + if rising_edge (CLK) then + if (RES = '1') then + OP_A <= (others => '0'); + OP_B <= (others => '0'); + BP1 <= (others => '0'); + MS_CARRY_REG <= '0'; + MS_OVFL_REG <= '0'; + elsif (G_HALT = '0') then + OP_A <= OP_A_IN; + OP_B <= OP_B_IN; + BP1 <= BP1_IN; + MS_CARRY_REG <= MS_CARRY_IN; + MS_OVFL_REG <= MS_OVFL_IN; + end if; + end if; + end process ALU_BUFFER; + + + + -- Forwarding Paths ------------------------------------------------------------------------------------ + -- -------------------------------------------------------------------------------------------------------- + ALU_FW_OUT(FWD_DATA_MSB downto FWD_DATA_LSB) <= ALU_OUT(31 downto 0); + ALU_FW_OUT(FWD_RD_MSB downto FWD_RD_LSB) <= CTRL(CTRL_RD_3 downto CTRL_RD_0); + + ALU_FW_OUT(FWD_WB) <= CTRL(CTRL_EN) and CTRL(CTRL_WB_EN); --(CTRL(CTRL_EN) and (not CTRL(CTRL_BRANCH)) and CTRL(CTRL_WB_EN)); -- write back enabled + ALU_FW_OUT(FWD_MEM_ACC) <= CTRL(CTRL_EN) and CTRL(CTRL_MEM_ACC); -- memory access + ALU_FW_OUT(FWD_MCR_ACC) <= CTRL(CTRL_EN) and CTRL(CTRL_MREG_ACC); -- mreg access + ALU_FW_OUT(FWD_MEM_R_ACC) <= CTRL(CTRL_EN) and CTRL(CTRL_MEM_ACC) and (not CTRL(CTRL_MEM_RW)); -- memory read access + + + + -- Arithemtical / Logical Units ------------------------------------------------------------------------ + -- -------------------------------------------------------------------------------------------------------- + Arithmetical_Core: + ARITHMETICAL_UNIT + port map ( + OP_A => OP_A, + OP_B => OP_B, + RESULT => ARITH_RES, + BS_OVF_IN => MS_OVFL_REG, + A_CARRY_IN => FLAG_IN(1), + FLAG_OUT => ARITH_FLAG_OUT, + CTRL => CTRL(CTRL_ALU_FS_2 downto CTRL_ALU_FS_0) + ); + + Logical_Core: + LOGICAL_UNIT + port map ( + OP_A => OP_A, + OP_B => OP_B, + RESULT => LOGIC_RES, + BS_CRY_IN => MS_CARRY_REG, + BS_OVF_IN => MS_OVFL_REG, + L_CARRY_IN => FLAG_IN(1), + FLAG_OUT => LOGIC_FLAG_OUT, + CTRL => CTRL(CTRL_ALU_FS_2 downto CTRL_ALU_FS_0) + ); + + + OPERATION_RESULT_MUX: process(CTRL(CTRL_ALU_FS_3), LOGIC_RES, LOGIC_FLAG_OUT, ARITH_RES, ARITH_FLAG_OUT) + begin + if (CTRL(CTRL_ALU_FS_3) = LOGICAL_OP) then + -- LOGICAL OPERATION + ALU_OUT <= LOGIC_RES; + FLAG_OUT <= LOGIC_FLAG_OUT; + else + -- ARITHMETICAL OPERATION + ALU_OUT <= ARITH_RES; + FLAG_OUT <= ARITH_FLAG_OUT; + end if; + end process OPERATION_RESULT_MUX; + + + + -- Stage Data Mux -------------------------------------------------------------------------------------- + -- -------------------------------------------------------------------------------------------------------- + DATA_OUT_MUX: process(CTRL, MCR_DTA_IN, ALU_OUT) + begin + if (CTRL(CTRL_MREG_ACC) = '1') and (CTRL(CTRL_MREG_RW) = '0') then + --- MCR Read Access --- + RESULT_OUT <= MCR_DTA_IN; + else + --- Normal Operation --- + RESULT_OUT <= ALU_OUT; + end if; + + --- MCR Connection --- + MCR_DTA_OUT <= ALU_OUT; + + --- Memory Address --- + ADR_OUT <= ALU_OUT; + + end process DATA_OUT_MUX; + + + + -- Bypass System --------------------------------------------------------------------------------------- + -- -------------------------------------------------------------------------------------------------------- + BP_MANAGER: process (BP1, EXC_PC_IN, INT_CALL_IN) + begin + if (INT_CALL_IN = '1') then + -- Interrupt Call -- + BP1_OUT <= EXC_PC_IN; + else + -- ALU Operation -- + BP1_OUT <= BP1; + end if; + end process BP_MANAGER; + + + +end ALU_STRUCTURE; \ No newline at end of file Index: storm_core/trunk/rtl/STORM_TOP.vhd =================================================================== --- storm_core/trunk/rtl/STORM_TOP.vhd (nonexistent) +++ storm_core/trunk/rtl/STORM_TOP.vhd (revision 10) @@ -0,0 +1,396 @@ +-- ######################################################################################################### +-- # <<< STORM CORE PROCESSOR SYSTEM by Stephan Nolting >>> # +-- # ***************************************************************************************************** # +-- # ~ STORM System Top Entity ~ | # +-- # File Hierarchy | Make sure, that all files listed on the left are added to # +-- # ---------------------------------------+ the project library, of which this file is the top entity. # +-- # System File Hierarchy: | # +-- # - STORM_TOP.vhd (this file) | This files instatiates the CORE itself, an internal working # +-- # + STORM_CORE.vhd (package file) | memory, the Wishbone interface as well as an access arbiter. # +-- # - SYSTEM_BRIDGE.vhd | The constant IO_BORDER gives the size of the internal memory # +-- # - MEMORY.vhd | and the constant LOG2_IO_BORDER is the dual logarithm of # +-- # - WISHBONE_IO.vhd | this border address (see beneath). # +-- # - CORE.vhd | # +-- # - REG_FILE.vhd | CORE_ADR_OUT < IO_BORDER : Access to internal memory # +-- # - OPERANT_UNIT.vhd | CORE_ADR_OUT >= IO_BORDER : Access to IO via Wishbone # +-- # - MS_UNIT.vhd | # +-- # - MULTIPLICATION_UNIT.vhd | =/\= "To boldly go, where no core has gone before..." =/\= # +-- # - BARREL_SHIFTER.vhd | # +-- # - ALU.vhd +------------------------------------------------------------- # +-- # - ARITHMETICAL_UNIT.vhd | # +-- # - LOGICAL_UNIT.vhd | The STORM Core System was created by Stephan Nolting # +-- # - FLOW_CTRL.vhd | Published at whttp://opencores.org/project,storm_core # +-- # - WB_UNIT.vhd | Contact me: # +-- # - MCR_SYS.vhd | -> stnolting@googlemail.com # +-- # - LOAD_STORE_UNIT.vhd | -> stnolting@web.de # +-- # - X1_OPCODE_DECODER.vhd | # +-- # ***************************************************************************************************** # +-- # Version 1.1, 01.09.2011 # +-- ######################################################################################################### + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity STORM_TOP is + port ( +-- ############################################################################################### +-- ## Wishbone Interface ## +-- ############################################################################################### + + CLK_I : in STD_LOGIC; + RST_I : in STD_LOGIC; + + WB_DATA_I : in STD_LOGIC_VECTOR(31 downto 0); + WB_DATA_O : out STD_LOGIC_VECTOR(31 downto 0); + WB_ADR_O : out STD_LOGIC_VECTOR(31 downto 0); + + WB_ACK_I : in STD_LOGIC; + WB_SEL_O : out STD_LOGIC_VECTOR(03 downto 0); + WB_WE_O : out STD_LOGIC; + WB_STB_O : out STD_LOGIC; + WB_CYC_O : out STD_LOGIC; + +-- ############################################################################################### +-- ## Direct STORM Core Interface ## +-- ############################################################################################### + + MODE_O : out STD_LOGIC_VECTOR(04 downto 0); + D_ABT_I : in STD_LOGIC; + I_ABT_I : in STD_LOGIC; + IRQ_I : in STD_LOGIC; + FIQ_I : in STD_LOGIC + + ); +end STORM_TOP; + +architecture Structure of STORM_TOP is + + -- Address border between internal memory and external IO + -- IO_BORDER = Absolute size of internal memory (in IO_BORDER * 32 byte) + -- ************************************************************************** + -- ************************************************************************** + constant IO_BORDER : natural := 512; + constant LOG2_IO_BORDER : natural := 9; -- log2(INT_MEM_END) + -- ************************************************************************** + -- ************************************************************************** + + -- reset sync -- + signal SYNC_RES : STD_LOGIC_VECTOR(1 downto 0) := "11"; + signal RST_INT : STD_LOGIC; + + -- special processor lines -- + signal ST_HALT : STD_LOGIC; + signal ST_MODE : STD_LOGIC_VECTOR(04 downto 00); + + -- D-MEM interface -- + signal ST_D_MEM_REQ : STD_LOGIC; + signal ST_D_MEM_ADR : STD_LOGIC_VECTOR(31 downto 0); + signal ST_D_MEM_RD_DTA : STD_LOGIC_VECTOR(31 downto 0); + signal ST_D_MEM_WR_DTA : STD_LOGIC_VECTOR(31 downto 0); + signal ST_D_MEM_DQ : STD_LOGIC_VECTOR(01 downto 0); + signal ST_D_MEM_RW : STD_LOGIC; + signal ST_D_MEM_ABORT : STD_LOGIC; + + -- I-MEM interface -- + signal ST_I_MEM_REQ : STD_LOGIC; + signal ST_I_MEM_ADR : STD_LOGIC_VECTOR(31 downto 0); + signal ST_I_MEM_RD_DTA : STD_LOGIC_VECTOR(31 downto 0); + signal ST_I_MEM_DQ : STD_LOGIC_VECTOR(01 downto 0); + signal ST_I_MEM_ABORT : STD_LOGIC; + + -- Memory interface -- + signal MEM_RD_DATA : STD_LOGIC_VECTOR(31 downto 0); + signal MEM_WR_DATA : STD_LOGIC_VECTOR(31 downto 0); + signal MEM_ADR : STD_LOGIC_VECTOR(31 downto 0); + signal MEM_SEL : STD_LOGIC_VECTOR(03 downto 0); + signal MEM_CS : STD_LOGIC; + signal MEM_RW : STD_LOGIC; + + -- Abort Signals -- + signal D_ABORT : STD_LOGIC; + signal I_ABORT : STD_LOGIC; + + -- Wishbone interface -- + signal WI_RD_DATA : STD_LOGIC_VECTOR(31 downto 0); + signal WI_WR_DATA : STD_LOGIC_VECTOR(31 downto 0); + signal WI_ADR : STD_LOGIC_VECTOR(31 downto 0); + signal WI_SEL : STD_LOGIC_VECTOR(03 downto 0); + signal WI_CS : STD_LOGIC; + signal WI_RW : STD_LOGIC; + signal WI_DONE : STD_LOGIC; + + -- storm component -- + -- =============== -- + component CORE + Port ( + RES : in STD_LOGIC; -- global reset input (high active) + CLK : in STD_LOGIC; -- global clock input + + HALT : in STD_LOGIC; -- halt processor + MODE : out STD_LOGIC_VECTOR(04 downto 0); -- current processor mode + + D_MEM_REQ : out STD_LOGIC; -- memory access in next cycle + D_MEM_ADR : out STD_LOGIC_VECTOR(31 downto 0); -- data address + D_MEM_RD_DTA : in STD_LOGIC_VECTOR(31 downto 0); -- read data + D_MEM_WR_DTA : out STD_LOGIC_VECTOR(31 downto 0); -- write data + D_MEM_DQ : out STD_LOGIC_VECTOR(01 downto 0); -- data transfer quantity + D_MEM_RW : out STD_LOGIC; -- read/write signal + D_MEM_ABORT : in STD_LOGIC; -- memory abort request + + I_MEM_REQ : out STD_LOGIC; -- memory access in next cycle + I_MEM_ADR : out STD_LOGIC_VECTOR(31 downto 0); -- instruction address + I_MEM_RD_DTA : in STD_LOGIC_VECTOR(31 downto 0); -- read data + I_MEM_DQ : out STD_LOGIC_VECTOR(01 downto 0); -- data transfer quantity + I_MEM_ABORT : in STD_LOGIC; -- memory abort request + + IRQ : in STD_LOGIC; -- interrupt request + FIQ : in STD_LOGIC -- fast interrupt request + ); + end component; + + -- access arbiter component -- + -- ======================== -- + component ACCESS_ARBITER + generic ( + SWITCH_ADR : natural; -- address border resource1/resource2 + RE1_TO_CNT : natural; -- resource 1 time out value + RE2_TO_CNT : natural; -- resource 2 time out value + CL1_INT_EN : boolean; -- allow interrupts for client 1 + CL2_INT_EN : boolean -- allow interrupts for client 2 + ); + port ( + CLK_I : in STD_LOGIC; -- clock signal, rising edge + RST_I : in STD_LOGIC; -- reset signal, sync, active high + HALT_CLIENTS_O : out STD_LOGIC; -- halt both clients + + CL1_ACC_REQ_I : in STD_LOGIC; -- access request + CL1_ADR_I : in STD_LOGIC_VECTOR(31 downto 00); -- address input + CL1_WR_DATA_I : in STD_LOGIC_VECTOR(31 downto 00); -- write data + CL1_RD_DATA_O : out STD_LOGIC_VECTOR(31 downto 00); -- read data + CL1_DQ_I : in STD_LOGIC_VECTOR(01 downto 00); -- data quantity + CL1_RW_I : in STD_LOGIC; -- read/write select + CL1_TAG_I : in STD_LOGIC_VECTOR(04 downto 00); -- tag input, here: mode + CL1_ABORT_O : out STD_LOGIC; -- access abort error + + CL2_ACC_REQ_I : in STD_LOGIC; -- access request + CL2_ADR_I : in STD_LOGIC_VECTOR(31 downto 00); -- address input + CL2_WR_DATA_I : in STD_LOGIC_VECTOR(31 downto 00); -- write data + CL2_RD_DATA_O : out STD_LOGIC_VECTOR(31 downto 00); -- read data + CL2_DQ_I : in STD_LOGIC_VECTOR(01 downto 00); -- data quantity + CL2_RW_I : in STD_LOGIC; -- read/write select + CL2_TAG_I : in STD_LOGIC_VECTOR(04 downto 00); -- tag input, here: mode + CL2_ABORT_O : out STD_LOGIC; -- access abort error + + RE1_ADR_O : out STD_LOGIC_VECTOR(31 downto 00); -- address + RE1_WR_DATA_O : out STD_LOGIC_VECTOR(31 downto 00); -- write data + RE1_RD_DATA_I : in STD_LOGIC_VECTOR(31 downto 00); -- read data + RE1_BYTE_SEL_O : out STD_LOGIC_VECTOR(03 downto 00); -- byte select + RE1_RW_O : out STD_LOGIC; -- read/write + RE1_CS_O : out STD_LOGIC; -- chip select + RE1_DONE_I : in STD_LOGIC; -- transfer done + + RE2_ADR_O : out STD_LOGIC_VECTOR(31 downto 00); -- address + RE2_WR_DATA_O : out STD_LOGIC_VECTOR(31 downto 00); -- write data + RE2_RD_DATA_I : in STD_LOGIC_VECTOR(31 downto 00); -- read data + RE2_BYTE_SEL_O : out STD_LOGIC_VECTOR(03 downto 00); -- byte select + RE2_RW_O : out STD_LOGIC; -- read/write + RE2_CS_O : out STD_LOGIC; -- chip select + RE2_DONE_I : in STD_LOGIC -- transfer done + ); + end component; + + -- internal memory component -- + -- ========================= -- + component MEMORY + generic ( + MEM_SIZE : natural; + LOG2_MEM_SIZE : natural + ); + port ( + CLK : in STD_LOGIC; + RES : in STD_LOGIC; + DATA_IN : in STD_LOGIC_VECTOR(31 downto 0); + DATA_OUT : out STD_LOGIC_VECTOR(31 downto 0); + ADR_IN : in STD_LOGIC_VECTOR(31 downto 0); + SEL_IN : in STD_LOGIC_VECTOR(03 downto 0); + CS : in STD_LOGIC; + RW : in STD_LOGIC + ); + end component; + + -- wishbone interface component -- + -- ============================ -- + component WISHBONE_IO + port ( + CLK_I : in STD_LOGIC; + RST_I : in STD_LOGIC; + AP_ADR_I : in STD_LOGIC_VECTOR(31 downto 00); + AP_WR_DATA_I : in STD_LOGIC_VECTOR(31 downto 00); + AP_RD_DATA_O : out STD_LOGIC_VECTOR(31 downto 00); + AP_BYTE_SEL_I : in STD_LOGIC_VECTOR(03 downto 00); + AP_RW_I : in STD_LOGIC; + AP_CS_I : in STD_LOGIC; + AP_DONE_O : out STD_LOGIC; + WB_DATA_I : in STD_LOGIC_VECTOR(31 downto 0); + WB_DATA_O : out STD_LOGIC_VECTOR(31 downto 0); + WB_ADR_O : out STD_LOGIC_VECTOR(31 downto 0); + WB_ACK_I : in STD_LOGIC; + WB_SEL_O : out STD_LOGIC_VECTOR(03 downto 0); + WB_WE_O : out STD_LOGIC; + WB_STB_O : out STD_LOGIC; + WB_CYC_O : out STD_LOGIC + ); + end component; + +begin + + -- Reset Synchronizer --------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + RESET_SYNC: process(CLK_I, RST_I, SYNC_RES) + begin + if rising_edge(CLK_I) then + RST_INT <= SYNC_RES(0) or SYNC_RES(1) or RST_I; + SYNC_RES(1) <= SYNC_RES(0); + SYNC_RES(0) <= RST_I; + end if; + end process RESET_SYNC; + + + + -- STORM Core Processor ------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + PROCESSOR_CORE: CORE + Port map ( + RES => RST_INT, + CLK => CLK_I, + HALT => ST_HALT, + MODE => ST_MODE, + + D_MEM_REQ => ST_D_MEM_REQ, + D_MEM_ADR => ST_D_MEM_ADR, + D_MEM_RD_DTA => ST_D_MEM_RD_DTA, + D_MEM_WR_DTA => ST_D_MEM_WR_DTA, + D_MEM_DQ => ST_D_MEM_DQ, + D_MEM_RW => ST_D_MEM_RW, + D_MEM_ABORT => ST_D_MEM_ABORT, + + I_MEM_REQ => ST_I_MEM_REQ, + I_MEM_ADR => ST_I_MEM_ADR, + I_MEM_RD_DTA => ST_I_MEM_RD_DTA, + I_MEM_DQ => ST_I_MEM_DQ, + I_MEM_ABORT => ST_I_MEM_ABORT, + + IRQ => IRQ_I, + FIQ => FIQ_I + ); + + --- external interface --- + MODE_O <= ST_MODE; + + + + -- Access Arbiter ------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + PERIPHERAL_UNIT: ACCESS_ARBITER + generic map ( + SWITCH_ADR => IO_BORDER, + RE1_TO_CNT => 200, + RE2_TO_CNT => 200, + CL1_INT_EN => FALSE, + CL2_INT_EN => FALSE + ) + port map ( + CLK_I => CLK_I, + RST_I => RST_INT, + HALT_CLIENTS_O => ST_HALT, + + CL1_ACC_REQ_I => ST_D_MEM_REQ, + CL1_ADR_I => ST_D_MEM_ADR, + CL1_WR_DATA_I => ST_D_MEM_WR_DTA, + CL1_RD_DATA_O => ST_D_MEM_RD_DTA, + CL1_DQ_I => ST_D_MEM_DQ, + CL1_RW_I => ST_D_MEM_RW, + CL1_TAG_I => ST_MODE, + CL1_ABORT_O => D_ABORT, + + CL2_ACC_REQ_I => ST_I_MEM_REQ, + CL2_ADR_I => ST_I_MEM_ADR, + CL2_WR_DATA_I => (others => '0'), + CL2_RD_DATA_O => ST_I_MEM_RD_DTA, + CL2_DQ_I => ST_I_MEM_DQ, + CL2_RW_I => '0', -- read only + CL2_TAG_I => ST_MODE, + CL2_ABORT_O => I_ABORT, + + RE1_ADR_O => MEM_ADR, + RE1_WR_DATA_O => MEM_WR_DATA, + RE1_RD_DATA_I => MEM_RD_DATA, + RE1_BYTE_SEL_O => MEM_SEL, + RE1_RW_O => MEM_RW, + RE1_CS_O => MEM_CS, + RE1_DONE_I => '1', -- mem is allways ready + + RE2_ADR_O => WI_ADR, + RE2_WR_DATA_O => WI_WR_DATA, + RE2_RD_DATA_I => WI_RD_DATA, + RE2_BYTE_SEL_O => WI_SEL, + RE2_RW_O => WI_RW, + RE2_CS_O => WI_CS, + RE2_DONE_I => WI_DONE + ); + + + --- External Abort Interrupts --- + ST_D_MEM_ABORT <= D_ABORT or D_ABT_I; + ST_I_MEM_ABORT <= I_ABORT or I_ABT_I; + + + -- Internal Memory ------------------------------------------------------------------------ + -- ------------------------------------------------------------------------------------------- + WORKING_MEMORY: MEMORY + generic map ( + MEM_SIZE => IO_BORDER, + LOG2_MEM_SIZE => LOG2_IO_BORDER + ) + port map ( + CLK => CLK_I, + RES => RST_INT, + DATA_IN => MEM_WR_DATA, + DATA_OUT => MEM_RD_DATA, + ADR_IN => MEM_ADR, + SEL_IN => MEM_SEL, + CS => MEM_CS, + RW => MEM_RW + ); + + + + -- Wishbone Interface --------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + WISHBONE_INTERFACE: WISHBONE_IO + Port map ( + CLK_I => CLK_I, + RST_I => RST_INT, + + AP_ADR_I => WI_ADR, + AP_WR_DATA_I => WI_WR_DATA, + AP_RD_DATA_O => WI_RD_DATA, + AP_BYTE_SEL_I => WI_SEL, + AP_RW_I => WI_RW, + AP_CS_I => WI_CS, + AP_DONE_O => WI_DONE, + + WB_DATA_I => WB_DATA_I, + WB_DATA_O => WB_DATA_O, + WB_ADR_O => WB_ADR_O, + WB_ACK_I => WB_ACK_I, + WB_SEL_O => WB_SEL_O, + WB_WE_O => WB_WE_O, + WB_STB_O => WB_STB_O, + WB_CYC_O => WB_CYC_O + ); + + + +end Structure; \ No newline at end of file Index: storm_core/trunk/rtl/OPERAND_UNIT.vhd =================================================================== --- storm_core/trunk/rtl/OPERAND_UNIT.vhd (nonexistent) +++ storm_core/trunk/rtl/OPERAND_UNIT.vhd (revision 10) @@ -0,0 +1,297 @@ +-- ####################################################### +-- # < STORM CORE PROCESSOR by Stephan Nolting > # +-- # *************************************************** # +-- # Operand Fetch & Data Dependency Detector # +-- # *************************************************** # +-- # Version 2.4.4, 03.08.2011 # +-- ####################################################### + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +library work; +use work.STORM_core_package.all; + +entity OPERAND_UNIT is + port ( +-- ############################################################################################### +-- ## Global Control ## +-- ############################################################################################### + + CTRL_IN : in STD_LOGIC_VECTOR(31 downto 0); -- control lines + OP_ADR_IN : in STD_LOGIC_VECTOR(14 downto 0); -- operand addresses from decoder + +-- ############################################################################################### +-- ## Operand Connection ## +-- ############################################################################################### + + OP_A_IN : in STD_LOGIC_VECTOR(31 downto 0); -- operand A reg_file output + OP_B_IN : in STD_LOGIC_VECTOR(31 downto 0); -- operant B reg_file output + OP_C_IN : in STD_LOGIC_VECTOR(31 downto 0); -- operant C reg_file output + SHIFT_VAL_IN : in STD_LOGIC_VECTOR(04 downto 0); -- immediate shift value + REG_PC_IN : in STD_LOGIC_VECTOR(31 downto 0); -- PC value for manual access + JMP_PC_IN : in STD_LOGIC_VECTOR(31 downto 0); -- PC value for branches + LNK_PC_IN : in STD_LOGIC_VECTOR(31 downto 0); -- PC value for linking + IMM_IN : in STD_LOGIC_VECTOR(31 downto 0); -- immediate data input + + OP_A_OUT : out STD_LOGIC_VECTOR(31 downto 0); -- new operand A + OP_B_OUT : out STD_LOGIC_VECTOR(31 downto 0); -- new operant B + SHIFT_VAL_OUT : out STD_LOGIC_VECTOR(04 downto 0); -- new shift value + BP1_OUT : out STD_LOGIC_VECTOR(31 downto 0); -- new operant C (BP) + + HOLD_BUS_OUT : out STD_LOGIC_VECTOR(02 downto 0); -- cycle control + +-- ############################################################################################### +-- ## Forwarding Paths ## +-- ############################################################################################### + + MSU_FW_IN : in STD_LOGIC_VECTOR(40 downto 0); -- msu forwarding data & ctrl + ALU_FW_IN : in STD_LOGIC_VECTOR(41 downto 0); -- alu forwarding data & ctrl + MEM_FW_IN : in STD_LOGIC_VECTOR(40 downto 0); -- memory forwarding data & ctrl + WB_FW_IN : in STD_LOGIC_VECTOR(40 downto 0) -- write back forwaring data & ctrl + + ); +end OPERAND_UNIT; + +architecture OPERAND_UNIT_STRUCTURE of OPERAND_UNIT is + + -- Local Signals -- + signal OP_A, OP_B, OP_C : STD_LOGIC_VECTOR(31 downto 0); + + -- Address Match -- + signal MSU_A_MATCH, MSU_B_MATCH, MSU_C_MATCH : STD_LOGIC; + signal ALU_A_MATCH, ALU_B_MATCH, ALU_C_MATCH : STD_LOGIC; + signal MEM_A_MATCH, MEM_B_MATCH, MEM_C_MATCH : STD_LOGIC; + signal WB_A_MATCH, WB_B_MATCH, WB_C_MATCH : STD_LOGIC; + signal MSU_MATCH, ALU_MATCH, MEM_MATCH : STD_LOGIC; + +begin + + -- Address Match Detector -------------------------------------------------------------------------------- + -- ---------------------------------------------------------------------------------------------------------- + ADR_MATCH: process(OP_ADR_IN, MSU_FW_IN, ALU_FW_IN, MEM_FW_IN, WB_FW_IN, CTRL_IN(CTRL_EN)) + begin + + --- Default Values --- + MSU_A_MATCH <= '0'; MSU_B_MATCH <= '0'; MSU_C_MATCH <= '0'; + ALU_A_MATCH <= '0'; ALU_B_MATCH <= '0'; ALU_C_MATCH <= '0'; + MEM_A_MATCH <= '0'; MEM_B_MATCH <= '0'; MEM_C_MATCH <= '0'; + WB_A_MATCH <= '0'; WB_B_MATCH <= '0'; WB_C_MATCH <= '0'; + + --- Multiply/Shift Unit --- + if (OP_ADR_IN(OP_A_ADR_3 downto OP_A_ADR_0) = MSU_FW_IN(FWD_RD_MSB downto FWD_RD_LSB)) and (OP_ADR_IN(OP_A_IS_REG) = '1') then + MSU_A_MATCH <= MSU_FW_IN(FWD_WB) and CTRL_IN(CTRL_EN); + end if; + if (OP_ADR_IN(OP_B_ADR_3 downto OP_B_ADR_0) = MSU_FW_IN(FWD_RD_MSB downto FWD_RD_LSB)) and (OP_ADR_IN(OP_B_IS_REG) = '1') then + MSU_B_MATCH <= MSU_FW_IN(FWD_WB) and CTRL_IN(CTRL_EN); + end if; + if (OP_ADR_IN(OP_C_ADR_3 downto OP_C_ADR_0) = MSU_FW_IN(FWD_RD_MSB downto FWD_RD_LSB)) and (OP_ADR_IN(OP_C_IS_REG) = '1') then + MSU_C_MATCH <= MSU_FW_IN(FWD_WB) and CTRL_IN(CTRL_EN); + end if; + + --- Arithmetical/Logical Unit --- + if (OP_ADR_IN(OP_A_ADR_3 downto OP_A_ADR_0) = ALU_FW_IN(FWD_RD_MSB downto FWD_RD_LSB)) and (OP_ADR_IN(OP_A_IS_REG) = '1') then + ALU_A_MATCH <= ALU_FW_IN(FWD_WB) and CTRL_IN(CTRL_EN); + end if; + if (OP_ADR_IN(OP_B_ADR_3 downto OP_B_ADR_0) = ALU_FW_IN(FWD_RD_MSB downto FWD_RD_LSB)) and (OP_ADR_IN(OP_B_IS_REG) = '1') then + ALU_B_MATCH <= ALU_FW_IN(FWD_WB) and CTRL_IN(CTRL_EN); + end if; + if (OP_ADR_IN(OP_C_ADR_3 downto OP_C_ADR_0) = ALU_FW_IN(FWD_RD_MSB downto FWD_RD_LSB)) and (OP_ADR_IN(OP_C_IS_REG) = '1') then + ALU_C_MATCH <= ALU_FW_IN(FWD_WB) and CTRL_IN(CTRL_EN); + end if; + + --- Memory-Access Unit --- + if (OP_ADR_IN(OP_A_ADR_3 downto OP_A_ADR_0) = MEM_FW_IN(FWD_RD_MSB downto FWD_RD_LSB)) and (OP_ADR_IN(OP_A_IS_REG) = '1') then + MEM_A_MATCH <= MEM_FW_IN(FWD_WB) and CTRL_IN(CTRL_EN); + end if; + if (OP_ADR_IN(OP_B_ADR_3 downto OP_B_ADR_0) = MEM_FW_IN(FWD_RD_MSB downto FWD_RD_LSB)) and (OP_ADR_IN(OP_B_IS_REG) = '1') then + MEM_B_MATCH <= MEM_FW_IN(FWD_WB) and CTRL_IN(CTRL_EN); + end if; + if (OP_ADR_IN(OP_C_ADR_3 downto OP_C_ADR_0) = MEM_FW_IN(FWD_RD_MSB downto FWD_RD_LSB)) and (OP_ADR_IN(OP_C_IS_REG) = '1') then + MEM_C_MATCH <= MEM_FW_IN(FWD_WB) and CTRL_IN(CTRL_EN); + end if; + + --- Write Back --- + if (OP_ADR_IN(OP_A_ADR_3 downto OP_A_ADR_0) = WB_FW_IN(FWD_RD_MSB downto FWD_RD_LSB)) and (OP_ADR_IN(OP_A_IS_REG) = '1') then + WB_A_MATCH <= WB_FW_IN(FWD_WB) and CTRL_IN(CTRL_EN); + end if; + if (OP_ADR_IN(OP_B_ADR_3 downto OP_B_ADR_0) = WB_FW_IN(FWD_RD_MSB downto FWD_RD_LSB)) and (OP_ADR_IN(OP_B_IS_REG) = '1') then + WB_B_MATCH <= WB_FW_IN(FWD_WB) and CTRL_IN(CTRL_EN); + end if; + if (OP_ADR_IN(OP_C_ADR_3 downto OP_C_ADR_0) = WB_FW_IN(FWD_RD_MSB downto FWD_RD_LSB)) and (OP_ADR_IN(OP_C_IS_REG) = '1') then + WB_C_MATCH <= WB_FW_IN(FWD_WB) and CTRL_IN(CTRL_EN); + end if; + + end process ADR_MATCH; + + + + -- Local Data Dependency Detector & Forwarding Unit ------------------------------------------------------ + -- ---------------------------------------------------------------------------------------------------------- + LOCAL_DATA_DEPENDENCE_DETECTOR: process (CTRL_IN, ALU_FW_IN, MEM_FW_IN, ALU_A_MATCH, ALU_B_MATCH, + ALU_C_MATCH, MEM_A_MATCH, MEM_B_MATCH, MEM_C_MATCH, WB_A_MATCH, + WB_B_MATCH, WB_C_MATCH, WB_FW_IN, OP_A_IN, OP_B_IN, OP_C_IN) + variable LDD_A, LDD_B, LDD_C : std_logic_vector(2 downto 0); + begin + -- Forward OP_X from EX/MEM/WB-stage if source and destination addresses are equal + -- and if the the instruction in the corresponding stage will perform a valid data write back. + -- Data from early stages have higher priority than data from later stages. + + --- LOCAL DATA DEPENDENCY FOR OPERANT A --------------------- + ---------------------------------------------------------------- + LDD_A := ALU_A_MATCH & MEM_A_MATCH & WB_A_MATCH; + case LDD_A is + when "100" | "101" | "110" | "111" => + OP_A <= ALU_FW_IN(FWD_DATA_MSB downto FWD_DATA_LSB); + when "010" | "011" => + OP_A <= MEM_FW_IN(FWD_DATA_MSB downto FWD_DATA_LSB); + when "001" => + OP_A <= WB_FW_IN( FWD_DATA_MSB downto FWD_DATA_LSB); + when others => -- "000" + OP_A <= OP_A_IN; + end case; + + --- LOCAL DATA DEPENDENCY FOR OPERANT B --------------------- + ---------------------------------------------------------------- + LDD_B := ALU_B_MATCH & MEM_B_MATCH & WB_B_MATCH; + case LDD_B is + when "100" | "101" | "110" | "111" => + OP_B <= ALU_FW_IN(FWD_DATA_MSB downto FWD_DATA_LSB); + when "010" | "011" => + OP_B <= MEM_FW_IN(FWD_DATA_MSB downto FWD_DATA_LSB); + when "001" => + OP_B <= WB_FW_IN( FWD_DATA_MSB downto FWD_DATA_LSB); + when others => -- "000" + OP_B <= OP_B_IN; + end case; + + --- LOCAL DATA DEPENDENCY FOR OPERANT C --------------------- + ---------------------------------------------------------------- + LDD_C := ALU_C_MATCH & MEM_C_MATCH & WB_C_MATCH; + case LDD_C is + when "100" | "101" | "110" | "111" => + OP_C <= ALU_FW_IN(FWD_DATA_MSB downto FWD_DATA_LSB); + when "010" | "011" => + OP_C <= MEM_FW_IN(FWD_DATA_MSB downto FWD_DATA_LSB); + when "001" => + OP_C <= WB_FW_IN( FWD_DATA_MSB downto FWD_DATA_LSB); + when others => -- "000" + OP_C <= OP_C_IN; + end case; + + end process LOCAL_DATA_DEPENDENCE_DETECTOR; + + + + -- Address Match Detector For ANY Match ------------------------------------------------------------------ + -- ---------------------------------------------------------------------------------------------------------- + MSU_MATCH <= MSU_A_MATCH or MSU_B_MATCH or MSU_C_MATCH; + ALU_MATCH <= ALU_A_MATCH or ALU_B_MATCH or ALU_C_MATCH; + MEM_MATCH <= MEM_A_MATCH or MEM_B_MATCH or MEM_C_MATCH; + + + -- Temporal Data Dependency Detector --------------------------------------------------------------------- + -- ---------------------------------------------------------------------------------------------------------- + TEMPORAL_DDD: process(MSU_MATCH, ALU_MATCH, MSU_FW_IN, ALU_FW_IN, MEM_MATCH) + begin + -- Data conflicts that cannot be solved by forwarding = Temporal Data Dependencies + -- -> Pipeline Stalls & Bubbles needed + -- Early stages have higher priority than later ones! + + -- MSU_MATCH (REG/FLAG) => 1 cycle(s) HALT_IF + -- ALU_MATCH and mem_r => 2 cycle(s) HALT_IF + -- MSU_MATCH and mem_r => 3 cycle(s) HALT_IF + + -- Normal Operation default + HOLD_BUS_OUT(2 downto 1) <= "00"; -- 0 + HOLD_BUS_OUT(0) <= '0'; -- disable + + if (MSU_MATCH = '1') or (MSU_FW_IN(FWD_CY_NEED) = '1') then + -- MS Register match + if (MSU_FW_IN(FWD_MEM_R_ACC) = '1') then + -- Data dependency OF <-> WB (mem read) form MS + HOLD_BUS_OUT(2 downto 1) <= "11"; -- 3 + HOLD_BUS_OUT(0) <= '1'; -- enable + elsif (MSU_FW_IN(FWD_MCR_ACC) = '1') then + -- Data dependency OF <-> MA (MCR access) + HOLD_BUS_OUT(2 downto 1) <= "10"; -- 2 + HOLD_BUS_OUT(0) <= '1'; -- enable + else + -- Data dependency OF <-> EX + HOLD_BUS_OUT(2 downto 1) <= "01"; -- 1 + HOLD_BUS_OUT(0) <= '1'; -- enable + end if; + + elsif (ALU_MATCH = '1') then + -- EX Register Match + if (ALU_FW_IN(FWD_MEM_R_ACC) = '1') then + -- Data dependency OF <-> WB (mem read) from EX + HOLD_BUS_OUT(2 downto 1) <= "10"; -- 2 + HOLD_BUS_OUT(0) <= '1'; -- enable + elsif (ALU_FW_IN(FWD_MCR_ACC) = '1') then + -- Data dependency OF <-> MA (MCR access) + HOLD_BUS_OUT(2 downto 1) <= "01"; -- 1 + HOLD_BUS_OUT(0) <= '1'; -- enable + end if; + + elsif (MEM_MATCH = '1') and (ALU_FW_IN(FWD_MEM_R_ACC) = '1') then + -- MEM Register Match with MEM_R access + HOLD_BUS_OUT(2 downto 1) <= "01"; -- 1 + HOLD_BUS_OUT(0) <= '1'; -- disable + + end if; + + end process TEMPORAL_DDD; + + + + -- Operand Multiplexers --------------------------------------------------------------------------------- + -- --------------------------------------------------------------------------------------------------------- + OPERAND_MUX: process(CTRL_IN, OP_A, OP_B, OP_C, IMM_IN, JMP_PC_IN, LNK_PC_IN, SHIFT_VAL_IN) + begin + + --- OPERANT A --- + ---------------------------------------------------------------- + if (CTRL_IN(CTRL_BRANCH) = '1') then -- BRANCH_INSTR signal + -- delayed program counter -- + OP_A_OUT <= JMP_PC_IN; + else + -- fowarding unit port A output -- + OP_A_OUT <= OP_A; + end if; + + --- OPERANT B --- + ---------------------------------------------------------------- + if (CTRL_IN(CTRL_CONST) = '1') then -- CONST signal + -- immediate -- + OP_B_OUT <= IMM_IN; + else + -- fowarding unit port B output -- + OP_B_OUT <= OP_B; + end if; + + --- SHIFT VALUE -- + ---------------------------------------------------------------- + if (CTRL_IN(CTRL_SHIFTR) = '1') then -- SHIFT_REG + -- fowarding unit port C output -- + SHIFT_VAL_OUT <= OP_C(4 downto 0); + else + -- immediate shift value -- + SHIFT_VAL_OUT <= SHIFT_VAL_IN; + end if; + + --- BYPASS DATA --- + ---------------------------------------------------------------- + if (CTRL_IN(CTRL_LINK) = '1') then -- LINK signal + -- current program counter -- + BP1_OUT <= LNK_PC_IN; + else + -- fowarding unit port C output -- + BP1_OUT <= OP_C; + end if; + end process OPERAND_MUX; + + + +end OPERAND_UNIT_STRUCTURE; \ No newline at end of file Index: storm_core/trunk/rtl/CORE.vhd =================================================================== --- storm_core/trunk/rtl/CORE.vhd (nonexistent) +++ storm_core/trunk/rtl/CORE.vhd (revision 10) @@ -0,0 +1,384 @@ +-- ####################################################################################################### +-- # <<< STORM CORE PROCESSOR by Stephan Nolting >>> # +-- # *************************************************************************************************** # +-- # ~ STORM Core Top Entity ~ | The STORM core is a powerfull 32 bit open source RISC # +-- # File Hierarchy | processor, partly compatible to the ARM architecture. # +-- # ------------------------------------+ This is the top entity of the core itself. Please refer to # +-- # Core File Hierarchy: | the core's data sheet for more information. # +-- # - CORE.vhd (this file) | # +-- # + STORM_CORE.vhd (package file) +---------------------------------------------------------------# +-- # - REG_FILE.vhd | # +-- # - OPERANT_UNIT.vhd | SSSS TTTTT OOO RRRR M M CCCC OOO RRRR EEEEE # +-- # - MS_UNIT.vhd | S T O O R R MM MM C O O R R E # +-- # - MULTIPLICATION_UNIT.vhd | SSS T O O RRRR M M M ### C O O RRRR EEE # +-- # - BARREL_SHIFTER.vhd | S T O O R R M M C O O R R E # +-- # - ALU.vhd | SSSS T OOO R R M M CCCC OOO R R EEEEE # +-- # - ARITHMETICAL_UNIT.vhd | # +-- # - LOGICAL_UNIT.vhd +-------------------------------------------------------------- # +-- # - FLOW_CTRL.vhd | The STORM Core Processor was created by Stephan Nolting # +-- # - WB_UNIT.vhd | Published at whttp://opencores.org/project,storm_core # +-- # - MCR_SYS.vhd | Contact me: # +-- # - LOAD_STORE_UNIT.vhd | -> stnolting@googlemail.com # +-- # - X1_OPCODE_DECODER.vhd | -> stnolting@web.de # +-- # *************************************************************************************************** # +-- # Version 1.4, 02.09.2011 # +-- ####################################################################################################### + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +library work; +use work.STORM_core_package.all; + +entity CORE is + Port ( +-- ############################################################################################### +-- ## Global Control Signals ## +-- ############################################################################################### + + RES : in STD_LOGIC; -- global reset input (high active) + CLK : in STD_LOGIC; -- global clock input + +-- ############################################################################################### +-- ## Status and Control ## +-- ############################################################################################### + + HALT : in STD_LOGIC; -- halt processor + MODE : out STD_LOGIC_VECTOR(04 downto 0); -- current processor mode + +-- ############################################################################################### +-- ## Data Memory Interface ## +-- ############################################################################################### + + D_MEM_REQ : out STD_LOGIC; -- memory access in next cycle + D_MEM_ADR : out STD_LOGIC_VECTOR(31 downto 0); -- data address + D_MEM_RD_DTA : in STD_LOGIC_VECTOR(31 downto 0); -- read data + D_MEM_WR_DTA : out STD_LOGIC_VECTOR(31 downto 0); -- write data + D_MEM_DQ : out STD_LOGIC_VECTOR(01 downto 0); -- data transfer quantity + D_MEM_RW : out STD_LOGIC; -- read/write signal + D_MEM_ABORT : in STD_LOGIC; -- memory abort request + +-- ############################################################################################### +-- ## Instruction Memory Interface ## +-- ############################################################################################### + + I_MEM_REQ : out STD_LOGIC; -- memory access in next cycle + I_MEM_ADR : out STD_LOGIC_VECTOR(31 downto 0); -- instruction address + I_MEM_RD_DTA : in STD_LOGIC_VECTOR(31 downto 0); -- read data + I_MEM_DQ : out STD_LOGIC_VECTOR(01 downto 0); -- data transfer quantity + I_MEM_ABORT : in STD_LOGIC; -- memory abort request + +-- ############################################################################################### +-- ## Interrupt Interface ## +-- ############################################################################################### + + IRQ : in STD_LOGIC; -- interrupt request + FIQ : in STD_LOGIC -- fast interrupt request + ); +end CORE; + +architecture CORE_STRUCTURE of CORE is + + -- ############################################################################################### + -- ## Internal Signals ## + -- ############################################################################################### + + signal ALU_FLAGS : STD_LOGIC_VECTOR(03 downto 0); -- CMSR/SMSR flag bits + signal CMSR : STD_LOGIC_VECTOR(31 downto 0); -- current machine status register + signal MCR_DTA_RD : STD_LOGIC_VECTOR(31 downto 0); -- machine control register read data + signal MCR_DTA_WR : STD_LOGIC_VECTOR(31 downto 0); -- machine control register write data + signal IMMEDIATE : STD_LOGIC_VECTOR(31 downto 0); -- immediate value + signal OP_ADR : STD_LOGIC_VECTOR(14 downto 0); -- operand register adresses and enables + signal MS_CTRL : STD_LOGIC_VECTOR(31 downto 0); -- multishifter control lines + signal BP_MS : STD_LOGIC_VECTOR(31 downto 0); -- multishifter bypass + signal OP_A_MS : STD_LOGIC_VECTOR(31 downto 0); -- operand A for multishifter + signal OP_B_MS : STD_LOGIC_VECTOR(31 downto 0); -- operand B for multishifter + signal MS_CARRY : STD_LOGIC; -- multishifter carry output + signal MS_OVFL : STD_LOGIC; -- multishifter overflow output + signal MS_FW_PATH : STD_LOGIC_VECTOR(40 downto 0); -- multishifter forwarding bus + signal WB_FW_PATH : STD_LOGIC_VECTOR(40 downto 0); -- write back unit forwarding bus + signal gCLK : STD_LOGIC; -- global clock line + signal gRES : STD_LOGIC; -- global reset line + signal G_HALT : STD_LOGIC; -- gloabl halt line + signal INT_EXECUTE : STD_LOGIC; -- execute interrupt + signal HALT_BUS : STD_LOGIC_VECTOR(02 downto 0); -- temporal data dependencie bus + signal OF_CTRL : STD_LOGIC_VECTOR(31 downto 0); -- OF stage control lines + signal OF_OP_A : STD_LOGIC_VECTOR(31 downto 0); -- operant A + signal OF_OP_B : STD_LOGIC_VECTOR(31 downto 0); -- operant B + signal OF_OP_C : STD_LOGIC_VECTOR(31 downto 0); -- operant C + signal PC_HALT : STD_LOGIC; -- halt instruction fetch + signal OF_OP_A_OUT : STD_LOGIC_VECTOR(31 downto 0); -- operand A output + signal OF_OP_B_OUT : STD_LOGIC_VECTOR(31 downto 0); -- operand B output + signal OF_BP1_OUT : STD_LOGIC_VECTOR(31 downto 0); -- bypass 1 output + signal SHIFT_VAL : STD_LOGIC_VECTOR(04 downto 0); -- shift value + signal SHIFT_MOD : STD_LOGIC_VECTOR(01 downto 0); -- shift mode + signal OPC_A : STD_LOGIC_VECTOR(15 downto 0); -- opcode decoder input + signal OPC_B : STD_LOGIC_VECTOR(99 downto 0); -- opcode decoder output + signal OP_DATA : STD_LOGIC_VECTOR(31 downto 0); -- opcode decoder INSTR input + signal EX1_CTRL : STD_LOGIC_VECTOR(31 downto 0); -- EX stage control lines + signal EX_BP1_OUT : STD_LOGIC_VECTOR(31 downto 0); -- bypass 1 register + signal EX_ALU_OUT : STD_LOGIC_VECTOR(31 downto 0); -- alu result output + signal ALU_FW_PATH : STD_LOGIC_VECTOR(41 downto 0); -- alu forwarding path + signal EX_BP_OUT : STD_LOGIC_VECTOR(31 downto 0); + signal EX_ADR_OUT : STD_LOGIC_VECTOR(31 downto 0); + signal EX_RES_OUT : STD_LOGIC_VECTOR(31 downto 0); + signal MEM_CTRL : STD_LOGIC_VECTOR(31 downto 0); -- MEM stage control lines + signal MEM_DATA : STD_LOGIC_VECTOR(31 downto 0); + signal MEM_DTA_OUT : STD_LOGIC_VECTOR(31 downto 0); -- mem_data and bp2 register + signal MEM_ADR_OUT : STD_LOGIC_VECTOR(31 downto 0); -- mem_data address bypass + signal MEM_BP_OUT : STD_LOGIC_VECTOR(31 downto 0); -- mem_data and bp2 register + signal MEM_FW_PATH : STD_LOGIC_VECTOR(40 downto 0); -- memory forwarding path + signal SHIFT_VAL_BUFF : STD_LOGIC_VECTOR(04 downto 0); -- shift value for barrelshifter + signal REG_PC : STD_LOGIC_VECTOR(31 downto 0); -- PC value for manual operations + signal JMP_PC : STD_LOGIC_VECTOR(31 downto 0); -- PC value for branches + signal LNK_PC : STD_LOGIC_VECTOR(31 downto 0); -- PC value for linking + signal INF_PC : STD_LOGIC_VECTOR(31 downto 0); -- PC value instruction fetch + signal EXC_PC : STD_LOGIC_VECTOR(31 downto 0); -- PC value for exceptions + signal WB_CTRL : STD_LOGIC_VECTOR(31 downto 0); -- WB stage control lines + signal WB_DATA_LINE : STD_LOGIC_VECTOR(31 downto 0); -- data write back line + +begin + -- ####################################################################################################### + -- ## GLOBAL CONTROL FOR ALL STAGES ## + -- ####################################################################################################### + + -- Global CLOCK, HALT and RESET Network + -- ------------------------------------------------------------------------------ + gCLK <= CLK; + gRES <= RES; + G_HALT <= HALT; -- maybe try clock gating?! + + + + -- Instruction Decoder + -- ------------------------------------------------------------------------------ + Instruction_Decoder: + X1_OPCODE_DECODER + port map ( + OPCODE_DATA_IN => OP_DATA, -- current instruction word + OPCODE_CTRL_IN => OPC_A, -- control feedback input + OPCODE_CTRL_OUT => OPC_B -- control lines output + ); + + + -- Operation Flow Control System + -- ------------------------------------------------------------------------------ + Operation_Flow_Control: + FLOW_CTRL + port map ( + RES => gRES, -- global active high reset + CLK => gCLK, -- global clock net + G_HALT => G_HALT, -- global halt signal + INSTR_IN => I_MEM_RD_DTA, -- instruction input + INST_MREQ_OUT => I_MEM_REQ, -- instr fetch memory request + OPCODE_DATA_OUT => OP_DATA, -- instruction register output + OPCODE_CTRL_IN => OPC_B, -- control lines input + OPCODE_CTRL_OUT => OPC_A, -- control feedback output + PC_HALT_OUT => PC_HALT, -- halt instruction fetch output + SREG_IN => CMSR, -- current machine status register + EXECUTE_INT_IN => INT_EXECUTE, -- execute interupt request + HOLD_BUS_IN => HALT_BUS, -- number of bubbles + OP_ADR_OUT => OP_ADR, -- operand register addresses + IMM_OUT => IMMEDIATE, -- immediate output + SHIFT_M_OUT => SHIFT_MOD, -- shift mode output + SHIFT_C_OUT => SHIFT_VAL, -- immediate shif value output + OF_CTRL_OUT => OF_CTRL, -- stage control OF + MS_CTRL_OUT => MS_CTRL, -- stage control MS + EX1_CTRL_OUT => EX1_CTRL, -- stage control EX + MEM_CTRL_OUT => MEM_CTRL, -- stage control MA + WB_CTRL_OUT => WB_CTRL -- stage control WB + ); + + + -- Machine Control System + -- ------------------------------------------------------------------------------ + Machine_Control_System: + MCR_SYS + port map ( + CLK => gCLK, -- global clock net + G_HALT => G_HALT, -- global halt signal + RES => gRES, -- global active high reset + CTRL => EX1_CTRL, -- stage control + HALT_IN => PC_HALT, -- halt program counter + INT_TKN_OUT => INT_EXECUTE, -- execute interrupt output + FLAG_IN => ALU_FLAGS, -- alu flags input + CMSR_OUT => CMSR, -- current machine status register + REG_PC_OUT => REG_PC, -- PC value for manual operations + JMP_PC_OUT => JMP_PC, -- PC value for branches + LNK_PC_OUT => LNK_PC, -- PC value for linking + INF_PC_OUT => INF_PC, -- PC value for instruction fetch + EXC_PC_OUT => EXC_PC, -- PC value for exceptions + MCR_DATA_IN => MCR_DTA_WR, -- mcr write data input + MCR_DATA_OUT => MCR_DTA_RD, -- mcr read data output + EX_FIQ_IN => FIQ, -- external fast interrupt request + EX_IRQ_IN => IRQ, -- external interrupt request + EX_ABT_IN => D_MEM_ABORT, -- external D memory abort request + EX_PRF_IN => I_MEM_ABORT -- external I memory abort request + ); + + + -- External Interface + -- ------------------------------------------------------------------------------ + I_MEM_ADR <= INF_PC; + I_MEM_DQ <= DQ_WORD; + + + -- ####################################################################################################### + -- ## PIPELINE STAGE 2: OPERAND FETCH & INSTRUCITON DECODE ## + -- ####################################################################################################### + + -- Data Register File + -- ------------------------------------------------------------------------------ + Register_File: + REG_FILE + port map ( + CLK => gCLK, -- global clock net + G_HALT => G_HALT, -- global halt signal + RES => gRES, -- global active high reset + CTRL_IN => WB_CTRL, -- stage control + OP_ADR_IN => OP_ADR, -- operand addresses + MODE_IN => CMSR(SREG_MODE_4 downto SREG_MODE_0), -- current processor mode + WB_DATA_IN => WB_DATA_LINE, -- write back bus + REG_PC_IN => REG_PC, -- PC for manual operations + OP_A_OUT => OF_OP_A, -- register A output + OP_B_OUT => OF_OP_B, -- register B output + OP_C_OUT => OF_OP_C -- register C output + ); + + -- Operant Fetch Unit + -- ------------------------------------------------------------------------------ + Operand_Fetch_Unit: + OPERAND_UNIT + port map ( + CTRL_IN => OF_CTRL, -- stage flow control + OP_ADR_IN => OP_ADR, -- register operand address + OP_A_IN => OF_OP_A, -- register A input + OP_B_IN => OF_OP_B, -- register B input + OP_C_IN => OF_OP_C, -- register C input + SHIFT_VAL_IN => SHIFT_VAL, -- immediate shift value in + REG_PC_IN => REG_PC, -- PC value for manual operations + JMP_PC_IN => JMP_PC, -- PC value for branches + LNK_PC_IN => LNK_PC, -- PC value for linking + IMM_IN => IMMEDIATE, -- immediate value + OP_A_OUT => OF_OP_A_OUT, -- operand A data output + OP_B_OUT => OF_OP_B_OUT, -- operant B data output + SHIFT_VAL_OUT => SHIFT_VAL_BUFF, -- shift operand output + BP1_OUT => OF_BP1_OUT, -- bypass data output + HOLD_BUS_OUT => HALT_BUS, -- insert n bubbles + MSU_FW_IN => MS_FW_PATH, -- ms forwarding path + ALU_FW_IN => ALU_FW_PATH, -- alu forwarding path + MEM_FW_IN => MEM_FW_PATH, -- memory forwarding path + WB_FW_IN => WB_FW_PATH -- write back forwarding path + ); + + + -- ####################################################################################################### + -- ## PIPELINE STAGE 3: MULTIPLICATION & SHIFT ## + -- ####################################################################################################### + + -- Multiply/Shift Unit + -- ------------------------------------------------------------------------------ + Multishifter: + MS_UNIT + port map ( + CLK => gCLK, -- global clock line + G_HALT => G_HALT, -- global halt signal + RES => gRES, -- global reset line + CTRL => MS_CTRL, -- stage control + OP_A_IN => OF_OP_A_OUT, -- operant a input + OP_B_IN => OF_OP_B_OUT, -- operant b input + BP_IN => OF_BP1_OUT, -- bypass input + CARRY_IN => CMSR(SREG_C_FLAG), -- carry input + SHIFT_V_IN => SHIFT_VAL_BUFF, -- shift value in + SHIFT_M_IN => SHIFT_MOD, -- shift mode in + OP_A_OUT => OP_A_MS, -- operant a bypass output + BP_OUT => BP_MS, -- bypass output + RESULT_OUT => OP_B_MS, -- operation result + CARRY_OUT => MS_CARRY, -- operation carry signal + OVFL_OUT => MS_OVFL, -- operation overflow signal + MSU_FW_OUT => MS_FW_PATH -- forwarding path + ); + + + -- ####################################################################################################### + -- ## PIPELINE STAGE 4: ALU OPERATION & MCR ACCESS ## + -- ####################################################################################################### + + -- Arithmetical/Logical Unit + -- ------------------------------------------------------------------------------ + Operator: + ALU + port map ( + CLK => gCLK, -- global clock net + G_HALT => G_HALT, -- global halt signal + RES => gRES, -- global active high reset + CTRL => EX1_CTRL, -- stage control + OP_A_IN => OP_A_MS, -- operand A input + OP_B_IN => OP_B_MS, -- operant B input + BP1_IN => BP_MS, -- bypass data input + BP1_OUT => EX_BP1_OUT, -- bypass data output + ADR_OUT => EX_ADR_OUT, -- memory access address + RESULT_OUT => EX_RES_OUT, -- EX result data + FLAG_IN => CMSR(31 downto 28), -- sreg alu flags input + FLAG_OUT => ALU_FLAGS, -- alu flags output + EXC_PC_IN => EXC_PC, -- pc for INT_LINK + INT_CALL_IN => INT_EXECUTE, -- this is an interrupt call + MS_CARRY_IN => MS_CARRY, -- ms carry output + MS_OVFL_IN => MS_OVFL, -- ms overflow output + MCR_DTA_OUT => MCR_DTA_WR, -- mcr write data output + MCR_DTA_IN => MCR_DTA_RD, -- mcr read data input + ALU_FW_OUT => ALU_FW_PATH -- alu forwarding path + ); + + + -- ##################################################################################################### + -- ## PIPELINE STAGE 5: DATA MEMORY ACCESS ## + -- ##################################################################################################### + + -- Memory Access System + -- ------------------------------------------------------------------------------ + Memory_Access: + LOAD_STORE_UNIT + port map ( + CLK => gCLK, -- global clock net + G_HALT => G_HALT, -- global halt signal + RES => gRES, -- global reset net + CTRL_IN => MEM_CTRL, -- stage control + MEM_DATA_IN => EX_RES_OUT, -- EX data result + MEM_ADR_IN => EX_ADR_OUT, -- memory access address + MEM_BP_IN => EX_BP1_OUT, -- bp/write data input + MODE_IN => CMSR(SREG_MODE_4 downto SREG_MODE_0), -- current processor mode + ADR_OUT => MEM_ADR_OUT, -- address bypass output + BP_OUT => MEM_BP_OUT, -- bypass(data) output + LDST_FW_OUT => MEM_FW_PATH, -- memory forwarding path + XMEM_MODE => MODE, -- processor mode for access + XMEM_ADR => D_MEM_ADR, -- D memory address output + XMEM_WR_DTA => D_MEM_WR_DTA, -- memory write data output + XMEM_ACC_REQ => D_MEM_REQ, -- access request + XMEM_RW => D_MEM_RW, -- read/write + XMEM_DQ => D_MEM_DQ -- memory data quantity + ); + + + -- ##################################################################################################### + -- ## PIPELINE STAGE 6: DATA WRITE BACK ## + -- ##################################################################################################### + + -- Data Write Back System + -- ------------------------------------------------------------------------------ + Data_Write_Back: + WB_UNIT + port map ( + CLK => gCLK, -- global clock net + G_HALT => G_HALT, -- global halt signal + RES => gRES, -- global reset net + CTRL_IN => WB_CTRL, -- stage control + ALU_DATA_IN => MEM_BP_OUT, -- alu data input + ADR_BUFF_IN => MEM_ADR_OUT, -- address bypass input + WB_DATA_OUT => WB_DATA_LINE, -- data write back line + XMEM_RD_DATA => D_MEM_RD_DTA, -- memory read data + WB_FW_OUT => WB_FW_PATH -- forwarding path + ); + +end CORE_STRUCTURE; \ No newline at end of file Index: storm_core/trunk/rtl/LOAD_STORE_UNIT.vhd =================================================================== --- storm_core/trunk/rtl/LOAD_STORE_UNIT.vhd (nonexistent) +++ storm_core/trunk/rtl/LOAD_STORE_UNIT.vhd (revision 10) @@ -0,0 +1,162 @@ +-- ####################################################### +-- # < STORM CORE PROCESSOR by Stephan Nolting > # +-- # *************************************************** # +-- # Load/Store Unit for Data/Instruction Memory Access # +-- # *************************************************** # +-- # Version 2.5, 14.07.2011 # +-- ####################################################### + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +library work; +use work.STORM_core_package.all; + +entity LOAD_STORE_UNIT is +port ( +-- ############################################################################################### +-- ## Global Control ## +-- ############################################################################################### + + CLK : in STD_LOGIC; + G_HALT : in STD_LOGIC; -- global halt line + RES : in STD_LOGIC; + CTRL_IN : in STD_LOGIC_VECTOR(31 downto 0); + +-- ############################################################################################### +-- ## Operand Connection ## +-- ############################################################################################### + + MEM_DATA_IN : in STD_LOGIC_VECTOR(31 downto 0); + MEM_ADR_IN : in STD_LOGIC_VECTOR(31 downto 0); + MEM_BP_IN : in STD_LOGIC_VECTOR(31 downto 0); + + MODE_IN : in STD_LOGIC_VECTOR(04 downto 0); + + ADR_OUT : out STD_LOGIC_VECTOR(31 downto 0); + BP_OUT : out STD_LOGIC_VECTOR(31 downto 0); + +-- ############################################################################################### +-- ## Forwarding Path ## +-- ############################################################################################### + + LDST_FW_OUT : out STD_LOGIC_VECTOR(40 downto 0); + +-- ############################################################################################### +-- ## External Memory Interface ## +-- ############################################################################################### + + XMEM_MODE : out STD_LOGIC_VECTOR(04 downto 0); -- processor mode for access + XMEM_ADR : out STD_LOGIC_VECTOR(31 downto 0); -- Address Output + XMEM_WR_DTA : out STD_LOGIC_VECTOR(31 downto 0); -- Data Output + XMEM_ACC_REQ : out STD_LOGIC; -- Access Request + XMEM_RW : out STD_LOGIC; -- Read/write signal + XMEM_DQ : out STD_LOGIC_VECTOR(01 downto 0) -- Data Quantity + + ); +end LOAD_STORE_UNIT; + +architecture LOAD_STORE_UNIT_STRUCTURE of LOAD_STORE_UNIT is + + -- Pipeline Regs -- + signal DATA_BUFFER : STD_LOGIC_VECTOR(31 downto 0); + signal ADR_BUFFER : STD_LOGIC_VECTOR(31 downto 0); + signal BP_BUFFER : STD_LOGIC_VECTOR(31 downto 0); + + -- Local Signals -- + signal BP_TEMP : STD_LOGIC_VECTOR(31 downto 0); + +begin + + -- Pipeline-Buffers ----------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + MEM_BUFFER: process(CLK, RES) + begin + if rising_edge(CLK) then + if (RES = '1') then + DATA_BUFFER <= (others => '0'); + ADR_BUFFER <= (others => '0'); + BP_BUFFER <= (others => '0'); + elsif (G_HALT = '0') then + DATA_BUFFER <= MEM_DATA_IN; -- Memory write data buffer + ADR_BUFFER <= MEM_ADR_IN; -- Memory adress buffer + BP_BUFFER <= MEM_BP_IN; -- Memory bypass buffer + end if; + end if; + end process MEM_BUFFER; + + -- Address Output -- + ADR_OUT <= ADR_BUFFER; + + -- Data MEM Address -- + XMEM_ADR <= ADR_BUFFER; + + + + -- Bypass Multiplexer --------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + BP_MUX: process(CTRL_IN, BP_BUFFER, DATA_BUFFER) + begin + if (CTRL_IN(CTRL_LINK) = '0') then + BP_TEMP <= DATA_BUFFER; + else + BP_TEMP <= BP_BUFFER; + end if; + end process BP_MUX; + + -- Stage Bypass Output -- + BP_OUT <= BP_TEMP; + + + + -- Forwarding Path ------------------------------------------------------------------------ + -- ------------------------------------------------------------------------------------------- + LDST_FW_OUT(FWD_RD_MSB downto FWD_RD_LSB) <= CTRL_IN(CTRL_RD_3 downto CTRL_RD_0); + LDST_FW_OUT(FWD_WB) <= CTRL_IN(CTRL_EN) and CTRL_IN(CTRL_WB_EN); + LDST_FW_OUT(FWD_DATA_MSB downto FWD_DATA_LSB) <= BP_TEMP; + + + + -- External Memory Interface -------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + MEM_DATA_INTERFACE: process(CTRL_IN, BP_BUFFER, MODE_IN) + variable OUTPUT_DATA_BUFFER : STD_LOGIC_VECTOR(31 downto 0); + variable ENDIAN_TMP : STD_LOGIC_VECTOR(31 downto 0); + begin + --- Output Data Alignment --- + case (CTRL_IN(CTRL_MEM_DQ_1 downto CTRL_MEM_DQ_0)) is + when DQ_WORD => -- Word Transfer + OUTPUT_DATA_BUFFER := BP_BUFFER; + when DQ_BYTE => -- Byte Transfer + OUTPUT_DATA_BUFFER := BP_BUFFER(07 downto 00) & BP_BUFFER(07 downto 00) & + BP_BUFFER(07 downto 00) & BP_BUFFER(07 downto 00); + when others => -- Halfword Transfer + OUTPUT_DATA_BUFFER := BP_BUFFER(15 downto 00) & BP_BUFFER(15 downto 00); + end case; + + --- Endianess Converter --- + if (USE_BIG_ENDIAN = FALSE) then -- Little Endian + ENDIAN_TMP := OUTPUT_DATA_BUFFER(07 downto 00) & OUTPUT_DATA_BUFFER(15 downto 08) & + OUTPUT_DATA_BUFFER(23 downto 16) & OUTPUT_DATA_BUFFER(31 downto 24); + else -- Big Endian + ENDIAN_TMP := OUTPUT_DATA_BUFFER(31 downto 24) & OUTPUT_DATA_BUFFER(23 downto 16) & + OUTPUT_DATA_BUFFER(15 downto 08) & OUTPUT_DATA_BUFFER(07 downto 00); + end if; + + --- D-MEM Interface --- + XMEM_WR_DTA <= ENDIAN_TMP; + XMEM_RW <= CTRL_IN(CTRL_MEM_RW); -- Read/Write + XMEM_DQ <= CTRL_IN(CTRL_MEM_DQ_1 downto CTRL_MEM_DQ_0); -- Data Quantity + XMEM_ACC_REQ <= CTRL_IN(CTRL_EN) and CTRL_IN(CTRL_MEM_ACC); + + --- Mode for MEM access -- + if (CTRL_IN(CTRL_MEM_USER) = '1') then + XMEM_MODE <= User32_MODE; -- force user_mode + else + XMEM_MODE <= MODE_IN; -- current processor mode + end if; + + end process MEM_DATA_INTERFACE; + + +end LOAD_STORE_UNIT_STRUCTURE; \ No newline at end of file Index: storm_core/trunk/rtl/FLOW_CTRL.vhd =================================================================== --- storm_core/trunk/rtl/FLOW_CTRL.vhd (nonexistent) +++ storm_core/trunk/rtl/FLOW_CTRL.vhd (revision 10) @@ -0,0 +1,509 @@ +-- ####################################################### +-- # < STORM CORE PROCESSOR by Stephan Nolting > # +-- # *************************************************** # +-- # Operation Flow Control Unit # +-- # *************************************************** # +-- # Version 2.7.6, 26.08.2011 # +-- ####################################################### + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +library work; +use work.STORM_core_package.all; + +entity FLOW_CTRL is + Port ( +-- ############################################################################################### +-- ## Global Control ## +-- ############################################################################################### + + RES : in STD_LOGIC; -- global reset input (high active) + CLK : in STD_LOGIC; -- global clock input + G_HALT : in STD_LOGIC; -- global halt line + +-- ############################################################################################### +-- ## Instruction Interface ## +-- ############################################################################################### + + INSTR_IN : in STD_LOGIC_VECTOR(31 downto 0); -- instr memory input + INST_MREQ_OUT : out STD_LOGIC; -- automatic instruction fetch memory request + +-- ############################################################################################### +-- ## OPCODE Decoder Connection ## +-- ############################################################################################### + + OPCODE_DATA_OUT : out STD_LOGIC_VECTOR(31 downto 0); + OPCODE_CTRL_IN : in STD_LOGIC_VECTOR(99 downto 0); + OPCODE_CTRL_OUT : out STD_LOGIC_VECTOR(15 downto 0); + +-- ############################################################################################### +-- ## Extended Control ## +-- ############################################################################################### + + PC_HALT_OUT : out STD_LOGIC; + SREG_IN : in STD_LOGIC_VECTOR(31 downto 0); + EXECUTE_INT_IN : in STD_LOGIC; + HOLD_BUS_IN : in STD_LOGIC_VECTOR(02 downto 0); + +-- ############################################################################################### +-- ## Pipeline Stage Control ## +-- ############################################################################################### + + OP_ADR_OUT : out STD_LOGIC_VECTOR(14 downto 0); + IMM_OUT : out STD_LOGIC_VECTOR(31 downto 0); + SHIFT_M_OUT : out STD_LOGIC_VECTOR(01 downto 0); + SHIFT_C_OUT : out STD_LOGIC_VECTOR(04 downto 0); + + OF_CTRL_OUT : out STD_LOGIC_VECTOR(31 downto 0); + MS_CTRL_OUT : out STD_LOGIC_VECTOR(31 downto 0); + EX1_CTRL_OUT : out STD_LOGIC_VECTOR(31 downto 0); + MEM_CTRL_OUT : out STD_LOGIC_VECTOR(31 downto 0); + WB_CTRL_OUT : out STD_LOGIC_VECTOR(31 downto 0) + + ); +end FLOW_CTRL; + +architecture FLOW_CTRL_STRUCTURE of FLOW_CTRL is + +-- ############################################################################################### +-- ## Local Signals ## +-- ############################################################################################### + + -- Branch System -- + signal BRANCH_TAKEN : STD_LOGIC; + signal DISABLE_CYCLE : STD_LOGIC; + + -- Halt System -- + signal HOLD_DIS_OF : STD_LOGIC; + signal MULTI_CYCLE_OP : STD_LOGIC; + + -- Instruction Validation System -- + signal VALID_INSTR : STD_LOGIC; + + -- Control Busses -- + signal DEC_CTRL : STD_LOGIC_VECTOR(31 downto 0); + signal MS_CTRL : STD_LOGIC_VECTOR(31 downto 0); + signal EX1_CTRL : STD_LOGIC_VECTOR(31 downto 0); + signal CTRL_EX1_BUS : STD_LOGIC_VECTOR(31 downto 0); + signal MEM_CTRL : STD_LOGIC_VECTOR(31 downto 0); + signal WB_CTRL : STD_LOGIC_VECTOR(31 downto 0); + + -- IF Arbiter -- + type PFR_TYPE is array (0 to 3) of STD_LOGIC_VECTOR(31 downto 0); + signal PFR_IR : PFR_TYPE; + signal WR_CNT, RD_CNT : STD_LOGIC_VECTOR(01 downto 0); + signal IF_CYCLE_CNT : STD_LOGIC_VECTOR(01 downto 0); + signal IF_CYCLE_CNT_NXT : STD_LOGIC_VECTOR(01 downto 0); + signal WR_IR_EN : STD_LOGIC; + signal WR_INC, RD_INC : STD_LOGIC; + +begin + + -- ####################################################################################################### + -- ## PIPELINE STAGE 0/1: INSTRUCTION FETCH ARBITER ## + -- ####################################################################################################### + + -- Active Cycle Counter ---------------------------------------------------------------------- + -- ---------------------------------------------------------------------------------------------- + -- SYNC -- + IF_CYCLE_COUNTER_ASYNC: process(IF_CYCLE_CNT, HOLD_BUS_IN, DISABLE_CYCLE, MULTI_CYCLE_OP) + begin + -- Load counter with operand unit value + if (HOLD_BUS_IN(0) = '1') and (DISABLE_CYCLE = '0') then + IF_CYCLE_CNT_NXT <= HOLD_BUS_IN(2 downto 1); + elsif (MULTI_CYCLE_OP = '1') then + IF_CYCLE_CNT_NXT <= "01"; + elsif (to_integer(unsigned(IF_CYCLE_CNT)) /= 0) then -- Decrement until zero + IF_CYCLE_CNT_NXT <= Std_Logic_Vector(unsigned(IF_CYCLE_CNT) - 1); + else + IF_CYCLE_CNT_NXT <= "00"; + end if; + end process IF_CYCLE_COUNTER_ASYNC; + + + -- ASYNC -- + IF_CYCLE_COUNTER_SYNC: process (CLK, RES, IF_CYCLE_CNT_NXT, BRANCH_TAKEN) + begin + --- Sync counter --- + if rising_edge(CLK) then + if (RES = '1') then + IF_CYCLE_CNT <= (others => '0'); + elsif (G_HALT = '0') then + IF_CYCLE_CNT <= IF_CYCLE_CNT_NXT; + end if; + end if; + + --- New Instruction Request --- + INST_MREQ_OUT <= '0'; + if (IF_CYCLE_CNT_NXT = "00") and (BRANCH_TAKEN = '0') then + INST_MREQ_OUT <= '1'; + end if; + end process IF_CYCLE_COUNTER_SYNC; + + + + -- IF Arbiter Control ------------------------------------------------------------------------ + -- ---------------------------------------------------------------------------------------------- + IF_ARBITER_CTRL : process(IF_CYCLE_CNT, HOLD_BUS_IN, DISABLE_CYCLE, MULTI_CYCLE_OP) + begin + --- Global IR Write Enable --- + if (to_integer(unsigned(IF_CYCLE_CNT)) = 0) then + WR_IR_EN <= '1'; -- RD_INC + else + WR_IR_EN <= '0'; -- '0' + end if; + + --- RD/WR CNT Enable & Stage Enable & Memory Request --- + if ((to_integer(unsigned(IF_CYCLE_CNT)) > 1) or + (HOLD_BUS_IN(0) = '1')) and (DISABLE_CYCLE = '0') then + RD_INC <= '0'; + HOLD_DIS_OF <= '1'; + PC_HALT_OUT <= '1'; + else -- Multi-Cycle Operations: Freeze instruction fetch but keep pipeline enabled + RD_INC <= not MULTI_CYCLE_OP; + HOLD_DIS_OF <= '0'; + PC_HALT_OUT <= MULTI_CYCLE_OP; + end if; + + if (to_integer(unsigned(IF_CYCLE_CNT)) = 0) then + WR_INC <= '1'; + else + WR_INC <= '0'; + end if; + + end process IF_ARBITER_CTRL; + + + + -- Prefetch Buffer Access Pointer ------------------------------------------------------------ + -- ---------------------------------------------------------------------------------------------- + PFR_BUFFER_CTRL: process(CLK, RES, RD_INC, WR_INC) + variable RD_C_INT, WR_C_INT : std_logic_vector(1 downto 0) := "00"; + begin + if rising_edge(CLK) then + if (RES = '1') then + RD_C_INT := "11"; -- we need 1 entry offset + WR_C_INT := "00"; + elsif (G_HALT = '0') then--if (RD_INC = '1') then -- no HALT applied + if (RD_INC = '1') then + RD_C_INT := Std_Logic_Vector(unsigned(RD_C_INT) + 1); + end if; + if (WR_INC = '1') then + WR_C_INT := Std_Logic_Vector(unsigned(WR_C_INT) + 1); + end if; + end if; + end if; + WR_CNT <= WR_C_INT; + RD_CNT <= RD_C_INT; + end process PFR_BUFFER_CTRL; + + + + -- Prefetch Buffer Access -------------------------------------------------------------------- + -- ---------------------------------------------------------------------------------------------- + PFR_BUFFER_W_ACC: process(CLK, RES, INSTR_IN, WR_CNT, WR_IR_EN) + begin + --- Sync Instruction Buffer Write --- + if rising_edge(CLK) then + if (RES = '1') then + PFR_IR <= (others => NOP_CMD); + elsif (WR_IR_EN = '1') and (G_HALT = '0') then + PFR_IR(to_integer(unsigned(WR_CNT))) <= INSTR_IN; + end if; + end if; + end process PFR_BUFFER_W_ACC; + + --- Async Instruction Buffer Read --- + OPCODE_DATA_OUT <= PFR_IR(to_integer(unsigned(RD_CNT))); + + + + -- ####################################################################################################### + -- ## PIPELINE STAGE 2: OPERAND FETCH ## + -- ####################################################################################################### + + -- Stage "Operand Fetch" Control Unit -------------------------------------------------------- + -- ---------------------------------------------------------------------------------------------- + OF_CTRL_UNIT: process(CLK, RES, OPCODE_CTRL_IN, DISABLE_CYCLE, HOLD_DIS_OF) + variable FORCE_DISABLE : STD_LOGIC; + variable OP_BUFFER : STD_LOGIC_VECTOR(31 downto 0); + variable M_CYC_CNT : STD_LOGIC; + begin + --- Opcode Decoder Connection --- + if rising_edge(CLK) then + if (RES = '1') then + OP_BUFFER := (others => '0'); + OP_ADR_OUT <= (others => '0'); + IMM_OUT <= (others => '0'); + SHIFT_M_OUT <= (others => '0'); + SHIFT_C_OUT <= (others => '0'); + M_CYC_CNT := '0'; + elsif (HOLD_DIS_OF = '0') and (G_HALT = '0') then + M_CYC_CNT := OPCODE_CTRL_IN(86); + OP_BUFFER := OPCODE_CTRL_IN(31 downto 00); + -- disable stage when branching -- + OP_BUFFER(CTRL_EN) := not (DISABLE_CYCLE or HOLD_DIS_OF); + OP_ADR_OUT <= OPCODE_CTRL_IN(46 downto 32); + IMM_OUT <= OPCODE_CTRL_IN(78 downto 47); + SHIFT_M_OUT <= OPCODE_CTRL_IN(80 downto 79); + SHIFT_C_OUT <= OPCODE_CTRL_IN(85 downto 81); + end if; + end if; + + --- Default Disable --- + FORCE_DISABLE := '0'; + if (OP_BUFFER(CTRL_COND_3 downto CTRL_COND_0) = COND_NV) then + FORCE_DISABLE := '1'; + end if; + + --- Multi-Cycle Operation Counter --- + -- Freeze instruction fetch but keep pipeline enabled + MULTI_CYCLE_OP <= '0'; + if (OPCODE_CTRL_IN(86) = '1') and (DISABLE_CYCLE = '0') then + MULTI_CYCLE_OP <= '1'; + end if; + + --- Multi-Cycle Counter Writeback --- + OPCODE_CTRL_OUT(0) <= M_CYC_CNT; + + --- Stage CTRL Bus --- + DEC_CTRL <= OP_BUFFER; + -- Disable Instruction Processing when inserting a dummy cycle and not + -- performing a multi-cycle operation + DEC_CTRL(CTRL_EN) <= OP_BUFFER(CTRL_EN) and (not FORCE_DISABLE); + + end process OF_CTRL_UNIT; + + + -- Pipeline Stage "OPERAND FETCH" CTRL Bus --------------------------------------------------- + -- ---------------------------------------------------------------------------------------------- + OF_CTRL_OUT <= DEC_CTRL; + + + + -- ####################################################################################################### + -- ## PIPELINE STAGE 3: MULTIPLICATION & SHIFT ## + -- ####################################################################################################### + + -- Pipeline Registers ------------------------------------------------------------------------ + -- ---------------------------------------------------------------------------------------------- + STAGE_BUFFER_2: process(CLK, RES, DEC_CTRL, DISABLE_CYCLE, HOLD_DIS_OF) + begin + if rising_edge (CLK) then + if (RES = '1') then + MS_CTRL <= (others => '0'); + -- set 'never condition' for start up -- + MS_CTRL(CTRL_COND_3 downto CTRL_COND_0) <= COND_NV; + elsif (G_HALT = '0') then + MS_CTRL <= DEC_CTRL; + -- disable stage when branching or inserting dummy cycle -- + MS_CTRL(CTRL_EN) <= DEC_CTRL(CTRL_EN) and (not DISABLE_CYCLE) and (not HOLD_DIS_OF); + end if; + end if; + end process STAGE_BUFFER_2; + + + -- Pipeline Stage "MULTIPLY/SHIFT" CTRL Bus -------------------------------------------------- + -- ---------------------------------------------------------------------------------------------- + MS_CTRL_OUT <= MS_CTRL; + + + + -- ##################################################################################################### + -- ## PIPELINE STAGE 4: ALU OPERATION & MCR ACCESS ## + -- ##################################################################################################### + + -- Pipeline Registers ------------------------------------------------------------------------ + -- ---------------------------------------------------------------------------------------------- + STAGE_BUFFER_3: process(CLK, RES, MS_CTRL, DISABLE_CYCLE) + begin + if rising_edge(CLK) then + if (RES = '1') then + EX1_CTRL <= (others => '0'); + -- set 'never condition' for start up -- + EX1_CTRL(CTRL_COND_3 downto CTRL_COND_0) <= COND_NV; + elsif (G_HALT = '0') then + EX1_CTRL <= MS_CTRL; + -- disable stage when branching -- + EX1_CTRL(CTRL_EN) <= MS_CTRL(CTRL_EN) and (not DISABLE_CYCLE); + end if; + end if; + end process STAGE_BUFFER_3; + + + -- Branch Cycle Arbiter ---------------------------------------------------------------------- + -- ---------------------------------------------------------------------------------------------- + BRANCH_CYCLE_ARBITER: process(CLK, RES, BRANCH_TAKEN, EXECUTE_INT_IN) + variable CA_CNT : STD_LOGIC_VECTOR(1 downto 0); + begin + --- Cycle Counter --- + if rising_edge(CLK) then + if (RES = '1') then -- reset + CA_CNT := (others => '0'); + elsif (G_HALT = '0') then + if (BRANCH_TAKEN = '1') or (EXECUTE_INT_IN = '1') then -- restart + CA_CNT := Std_Logic_Vector(to_unsigned(DC_TAKEN_BRANCH, 2)); + elsif (to_integer(unsigned(CA_CNT)) /= 0) then -- decrement until zero + CA_CNT := Std_Logic_Vector(unsigned(CA_CNT) - 1); + end if; + end if; + end if; + + --- Disable OF, MS and EX stage in next cycle --- + DISABLE_CYCLE <= '0'; + if (to_integer(unsigned(CA_CNT)) /= 0) or (BRANCH_TAKEN = '1') or (EXECUTE_INT_IN = '1') then + DISABLE_CYCLE <= '1'; + end if; + end process BRANCH_CYCLE_ARBITER; + + + -- Condition Check System -------------------------------------------------------------------- + -- ---------------------------------------------------------------------------------------------- + COND_CHECK_SYS: process(EX1_CTRL, SREG_IN) + variable EXECUTE : STD_LOGIC; + begin + case EX1_CTRL(CTRL_COND_3 downto CTRL_COND_0) is + when COND_EQ => -- EQ = EQUAL: Zero set + EXECUTE := SREG_IN(SREG_Z_FLAG); + when COND_NE => -- NE = NOT EQUAL: Zero clr + EXECUTE := not SREG_IN(SREG_Z_FLAG); + when COND_CS => -- CS = UNSIGNED OR HIGHER: Carry set + EXECUTE := SREG_IN(SREG_C_FLAG); + when COND_CC => -- CC = UNSIGNED LOWER: Carry clr + EXECUTE := not SREG_IN(SREG_C_FLAG); + when COND_MI => -- MI = NEGATIVE: Negative set + EXECUTE := SREG_IN(SREG_N_FLAG); + when COND_PL => -- PL = POSITIVE OR ZERO: Negative clr + EXECUTE := not SREG_IN(SREG_N_FLAG); + when COND_VS => -- VS = OVERFLOW: Overflow set + EXECUTE := SREG_IN(SREG_O_FLAG); + when COND_VC => -- VC = NO OVERFLOW: Overflow clr + EXECUTE := not SREG_IN(SREG_O_FLAG); + when COND_HI => -- HI = UNSIGNED HIGHER: Carry set and Zero clr + EXECUTE := SREG_IN(SREG_C_FLAG) and (not SREG_IN(SREG_Z_FLAG)); + when COND_LS => -- LS = UNSIGNED LOWER OR SAME: Carry clr or Zero set + EXECUTE := (not SREG_IN(SREG_C_FLAG)) or SREG_IN(SREG_Z_FLAG); + when COND_GE => -- GE = GREATER OR EQUAL + EXECUTE := not(SREG_IN(SREG_N_FLAG) xor SREG_IN(SREG_O_FLAG)); + when COND_LT => -- LT = LESS THAN + EXECUTE := SREG_IN(SREG_N_FLAG) xor SREG_IN(SREG_O_FLAG); + when COND_GT => -- GT = GREATER THAN + EXECUTE := (not SREG_IN(SREG_Z_FLAG)) and SREG_IN(SREG_O_FLAG); + when COND_LE => -- LE = LESS THAN OR EQUAL + EXECUTE := SREG_IN(SREG_Z_FLAG) and (SREG_IN(SREG_N_FLAG) xor SREG_IN(SREG_O_FLAG)); + when COND_AL => -- AL = ALWAYS + EXECUTE := '1'; + when COND_NV => -- NV = NEVER + EXECUTE := '0'; + when others => -- UNDEFINED + EXECUTE := '0'; + end case; + --- Valid Instruction Signal --- + VALID_INSTR <= EX1_CTRL(CTRL_EN) and EXECUTE; + end process COND_CHECK_SYS; + + + + -- Detector for automatic/manual branches ---------------------------------------------------- + -- ---------------------------------------------------------------------------------------------- + BRANCH_DETECTOR: process(EX1_CTRL, VALID_INSTR) + variable MANUAL_BRANCH : STD_LOGIC; + begin + MANUAL_BRANCH := '0'; + if (EX1_CTRL(CTRL_RD_3 downto CTRL_RD_0) = C_PC_ADR) and (EX1_CTRL(CTRL_WB_EN) = '1') then + MANUAL_BRANCH := '1'; -- set if destination register is the PC + end if; + -- Branch Taken Signal -- + BRANCH_TAKEN <= VALID_INSTR and (EX1_CTRL(CTRL_BRANCH) or MANUAL_BRANCH); + end process BRANCH_DETECTOR; + + + -- EX Stage CTRL_BUS and Link Control -------------------------------------------------------- + -- ---------------------------------------------------------------------------------------------- + EX_CTRL_BUS_CONSTRUCTION: process(EX1_CTRL, BRANCH_TAKEN, VALID_INSTR, EXECUTE_INT_IN) + begin + + --- CTRL_BUS for THIS stage --- + EX1_CTRL_OUT <= EX1_CTRL; + EX1_CTRL_OUT(CTRL_BRANCH) <= BRANCH_TAKEN; -- insert branch taken signal + EX1_CTRL_OUT(CTRL_EN) <= VALID_INSTR; -- insert current op validation + + --- CTRL_BUS for NEXT stage --- + CTRL_EX1_BUS <= EX1_CTRL; + CTRL_EX1_BUS(CTRL_BRANCH) <= BRANCH_TAKEN; -- insert branch taken signal + CTRL_EX1_BUS(CTRL_EN) <= VALID_INSTR; -- insert current op validation + + --- Branch & Link Operation for Interrupt Call (Next stage) --- + if (EXECUTE_INT_IN = '1') then + CTRL_EX1_BUS(CTRL_MEM_ACC) <= '0'; -- disable memory access + CTRL_EX1_BUS(CTRL_MREG_ACC) <= '0'; -- disable mcr access + CTRL_EX1_BUS(CTRL_EN) <= '1'; -- force enable + CTRL_EX1_BUS(CTRL_LINK) <= '1'; -- force LR pass + CTRL_EX1_BUS(CTRL_WB_EN) <= '1'; -- force LR write back + end if; + + --- Insert RD = LR when performing Link Operations --- + if (EX1_CTRL(CTRL_LINK) = '1') or (EXECUTE_INT_IN = '1') then + CTRL_EX1_BUS(CTRL_RD_3 downto CTRL_RD_0) <= C_LR_ADR; + end if; + end process EX_CTRL_BUS_CONSTRUCTION; + + + -- Pipeline Stage "EXECUTE" CTRL Bus --------------------------------------------------------- + -- ---------------------------------------------------------------------------------------------- + --EX1_CTRL_OUT <= CTRL_EX1_BUS; + + + + -- ##################################################################################################### + -- ## PIPELINE STAGE 5: DATA MEMORY ACCESS ## + -- ##################################################################################################### + + -- Pipeline Registers ------------------------------------------------------------------------ + -- ---------------------------------------------------------------------------------------------- + STAGE_BUFFER_4: process(CLK, RES) + begin + if rising_edge (CLK) then + if (RES = '1') then + MEM_CTRL <= (others => '0'); + elsif (G_HALT = '0') then + MEM_CTRL <= CTRL_EX1_BUS; + end if; + end if; + end process STAGE_BUFFER_4; + + + -- Pipeline Stage "MEMORY" CTRL Bus ---------------------------------------------------------- + -- ---------------------------------------------------------------------------------------------- + MEM_CTRL_OUT <= MEM_CTRL; + + + + -- ##################################################################################################### + -- ## PIPELINE STAGE 6: DATA WRITE BACK ## + -- ##################################################################################################### + + -- Pipeline Registers ------------------------------------------------------------------------ + -- ---------------------------------------------------------------------------------------------- + STAGE_BUFFER_5: process(CLK, RES) + begin + if rising_edge (CLK) then + if (RES = '1') then + WB_CTRL <= (others => '0'); + elsif (G_HALT = '0') then + WB_CTRL <= MEM_CTRL; + WB_CTRL(CTRL_MODE_4 downto CTRL_MODE_0) <= SREG_IN(SREG_MODE_4 downto SREG_MODE_0); + end if; + end if; + end process STAGE_BUFFER_5; + + + -- Pipeline Stage "WRITE BACK" CTRL Bus ------------------------------------------------------ + -- ---------------------------------------------------------------------------------------------- + WB_CTRL_OUT <= WB_CTRL; + + + +end FLOW_CTRL_STRUCTURE; \ No newline at end of file Index: storm_core/trunk/rtl/BARREL_SHIFTER.vhd =================================================================== --- storm_core/trunk/rtl/BARREL_SHIFTER.vhd (nonexistent) +++ storm_core/trunk/rtl/BARREL_SHIFTER.vhd (revision 10) @@ -0,0 +1,109 @@ +-- ####################################################### +-- # < STORM CORE PROCESSOR by Stephan Nolting > # +-- # *************************************************** # +-- # Barrelshifter Unit # +-- # *************************************************** # +-- # Version 1.2, 14.01.2011 # +-- ####################################################### + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +library work; +use work.STORM_core_package.all; + +entity BARREL_SHIFTER is + port ( + -- Function Operands -- + ---------------------------------------------------- + SHIFT_DATA_IN : in STD_LOGIC_VECTOR(31 downto 0); + SHIFT_DATA_OUT : out STD_LOGIC_VECTOR(31 downto 0); + + -- Flag Operands -- + ---------------------------------------------------- + CARRY_IN : in STD_LOGIC; + CARRY_OUT : out STD_LOGIC; + OVERFLOW_OUT : out STD_LOGIC; + + -- Operation Control -- + ---------------------------------------------------- + SHIFT_MODE : in STD_LOGIC_VECTOR(01 downto 0); + SHIFT_POS : in STD_LOGIC_VECTOR(04 downto 0) + ); +end BARREL_SHIFTER; + +architecture Structure of BARREL_SHIFTER is + +begin + + -- Barrelshifter --------------------------------------------------------------------------------------- + -- -------------------------------------------------------------------------------------------------------- + BARREL_SHIFTER: process(SHIFT_MODE, SHIFT_POS, SHIFT_DATA_IN, CARRY_IN) + variable shift_positions : integer range 0 to 31; + variable SHIFT_DATA : STD_LOGIC_VECTOR(31 downto 00); + begin + --- Shift amount --- + shift_positions := to_integer(unsigned(SHIFT_POS)); + + --- Shifter --- + case (SHIFT_MODE) is + when S_LSL => -- Logical Shift Left + if (shift_positions = 0) then -- no shift, keep carry + SHIFT_DATA := SHIFT_DATA_IN; + CARRY_OUT <= CARRY_IN; + else -- LSL #shift_positions + SHIFT_DATA := to_StdLogicVector(to_BitVector(SHIFT_DATA_IN) sll shift_positions); + CARRY_OUT <= SHIFT_DATA_IN(32 - shift_positions); + end if; + + when S_LSR => -- Logical Shift Right + if (shift_positions = 0) then -- LSR #32 + SHIFT_DATA := to_StdLogicVector(to_BitVector(SHIFT_DATA_IN) srl 32); + CARRY_OUT <= SHIFT_DATA_IN(31); + else -- LSR #shift_positions + SHIFT_DATA := to_StdLogicVector(to_BitVector(SHIFT_DATA_IN) srl shift_positions); + CARRY_OUT <= SHIFT_DATA_IN(shift_positions - 1); + end if; + + when S_ASR => -- Arithmetical Shift Right + if (shift_positions = 0) then -- ASR #32 + SHIFT_DATA := to_StdLogicVector(to_BitVector(SHIFT_DATA_IN) sra 32); + CARRY_OUT <= SHIFT_DATA_IN(31); + else -- ASR #shift_positions + SHIFT_DATA := to_StdLogicVector(to_BitVector(SHIFT_DATA_IN) sra shift_positions); + CARRY_OUT <= SHIFT_DATA_IN(shift_positions - 1); + end if; + + when S_ROR => -- Rotate Right (Extended) + if (shift_positions = 0) then -- RRX = ROR #1 and fill with carry flag + SHIFT_DATA := CARRY_IN & SHIFT_DATA_IN(31 downto 1); -- fill with carry flag + CARRY_OUT <= SHIFT_DATA_IN(0); + else -- ROR #shift_positions + SHIFT_DATA := to_StdLogicVector(to_BitVector(SHIFT_DATA_IN) ror shift_positions); + CARRY_OUT <= SHIFT_DATA_IN(shift_positions - 1); + end if; + + when others => -- undefined + SHIFT_DATA := (others => '0'); + CARRY_OUT <= '0'; + end case; + + --- Overflow Flag --- + if (STORM_MODE = TRUE) then -- use cool overflow feature ;) + if (SHIFT_MODE = S_LSL) then -- broken sign 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=================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: storm_core/trunk/doc/STORM CORE datasheet.pdf =================================================================== --- storm_core/trunk/doc/STORM CORE datasheet.pdf (nonexistent) +++ storm_core/trunk/doc/STORM CORE datasheet.pdf (revision 10)
storm_core/trunk/doc/STORM CORE datasheet.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: storm_core/trunk/sim/storm_debug_wave.wcfg =================================================================== --- storm_core/trunk/sim/storm_debug_wave.wcfg (nonexistent) +++ storm_core/trunk/sim/storm_debug_wave.wcfg (revision 10) @@ -0,0 +1,2568 @@ + + + + + + + + + + + + + + + + + PROCESSOR CORE + label + #000000 + 230 230 230 + + + halt + halt + + + gclk + gclk + + + [0] + of_ctrl_out[0] + + + [0] + ms_ctrl_out[0] + + + [0] + ex1_ctrl_out[0] + + + [0] + mem_ctrl_out[0] + + + [0] + wb_ctrl_out[0] + + + of_ctrl_out[31:0] + of_ctrl_out[31:0] + + + ms_ctrl_out[31:0] + ms_ctrl_out[31:0] + + + ex1_ctrl_out[31:0] + ex1_ctrl_out[31:0] + + + mem_ctrl_out[31:0] + mem_ctrl_out[31:0] + + + op_adr_out[14:0] + op_adr_out[14:0] + HEXRADIX + + + label + reg_file[0:31] + reg_file[0:31] + UNSIGNEDDECRADIX + reg_file[0:31] + true + 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