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/tags/arelease/gpl.txt File deleted
/tags/arelease/lgpl.txt File deleted
/tags/arelease/VHDL/TG68.vhd File deleted \ No newline at end of file
/tags/arelease/VHDL/TG68_fast.vhd File deleted
/trunk/lgpl.txt File deleted
/trunk/VHDL/TG68_fast.vhd File deleted
/trunk/VHDL/TG68.vhd File deleted \ No newline at end of file
/trunk/gpl.txt File deleted
/tg68/trunk/VHDL/TG68_fast.vhd
0,0 → 1,3232
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- --
-- This is the 68000 software compatible Kernal of TG68 --
-- --
-- Copyright (c) 2007 Tobias Gubener <tobiflex@opencores.org> --
-- --
-- This source file is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU Lesser General Public License as published --
-- by the Free Software Foundation, either version 3 of the License, or --
-- (at your option) any later version. --
-- --
-- This source file is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
-- --
------------------------------------------------------------------------------
------------------------------------------------------------------------------
--
-- Revision 1.06 2009/02/10
-- Bugfix shift and rotations opcodes when the bitcount and the data are in the same register:
-- Example lsr.l D2,D2
-- Thanks to Peter Graf for report
--
-- Revision 1.05 2009/01/26
-- Implement missing RTR
-- Thanks to Peter Graf for report
--
-- Revision 1.04 2007/12/29
-- size improvement
-- change signal "microaddr" to one hot state machine
--
-- Revision 1.03 2007/12/21
-- Thanks to Andreas Ehliar
-- Split regfile to use blockram for registers
-- insert "WHEN OTHERS => null;" on END CASE;
--
-- Revision 1.02 2007/12/17
-- Bugfix jsr nn.w
--
-- Revision 1.01 2007/11/28
-- add MOVEP
-- Bugfix Interrupt in MOVEQ
--
-- Revision 1.0 2007/11/05
-- Clean up code and first release
--
-- known bugs/todo:
-- Add CHK INSTRUCTION
-- full decode ILLEGAL INSTRUCTIONS
-- Add FC Output
-- add odd Address test
-- add TRACE
-- Movem with regmask==x0000
 
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity TG68_fast is
port(clk : in std_logic;
reset : in std_logic; --low active
clkena_in : in std_logic:='1';
data_in : in std_logic_vector(15 downto 0);
IPL : in std_logic_vector(2 downto 0):="111";
test_IPL : in std_logic:='0'; --only for debugging
address : out std_logic_vector(31 downto 0);
data_write : out std_logic_vector(15 downto 0);
state_out : out std_logic_vector(1 downto 0);
LDS, UDS : out std_logic;
decodeOPC : buffer std_logic;
wr : out std_logic
);
end TG68_fast;
 
architecture logic of TG68_fast is
 
signal state : std_logic_vector(1 downto 0);
signal clkena : std_logic;
signal TG68_PC : std_logic_vector(31 downto 0);
signal TG68_PC_add : std_logic_vector(31 downto 0);
signal memaddr : std_logic_vector(31 downto 0);
signal memaddr_in : std_logic_vector(31 downto 0);
signal ea_data : std_logic_vector(31 downto 0);
signal ea_data_OP1 : std_logic;
signal setaddrlong : std_logic;
signal OP1out, OP2out : std_logic_vector(31 downto 0);
signal OP1outbrief : std_logic_vector(15 downto 0);
signal OP1in : std_logic_vector(31 downto 0);
signal data_write_tmp : std_logic_vector(31 downto 0);
signal Xtmp : std_logic_vector(31 downto 0);
signal PC_dataa, PC_datab, PC_result : std_logic_vector(31 downto 0);
signal setregstore : std_logic;
signal datatype : std_logic_vector(1 downto 0);
signal longread : std_logic;
signal longreaddirect : std_logic;
signal long_done : std_logic;
signal nextpass : std_logic;
signal setnextpass : std_logic;
signal setdispbyte : std_logic;
signal setdisp : std_logic;
signal setdispbrief : std_logic;
signal regdirectsource : std_logic;
signal endOPC : std_logic;
signal postadd : std_logic;
signal presub : std_logic;
signal addsub_a : std_logic_vector(31 downto 0);
signal addsub_b : std_logic_vector(31 downto 0);
signal addsub_q : std_logic_vector(31 downto 0);
signal briefext : std_logic_vector(31 downto 0);
signal setbriefext : std_logic;
signal addsub : std_logic;
signal c_in : std_logic_vector(3 downto 0);
signal c_out : std_logic_vector(2 downto 0);
signal add_result : std_logic_vector(33 downto 0);
signal addsub_ofl : std_logic_vector(2 downto 0);
signal flag_z : std_logic_vector(2 downto 0);
 
signal last_data_read : std_logic_vector(15 downto 0);
signal data_read : std_logic_vector(31 downto 0);
 
signal registerin : std_logic_vector(31 downto 0);
signal reg_QA : std_logic_vector(31 downto 0);
signal reg_QB : std_logic_vector(31 downto 0);
signal Hwrena,Lwrena : std_logic;
signal Regwrena : std_logic;
signal rf_dest_addr : std_logic_vector(6 downto 0);
signal rf_source_addr : std_logic_vector(6 downto 0);
signal rf_dest_addr_tmp : std_logic_vector(6 downto 0);
signal rf_source_addr_tmp : std_logic_vector(6 downto 0);
signal opcode : std_logic_vector(15 downto 0);
signal laststate : std_logic_vector(1 downto 0);
signal setstate : std_logic_vector(1 downto 0);
 
signal mem_address : std_logic_vector(31 downto 0);
signal memaddr_a : std_logic_vector(31 downto 0);
signal mem_data_read : std_logic_vector(31 downto 0);
signal mem_data_write : std_logic_vector(31 downto 0);
signal set_mem_rega : std_logic;
signal data_read_ram : std_logic_vector(31 downto 0);
signal data_read_uart : std_logic_vector(7 downto 0);
 
signal counter_reg : std_logic_vector(31 downto 0);
 
signal TG68_PC_br8 : std_logic;
signal TG68_PC_brw : std_logic;
signal TG68_PC_nop : std_logic;
signal setgetbrief : std_logic;
signal getbrief : std_logic;
signal brief : std_logic_vector(15 downto 0);
signal dest_areg : std_logic;
signal source_areg : std_logic;
signal data_is_source : std_logic;
signal set_store_in_tmp : std_logic;
signal store_in_tmp : std_logic;
signal write_back : std_logic;
signal setaddsub : std_logic;
signal setstackaddr : std_logic;
signal writePC : std_logic;
signal writePC_add : std_logic;
signal set_TG68_PC_dec: std_logic;
signal TG68_PC_dec : std_logic_vector(1 downto 0);
signal directPC : std_logic;
signal set_directPC : std_logic;
signal execOPC : std_logic;
signal fetchOPC : std_logic;
signal Flags : std_logic_vector(15 downto 0); --T.S..III ...XNZVC
signal set_Flags : std_logic_vector(3 downto 0); --NZVC
signal exec_ADD : std_logic;
signal exec_OR : std_logic;
signal exec_AND : std_logic;
signal exec_EOR : std_logic;
signal exec_MOVE : std_logic;
signal exec_MOVEQ : std_logic;
signal exec_MOVESR : std_logic;
signal exec_DIRECT : std_logic;
signal exec_ADDQ : std_logic;
signal exec_CMP : std_logic;
signal exec_ROT : std_logic;
signal exec_exg : std_logic;
signal exec_swap : std_logic;
signal exec_write_back: std_logic;
signal exec_tas : std_logic;
signal exec_EXT : std_logic;
signal exec_ABCD : std_logic;
signal exec_SBCD : std_logic;
signal exec_MULU : std_logic;
signal exec_DIVU : std_logic;
signal exec_Scc : std_logic;
signal exec_CPMAW : std_logic;
signal set_exec_ADD : std_logic;
signal set_exec_OR : std_logic;
signal set_exec_AND : std_logic;
signal set_exec_EOR : std_logic;
signal set_exec_MOVE : std_logic;
signal set_exec_MOVEQ : std_logic;
signal set_exec_MOVESR: std_logic;
signal set_exec_ADDQ : std_logic;
signal set_exec_CMP : std_logic;
signal set_exec_ROT : std_logic;
signal set_exec_tas : std_logic;
signal set_exec_EXT : std_logic;
signal set_exec_ABCD : std_logic;
signal set_exec_SBCD : std_logic;
signal set_exec_MULU : std_logic;
signal set_exec_DIVU : std_logic;
signal set_exec_Scc : std_logic;
signal set_exec_CPMAW : std_logic;
 
signal condition : std_logic;
signal OP2out_one : std_logic;
signal OP1out_zero : std_logic;
signal ea_to_pc : std_logic;
signal ea_build : std_logic;
signal ea_only : std_logic;
signal get_ea_now : std_logic;
signal source_lowbits : std_logic;
signal dest_hbits : std_logic;
signal rot_rot : std_logic;
signal rot_lsb : std_logic;
signal rot_msb : std_logic;
signal rot_XC : std_logic;
signal set_rot_nop : std_logic;
signal rot_nop : std_logic;
signal rot_out : std_logic_vector(31 downto 0);
signal rot_bits : std_logic_vector(1 downto 0);
signal rot_cnt : std_logic_vector(5 downto 0);
signal set_rot_cnt : std_logic_vector(5 downto 0);
signal movem_busy : std_logic;
signal set_movem_busy : std_logic;
signal movem_addr : std_logic;
signal movem_regaddr : std_logic_vector(3 downto 0);
signal movem_mask : std_logic_vector(15 downto 0);
signal set_get_movem_mask : std_logic;
signal get_movem_mask : std_logic;
signal movem_muxa : std_logic_vector(7 downto 0);
signal movem_muxb : std_logic_vector(3 downto 0);
signal movem_muxc : std_logic_vector(1 downto 0);
signal movem_presub : std_logic;
signal save_memaddr : std_logic;
signal movem_bits : std_logic_vector(4 downto 0);
signal ea_calc_b : std_logic_vector(31 downto 0);
signal set_mem_addsub : std_logic;
signal bit_bits : std_logic_vector(1 downto 0);
signal bit_number_reg : std_logic_vector(4 downto 0);
signal bit_number : std_logic_vector(4 downto 0);
signal exec_Bits : std_logic;
signal bits_out : std_logic_vector(31 downto 0);
signal one_bit_in : std_logic;
signal one_bit_out : std_logic;
signal set_get_bitnumber : std_logic;
signal get_bitnumber : std_logic;
signal mem_byte : std_logic;
signal wait_mem_byte : std_logic;
signal movepl : std_logic;
signal movepw : std_logic;
signal set_movepl : std_logic;
signal set_movepw : std_logic;
signal set_direct_data: std_logic;
signal use_direct_data: std_logic;
signal direct_data : std_logic;
signal set_get_extendedOPC : std_logic;
signal get_extendedOPC: std_logic;
signal setstate_delay : std_logic_vector(1 downto 0);
signal setstate_mux : std_logic_vector(1 downto 0);
signal use_XZFlag : std_logic;
signal use_XFlag : std_logic;
 
signal dummy_a : std_logic_vector(8 downto 0);
signal niba_l : std_logic_vector(5 downto 0);
signal niba_h : std_logic_vector(5 downto 0);
signal niba_lc : std_logic;
signal niba_hc : std_logic;
signal bcda_lc : std_logic;
signal bcda_hc : std_logic;
signal dummy_s : std_logic_vector(8 downto 0);
signal nibs_l : std_logic_vector(5 downto 0);
signal nibs_h : std_logic_vector(5 downto 0);
signal nibs_lc : std_logic;
signal nibs_hc : std_logic;
signal dummy_mulu : std_logic_vector(31 downto 0);
signal dummy_div : std_logic_vector(31 downto 0);
signal dummy_div_sub : std_logic_vector(16 downto 0);
signal dummy_div_over : std_logic_vector(16 downto 0);
signal set_V_Flag : std_logic;
signal OP1sign : std_logic;
signal set_sign : std_logic;
signal sign : std_logic;
signal sign2 : std_logic;
signal muls_msb : std_logic;
signal mulu_reg : std_logic_vector(31 downto 0);
signal div_reg : std_logic_vector(31 downto 0);
signal div_sign : std_logic;
signal div_quot : std_logic_vector(31 downto 0);
signal div_ovl : std_logic;
signal pre_V_Flag : std_logic;
signal set_vectoraddr : std_logic;
signal writeSR : std_logic;
signal trap_illegal : std_logic;
signal trap_priv : std_logic;
signal trap_1010 : std_logic;
signal trap_1111 : std_logic;
signal trap_trap : std_logic;
signal trap_trapv : std_logic;
signal trap_interrupt : std_logic;
signal trapmake : std_logic;
signal trapd : std_logic;
-- signal trap_PC : std_logic_vector(31 downto 0);
signal trap_SR : std_logic_vector(15 downto 0);
signal set_directSR : std_logic;
signal directSR : std_logic;
signal set_directCCR : std_logic;
signal directCCR : std_logic;
signal set_stop : std_logic;
signal stop : std_logic;
signal trap_vector : std_logic_vector(31 downto 0);
signal to_USP : std_logic;
signal from_USP : std_logic;
signal to_SR : std_logic;
signal from_SR : std_logic;
signal illegal_write_mode : std_logic;
signal illegal_read_mode : std_logic;
signal illegal_byteaddr : std_logic;
signal use_SP : std_logic;
 
signal no_Flags : std_logic;
signal IPL_nr : std_logic_vector(2 downto 0);
signal rIPL_nr : std_logic_vector(2 downto 0);
signal interrupt : std_logic;
signal SVmode : std_logic;
signal trap_chk : std_logic;
signal test_delay : std_logic_vector(2 downto 0);
signal set_PCmarker : std_logic;
signal PCmarker : std_logic;
signal set_Z_error : std_logic;
signal Z_error : std_logic;
 
type micro_states is (idle, nop, ld_nn, st_nn, ld_dAn1, ld_dAn2, ld_AnXn1, ld_AnXn2, ld_AnXn3, st_dAn1, st_dAn2,
st_AnXn1, st_AnXn2, st_AnXn3, bra1, bra2, bsr1, bsr2, dbcc1, dbcc2,
movem, andi, op_AxAy, cmpm, link, int1, int2, int3, int4, rte, trap1, trap2, trap3,
movep1, movep2, movep3, movep4, movep5, init1, init2,
mul1, mul2, mul3, mul4, mul5, mul6, mul7, mul8, mul9, mul10, mul11, mul12, mul13, mul14, mul15,
div1, div2, div3, div4, div5, div6, div7, div8, div9, div10, div11, div12, div13, div14, div15 );
signal micro_state : micro_states;
signal next_micro_state : micro_states;
 
type regfile_t is array(0 to 16) of std_logic_vector(15 downto 0);
signal regfile_low : regfile_t;
signal regfile_high : regfile_t;
signal RWindex_A : integer range 0 to 16;
signal RWindex_B : integer range 0 to 16;
 
 
BEGIN
 
-----------------------------------------------------------------------------
-- Registerfile
-----------------------------------------------------------------------------
 
RWindex_A <= conv_integer(rf_dest_addr(4)&(rf_dest_addr(3 downto 0) XOR "1111"));
RWindex_B <= conv_integer(rf_source_addr(4)&(rf_source_addr(3 downto 0) XOR "1111"));
PROCESS (clk)
BEGIN
IF falling_edge(clk) THEN
IF clkena='1' THEN
reg_QA <= regfile_high(RWindex_A) & regfile_low(RWindex_A);
reg_QB <= regfile_high(RWindex_B) & regfile_low(RWindex_B);
END IF;
END IF;
IF rising_edge(clk) THEN
IF clkena='1' THEN
IF Lwrena='1' THEN
regfile_low(RWindex_A) <= registerin(15 downto 0);
END IF;
IF Hwrena='1' THEN
regfile_high(RWindex_A) <= registerin(31 downto 16);
END IF;
END IF;
END IF;
END PROCESS;
 
 
 
address <= TG68_PC when state="00" else X"ffffffff" when state="01" else memaddr;
LDS <= '0' WHEN (datatype/="00" OR state="00" OR memaddr(0)='1') AND state/="01" ELSE '1';
UDS <= '0' WHEN (datatype/="00" OR state="00" OR memaddr(0)='0') AND state/="01" ELSE '1';
state_out <= state;
wr <= '0' WHEN state="11" ELSE '1';
IPL_nr <= NOT IPL;
-----------------------------------------------------------------------------
-- "ALU"
-----------------------------------------------------------------------------
PROCESS (addsub_a, addsub_b, addsub, add_result, c_in)
BEGIN
IF addsub='1' THEN --ADD
add_result <= (('0'&addsub_a&c_in(0))+('0'&addsub_b&c_in(0)));
ELSE --SUB
add_result <= (('0'&addsub_a&'0')-('0'&addsub_b&c_in(0)));
END IF;
addsub_q <= add_result(32 downto 1);
c_in(1) <= add_result(9) XOR addsub_a(8) XOR addsub_b(8);
c_in(2) <= add_result(17) XOR addsub_a(16) XOR addsub_b(16);
c_in(3) <= add_result(33);
addsub_ofl(0) <= (c_in(1) XOR add_result(8) XOR addsub_a(7) XOR addsub_b(7)); --V Byte
addsub_ofl(1) <= (c_in(2) XOR add_result(16) XOR addsub_a(15) XOR addsub_b(15)); --V Word
addsub_ofl(2) <= (c_in(3) XOR add_result(32) XOR addsub_a(31) XOR addsub_b(31)); --V Long
c_out <= c_in(3 downto 1);
END PROCESS;
-----------------------------------------------------------------------------
-- MEM_IO
-----------------------------------------------------------------------------
PROCESS (clk, reset, clkena_in, opcode, rIPL_nr, longread, get_extendedOPC, memaddr, memaddr_a, set_mem_addsub, movem_presub,
movem_busy, state, PCmarker, execOPC, datatype, setdisp, setdispbrief, briefext, setdispbyte, brief,
set_mem_rega, reg_QA, setaddrlong, data_read, decodeOPC, TG68_PC, data_in, long_done, last_data_read, mem_byte,
data_write_tmp, addsub_q, set_vectoraddr, trap_vector, interrupt)
BEGIN
clkena <= clkena_in AND NOT longread AND NOT get_extendedOPC;
IF rising_edge(clk) THEN
IF clkena='1' THEN
trap_vector(31 downto 8) <= (others => '0');
-- IF trap_addr_fault='1' THEN
-- trap_vector(7 downto 0) <= X"08";
-- END IF;
-- IF trap_addr_error='1' THEN
-- trap_vector(7 downto 0) <= X"0C";
-- END IF;
IF trap_illegal='1' THEN
trap_vector(7 downto 0) <= X"10";
END IF;
IF z_error='1' THEN
trap_vector(7 downto 0) <= X"14";
END IF;
-- IF trap_chk='1' THEN
-- trap_vector(7 downto 0) <= X"18";
-- END IF;
IF trap_trapv='1' THEN
trap_vector(7 downto 0) <= X"1C";
END IF;
IF trap_priv='1' THEN
trap_vector(7 downto 0) <= X"20";
END IF;
-- IF trap_trace='1' THEN
-- trap_vector(7 downto 0) <= X"24";
-- END IF;
IF trap_1010='1' THEN
trap_vector(7 downto 0) <= X"28";
END IF;
IF trap_1111='1' THEN
trap_vector(7 downto 0) <= X"2C";
END IF;
IF trap_trap='1' THEN
trap_vector(7 downto 2) <= "10"&opcode(3 downto 0);
END IF;
IF interrupt='1' THEN
trap_vector(7 downto 2) <= "011"&rIPL_nr;
END IF;
END IF;
END IF;
 
memaddr_a(3 downto 0) <= "0000";
memaddr_a(7 downto 4) <= (OTHERS=>memaddr_a(3));
memaddr_a(15 downto 8) <= (OTHERS=>memaddr_a(7));
memaddr_a(31 downto 16) <= (OTHERS=>memaddr_a(15));
IF movem_presub='1' THEN
IF movem_busy='1' OR longread='1' THEN
memaddr_a(3 downto 0) <= "1110";
END IF;
ELSIF state(1)='1' OR (get_extendedOPC='1' AND PCmarker='1') THEN
memaddr_a(1) <= '1';
ELSIF execOPC='1' THEN
IF datatype="10" THEN
memaddr_a(3 downto 0) <= "1100";
ELSE
memaddr_a(3 downto 0) <= "1110";
END IF;
ELSIF setdisp='1' THEN
IF setdispbrief='1' THEN
memaddr_a <= briefext;
ELSIF setdispbyte='1' THEN
memaddr_a(7 downto 0) <= brief(7 downto 0);
ELSE
memaddr_a(15 downto 0) <= brief;
END IF;
END IF;
memaddr_in <= memaddr+memaddr_a;
IF longread='0' THEN
IF set_mem_addsub='1' THEN
memaddr_in <= addsub_q;
ELSIF set_vectoraddr='1' THEN
memaddr_in <= trap_vector;
ELSIF interrupt='1' THEN
memaddr_in <= "1111111111111111111111111111"&rIPL_nr&'0';
ELSIF set_mem_rega='1' THEN
memaddr_in <= reg_QA;
ELSIF setaddrlong='1' AND longread='0' THEN
memaddr_in <= data_read;
ELSIF decodeOPC='1' THEN
memaddr_in <= TG68_PC;
END IF;
END IF;
data_read(15 downto 0) <= data_in;
data_read(31 downto 16) <= (OTHERS=>data_in(15));
IF long_done='1' THEN
data_read(31 downto 16) <= last_data_read;
END IF;
IF mem_byte='1' AND memaddr(0)='0' THEN
data_read(7 downto 0) <= data_in(15 downto 8);
END IF;
IF longread='1' THEN
data_write <= data_write_tmp(31 downto 16);
ELSE
data_write(7 downto 0) <= data_write_tmp(7 downto 0);
IF mem_byte='1' THEN
data_write(15 downto 8) <= data_write_tmp(7 downto 0);
ELSE
data_write(15 downto 8) <= data_write_tmp(15 downto 8);
IF datatype="00" THEN
data_write(7 downto 0) <= data_write_tmp(15 downto 8);
END IF;
END IF;
END IF;
IF reset='0' THEN
longread <= '0';
long_done <= '0';
ELSIF rising_edge(clk) THEN
IF clkena_in='1' THEN
last_data_read <= data_in;
long_done <= longread;
IF get_extendedOPC='0' OR (get_extendedOPC='1' AND PCmarker='1') THEN
memaddr <= memaddr_in;
END IF;
IF get_extendedOPC='0' THEN
IF ((setstate_mux(1)='1' AND datatype="10") OR longreaddirect='1') AND longread='0' AND interrupt='0' THEN
longread <= '1';
ELSE
longread <= '0';
END IF;
END IF;
END IF;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- brief
-----------------------------------------------------------------------------
process (clk, brief, OP1out)
begin
IF brief(11)='1' THEN
OP1outbrief <= OP1out(31 downto 16);
ELSE
OP1outbrief <= (OTHERS=>OP1out(15));
END IF;
IF rising_edge(clk) THEN
IF clkena='1' THEN
briefext <= OP1outbrief&OP1out(15 downto 0);
-- CASE brief(10 downto 9) IS
-- WHEN "00" => briefext <= OP1outbrief&OP1out(15 downto 0);
-- WHEN "01" => briefext <= OP1outbrief(14 downto 0)&OP1out(15 downto 0)&'0';
-- WHEN "10" => briefext <= OP1outbrief(13 downto 0)&OP1out(15 downto 0)&"00";
-- WHEN "11" => briefext <= OP1outbrief(12 downto 0)&OP1out(15 downto 0)&"000";
-- END CASE;
end if;
end if;
end process;
 
-----------------------------------------------------------------------------
-- PC Calc + fetch opcode
-----------------------------------------------------------------------------
process (clk, reset, opcode, TG68_PC, TG68_PC_dec, TG68_PC_br8, TG68_PC_brw, PC_dataa, PC_datab, execOPC, last_data_read, get_extendedOPC,
setstate_delay, setstate)
begin
PC_dataa <= TG68_PC;
PC_datab(2 downto 0) <= "010";
PC_datab(7 downto 3) <= (others => PC_datab(2));
PC_datab(15 downto 8) <= (others => PC_datab(7));
PC_datab(31 downto 16) <= (others => PC_datab(15));
IF execOPC='0' THEN
IF TG68_PC_br8='1' THEN
PC_datab(7 downto 0) <= opcode(7 downto 0);
END IF;
IF TG68_PC_dec(1)='1' THEN
PC_datab(2) <= '1';
END IF;
IF TG68_PC_brw = '1' THEN
PC_datab(15 downto 0) <= last_data_read(15 downto 0);
END IF;
END IF;
TG68_PC_add <= PC_dataa+PC_datab;
IF get_extendedOPC='1' THEN
setstate_mux <= setstate_delay;
ELSE
setstate_mux <= setstate;
END IF;
IF reset = '0' THEN
opcode(15 downto 12) <= X"7"; --moveq
opcode(8 downto 6) <= "010"; --long
TG68_PC <= (others =>'0');
state <= "01";
decodeOPC <= '0';
fetchOPC <= '0';
endOPC <= '0';
interrupt <= '0';
trap_interrupt <= '1';
execOPC <= '0';
getbrief <= '0';
TG68_PC_dec <= "00";
directPC <= '0';
directSR <= '0';
directCCR <= '0';
stop <= '0';
exec_ADD <= '0';
exec_OR <= '0';
exec_AND <= '0';
exec_EOR <= '0';
exec_MOVE <= '0';
exec_MOVEQ <= '0';
exec_MOVESR <= '0';
exec_ADDQ <= '0';
exec_CMP <= '0';
exec_ROT <= '0';
exec_EXT <= '0';
exec_ABCD <= '0';
exec_SBCD <= '0';
exec_MULU <= '0';
exec_DIVU <= '0';
exec_Scc <= '0';
exec_CPMAW <= '0';
mem_byte <= '0';
rot_cnt <="000001";
rot_nop <= '0';
get_extendedOPC <= '0';
get_bitnumber <= '0';
get_movem_mask <= '0';
movepl <= '0';
movepw <= '0';
test_delay <= "000";
PCmarker <= '0';
ELSIF rising_edge(clk) THEN
IF clkena_in='1' THEN
get_extendedOPC <= set_get_extendedOPC;
get_bitnumber <= set_get_bitnumber;
get_movem_mask <= set_get_movem_mask;
setstate_delay <= setstate;
TG68_PC_dec <= TG68_PC_dec(0)&set_TG68_PC_dec;
IF directPC='1' AND clkena='1' THEN
TG68_PC <= data_read;
ELSIF ea_to_pc='1' AND longread='0' THEN
TG68_PC <= memaddr_in;
ELSIF (state ="00" AND TG68_PC_nop='0') OR TG68_PC_br8='1' OR TG68_PC_brw='1' OR TG68_PC_dec(1)='1' THEN
TG68_PC <= TG68_PC_add;
END IF;
IF get_bitnumber='1' THEN
bit_number_reg <= data_read(4 downto 0);
END IF;
 
IF clkena='1' OR get_extendedOPC='1' THEN
IF set_get_extendedOPC='1' THEN
state <= "00";
ELSIF get_extendedOPC='1' THEN
state <= setstate_mux;
ELSIF fetchOPC='1' OR (state="10" AND write_back='1' AND setstate/="10") OR set_rot_cnt/="000001" OR stop='1' THEN
state <= "01"; --decode cycle, execute cycle
ELSE
state <= setstate_mux;
END IF;
IF setstate_mux(1)='1' AND datatype="00" AND set_get_extendedOPC='0' AND wait_mem_byte='0' THEN
mem_byte <= '1';
ELSE
mem_byte <= '0';
END IF;
END IF;
END IF;
IF clkena='1' THEN
exec_ADD <= '0';
exec_OR <= '0';
exec_AND <= '0';
exec_EOR <= '0';
exec_MOVE <= '0';
exec_MOVEQ <= '0';
exec_MOVESR <= '0';
exec_ADDQ <= '0';
exec_CMP <= '0';
exec_ROT <= '0';
exec_ABCD <= '0';
exec_SBCD <= '0';
fetchOPC <= '0';
exec_CPMAW <= '0';
endOPC <= '0';
interrupt <= '0';
execOPC <= '0';
exec_EXT <= '0';
exec_Scc <= '0';
rot_nop <= '0';
decodeOPC <= fetchOPC;
directPC <= set_directPC;
directSR <= set_directSR;
directCCR <= set_directCCR;
exec_MULU <= set_exec_MULU;
exec_DIVU <= set_exec_DIVU;
movepl <= '0';
movepw <= '0';
stop <= set_stop OR (stop AND NOT interrupt);
IF set_PCmarker='1' THEN
PCmarker <= '1';
ELSIF (state="10" AND longread='0') OR (ea_only='1' AND get_ea_now='1') THEN
PCmarker <= '0';
END IF;
IF (decodeOPC OR execOPC)='1' THEN
rot_cnt <= set_rot_cnt;
END IF;
IF next_micro_state=idle AND setstate_mux="00" AND (setnextpass='0' OR ea_only='1') AND endOPC='0' AND movem_busy='0' AND set_movem_busy='0' AND set_get_bitnumber='0' THEN
nextpass <= '0';
IF (exec_write_back='0' OR state="11") AND set_rot_cnt="000001" THEN
endOPC <= '1';
IF Flags(10 downto 8)<IPL_nr OR IPL_nr="111" THEN
interrupt <= '1';
rIPL_nr <= IPL_nr;
ELSE
IF stop='0' THEN
fetchOPC <= '1';
END IF;
END IF;
END IF;
IF exec_write_back='0' OR state/="11" THEN
IF stop='0' THEN
execOPC <= '1';
END IF;
exec_ADD <= set_exec_ADD;
exec_OR <= set_exec_OR;
exec_AND <= set_exec_AND;
exec_EOR <= set_exec_EOR;
exec_MOVE <= set_exec_MOVE;
exec_MOVEQ <= set_exec_MOVEQ;
exec_MOVESR <= set_exec_MOVESR;
exec_ADDQ <= set_exec_ADDQ;
exec_CMP <= set_exec_CMP;
exec_ROT <= set_exec_ROT;
exec_tas <= set_exec_tas;
exec_EXT <= set_exec_EXT;
exec_ABCD <= set_exec_ABCD;
exec_SBCD <= set_exec_SBCD;
exec_Scc <= set_exec_Scc;
exec_CPMAW <= set_exec_CPMAW;
rot_nop <= set_rot_nop;
 
END IF;
ELSE
IF endOPC='0' AND (setnextpass='1' OR (regdirectsource='1' AND decodeOPC='1')) THEN
nextpass <= '1';
END IF;
END IF;
IF interrupt='1' THEN
opcode(15 downto 12) <= X"7"; --moveq
opcode(8 downto 6) <= "010"; --long
-- trap_PC <= TG68_PC;
trap_interrupt <= '1';
END IF;
IF fetchOPC='1' THEN
trap_interrupt <= '0';
IF (test_IPL='1' AND (Flags(10 downto 8)<IPL_nr OR IPL_nr="111")) OR to_SR='1' THEN
 
opcode <= X"60FE";
IF to_SR='0' THEN
test_delay <= "001";
END IF;
ELSE
opcode <= data_read(15 downto 0);
END IF;
getbrief <= '0';
-- trap_PC <= TG68_PC;
ELSE
test_delay <= test_delay(1 downto 0)&'0';
getbrief <= setgetbrief;
movepl <= set_movepl;
movepw <= set_movepw;
END IF;
IF decodeOPC='1' OR interrupt='1' THEN
trap_SR <= Flags;
END IF;
 
IF getbrief='1' THEN
brief <= data_read(15 downto 0);
END IF;
end if;
end if;
end process;
 
-----------------------------------------------------------------------------
-- handle EA_data, data_write_tmp
-----------------------------------------------------------------------------
PROCESS (clk, reset, opcode)
BEGIN
IF reset = '0' THEN
set_store_in_tmp <='0';
exec_DIRECT <= '0';
exec_write_back <= '0';
direct_data <= '0';
use_direct_data <= '0';
Z_error <= '0';
ELSIF rising_edge(clk) THEN
IF clkena='1' THEN
direct_data <= '0';
IF endOPC='1' THEN
set_store_in_tmp <='0';
exec_DIRECT <= '0';
exec_write_back <= '0';
use_direct_data <= '0';
Z_error <= '0';
ELSE
IF set_Z_error='1' THEN
Z_error <= '1';
END IF;
exec_DIRECT <= set_exec_MOVE;
IF setstate_mux="10" AND write_back='1' THEN
exec_write_back <= '1';
END IF;
END IF;
IF set_direct_data='1' THEN
direct_data <= '1';
use_direct_data <= '1';
END IF;
IF set_exec_MOVE='1' AND state="11" THEN
use_direct_data <= '1';
END IF;
 
IF (exec_DIRECT='1' AND state="00" AND getbrief='0' AND endOPC='0') OR state="10" THEN
set_store_in_tmp <= '1';
ea_data <= data_read;
END IF;
IF writePC_add='1' THEN
data_write_tmp <= TG68_PC_add;
 
data_write_tmp <= TG68_PC;
 
data_write_tmp <= registerin(31 downto 8)&(registerin(7)OR exec_tas)&registerin(6 downto 0);
ELSIF (exec_DIRECT='1' AND state="10") OR direct_data='1' THEN
data_write_tmp <= data_read;
IF movepl='1' THEN
data_write_tmp(31 downto 8) <= data_write_tmp(23 downto 0);
END IF;
ELSIF (movem_busy='1' AND datatype="10" AND movem_presub='1') OR movepl='1' THEN
data_write_tmp <= OP2out(15 downto 0)&OP2out(31 downto 16);
ELSIF (NOT trapmake AND decodeOPC)='1' OR movem_busy='1' OR movepw='1' THEN
data_write_tmp <= OP2out;
ELSIF writeSR='1'THEN
data_write_tmp(15 downto 0) <= trap_SR(15 downto 8)& Flags(7 downto 0);
END IF;
END IF;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- set dest regaddr
-----------------------------------------------------------------------------
PROCESS (opcode, rf_dest_addr_tmp, to_USP, Flags, trapmake, movem_addr, movem_presub, movem_regaddr, setbriefext, brief, setstackaddr, dest_hbits, dest_areg, data_is_source)
BEGIN
rf_dest_addr <= rf_dest_addr_tmp;
IF rf_dest_addr_tmp(3 downto 0)="1111" AND to_USP='0' THEN
rf_dest_addr(4) <= Flags(13) OR trapmake;
END IF;
IF movem_addr='1' THEN
IF movem_presub='1' THEN
rf_dest_addr_tmp <= "000"&(movem_regaddr XOR "1111");
ELSE
rf_dest_addr_tmp <= "000"&movem_regaddr;
END IF;
ELSIF setbriefext='1' THEN
rf_dest_addr_tmp <= ("000"&brief(15 downto 12));
ELSIF setstackaddr='1' THEN
rf_dest_addr_tmp <= "0001111";
ELSIF dest_hbits='1' THEN
rf_dest_addr_tmp <= "000"&dest_areg&opcode(11 downto 9);
ELSE
IF opcode(5 downto 3)="000" OR data_is_source='1' THEN
rf_dest_addr_tmp <= "000"&dest_areg&opcode(2 downto 0);
ELSE
rf_dest_addr_tmp <= "0001"&opcode(2 downto 0);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- set OP1
-----------------------------------------------------------------------------
PROCESS (reg_QA, OP1out_zero, from_SR, Flags, ea_data_OP1, set_store_in_tmp, ea_data)
BEGIN
OP1out <= reg_QA;
IF OP1out_zero='1' THEN
OP1out <= (OTHERS => '0');
ELSIF from_SR='1' THEN
OP1out(15 downto 0) <= Flags;
ELSIF ea_data_OP1='1' AND set_store_in_tmp='1' THEN
OP1out <= ea_data;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- set source regaddr
-----------------------------------------------------------------------------
PROCESS (opcode, Flags, movem_addr, movem_presub, movem_regaddr, source_lowbits, source_areg, from_USP, rf_source_addr_tmp)
BEGIN
rf_source_addr <= rf_source_addr_tmp;
IF rf_source_addr_tmp(3 downto 0)="1111" AND from_USP='0' THEN
rf_source_addr(4) <= Flags(13);
END IF;
IF movem_addr='1' THEN
IF movem_presub='1' THEN
rf_source_addr_tmp <= "000"&(movem_regaddr XOR "1111");
ELSE
rf_source_addr_tmp <= "000"&movem_regaddr;
END IF;
ELSIF from_USP='1' THEN
rf_source_addr_tmp <= "0001111";
ELSIF source_lowbits='1' THEN
rf_source_addr_tmp <= "000"&source_areg&opcode(2 downto 0);
ELSE
rf_source_addr_tmp <= "000"&source_areg&opcode(11 downto 9);
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- set OP2
-----------------------------------------------------------------------------
PROCESS (OP2out, reg_QB, opcode, datatype, OP2out_one, exec_EXT, exec_MOVEQ, EXEC_ADDQ, use_direct_data, data_write_tmp,
ea_data_OP1, set_store_in_tmp, ea_data, movepl)
BEGIN
OP2out(15 downto 0) <= reg_QB(15 downto 0);
OP2out(31 downto 16) <= (OTHERS => OP2out(15));
IF OP2out_one='1' THEN
OP2out(15 downto 0) <= "1111111111111111";
ELSIF exec_EXT='1' THEN
IF opcode(6)='0' THEN --ext.w
OP2out(15 downto 8) <= (OTHERS => OP2out(7));
END IF;
ELSIF use_direct_data='1' THEN
OP2out <= data_write_tmp;
ELSIF ea_data_OP1='0' AND set_store_in_tmp='1' THEN
OP2out <= ea_data;
ELSIF exec_MOVEQ='1' THEN
OP2out(7 downto 0) <= opcode(7 downto 0);
OP2out(15 downto 8) <= (OTHERS => opcode(7));
ELSIF exec_ADDQ='1' THEN
OP2out(2 downto 0) <= opcode(11 downto 9);
IF opcode(11 downto 9)="000" THEN
OP2out(3) <='1';
ELSE
OP2out(3) <='0';
END IF;
OP2out(15 downto 4) <= (OTHERS => '0');
ELSIF datatype="10" OR movepl='1' THEN
OP2out(31 downto 16) <= reg_QB(31 downto 16);
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- addsub
-----------------------------------------------------------------------------
PROCESS (OP1out, OP2out, presub, postadd, execOPC, OP2out_one, datatype, use_SP, use_XZFlag, use_XFlag, Flags, setaddsub)
BEGIN
addsub_a <= OP1out;
addsub_b <= OP2out;
addsub <= NOT presub;
c_in(0) <='0';
IF execOPC='0' AND OP2out_one='0' THEN
IF datatype="00" AND use_SP='0' THEN
addsub_b <= "00000000000000000000000000000001";
ELSIF datatype="10" AND (presub OR postadd)='1' THEN
addsub_b <= "00000000000000000000000000000100";
ELSE
addsub_b <= "00000000000000000000000000000010";
END IF;
ELSE
IF (use_XZFlag='1' OR use_XFlag='1') AND Flags(4)='1' THEN
c_in(0) <= '1';
END IF;
addsub <= setaddsub;
END IF;
END PROCESS;
 
-----------------------------------------------------------------------------
-- Write Reg
-----------------------------------------------------------------------------
PROCESS (clkena, OP1in, datatype, presub, postadd, endOPC, regwrena, state, execOPC, last_data_read, movem_addr, rf_dest_addr, reg_QA)
BEGIN
Lwrena <= '0';
Hwrena <= '0';
registerin <= OP1in;
IF (presub='1' OR postadd='1') AND endOPC='0' THEN -- -(An)+
Hwrena <= '1';
Lwrena <= '1';
ELSIF Regwrena='1' THEN --read (mem)
Lwrena <= '1';
CASE datatype IS
WHEN "00" => --BYTE
registerin(15 downto 8) <= reg_QA(15 downto 8);
WHEN "01" => --WORD
IF rf_dest_addr(3)='1' OR movem_addr='1' THEN
Hwrena <='1';
END IF;
WHEN OTHERS => --LONG
Hwrena <= '1';
END CASE;
END IF;
END PROCESS;
------------------------------------------------------------------------------
--ALU
------------------------------------------------------------------------------
PROCESS (opcode, OP1in, OP1out, OP2out, datatype, c_out, exec_ABCD, exec_SBCD, exec_CPMAW, exec_MOVESR, bits_out, Flags, flag_z, use_XZFlag, addsub_ofl,
dummy_s, dummy_a, niba_hc, niba_h, niba_l, niba_lc, nibs_hc, nibs_h, nibs_l, nibs_lc, addsub_q, movem_addr, data_read, exec_MULU, exec_DIVU, exec_OR,
exec_AND, exec_Scc, exec_EOR, exec_MOVE, exec_exg, exec_ROT, execOPC, exec_swap, exec_Bits, rot_out, dummy_mulu, dummy_div, save_memaddr, memaddr,
memaddr_in, ea_only, get_ea_now)
BEGIN
--BCD_ARITH-------------------------------------------------------------------
--ADC
dummy_a <= niba_hc&(niba_h(4 downto 1)+('0',niba_hc,niba_hc,'0'))&(niba_l(4 downto 1)+('0',niba_lc,niba_lc,'0'));
niba_l <= ('0'&OP1out(3 downto 0)&'1') + ('0'&OP2out(3 downto 0)&Flags(4));
niba_lc <= niba_l(5) OR (niba_l(4) AND niba_l(3)) OR (niba_l(4) AND niba_l(2));
 
niba_h <= ('0'&OP1out(7 downto 4)&'1') + ('0'&OP2out(7 downto 4)&niba_lc);
niba_hc <= niba_h(5) OR (niba_h(4) AND niba_h(3)) OR (niba_h(4) AND niba_h(2));
--SBC
dummy_s <= nibs_hc&(nibs_h(4 downto 1)-('0',nibs_hc,nibs_hc,'0'))&(nibs_l(4 downto 1)-('0',nibs_lc,nibs_lc,'0'));
nibs_l <= ('0'&OP1out(3 downto 0)&'0') - ('0'&OP2out(3 downto 0)&Flags(4));
nibs_lc <= nibs_l(5);
 
nibs_h <= ('0'&OP1out(7 downto 4)&'0') - ('0'&OP2out(7 downto 4)&nibs_lc);
nibs_hc <= nibs_h(5);
------------------------------------------------------------------------------
flag_z <= "000";
 
OP1in <= addsub_q;
IF movem_addr='1' THEN
OP1in <= data_read;
ELSIF exec_ABCD='1' THEN
OP1in(7 downto 0) <= dummy_a(7 downto 0);
ELSIF exec_SBCD='1' THEN
OP1in(7 downto 0) <= dummy_s(7 downto 0);
ELSIF exec_MULU='1' THEN
OP1in <= dummy_mulu;
ELSIF exec_DIVU='1' AND execOPC='1' THEN
OP1in <= dummy_div;
ELSIF exec_OR='1' THEN
OP1in <= OP2out OR OP1out;
ELSIF exec_AND='1' OR exec_Scc='1' THEN
OP1in <= OP2out AND OP1out;
ELSIF exec_EOR='1' THEN
OP1in <= OP2out XOR OP1out;
ELSIF exec_MOVE='1' OR exec_exg='1' THEN
OP1in <= OP2out;
ELSIF exec_ROT='1' THEN
OP1in <= rot_out;
ELSIF save_memaddr='1' THEN
OP1in <= memaddr;
ELSIF get_ea_now='1' AND ea_only='1' THEN
OP1in <= memaddr_in;
ELSIF exec_swap='1' THEN
OP1in <= OP1out(15 downto 0)& OP1out(31 downto 16);
ELSIF exec_bits='1' THEN
OP1in <= bits_out;
ELSIF exec_MOVESR='1' THEN
OP1in(15 downto 0) <= Flags;
END IF;
IF use_XZFlag='1' AND flags(2)='0' THEN
flag_z <= "000";
ELSIF OP1in(7 downto 0)="00000000" THEN
flag_z(0) <= '1';
IF OP1in(15 downto 8)="00000000" THEN
flag_z(1) <= '1';
IF OP1in(31 downto 16)="0000000000000000" THEN
flag_z(2) <= '1';
END IF;
END IF;
END IF;
-- --Flags NZVC
IF datatype="00" THEN --Byte
set_flags <= OP1IN(7)&flag_z(0)&addsub_ofl(0)&c_out(0);
IF exec_ABCD='1' THEN
set_flags(0) <= dummy_a(8);
ELSIF exec_SBCD='1' THEN
set_flags(0) <= dummy_s(8);
END IF;
ELSIF datatype="10" OR exec_CPMAW='1' THEN --Long
set_flags <= OP1IN(31)&flag_z(2)&addsub_ofl(2)&c_out(2);
ELSE --Word
set_flags <= OP1IN(15)&flag_z(1)&addsub_ofl(1)&c_out(1);
END IF;
END PROCESS;
------------------------------------------------------------------------------
--Flags
------------------------------------------------------------------------------
PROCESS (clk, reset, opcode)
BEGIN
IF reset='0' THEN
Flags(13) <= '1';
SVmode <= '1';
Flags(10 downto 8) <= "111";
ELSIF rising_edge(clk) THEN
IF clkena = '1' THEN
IF directSR='1' THEN
Flags <= data_read(15 downto 0);
END IF;
IF directCCR='1' THEN
Flags(7 downto 0) <= data_read(7 downto 0);
END IF;
IF interrupt='1' THEN
Flags(10 downto 8) <=rIPL_nr;
SVmode <= '1';
END IF;
IF writeSR='1' OR interrupt='1' THEN
Flags(13) <='1';
END IF;
IF endOPC='1' AND to_SR='0' THEN
SVmode <= Flags(13);
END IF;
IF execOPC='1' AND to_SR='1' THEN
Flags(7 downto 0) <= OP1in(7 downto 0); --CCR
IF datatype="01" AND (opcode(14)='0' OR opcode(9)='1') THEN --move to CCR wird als word gespeichert
Flags(15 downto 8) <= OP1in(15 downto 8); --SR
SVmode <= OP1in(13);
END IF;
ELSIF Z_error='1' THEN
IF opcode(8)='0' THEN
Flags(3 downto 0) <= "1000";
ELSE
Flags(3 downto 0) <= "0100";
END IF;
ELSIF no_Flags='0' AND trapmake='0' THEN
IF exec_ADD='1' THEN
Flags(4) <= set_flags(0);
ELSIF exec_ROT='1' AND rot_bits/="11" AND rot_nop='0' THEN
Flags(4) <= rot_XC;
END IF;
IF (exec_ADD OR exec_CMP)='1' THEN
Flags(3 downto 0) <= set_flags;
ELSIF decodeOPC='1' and set_exec_ROT='1' THEN
Flags(1) <= '0';
ELSIF exec_DIVU='1' THEN
IF set_V_Flag='1' THEN
Flags(3 downto 0) <= "1010";
ELSE
Flags(3 downto 0) <= OP1IN(15)&flag_z(1)&"00";
END IF;
ELSIF exec_OR='1' OR exec_AND='1' OR exec_EOR='1' OR exec_MOVE='1' OR exec_swap='1' OR exec_MULU='1' THEN
Flags(3 downto 0) <= set_flags(3 downto 2)&"00";
ELSIF exec_ROT='1' THEN
Flags(3 downto 2) <= set_flags(3 downto 2);
Flags(0) <= rot_XC;
IF rot_bits="00" THEN --ASL/ASR
Flags(1) <= ((set_flags(3) XOR rot_rot) OR Flags(1));
END IF;
ELSIF exec_bits='1' THEN
Flags(2) <= NOT one_bit_in;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- execute opcode
-----------------------------------------------------------------------------
PROCESS (clk, reset, OP2out, opcode, fetchOPC, decodeOPC, execOPC, endOPC, nextpass, condition, set_V_flag, trapmake, trapd, interrupt, trap_interrupt,
Z_error, c_in, rot_cnt, one_bit_in, bit_number_reg, bit_number, ea_only, get_ea_now, ea_build, datatype, exec_write_back, get_extendedOPC,
Flags, SVmode, movem_addr, movem_busy, getbrief, set_exec_AND, set_exec_OR, set_exec_EOR, TG68_PC_dec, c_out, OP1out, micro_state)
BEGIN
TG68_PC_br8 <= '0';
TG68_PC_brw <= '0';
TG68_PC_nop <= '0';
setstate <= "00";
Regwrena <= '0';
postadd <= '0';
presub <= '0';
movem_presub <= '0';
setaddsub <= '1';
setaddrlong <= '0';
setnextpass <= '0';
regdirectsource <= '0';
setdisp <= '0';
setdispbyte <= '0';
setdispbrief <= '0';
setbriefext <= '0';
setgetbrief <= '0';
longreaddirect <= '0';
dest_areg <= '0';
source_areg <= '0';
data_is_source <= '0';
write_back <= '0';
setstackaddr <= '0';
writePC <= '0';
writePC_add <= '0';
set_TG68_PC_dec <= '0';
set_directPC <= '0';
set_exec_ADD <= '0';
set_exec_OR <= '0';
set_exec_AND <= '0';
set_exec_EOR <= '0';
set_exec_MOVE <= '0';
set_exec_MOVEQ <= '0';
set_exec_MOVESR <= '0';
set_exec_ADDQ <= '0';
set_exec_CMP <= '0';
set_exec_ROT <= '0';
set_exec_EXT <= '0';
set_exec_CPMAW <= '0';
OP2out_one <= '0';
ea_to_pc <= '0';
ea_build <= '0';
get_ea_now <= '0';
rot_bits <= "XX";
set_rot_nop <= '0';
set_rot_cnt <= "000001";
set_movem_busy <= '0';
set_get_movem_mask <= '0';
save_memaddr <= '0';
set_mem_addsub <= '0';
exec_exg <= '0';
exec_swap <= '0';
exec_Bits <= '0';
set_get_bitnumber <= '0';
dest_hbits <= '0';
source_lowbits <= '0';
set_mem_rega <= '0';
ea_data_OP1 <= '0';
ea_only <= '0';
set_direct_data <= '0';
set_get_extendedOPC <= '0';
set_exec_tas <= '0';
OP1out_zero <= '0';
use_XZFlag <= '0';
use_XFlag <= '0';
set_exec_ABCD <= '0';
set_exec_SBCD <= '0';
set_exec_MULU <= '0';
set_exec_DIVU <= '0';
set_exec_Scc <= '0';
trap_illegal <='0';
trap_priv <='0';
trap_1010 <='0';
trap_1111 <='0';
trap_trap <='0';
trap_trapv <= '0';
trapmake <='0';
set_vectoraddr <='0';
writeSR <= '0';
set_directSR <= '0';
set_directCCR <= '0';
set_stop <= '0';
from_SR <= '0';
to_SR <= '0';
from_USP <= '0';
to_USP <= '0';
illegal_write_mode <= '0';
illegal_read_mode <= '0';
illegal_byteaddr <= '0';
no_Flags <= '0';
set_PCmarker <= '0';
use_SP <= '0';
set_Z_error <= '0';
wait_mem_byte <= '0';
set_movepl <= '0';
set_movepw <= '0';
 
trap_chk <= '0';
next_micro_state <= idle;
 
------------------------------------------------------------------------------
--Sourcepass
------------------------------------------------------------------------------
IF ea_only='0' AND get_ea_now='1' THEN
setstate <= "10";
END IF;
IF ea_build='1' THEN
CASE opcode(5 downto 3) IS --source
WHEN "010"|"011"|"100" => -- -(An)+
get_ea_now <='1';
setnextpass <= '1';
IF opcode(4)='1' THEN
set_mem_rega <= '1';
ELSE
set_mem_addsub <= '1';
END IF;
IF opcode(3)='1' THEN --(An)+
postadd <= '1';
IF opcode(2 downto 0)="111" THEN
use_SP <= '1';
END IF;
END IF;
IF opcode(5)='1' THEN -- -(An)
presub <= '1';
IF opcode(2 downto 0)="111" THEN
use_SP <= '1';
END IF;
END IF;
IF opcode(4 downto 3)/="10" THEN
regwrena <= '1';
END IF;
WHEN "101" => --(d16,An)
next_micro_state <= ld_dAn1;
setgetbrief <='1';
set_mem_regA <= '1';
WHEN "110" => --(d8,An,Xn)
next_micro_state <= ld_AnXn1;
setgetbrief <='1';
set_mem_regA <= '1';
WHEN "111" =>
CASE opcode(2 downto 0) IS
WHEN "000" => --(xxxx).w
next_micro_state <= ld_nn;
WHEN "001" => --(xxxx).l
longreaddirect <= '1';
next_micro_state <= ld_nn;
WHEN "010" => --(d16,PC)
next_micro_state <= ld_dAn1;
setgetbrief <= '1';
set_PCmarker <= '1';
WHEN "011" => --(d8,PC,Xn)
next_micro_state <= ld_AnXn1;
setgetbrief <= '1';
set_PCmarker <= '1';
WHEN "100" => --#data
setnextpass <= '1';
set_direct_data <= '1';
IF datatype="10" THEN
longreaddirect <= '1';
END IF;
WHEN OTHERS =>
END CASE;
WHEN OTHERS =>
END CASE;
END IF;
------------------------------------------------------------------------------
--prepere opcode
------------------------------------------------------------------------------
CASE opcode(7 downto 6) IS
WHEN "00" => datatype <= "00"; --Byte
WHEN "01" => datatype <= "01"; --Word
WHEN OTHERS => datatype <= "10"; --Long
END CASE;
IF execOPC='1' AND endOPC='0' AND exec_write_back='1' THEN
setstate <="11";
END IF;
------------------------------------------------------------------------------
--test illegal mode
------------------------------------------------------------------------------
IF (opcode(5 downto 3)="111" AND opcode(2 downto 1)/="00") OR (opcode(5 downto 3)="001" AND datatype="00") THEN
illegal_write_mode <= '1';
END IF;
IF (opcode(5 downto 2)="1111" AND opcode(1 downto 0)/="00") OR (opcode(5 downto 3)="001" AND datatype="00") THEN
illegal_read_mode <= '1';
END IF;
IF opcode(5 downto 3)="001" AND datatype="00" THEN
illegal_byteaddr <= '1';
END IF;
 
CASE opcode(15 downto 12) IS
-- 0000 ----------------------------------------------------------------------------
WHEN "0000" =>
IF opcode(8)='1' AND opcode(5 downto 3)="001" THEN --movep
datatype <= "00"; --Byte
use_SP <= '1';
no_Flags <='1';
IF opcode(7)='0' THEN
set_exec_move <= '1';
set_movepl <= '1';
END IF;
IF decodeOPC='1' THEN
IF opcode(7)='0' THEN
set_direct_data <= '1';
END IF;
next_micro_state <= movep1;
setgetbrief <='1';
set_mem_regA <= '1';
END IF;
IF opcode(7)='0' AND endOPC='1' THEN
IF opcode(6)='1' THEN
datatype <= "10"; --Long
ELSE
datatype <= "01"; --Word
END IF;
dest_hbits <='1';
regwrena <= '1';
END IF;
ELSE
IF opcode(8)='1' OR opcode(11 downto 8)="1000" THEN --Bits
IF execOPC='1' AND get_extendedOPC='0' THEN
IF opcode(7 downto 6)/="00" AND endOPC='1' THEN
regwrena <= '1';
END IF;
exec_Bits <= '1';
ea_data_OP1 <= '1';
END IF;
-- IF get_extendedOPC='1' THEN
-- datatype <= "01"; --Word
-- ELS
IF opcode(5 downto 4)="00" THEN
datatype <= "10"; --Long
ELSE
datatype <= "00"; --Byte
IF opcode(7 downto 6)/="00" THEN
write_back <= '1';
END IF;
END IF;
IF decodeOPC='1' THEN
ea_build <= '1';
IF opcode(8)='0' THEN
IF opcode(5 downto 4)/="00" THEN --Dn, An
set_get_extendedOPC <= '1';
END IF;
set_get_bitnumber <= '1';
END IF;
END IF;
ELSE --andi, ...xxxi
IF opcode(11 downto 8)="0000" THEN --ORI
set_exec_OR <= '1';
END IF;
IF opcode(11 downto 8)="0010" THEN --ANDI
set_exec_AND <= '1';
END IF;
IF opcode(11 downto 8)="0100" OR opcode(11 downto 8)="0110" THEN --SUBI, ADDI
set_exec_ADD <= '1';
END IF;
IF opcode(11 downto 8)="1010" THEN --EORI
set_exec_EOR <= '1';
END IF;
IF opcode(11 downto 8)="1100" THEN --CMPI
set_exec_CMP <= '1';
ELSIF trapmake='0' THEN
write_back <= '1';
END IF;
IF opcode(7)='0' AND opcode(5 downto 0)="111100" AND (set_exec_AND OR set_exec_OR OR set_exec_EOR)='1' THEN --SR
-- IF opcode(7)='0' AND opcode(5 downto 0)="111100" AND (opcode(11 downto 8)="0010" OR opcode(11 downto 8)="0000" OR opcode(11 downto 8)="1010") THEN --SR
IF SVmode='0' AND opcode(6)='1' THEN --SR
trap_priv <= '1';
trapmake <= '1';
ELSE
from_SR <= '1';
to_SR <= '1';
IF decodeOPC='1' THEN
setnextpass <= '1';
set_direct_data <= '1';
END IF;
END IF;
ELSE
IF decodeOPC='1' THEN
IF opcode(11 downto 8)="0010" OR opcode(11 downto 8)="0000" OR opcode(11 downto 8)="0100" --ANDI, ORI, SUBI
OR opcode(11 downto 8)="0110" OR opcode(11 downto 8)="1010" OR opcode(11 downto 8)="1100" THEN --ADDI, EORI, CMPI
-- IF (set_exec_AND OR set_exec_OR OR set_exec_ADD --ANDI, ORI, SUBI
-- OR set_exec_EOR OR set_exec_CMP)='1' THEN --ADDI, EORI, CMPI
next_micro_state <= andi;
set_direct_data <= '1';
IF datatype="10" THEN
longreaddirect <= '1';
END IF;
END IF;
END IF;
IF execOPC='1' THEN
ea_data_OP1 <= '1';
IF opcode(11 downto 8)/="1100" THEN --CMPI
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
IF opcode(11 downto 8)="1100" OR opcode(11 downto 8)="0100" THEN --CMPI, SUBI
setaddsub <= '0';
END IF;
END IF;
END IF;
END IF;
END IF;
-- 0001, 0010, 0011 -----------------------------------------------------------------
WHEN "0001"|"0010"|"0011" => --move.b, move.l, move.w
set_exec_MOVE <= '1';
IF opcode(8 downto 6)="001" THEN
no_Flags <= '1';
END IF;
IF opcode(5 downto 4)="00" THEN --Dn, An
regdirectsource <= '1';
END IF;
CASE opcode(13 downto 12) IS
WHEN "01" => datatype <= "00"; --Byte
WHEN "10" => datatype <= "10"; --Long
WHEN OTHERS => datatype <= "01"; --Word
END CASE;
source_lowbits <= '1'; -- Dn=> An=>
IF opcode(3)='1' THEN
source_areg <= '1';
END IF;
IF getbrief='1' AND nextpass='1' THEN -- =>(d16,An) =>(d8,An,Xn)
set_mem_rega <= '1';
END IF;
IF execOPC='1' AND opcode(8 downto 7)="00" THEN
Regwrena <= '1';
END IF;
IF nextpass='1' OR execOPC='1' OR opcode(5 downto 4)="00" THEN
dest_hbits <= '1';
IF opcode(8 downto 6)/="000" THEN
dest_areg <= '1';
END IF;
END IF;
 
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF micro_state=idle AND (nextpass='1' OR (opcode(5 downto 4)="00" AND decodeOPC='1')) THEN
CASE opcode(8 downto 6) IS --destination
-- WHEN "000" => --Dn
-- WHEN "001" => --An
WHEN "010"|"011"|"100" => --destination -(an)+
IF opcode(7)='1' THEN
set_mem_rega <= '1';
ELSE
set_mem_addsub <= '1';
END IF;
IF opcode(6)='1' THEN --(An)+
postadd <= '1';
IF opcode(11 downto 9)="111" THEN
use_SP <= '1';
END IF;
END IF;
IF opcode(8)='1' THEN -- -(An)
presub <= '1';
IF opcode(11 downto 9)="111" THEN
use_SP <= '1';
END IF;
END IF;
IF opcode(7 downto 6)/="10" THEN
regwrena <= '1';
END IF;
setstate <= "11";
next_micro_state <= nop;
WHEN "101" => --(d16,An)
next_micro_state <= st_dAn1;
set_mem_regA <= '1';
setgetbrief <= '1';
WHEN "110" => --(d8,An,Xn)
next_micro_state <= st_AnXn1;
set_mem_regA <= '1';
setgetbrief <= '1';
WHEN "111" =>
CASE opcode(11 downto 9) IS
WHEN "000" => --(xxxx).w
next_micro_state <= st_nn;
WHEN "001" => --(xxxx).l
longreaddirect <= '1';
next_micro_state <= st_nn;
WHEN OTHERS =>
END CASE;
WHEN OTHERS =>
END CASE;
END IF;
-- 0100 ----------------------------------------------------------------------------
WHEN "0100" => --rts_group
IF opcode(8)='1' THEN --lea
IF opcode(6)='1' THEN --lea
IF opcode(7)='1' THEN
ea_only <= '1';
IF opcode(5 downto 3)="010" THEN --lea (Am),An
set_exec_move <='1';
no_Flags <='1';
dest_areg <= '1';
dest_hbits <= '1';
source_lowbits <= '1';
source_areg <= '1';
IF execOPC='1' THEN
Regwrena <= '1';
END IF;
ELSE
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
END IF;
IF get_ea_now='1' THEN
dest_areg <= '1';
dest_hbits <= '1';
regwrena <= '1';
END IF;
ELSE
trap_illegal <= '1';
trapmake <= '1';
END IF;
ELSE --chk
IF opcode(7)='1' THEN
set_exec_ADD <= '1';
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
datatype <= "01"; --Word
IF execOPC='1' THEN
setaddsub <= '0';
--first alternative
ea_data_OP1 <= '1';
IF c_out(1)='1' OR OP1out(15)='1' OR OP2out(15)='1' THEN
-- trap_chk <= '1'; --first I must change the Trap System
-- trapmake <= '1';
END IF;
--second alternative
-- IF (c_out(1)='0' AND flag_z(1)='0') OR OP1out(15)='1' OR OP2out(15)='1' THEN
-- -- trap_chk <= '1'; --first I must change the Trap System
-- -- trapmake <= '1';
-- END IF;
-- dest_hbits <= '1';
-- source_lowbits <='1';
END IF;
ELSE
trap_illegal <= '1'; -- chk long for 68020
trapmake <= '1';
END IF;
END IF;
ELSE
CASE opcode(11 downto 9) IS
WHEN "000"=>
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF opcode(7 downto 6)="11" THEN --move from SR
set_exec_MOVESR <= '1';
datatype <= "01";
write_back <='1'; -- im 68000 wird auch erst gelesen
IF execOPC='1' THEN
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
ELSE --negx
use_XFlag <= '1';
write_back <='1';
set_exec_ADD <= '1';
setaddsub <='0';
IF execOPC='1' THEN
source_lowbits <= '1';
OP1out_zero <= '1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
END IF;
WHEN "001"=>
IF opcode(7 downto 6)="11" THEN --move from CCR 68010
trap_illegal <= '1';
trapmake <= '1';
ELSE --clr
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
write_back <='1';
set_exec_AND <= '1';
IF execOPC='1' THEN
OP1out_zero <= '1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
END IF;
WHEN "010"=>
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF opcode(7 downto 6)="11" THEN --move to CCR
set_exec_MOVE <= '1';
datatype <= "01";
IF execOPC='1' THEN
source_lowbits <= '1';
to_SR <= '1';
END IF;
ELSE --neg
write_back <='1';
set_exec_ADD <= '1';
setaddsub <='0';
IF execOPC='1' THEN
source_lowbits <= '1';
OP1out_zero <= '1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
END IF;
WHEN "011"=> --not, move toSR
IF opcode(7 downto 6)="11" THEN --move to SR
IF SVmode='1' THEN
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
set_exec_MOVE <= '1';
datatype <= "01";
IF execOPC='1' THEN
source_lowbits <= '1';
to_SR <= '1';
END IF;
ELSE
trap_priv <= '1';
trapmake <= '1';
END IF;
ELSE --not
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
write_back <='1';
set_exec_EOR <= '1';
IF execOPC='1' THEN
OP2out_one <= '1';
ea_data_OP1 <= '1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
END IF;
WHEN "100"|"110"=>
IF opcode(7)='1' THEN --movem, ext
IF opcode(5 downto 3)="000" AND opcode(10)='0' THEN --ext
source_lowbits <= '1';
IF decodeOPC='1' THEN
set_exec_EXT <= '1';
set_exec_move <= '1';
END IF;
IF opcode(6)='0' THEN
datatype <= "01"; --WORD
END IF;
IF execOPC='1' THEN
regwrena <= '1';
END IF;
ELSE --movem
-- IF opcode(11 downto 7)="10001" OR opcode(11 downto 7)="11001" THEN --MOVEM
ea_only <= '1';
IF decodeOPC='1' THEN
datatype <= "01"; --Word
set_get_movem_mask <='1';
set_get_extendedOPC <='1';
IF opcode(5 downto 3)="010" OR opcode(5 downto 3)="011" OR opcode(5 downto 3)="100" THEN
set_mem_rega <= '1';
setstate <= "01";
IF opcode(10)='0' THEN
set_movem_busy <='1';
ELSE
next_micro_state <= movem;
END IF;
ELSE
ea_build <= '1';
END IF;
ELSE
IF opcode(6)='0' THEN
datatype <= "01"; --Word
END IF;
END IF;
IF execOPC='1' THEN
IF opcode(5 downto 3)="100" OR opcode(5 downto 3)="011" THEN
regwrena <= '1';
save_memaddr <= '1';
END IF;
END IF;
IF get_ea_now='1' THEN
set_movem_busy <= '1';
IF opcode(10)='0' THEN
setstate <="01";
ELSE
setstate <="10";
END IF;
END IF;
IF opcode(5 downto 3)="100" THEN
movem_presub <= '1';
END IF;
IF movem_addr='1' THEN
IF opcode(10)='1' THEN
regwrena <= '1';
END IF;
END IF;
IF movem_busy='1' THEN
IF opcode(10)='0' THEN
setstate <="11";
ELSE
setstate <="10";
END IF;
END IF;
END IF;
ELSE
IF opcode(10)='1' THEN --MUL, DIV 68020
trap_illegal <= '1';
trapmake <= '1';
ELSE --pea, swap
IF opcode(6)='1' THEN
datatype <= "10";
IF opcode(5 downto 3)="000" THEN --swap
IF execOPC='1' THEN
exec_swap <= '1';
regwrena <= '1';
END IF;
ELSIF opcode(5 downto 3)="001" THEN --bkpt
ELSE --pea
ea_only <= '1';
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF nextpass='1' AND micro_state=idle THEN
presub <= '1';
setstackaddr <='1';
set_mem_addsub <= '1';
setstate <="11";
next_micro_state <= nop;
END IF;
IF get_ea_now='1' THEN
setstate <="01";
END IF;
END IF;
ELSE --nbcd
IF decodeOPC='1' THEN --nbcd
ea_build <= '1';
END IF;
use_XFlag <= '1';
write_back <='1';
set_exec_ADD <= '1';
set_exec_SBCD <= '1';
IF execOPC='1' THEN
source_lowbits <= '1';
OP1out_zero <= '1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
END IF;
END IF;
END IF;
WHEN "101"=> --tst, tas
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF execOPC='1' THEN
dest_hbits <= '1'; --for Flags
source_lowbits <= '1';
-- IF opcode(3)='1' THEN --MC68020...
-- source_areg <= '1';
-- END IF;
END IF;
set_exec_MOVE <= '1';
IF opcode(7 downto 6)="11" THEN --tas
set_exec_tas <= '1';
write_back <= '1';
datatype <= "00"; --Byte
IF execOPC='1' AND endOPC='1' THEN
regwrena <= '1';
END IF;
END IF;
-- WHEN "110"=>
WHEN "111"=> --4EXX
IF opcode(7)='1' THEN --jsr, jmp
datatype <= "10";
ea_only <= '1';
IF nextpass='1' AND micro_state=idle THEN
presub <= '1';
setstackaddr <='1';
set_mem_addsub <= '1';
setstate <="11";
next_micro_state <= nop;
END IF;
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF get_ea_now='1' THEN --jsr
IF opcode(6)='0' THEN
setstate <="01";
END IF;
ea_to_pc <= '1';
IF opcode(5 downto 1)="11100" THEN
writePC_add <= '1';
ELSE
writePC <= '1';
END IF;
END IF;
ELSE --
CASE opcode(6 downto 0) IS
WHEN "1000000"|"1000001"|"1000010"|"1000011"|"1000100"|"1000101"|"1000110"|"1000111"| --trap
"1001000"|"1001001"|"1001010"|"1001011"|"1001100"|"1001101"|"1001110"|"1001111" => --trap
trap_trap <='1';
trapmake <= '1';
WHEN "1010000"|"1010001"|"1010010"|"1010011"|"1010100"|"1010101"|"1010110"|"1010111" => --link
datatype <= "10";
IF decodeOPC='1' THEN
next_micro_state <= link;
 
presub <= '1';
setstackaddr <='1';
set_mem_addsub <= '1';
source_lowbits <= '1';
source_areg <= '1';
END IF;
IF execOPC='1' THEN
setstackaddr <='1';
regwrena <= '1';
END IF;
WHEN "1011000"|"1011001"|"1011010"|"1011011"|"1011100"|"1011101"|"1011110"|"1011111" => --unlink
datatype <= "10";
IF decodeOPC='1' THEN
setstate <= "10";
set_mem_rega <= '1';
ELSIF execOPC='1' THEN
regwrena <= '1';
exec_exg <= '1';
ELSE
setstackaddr <='1';
regwrena <= '1';
get_ea_now <= '1';
ea_only <= '1';
END IF;
WHEN "1100000"|"1100001"|"1100010"|"1100011"|"1100100"|"1100101"|"1100110"|"1100111" => --move An,USP
IF SVmode='1' THEN
no_Flags <= '1';
to_USP <= '1';
setstackaddr <= '1';
source_lowbits <= '1';
source_areg <= '1';
set_exec_MOVE <= '1';
datatype <= "10";
IF execOPC='1' THEN
regwrena <= '1';
END IF;
ELSE
trap_priv <= '1';
trapmake <= '1';
END IF;
WHEN "1101000"|"1101001"|"1101010"|"1101011"|"1101100"|"1101101"|"1101110"|"1101111" => --move USP,An
IF SVmode='1' THEN
no_Flags <= '1';
from_USP <= '1';
set_exec_MOVE <= '1';
datatype <= "10";
IF execOPC='1' THEN
regwrena <= '1';
END IF;
ELSE
trap_priv <= '1';
trapmake <= '1';
END IF;
WHEN "1110000" => --reset
IF SVmode='0' THEN
trap_priv <= '1';
trapmake <= '1';
END IF;
WHEN "1110001" => --nop
WHEN "1110010" => --stop
IF SVmode='0' THEN
trap_priv <= '1';
trapmake <= '1';
ELSE
IF decodeOPC='1' THEN
setnextpass <= '1';
set_directSR <= '1';
set_stop <= '1';
END IF;
END IF;
WHEN "1110011" => --rte
IF SVmode='1' THEN
IF decodeOPC='1' THEN
datatype <= "01";
setstate <= "10";
postadd <= '1';
setstackaddr <= '1';
set_mem_rega <= '1';
set_directSR <= '1';
next_micro_state <= rte;
END IF;
ELSE
trap_priv <= '1';
trapmake <= '1';
END IF;
WHEN "1110101" => --rts
IF decodeOPC='1' THEN
datatype <= "10";
setstate <= "10";
postadd <= '1';
setstackaddr <= '1';
set_mem_rega <= '1';
set_directPC <= '1';
next_micro_state <= nop;
END IF;
WHEN "1110110" => --trapv
IF Flags(1)='1' THEN
trap_trapv <= '1';
trapmake <= '1';
END IF;
WHEN "1110111" => --rtr
IF decodeOPC='1' THEN
datatype <= "01";
setstate <= "10";
postadd <= '1';
setstackaddr <= '1';
set_mem_rega <= '1';
set_directCCR <= '1';
next_micro_state <= rte;
END IF;
WHEN OTHERS =>
trap_illegal <= '1';
trapmake <= '1';
END CASE;
END IF;
WHEN OTHERS => null;
END CASE;
END IF;
-- 0101 ----------------------------------------------------------------------------
WHEN "0101" => --subq, addq
IF opcode(7 downto 6)="11" THEN --dbcc
IF opcode(5 downto 3)="001" THEN --dbcc
datatype <= "01"; --Word
IF decodeOPC='1' THEN
next_micro_state <= nop;
OP2out_one <= '1';
IF condition='0' THEN
Regwrena <= '1';
IF c_in(2)='1' THEN
next_micro_state <= dbcc1;
END IF;
END IF;
data_is_source <= '1';
END IF;
ELSE --Scc
datatype <= "00"; --Byte
write_back <= '1';
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF condition='0' THEN
set_exec_Scc <= '1';
END IF;
IF execOPC='1' THEN
IF condition='1' THEN
OP2out_one <= '1';
exec_EXG <= '1';
ELSE
OP1out_zero <= '1';
END IF;
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
END IF;
ELSE --addq, subq
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF opcode(5 downto 3)="001" THEN
no_Flags <= '1';
END IF;
write_back <= '1';
set_exec_ADDQ <= '1';
set_exec_ADD <= '1';
IF execOPC='1' THEN
ea_data_OP1 <= '1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
IF opcode(8)='1' THEN
setaddsub <= '0';
END IF;
END IF;
END IF;
-- 0110 ----------------------------------------------------------------------------
WHEN "0110" => --bra,bsr,bcc
datatype <= "10";
IF micro_state=idle THEN
IF opcode(11 downto 8)="0001" THEN --bsr
IF opcode(7 downto 0)="00000000" THEN
next_micro_state <= bsr1;
ELSE
next_micro_state <= bsr2;
setstate <= "01";
END IF;
presub <= '1';
setstackaddr <='1';
set_mem_addsub <= '1';
ELSE --bra
IF opcode(7 downto 0)="00000000" THEN
next_micro_state <= bra1;
END IF;
IF condition='1' THEN
TG68_PC_br8 <= '1';
END IF;
END IF;
END IF;
-- 0111 ----------------------------------------------------------------------------
WHEN "0111" => --moveq
IF opcode(8)='0' THEN
IF trap_interrupt='0' THEN
datatype <= "10"; --Long
Regwrena <= '1';
set_exec_MOVEQ <= '1';
set_exec_MOVE <= '1';
dest_hbits <= '1';
END IF;
ELSE
trap_illegal <= '1';
trapmake <= '1';
END IF;
-- 1000 ----------------------------------------------------------------------------
WHEN "1000" => --or
IF opcode(7 downto 6)="11" THEN --divu, divs
IF opcode(5 downto 4)="00" THEN --Dn, An
regdirectsource <= '1';
END IF;
IF (micro_state=idle AND nextpass='1') OR (opcode(5 downto 4)="00" AND decodeOPC='1') THEN
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div1;
END IF;
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF execOPC='1' AND z_error='0' AND set_V_Flag='0' THEN
regwrena <= '1';
END IF;
IF (micro_state/=idle AND nextpass='1') OR execOPC='1' THEN
dest_hbits <= '1';
source_lowbits <='1';
ELSE
datatype <= "01";
END IF;
ELSIF opcode(8)='1' AND opcode(5 downto 4)="00" THEN --sbcd, pack , unpack
IF opcode(7 downto 6)="00" THEN --sbcd
use_XZFlag <= '1';
set_exec_ADD <= '1';
set_exec_SBCD <= '1';
IF opcode(3)='1' THEN
write_back <= '1';
IF decodeOPC='1' THEN
set_direct_data <= '1';
setstate <= "10";
set_mem_addsub <= '1';
presub <= '1';
next_micro_state <= op_AxAy;
END IF;
END IF;
IF execOPC='1' THEN
ea_data_OP1 <= '1';
dest_hbits <= '1';
source_lowbits <='1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
ELSE --pack, unpack
trap_illegal <= '1';
trapmake <= '1';
END IF;
ELSE --or
set_exec_OR <= '1';
IF opcode(8)='1' THEN
write_back <= '1';
END IF;
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF execOPC='1' THEN
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
IF opcode(8)='1' THEN
ea_data_OP1 <= '1';
ELSE
dest_hbits <= '1';
source_lowbits <='1';
IF opcode(3)='1' THEN
source_areg <= '1';
END IF;
END IF;
END IF;
END IF;
-- 1001, 1101 -----------------------------------------------------------------------
WHEN "1001"|"1101" => --sub, add
set_exec_ADD <= '1';
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF opcode(8 downto 6)="011" THEN --adda.w, suba.w
datatype <= "01"; --Word
END IF;
IF execOPC='1' THEN
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
IF opcode(14)='0' THEN
setaddsub <= '0';
END IF;
END IF;
IF opcode(8)='1' AND opcode(5 downto 4)="00" AND opcode(7 downto 6)/="11" THEN --addx, subx
use_XZFlag <= '1';
IF opcode(3)='1' THEN
write_back <= '1';
IF decodeOPC='1' THEN
set_direct_data <= '1';
setstate <= "10";
set_mem_addsub <= '1';
presub <= '1';
next_micro_state <= op_AxAy;
END IF;
END IF;
IF execOPC='1' THEN
ea_data_OP1 <= '1';
dest_hbits <= '1';
source_lowbits <='1';
END IF;
ELSE --sub, add
IF opcode(8)='1' AND opcode(7 downto 6)/="11" THEN
write_back <= '1';
END IF;
IF execOPC='1' THEN
IF opcode(7 downto 6)="11" THEN --adda, suba
no_Flags <= '1';
dest_areg <='1';
dest_hbits <= '1';
source_lowbits <='1';
IF opcode(3)='1' THEN
source_areg <= '1';
END IF;
ELSE
IF opcode(8)='1' THEN
ea_data_OP1 <= '1';
ELSE
dest_hbits <= '1';
source_lowbits <='1';
IF opcode(3)='1' THEN
source_areg <= '1';
END IF;
END IF;
END IF;
END IF;
END IF;
-- 1010 ----------------------------------------------------------------------------
WHEN "1010" => --Trap 1010
trap_1010 <= '1';
trapmake <= '1';
-- 1011 ----------------------------------------------------------------------------
WHEN "1011" => --eor, cmp
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF opcode(8 downto 6)="011" THEN --cmpa.w
datatype <= "01"; --Word
set_exec_CPMAW <= '1';
END IF;
IF opcode(8)='1' AND opcode(5 downto 3)="001" AND opcode(7 downto 6)/="11" THEN --cmpm
set_exec_CMP <= '1';
IF decodeOPC='1' THEN
set_direct_data <= '1';
setstate <= "10";
set_mem_rega <= '1';
postadd <= '1';
next_micro_state <= cmpm;
END IF;
IF execOPC='1' THEN
ea_data_OP1 <= '1';
setaddsub <= '0';
END IF;
ELSE --sub, add
IF opcode(8)='1' AND opcode(7 downto 6)/="11" THEN --eor
set_exec_EOR <= '1';
write_back <= '1';
ELSE --cmp
set_exec_CMP <= '1';
END IF;
IF execOPC='1' THEN
IF opcode(8)='1' AND opcode(7 downto 6)/="11" THEN --eor
ea_data_OP1 <= '1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
ELSE --cmp
source_lowbits <='1';
IF opcode(3)='1' THEN
source_areg <= '1';
END IF;
IF opcode(7 downto 6)="11" THEN --cmpa
dest_areg <='1';
END IF;
dest_hbits <= '1';
setaddsub <= '0';
END IF;
END IF;
END IF;
-- 1100 ----------------------------------------------------------------------------
WHEN "1100" => --and, exg
IF opcode(7 downto 6)="11" THEN --mulu, muls
IF opcode(5 downto 4)="00" THEN --Dn, An
regdirectsource <= '1';
END IF;
IF (micro_state=idle AND nextpass='1') OR (opcode(5 downto 4)="00" AND decodeOPC='1') THEN
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul1;
END IF;
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF execOPC='1' THEN
regwrena <= '1';
END IF;
IF (micro_state/=idle AND nextpass='1') OR execOPC='1' THEN
dest_hbits <= '1';
source_lowbits <='1';
ELSE
datatype <= "01";
END IF;
ELSIF opcode(8)='1' AND opcode(5 downto 4)="00" THEN --exg, abcd
IF opcode(7 downto 6)="00" THEN --abcd
use_XZFlag <= '1';
-- datatype <= "00"; --ist schon default
set_exec_ADD <= '1';
set_exec_ABCD <= '1';
IF opcode(3)='1' THEN
write_back <= '1';
IF decodeOPC='1' THEN
set_direct_data <= '1';
setstate <= "10";
set_mem_addsub <= '1';
presub <= '1';
next_micro_state <= op_AxAy;
END IF;
END IF;
IF execOPC='1' THEN
ea_data_OP1 <= '1';
dest_hbits <= '1';
source_lowbits <='1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
ELSE --exg
datatype <= "10";
regwrena <= '1';
IF opcode(6)='1' AND opcode(3)='1' THEN
dest_areg <= '1';
source_areg <= '1';
END IF;
IF decodeOPC='1' THEN
set_mem_rega <= '1';
exec_exg <= '1';
ELSE
save_memaddr <= '1';
dest_hbits <= '1';
END IF;
END IF;
ELSE --and
set_exec_AND <= '1';
IF opcode(8)='1' THEN
write_back <= '1';
END IF;
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF execOPC='1' THEN
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
IF opcode(8)='1' THEN
ea_data_OP1 <= '1';
ELSE
dest_hbits <= '1';
source_lowbits <='1';
IF opcode(3)='1' THEN
source_areg <= '1';
END IF;
END IF;
END IF;
END IF;
-- 1110 ----------------------------------------------------------------------------
WHEN "1110" => --rotation
set_exec_ROT <= '1';
IF opcode(7 downto 6)="11" THEN
datatype <= "01";
rot_bits <= opcode(10 downto 9);
ea_data_OP1 <= '1';
write_back <= '1';
ELSE
rot_bits <= opcode(4 downto 3);
data_is_source <= '1';
END IF;
IF decodeOPC='1' THEN
IF opcode(7 downto 6)="11" THEN
ea_build <= '1';
ELSE
IF opcode(5)='1' THEN
IF OP2out(5 downto 0)/="000000" THEN
set_rot_cnt <= OP2out(5 downto 0);
ELSE
set_rot_nop <= '1';
END IF;
ELSE
set_rot_cnt(2 downto 0) <= opcode(11 downto 9);
IF opcode(11 downto 9)="000" THEN
set_rot_cnt(3) <='1';
ELSE
set_rot_cnt(3) <='0';
END IF;
END IF;
END IF;
END IF;
IF opcode(7 downto 6)/="11" THEN
IF execOPC='1' AND rot_nop='0' THEN
Regwrena <= '1';
set_rot_cnt <= rot_cnt-1;
END IF;
END IF;
-- ----------------------------------------------------------------------------
WHEN OTHERS =>
trap_1111 <= '1';
trapmake <= '1';
 
END CASE;
-- END PROCESS;
-----------------------------------------------------------------------------
-- execute microcode
-----------------------------------------------------------------------------
--PROCESS (micro_state)
-- BEGIN
IF Z_error='1' THEN -- divu by zero
 
IF trapd='0' THEN
writePC <= '1';
END IF;
END IF;
IF trapmake='1' AND trapd='0' THEN
next_micro_state <= trap1;
presub <= '1';
setstackaddr <='1';
set_mem_addsub <= '1';
setstate <= "11";
datatype <= "10";
END IF;
IF interrupt='1' THEN
next_micro_state <= int1;
setstate <= "10";
-- datatype <= "01"; --wirkt sich auf Flags aus
END IF;
 
IF reset='0' THEN
micro_state <= init1;
ELSIF rising_edge(clk) THEN
IF clkena='1' THEN
trapd <= trapmake;
IF fetchOPC='1' THEN
micro_state <= idle;
ELSE
micro_state <= next_micro_state;
END IF;
END IF;
END IF;
CASE micro_state IS
WHEN ld_nn => -- (nnnn).w/l=>
get_ea_now <='1';
setnextpass <= '1';
setaddrlong <= '1';
WHEN st_nn => -- =>(nnnn).w/l
setstate <= "11";
setaddrlong <= '1';
next_micro_state <= nop;
WHEN ld_dAn1 => -- d(An)=>, --d(PC)=>
setstate <= "01";
next_micro_state <= ld_dAn2;
WHEN ld_dAn2 => -- d(An)=>, --d(PC)=>
get_ea_now <='1';
setdisp <= '1'; --word
setnextpass <= '1';
WHEN ld_AnXn1 => -- d(An,Xn)=>, --d(PC,Xn)=>
setstate <= "01";
next_micro_state <= ld_AnXn2;
WHEN ld_AnXn2 => -- d(An,Xn)=>, --d(PC,Xn)=>
setdisp <= '1'; --byte
setdispbyte <= '1';
setstate <= "01";
setbriefext <= '1';
next_micro_state <= ld_AnXn3;
WHEN ld_AnXn3 =>
get_ea_now <='1';
setdisp <= '1'; --brief
setdispbrief <= '1';
setnextpass <= '1';
WHEN st_dAn1 => -- =>d(An)
setstate <= "01";
next_micro_state <= st_dAn2;
WHEN st_dAn2 => -- =>d(An)
setstate <= "11";
setdisp <= '1'; --word
next_micro_state <= nop;
WHEN st_AnXn1 => -- =>d(An,Xn)
setstate <= "01";
next_micro_state <= st_AnXn2;
WHEN st_AnXn2 => -- =>d(An,Xn)
setdisp <= '1'; --byte
setdispbyte <= '1';
setstate <= "01";
setbriefext <= '1';
next_micro_state <= st_AnXn3;
WHEN st_AnXn3 =>
setstate <= "11";
setdisp <= '1'; --brief
setdispbrief <= '1';
next_micro_state <= nop;
WHEN bra1 => --bra
IF condition='1' THEN
TG68_PC_br8 <= '1'; --pc+0000
setstate <= "01";
next_micro_state <= bra2;
END IF;
WHEN bra2 => --bra
TG68_PC_brw <= '1';
WHEN bsr1 => --bsr
set_TG68_PC_dec <= '1'; --in 2 Takten -2
setstate <= "01";
next_micro_state <= bsr2;
WHEN bsr2 => --bsr
IF TG68_PC_dec(0)='1' THEN
TG68_PC_brw <= '1';
ELSE
TG68_PC_br8 <= '1';
END IF;
writePC <= '1';
setstate <= "11";
next_micro_state <= nop;
 
WHEN dbcc1 => --dbcc
TG68_PC_nop <= '1';
setstate <= "01";
next_micro_state <= dbcc2;
WHEN dbcc2 => --dbcc
TG68_PC_brw <= '1';
WHEN movem => --movem
set_movem_busy <='1';
setstate <= "10";
 
WHEN andi => --andi
IF opcode(5 downto 4)/="00" THEN
ea_build <= '1';
setnextpass <= '1';
END IF;
 
WHEN op_AxAy => -- op -(Ax),-(Ay)
presub <= '1';
dest_hbits <= '1';
dest_areg <= '1';
set_mem_addsub <= '1';
setstate <= "10";
 
WHEN cmpm => -- cmpm (Ay)+,(Ax)+
postadd <= '1';
dest_hbits <= '1';
dest_areg <= '1';
set_mem_rega <= '1';
setstate <= "10";
WHEN link => -- link
setstate <="11";
save_memaddr <= '1';
regwrena <= '1';
WHEN int1 => -- interrupt
presub <= '1';
setstackaddr <='1';
set_mem_addsub <= '1';
setstate <= "11";
datatype <= "10";
next_micro_state <= int2;
WHEN int2 => -- interrupt
presub <= '1';
setstackaddr <='1';
set_mem_addsub <= '1';
setstate <= "11";
datatype <= "01";
writeSR <= '1';
next_micro_state <= int3;
WHEN int3 => -- interrupt
set_vectoraddr <= '1';
datatype <= "10";
set_directPC <= '1';
setstate <= "10";
next_micro_state <= int4;
WHEN int4 => -- interrupt
datatype <= "10";
 
WHEN rte => -- RTE
datatype <= "10";
setstate <= "10";
postadd <= '1';
setstackaddr <= '1';
set_mem_rega <= '1';
set_directPC <= '1';
next_micro_state <= nop;
 
WHEN trap1 => -- TRAP
presub <= '1';
setstackaddr <='1';
set_mem_addsub <= '1';
setstate <= "11";
datatype <= "01";
writeSR <= '1';
next_micro_state <= trap2;
WHEN trap2 => -- TRAP
set_vectoraddr <= '1';
datatype <= "10";
set_directPC <= '1';
-- longreaddirect <= '1';
setstate <= "10";
next_micro_state <= trap3;
WHEN trap3 => -- TRAP
datatype <= "10";
WHEN movep1 => -- MOVEP d(An)
setstate <= "01";
IF opcode(6)='1' THEN
set_movepl <= '1';
END IF;
next_micro_state <= movep2;
WHEN movep2 =>
setdisp <= '1';
IF opcode(7)='0' THEN
setstate <= "10";
ELSE
setstate <= "11";
wait_mem_byte <= '1';
END IF;
next_micro_state <= movep3;
WHEN movep3 =>
IF opcode(6)='1' THEN
set_movepw <= '1';
next_micro_state <= movep4;
END IF;
IF opcode(7)='0' THEN
setstate <= "10";
ELSE
setstate <= "11";
END IF;
WHEN movep4 =>
IF opcode(7)='0' THEN
setstate <= "10";
ELSE
wait_mem_byte <= '1';
setstate <= "11";
END IF;
next_micro_state <= movep5;
WHEN movep5 =>
IF opcode(7)='0' THEN
setstate <= "10";
ELSE
setstate <= "11";
END IF;
WHEN init1 => -- init SP
longreaddirect <= '1';
next_micro_state <= init2;
WHEN init2 => -- init PC
get_ea_now <='1'; --\
ea_only <= '1'; --- OP1in <= memaddr_in
setaddrlong <= '1'; -- memaddr_in <= data_read
regwrena <= '1';
setstackaddr <='1'; -- dest_addr <= SP
set_directPC <= '1';
longreaddirect <= '1';
next_micro_state <= nop;
 
WHEN mul1 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul2;
WHEN mul2 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul3;
WHEN mul3 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul4;
WHEN mul4 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul5;
WHEN mul5 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul6;
WHEN mul6 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul7;
WHEN mul7 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul8;
WHEN mul8 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul9;
WHEN mul9 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul10;
WHEN mul10 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul11;
WHEN mul11 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul12;
WHEN mul12 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul13;
WHEN mul13 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul14;
WHEN mul14 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul15;
WHEN mul15 => -- mulu
set_exec_MULU <= '1';
 
WHEN div1 => -- divu
IF OP2out(15 downto 0)=x"0000" THEN --div zero
set_Z_error <= '1';
ELSE
set_exec_DIVU <= '1';
next_micro_state <= div2;
END IF;
setstate <="01";
WHEN div2 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div3;
WHEN div3 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div4;
WHEN div4 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div5;
WHEN div5 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div6;
WHEN div6 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div7;
WHEN div7 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div8;
WHEN div8 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div9;
WHEN div9 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div10;
WHEN div10 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div11;
WHEN div11 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div12;
WHEN div12 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div13;
WHEN div13 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div14;
WHEN div14 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div15;
WHEN div15 => -- divu
set_exec_DIVU <= '1';
 
WHEN OTHERS => null;
END CASE;
END PROCESS;
 
-----------------------------------------------------------------------------
-- Conditions
-----------------------------------------------------------------------------
PROCESS (opcode, Flags)
BEGIN
CASE opcode(11 downto 8) IS
WHEN X"0" => condition <= '1';
WHEN X"1" => condition <= '0';
WHEN X"2" => condition <= NOT Flags(0) AND NOT Flags(2);
WHEN X"3" => condition <= Flags(0) OR Flags(2);
WHEN X"4" => condition <= NOT Flags(0);
WHEN X"5" => condition <= Flags(0);
WHEN X"6" => condition <= NOT Flags(2);
WHEN X"7" => condition <= Flags(2);
WHEN X"8" => condition <= NOT Flags(1);
WHEN X"9" => condition <= Flags(1);
WHEN X"a" => condition <= NOT Flags(3);
WHEN X"b" => condition <= Flags(3);
WHEN X"c" => condition <= (Flags(3) AND Flags(1)) OR (NOT Flags(3) AND NOT Flags(1));
WHEN X"d" => condition <= (Flags(3) AND NOT Flags(1)) OR (NOT Flags(3) AND Flags(1));
WHEN X"e" => condition <= (Flags(3) AND Flags(1) AND NOT Flags(2)) OR (NOT Flags(3) AND NOT Flags(1) AND NOT Flags(2));
WHEN X"f" => condition <= (Flags(3) AND NOT Flags(1)) OR (NOT Flags(3) AND Flags(1)) OR Flags(2);
WHEN OTHERS => null;
END CASE;
END PROCESS;
 
-----------------------------------------------------------------------------
-- Bits
-----------------------------------------------------------------------------
PROCESS (opcode, OP1out, OP2out, one_bit_in, one_bit_out, bit_Number, bit_number_reg)
BEGIN
CASE opcode(7 downto 6) IS
WHEN "00" => --btst
one_bit_out <= one_bit_in;
WHEN "01" => --bchg
one_bit_out <= NOT one_bit_in;
WHEN "10" => --bclr
one_bit_out <= '0';
WHEN "11" => --bset
one_bit_out <= '1';
WHEN OTHERS => null;
END CASE;
IF opcode(8)='0' THEN
IF opcode(5 downto 4)="00" THEN
bit_number <= bit_number_reg(4 downto 0);
ELSE
bit_number <= "00"&bit_number_reg(2 downto 0);
END IF;
ELSE
IF opcode(5 downto 4)="00" THEN
bit_number <= OP2out(4 downto 0);
ELSE
bit_number <= "00"&OP2out(2 downto 0);
END IF;
END IF;
bits_out <= OP1out;
CASE bit_Number IS
WHEN "00000" => one_bit_in <= OP1out(0);
bits_out(0) <= one_bit_out;
WHEN "00001" => one_bit_in <= OP1out(1);
bits_out(1) <= one_bit_out;
WHEN "00010" => one_bit_in <= OP1out(2);
bits_out(2) <= one_bit_out;
WHEN "00011" => one_bit_in <= OP1out(3);
bits_out(3) <= one_bit_out;
WHEN "00100" => one_bit_in <= OP1out(4);
bits_out(4) <= one_bit_out;
WHEN "00101" => one_bit_in <= OP1out(5);
bits_out(5) <= one_bit_out;
WHEN "00110" => one_bit_in <= OP1out(6);
bits_out(6) <= one_bit_out;
WHEN "00111" => one_bit_in <= OP1out(7);
bits_out(7) <= one_bit_out;
WHEN "01000" => one_bit_in <= OP1out(8);
bits_out(8) <= one_bit_out;
WHEN "01001" => one_bit_in <= OP1out(9);
bits_out(9) <= one_bit_out;
WHEN "01010" => one_bit_in <= OP1out(10);
bits_out(10) <= one_bit_out;
WHEN "01011" => one_bit_in <= OP1out(11);
bits_out(11) <= one_bit_out;
WHEN "01100" => one_bit_in <= OP1out(12);
bits_out(12) <= one_bit_out;
WHEN "01101" => one_bit_in <= OP1out(13);
bits_out(13) <= one_bit_out;
WHEN "01110" => one_bit_in <= OP1out(14);
bits_out(14) <= one_bit_out;
WHEN "01111" => one_bit_in <= OP1out(15);
bits_out(15) <= one_bit_out;
WHEN "10000" => one_bit_in <= OP1out(16);
bits_out(16) <= one_bit_out;
WHEN "10001" => one_bit_in <= OP1out(17);
bits_out(17) <= one_bit_out;
WHEN "10010" => one_bit_in <= OP1out(18);
bits_out(18) <= one_bit_out;
WHEN "10011" => one_bit_in <= OP1out(19);
bits_out(19) <= one_bit_out;
WHEN "10100" => one_bit_in <= OP1out(20);
bits_out(20) <= one_bit_out;
WHEN "10101" => one_bit_in <= OP1out(21);
bits_out(21) <= one_bit_out;
WHEN "10110" => one_bit_in <= OP1out(22);
bits_out(22) <= one_bit_out;
WHEN "10111" => one_bit_in <= OP1out(23);
bits_out(23) <= one_bit_out;
WHEN "11000" => one_bit_in <= OP1out(24);
bits_out(24) <= one_bit_out;
WHEN "11001" => one_bit_in <= OP1out(25);
bits_out(25) <= one_bit_out;
WHEN "11010" => one_bit_in <= OP1out(26);
bits_out(26) <= one_bit_out;
WHEN "11011" => one_bit_in <= OP1out(27);
bits_out(27) <= one_bit_out;
WHEN "11100" => one_bit_in <= OP1out(28);
bits_out(28) <= one_bit_out;
WHEN "11101" => one_bit_in <= OP1out(29);
bits_out(29) <= one_bit_out;
WHEN "11110" => one_bit_in <= OP1out(30);
bits_out(30) <= one_bit_out;
WHEN "11111" => one_bit_in <= OP1out(31);
bits_out(31) <= one_bit_out;
WHEN OTHERS => null;
END CASE;
END PROCESS;
 
-----------------------------------------------------------------------------
-- Rotation
-----------------------------------------------------------------------------
PROCESS (opcode, OP1out, Flags, rot_bits, rot_msb, rot_lsb, rot_rot, rot_nop)
BEGIN
CASE opcode(7 downto 6) IS
WHEN "00" => --Byte
rot_rot <= OP1out(7);
WHEN "01"|"11" => --Word
rot_rot <= OP1out(15);
WHEN "10" => --Long
rot_rot <= OP1out(31);
WHEN OTHERS => null;
END CASE;
CASE rot_bits IS
WHEN "00" => --ASL, ASR
rot_lsb <= '0';
rot_msb <= rot_rot;
WHEN "01" => --LSL, LSR
rot_lsb <= '0';
rot_msb <= '0';
WHEN "10" => --ROXL, ROXR
rot_lsb <= Flags(4);
rot_msb <= Flags(4);
WHEN "11" => --ROL, ROR
rot_lsb <= rot_rot;
rot_msb <= OP1out(0);
WHEN OTHERS => null;
END CASE;
IF rot_nop='1' THEN
rot_out <= OP1out;
rot_XC <= Flags(0);
ELSE
IF opcode(8)='1' THEN --left
rot_out <= OP1out(30 downto 0)&rot_lsb;
rot_XC <= rot_rot;
ELSE --right
rot_XC <= OP1out(0);
rot_out <= rot_msb&OP1out(31 downto 1);
CASE opcode(7 downto 6) IS
WHEN "00" => --Byte
rot_out(7) <= rot_msb;
WHEN "01"|"11" => --Word
rot_out(15) <= rot_msb;
WHEN OTHERS =>
END CASE;
END IF;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- MULU/MULS
-----------------------------------------------------------------------------
PROCESS (clk, opcode, OP2out, muls_msb, mulu_reg, OP1sign, sign2)
BEGIN
IF rising_edge(clk) THEN
IF clkena='1' THEN
IF decodeOPC='1' THEN
IF opcode(8)='1' AND reg_QB(15)='1' THEN --MULS Neg faktor
OP1sign <= '1';
mulu_reg <= "0000000000000000"&(0-reg_QB(15 downto 0));
ELSE
OP1sign <= '0';
mulu_reg <= "0000000000000000"&reg_QB(15 downto 0);
END IF;
ELSIF exec_MULU='1' THEN
mulu_reg <= dummy_mulu;
END IF;
END IF;
END IF;
IF (opcode(8)='1' AND OP2out(15)='1') OR OP1sign='1' THEN
muls_msb <= mulu_reg(31);
ELSE
muls_msb <= '0';
END IF;
IF opcode(8)='1' AND OP2out(15)='1' THEN
sign2 <= '1';
ELSE
sign2 <= '0';
END IF;
IF mulu_reg(0)='1' THEN
IF OP1sign='1' THEN
dummy_mulu <= (muls_msb&mulu_reg(31 downto 16))-(sign2&OP2out(15 downto 0))& mulu_reg(15 downto 1);
ELSE
dummy_mulu <= (muls_msb&mulu_reg(31 downto 16))+(sign2&OP2out(15 downto 0))& mulu_reg(15 downto 1);
END IF;
ELSE
dummy_mulu <= muls_msb&mulu_reg(31 downto 1);
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- DIVU
-----------------------------------------------------------------------------
PROCESS (clk, execOPC, opcode, OP1out, OP2out, div_reg, dummy_div_sub, div_quot, div_sign, dummy_div_over, dummy_div)
BEGIN
set_V_Flag <= '0';
IF rising_edge(clk) THEN
IF clkena='1' THEN
IF decodeOPC='1' THEN
IF opcode(8)='1' AND reg_QB(31)='1' THEN -- Neg divisor
div_sign <= '1';
div_reg <= 0-reg_QB;
ELSE
div_sign <= '0';
div_reg <= reg_QB;
END IF;
ELSIF exec_DIVU='1' THEN
div_reg <= div_quot;
END IF;
END IF;
END IF;
dummy_div_over <= ('0'&OP1out(31 downto 16))-('0'&OP2out(15 downto 0));
IF opcode(8)='1' AND OP2out(15) ='1' THEN
dummy_div_sub <= (div_reg(31 downto 15))+('1'&OP2out(15 downto 0));
ELSE
dummy_div_sub <= (div_reg(31 downto 15))-('0'&OP2out(15 downto 0));
END IF;
IF (dummy_div_sub(16))='1' THEN
div_quot(31 downto 16) <= div_reg(30 downto 15);
ELSE
div_quot(31 downto 16) <= dummy_div_sub(15 downto 0);
END IF;
div_quot(15 downto 0) <= div_reg(14 downto 0)&NOT dummy_div_sub(16);
IF execOPC='1' AND opcode(8)='1' AND (OP2out(15) XOR div_sign)='1' THEN
dummy_div(15 downto 0) <= 0-div_quot(15 downto 0);
ELSE
dummy_div(15 downto 0) <= div_quot(15 downto 0);
END IF;
IF div_sign='1' THEN
dummy_div(31 downto 16) <= 0-div_quot(31 downto 16);
ELSE
dummy_div(31 downto 16) <= div_quot(31 downto 16);
END IF;
IF (opcode(8)='1' AND (OP2out(15) XOR div_sign XOR dummy_div(15))='1' AND dummy_div(15 downto 0)/=X"0000") --Overflow DIVS
OR (opcode(8)='0' AND dummy_div_over(16)='0') THEN --Overflow DIVU
set_V_Flag <= '1';
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- Movem
-----------------------------------------------------------------------------
PROCESS (reset, clk, movem_mask, movem_muxa ,movem_muxb, movem_muxc)
BEGIN
IF movem_mask(7 downto 0)="00000000" THEN
movem_muxa <= movem_mask(15 downto 8);
movem_regaddr(3) <= '1';
ELSE
movem_muxa <= movem_mask(7 downto 0);
movem_regaddr(3) <= '0';
END IF;
IF movem_muxa(3 downto 0)="0000" THEN
movem_muxb <= movem_muxa(7 downto 4);
movem_regaddr(2) <= '1';
ELSE
movem_muxb <= movem_muxa(3 downto 0);
movem_regaddr(2) <= '0';
END IF;
IF movem_muxb(1 downto 0)="00" THEN
movem_muxc <= movem_muxb(3 downto 2);
movem_regaddr(1) <= '1';
ELSE
movem_muxc <= movem_muxb(1 downto 0);
movem_regaddr(1) <= '0';
END IF;
IF movem_muxc(0)='0' THEN
movem_regaddr(0) <= '1';
ELSE
movem_regaddr(0) <= '0';
END IF;
 
movem_bits <= ("0000"&movem_mask(0))+("0000"&movem_mask(1))+("0000"&movem_mask(2))+("0000"&movem_mask(3))+
("0000"&movem_mask(4))+("0000"&movem_mask(5))+("0000"&movem_mask(6))+("0000"&movem_mask(7))+
("0000"&movem_mask(8))+("0000"&movem_mask(9))+("0000"&movem_mask(10))+("0000"&movem_mask(11))+
("0000"&movem_mask(12))+("0000"&movem_mask(13))+("0000"&movem_mask(14))+("0000"&movem_mask(15));
IF reset = '0' THEN
movem_busy <= '0';
movem_addr <= '0';
ELSIF rising_edge(clk) THEN
IF clkena_in='1' AND get_movem_mask='1' THEN
movem_mask <= data_read(15 downto 0);
END IF;
IF clkena='1' THEN
IF set_movem_busy='1' THEN
IF movem_bits(3 downto 1) /= "000" OR opcode(10)='0' THEN
movem_busy <= '1';
END IF;
movem_addr <= '1';
END IF;
IF movem_addr='1' THEN
CASE movem_regaddr IS
WHEN "0000" => movem_mask(0) <= '0';
WHEN "0001" => movem_mask(1) <= '0';
WHEN "0010" => movem_mask(2) <= '0';
WHEN "0011" => movem_mask(3) <= '0';
WHEN "0100" => movem_mask(4) <= '0';
WHEN "0101" => movem_mask(5) <= '0';
WHEN "0110" => movem_mask(6) <= '0';
WHEN "0111" => movem_mask(7) <= '0';
WHEN "1000" => movem_mask(8) <= '0';
WHEN "1001" => movem_mask(9) <= '0';
WHEN "1010" => movem_mask(10) <= '0';
WHEN "1011" => movem_mask(11) <= '0';
WHEN "1100" => movem_mask(12) <= '0';
WHEN "1101" => movem_mask(13) <= '0';
WHEN "1110" => movem_mask(14) <= '0';
WHEN "1111" => movem_mask(15) <= '0';
WHEN OTHERS => null;
END CASE;
IF opcode(10)='1' THEN
IF movem_bits="00010" OR movem_bits="00001" OR movem_bits="00000" THEN
movem_busy <= '0';
END IF;
END IF;
IF movem_bits="00001" OR movem_bits="00000" THEN
movem_busy <= '0';
movem_addr <= '0';
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END;
/tg68/trunk/VHDL/TG68.vhd
0,0 → 1,224
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- --
-- This is the TOP-Level for TG68_fast to generate 68K Bus signals --
-- --
-- Copyright (c) 2007-2008 Tobias Gubener <tobiflex@opencores.org> --
-- --
-- This source file is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU Lesser General Public License as published --
-- by the Free Software Foundation, either version 3 of the License, or --
-- (at your option) any later version. --
-- --
-- This source file is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
-- --
------------------------------------------------------------------------------
------------------------------------------------------------------------------
--
-- Revision 1.02 2008/01/23
-- bugfix Timing
--
-- Revision 1.01 2007/11/28
-- add MOVEP
-- Bugfix Interrupt in MOVEQ
--
-- Revision 1.0 2007/11/05
-- Clean up code and first release
--
-- known bugs/todo:
-- Add CHK INSTRUCTION
-- full decode ILLEGAL INSTRUCTIONS
-- Add FDC Output
-- add odd Address test
-- add TRACE
-- Movem with regmask==x0000
 
 
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity TG68 is
port(
clk : in std_logic;
reset : in std_logic;
clkena_in : in std_logic:='1';
data_in : in std_logic_vector(15 downto 0);
IPL : in std_logic_vector(2 downto 0):="111";
dtack : in std_logic;
addr : out std_logic_vector(31 downto 0);
data_out : out std_logic_vector(15 downto 0);
as : out std_logic;
uds : out std_logic;
lds : out std_logic;
rw : out std_logic;
drive_data : out std_logic --enable for data_out driver
);
end TG68;
 
ARCHITECTURE logic OF TG68 IS
 
COMPONENT TG68_fast
PORT (
clk : in std_logic;
reset : in std_logic;
clkena_in : in std_logic;
data_in : in std_logic_vector(15 downto 0);
IPL : in std_logic_vector(2 downto 0);
test_IPL : in std_logic;
address : out std_logic_vector(31 downto 0);
data_write : out std_logic_vector(15 downto 0);
state_out : out std_logic_vector(1 downto 0);
decodeOPC : buffer std_logic;
wr : out std_logic;
UDS, LDS : out std_logic
);
END COMPONENT;
 
 
SIGNAL as_s : std_logic;
SIGNAL as_e : std_logic;
SIGNAL uds_s : std_logic;
SIGNAL uds_e : std_logic;
SIGNAL lds_s : std_logic;
SIGNAL lds_e : std_logic;
SIGNAL rw_s : std_logic;
SIGNAL rw_e : std_logic;
SIGNAL waitm : std_logic;
SIGNAL clkena_e : std_logic;
SIGNAL S_state : std_logic_vector(1 downto 0);
SIGNAL decode : std_logic;
SIGNAL wr : std_logic;
SIGNAL uds_in : std_logic;
SIGNAL lds_in : std_logic;
SIGNAL state : std_logic_vector(1 downto 0);
SIGNAL clkena : std_logic;
SIGNAL n_clk : std_logic;
SIGNAL cpuIPL : std_logic_vector(2 downto 0);
 
 
BEGIN
 
n_clk <= NOT clk;
 
TG68_fast_inst: TG68_fast
PORT MAP (
clk => n_clk, -- : in std_logic;
reset => reset, -- : in std_logic;
clkena_in => clkena, -- : in std_logic;
data_in => data_in, -- : in std_logic_vector(15 downto 0);
IPL => cpuIPL, -- : in std_logic_vector(2 downto 0);
test_IPL => '0', -- : in std_logic;
address => addr, -- : out std_logic_vector(31 downto 0);
data_write => data_out, -- : out std_logic_vector(15 downto 0);
state_out => state, -- : out std_logic_vector(1 downto 0);
decodeOPC => decode, -- : buffer std_logic;
wr => wr, -- : out std_logic;
UDS => uds_in, -- : out std_logic;
LDS => lds_in -- : out std_logic;
);
PROCESS (clk)
BEGIN
IF clkena_in='1' AND (clkena_e='1' OR state="01") THEN
clkena <= '1';
ELSE
clkena <= '0';
END IF;
END PROCESS;
PROCESS (clk, reset, state, as_s, as_e, rw_s, rw_e, uds_s, uds_e, lds_s, lds_e)
BEGIN
IF state="01" THEN
as <= '1';
rw <= '1';
uds <= '1';
lds <= '1';
ELSE
as <= as_s AND as_e;
rw <= rw_s AND rw_e;
uds <= uds_s AND uds_e;
lds <= lds_s AND lds_e;
END IF;
IF reset='0' THEN
S_state <= "11";
as_s <= '1';
rw_s <= '1';
uds_s <= '1';
lds_s <= '1';
ELSIF rising_edge(clk) THEN
IF clkena_in='1' THEN
as_s <= '1';
rw_s <= '1';
uds_s <= '1';
lds_s <= '1';
IF state/="01" OR decode='1' THEN
CASE S_state IS
WHEN "00" => as_s <= '0';
rw_s <= wr;
IF wr='1' THEN
uds_s <= uds_in;
lds_s <= lds_in;
END IF;
S_state <= "01";
WHEN "01" => as_s <= '0';
rw_s <= wr;
uds_s <= uds_in;
lds_s <= lds_in;
S_state <= "10";
WHEN "10" =>
rw_s <= wr;
IF waitm='0' THEN
S_state <= "11";
END IF;
WHEN "11" =>
S_state <= "00";
WHEN OTHERS => null;
END CASE;
END IF;
END IF;
END IF;
IF reset='0' THEN
as_e <= '1';
rw_e <= '1';
uds_e <= '1';
lds_e <= '1';
clkena_e <= '0';
cpuIPL <= "111";
drive_data <= '0';
ELSIF falling_edge(clk) THEN
IF clkena_in='1' THEN
as_e <= '1';
rw_e <= '1';
uds_e <= '1';
lds_e <= '1';
clkena_e <= '0';
drive_data <= '0';
CASE S_state IS
WHEN "00" => null;
WHEN "01" => drive_data <= NOT wr;
WHEN "10" => as_e <= '0';
uds_e <= uds_in;
lds_e <= lds_in;
cpuIPL <= IPL;
drive_data <= NOT wr;
IF state="01" THEN
clkena_e <= '1';
waitm <= '0';
ELSE
clkena_e <= NOT dtack;
waitm <= dtack;
END IF;
WHEN OTHERS => null;
END CASE;
END IF;
END IF;
END PROCESS;
END;
/tg68/trunk/gpl.txt
0,0 → 1,674
GNU GENERAL PUBLIC LICENSE
Version 3, 29 June 2007
 
Copyright (C) 2007 Free Software Foundation, Inc. <http://fsf.org/>
Everyone is permitted to copy and distribute verbatim copies
of this license document, but changing it is not allowed.
 
Preamble
 
The GNU General Public License is a free, copyleft license for
software and other kinds of works.
 
The licenses for most software and other practical works are designed
to take away your freedom to share and change the works. By contrast,
the GNU General Public License is intended to guarantee your freedom to
share and change all versions of a program--to make sure it remains free
software for all its users. We, the Free Software Foundation, use the
GNU General Public License for most of our software; it applies also to
any other work released this way by its authors. You can apply it to
your programs, too.
 
When we speak of free software, we are referring to freedom, not
price. Our General Public Licenses are designed to make sure that you
have the freedom to distribute copies of free software (and charge for
them if you wish), that you receive source code or can get it if you
want it, that you can change the software or use pieces of it in new
free programs, and that you know you can do these things.
 
To protect your rights, we need to prevent others from denying you
these rights or asking you to surrender the rights. Therefore, you have
certain responsibilities if you distribute copies of the software, or if
you modify it: responsibilities to respect the freedom of others.
 
For example, if you distribute copies of such a program, whether
gratis or for a fee, you must pass on to the recipients the same
freedoms that you received. You must make sure that they, too, receive
or can get the source code. And you must show them these terms so they
know their rights.
 
Developers that use the GNU GPL protect your rights with two steps:
(1) assert copyright on the software, and (2) offer you this License
giving you legal permission to copy, distribute and/or modify it.
 
For the developers' and authors' protection, the GPL clearly explains
that there is no warranty for this free software. For both users' and
authors' sake, the GPL requires that modified versions be marked as
changed, so that their problems will not be attributed erroneously to
authors of previous versions.
 
Some devices are designed to deny users access to install or run
modified versions of the software inside them, although the manufacturer
can do so. This is fundamentally incompatible with the aim of
protecting users' freedom to change the software. The systematic
pattern of such abuse occurs in the area of products for individuals to
use, which is precisely where it is most unacceptable. Therefore, we
have designed this version of the GPL to prohibit the practice for those
products. If such problems arise substantially in other domains, we
stand ready to extend this provision to those domains in future versions
of the GPL, as needed to protect the freedom of users.
 
Finally, every program is threatened constantly by software patents.
States should not allow patents to restrict development and use of
software on general-purpose computers, but in those that do, we wish to
avoid the special danger that patents applied to a free program could
make it effectively proprietary. To prevent this, the GPL assures that
patents cannot be used to render the program non-free.
 
The precise terms and conditions for copying, distribution and
modification follow.
 
TERMS AND CONDITIONS
 
0. Definitions.
 
"This License" refers to version 3 of the GNU General Public License.
 
"Copyright" also means copyright-like laws that apply to other kinds of
works, such as semiconductor masks.
 
"The Program" refers to any copyrightable work licensed under this
License. Each licensee is addressed as "you". "Licensees" and
"recipients" may be individuals or organizations.
 
To "modify" a work means to copy from or adapt all or part of the work
in a fashion requiring copyright permission, other than the making of an
exact copy. The resulting work is called a "modified version" of the
earlier work or a work "based on" the earlier work.
 
A "covered work" means either the unmodified Program or a work based
on the Program.
 
To "propagate" a work means to do anything with it that, without
permission, would make you directly or secondarily liable for
infringement under applicable copyright law, except executing it on a
computer or modifying a private copy. Propagation includes copying,
distribution (with or without modification), making available to the
public, and in some countries other activities as well.
 
To "convey" a work means any kind of propagation that enables other
parties to make or receive copies. Mere interaction with a user through
a computer network, with no transfer of a copy, is not conveying.
 
An interactive user interface displays "Appropriate Legal Notices"
to the extent that it includes a convenient and prominently visible
feature that (1) displays an appropriate copyright notice, and (2)
tells the user that there is no warranty for the work (except to the
extent that warranties are provided), that licensees may convey the
work under this License, and how to view a copy of this License. If
the interface presents a list of user commands or options, such as a
menu, a prominent item in the list meets this criterion.
 
1. Source Code.
 
The "source code" for a work means the preferred form of the work
for making modifications to it. "Object code" means any non-source
form of a work.
 
A "Standard Interface" means an interface that either is an official
standard defined by a recognized standards body, or, in the case of
interfaces specified for a particular programming language, one that
is widely used among developers working in that language.
 
The "System Libraries" of an executable work include anything, other
than the work as a whole, that (a) is included in the normal form of
packaging a Major Component, but which is not part of that Major
Component, and (b) serves only to enable use of the work with that
Major Component, or to implement a Standard Interface for which an
implementation is available to the public in source code form. A
"Major Component", in this context, means a major essential component
(kernel, window system, and so on) of the specific operating system
(if any) on which the executable work runs, or a compiler used to
produce the work, or an object code interpreter used to run it.
 
The "Corresponding Source" for a work in object code form means all
the source code needed to generate, install, and (for an executable
work) run the object code and to modify the work, including scripts to
control those activities. However, it does not include the work's
System Libraries, or general-purpose tools or generally available free
programs which are used unmodified in performing those activities but
which are not part of the work. For example, Corresponding Source
includes interface definition files associated with source files for
the work, and the source code for shared libraries and dynamically
linked subprograms that the work is specifically designed to require,
such as by intimate data communication or control flow between those
subprograms and other parts of the work.
 
The Corresponding Source need not include anything that users
can regenerate automatically from other parts of the Corresponding
Source.
 
The Corresponding Source for a work in source code form is that
same work.
 
2. Basic Permissions.
 
All rights granted under this License are granted for the term of
copyright on the Program, and are irrevocable provided the stated
conditions are met. This License explicitly affirms your unlimited
permission to run the unmodified Program. The output from running a
covered work is covered by this License only if the output, given its
content, constitutes a covered work. This License acknowledges your
rights of fair use or other equivalent, as provided by copyright law.
 
You may make, run and propagate covered works that you do not
convey, without conditions so long as your license otherwise remains
in force. You may convey covered works to others for the sole purpose
of having them make modifications exclusively for you, or provide you
with facilities for running those works, provided that you comply with
the terms of this License in conveying all material for which you do
not control copyright. Those thus making or running the covered works
for you must do so exclusively on your behalf, under your direction
and control, on terms that prohibit them from making any copies of
your copyrighted material outside their relationship with you.
 
Conveying under any other circumstances is permitted solely under
the conditions stated below. Sublicensing is not allowed; section 10
makes it unnecessary.
 
3. Protecting Users' Legal Rights From Anti-Circumvention Law.
 
No covered work shall be deemed part of an effective technological
measure under any applicable law fulfilling obligations under article
11 of the WIPO copyright treaty adopted on 20 December 1996, or
similar laws prohibiting or restricting circumvention of such
measures.
 
When you convey a covered work, you waive any legal power to forbid
circumvention of technological measures to the extent such circumvention
is effected by exercising rights under this License with respect to
the covered work, and you disclaim any intention to limit operation or
modification of the work as a means of enforcing, against the work's
users, your or third parties' legal rights to forbid circumvention of
technological measures.
 
4. Conveying Verbatim Copies.
 
You may convey verbatim copies of the Program's source code as you
receive it, in any medium, provided that you conspicuously and
appropriately publish on each copy an appropriate copyright notice;
keep intact all notices stating that this License and any
non-permissive terms added in accord with section 7 apply to the code;
keep intact all notices of the absence of any warranty; and give all
recipients a copy of this License along with the Program.
 
You may charge any price or no price for each copy that you convey,
and you may offer support or warranty protection for a fee.
 
5. Conveying Modified Source Versions.
 
You may convey a work based on the Program, or the modifications to
produce it from the Program, in the form of source code under the
terms of section 4, provided that you also meet all of these conditions:
 
a) The work must carry prominent notices stating that you modified
it, and giving a relevant date.
 
b) The work must carry prominent notices stating that it is
released under this License and any conditions added under section
7. This requirement modifies the requirement in section 4 to
"keep intact all notices".
 
c) You must license the entire work, as a whole, under this
License to anyone who comes into possession of a copy. This
License will therefore apply, along with any applicable section 7
additional terms, to the whole of the work, and all its parts,
regardless of how they are packaged. This License gives no
permission to license the work in any other way, but it does not
invalidate such permission if you have separately received it.
 
d) If the work has interactive user interfaces, each must display
Appropriate Legal Notices; however, if the Program has interactive
interfaces that do not display Appropriate Legal Notices, your
work need not make them do so.
 
A compilation of a covered work with other separate and independent
works, which are not by their nature extensions of the covered work,
and which are not combined with it such as to form a larger program,
in or on a volume of a storage or distribution medium, is called an
"aggregate" if the compilation and its resulting copyright are not
used to limit the access or legal rights of the compilation's users
beyond what the individual works permit. Inclusion of a covered work
in an aggregate does not cause this License to apply to the other
parts of the aggregate.
 
6. Conveying Non-Source Forms.
 
You may convey a covered work in object code form under the terms
of sections 4 and 5, provided that you also convey the
machine-readable Corresponding Source under the terms of this License,
in one of these ways:
 
a) Convey the object code in, or embodied in, a physical product
(including a physical distribution medium), accompanied by the
Corresponding Source fixed on a durable physical medium
customarily used for software interchange.
 
b) Convey the object code in, or embodied in, a physical product
(including a physical distribution medium), accompanied by a
written offer, valid for at least three years and valid for as
long as you offer spare parts or customer support for that product
model, to give anyone who possesses the object code either (1) a
copy of the Corresponding Source for all the software in the
product that is covered by this License, on a durable physical
medium customarily used for software interchange, for a price no
more than your reasonable cost of physically performing this
conveying of source, or (2) access to copy the
Corresponding Source from a network server at no charge.
 
c) Convey individual copies of the object code with a copy of the
written offer to provide the Corresponding Source. This
alternative is allowed only occasionally and noncommercially, and
only if you received the object code with such an offer, in accord
with subsection 6b.
 
d) Convey the object code by offering access from a designated
place (gratis or for a charge), and offer equivalent access to the
Corresponding Source in the same way through the same place at no
further charge. You need not require recipients to copy the
Corresponding Source along with the object code. If the place to
copy the object code is a network server, the Corresponding Source
may be on a different server (operated by you or a third party)
that supports equivalent copying facilities, provided you maintain
clear directions next to the object code saying where to find the
Corresponding Source. Regardless of what server hosts the
Corresponding Source, you remain obligated to ensure that it is
available for as long as needed to satisfy these requirements.
 
e) Convey the object code using peer-to-peer transmission, provided
you inform other peers where the object code and Corresponding
Source of the work are being offered to the general public at no
charge under subsection 6d.
 
A separable portion of the object code, whose source code is excluded
from the Corresponding Source as a System Library, need not be
included in conveying the object code work.
 
A "User Product" is either (1) a "consumer product", which means any
tangible personal property which is normally used for personal, family,
or household purposes, or (2) anything designed or sold for incorporation
into a dwelling. In determining whether a product is a consumer product,
doubtful cases shall be resolved in favor of coverage. For a particular
product received by a particular user, "normally used" refers to a
typical or common use of that class of product, regardless of the status
of the particular user or of the way in which the particular user
actually uses, or expects or is expected to use, the product. A product
is a consumer product regardless of whether the product has substantial
commercial, industrial or non-consumer uses, unless such uses represent
the only significant mode of use of the product.
 
"Installation Information" for a User Product means any methods,
procedures, authorization keys, or other information required to install
and execute modified versions of a covered work in that User Product from
a modified version of its Corresponding Source. The information must
suffice to ensure that the continued functioning of the modified object
code is in no case prevented or interfered with solely because
modification has been made.
 
If you convey an object code work under this section in, or with, or
specifically for use in, a User Product, and the conveying occurs as
part of a transaction in which the right of possession and use of the
User Product is transferred to the recipient in perpetuity or for a
fixed term (regardless of how the transaction is characterized), the
Corresponding Source conveyed under this section must be accompanied
by the Installation Information. But this requirement does not apply
if neither you nor any third party retains the ability to install
modified object code on the User Product (for example, the work has
been installed in ROM).
 
The requirement to provide Installation Information does not include a
requirement to continue to provide support service, warranty, or updates
for a work that has been modified or installed by the recipient, or for
the User Product in which it has been modified or installed. Access to a
network may be denied when the modification itself materially and
adversely affects the operation of the network or violates the rules and
protocols for communication across the network.
 
Corresponding Source conveyed, and Installation Information provided,
in accord with this section must be in a format that is publicly
documented (and with an implementation available to the public in
source code form), and must require no special password or key for
unpacking, reading or copying.
 
7. Additional Terms.
 
"Additional permissions" are terms that supplement the terms of this
License by making exceptions from one or more of its conditions.
Additional permissions that are applicable to the entire Program shall
be treated as though they were included in this License, to the extent
that they are valid under applicable law. If additional permissions
apply only to part of the Program, that part may be used separately
under those permissions, but the entire Program remains governed by
this License without regard to the additional permissions.
 
When you convey a copy of a covered work, you may at your option
remove any additional permissions from that copy, or from any part of
it. (Additional permissions may be written to require their own
removal in certain cases when you modify the work.) You may place
additional permissions on material, added by you to a covered work,
for which you have or can give appropriate copyright permission.
 
Notwithstanding any other provision of this License, for material you
add to a covered work, you may (if authorized by the copyright holders of
that material) supplement the terms of this License with terms:
 
a) Disclaiming warranty or limiting liability differently from the
terms of sections 15 and 16 of this License; or
 
b) Requiring preservation of specified reasonable legal notices or
author attributions in that material or in the Appropriate Legal
Notices displayed by works containing it; or
 
c) Prohibiting misrepresentation of the origin of that material, or
requiring that modified versions of such material be marked in
reasonable ways as different from the original version; or
 
d) Limiting the use for publicity purposes of names of licensors or
authors of the material; or
 
e) Declining to grant rights under trademark law for use of some
trade names, trademarks, or service marks; or
 
f) Requiring indemnification of licensors and authors of that
material by anyone who conveys the material (or modified versions of
it) with contractual assumptions of liability to the recipient, for
any liability that these contractual assumptions directly impose on
those licensors and authors.
 
All other non-permissive additional terms are considered "further
restrictions" within the meaning of section 10. If the Program as you
received it, or any part of it, contains a notice stating that it is
governed by this License along with a term that is a further
restriction, you may remove that term. If a license document contains
a further restriction but permits relicensing or conveying under this
License, you may add to a covered work material governed by the terms
of that license document, provided that the further restriction does
not survive such relicensing or conveying.
 
If you add terms to a covered work in accord with this section, you
must place, in the relevant source files, a statement of the
additional terms that apply to those files, or a notice indicating
where to find the applicable terms.
 
Additional terms, permissive or non-permissive, may be stated in the
form of a separately written license, or stated as exceptions;
the above requirements apply either way.
 
8. Termination.
 
You may not propagate or modify a covered work except as expressly
provided under this License. Any attempt otherwise to propagate or
modify it is void, and will automatically terminate your rights under
this License (including any patent licenses granted under the third
paragraph of section 11).
 
However, if you cease all violation of this License, then your
license from a particular copyright holder is reinstated (a)
provisionally, unless and until the copyright holder explicitly and
finally terminates your license, and (b) permanently, if the copyright
holder fails to notify you of the violation by some reasonable means
prior to 60 days after the cessation.
 
Moreover, your license from a particular copyright holder is
reinstated permanently if the copyright holder notifies you of the
violation by some reasonable means, this is the first time you have
received notice of violation of this License (for any work) from that
copyright holder, and you cure the violation prior to 30 days after
your receipt of the notice.
 
Termination of your rights under this section does not terminate the
licenses of parties who have received copies or rights from you under
this License. If your rights have been terminated and not permanently
reinstated, you do not qualify to receive new licenses for the same
material under section 10.
 
9. Acceptance Not Required for Having Copies.
 
You are not required to accept this License in order to receive or
run a copy of the Program. Ancillary propagation of a covered work
occurring solely as a consequence of using peer-to-peer transmission
to receive a copy likewise does not require acceptance. However,
nothing other than this License grants you permission to propagate or
modify any covered work. These actions infringe copyright if you do
not accept this License. Therefore, by modifying or propagating a
covered work, you indicate your acceptance of this License to do so.
 
10. Automatic Licensing of Downstream Recipients.
 
Each time you convey a covered work, the recipient automatically
receives a license from the original licensors, to run, modify and
propagate that work, subject to this License. You are not responsible
for enforcing compliance by third parties with this License.
 
An "entity transaction" is a transaction transferring control of an
organization, or substantially all assets of one, or subdividing an
organization, or merging organizations. If propagation of a covered
work results from an entity transaction, each party to that
transaction who receives a copy of the work also receives whatever
licenses to the work the party's predecessor in interest had or could
give under the previous paragraph, plus a right to possession of the
Corresponding Source of the work from the predecessor in interest, if
the predecessor has it or can get it with reasonable efforts.
 
You may not impose any further restrictions on the exercise of the
rights granted or affirmed under this License. For example, you may
not impose a license fee, royalty, or other charge for exercise of
rights granted under this License, and you may not initiate litigation
(including a cross-claim or counterclaim in a lawsuit) alleging that
any patent claim is infringed by making, using, selling, offering for
sale, or importing the Program or any portion of it.
 
11. Patents.
 
A "contributor" is a copyright holder who authorizes use under this
License of the Program or a work on which the Program is based. The
work thus licensed is called the contributor's "contributor version".
 
A contributor's "essential patent claims" are all patent claims
owned or controlled by the contributor, whether already acquired or
hereafter acquired, that would be infringed by some manner, permitted
by this License, of making, using, or selling its contributor version,
but do not include claims that would be infringed only as a
consequence of further modification of the contributor version. For
purposes of this definition, "control" includes the right to grant
patent sublicenses in a manner consistent with the requirements of
this License.
 
Each contributor grants you a non-exclusive, worldwide, royalty-free
patent license under the contributor's essential patent claims, to
make, use, sell, offer for sale, import and otherwise run, modify and
propagate the contents of its contributor version.
 
In the following three paragraphs, a "patent license" is any express
agreement or commitment, however denominated, not to enforce a patent
(such as an express permission to practice a patent or covenant not to
sue for patent infringement). To "grant" such a patent license to a
party means to make such an agreement or commitment not to enforce a
patent against the party.
 
If you convey a covered work, knowingly relying on a patent license,
and the Corresponding Source of the work is not available for anyone
to copy, free of charge and under the terms of this License, through a
publicly available network server or other readily accessible means,
then you must either (1) cause the Corresponding Source to be so
available, or (2) arrange to deprive yourself of the benefit of the
patent license for this particular work, or (3) arrange, in a manner
consistent with the requirements of this License, to extend the patent
license to downstream recipients. "Knowingly relying" means you have
actual knowledge that, but for the patent license, your conveying the
covered work in a country, or your recipient's use of the covered work
in a country, would infringe one or more identifiable patents in that
country that you have reason to believe are valid.
 
If, pursuant to or in connection with a single transaction or
arrangement, you convey, or propagate by procuring conveyance of, a
covered work, and grant a patent license to some of the parties
receiving the covered work authorizing them to use, propagate, modify
or convey a specific copy of the covered work, then the patent license
you grant is automatically extended to all recipients of the covered
work and works based on it.
 
A patent license is "discriminatory" if it does not include within
the scope of its coverage, prohibits the exercise of, or is
conditioned on the non-exercise of one or more of the rights that are
specifically granted under this License. You may not convey a covered
work if you are a party to an arrangement with a third party that is
in the business of distributing software, under which you make payment
to the third party based on the extent of your activity of conveying
the work, and under which the third party grants, to any of the
parties who would receive the covered work from you, a discriminatory
patent license (a) in connection with copies of the covered work
conveyed by you (or copies made from those copies), or (b) primarily
for and in connection with specific products or compilations that
contain the covered work, unless you entered into that arrangement,
or that patent license was granted, prior to 28 March 2007.
 
Nothing in this License shall be construed as excluding or limiting
any implied license or other defenses to infringement that may
otherwise be available to you under applicable patent law.
 
12. No Surrender of Others' Freedom.
 
If conditions are imposed on you (whether by court order, agreement or
otherwise) that contradict the conditions of this License, they do not
excuse you from the conditions of this License. If you cannot convey a
covered work so as to satisfy simultaneously your obligations under this
License and any other pertinent obligations, then as a consequence you may
not convey it at all. For example, if you agree to terms that obligate you
to collect a royalty for further conveying from those to whom you convey
the Program, the only way you could satisfy both those terms and this
License would be to refrain entirely from conveying the Program.
 
13. Use with the GNU Affero General Public License.
 
Notwithstanding any other provision of this License, you have
permission to link or combine any covered work with a work licensed
under version 3 of the GNU Affero General Public License into a single
combined work, and to convey the resulting work. The terms of this
License will continue to apply to the part which is the covered work,
but the special requirements of the GNU Affero General Public License,
section 13, concerning interaction through a network will apply to the
combination as such.
 
14. Revised Versions of this License.
 
The Free Software Foundation may publish revised and/or new versions of
the GNU General Public License from time to time. Such new versions will
be similar in spirit to the present version, but may differ in detail to
address new problems or concerns.
 
Each version is given a distinguishing version number. If the
Program specifies that a certain numbered version of the GNU General
Public License "or any later version" applies to it, you have the
option of following the terms and conditions either of that numbered
version or of any later version published by the Free Software
Foundation. If the Program does not specify a version number of the
GNU General Public License, you may choose any version ever published
by the Free Software Foundation.
 
If the Program specifies that a proxy can decide which future
versions of the GNU General Public License can be used, that proxy's
public statement of acceptance of a version permanently authorizes you
to choose that version for the Program.
 
Later license versions may give you additional or different
permissions. However, no additional obligations are imposed on any
author or copyright holder as a result of your choosing to follow a
later version.
 
15. Disclaimer of Warranty.
 
THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY
APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT
HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY
OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO,
THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM
IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF
ALL NECESSARY SERVICING, REPAIR OR CORRECTION.
 
16. Limitation of Liability.
 
IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES AND/OR CONVEYS
THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY
GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE
USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF
DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD
PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS),
EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF
SUCH DAMAGES.
 
17. Interpretation of Sections 15 and 16.
 
If the disclaimer of warranty and limitation of liability provided
above cannot be given local legal effect according to their terms,
reviewing courts shall apply local law that most closely approximates
an absolute waiver of all civil liability in connection with the
Program, unless a warranty or assumption of liability accompanies a
copy of the Program in return for a fee.
 
END OF TERMS AND CONDITIONS
 
How to Apply These Terms to Your New Programs
 
If you develop a new program, and you want it to be of the greatest
possible use to the public, the best way to achieve this is to make it
free software which everyone can redistribute and change under these terms.
 
To do so, attach the following notices to the program. It is safest
to attach them to the start of each source file to most effectively
state the exclusion of warranty; and each file should have at least
the "copyright" line and a pointer to where the full notice is found.
 
<one line to give the program's name and a brief idea of what it does.>
Copyright (C) <year> <name of author>
 
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
 
Also add information on how to contact you by electronic and paper mail.
 
If the program does terminal interaction, make it output a short
notice like this when it starts in an interactive mode:
 
<program> Copyright (C) <year> <name of author>
This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
 
The hypothetical commands `show w' and `show c' should show the appropriate
parts of the General Public License. Of course, your program's commands
might be different; for a GUI interface, you would use an "about box".
 
You should also get your employer (if you work as a programmer) or school,
if any, to sign a "copyright disclaimer" for the program, if necessary.
For more information on this, and how to apply and follow the GNU GPL, see
<http://www.gnu.org/licenses/>.
 
The GNU General Public License does not permit incorporating your program
into proprietary programs. If your program is a subroutine library, you
may consider it more useful to permit linking proprietary applications with
the library. If this is what you want to do, use the GNU Lesser General
Public License instead of this License. But first, please read
<http://www.gnu.org/philosophy/why-not-lgpl.html>.
/tg68/trunk/lgpl.txt
0,0 → 1,165
GNU LESSER GENERAL PUBLIC LICENSE
Version 3, 29 June 2007
 
Copyright (C) 2007 Free Software Foundation, Inc. <http://fsf.org/>
Everyone is permitted to copy and distribute verbatim copies
of this license document, but changing it is not allowed.
 
 
This version of the GNU Lesser General Public License incorporates
the terms and conditions of version 3 of the GNU General Public
License, supplemented by the additional permissions listed below.
 
0. Additional Definitions.
 
As used herein, "this License" refers to version 3 of the GNU Lesser
General Public License, and the "GNU GPL" refers to version 3 of the GNU
General Public License.
 
"The Library" refers to a covered work governed by this License,
other than an Application or a Combined Work as defined below.
 
An "Application" is any work that makes use of an interface provided
by the Library, but which is not otherwise based on the Library.
Defining a subclass of a class defined by the Library is deemed a mode
of using an interface provided by the Library.
 
A "Combined Work" is a work produced by combining or linking an
Application with the Library. The particular version of the Library
with which the Combined Work was made is also called the "Linked
Version".
 
The "Minimal Corresponding Source" for a Combined Work means the
Corresponding Source for the Combined Work, excluding any source code
for portions of the Combined Work that, considered in isolation, are
based on the Application, and not on the Linked Version.
 
The "Corresponding Application Code" for a Combined Work means the
object code and/or source code for the Application, including any data
and utility programs needed for reproducing the Combined Work from the
Application, but excluding the System Libraries of the Combined Work.
 
1. Exception to Section 3 of the GNU GPL.
 
You may convey a covered work under sections 3 and 4 of this License
without being bound by section 3 of the GNU GPL.
 
2. Conveying Modified Versions.
 
If you modify a copy of the Library, and, in your modifications, a
facility refers to a function or data to be supplied by an Application
that uses the facility (other than as an argument passed when the
facility is invoked), then you may convey a copy of the modified
version:
 
a) under this License, provided that you make a good faith effort to
ensure that, in the event an Application does not supply the
function or data, the facility still operates, and performs
whatever part of its purpose remains meaningful, or
 
b) under the GNU GPL, with none of the additional permissions of
this License applicable to that copy.
 
3. Object Code Incorporating Material from Library Header Files.
 
The object code form of an Application may incorporate material from
a header file that is part of the Library. You may convey such object
code under terms of your choice, provided that, if the incorporated
material is not limited to numerical parameters, data structure
layouts and accessors, or small macros, inline functions and templates
(ten or fewer lines in length), you do both of the following:
 
a) Give prominent notice with each copy of the object code that the
Library is used in it and that the Library and its use are
covered by this License.
 
b) Accompany the object code with a copy of the GNU GPL and this license
document.
 
4. Combined Works.
 
You may convey a Combined Work under terms of your choice that,
taken together, effectively do not restrict modification of the
portions of the Library contained in the Combined Work and reverse
engineering for debugging such modifications, if you also do each of
the following:
 
a) Give prominent notice with each copy of the Combined Work that
the Library is used in it and that the Library and its use are
covered by this License.
 
b) Accompany the Combined Work with a copy of the GNU GPL and this license
document.
 
c) For a Combined Work that displays copyright notices during
execution, include the copyright notice for the Library among
these notices, as well as a reference directing the user to the
copies of the GNU GPL and this license document.
 
d) Do one of the following:
 
0) Convey the Minimal Corresponding Source under the terms of this
License, and the Corresponding Application Code in a form
suitable for, and under terms that permit, the user to
recombine or relink the Application with a modified version of
the Linked Version to produce a modified Combined Work, in the
manner specified by section 6 of the GNU GPL for conveying
Corresponding Source.
 
1) Use a suitable shared library mechanism for linking with the
Library. A suitable mechanism is one that (a) uses at run time
a copy of the Library already present on the user's computer
system, and (b) will operate properly with a modified version
of the Library that is interface-compatible with the Linked
Version.
 
e) Provide Installation Information, but only if you would otherwise
be required to provide such information under section 6 of the
GNU GPL, and only to the extent that such information is
necessary to install and execute a modified version of the
Combined Work produced by recombining or relinking the
Application with a modified version of the Linked Version. (If
you use option 4d0, the Installation Information must accompany
the Minimal Corresponding Source and Corresponding Application
Code. If you use option 4d1, you must provide the Installation
Information in the manner specified by section 6 of the GNU GPL
for conveying Corresponding Source.)
 
5. Combined Libraries.
 
You may place library facilities that are a work based on the
Library side by side in a single library together with other library
facilities that are not Applications and are not covered by this
License, and convey such a combined library under terms of your
choice, if you do both of the following:
 
a) Accompany the combined library with a copy of the same work based
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tg68/trunk Property changes : Added: svn:mergeinfo ## -0,0 +0,0 ## Index: tg68/web_uploads =================================================================== --- tg68/web_uploads (nonexistent) +++ tg68/web_uploads (revision 10)
tg68/web_uploads Property changes : Added: svn:mergeinfo ## -0,0 +0,0 ## Index: tg68/branches =================================================================== --- tg68/branches (nonexistent) +++ tg68/branches (revision 10)
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Index: tg68/tags/arelease/VHDL/TG68_fast.vhd =================================================================== --- tg68/tags/arelease/VHDL/TG68_fast.vhd (nonexistent) +++ tg68/tags/arelease/VHDL/TG68_fast.vhd (revision 10) @@ -0,0 +1,3034 @@ +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ +-- -- +-- This is the 68000 software compatible Kernal of TG68 -- +-- -- +-- Copyright (c) 2007 Tobias Gubener -- +-- -- +-- This source file is free software: you can redistribute it and/or modify -- +-- it under the terms of the GNU Lesser General Public License as published -- +-- by the Free Software Foundation, either version 3 of the License, or -- +-- (at your option) any later version. -- +-- -- +-- This source file is distributed in the hope that it will be useful, -- +-- but WITHOUT ANY WARRANTY; without even the implied warranty of -- +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- +-- GNU General Public License for more details. -- +-- -- +-- You should have received a copy of the GNU General Public License -- +-- along with this program. If not, see . -- +-- -- +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ +-- +-- Revision 1.0 2007/11/05 +-- Clean up code and first release +-- +-- known bugs/todo: +-- Add CHK INSTRUCTION +-- Add MOVEP INSTRUCTION +-- full decode ILLEGAL INSTRUCTIONS +-- Add FDC Output +-- add odd Address test +-- add TRACE +-- Movem with regmask==x0000 + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity TG68_fast is + port(clk : in std_logic; + reset : in std_logic; --low active + clkena_in : in std_logic:='1'; + data_in : in std_logic_vector(15 downto 0); + IPL : in std_logic_vector(2 downto 0):="111"; + test_IPL : in std_logic:='0'; --only for debugging + address : out std_logic_vector(31 downto 0); + data_write : out std_logic_vector(15 downto 0); + state_out : out std_logic_vector(1 downto 0); + decodeOPC : buffer std_logic; + wr : out std_logic; + UDS, LDS : out std_logic + ); +end TG68_fast; + +architecture logic of TG68_fast is + + signal state : std_logic_vector(1 downto 0); + signal clkena : std_logic; + signal TG68_PC : std_logic_vector(31 downto 0); + signal TG68_PC_add : std_logic_vector(31 downto 0); + signal memaddr : std_logic_vector(31 downto 0); + signal memaddr_in : std_logic_vector(31 downto 0); + signal ea_data : std_logic_vector(31 downto 0); + signal ea_data_OP1 : std_logic; + signal setaddrlong : std_logic; + signal OP1out, OP2out : std_logic_vector(31 downto 0); + signal OP1outbrief : std_logic_vector(15 downto 0); + signal OP1in : std_logic_vector(31 downto 0); + signal data_write_tmp : std_logic_vector(31 downto 0); + signal Xtmp : std_logic_vector(31 downto 0); + signal PC_dataa, PC_datab, PC_result : std_logic_vector(31 downto 0); + signal setregstore : std_logic; + signal datatype : std_logic_vector(1 downto 0); + signal longread : std_logic; + signal longreaddirect : std_logic; + signal long_done : std_logic; + signal nextpass : std_logic; + signal setnextpass : std_logic; + signal setdispbyte : std_logic; + signal setdisp : std_logic; + signal setdispbrief : std_logic; + signal prefix : std_logic; + signal regdirectsource : std_logic; + signal endOPC : std_logic; + signal postadd : std_logic; + signal presub : std_logic; + signal addsub_a : std_logic_vector(31 downto 0); + signal addsub_b : std_logic_vector(31 downto 0); + signal addsub_q : std_logic_vector(31 downto 0); + signal briefext : std_logic_vector(31 downto 0); + signal setbriefext : std_logic; + signal addsub : std_logic; + signal c_in : std_logic_vector(3 downto 0); + signal c_out : std_logic_vector(2 downto 0); + signal add_result : std_logic_vector(33 downto 0); + signal addsub_ofl : std_logic_vector(2 downto 0); + signal flag_z : std_logic_vector(2 downto 0); + + signal last_data_read : std_logic_vector(15 downto 0); + signal data_read : std_logic_vector(31 downto 0); + signal microaddr : std_logic_vector(7 downto 0); + signal micronext : std_logic_vector(7 downto 0); + signal microstep : std_logic; + signal microset : std_logic; + + signal registerin : std_logic_vector(31 downto 0); + signal reg_QA : std_logic_vector(31 downto 0); + signal reg_QB : std_logic_vector(31 downto 0); + signal Hwrena,Lwrena : std_logic; + signal Regwrena : std_logic; + signal rf_dest_addr : std_logic_vector(6 downto 0); + signal rf_source_addr : std_logic_vector(6 downto 0); + signal rf_dest_addr_tmp : std_logic_vector(6 downto 0); + signal rf_source_addr_tmp : std_logic_vector(6 downto 0); + signal opcode : std_logic_vector(15 downto 0); + signal laststate : std_logic_vector(1 downto 0); + signal setstate : std_logic_vector(1 downto 0); + + signal mem_address : std_logic_vector(31 downto 0); + signal memaddr_a : std_logic_vector(31 downto 0); + signal mem_data_read : std_logic_vector(31 downto 0); + signal mem_data_write : std_logic_vector(31 downto 0); + signal set_mem_rega : std_logic; + signal data_read_ram : std_logic_vector(31 downto 0); + signal data_read_uart : std_logic_vector(7 downto 0); + + signal counter_reg : std_logic_vector(31 downto 0); + + signal TG68_PC_br8 : std_logic; + signal TG68_PC_brw : std_logic; + signal TG68_PC_nop : std_logic; + signal setgetbrief : std_logic; + signal getbrief : std_logic; + signal brief : std_logic_vector(15 downto 0); + signal dest_areg : std_logic; + signal source_areg : std_logic; + signal data_is_source : std_logic; + signal set_store_in_tmp : std_logic; + signal store_in_tmp : std_logic; + signal write_back : std_logic; + signal setaddsub : std_logic; + signal setstackaddr : std_logic; + signal writePC : std_logic; + signal writePC_add : std_logic; + signal set_TG68_PC_dec: std_logic; + signal TG68_PC_dec : std_logic_vector(1 downto 0); + signal directPC : std_logic; + signal set_directPC : std_logic; + signal execOPC : std_logic; + signal fetchOPC : std_logic; + signal Flags : std_logic_vector(15 downto 0); --T.S..III ...XNZVC + signal set_Flags : std_logic_vector(3 downto 0); --NZVC + signal exec_ADD : std_logic; + signal exec_OR : std_logic; + signal exec_AND : std_logic; + signal exec_EOR : std_logic; + signal exec_MOVE : std_logic; + signal exec_MOVEQ : std_logic; + signal exec_MOVESR : std_logic; + signal exec_DIRECT : std_logic; + signal exec_ADDQ : std_logic; + signal exec_CMP : std_logic; + signal exec_ROT : std_logic; + signal exec_exg : std_logic; + signal exec_swap : std_logic; + signal exec_write_back: std_logic; + signal exec_tas : std_logic; + signal exec_EXT : std_logic; + signal exec_ABCD : std_logic; + signal exec_SBCD : std_logic; + signal exec_MULU : std_logic; + signal exec_DIVU : std_logic; + signal exec_Scc : std_logic; + signal exec_CPMAW : std_logic; + signal set_exec_ADD : std_logic; + signal set_exec_OR : std_logic; + signal set_exec_AND : std_logic; + signal set_exec_EOR : std_logic; + signal set_exec_MOVE : std_logic; + signal set_exec_MOVEQ : std_logic; + signal set_exec_MOVESR: std_logic; + signal set_exec_ADDQ : std_logic; + signal set_exec_CMP : std_logic; + signal set_exec_ROT : std_logic; + signal set_exec_tas : std_logic; + signal set_exec_EXT : std_logic; + signal set_exec_ABCD : std_logic; + signal set_exec_SBCD : std_logic; + signal set_exec_MULU : std_logic; + signal set_exec_DIVU : std_logic; + signal set_exec_Scc : std_logic; + signal set_exec_CPMAW : std_logic; + + signal condition : std_logic; + signal OP2out_one : std_logic; + signal OP1out_zero : std_logic; + signal ea_to_pc : std_logic; + signal ea_build : std_logic; + signal ea_only : std_logic; + signal get_ea_now : std_logic; + signal source_lowbits : std_logic; + signal dest_hbits : std_logic; + signal rot_rot : std_logic; + signal rot_lsb : std_logic; + signal rot_msb : std_logic; + signal rot_XC : std_logic; + signal rot_nop : std_logic; + signal rot_out : std_logic_vector(31 downto 0); + signal rot_bits : std_logic_vector(1 downto 0); + signal rot_cnt : std_logic_vector(5 downto 0); + signal set_rot_cnt : std_logic_vector(5 downto 0); + signal movem_busy : std_logic; + signal set_movem_busy : std_logic; + signal movem_addr : std_logic; + signal movem_regaddr : std_logic_vector(3 downto 0); + signal movem_mask : std_logic_vector(15 downto 0); + signal set_get_movem_mask : std_logic; + signal get_movem_mask : std_logic; + signal movem_muxa : std_logic_vector(7 downto 0); + signal movem_muxb : std_logic_vector(3 downto 0); + signal movem_muxc : std_logic_vector(1 downto 0); + signal movem_presub : std_logic; + signal save_memaddr : std_logic; + signal movem_bits : std_logic_vector(4 downto 0); + signal ea_calc_b : std_logic_vector(31 downto 0); + signal set_mem_addsub : std_logic; + signal bit_bits : std_logic_vector(1 downto 0); + signal bit_number_reg : std_logic_vector(4 downto 0); + signal bit_number : std_logic_vector(4 downto 0); + signal exec_Bits : std_logic; + signal bits_out : std_logic_vector(31 downto 0); + signal one_bit_in : std_logic; + signal one_bit_out : std_logic; + signal set_get_bitnumber : std_logic; + signal get_bitnumber : std_logic; + signal mem_byte : std_logic; + signal set_direct_data: std_logic; + signal use_direct_data: std_logic; + signal direct_data : std_logic; + signal set_get_extendedOPC : std_logic; + signal get_extendedOPC: std_logic; + signal setstate_delay : std_logic_vector(1 downto 0); + signal setstate_mux : std_logic_vector(1 downto 0); + signal use_XZFlag : std_logic; + signal use_XFlag : std_logic; + + signal dummy_a : std_logic_vector(8 downto 0); + signal niba_l : std_logic_vector(5 downto 0); + signal niba_h : std_logic_vector(5 downto 0); + signal niba_lc : std_logic; + signal niba_hc : std_logic; + signal bcda_lc : std_logic; + signal bcda_hc : std_logic; + signal dummy_s : std_logic_vector(8 downto 0); + signal nibs_l : std_logic_vector(5 downto 0); + signal nibs_h : std_logic_vector(5 downto 0); + signal nibs_lc : std_logic; + signal nibs_hc : std_logic; + signal dummy_mulu : std_logic_vector(31 downto 0); + signal dummy_div : std_logic_vector(31 downto 0); + signal dummy_div_sub : std_logic_vector(16 downto 0); + signal dummy_div_over : std_logic_vector(16 downto 0); + signal set_V_Flag : std_logic; + signal OP1sign : std_logic; + signal set_sign : std_logic; + signal sign : std_logic; + signal sign2 : std_logic; + signal muls_msb : std_logic; + signal mulu_reg : std_logic_vector(31 downto 0); + signal div_reg : std_logic_vector(31 downto 0); + signal div_sign : std_logic; + signal div_quot : std_logic_vector(31 downto 0); + signal div_ovl : std_logic; + signal pre_V_Flag : std_logic; + signal set_vectoraddr : std_logic; + signal writeSR : std_logic; + signal trap_illegal : std_logic; + signal trap_priv : std_logic; + signal trap_1010 : std_logic; + signal trap_1111 : std_logic; + signal trap_trap : std_logic; + signal trap_trapv : std_logic; + signal trap_interrupt : std_logic; + signal trap : std_logic; + signal trapd : std_logic; +-- signal trap_PC : std_logic_vector(31 downto 0); + signal trap_SR : std_logic_vector(15 downto 0); + + signal set_directSR : std_logic; + signal directSR : std_logic; + signal set_stop : std_logic; + signal stop : std_logic; + signal trap_vector : std_logic_vector(31 downto 0); + signal to_USP : std_logic; + signal from_USP : std_logic; + signal to_SR : std_logic; + signal from_SR : std_logic; + signal illegal_write_mode : std_logic; + signal illegal_read_mode : std_logic; + signal illegal_byteaddr : std_logic; + signal use_SP : std_logic; + + signal no_Flags : std_logic; + signal IPL_nr : std_logic_vector(2 downto 0); + signal rIPL_nr : std_logic_vector(2 downto 0); + signal interrupt : std_logic; + signal SVmode : std_logic; + signal check_movep : std_logic; + signal check_chk : std_logic; + signal test_delay : std_logic_vector(2 downto 0); + signal set_PCmarker : std_logic; + signal PCmarker : std_logic; + signal set_Z_error : std_logic; + signal Z_error : std_logic; + + + type regfile_t is array(0 to 16) of std_logic_vector(31 downto 0); + signal regfile : regfile_t; + signal RWindex_A : integer range 0 to 16; + signal RWindex_B : integer range 0 to 16; + +BEGIN + +----------------------------------------------------------------------------- +-- Registerfile +----------------------------------------------------------------------------- + + RWindex_A <= conv_integer(rf_dest_addr(4)&(rf_dest_addr(3 downto 0) XOR "1111")); + RWindex_B <= conv_integer(rf_source_addr(4)&(rf_source_addr(3 downto 0) XOR "1111")); + + PROCESS (clk) + BEGIN + IF falling_edge(clk) THEN + IF clkena='1' THEN + reg_QA <= regfile(RWindex_A); + reg_QB <= regfile(RWindex_B); + END IF; + END IF; + IF rising_edge(clk) THEN + IF clkena='1' THEN + IF Lwrena='1' THEN + regfile(RWindex_A)(15 downto 0) <= registerin(15 downto 0); + END IF; + IF Hwrena='1' THEN + regfile(RWindex_A)(31 downto 16) <= registerin(31 downto 16); + END IF; + END IF; + END IF; + END PROCESS; + + + + address <= TG68_PC when state="00" else X"ffffffff" when state="01" else memaddr; + LDS <= '0' WHEN (datatype/="00" OR state="00" OR memaddr(0)='1') AND state/="01" ELSE '1'; + UDS <= '0' WHEN (datatype/="00" OR state="00" OR memaddr(0)='0') AND state/="01" ELSE '1'; + state_out <= state; + wr <= '0' WHEN state="11" ELSE '1'; + IPL_nr <= NOT IPL; + + +----------------------------------------------------------------------------- +-- "ALU" +----------------------------------------------------------------------------- +PROCESS (addsub_a, addsub_b, addsub, add_result, c_in) + BEGIN + IF addsub='1' THEN --ADD + add_result <= (('0'&addsub_a&c_in(0))+('0'&addsub_b&c_in(0))); + ELSE --SUB + add_result <= (('0'&addsub_a&'0')-('0'&addsub_b&c_in(0))); + END IF; + addsub_q <= add_result(32 downto 1); + c_in(1) <= add_result(9) XOR addsub_a(8) XOR addsub_b(8); + c_in(2) <= add_result(17) XOR addsub_a(16) XOR addsub_b(16); + c_in(3) <= add_result(33); + addsub_ofl(0) <= (c_in(1) XOR add_result(8) XOR addsub_a(7) XOR addsub_b(7)); --V Byte + addsub_ofl(1) <= (c_in(2) XOR add_result(16) XOR addsub_a(15) XOR addsub_b(15)); --V Word + addsub_ofl(2) <= (c_in(3) XOR add_result(32) XOR addsub_a(31) XOR addsub_b(31)); --V Long + c_out <= c_in(3 downto 1); +END PROCESS; + +----------------------------------------------------------------------------- +-- MEM_IO +----------------------------------------------------------------------------- +PROCESS (clk, reset, clkena_in, opcode, rIPL_nr, longread, get_extendedOPC, trap_illegal, z_error, trap_trapv, trap_priv, trap_1010, trap_1111, trap_trap, + memaddr, memaddr_a, set_mem_addsub, movem_presub, movem_busy, state, PCmarker, execOPC, datatype, setdisp, setdispbrief, briefext, setdispbyte, brief, + trap_vector, interrupt, set_mem_rega, reg_QA, setaddrlong, data_read, decodeOPC, TG68_PC, data_in, long_done, last_data_read, mem_byte, + data_write_tmp, addsub_q, set_vectoraddr) + BEGIN + clkena <= clkena_in AND NOT longread AND NOT get_extendedOPC; + +-- IF rising_edge(clk) THEN +-- IF clkena='1' THEN +-- trap_vector <= "000000000000000000000000011"&rIPL_nr&"00"; + trap_vector <= (others => '0'); +-- IF trap_addr_fault='1' THEN +-- trap_vector(7 downto 0) <= X"08"; +-- END IF; +-- IF trap_addr_error='1' THEN +-- trap_vector(7 downto 0) <= X"0C"; +-- END IF; + IF trap_illegal='1' THEN + trap_vector(7 downto 0) <= X"10"; +-- END IF; + ELSIF z_error='1' THEN + trap_vector(7 downto 0) <= X"14"; +-- END IF; +-- IF trap_chk='1' THEN +-- trap_vector(7 downto 0) <= X"18"; +-- END IF; + ELSIF trap_trapv='1' THEN + trap_vector(7 downto 0) <= X"1C"; +-- END IF; + ELSIF trap_priv='1' THEN + trap_vector(7 downto 0) <= X"20"; +-- END IF; +-- IF trap_trace='1' THEN +-- trap_vector(7 downto 0) <= X"24"; +-- END IF; + ELSIF trap_1010='1' THEN + trap_vector(7 downto 0) <= X"28"; +-- END IF; + ELSIF trap_1111='1' THEN + trap_vector(7 downto 0) <= X"2C"; +-- END IF; + ELSIF trap_trap='1' THEN + trap_vector(7 downto 2) <= "10"&opcode(3 downto 0); +-- ELSIF trap_interrupt='1' THEN + ELSE + trap_vector(7 downto 2) <= "011"&rIPL_nr; +-- END IF; +-- END IF; + END IF; + + memaddr_a(3 downto 0) <= "0000"; + memaddr_a(7 downto 4) <= (OTHERS=>memaddr_a(3)); + memaddr_a(15 downto 8) <= (OTHERS=>memaddr_a(7)); + memaddr_a(31 downto 16) <= (OTHERS=>memaddr_a(15)); + IF movem_presub='1' THEN + IF movem_busy='1' OR longread='1' THEN + memaddr_a(3 downto 0) <= "1110"; + END IF; + ELSIF state(1)='1' OR (get_extendedOPC='1' AND PCmarker='1') THEN + memaddr_a(1) <= '1'; + ELSIF execOPC='1' THEN + IF datatype="10" THEN + memaddr_a(3 downto 0) <= "1100"; + ELSE + memaddr_a(3 downto 0) <= "1110"; + END IF; + ELSIF setdisp='1' THEN + IF setdispbrief='1' THEN + memaddr_a <= briefext; + ELSIF setdispbyte='1' THEN + memaddr_a(7 downto 0) <= brief(7 downto 0); + ELSE + memaddr_a(15 downto 0) <= brief; + END IF; + END IF; + + memaddr_in <= memaddr+memaddr_a; + IF longread='0' THEN + IF set_mem_addsub='1' THEN + memaddr_in <= addsub_q; + ELSIF set_vectoraddr='1' THEN + memaddr_in <= trap_vector; + ELSIF interrupt='1' THEN + memaddr_in <= "1111111111111111111111111111"&rIPL_nr&'0'; + ELSIF set_mem_rega='1' THEN + memaddr_in <= reg_QA; + ELSIF setaddrlong='1' AND longread='0' THEN + memaddr_in <= data_read; + ELSIF decodeOPC='1' THEN + memaddr_in <= TG68_PC; + END IF; + END IF; + + data_read(15 downto 0) <= data_in; + data_read(31 downto 16) <= (OTHERS=>data_in(15)); + IF long_done='1' THEN + data_read(31 downto 16) <= last_data_read; + END IF; + IF mem_byte='1' AND memaddr(0)='0' THEN + data_read(7 downto 0) <= data_in(15 downto 8); + END IF; + + IF longread='1' THEN + data_write <= data_write_tmp(31 downto 16); + ELSE + data_write(7 downto 0) <= data_write_tmp(7 downto 0); + IF mem_byte='1' THEN + data_write(15 downto 8) <= data_write_tmp(7 downto 0); + ELSE + data_write(15 downto 8) <= data_write_tmp(15 downto 8); + IF datatype="00" THEN + data_write(7 downto 0) <= data_write_tmp(15 downto 8); + END IF; + END IF; + END IF; + + IF reset='0' THEN + longread <= '0'; + long_done <= '0'; + ELSIF rising_edge(clk) THEN + IF clkena_in='1' THEN + last_data_read <= data_in; + long_done <= longread; + IF get_extendedOPC='0' OR (get_extendedOPC='1' AND PCmarker='1') THEN + memaddr <= memaddr_in; + END IF; + IF get_extendedOPC='0' THEN + + IF ((setstate_mux(1)='1' AND datatype="10") OR longreaddirect='1') AND longread='0' AND interrupt='0' THEN + longread <= '1'; + ELSE + longread <= '0'; + END IF; + END IF; + + END IF; + END IF; + END PROCESS; +----------------------------------------------------------------------------- +-- brief +----------------------------------------------------------------------------- +process (clk, brief, OP1out) + begin + IF brief(11)='1' THEN + OP1outbrief <= OP1out(31 downto 16); + ELSE + OP1outbrief <= (OTHERS=>OP1out(15)); + END IF; + IF rising_edge(clk) THEN + IF clkena='1' THEN +-- briefext <= OP1outbrief&OP1out(15 downto 0); + CASE brief(10 downto 9) IS + WHEN "00" => briefext <= OP1outbrief&OP1out(15 downto 0); + WHEN "01" => briefext <= OP1outbrief(14 downto 0)&OP1out(15 downto 0)&'0'; + WHEN "10" => briefext <= OP1outbrief(13 downto 0)&OP1out(15 downto 0)&"00"; + WHEN "11" => briefext <= OP1outbrief(12 downto 0)&OP1out(15 downto 0)&"000"; + END CASE; + end if; + end if; + end process; + +----------------------------------------------------------------------------- +-- PC Calc + fetch opcode +----------------------------------------------------------------------------- +process (clk, reset, opcode, TG68_PC, TG68_PC_dec, TG68_PC_br8, TG68_PC_brw, PC_dataa, PC_datab, execOPC, last_data_read, get_extendedOPC, + setstate_delay, setstate) + begin + PC_dataa <= TG68_PC; + PC_datab(2 downto 0) <= "010"; + PC_datab(7 downto 3) <= (others => PC_datab(2)); + PC_datab(15 downto 8) <= (others => PC_datab(7)); + PC_datab(31 downto 16) <= (others => PC_datab(15)); + IF execOPC='0' THEN + IF TG68_PC_br8='1' THEN + PC_datab(7 downto 0) <= opcode(7 downto 0); + END IF; + IF TG68_PC_dec(1)='1' THEN + PC_datab(2) <= '1'; + END IF; + IF TG68_PC_brw = '1' THEN + PC_datab(15 downto 0) <= last_data_read(15 downto 0); + END IF; + END IF; + TG68_PC_add <= PC_dataa+PC_datab; + + IF get_extendedOPC='1' THEN + setstate_mux <= setstate_delay; + ELSE + setstate_mux <= setstate; + END IF; + + + IF reset = '0' THEN + opcode(15 downto 12) <= X"7"; --moveq + opcode(8 downto 6) <= "010"; --long + TG68_PC <= (others =>'0'); + state <= "01"; + decodeOPC <= '0'; + fetchOPC <= '0'; + endOPC <= '0'; + interrupt <= '0'; + trap_interrupt <= '1'; + execOPC <= '0'; + getbrief <= '0'; + TG68_PC_dec <= "00"; + directPC <= '0'; + directSR <= '0'; + stop <= '0'; + exec_ADD <= '0'; + exec_OR <= '0'; + exec_AND <= '0'; + exec_EOR <= '0'; + exec_MOVE <= '0'; + exec_MOVEQ <= '0'; + exec_MOVESR <= '0'; + exec_ADDQ <= '0'; + exec_CMP <= '0'; + exec_ROT <= '0'; + exec_EXT <= '0'; + exec_ABCD <= '0'; + exec_SBCD <= '0'; + exec_MULU <= '0'; + exec_DIVU <= '0'; + exec_Scc <= '0'; + exec_CPMAW <= '0'; + mem_byte <= '0'; + rot_cnt <="000001"; + get_extendedOPC <= '0'; + get_bitnumber <= '0'; + get_movem_mask <= '0'; + test_delay <= "000"; + PCmarker <= '0'; + ELSIF rising_edge(clk) THEN + IF clkena_in='1' THEN + get_extendedOPC <= set_get_extendedOPC; + get_bitnumber <= set_get_bitnumber; + get_movem_mask <= set_get_movem_mask; + setstate_delay <= setstate; + + TG68_PC_dec <= TG68_PC_dec(0)&set_TG68_PC_dec; + IF directPC='1' AND clkena='1' THEN + TG68_PC <= data_read; + ELSIF ea_to_pc='1' AND longread='0' THEN + TG68_PC <= memaddr_in; + ELSIF (state ="00" AND TG68_PC_nop='0') OR TG68_PC_br8='1' OR TG68_PC_brw='1' OR TG68_PC_dec(1)='1' THEN + TG68_PC <= TG68_PC_add; + END IF; + + IF get_bitnumber='1' THEN + bit_number_reg <= data_read(4 downto 0); + END IF; + + IF clkena='1' OR get_extendedOPC='1' THEN + IF set_get_extendedOPC='1' THEN + state <= "00"; + ELSIF get_extendedOPC='1' THEN + state <= setstate_mux; + ELSIF fetchOPC='1' OR (state="10" AND write_back='1' AND setstate/="10") OR set_rot_cnt/="000001" OR stop='1' THEN + state <= "01"; --decode cycle, execute cycle + ELSE + state <= setstate_mux; + END IF; + IF setstate_mux(1)='1' AND datatype="00" AND set_get_extendedOPC='0' THEN + mem_byte <= '1'; + ELSE + mem_byte <= '0'; + END IF; + + END IF; + END IF; + + IF clkena='1' THEN + exec_ADD <= '0'; + exec_OR <= '0'; + exec_AND <= '0'; + exec_EOR <= '0'; + exec_MOVE <= '0'; + exec_MOVEQ <= '0'; + exec_MOVESR <= '0'; + exec_ADDQ <= '0'; + exec_CMP <= '0'; + exec_ROT <= '0'; + exec_ABCD <= '0'; + exec_SBCD <= '0'; + fetchOPC <= '0'; + exec_CPMAW <= '0'; + endOPC <= '0'; + interrupt <= '0'; + execOPC <= '0'; + exec_EXT <= '0'; + exec_Scc <= '0'; + decodeOPC <= fetchOPC; + directPC <= set_directPC; + directSR <= set_directSR; + exec_MULU <= set_exec_MULU; + exec_DIVU <= set_exec_DIVU; + + stop <= set_stop OR (stop AND NOT interrupt); + IF set_PCmarker='1' THEN + PCmarker <= '1'; + ELSIF (state="10" AND longread='0') OR (ea_only='1' AND get_ea_now='1') THEN + PCmarker <= '0'; + END IF; + IF (decodeOPC OR execOPC)='1' THEN + rot_cnt <= set_rot_cnt; + END IF; + IF microstep='0' AND setstate_mux="00" AND (setnextpass='0' OR ea_only='1') AND endOPC='0' AND movem_busy='0' AND set_movem_busy='0' AND set_get_bitnumber='0' THEN + nextpass <= '0'; +-- IF stop='0' THEN + IF (exec_write_back='0' OR state="11") AND set_rot_cnt="000001" THEN + endOPC <= '1'; + IF Flags(10 downto 8) '0'); + ELSIF from_SR='1' THEN + OP1out(15 downto 0) <= Flags; + ELSIF ea_data_OP1='1' AND set_store_in_tmp='1' THEN + OP1out <= ea_data; + END IF; + END PROCESS; + +----------------------------------------------------------------------------- +-- set source regaddr +----------------------------------------------------------------------------- +PROCESS (opcode, Flags, movem_addr, movem_presub, movem_regaddr, source_lowbits, source_areg, from_USP, rf_source_addr_tmp) + BEGIN + rf_source_addr <= rf_source_addr_tmp; + IF rf_source_addr_tmp(3 downto 0)="1111" AND from_USP='0' THEN + rf_source_addr(4) <= Flags(13); + END IF; + IF movem_addr='1' THEN + IF movem_presub='1' THEN + rf_source_addr_tmp <= "000"&(movem_regaddr XOR "1111"); + ELSE + rf_source_addr_tmp <= "000"&movem_regaddr; + END IF; + ELSIF from_USP='1' THEN + rf_source_addr_tmp <= "0001111"; + ELSIF source_lowbits='1' THEN + rf_source_addr_tmp <= "000"&source_areg&opcode(2 downto 0); + ELSE + rf_source_addr_tmp <= "000"&source_areg&opcode(11 downto 9); + END IF; + END PROCESS; + +----------------------------------------------------------------------------- +-- set OP2 +----------------------------------------------------------------------------- +PROCESS (OP2out, reg_QB, opcode, datatype, OP2out_one, exec_EXT, exec_MOVEQ, EXEC_ADDQ, use_direct_data, data_write_tmp, ea_data_OP1, set_store_in_tmp, ea_data) + BEGIN + OP2out(15 downto 0) <= reg_QB(15 downto 0); + OP2out(31 downto 16) <= (OTHERS => OP2out(15)); + IF OP2out_one='1' THEN + OP2out(15 downto 0) <= "1111111111111111"; + ELSIF exec_EXT='1' THEN + IF opcode(6)='0' THEN --ext.w + OP2out(15 downto 8) <= (OTHERS => OP2out(7)); + END IF; + ELSIF use_direct_data='1' THEN + OP2out <= data_write_tmp; + ELSIF ea_data_OP1='0' AND set_store_in_tmp='1' THEN + OP2out <= ea_data; + ELSIF exec_MOVEQ='1' THEN + OP2out(7 downto 0) <= opcode(7 downto 0); + OP2out(15 downto 8) <= (OTHERS => opcode(7)); + ELSIF exec_ADDQ='1' THEN + OP2out(2 downto 0) <= opcode(11 downto 9); + IF opcode(11 downto 9)="000" THEN + OP2out(3) <='1'; + ELSE + OP2out(3) <='0'; + END IF; + OP2out(15 downto 4) <= (OTHERS => '0'); + ELSIF datatype="10" THEN + OP2out(31 downto 16) <= reg_QB(31 downto 16); + END IF; + END PROCESS; + +----------------------------------------------------------------------------- +-- addsub +----------------------------------------------------------------------------- +PROCESS (OP1out, OP2out, presub, postadd, execOPC, OP2out_one, datatype, use_SP, use_XZFlag, use_XFlag, Flags, setaddsub) + BEGIN + addsub_a <= OP1out; + addsub_b <= OP2out; + addsub <= NOT presub; + c_in(0) <='0'; + IF execOPC='0' AND OP2out_one='0' THEN + IF datatype="00" AND use_SP='0' THEN + addsub_b <= "00000000000000000000000000000001"; + ELSIF datatype="10" AND (presub OR postadd)='1' THEN + addsub_b <= "00000000000000000000000000000100"; + ELSE + addsub_b <= "00000000000000000000000000000010"; + END IF; + ELSE + IF (use_XZFlag='1' OR use_XFlag='1') AND Flags(4)='1' THEN + c_in(0) <= '1'; + END IF; + addsub <= setaddsub; + END IF; + END PROCESS; + +----------------------------------------------------------------------------- +-- Write Reg +----------------------------------------------------------------------------- +PROCESS (clkena, OP1in, datatype, presub, postadd, endOPC, regwrena, state, execOPC, last_data_read, movem_addr, rf_dest_addr, reg_QA) + BEGIN + Lwrena <= '0'; + Hwrena <= '0'; + registerin <= OP1in; + + IF (presub='1' OR postadd='1') AND endOPC='0' THEN -- -(An)+ + Hwrena <= '1'; + Lwrena <= '1'; + ELSIF Regwrena='1' THEN --read (mem) + Lwrena <= '1'; + CASE datatype IS + WHEN "00" => --BYTE + registerin(15 downto 8) <= reg_QA(15 downto 8); + WHEN "01" => --WORD + IF rf_dest_addr(3)='1' OR movem_addr='1' THEN + Hwrena <='1'; + END IF; + WHEN OTHERS => --LONG + Hwrena <= '1'; + END CASE; + END IF; + END PROCESS; + +------------------------------------------------------------------------------ +--ALU +------------------------------------------------------------------------------ +PROCESS (opcode, OP1in, OP1out, OP2out, datatype, c_out, exec_ABCD, exec_SBCD, exec_CPMAW, exec_MOVESR, bits_out, Flags, flag_z, use_XZFlag, addsub_ofl, + dummy_s, dummy_a, niba_hc, niba_h, niba_l, niba_lc, nibs_hc, nibs_h, nibs_l, nibs_lc, addsub_q, movem_addr, data_read, exec_MULU, exec_DIVU, exec_OR, + exec_AND, exec_Scc, exec_EOR, exec_MOVE, exec_exg, exec_ROT, execOPC, exec_swap, exec_Bits, rot_out, dummy_mulu, dummy_div, save_memaddr, memaddr, + memaddr_in, ea_only, get_ea_now) + BEGIN + +--BCD_ARITH------------------------------------------------------------------- + --ADC + dummy_a <= niba_hc&(niba_h(4 downto 1)+('0',niba_hc,niba_hc,'0'))&(niba_l(4 downto 1)+('0',niba_lc,niba_lc,'0')); + niba_l <= ('0'&OP1out(3 downto 0)&'1') + ('0'&OP2out(3 downto 0)&Flags(4)); + niba_lc <= niba_l(5) OR (niba_l(4) AND niba_l(3)) OR (niba_l(4) AND niba_l(2)); + + niba_h <= ('0'&OP1out(7 downto 4)&'1') + ('0'&OP2out(7 downto 4)&niba_lc); + niba_hc <= niba_h(5) OR (niba_h(4) AND niba_h(3)) OR (niba_h(4) AND niba_h(2)); + --SBC + dummy_s <= nibs_hc&(nibs_h(4 downto 1)-('0',nibs_hc,nibs_hc,'0'))&(nibs_l(4 downto 1)-('0',nibs_lc,nibs_lc,'0')); + nibs_l <= ('0'&OP1out(3 downto 0)&'0') - ('0'&OP2out(3 downto 0)&Flags(4)); + nibs_lc <= nibs_l(5); + + nibs_h <= ('0'&OP1out(7 downto 4)&'0') - ('0'&OP2out(7 downto 4)&nibs_lc); + nibs_hc <= nibs_h(5); +------------------------------------------------------------------------------ + + flag_z <= "000"; + + OP1in <= addsub_q; + IF movem_addr='1' THEN + OP1in <= data_read; + ELSIF exec_ABCD='1' THEN + OP1in(7 downto 0) <= dummy_a(7 downto 0); + ELSIF exec_SBCD='1' THEN + OP1in(7 downto 0) <= dummy_s(7 downto 0); + ELSIF exec_MULU='1' THEN + OP1in <= dummy_mulu; + ELSIF exec_DIVU='1' AND execOPC='1' THEN + OP1in <= dummy_div; + ELSIF exec_OR='1' THEN + OP1in <= OP2out OR OP1out; + ELSIF exec_AND='1' OR exec_Scc='1' THEN + OP1in <= OP2out AND OP1out; + ELSIF exec_EOR='1' THEN + OP1in <= OP2out XOR OP1out; + ELSIF exec_MOVE='1' OR exec_exg='1' THEN + OP1in <= OP2out; + ELSIF exec_ROT='1' THEN + OP1in <= rot_out; + ELSIF save_memaddr='1' THEN + OP1in <= memaddr; + ELSIF get_ea_now='1' AND ea_only='1' THEN + OP1in <= memaddr_in; + ELSIF exec_swap='1' THEN + OP1in <= OP1out(15 downto 0)& OP1out(31 downto 16); + ELSIF exec_bits='1' THEN + OP1in <= bits_out; + ELSIF exec_MOVESR='1' THEN + OP1in(15 downto 0) <= Flags; + END IF; + + IF use_XZFlag='1' AND flags(2)='0' THEN + flag_z <= "000"; + ELSIF OP1in(7 downto 0)="00000000" THEN + flag_z(0) <= '1'; + IF OP1in(15 downto 8)="00000000" THEN + flag_z(1) <= '1'; + IF OP1in(31 downto 16)="0000000000000000" THEN + flag_z(2) <= '1'; + END IF; + END IF; + END IF; + +-- --Flags NZVC + IF datatype="00" THEN --Byte + set_flags <= OP1IN(7)&flag_z(0)&addsub_ofl(0)&c_out(0); + IF exec_ABCD='1' THEN + set_flags(0) <= dummy_a(8); + ELSIF exec_SBCD='1' THEN + set_flags(0) <= dummy_s(8); + END IF; + ELSIF datatype="10" OR exec_CPMAW='1' THEN --Long + set_flags <= OP1IN(31)&flag_z(2)&addsub_ofl(2)&c_out(2); + ELSE --Word + set_flags <= OP1IN(15)&flag_z(1)&addsub_ofl(1)&c_out(1); + END IF; + END PROCESS; + +------------------------------------------------------------------------------ +--Flags +------------------------------------------------------------------------------ +PROCESS (clk, reset, opcode) + BEGIN + IF reset='0' THEN + Flags(13) <= '1'; + SVmode <= '1'; + Flags(10 downto 8) <= "111"; + ELSIF rising_edge(clk) THEN + + IF clkena = '1' THEN + IF directSR='1' THEN + Flags <= data_read(15 downto 0); + END IF; + IF interrupt='1' THEN + Flags(10 downto 8) <=rIPL_nr; + SVmode <= '1'; + END IF; + IF writeSR='1' OR interrupt='1' THEN + Flags(13) <='1'; + END IF; + IF endOPC='1' AND to_SR='0' THEN + SVmode <= Flags(13); + END IF; + IF execOPC='1' AND to_SR='1' THEN + Flags(7 downto 0) <= OP1in(7 downto 0); --CCR + IF datatype="01" AND (opcode(14)='0' OR opcode(9)='1') THEN --move to CCR wird als word gespeichert + Flags(15 downto 8) <= OP1in(15 downto 8); --SR + SVmode <= OP1in(13); + END IF; + ELSIF Z_error='1' THEN + IF opcode(8)='0' THEN + Flags(3 downto 0) <= "1000"; + ELSE + Flags(3 downto 0) <= "0100"; + END IF; + ELSIF no_Flags='0' AND trap='0' THEN + IF exec_ADD='1' THEN + Flags(4) <= set_flags(0); + ELSIF exec_ROT='1' AND rot_bits/="11" AND rot_nop='0' THEN + Flags(4) <= rot_XC; + END IF; + + IF (exec_ADD OR exec_CMP)='1' THEN + Flags(3 downto 0) <= set_flags; + ELSIF decodeOPC='1' and set_exec_ROT='1' THEN + Flags(1) <= '0'; + ELSIF exec_DIVU='1' THEN + IF set_V_Flag='1' THEN + Flags(3 downto 0) <= "1010"; + ELSE + Flags(3 downto 0) <= OP1IN(15)&flag_z(1)&"00"; + END IF; + ELSIF exec_OR='1' OR exec_AND='1' OR exec_EOR='1' OR exec_MOVE='1' OR exec_swap='1' OR exec_MULU='1' THEN + Flags(3 downto 0) <= set_flags(3 downto 2)&"00"; + ELSIF exec_ROT='1' THEN + Flags(3 downto 2) <= set_flags(3 downto 2); + Flags(0) <= rot_XC; + IF rot_bits="00" THEN --ASL/ASR + Flags(1) <= ((set_flags(3) XOR rot_rot) OR Flags(1)); + END IF; + ELSIF exec_bits='1' THEN + Flags(2) <= NOT one_bit_in; + END IF; + END IF; + END IF; + END IF; + END PROCESS; + +----------------------------------------------------------------------------- +-- execute opcode +----------------------------------------------------------------------------- +PROCESS (clk, reset, OP2out, opcode, fetchOPC, decodeOPC, execOPC, endOPC, prefix, nextpass, condition, set_V_flag, trap, trapd, interrupt, trap_interrupt, + Z_error, microaddr, c_in, rot_cnt, one_bit_in, bit_number_reg, bit_number, ea_only, get_ea_now, ea_build, datatype, exec_write_back, get_extendedOPC, + Flags, SVmode, movem_addr, movem_busy, getbrief, set_exec_AND, set_exec_OR, set_exec_EOR, TG68_PC_dec) + BEGIN + TG68_PC_br8 <= '0'; + TG68_PC_brw <= '0'; + TG68_PC_nop <= '0'; + setstate <= "00"; + Regwrena <= '0'; + microstep <= '0'; + microset <= '0'; + postadd <= '0'; + presub <= '0'; + movem_presub <= '0'; + setaddsub <= '1'; + micronext <= "00000001"; + setaddrlong <= '0'; + setnextpass <= '0'; + regdirectsource <= '0'; + setdisp <= '0'; + setdispbyte <= '0'; + setdispbrief <= '0'; + setbriefext <= '0'; + setgetbrief <= '0'; + longreaddirect <= '0'; + dest_areg <= '0'; + source_areg <= '0'; + data_is_source <= '0'; + write_back <= '0'; + setstackaddr <= '0'; + writePC <= '0'; + writePC_add <= '0'; + set_TG68_PC_dec <= '0'; + set_directPC <= '0'; + set_exec_ADD <= '0'; + set_exec_OR <= '0'; + set_exec_AND <= '0'; + set_exec_EOR <= '0'; + set_exec_MOVE <= '0'; + set_exec_MOVEQ <= '0'; + set_exec_MOVESR <= '0'; + set_exec_ADDQ <= '0'; + set_exec_CMP <= '0'; + set_exec_ROT <= '0'; + set_exec_EXT <= '0'; + set_exec_CPMAW <= '0'; + OP2out_one <= '0'; + ea_to_pc <= '0'; + ea_build <= '0'; + get_ea_now <= '0'; + rot_bits <= "XX"; + rot_nop <= '0'; + set_rot_cnt <= "000001"; + set_movem_busy <= '0'; + set_get_movem_mask <= '0'; + save_memaddr <= '0'; + set_mem_addsub <= '0'; + exec_exg <= '0'; + exec_swap <= '0'; + exec_Bits <= '0'; + set_get_bitnumber <= '0'; + dest_hbits <= '0'; + source_lowbits <= '0'; + set_mem_rega <= '0'; + ea_data_OP1 <= '0'; + ea_only <= '0'; + set_direct_data <= '0'; + set_get_extendedOPC <= '0'; + set_exec_tas <= '0'; + OP1out_zero <= '0'; + use_XZFlag <= '0'; + use_XFlag <= '0'; + set_exec_ABCD <= '0'; + set_exec_SBCD <= '0'; + set_exec_MULU <= '0'; + set_exec_DIVU <= '0'; + set_exec_Scc <= '0'; + trap_illegal <='0'; + trap_priv <='0'; + trap_1010 <='0'; + trap_1111 <='0'; + trap_trap <='0'; + trap_trapv <= '0'; + trap <='0'; + set_vectoraddr <='0'; + writeSR <= '0'; + set_directSR <= '0'; + set_stop <= '0'; + from_SR <= '0'; + to_SR <= '0'; + from_USP <= '0'; + to_USP <= '0'; + illegal_write_mode <= '0'; + illegal_read_mode <= '0'; + illegal_byteaddr <= '0'; + no_Flags <= '0'; + set_PCmarker <= '0'; + use_SP <= '0'; + set_Z_error <= '0'; + + check_movep <= '0'; + check_chk <= '0'; + +------------------------------------------------------------------------------ +--Sourcepass +------------------------------------------------------------------------------ + IF ea_only='0' AND get_ea_now='1' THEN + setstate <= "10"; + END IF; + + IF ea_build='1' THEN + CASE opcode(5 downto 3) IS --source + WHEN "010"|"011"|"100" => -- -(An)+ + get_ea_now <='1'; + setnextpass <= '1'; + IF opcode(4)='1' THEN + set_mem_rega <= '1'; + ELSE + set_mem_addsub <= '1'; + END IF; + IF opcode(3)='1' THEN --(An)+ + postadd <= '1'; + IF opcode(2 downto 0)="111" THEN + use_SP <= '1'; + END IF; + END IF; + IF opcode(5)='1' THEN -- -(An) + presub <= '1'; + IF opcode(2 downto 0)="111" THEN + use_SP <= '1'; + END IF; + END IF; + IF opcode(4 downto 3)/="10" THEN + regwrena <= '1'; + END IF; + WHEN "101" => --(d16,An) + microstep <='1'; + micronext <="00000110"; + setgetbrief <='1'; + set_mem_regA <= '1'; + WHEN "110" => --(d8,An,Xn) + microstep <='1'; + micronext <="00001000"; + setgetbrief <='1'; + set_mem_regA <= '1'; + WHEN "111" => + CASE opcode(2 downto 0) IS + WHEN "000" => --(xxxx).w + micronext <="00000010"; + microstep <='1'; + WHEN "001" => --(xxxx).l + longreaddirect <= '1'; + micronext <="00000010"; + microstep <='1'; + WHEN "010" => --(d16,PC) + microstep <='1'; + micronext <="00000110"; + setgetbrief <= '1'; + set_PCmarker <= '1'; + WHEN "011" => --(d8,PC,Xn) + microstep <='1'; + micronext <="00001000"; + setgetbrief <= '1'; + set_PCmarker <= '1'; + WHEN "100" => --#data + setnextpass <= '1'; + set_direct_data <= '1'; + IF datatype="10" THEN + longreaddirect <= '1'; + END IF; + WHEN OTHERS => + END CASE; + WHEN OTHERS => + END CASE; + END IF; +------------------------------------------------------------------------------ +--prepere opcode +------------------------------------------------------------------------------ + CASE opcode(7 downto 6) IS + WHEN "00" => datatype <= "00"; --Byte + WHEN "01" => datatype <= "01"; --Word + WHEN OTHERS => datatype <= "10"; --Long + END CASE; + + IF execOPC='1' AND endOPC='0' AND exec_write_back='1' THEN + setstate <="11"; + END IF; + +------------------------------------------------------------------------------ +--test illegal mode +------------------------------------------------------------------------------ + IF (opcode(5 downto 3)="111" AND opcode(2 downto 1)/="00") OR (opcode(5 downto 3)="001" AND datatype="00") THEN + illegal_write_mode <= '1'; + END IF; + IF (opcode(5 downto 2)="1111" AND opcode(1 downto 0)/="00") OR (opcode(5 downto 3)="001" AND datatype="00") THEN + illegal_read_mode <= '1'; + END IF; + IF opcode(5 downto 3)="001" AND datatype="00" THEN + illegal_byteaddr <= '1'; + END IF; + + + CASE opcode(15 downto 12) IS +-- 0000 ---------------------------------------------------------------------------- + WHEN "0000" => + --hier muss noch MOVEP rein + IF opcode(8)='1' AND opcode(5 downto 3)="001" THEN --movep + trap_illegal <= '1'; + trap <= '1'; + ELSE + IF opcode(8)='1' OR opcode(11 downto 8)="1000" THEN --Bits + IF execOPC='1' AND get_extendedOPC='0' THEN + IF opcode(7 downto 6)/="00" AND endOPC='1' THEN + regwrena <= '1'; + END IF; + exec_Bits <= '1'; + ea_data_OP1 <= '1'; + END IF; +-- IF get_extendedOPC='1' THEN +-- datatype <= "01"; --Word +-- ELS + IF opcode(5 downto 4)="00" THEN + datatype <= "10"; --Long + ELSE + datatype <= "00"; --Byte + IF opcode(7 downto 6)/="00" THEN + write_back <= '1'; + END IF; + END IF; + IF decodeOPC='1' THEN + ea_build <= '1'; + IF opcode(8)='0' THEN + IF opcode(5 downto 4)/="00" THEN --Dn, An + set_get_extendedOPC <= '1'; + END IF; + set_get_bitnumber <= '1'; + END IF; + END IF; + ELSE --andi, ...xxxi + IF opcode(11 downto 8)="0000" THEN --ORI + set_exec_OR <= '1'; + END IF; + IF opcode(11 downto 8)="0010" THEN --ANDI + set_exec_AND <= '1'; + END IF; + IF opcode(11 downto 8)="0100" OR opcode(11 downto 8)="0110" THEN --SUBI, ADDI + set_exec_ADD <= '1'; + END IF; + IF opcode(11 downto 8)="1010" THEN --EORI + set_exec_EOR <= '1'; + END IF; + IF opcode(11 downto 8)="1100" THEN --CMPI + set_exec_CMP <= '1'; + ELSIF trap='0' THEN + write_back <= '1'; + END IF; + IF opcode(7)='0' AND opcode(5 downto 0)="111100" AND (set_exec_AND OR set_exec_OR OR set_exec_EOR)='1' THEN --SR +-- IF opcode(7)='0' AND opcode(5 downto 0)="111100" AND (opcode(11 downto 8)="0010" OR opcode(11 downto 8)="0000" OR opcode(11 downto 8)="1010") THEN --SR + IF SVmode='0' AND opcode(6)='1' THEN --SR + trap_priv <= '1'; + trap <= '1'; + ELSE + from_SR <= '1'; + to_SR <= '1'; + IF decodeOPC='1' THEN + setnextpass <= '1'; + set_direct_data <= '1'; + END IF; + END IF; + ELSE + IF decodeOPC='1' THEN + IF opcode(11 downto 8)="0010" OR opcode(11 downto 8)="0000" OR opcode(11 downto 8)="0100" --ANDI, ORI, SUBI + OR opcode(11 downto 8)="0110" OR opcode(11 downto 8)="1010" OR opcode(11 downto 8)="1100" THEN --ADDI, EORI, CMPI + -- IF (set_exec_AND OR set_exec_OR OR set_exec_ADD --ANDI, ORI, SUBI + -- OR set_exec_EOR OR set_exec_CMP)='1' THEN --ADDI, EORI, CMPI + + microstep <='1'; + micronext <="00101000"; + set_direct_data <= '1'; + IF datatype="10" THEN + longreaddirect <= '1'; + END IF; + END IF; + END IF; + + IF execOPC='1' THEN + ea_data_OP1 <= '1'; + IF opcode(11 downto 8)/="1100" THEN --CMPI + IF endOPC='1' THEN + Regwrena <= '1'; + END IF; + END IF; + IF opcode(11 downto 8)="1100" OR opcode(11 downto 8)="0100" THEN --CMPI, SUBI + setaddsub <= '0'; + END IF; + END IF; + END IF; + END IF; + END IF; + +-- 0001, 0010, 0011 ----------------------------------------------------------------- + WHEN "0001"|"0010"|"0011" => --move.b, move.l, move.w + set_exec_MOVE <= '1'; + IF opcode(8 downto 6)="001" THEN + no_Flags <= '1'; + END IF; + IF opcode(5 downto 4)="00" THEN --Dn, An + regdirectsource <= '1'; + END IF; + CASE opcode(13 downto 12) IS + WHEN "01" => datatype <= "00"; --Byte + WHEN "10" => datatype <= "10"; --Long + WHEN OTHERS => datatype <= "01"; --Word + END CASE; + source_lowbits <= '1'; -- Dn=> An=> + IF opcode(3)='1' THEN + source_areg <= '1'; + END IF; + IF getbrief='1' AND nextpass='1' THEN -- =>(d16,An) =>(d8,An,Xn) + set_mem_rega <= '1'; + END IF; + + IF execOPC='1' AND opcode(8 downto 7)="00" THEN + Regwrena <= '1'; + END IF; + + IF nextpass='1' OR execOPC='1' OR opcode(5 downto 4)="00" THEN + dest_hbits <= '1'; + IF opcode(8 downto 6)/="000" THEN + dest_areg <= '1'; + END IF; + END IF; + + IF decodeOPC='1' THEN + ea_build <= '1'; + END IF; + + IF prefix='0' AND (nextpass='1' OR (opcode(5 downto 4)="00" AND decodeOPC='1')) THEN + CASE opcode(8 downto 6) IS --destination +-- WHEN "000" => --Dn +-- WHEN "001" => --An + WHEN "010"|"011"|"100" => --destination -(an)+ + IF opcode(7)='1' THEN + set_mem_rega <= '1'; + ELSE + set_mem_addsub <= '1'; + END IF; + IF opcode(6)='1' THEN --(An)+ + postadd <= '1'; + IF opcode(11 downto 9)="111" THEN + use_SP <= '1'; + END IF; + END IF; + IF opcode(8)='1' THEN -- -(An) + presub <= '1'; + IF opcode(11 downto 9)="111" THEN + use_SP <= '1'; + END IF; + END IF; + IF opcode(7 downto 6)/="10" THEN + regwrena <= '1'; + END IF; + setstate <= "11"; + microstep <='1'; --nop + WHEN "101" => --(d16,An) + microstep <='1'; + micronext <="00001011"; + set_mem_regA <= '1'; + setgetbrief <= '1'; + WHEN "110" => --(d8,An,Xn) + microstep <='1'; + micronext <="00001110"; + set_mem_regA <= '1'; + setgetbrief <= '1'; + WHEN "111" => + CASE opcode(11 downto 9) IS + WHEN "000" => --(xxxx).w + microstep <='1'; + micronext <="00000011"; + WHEN "001" => --(xxxx).l + longreaddirect <= '1'; + microstep <='1'; + micronext <="00000011"; + WHEN OTHERS => + END CASE; + WHEN OTHERS => + END CASE; + END IF; +-- 0100 ---------------------------------------------------------------------------- + WHEN "0100" => --rts_group + IF opcode(8)='1' THEN --lea + IF opcode(6)='1' THEN --lea + IF opcode(7)='1' THEN + ea_only <= '1'; + IF opcode(5 downto 3)="010" THEN --lea (Am),An + set_exec_move <='1'; + no_Flags <='1'; + dest_areg <= '1'; + dest_hbits <= '1'; + source_lowbits <= '1'; + source_areg <= '1'; + IF execOPC='1' THEN + Regwrena <= '1'; + END IF; + ELSE + IF decodeOPC='1' THEN + ea_build <= '1'; + END IF; + END IF; + IF get_ea_now='1' THEN + dest_areg <= '1'; + dest_hbits <= '1'; + regwrena <= '1'; + END IF; + ELSE + trap_illegal <= '1'; + trap <= '1'; + END IF; + ELSE --chk + trap_illegal <= '1'; + trap <= '1'; + check_chk <= '1'; + END IF; + ELSE + CASE opcode(11 downto 9) IS + WHEN "000"=> + IF decodeOPC='1' THEN + ea_build <= '1'; + END IF; + IF opcode(7downto 6)="11" THEN --move from SR + set_exec_MOVESR <= '1'; + datatype <= "01"; + write_back <='1'; -- im 68000 wird auch erst gelesen + IF execOPC='1' THEN + IF endOPC='1' THEN + Regwrena <= '1'; + END IF; + END IF; + ELSE --negx + use_XFlag <= '1'; + write_back <='1'; + set_exec_ADD <= '1'; + setaddsub <='0'; + IF execOPC='1' THEN + source_lowbits <= '1'; + OP1out_zero <= '1'; + IF endOPC='1' THEN + Regwrena <= '1'; + END IF; + END IF; + END IF; + WHEN "001"=> + IF opcode(7downto 6)="11" THEN --move from CCR 68010 + trap_illegal <= '1'; + trap <= '1'; + ELSE --clr + IF decodeOPC='1' THEN + ea_build <= '1'; + END IF; + write_back <='1'; + set_exec_AND <= '1'; + IF execOPC='1' THEN + OP1out_zero <= '1'; + IF endOPC='1' THEN + Regwrena <= '1'; + END IF; + END IF; + END IF; + WHEN "010"=> + IF decodeOPC='1' THEN + ea_build <= '1'; + END IF; + IF opcode(7downto 6)="11" THEN --move to CCR + set_exec_MOVE <= '1'; + datatype <= "01"; + IF execOPC='1' THEN + source_lowbits <= '1'; + to_SR <= '1'; + END IF; + ELSE --neg + write_back <='1'; + set_exec_ADD <= '1'; + setaddsub <='0'; + IF execOPC='1' THEN + source_lowbits <= '1'; + OP1out_zero <= '1'; + IF endOPC='1' THEN + Regwrena <= '1'; + END IF; + END IF; + END IF; + WHEN "011"=> --not, move toSR + IF opcode(7downto 6)="11" THEN --move to SR + IF SVmode='1' THEN + IF decodeOPC='1' THEN + ea_build <= '1'; + END IF; + set_exec_MOVE <= '1'; + datatype <= "01"; + IF execOPC='1' THEN + source_lowbits <= '1'; + to_SR <= '1'; + END IF; + ELSE + trap_priv <= '1'; + trap <= '1'; + END IF; + ELSE --not + IF decodeOPC='1' THEN + ea_build <= '1'; + END IF; + write_back <='1'; + set_exec_EOR <= '1'; + IF execOPC='1' THEN + OP2out_one <= '1'; + ea_data_OP1 <= '1'; + IF endOPC='1' THEN + Regwrena <= '1'; + END IF; + END IF; + END IF; + WHEN "100"|"110"=> + IF opcode(7)='1' THEN --movem, ext + IF opcode(5 downto 3)="000" AND opcode(10)='0' THEN --ext + source_lowbits <= '1'; + IF decodeOPC='1' THEN + set_exec_EXT <= '1'; + set_exec_move <= '1'; + END IF; + IF opcode(6)='0' THEN + datatype <= "01"; --WORD + END IF; + IF execOPC='1' THEN + regwrena <= '1'; + END IF; + ELSE --movem +-- IF opcode(11 downto 7)="10001" OR opcode(11 downto 7)="11001" THEN --MOVEM + ea_only <= '1'; + IF decodeOPC='1' THEN + datatype <= "01"; --Word + set_get_movem_mask <='1'; + set_get_extendedOPC <='1'; + + IF opcode(5 downto 3)="010" OR opcode(5 downto 3)="011" OR opcode(5 downto 3)="100" THEN + set_mem_rega <= '1'; + setstate <= "01"; + IF opcode(10)='0' THEN + set_movem_busy <='1'; + ELSE + micronext <="00100010"; + microstep <='1'; + END IF; + ELSE + ea_build <= '1'; + END IF; + + ELSE + IF opcode(6)='0' THEN + datatype <= "01"; --Word + END IF; + END IF; + IF execOPC='1' THEN + IF opcode(5 downto 3)="100" OR opcode(5 downto 3)="011" THEN + regwrena <= '1'; + save_memaddr <= '1'; + END IF; + END IF; + IF get_ea_now='1' THEN + set_movem_busy <= '1'; + IF opcode(10)='0' THEN + setstate <="01"; + ELSE + setstate <="10"; + END IF; + END IF; + IF opcode(5 downto 3)="100" THEN + movem_presub <= '1'; + END IF; + IF movem_addr='1' THEN + IF opcode(10)='1' THEN + regwrena <= '1'; + END IF; + END IF; + IF movem_busy='1' THEN + IF opcode(10)='0' THEN + setstate <="11"; + ELSE + setstate <="10"; + END IF; + END IF; + END IF; + ELSE + IF opcode(10)='1' THEN --MUL, DIV 68020 + trap_illegal <= '1'; + trap <= '1'; + ELSE --pea, swap + IF opcode(6)='1' THEN + datatype <= "10"; + IF opcode(5 downto 3)="000" THEN --swap + IF execOPC='1' THEN + exec_swap <= '1'; + regwrena <= '1'; + END IF; + ELSIF opcode(5 downto 3)="001" THEN --bkpt + + ELSE --pea + ea_only <= '1'; + IF decodeOPC='1' THEN + ea_build <= '1'; + END IF; + IF nextpass='1' AND prefix='0' THEN + presub <= '1'; + setstackaddr <='1'; + set_mem_addsub <= '1'; + setstate <="11"; + microstep <='1'; + END IF; + IF get_ea_now='1' THEN + setstate <="01"; + END IF; + END IF; + ELSE --nbcd + IF decodeOPC='1' THEN --nbcd + ea_build <= '1'; + END IF; + use_XFlag <= '1'; + write_back <='1'; + set_exec_ADD <= '1'; + set_exec_SBCD <= '1'; + IF execOPC='1' THEN + source_lowbits <= '1'; + OP1out_zero <= '1'; + IF endOPC='1' THEN + Regwrena <= '1'; + END IF; + END IF; + END IF; + END IF; + END IF; + + WHEN "101"=> --tst, tas + IF decodeOPC='1' THEN + ea_build <= '1'; + END IF; + IF execOPC='1' THEN + dest_hbits <= '1'; --for Flags + source_lowbits <= '1'; + -- IF opcode(3)='1' THEN --MC68020... + -- source_areg <= '1'; + -- END IF; + END IF; + set_exec_MOVE <= '1'; + IF opcode(7 downto 6)="11" THEN --tas + set_exec_tas <= '1'; + write_back <= '1'; + datatype <= "00"; --Byte + IF execOPC='1' AND endOPC='1' THEN + regwrena <= '1'; + END IF; + END IF; +-- WHEN "110"=> + WHEN "111"=> --4EXX + IF opcode(7)='1' THEN --jsr, jmp + datatype <= "10"; + ea_only <= '1'; + IF nextpass='1' AND prefix='0' THEN + presub <= '1'; + setstackaddr <='1'; + set_mem_addsub <= '1'; + setstate <="11"; + microstep <='1'; + END IF; + IF decodeOPC='1' THEN + ea_build <= '1'; + END IF; + IF get_ea_now='1' THEN --jsr + IF opcode(6)='0' THEN + setstate <="01"; + END IF; + ea_to_pc <= '1'; + IF opcode(5 downto 0)="111001" THEN + writePC_add <= '1'; + ELSE + writePC <= '1'; + END IF; + END IF; + ELSE -- + CASE opcode(6 downto 0) IS + WHEN "1000000"|"1000001"|"1000010"|"1000011"|"1000100"|"1000101"|"1000110"|"1000111"| --trap + "1001000"|"1001001"|"1001010"|"1001011"|"1001100"|"1001101"|"1001110"|"1001111" => --trap + trap_trap <='1'; + trap <= '1'; + WHEN "1010000"|"1010001"|"1010010"|"1010011"|"1010100"|"1010101"|"1010110"|"1010111" => --link + datatype <= "10"; + IF decodeOPC='1' THEN + micronext <="01000000"; + microstep <='1'; + set_exec_MOVE <= '1'; --für displacement + presub <= '1'; + setstackaddr <='1'; + set_mem_addsub <= '1'; + source_lowbits <= '1'; + source_areg <= '1'; + END IF; + IF execOPC='1' THEN + setstackaddr <='1'; + regwrena <= '1'; + END IF; + + WHEN "1011000"|"1011001"|"1011010"|"1011011"|"1011100"|"1011101"|"1011110"|"1011111" => --unlink + datatype <= "10"; + IF decodeOPC='1' THEN + setstate <= "10"; + set_mem_rega <= '1'; + ELSIF execOPC='1' THEN + regwrena <= '1'; + exec_exg <= '1'; + ELSE + setstackaddr <='1'; + regwrena <= '1'; + get_ea_now <= '1'; + ea_only <= '1'; + END IF; + + WHEN "1100000"|"1100001"|"1100010"|"1100011"|"1100100"|"1100101"|"1100110"|"1100111" => --move An,USP + IF SVmode='1' THEN + no_Flags <= '1'; + to_USP <= '1'; + setstackaddr <= '1'; + source_lowbits <= '1'; + source_areg <= '1'; + set_exec_MOVE <= '1'; + datatype <= "10"; + IF execOPC='1' THEN + regwrena <= '1'; + END IF; + ELSE + trap_priv <= '1'; + trap <= '1'; + END IF; + WHEN "1101000"|"1101001"|"1101010"|"1101011"|"1101100"|"1101101"|"1101110"|"1101111" => --move USP,An + IF SVmode='1' THEN + no_Flags <= '1'; + from_USP <= '1'; + set_exec_MOVE <= '1'; + datatype <= "10"; + IF execOPC='1' THEN + regwrena <= '1'; + END IF; + ELSE + trap_priv <= '1'; + trap <= '1'; + END IF; + + WHEN "1110000" => --reset + IF SVmode='0' THEN + trap_priv <= '1'; + trap <= '1'; + END IF; + + WHEN "1110001" => --nop + + WHEN "1110010" => --stop + IF SVmode='0' THEN + trap_priv <= '1'; + trap <= '1'; + ELSE + IF decodeOPC='1' THEN + setnextpass <= '1'; + set_directSR <= '1'; + set_stop <= '1'; + END IF; + END IF; + + WHEN "1110011" => --rte + IF SVmode='1' THEN + IF decodeOPC='1' THEN + datatype <= "01"; + setstate <= "10"; + postadd <= '1'; + setstackaddr <= '1'; + set_mem_rega <= '1'; + set_directSR <= '1'; + microstep <='1'; + micronext <= "01001000"; + END IF; + ELSE + trap_priv <= '1'; + trap <= '1'; + END IF; + + WHEN "1110101" => --rts + IF decodeOPC='1' THEN + datatype <= "10"; + setstate <= "10"; + postadd <= '1'; + setstackaddr <= '1'; + set_mem_rega <= '1'; + set_directPC <= '1'; + microstep <='1'; + END IF; + + WHEN "1110110" => --trapv + IF Flags(1)='1' THEN + trap_trapv <= '1'; + trap <= '1'; + END IF; + + WHEN OTHERS => + trap_illegal <= '1'; + trap <= '1'; + END CASE; + END IF; + END CASE; + END IF; + +-- 0101 ---------------------------------------------------------------------------- + WHEN "0101" => --subq, addq + + IF opcode(7 downto 6)="11" THEN --dbcc + IF opcode(5 downto 3)="001" THEN --dbcc + datatype <= "01"; --Word + IF decodeOPC='1' THEN + OP2out_one <= '1'; + IF condition='0' THEN + Regwrena <= '1'; + IF c_in(2)='1' THEN + micronext <="00011110"; + END IF; + END IF; + data_is_source <= '1'; + microstep <='1'; + END IF; + ELSE --Scc + datatype <= "00"; --Byte + write_back <= '1'; + IF decodeOPC='1' THEN + ea_build <= '1'; + END IF; + IF condition='0' THEN + set_exec_Scc <= '1'; + END IF; + IF execOPC='1' THEN + IF condition='1' THEN + OP2out_one <= '1'; + exec_EXG <= '1'; + ELSE + OP1out_zero <= '1'; + END IF; + IF endOPC='1' THEN + Regwrena <= '1'; + END IF; + END IF; + END IF; + ELSE --addq, subq + IF decodeOPC='1' THEN + ea_build <= '1'; + END IF; + IF opcode(5 downto 3)="001" THEN + no_Flags <= '1'; + END IF; + write_back <= '1'; + set_exec_ADDQ <= '1'; + set_exec_ADD <= '1'; + IF execOPC='1' THEN + ea_data_OP1 <= '1'; + IF endOPC='1' THEN + Regwrena <= '1'; + END IF; + IF opcode(8)='1' THEN + setaddsub <= '0'; + END IF; + END IF; + END IF; + +-- 0110 ---------------------------------------------------------------------------- + WHEN "0110" => --bra,bsr,bcc + datatype <= "10"; + + IF prefix='0' THEN + IF opcode(11 downto 8)="0001" THEN --bsr + IF opcode(7 downto 0)="00000000" THEN + micronext <="00011000"; + ELSE + micronext <="00011001"; + setstate <= "01"; + END IF; + microstep <='1'; + presub <= '1'; + setstackaddr <='1'; + set_mem_addsub <= '1'; + ELSE --bra + IF opcode(7 downto 0)="00000000" THEN + microstep <='1'; + micronext <="00010010"; + END IF; + IF condition='1' THEN + TG68_PC_br8 <= '1'; + END IF; + END IF; + END IF; + +-- 0111 ---------------------------------------------------------------------------- + WHEN "0111" => --moveq + IF opcode(8)='0' THEN + IF trap_interrupt='0' THEN + datatype <= "10"; --Long + Regwrena <= '1'; + set_exec_MOVEQ <= '1'; + set_exec_MOVE <= '1'; + dest_hbits <= '1'; + END IF; + ELSE + trap_illegal <= '1'; + trap <= '1'; + END IF; + +-- 1000 ---------------------------------------------------------------------------- + WHEN "1000" => --or + IF opcode(7 downto 6)="11" THEN --divu, divs + IF opcode(5 downto 4)="00" THEN --Dn, An + regdirectsource <= '1'; + END IF; + IF (prefix='0' AND nextpass='1') OR (opcode(5 downto 4)="00" AND decodeOPC='1') THEN + set_exec_DIVU <= '1'; + setstate <="01"; + microstep <='1'; + micronext <="10100000"; + END IF; + IF decodeOPC='1' THEN + ea_build <= '1'; + END IF; + IF execOPC='1' AND z_error='0' AND set_V_Flag='0' THEN + regwrena <= '1'; + END IF; + IF (prefix='1' AND nextpass='1') OR execOPC='1' THEN + dest_hbits <= '1'; + source_lowbits <='1'; + ELSE + datatype <= "01"; + END IF; + + + ELSIF opcode(8)='1' AND opcode(5 downto 4)="00" THEN --sbcd, pack , unpack + IF opcode(7 downto 6)="00" THEN --sbcd + use_XZFlag <= '1'; + set_exec_ADD <= '1'; + set_exec_SBCD <= '1'; + IF opcode(3)='1' THEN + write_back <= '1'; + IF decodeOPC='1' THEN + set_direct_data <= '1'; + setstate <= "10"; + set_mem_addsub <= '1'; + presub <= '1'; + microstep <='1'; + micronext <="00110000"; + END IF; + END IF; + IF execOPC='1' THEN + ea_data_OP1 <= '1'; + dest_hbits <= '1'; + source_lowbits <='1'; + IF endOPC='1' THEN + Regwrena <= '1'; + END IF; + END IF; + ELSE --pack, unpack + trap_illegal <= '1'; + trap <= '1'; + END IF; + ELSE --or + set_exec_OR <= '1'; + IF opcode(8)='1' THEN + write_back <= '1'; + END IF; + IF decodeOPC='1' THEN + ea_build <= '1'; + END IF; + IF execOPC='1' THEN + IF endOPC='1' THEN + Regwrena <= '1'; + END IF; + IF opcode(8)='1' THEN + ea_data_OP1 <= '1'; + ELSE + dest_hbits <= '1'; + source_lowbits <='1'; + IF opcode(3)='1' THEN + source_areg <= '1'; + END IF; + END IF; + END IF; + END IF; + +-- 1001, 1101 ----------------------------------------------------------------------- + WHEN "1001"|"1101" => --sub, add + set_exec_ADD <= '1'; + IF decodeOPC='1' THEN + ea_build <= '1'; + END IF; + IF opcode(8 downto 6)="011" THEN --adda.w, suba.w + datatype <= "01"; --Word + END IF; + IF execOPC='1' THEN + IF endOPC='1' THEN + Regwrena <= '1'; + END IF; + IF opcode(14)='0' THEN + setaddsub <= '0'; + END IF; + END IF; + IF opcode(8)='1' AND opcode(5 downto 4)="00" AND opcode(7 downto 6)/="11" THEN --addx, subx + use_XZFlag <= '1'; + IF opcode(3)='1' THEN + write_back <= '1'; + IF decodeOPC='1' THEN + set_direct_data <= '1'; + setstate <= "10"; + set_mem_addsub <= '1'; + presub <= '1'; + microstep <='1'; + micronext <="00110000"; + END IF; + END IF; + IF execOPC='1' THEN + ea_data_OP1 <= '1'; + dest_hbits <= '1'; + source_lowbits <='1'; + END IF; + ELSE --sub, add + IF opcode(8)='1' AND opcode(7 downto 6)/="11" THEN + write_back <= '1'; + END IF; + IF execOPC='1' THEN + IF opcode(7 downto 6)="11" THEN --adda, suba + no_Flags <= '1'; + dest_areg <='1'; + dest_hbits <= '1'; + source_lowbits <='1'; + IF opcode(3)='1' THEN + source_areg <= '1'; + END IF; + ELSE + IF opcode(8)='1' THEN + ea_data_OP1 <= '1'; + ELSE + dest_hbits <= '1'; + source_lowbits <='1'; + IF opcode(3)='1' THEN + source_areg <= '1'; + END IF; + END IF; + END IF; + END IF; + END IF; + +-- 1010 ---------------------------------------------------------------------------- + WHEN "1010" => --Trap 1010 + trap_1010 <= '1'; + trap <= '1'; +-- 1011 ---------------------------------------------------------------------------- + WHEN "1011" => --eor, cmp + IF decodeOPC='1' THEN + ea_build <= '1'; + END IF; + IF opcode(8 downto 6)="011" THEN --cmpa.w + datatype <= "01"; --Word + set_exec_CPMAW <= '1'; + END IF; + IF opcode(8)='1' AND opcode(5 downto 3)="001" AND opcode(7 downto 6)/="11" THEN --cmpm + set_exec_CMP <= '1'; + IF decodeOPC='1' THEN + set_direct_data <= '1'; + setstate <= "10"; + set_mem_rega <= '1'; + postadd <= '1'; + microstep <='1'; + micronext <="00110010"; + END IF; + IF execOPC='1' THEN + ea_data_OP1 <= '1'; + setaddsub <= '0'; + END IF; + ELSE --sub, add + IF opcode(8)='1' AND opcode(7 downto 6)/="11" THEN --eor + set_exec_EOR <= '1'; + write_back <= '1'; + ELSE --cmp + set_exec_CMP <= '1'; + END IF; + + IF execOPC='1' THEN + IF opcode(8)='1' AND opcode(7 downto 6)/="11" THEN --eor + ea_data_OP1 <= '1'; + IF endOPC='1' THEN + Regwrena <= '1'; + END IF; + ELSE --cmp + source_lowbits <='1'; + IF opcode(3)='1' THEN + source_areg <= '1'; + END IF; + IF opcode(7 downto 6)="11" THEN --cmpa + dest_areg <='1'; + END IF; + dest_hbits <= '1'; + setaddsub <= '0'; + END IF; + END IF; + END IF; + +-- 1100 ---------------------------------------------------------------------------- + WHEN "1100" => --and, exg + IF opcode(7 downto 6)="11" THEN --mulu, muls + IF opcode(5 downto 4)="00" THEN --Dn, An + regdirectsource <= '1'; + END IF; + IF (prefix='0' AND nextpass='1') OR (opcode(5 downto 4)="00" AND decodeOPC='1') THEN + set_exec_MULU <= '1'; + setstate <="01"; + microstep <='1'; + micronext <="10000000"; + END IF; + IF decodeOPC='1' THEN + ea_build <= '1'; + END IF; + IF execOPC='1' THEN + regwrena <= '1'; + END IF; + IF (prefix='1' AND nextpass='1') OR execOPC='1' THEN + dest_hbits <= '1'; + source_lowbits <='1'; + ELSE + datatype <= "01"; + END IF; + + ELSIF opcode(8)='1' AND opcode(5 downto 4)="00" THEN --exg, abcd + IF opcode(7 downto 6)="00" THEN --abcd + use_XZFlag <= '1'; +-- datatype <= "00"; --ist schon default + set_exec_ADD <= '1'; + set_exec_ABCD <= '1'; + IF opcode(3)='1' THEN + write_back <= '1'; + IF decodeOPC='1' THEN + set_direct_data <= '1'; + setstate <= "10"; + set_mem_addsub <= '1'; + presub <= '1'; + microstep <='1'; + micronext <="00110000"; + END IF; + END IF; + IF execOPC='1' THEN + ea_data_OP1 <= '1'; + dest_hbits <= '1'; + source_lowbits <='1'; + IF endOPC='1' THEN + Regwrena <= '1'; + END IF; + END IF; + ELSE --exg + datatype <= "10"; + regwrena <= '1'; + IF opcode(6)='1' AND opcode(3)='1' THEN + dest_areg <= '1'; + source_areg <= '1'; + END IF; + IF decodeOPC='1' THEN + set_mem_rega <= '1'; + exec_exg <= '1'; + ELSE + save_memaddr <= '1'; + dest_hbits <= '1'; + END IF; + END IF; + ELSE --and + set_exec_AND <= '1'; + IF opcode(8)='1' THEN + write_back <= '1'; + END IF; + IF decodeOPC='1' THEN + ea_build <= '1'; + END IF; + + IF execOPC='1' THEN + IF endOPC='1' THEN + Regwrena <= '1'; + END IF; + IF opcode(8)='1' THEN + ea_data_OP1 <= '1'; + ELSE + dest_hbits <= '1'; + source_lowbits <='1'; + IF opcode(3)='1' THEN + source_areg <= '1'; + END IF; + END IF; + END IF; + END IF; + +-- 1110 ---------------------------------------------------------------------------- + WHEN "1110" => --rotation + set_exec_ROT <= '1'; + IF opcode(7 downto 6)="11" THEN + datatype <= "01"; + rot_bits <= opcode(10 downto 9); + ea_data_OP1 <= '1'; + write_back <= '1'; + ELSE + rot_bits <= opcode(4 downto 3); + data_is_source <= '1'; + END IF; + + IF decodeOPC='1' THEN + IF opcode(7 downto 6)="11" THEN + ea_build <= '1'; + ELSE + IF opcode(5)='1' THEN + IF OP2out(5 downto 0)/="000000" THEN + set_rot_cnt <= OP2out(5 downto 0); +-- ELSE +-- set_no_Flags <='1'; + END IF; + ELSE + set_rot_cnt(2 downto 0) <= opcode(11 downto 9); + IF opcode(11 downto 9)="000" THEN + set_rot_cnt(3) <='1'; + ELSE + set_rot_cnt(3) <='0'; + END IF; + END IF; + END IF; + END IF; + IF opcode(7 downto 6)/="11" THEN + IF opcode(5)='1' AND OP2out(5 downto 0)="000000" THEN --Macht Fehler wenn mit sich selbst geschoben wird +-- no_Flags <= '1'; + rot_nop <= '1'; + ELSIF execOPC='1' THEN + Regwrena <= '1'; + set_rot_cnt <= rot_cnt-1; + END IF; + END IF; + +-- ---------------------------------------------------------------------------- + WHEN OTHERS => + trap_1111 <= '1'; + trap <= '1'; + + END CASE; + +-- END PROCESS; + +----------------------------------------------------------------------------- +-- execute microcode +----------------------------------------------------------------------------- +--PROCESS (microaddr) +-- BEGIN + IF Z_error='1' THEN -- divu by zero + trap <= '1'; --wichtig für USP + IF trapd='0' THEN + writePC <= '1'; + microset <= '1'; + END IF; + END IF; + + IF trap='1' AND trapd='0' THEN + microstep <= '1'; + micronext <= "01010000"; + presub <= '1'; + setstackaddr <='1'; + set_mem_addsub <= '1'; + setstate <= "11"; + datatype <= "10"; + END IF; + + IF interrupt='1' THEN + microstep <= '1'; + micronext <= "01000100"; + setstate <= "10"; +-- datatype <= "01"; --wirkt sich auf Flags aus + END IF; + + + IF reset='0' THEN + microaddr <= "01100000"; --init + prefix <= '1'; + ELSIF rising_edge(clk) THEN + IF clkena='1' THEN + trapd <= trap; + prefix <= (prefix AND ea_build) OR (microstep AND NOT fetchOPC); + IF prefix='1' AND ea_build='0' AND microset='0' THEN + microaddr <= microaddr + micronext; + ELSE + microaddr <= micronext; + END IF; + END IF; + END IF; + IF prefix='1' THEN + CASE microaddr IS + WHEN "00000001" => -- nop + + WHEN "00000010" => -- (nnnn).w/l=> + get_ea_now <='1'; + setnextpass <= '1'; + setaddrlong <= '1'; + + WHEN "00000011" => -- =>(nnnn).w/l + setstate <= "11"; + setaddrlong <= '1'; + microstep <='1'; + + WHEN "00000110" => -- d(An)=>, --d(PC)=> + microstep <='1'; + setstate <= "01"; + WHEN "00000111" => -- d(An)=>, --d(PC)=> + get_ea_now <='1'; + setdisp <= '1'; --word + setnextpass <= '1'; + + WHEN "00001000" => -- d(An,Xn)=>, --d(PC,Xn)=> + microstep <='1'; + setstate <= "01"; + WHEN "00001001" => -- d(An,Xn)=>, --d(PC,Xn)=> + setdisp <= '1'; --byte + setdispbyte <= '1'; + microstep <='1'; + setstate <= "01"; + setbriefext <= '1'; + WHEN "00001010" => + get_ea_now <='1'; + setdisp <= '1'; --brief + setdispbrief <= '1'; + setnextpass <= '1'; + + WHEN "00001011" => -- =>d(An) + microstep <='1'; + setstate <= "01"; + WHEN "00001100" => -- =>d(An) + setstate <= "11"; + setdisp <= '1'; --word + microstep <='1'; + WHEN "00001101" => + + WHEN "00001110" => -- =>d(An,Xn) + microstep <='1'; + setstate <= "01"; + WHEN "00001111" => -- =>d(An,Xn) + setdisp <= '1'; --byte + setdispbyte <= '1'; + microstep <='1'; + setstate <= "01"; + setbriefext <= '1'; + WHEN "00010000" => + setstate <= "11"; + setdisp <= '1'; --brief + setdispbrief <= '1'; + microstep <='1'; + WHEN "00010001" => + + WHEN "00010010" => --bra + IF condition='1' THEN + TG68_PC_br8 <= '1'; --pc+0000 + microstep <='1'; + setstate <= "01"; + END IF; + WHEN "00010011" => --bra + TG68_PC_brw <= '1'; + + WHEN "00011000" => --bsr + set_TG68_PC_dec <= '1'; --in 2 Takten -2 + microstep <='1'; + setstate <= "01"; + WHEN "00011001" => --bsr + IF TG68_PC_dec(0)='1' THEN + TG68_PC_brw <= '1'; + ELSE + TG68_PC_br8 <= '1'; + END IF; + writePC <= '1'; + setstate <= "11"; + microstep <='1'; + WHEN "00011010" => --bsr + + WHEN "00011110" => --dbcc + TG68_PC_nop <= '1'; + microstep <='1'; + setstate <= "01"; + WHEN "00011111" => --dbcc + TG68_PC_brw <= '1'; + + WHEN "00100010" => --movem + set_movem_busy <='1'; + setstate <= "10"; + + WHEN "00101000" => --andi + IF opcode(5 downto 4)/="00" THEN + ea_build <= '1'; + setnextpass <= '1'; + END IF; + + WHEN "00101100" => --jsr + presub <= '1'; + setstackaddr <='1'; + set_mem_addsub <= '1'; + setstate <= "11"; + + WHEN "00110000" => -- op -(Ax),-(Ay) + presub <= '1'; + dest_hbits <= '1'; + dest_areg <= '1'; + set_mem_addsub <= '1'; + setstate <= "10"; + + WHEN "00110010" => -- cmpm (Ay)+,(Ax)+ + postadd <= '1'; + dest_hbits <= '1'; + dest_areg <= '1'; + set_mem_rega <= '1'; + setstate <= "10"; + + WHEN "01000000" => -- link + setstate <="11"; + save_memaddr <= '1'; + regwrena <= '1'; + + WHEN "01000100" => -- interrupt + microstep <= '1'; + presub <= '1'; + setstackaddr <='1'; + set_mem_addsub <= '1'; + setstate <= "11"; + datatype <= "10"; + WHEN "01000101" => -- interrupt + microstep <= '1'; + presub <= '1'; + setstackaddr <='1'; + set_mem_addsub <= '1'; + setstate <= "11"; + datatype <= "01"; + writeSR <= '1'; + WHEN "01000110" => -- interrupt + set_vectoraddr <= '1'; + datatype <= "10"; + set_directPC <= '1'; + microstep <='1'; + + setstate <= "10"; + WHEN "01000111" => -- interrupt + datatype <= "10"; + + WHEN "01001000" => -- RTE + datatype <= "10"; + setstate <= "10"; + postadd <= '1'; + setstackaddr <= '1'; + set_mem_rega <= '1'; + set_directPC <= '1'; + microstep <='1'; + + WHEN "01010000" => -- TRAP + microstep <= '1'; + presub <= '1'; + setstackaddr <='1'; + set_mem_addsub <= '1'; + setstate <= "11"; + datatype <= "01"; + writeSR <= '1'; + WHEN "01010001" => -- TRAP + set_vectoraddr <= '1'; + datatype <= "10"; + set_directPC <= '1'; + microstep <='1'; +-- longreaddirect <= '1'; + setstate <= "10"; + WHEN "01010010" => -- TRAP + datatype <= "10"; + + + + + WHEN "01100000" => -- init SP + microstep <='1'; + longreaddirect <= '1'; + WHEN "01100001" => -- init PC + get_ea_now <='1'; --\ + ea_only <= '1'; --- OP1in <= memaddr_in + setaddrlong <= '1'; -- memaddr_in <= data_read + regwrena <= '1'; + setstackaddr <='1'; -- dest_addr <= SP + set_directPC <= '1'; + microstep <='1'; + longreaddirect <= '1'; +-- WHEN "01100010" => -- wr SP + + + + + WHEN "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"| + "10000111"|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101" => -- mulu + microstep <='1'; + set_exec_MULU <= '1'; + setstate <="01"; + WHEN "10001110" => -- mulu + set_exec_MULU <= '1'; + + + WHEN "10100000" => -- divu + IF OP2out(15 downto 0)=x"0000" THEN --div zero + set_Z_error <= '1'; + microset <= '1'; + ELSE + set_exec_DIVU <= '1'; + END IF; + setstate <="01"; + microstep <='1'; + WHEN "10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100110"|"10100111"| + "10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101" => -- divu + microstep <='1'; + set_exec_DIVU <= '1'; + setstate <="01"; + WHEN "10101110" => -- divu + set_exec_DIVU <= '1'; + + + WHEN OTHERS => + END CASE; + END IF; + END PROCESS; + +----------------------------------------------------------------------------- +-- Conditions +----------------------------------------------------------------------------- +PROCESS (opcode, Flags) + BEGIN + CASE opcode(11 downto 8) IS + WHEN X"0" => condition <= '1'; + WHEN X"1" => condition <= '0'; + WHEN X"2" => condition <= NOT Flags(0) AND NOT Flags(2); + WHEN X"3" => condition <= Flags(0) OR Flags(2); + WHEN X"4" => condition <= NOT Flags(0); + WHEN X"5" => condition <= Flags(0); + WHEN X"6" => condition <= NOT Flags(2); + WHEN X"7" => condition <= Flags(2); + WHEN X"8" => condition <= NOT Flags(1); + WHEN X"9" => condition <= Flags(1); + WHEN X"a" => condition <= NOT Flags(3); + WHEN X"b" => condition <= Flags(3); + WHEN X"c" => condition <= (Flags(3) AND Flags(1)) OR (NOT Flags(3) AND NOT Flags(1)); + WHEN X"d" => condition <= (Flags(3) AND NOT Flags(1)) OR (NOT Flags(3) AND Flags(1)); + WHEN X"e" => condition <= (Flags(3) AND Flags(1) AND NOT Flags(2)) OR (NOT Flags(3) AND NOT Flags(1) AND NOT Flags(2)); + WHEN X"f" => condition <= (Flags(3) AND NOT Flags(1)) OR (NOT Flags(3) AND Flags(1)) OR Flags(2); + END CASE; + END PROCESS; + +----------------------------------------------------------------------------- +-- Bits +----------------------------------------------------------------------------- +PROCESS (opcode, OP1out, OP2out, one_bit_in, one_bit_out, bit_Number, bit_number_reg) + BEGIN + CASE opcode(7 downto 6) IS + WHEN "00" => --btst + one_bit_out <= one_bit_in; + WHEN "01" => --bchg + one_bit_out <= NOT one_bit_in; + WHEN "10" => --bclr + one_bit_out <= '0'; + WHEN "11" => --bset + one_bit_out <= '1'; + END CASE; + + IF opcode(8)='0' THEN + IF opcode(5 downto 4)="00" THEN + bit_number <= bit_number_reg(4 downto 0); + ELSE + bit_number <= "00"&bit_number_reg(2 downto 0); + END IF; + ELSE + IF opcode(5 downto 4)="00" THEN + bit_number <= OP2out(4 downto 0); + ELSE + bit_number <= "00"&OP2out(2 downto 0); + END IF; + END IF; + + bits_out <= OP1out; + CASE bit_Number IS + WHEN "00000" => one_bit_in <= OP1out(0); + bits_out(0) <= one_bit_out; + WHEN "00001" => one_bit_in <= OP1out(1); + bits_out(1) <= one_bit_out; + WHEN "00010" => one_bit_in <= OP1out(2); + bits_out(2) <= one_bit_out; + WHEN "00011" => one_bit_in <= OP1out(3); + bits_out(3) <= one_bit_out; + WHEN "00100" => one_bit_in <= OP1out(4); + bits_out(4) <= one_bit_out; + WHEN "00101" => one_bit_in <= OP1out(5); + bits_out(5) <= one_bit_out; + WHEN "00110" => one_bit_in <= OP1out(6); + bits_out(6) <= one_bit_out; + WHEN "00111" => one_bit_in <= OP1out(7); + bits_out(7) <= one_bit_out; + WHEN "01000" => one_bit_in <= OP1out(8); + bits_out(8) <= one_bit_out; + WHEN "01001" => one_bit_in <= OP1out(9); + bits_out(9) <= one_bit_out; + WHEN "01010" => one_bit_in <= OP1out(10); + bits_out(10) <= one_bit_out; + WHEN "01011" => one_bit_in <= OP1out(11); + bits_out(11) <= one_bit_out; + WHEN "01100" => one_bit_in <= OP1out(12); + bits_out(12) <= one_bit_out; + WHEN "01101" => one_bit_in <= OP1out(13); + bits_out(13) <= one_bit_out; + WHEN "01110" => one_bit_in <= OP1out(14); + bits_out(14) <= one_bit_out; + WHEN "01111" => one_bit_in <= OP1out(15); + bits_out(15) <= one_bit_out; + WHEN "10000" => one_bit_in <= OP1out(16); + bits_out(16) <= one_bit_out; + WHEN "10001" => one_bit_in <= OP1out(17); + bits_out(17) <= one_bit_out; + WHEN "10010" => one_bit_in <= OP1out(18); + bits_out(18) <= one_bit_out; + WHEN "10011" => one_bit_in <= OP1out(19); + bits_out(19) <= one_bit_out; + WHEN "10100" => one_bit_in <= OP1out(20); + bits_out(20) <= one_bit_out; + WHEN "10101" => one_bit_in <= OP1out(21); + bits_out(21) <= one_bit_out; + WHEN "10110" => one_bit_in <= OP1out(22); + bits_out(22) <= one_bit_out; + WHEN "10111" => one_bit_in <= OP1out(23); + bits_out(23) <= one_bit_out; + WHEN "11000" => one_bit_in <= OP1out(24); + bits_out(24) <= one_bit_out; + WHEN "11001" => one_bit_in <= OP1out(25); + bits_out(25) <= one_bit_out; + WHEN "11010" => one_bit_in <= OP1out(26); + bits_out(26) <= one_bit_out; + WHEN "11011" => one_bit_in <= OP1out(27); + bits_out(27) <= one_bit_out; + WHEN "11100" => one_bit_in <= OP1out(28); + bits_out(28) <= one_bit_out; + WHEN "11101" => one_bit_in <= OP1out(29); + bits_out(29) <= one_bit_out; + WHEN "11110" => one_bit_in <= OP1out(30); + bits_out(30) <= one_bit_out; + WHEN "11111" => one_bit_in <= OP1out(31); + bits_out(31) <= one_bit_out; + WHEN OTHERS => + END CASE; + END PROCESS; + +----------------------------------------------------------------------------- +-- Rotation +----------------------------------------------------------------------------- +PROCESS (opcode, OP1out, Flags, rot_bits, rot_msb, rot_lsb, rot_rot, rot_nop) + BEGIN + CASE opcode(7 downto 6) IS + WHEN "00" => --Byte + rot_rot <= OP1out(7); + WHEN "01"|"11" => --Word + rot_rot <= OP1out(15); + WHEN "10" => --Long + rot_rot <= OP1out(31); + END CASE; + + CASE rot_bits IS + WHEN "00" => --ASL, ASR + rot_lsb <= '0'; + rot_msb <= rot_rot; + WHEN "01" => --LSL, LSR + rot_lsb <= '0'; + rot_msb <= '0'; + WHEN "10" => --ROXL, ROXR + rot_lsb <= Flags(4); + rot_msb <= Flags(4); + WHEN "11" => --ROL, ROR + rot_lsb <= rot_rot; + rot_msb <= OP1out(0); + END CASE; + + IF rot_nop='1' THEN + rot_out <= OP1out; + rot_XC <= Flags(0); + ELSE + IF opcode(8)='1' THEN --left + rot_out <= OP1out(30 downto 0)&rot_lsb; + rot_XC <= rot_rot; + ELSE --right + rot_XC <= OP1out(0); + rot_out <= rot_msb&OP1out(31 downto 1); + CASE opcode(7 downto 6) IS + WHEN "00" => --Byte + rot_out(7) <= rot_msb; + WHEN "01"|"11" => --Word + rot_out(15) <= rot_msb; + WHEN OTHERS => + END CASE; + END IF; + END IF; + END PROCESS; + +----------------------------------------------------------------------------- +-- MULU/MULS +----------------------------------------------------------------------------- +PROCESS (clk, opcode, OP2out, muls_msb, mulu_reg, OP1sign, sign2) + BEGIN + IF rising_edge(clk) THEN + IF clkena='1' THEN + IF decodeOPC='1' THEN + IF opcode(8)='1' AND reg_QB(15)='1' THEN --MULS Neg faktor + OP1sign <= '1'; + mulu_reg <= "0000000000000000"&(0-reg_QB(15 downto 0)); + ELSE + OP1sign <= '0'; + mulu_reg <= "0000000000000000"®_QB(15 downto 0); + END IF; + ELSIF exec_MULU='1' THEN + mulu_reg <= dummy_mulu; + END IF; + END IF; + END IF; + + IF (opcode(8)='1' AND OP2out(15)='1') OR OP1sign='1' THEN + muls_msb <= mulu_reg(31); + ELSE + muls_msb <= '0'; + END IF; + + IF opcode(8)='1' AND OP2out(15)='1' THEN + sign2 <= '1'; + ELSE + sign2 <= '0'; + END IF; + + IF mulu_reg(0)='1' THEN + IF OP1sign='1' THEN + dummy_mulu <= (muls_msb&mulu_reg(31 downto 16))-(sign2&OP2out(15 downto 0))& mulu_reg(15 downto 1); + ELSE + dummy_mulu <= (muls_msb&mulu_reg(31 downto 16))+(sign2&OP2out(15 downto 0))& mulu_reg(15 downto 1); + END IF; + ELSE + dummy_mulu <= muls_msb&mulu_reg(31 downto 1); + END IF; + END PROCESS; + +----------------------------------------------------------------------------- +-- DIVU +----------------------------------------------------------------------------- +PROCESS (clk, execOPC, opcode, OP1out, OP2out, div_reg, dummy_div_sub, div_quot, div_sign, dummy_div_over, dummy_div) + BEGIN + set_V_Flag <= '0'; + + IF rising_edge(clk) THEN + IF clkena='1' THEN + IF decodeOPC='1' THEN + IF opcode(8)='1' AND reg_QB(31)='1' THEN -- Neg divisor + div_sign <= '1'; + div_reg <= 0-reg_QB; + ELSE + div_sign <= '0'; + div_reg <= reg_QB; + END IF; + ELSIF exec_DIVU='1' THEN + div_reg <= div_quot; + END IF; + END IF; + END IF; + + dummy_div_over <= ('0'&OP1out(31 downto 16))-('0'&OP2out(15 downto 0)); + + IF opcode(8)='1' AND OP2out(15) ='1' THEN + dummy_div_sub <= (div_reg(31 downto 15))+('1'&OP2out(15 downto 0)); + ELSE + dummy_div_sub <= (div_reg(31 downto 15))-('0'&OP2out(15 downto 0)); + END IF; + + IF (dummy_div_sub(16))='1' THEN + div_quot(31 downto 16) <= div_reg(30 downto 15); + ELSE + div_quot(31 downto 16) <= dummy_div_sub(15 downto 0); + END IF; + + div_quot(15 downto 0) <= div_reg(14 downto 0)&NOT dummy_div_sub(16); + + IF execOPC='1' AND opcode(8)='1' AND (OP2out(15) XOR div_sign)='1' THEN + dummy_div(15 downto 0) <= 0-div_quot(15 downto 0); + ELSE + dummy_div(15 downto 0) <= div_quot(15 downto 0); + END IF; + + IF div_sign='1' THEN + dummy_div(31 downto 16) <= 0-div_quot(31 downto 16); + ELSE + dummy_div(31 downto 16) <= div_quot(31 downto 16); + END IF; + + IF (opcode(8)='1' AND (OP2out(15) XOR div_sign XOR dummy_div(15))='1' AND dummy_div(15 downto 0)/=X"0000") --Overflow DIVS + OR (opcode(8)='0' AND dummy_div_over(16)='0') THEN --Overflow DIVU + set_V_Flag <= '1'; + END IF; + END PROCESS; + +----------------------------------------------------------------------------- +-- Movem +----------------------------------------------------------------------------- +PROCESS (reset, clk, movem_mask, movem_muxa ,movem_muxb, movem_muxc) + BEGIN + IF movem_mask(7 downto 0)="00000000" THEN + movem_muxa <= movem_mask(15 downto 8); + movem_regaddr(3) <= '1'; + ELSE + movem_muxa <= movem_mask(7 downto 0); + movem_regaddr(3) <= '0'; + END IF; + IF movem_muxa(3 downto 0)="0000" THEN + movem_muxb <= movem_muxa(7 downto 4); + movem_regaddr(2) <= '1'; + ELSE + movem_muxb <= movem_muxa(3 downto 0); + movem_regaddr(2) <= '0'; + END IF; + IF movem_muxb(1 downto 0)="00" THEN + movem_muxc <= movem_muxb(3 downto 2); + movem_regaddr(1) <= '1'; + ELSE + movem_muxc <= movem_muxb(1 downto 0); + movem_regaddr(1) <= '0'; + END IF; + IF movem_muxc(0)='0' THEN + movem_regaddr(0) <= '1'; + ELSE + movem_regaddr(0) <= '0'; + END IF; + + movem_bits <= ("0000"&movem_mask(0))+("0000"&movem_mask(1))+("0000"&movem_mask(2))+("0000"&movem_mask(3))+ + ("0000"&movem_mask(4))+("0000"&movem_mask(5))+("0000"&movem_mask(6))+("0000"&movem_mask(7))+ + ("0000"&movem_mask(8))+("0000"&movem_mask(9))+("0000"&movem_mask(10))+("0000"&movem_mask(11))+ + ("0000"&movem_mask(12))+("0000"&movem_mask(13))+("0000"&movem_mask(14))+("0000"&movem_mask(15)); + + IF reset = '0' THEN + movem_busy <= '0'; + movem_addr <= '0'; + ELSIF rising_edge(clk) THEN + IF clkena_in='1' AND get_movem_mask='1' THEN + movem_mask <= data_read(15 downto 0); + END IF; + IF clkena='1' THEN + IF set_movem_busy='1' THEN + IF movem_bits(3 downto 1) /= "000" OR opcode(10)='0' THEN + movem_busy <= '1'; + END IF; + movem_addr <= '1'; + END IF; + IF movem_addr='1' THEN + CASE movem_regaddr IS + WHEN "0000" => movem_mask(0) <= '0'; + WHEN "0001" => movem_mask(1) <= '0'; + WHEN "0010" => movem_mask(2) <= '0'; + WHEN "0011" => movem_mask(3) <= '0'; + WHEN "0100" => movem_mask(4) <= '0'; + WHEN "0101" => movem_mask(5) <= '0'; + WHEN "0110" => movem_mask(6) <= '0'; + WHEN "0111" => movem_mask(7) <= '0'; + WHEN "1000" => movem_mask(8) <= '0'; + WHEN "1001" => movem_mask(9) <= '0'; + WHEN "1010" => movem_mask(10) <= '0'; + WHEN "1011" => movem_mask(11) <= '0'; + WHEN "1100" => movem_mask(12) <= '0'; + WHEN "1101" => movem_mask(13) <= '0'; + WHEN "1110" => movem_mask(14) <= '0'; + WHEN "1111" => movem_mask(15) <= '0'; + END CASE; + IF opcode(10)='1' THEN + IF movem_bits="00010" OR movem_bits="00001" OR movem_bits="00000" THEN + movem_busy <= '0'; + END IF; + END IF; + IF movem_bits="00001" OR movem_bits="00000" THEN + movem_busy <= '0'; + movem_addr <= '0'; + END IF; + END IF; + END IF; + END IF; + END PROCESS; +END; Index: tg68/tags/arelease/VHDL/TG68.vhd =================================================================== --- tg68/tags/arelease/VHDL/TG68.vhd (nonexistent) +++ tg68/tags/arelease/VHDL/TG68.vhd (revision 10) @@ -0,0 +1,214 @@ +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ +-- -- +-- This is the TOP-Level for TG68_fast to generate 68K Bus signals -- +-- -- +-- Copyright (c) 2007 Tobias Gubener -- +-- -- +-- This source file is free software: you can redistribute it and/or modify -- +-- it under the terms of the GNU Lesser General Public License as published -- +-- by the Free Software Foundation, either version 3 of the License, or -- +-- (at your option) any later version. -- +-- -- +-- This source file is distributed in the hope that it will be useful, -- +-- but WITHOUT ANY WARRANTY; without even the implied warranty of -- +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- +-- GNU General Public License for more details. -- +-- -- +-- You should have received a copy of the GNU General Public License -- +-- along with this program. If not, see . -- +-- -- +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ +-- +-- Revision 1.0 2007/11/05 +-- Clean up code and first release +-- +-- known bugs/todo: +-- Add CHK INSTRUCTION +-- Add MOVEP INSTRUCTION +-- full decode ILLEGAL INSTRUCTIONS +-- Add FDC Output +-- add odd Address test +-- add TRACE +-- Movem with regmask==x0000 + + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity TG68 is + port( + clk : in std_logic; + reset : in std_logic; + clkena_in : in std_logic:='1'; + data_in : in std_logic_vector(15 downto 0); + IPL : in std_logic_vector(2 downto 0):="111"; + dtack : in std_logic; + addr : out std_logic_vector(31 downto 0); + data_out : out std_logic_vector(15 downto 0); + as : out std_logic; + uds : out std_logic; + lds : out std_logic; + rw : out std_logic + ); +end TG68; + +ARCHITECTURE logic OF TG68 IS + + COMPONENT TG68_fast + PORT ( + clk : in std_logic; + reset : in std_logic; + clkena_in : in std_logic; + data_in : in std_logic_vector(15 downto 0); + IPL : in std_logic_vector(2 downto 0); + test_IPL : in std_logic; + address : out std_logic_vector(31 downto 0); + data_write : out std_logic_vector(15 downto 0); + state_out : out std_logic_vector(1 downto 0); + decodeOPC : buffer std_logic; + wr : out std_logic; + UDS, LDS : out std_logic + ); + END COMPONENT; + + + SIGNAL as_s : std_logic; + SIGNAL as_e : std_logic; + SIGNAL uds_s : std_logic; + SIGNAL uds_e : std_logic; + SIGNAL lds_s : std_logic; + SIGNAL lds_e : std_logic; + SIGNAL rw_s : std_logic; + SIGNAL rw_e : std_logic; + SIGNAL waitm : std_logic; + SIGNAL clkena_e : std_logic; + SIGNAL S_state : std_logic_vector(1 downto 0); + SIGNAL decode : std_logic; + SIGNAL wr : std_logic; + SIGNAL uds_in : std_logic; + SIGNAL lds_in : std_logic; + SIGNAL state : std_logic_vector(1 downto 0); + SIGNAL clkena : std_logic; + + +BEGIN + +TG68_fast_inst: TG68_fast + PORT MAP ( + clk => not clk, -- : in std_logic; + reset => reset, -- : in std_logic; + clkena_in => clkena, -- : in std_logic; + data_in => data_in, -- : in std_logic_vector(15 downto 0); + IPL => IPL, -- : in std_logic_vector(2 downto 0); + test_IPL => '0', -- : in std_logic; + address => addr, -- : out std_logic_vector(31 downto 0); + data_write => data_out, -- : out std_logic_vector(15 downto 0); + state_out => state, -- : out std_logic_vector(1 downto 0); + decodeOPC => decode, -- : buffer std_logic; + wr => wr, -- : out std_logic; + UDS => uds_in, -- : out std_logic; + LDS => lds_in -- : out std_logic; + ); + +-- clkena <= '1' WHEN clkena_in='1' AND ((clkena_e OR decode)='1') +-- ELSE '0'; + + + PROCESS (clk) + BEGIN + IF rising_edge(clk) THEN +-- IF clkena_in='1' AND ((clkena_e OR decode)='1') THEN + IF clkena_in='1' AND (clkena_e='1' OR state="01") THEN + clkena <= '1'; + ELSE + clkena <= '0'; + END IF; + END IF; + END PROCESS; + +PROCESS (clk, reset, state, as_s, as_e, rw_s, rw_e, uds_s, uds_e, lds_s, lds_e) + BEGIN + IF state="01" THEN + as <= '1'; + rw <= '1'; + uds <= '1'; + lds <= '1'; + ELSE + as <= as_s AND as_e; + rw <= rw_s AND rw_e; + uds <= uds_s AND uds_e; + lds <= lds_s AND lds_e; + END IF; + IF reset='0' THEN + S_state <= "11"; + as_s <= '1'; + rw_s <= '1'; + uds_s <= '1'; + lds_s <= '1'; + ELSIF rising_edge(clk) THEN + IF clkena_in='1' THEN + as_s <= '1'; + rw_s <= '1'; + uds_s <= '1'; + lds_s <= '1'; + IF state/="01" OR decode='1' THEN + CASE S_state IS + WHEN "00" => as_s <= '0'; + rw_s <= wr; + IF wr='1' THEN + uds_s <= uds_in; + lds_s <= lds_in; + END IF; + S_state <= "01"; + WHEN "01" => as_s <= '0'; + rw_s <= wr; + uds_s <= uds_in; + lds_s <= lds_in; + S_state <= "10"; + WHEN "10" => + rw_s <= wr; + IF waitm='0' THEN + S_state <= "11"; + END IF; + WHEN "11" => + S_state <= "00"; + END CASE; + END IF; + END IF; + END IF; + IF reset='0' THEN + as_e <= '1'; + rw_e <= '1'; + uds_e <= '1'; + lds_e <= '1'; + clkena_e <= '0'; + ELSIF falling_edge(clk) THEN + IF clkena_in='1' THEN + as_e <= '1'; + rw_e <= '1'; + uds_e <= '1'; + lds_e <= '1'; + clkena_e <= '0'; + CASE S_state IS + WHEN "00" => + WHEN "01" => + WHEN "10" => as_e <= '0'; + uds_e <= uds_in; + lds_e <= lds_in; + IF state="01" THEN + clkena_e <= '1'; + waitm <= '0'; + ELSE + clkena_e <= NOT dtack; + waitm <= dtack; + END IF; + WHEN "11" => + END CASE; + END IF; + END IF; + END PROCESS; +END; \ No newline at end of file Index: tg68/tags =================================================================== --- tg68/tags (nonexistent) +++ tg68/tags (revision 10)
tg68/tags Property changes : Added: svn:mergeinfo ## -0,0 +0,0 ##

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