URL
https://opencores.org/ocsvn/uart16750/uart16750/trunk
Subversion Repositories uart16750
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 9 to Rev 10
- ↔ Reverse comparison
Rev 9 → Rev 10
/trunk/rtl/vhdl/slib_mv_filter.vhd
3,7 → 3,7
-- |
-- Author: Sebastian Witt |
-- Date: 27.01.2008 |
-- Version: 1.0 |
-- Version: 1.1 |
-- |
-- This code is free software; you can redistribute it and/or |
-- modify it under the terms of the GNU Lesser General Public |
23,7 → 23,6
|
LIBRARY IEEE; |
USE IEEE.std_logic_1164.all; |
USE IEEE.std_logic_unsigned.all; |
USE IEEE.numeric_std.all; |
|
|
45,7 → 44,7
architecture rtl of slib_mv_filter is |
|
-- Signals |
signal iCounter : std_logic_vector(WIDTH downto 0); -- Sample counter |
signal iCounter : unsigned(WIDTH downto 0); -- Sample counter |
signal iQ : std_logic; -- Internal Q |
|
begin |
60,7 → 59,7
iQ <= '1'; |
else |
if (SAMPLE = '1' and D = '1') then -- Take sample |
iCounter <= iCounter + '1'; |
iCounter <= iCounter + 1; |
end if; |
end if; |
|
/trunk/rtl/vhdl/slib_input_sync.vhd
23,7 → 23,6
|
LIBRARY IEEE; |
USE IEEE.std_logic_1164.all; |
USE IEEE.std_logic_unsigned.all; |
USE IEEE.numeric_std.all; |
|
entity slib_input_sync is |
/trunk/rtl/vhdl/slib_edge_detect.vhd
3,7 → 3,7
-- |
-- Author: Sebastian Witt |
-- Data: 27.01.2008 |
-- Version: 1.0 |
-- Version: 1.1 |
-- |
-- This code is free software; you can redistribute it and/or |
-- modify it under the terms of the GNU Lesser General Public |
23,7 → 23,6
|
LIBRARY IEEE; |
USE IEEE.std_logic_1164.all; |
USE IEEE.std_logic_unsigned.all; |
USE IEEE.numeric_std.all; |
|
entity slib_edge_detect is |
/trunk/rtl/vhdl/slib_clock_div.vhd
3,7 → 3,7
-- |
-- Author: Sebastian Witt |
-- Date: 27.01.2008 |
-- Version: 1.0 |
-- Version: 1.1 |
-- |
-- This code is free software; you can redistribute it and/or |
-- modify it under the terms of the GNU Lesser General Public |
23,7 → 23,6
|
LIBRARY IEEE; |
USE IEEE.std_logic_1164.all; |
USE IEEE.std_logic_unsigned.all; |
USE IEEE.numeric_std.all; |
|
|
/trunk/rtl/vhdl/slib_counter.vhd
3,7 → 3,7
-- |
-- Author: Sebastian Witt |
-- Date: 27.01.2008 |
-- Version: 1.1 |
-- Version: 1.2 |
-- |
-- This code is free software; you can redistribute it and/or |
-- modify it under the terms of the GNU Lesser General Public |
23,7 → 23,6
|
LIBRARY IEEE; |
USE IEEE.std_logic_1164.all; |
USE IEEE.std_logic_unsigned.all; |
USE IEEE.numeric_std.all; |
|
-- Counter |
45,7 → 44,7
end slib_counter; |
|
architecture rtl of slib_counter is |
signal iCounter : std_logic_vector(WIDTH downto 0); -- Counter register |
signal iCounter : unsigned(WIDTH downto 0); -- Counter register |
begin |
-- Counter process |
COUNT_SHIFT: process (RST, CLK) |
56,12 → 55,12
if (CLEAR = '1') then |
iCounter <= (others => '0'); -- Clear counter register |
elsif (LOAD = '1') then -- Load counter register |
iCounter <= '0' & D; |
iCounter <= unsigned('0' & D); |
elsif (ENABLE = '1') then -- Enable counter |
if (DOWN = '0') then -- Count up |
iCounter <= iCounter + '1'; |
iCounter <= iCounter + 1; |
else -- Count down |
iCounter <= iCounter - '1'; |
iCounter <= iCounter - 1; |
end if; |
end if; |
if (iCounter(WIDTH) = '1') then -- Clear overflow |
72,7 → 71,7
end process; |
|
-- Output ports |
Q <= iCounter(WIDTH-1 downto 0); |
Q <= std_logic_vector(iCounter(WIDTH-1 downto 0)); |
OVERFLOW <= iCounter(WIDTH); |
end rtl; |
|
/trunk/rtl/vhdl/slib_fifo.vhd
23,7 → 23,6
|
LIBRARY IEEE; |
USE IEEE.std_logic_1164.all; |
USE IEEE.std_logic_unsigned.all; |
USE IEEE.numeric_std.all; |
|
|
50,9 → 49,9
-- Signals |
signal iEMPTY : std_logic; -- Internal EMPTY |
signal iFULL : std_logic; -- Internal FULL |
signal iWRAddr : std_logic_vector(SIZE_E downto 0); -- FIFO write address |
signal iRDAddr : std_logic_vector(SIZE_E downto 0); -- FIFO read address |
signal iUSAGE : std_logic_vector(SIZE_E-1 downto 0); -- FIFO usage |
signal iWRAddr : unsigned(SIZE_E downto 0); -- FIFO write address |
signal iRDAddr : unsigned(SIZE_E downto 0); -- FIFO read address |
signal iUSAGE : unsigned(SIZE_E-1 downto 0); -- FIFO usage |
-- FIFO memory |
type FIFO_Mem_Type is array (2**SIZE_E-1 downto 0) of std_logic_vector(WIDTH-1 downto 0); |
signal iFIFOMem : FIFO_Mem_Type := (others => (others => '0')); |
71,11 → 70,11
iEMPTY <= '1'; |
elsif (CLK'event and CLK='1') then |
if (WRITE = '1' and iFULL = '0') then -- Write to FIFO |
iWRAddr <= iWRAddr + '1'; |
iWRAddr <= iWRAddr + 1; |
end if; |
|
if (READ = '1' and iEMPTY = '0') then -- Read from FIFO |
iRDAddr <= iRDAddr + '1'; |
iRDAddr <= iRDAddr + 1; |
end if; |
|
if (CLEAR = '1') then -- Reset FIFO |
98,9 → 97,9
--iFIFOMem(2**SIZE_E-1 downto 0) <= (others => (others => '0')); |
elsif (CLK'event and CLK = '1') then |
if (WRITE = '1' and iFULL = '0') then |
iFIFOMem(CONV_INTEGER(iWRAddr(SIZE_E-1 downto 0))) <= D; |
iFIFOMem(to_integer(iWRAddr(SIZE_E-1 downto 0))) <= D; |
end if; |
Q <= iFIFOMem(CONV_INTEGER(iRDAddr(SIZE_E-1 downto 0))); |
Q <= iFIFOMem(to_integer(iRDAddr(SIZE_E-1 downto 0))); |
end if; |
end process; |
|
114,10 → 113,10
iUSAGE <= (others => '0'); |
else |
if (READ = '0' and WRITE = '1' and iFULL = '0') then |
iUSAGE <= iUSAGE + '1'; |
iUSAGE <= iUSAGE + 1; |
end if; |
if (WRITE = '0' and READ = '1' and iEMPTY = '0') then |
iUSAGE <= iUSAGE - '1'; |
iUSAGE <= iUSAGE - 1; |
end if; |
end if; |
end if; |
126,7 → 125,7
-- Output signals |
EMPTY <= iEMPTY; |
FULL <= iFULL; |
USAGE <= iUSAGE; |
USAGE <= std_logic_vector(iUSAGE); |
|
end rtl; |
|
/trunk/rtl/vhdl/slib_input_filter.vhd
23,7 → 23,6
|
LIBRARY IEEE; |
USE IEEE.std_logic_1164.all; |
USE IEEE.std_logic_unsigned.all; |
USE IEEE.numeric_std.all; |
|
entity slib_input_filter is |