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URL https://opencores.org/ocsvn/ultimate_crc/ultimate_crc/trunk

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/trunk/rtl/vhdl/ucrc_ser.vhd
44,6 → 44,9
-- CVS Revision History
--
-- $Log: not supported by cvs2svn $
-- Revision 1.2 2005/05/09 19:26:58 gedra
-- Moved match signal into clock enable
--
-- Revision 1.1 2005/05/07 12:47:47 gedra
-- Serial implementation.
--
53,113 → 56,113
library ieee;
use ieee.std_logic_1164.all;
 
entity ucrc_ser is
generic (
POLYNOMIAL: std_logic_vector;
INIT_VALUE: std_logic_vector;
SYNC_RESET: integer range 0 to 1:=0); -- use synchronous reset
port (
clk_i: in std_logic; -- clock
rst_i: in std_logic; -- init CRC
clken_i: in std_logic; -- clock enable
data_i: in std_logic; -- data input
flush_i: in std_logic; -- flush crc
match_o: out std_logic; -- CRC match flag
crc_o: out std_logic_vector(POLYNOMIAL'length - 1 downto 0)); -- CRC output
entity ucrc_ser is
generic (
POLYNOMIAL : std_logic_vector;
INIT_VALUE : std_logic_vector;
SYNC_RESET : integer range 0 to 1 := 0); -- use synchronous reset
port (
clk_i : in std_logic; -- clock
rst_i : in std_logic; -- init CRC
clken_i : in std_logic; -- clock enable
data_i : in std_logic; -- data input
flush_i : in std_logic; -- flush crc
match_o : out std_logic; -- CRC match flag
crc_o : out std_logic_vector(POLYNOMIAL'length - 1 downto 0)); -- CRC output
end ucrc_ser;
 
architecture rtl of ucrc_ser is
 
constant msb : integer := POLYNOMIAL'length - 1;
constant init_msb : integer := INIT_VALUE'length - 1;
constant p : std_logic_vector(msb downto 0) := POLYNOMIAL;
signal din, crc_msb: std_logic_vector(msb downto 1);
signal crc, zero, fb: std_logic_vector(msb downto 0);
signal arst, srst: std_logic;
constant msb : integer := POLYNOMIAL'length - 1;
constant init_msb : integer := INIT_VALUE'length - 1;
constant p : std_logic_vector(msb downto 0) := POLYNOMIAL;
signal din, crc_msb : std_logic_vector(msb downto 1);
signal crc, zero, fb : std_logic_vector(msb downto 0);
signal arst, srst : std_logic;
begin
 
-- Parameter checking: Invalid generics will abort simulation/synthesis
PCHK: if msb /= init_msb generate
process
begin
report "POLYNOMIAL and INIT_VALUE vectors must be equal length!"
severity failure;
wait;
end process;
end generate PCHK;
PCHK2: if (msb < 3) or (msb > 31) generate
process
begin
report "POLYNOMIAL must be of order 4 to 32!"
severity failure;
wait;
end process;
end generate PCHK2;
PCHK : if msb /= init_msb generate
process
begin
report "POLYNOMIAL and INIT_VALUE vectors must be equal length!"
severity failure;
wait;
end process;
end generate PCHK;
 
PCHK3: if p(0) /= '1' generate -- LSB must be 1
process
begin
report "POLYNOMIAL must have lsb set to 1!"
severity failure;
wait;
end process;
end generate PCHK3;
zero <= (others => '0');
crc_o <= crc;
PCHK2 : if (msb < 3) or (msb > 31) generate
process
begin
report "POLYNOMIAL must be of order 4 to 32!"
severity failure;
wait;
end process;
end generate PCHK2;
 
PCHK3 : if p(0) /= '1' generate -- LSB must be 1
process
begin
report "POLYNOMIAL must have lsb set to 1!"
severity failure;
wait;
end process;
end generate PCHK3;
 
zero <= (others => '0');
crc_o <= crc;
 
-- Create vectors of data input and MSB of CRC
DI: for i in 1 to msb generate
din(i) <= data_i;
crc_msb(i) <= crc(msb);
end generate DI;
DI : for i in 1 to msb generate
din(i) <= data_i;
crc_msb(i) <= crc(msb);
end generate DI;
 
-- Feedback signals
fb(0) <= data_i xor crc(msb);
fb(msb downto 1) <= crc(msb-1 downto 0) xor ((din xor crc_msb) and p(msb downto 1));
fb(0) <= data_i xor crc(msb);
fb(msb downto 1) <= crc(msb-1 downto 0) xor ((din xor crc_msb) and p(msb downto 1));
 
-- Reset signal
SR: if SYNC_RESET = 1 generate
srst <= rst_i;
arst <= '0';
end generate SR;
AR: if SYNC_RESET = 0 generate
srst <= '0';
arst <= rst_i;
end generate AR;
SR : if SYNC_RESET = 1 generate
srst <= rst_i;
arst <= '0';
end generate SR;
AR : if SYNC_RESET = 0 generate
srst <= '0';
arst <= rst_i;
end generate AR;
 
-- CRC process
CRCP: process (clk_i, arst)
begin
if arst = '1' then -- async. reset
crc <= INIT_VALUE;
match_o <= '0';
elsif rising_edge(clk_i) then
if srst = '1' then -- sync. reset
crc <= INIT_VALUE;
match_o <= '0';
else
if clken_i = '1' then
-- CRC generation
if flush_i = '1' then
crc(0) <= '0';
crc(msb downto 1) <= crc(msb - 1 downto 0);
else
crc <= fb;
end if;
-- CRC match checker (if data plus CRC is clocked in without errors,
-- the CRC register ends up with all zeroes)
if fb = zero then
match_o <= '1';
else
CRCP : process (clk_i, arst)
begin
if arst = '1' then -- async. reset
crc <= INIT_VALUE;
match_o <= '0';
elsif rising_edge(clk_i) then
if srst = '1' then -- sync. reset
crc <= INIT_VALUE;
match_o <= '0';
end if;
end if;
else
if clken_i = '1' then
-- CRC generation
if flush_i = '1' then
crc(0) <= '0';
crc(msb downto 1) <= crc(msb - 1 downto 0);
else
crc <= fb;
end if;
-- CRC match checker (if data plus CRC is clocked in without errors,
-- the CRC register ends up with all zeroes)
if fb = zero then
match_o <= '1';
else
match_o <= '0';
end if;
end if;
end if;
end if;
end if;
end process;
end process;
end rtl;
 
/trunk/rtl/vhdl/ucrc_pkg.vhd
44,8 → 44,11
-- CVS Revision History
--
-- $Log: not supported by cvs2svn $
-- Revision 1.1 2005/05/09 15:56:14 gedra
-- Component declarations
--
--
--
 
library ieee;
use ieee.std_logic_1164.all;
52,34 → 55,34
 
package ucrc_pkg is
 
component ucrc_ser
generic (
POLYNOMIAL: std_logic_vector; -- 4 to 32 bits
INIT_VALUE: std_logic_vector;
SYNC_RESET: integer range 0 to 1); -- use synchronous reset
port (
clk_i: in std_logic; -- clock
rst_i: in std_logic; -- init CRC
clken_i: in std_logic; -- clock enable
data_i: in std_logic; -- data input
flush_i: in std_logic; -- flush crc
match_o: out std_logic; -- CRC match flag
crc_o: out std_logic_vector(POLYNOMIAL'length - 1 downto 0)); -- CRC output
end component;
component ucrc_ser
generic (
POLYNOMIAL : std_logic_vector; -- 4 to 32 bits
INIT_VALUE : std_logic_vector;
SYNC_RESET : integer range 0 to 1); -- use synchronous reset
port (
clk_i : in std_logic; -- clock
rst_i : in std_logic; -- init CRC
clken_i : in std_logic; -- clock enable
data_i : in std_logic; -- data input
flush_i : in std_logic; -- flush crc
match_o : out std_logic; -- CRC match flag
crc_o : out std_logic_vector(POLYNOMIAL'length - 1 downto 0)); -- CRC output
end component;
 
component ucrc_par
generic (
POLYNOMIAL: std_logic_vector;
INIT_VALUE: std_logic_vector;
DATA_WIDTH: integer range 2 to 256;
SYNC_RESET: integer range 0 to 1); -- use synchronous reset
port (
clk_i: in std_logic; -- clock
rst_i: in std_logic; -- init CRC
clken_i: in std_logic; -- clock enable
data_i: in std_logic_vector(DATA_WIDTH - 1 downto 0); -- data input
match_o: out std_logic; -- CRC match flag
crc_o: out std_logic_vector(POLYNOMIAL'length - 1 downto 0)); -- CRC output
end component;
component ucrc_par
generic (
POLYNOMIAL : std_logic_vector;
INIT_VALUE : std_logic_vector;
DATA_WIDTH : integer range 2 to 256;
SYNC_RESET : integer range 0 to 1); -- use synchronous reset
port (
clk_i : in std_logic; -- clock
rst_i : in std_logic; -- init CRC
clken_i : in std_logic; -- clock enable
data_i : in std_logic_vector(DATA_WIDTH - 1 downto 0); -- data input
match_o : out std_logic; -- CRC match flag
crc_o : out std_logic_vector(POLYNOMIAL'length - 1 downto 0)); -- CRC output
end component;
 
end ucrc_pkg;
/trunk/rtl/vhdl/ucrc_par.vhd
44,130 → 44,133
-- CVS Revision History
--
-- $Log: not supported by cvs2svn $
-- Revision 1.1 2005/05/09 15:58:38 gedra
-- Parallel implementation
--
--
--
 
library ieee;
use ieee.std_logic_1164.all;
 
entity ucrc_par is
generic (
POLYNOMIAL: std_logic_vector;
INIT_VALUE: std_logic_vector;
DATA_WIDTH: integer range 2 to 256;
SYNC_RESET: integer range 0 to 1); -- use sync./async reset
port (
clk_i: in std_logic; -- clock
rst_i: in std_logic; -- init CRC
clken_i: in std_logic; -- clock enable
data_i: in std_logic_vector(DATA_WIDTH - 1 downto 0); -- data input
match_o: out std_logic; -- CRC match flag
crc_o: out std_logic_vector(POLYNOMIAL'length - 1 downto 0)); -- CRC output
entity ucrc_par is
generic (
POLYNOMIAL : std_logic_vector;
INIT_VALUE : std_logic_vector;
DATA_WIDTH : integer range 2 to 256;
SYNC_RESET : integer range 0 to 1); -- use sync./async reset
port (
clk_i : in std_logic; -- clock
rst_i : in std_logic; -- init CRC
clken_i : in std_logic; -- clock enable
data_i : in std_logic_vector(DATA_WIDTH - 1 downto 0); -- data input
match_o : out std_logic; -- CRC match flag
crc_o : out std_logic_vector(POLYNOMIAL'length - 1 downto 0)); -- CRC output
end ucrc_par;
 
architecture rtl of ucrc_par is
 
constant msb : integer := POLYNOMIAL'length - 1;
constant init_msb : integer := INIT_VALUE'length - 1;
constant p : std_logic_vector(msb downto 0) := POLYNOMIAL;
constant dw : integer := DATA_WIDTH;
constant pw : integer := POLYNOMIAL'length;
type fb_array is array (dw downto 1) of std_logic_vector(msb downto 0);
type dmsb_array is array (dw downto 1) of std_logic_vector(msb downto 1);
signal crca: fb_array;
signal da, ma : dmsb_array;
signal crc, zero: std_logic_vector(msb downto 0);
signal arst, srst: std_logic;
constant msb : integer := POLYNOMIAL'length - 1;
constant init_msb : integer := INIT_VALUE'length - 1;
constant p : std_logic_vector(msb downto 0) := POLYNOMIAL;
constant dw : integer := DATA_WIDTH;
constant pw : integer := POLYNOMIAL'length;
type fb_array is array (dw downto 1) of std_logic_vector(msb downto 0);
type dmsb_array is array (dw downto 1) of std_logic_vector(msb downto 1);
signal crca : fb_array;
signal da, ma : dmsb_array;
signal crc, zero : std_logic_vector(msb downto 0);
signal arst, srst : std_logic;
begin
 
-- Parameter checking: Invalid generics will abort simulation/synthesis
PCHK1: if msb /= init_msb generate
process
begin
report "POLYNOMIAL and INIT_VALUE vectors must be equal length!"
severity failure;
wait;
end process;
end generate PCHK1;
PCHK2: if (msb < 3) or (msb > 31) generate
process
begin
report "POLYNOMIAL must be of order 4 to 32!"
severity failure;
wait;
end process;
end generate PCHK2;
PCHK1 : if msb /= init_msb generate
process
begin
report "POLYNOMIAL and INIT_VALUE vectors must be equal length!"
severity failure;
wait;
end process;
end generate PCHK1;
 
PCHK3: if p(0) /= '1' generate -- LSB must be 1
process
begin
report "POLYNOMIAL must have lsb set to 1!"
severity failure;
wait;
end process;
end generate PCHK3;
PCHK2 : if (msb < 3) or (msb > 31) generate
process
begin
report "POLYNOMIAL must be of order 4 to 32!"
severity failure;
wait;
end process;
end generate PCHK2;
 
PCHK3 : if p(0) /= '1' generate -- LSB must be 1
process
begin
report "POLYNOMIAL must have lsb set to 1!"
severity failure;
wait;
end process;
end generate PCHK3;
 
-- Generate vector of each data bit
CA: for i in 1 to dw generate -- data bits
DAT: for j in 1 to msb generate
da(i)(j) <= data_i(i - 1);
end generate DAT;
end generate CA;
CA : for i in 1 to dw generate -- data bits
DAT : for j in 1 to msb generate
da(i)(j) <= data_i(i - 1);
end generate DAT;
end generate CA;
 
-- Generate vector of each CRC MSB
MS0: for i in 1 to msb generate
ma(1)(i) <= crc(msb);
end generate MS0;
MSP: for i in 2 to dw generate
MSU: for j in 1 to msb generate
ma(i)(j) <= crca(i - 1)(msb);
end generate MSU;
end generate MSP;
MS0 : for i in 1 to msb generate
ma(1)(i) <= crc(msb);
end generate MS0;
MSP : for i in 2 to dw generate
MSU : for j in 1 to msb generate
ma(i)(j) <= crca(i - 1)(msb);
end generate MSU;
end generate MSP;
 
-- Generate feedback matrix
crca(1)(0) <= da(1)(1) xor crc(msb);
crca(1)(msb downto 1) <= crc(msb - 1 downto 0) xor ((da(1) xor ma(1)) and p(msb downto 1));
FB: for i in 2 to dw generate
crca(i)(0) <= da(i)(1) xor crca(i - 1)(msb);
crca(i)(msb downto 1) <= crca(i - 1)(msb - 1 downto 0) xor
((da(i) xor ma(i)) and p(msb downto 1));
end generate FB;
crca(1)(0) <= da(1)(1) xor crc(msb);
crca(1)(msb downto 1) <= crc(msb - 1 downto 0) xor ((da(1) xor ma(1)) and p(msb downto 1));
FB : for i in 2 to dw generate
crca(i)(0) <= da(i)(1) xor crca(i - 1)(msb);
crca(i)(msb downto 1) <= crca(i - 1)(msb - 1 downto 0) xor
((da(i) xor ma(i)) and p(msb downto 1));
end generate FB;
 
-- Reset signal
SR: if SYNC_RESET = 1 generate
srst <= rst_i;
arst <= '0';
end generate SR;
AR: if SYNC_RESET = 0 generate
srst <= '0';
arst <= rst_i;
end generate AR;
SR : if SYNC_RESET = 1 generate
srst <= rst_i;
arst <= '0';
end generate SR;
AR : if SYNC_RESET = 0 generate
srst <= '0';
arst <= rst_i;
end generate AR;
 
-- CRC process
crc_o <= crc;
zero <= (others => '0');
CRCP: process (clk_i, arst)
begin
if arst = '1' then -- async. reset
crc <= INIT_VALUE;
match_o <= '0';
elsif rising_edge(clk_i) then
if srst = '1' then -- sync. reset
crc <= INIT_VALUE;
match_o <= '0';
elsif clken_i = '1' then
crc <= crca(dw);
if crca(dw) = zero then
match_o <= '1';
else
match_o <= '0';
end if;
crc_o <= crc;
zero <= (others => '0');
 
CRCP : process (clk_i, arst)
begin
if arst = '1' then -- async. reset
crc <= INIT_VALUE;
match_o <= '0';
elsif rising_edge(clk_i) then
if srst = '1' then -- sync. reset
crc <= INIT_VALUE;
match_o <= '0';
elsif clken_i = '1' then
crc <= crca(dw);
if crca(dw) = zero then
match_o <= '1';
else
match_o <= '0';
end if;
end if;
end if;
end if;
end process;
end process;
end rtl;
 

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