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https://opencores.org/ocsvn/wb_dma/wb_dma/trunk
Subversion Repositories wb_dma
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- ↔ Reverse comparison
Rev 9 → Rev 10
/trunk/rtl/verilog/wb_dma_top.v
37,10 → 37,10
|
// CVS Log |
// |
// $Id: wb_dma_top.v,v 1.3 2001-09-07 15:34:38 rudi Exp $ |
// $Id: wb_dma_top.v,v 1.4 2001-10-19 04:35:04 rudi Exp $ |
// |
// $Date: 2001-09-07 15:34:38 $ |
// $Revision: 1.3 $ |
// $Date: 2001-10-19 04:35:04 $ |
// $Revision: 1.4 $ |
// $Author: rudi $ |
// $Locker: $ |
// $State: Exp $ |
47,6 → 47,10
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.3 2001/09/07 15:34:38 rudi |
// |
// Changed reset to active high. |
// |
// Revision 1.2 2001/08/15 05:40:30 rudi |
// |
// - Changed IO names to be more clear. |
98,6 → 102,52
inta_o, intb_o |
); |
|
//////////////////////////////////////////////////////////////////// |
// |
// Module Parameters |
// |
|
// chXX_conf = { CBUF, ED, ARS, EN } |
parameter rf_addr = 0; |
parameter [1:0] pri_sel = 2'h0; |
parameter ch_count = 1; |
parameter [3:0] ch0_conf = 4'h1; |
parameter [3:0] ch1_conf = 4'h0; |
parameter [3:0] ch2_conf = 4'h0; |
parameter [3:0] ch3_conf = 4'h0; |
parameter [3:0] ch4_conf = 4'h0; |
parameter [3:0] ch5_conf = 4'h0; |
parameter [3:0] ch6_conf = 4'h0; |
parameter [3:0] ch7_conf = 4'h0; |
parameter [3:0] ch8_conf = 4'h0; |
parameter [3:0] ch9_conf = 4'h0; |
parameter [3:0] ch10_conf = 4'h0; |
parameter [3:0] ch11_conf = 4'h0; |
parameter [3:0] ch12_conf = 4'h0; |
parameter [3:0] ch13_conf = 4'h0; |
parameter [3:0] ch14_conf = 4'h0; |
parameter [3:0] ch15_conf = 4'h0; |
parameter [3:0] ch16_conf = 4'h0; |
parameter [3:0] ch17_conf = 4'h0; |
parameter [3:0] ch18_conf = 4'h0; |
parameter [3:0] ch19_conf = 4'h0; |
parameter [3:0] ch20_conf = 4'h0; |
parameter [3:0] ch21_conf = 4'h0; |
parameter [3:0] ch22_conf = 4'h0; |
parameter [3:0] ch23_conf = 4'h0; |
parameter [3:0] ch24_conf = 4'h0; |
parameter [3:0] ch25_conf = 4'h0; |
parameter [3:0] ch26_conf = 4'h0; |
parameter [3:0] ch27_conf = 4'h0; |
parameter [3:0] ch28_conf = 4'h0; |
parameter [3:0] ch29_conf = 4'h0; |
parameter [3:0] ch30_conf = 4'h0; |
|
//////////////////////////////////////////////////////////////////// |
// |
// Module IOs |
// |
|
input clk_i, rst_i; |
|
// -------------------------------------- |
156,10 → 206,10
|
// -------------------------------------- |
// Misc Signals |
input [`WDMA_CH_COUNT-1:0] dma_req_i; |
input [`WDMA_CH_COUNT-1:0] dma_nd_i; |
output [`WDMA_CH_COUNT-1:0] dma_ack_o; |
input [`WDMA_CH_COUNT-1:0] dma_rest_i; |
input [ch_count-1:0] dma_req_i; |
input [ch_count-1:0] dma_nd_i; |
output [ch_count-1:0] dma_ack_o; |
input [ch_count-1:0] dma_rest_i; |
output inta_o; |
output intb_o; |
|
281,11 → 331,13
// Misc Logic |
// |
|
assign dma_req[`WDMA_CH_COUNT-1:0] = dma_req_i; |
assign dma_nd[`WDMA_CH_COUNT-1:0] = dma_nd_i; |
assign dma_rest[`WDMA_CH_COUNT-1:0] = dma_rest_i; |
assign dma_ack_o = dma_ack[`WDMA_CH_COUNT-1:0]; |
wire [31:0] tmp_gnd = 32'h0; |
|
assign dma_req[ch_count-1:0] = dma_req_i; |
assign dma_nd[ch_count-1:0] = dma_nd_i; |
assign dma_rest[ch_count-1:0] = dma_rest_i; |
assign dma_ack_o = {tmp_gnd[31-ch_count:0], dma_ack[ch_count-1:0]}; |
|
// -------------------------------------------------- |
// This should go in to a separate Pass Through Block |
assign pt1_sel_i = pt0_sel_o; |
301,10 → 353,39
// Modules |
// |
|
|
// DMA Register File |
|
wb_dma_rf u0( |
wb_dma_rf #( ch0_conf, |
ch1_conf, |
ch2_conf, |
ch3_conf, |
ch4_conf, |
ch5_conf, |
ch6_conf, |
ch7_conf, |
ch8_conf, |
ch9_conf, |
ch10_conf, |
ch11_conf, |
ch12_conf, |
ch13_conf, |
ch14_conf, |
ch15_conf, |
ch16_conf, |
ch17_conf, |
ch18_conf, |
ch19_conf, |
ch20_conf, |
ch21_conf, |
ch22_conf, |
ch23_conf, |
ch24_conf, |
ch25_conf, |
ch26_conf, |
ch27_conf, |
ch28_conf, |
ch29_conf, |
ch30_conf) |
u0( |
.clk( clk_i ), |
.rst( ~rst_i ), |
.wb_rf_adr( slv0_adr[9:2] ), |
585,7 → 666,39
); |
|
// Channel Select |
wb_dma_ch_sel u1( |
wb_dma_ch_sel #(pri_sel, |
ch0_conf, |
ch1_conf, |
ch2_conf, |
ch3_conf, |
ch4_conf, |
ch5_conf, |
ch6_conf, |
ch7_conf, |
ch8_conf, |
ch9_conf, |
ch10_conf, |
ch11_conf, |
ch12_conf, |
ch13_conf, |
ch14_conf, |
ch15_conf, |
ch16_conf, |
ch17_conf, |
ch18_conf, |
ch19_conf, |
ch20_conf, |
ch21_conf, |
ch22_conf, |
ch23_conf, |
ch24_conf, |
ch25_conf, |
ch26_conf, |
ch27_conf, |
ch28_conf, |
ch29_conf, |
ch30_conf) |
u1( |
.clk( clk_i ), |
.rst( ~rst_i ), |
.req_i( dma_req ), |
911,7 → 1024,7
); |
|
// Wishbone Interface 0 |
wb_dma_wb_if u3( |
wb_dma_wb_if #(rf_addr) u3( |
.clk( clk_i ), |
.rst( ~rst_i ), |
.wbs_data_i( wb0s_data_i ), |
956,7 → 1069,7
); |
|
// Wishbone Interface 1 |
wb_dma_wb_if u4( |
wb_dma_wb_if #(rf_addr) u4( |
.clk( clk_i ), |
.rst( ~rst_i ), |
.wbs_data_i( wb1s_data_i ), |
/trunk/rtl/verilog/wb_dma_wb_if.v
37,10 → 37,10
|
// CVS Log |
// |
// $Id: wb_dma_wb_if.v,v 1.1 2001-07-29 08:57:02 rudi Exp $ |
// $Id: wb_dma_wb_if.v,v 1.2 2001-10-19 04:35:04 rudi Exp $ |
// |
// $Date: 2001-07-29 08:57:02 $ |
// $Revision: 1.1 $ |
// $Date: 2001-10-19 04:35:04 $ |
// $Revision: 1.2 $ |
// $Author: rudi $ |
// $Locker: $ |
// $State: Exp $ |
47,6 → 47,12
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.1 2001/07/29 08:57:02 rudi |
// |
// |
// 1) Changed Directory Structure |
// 2) Added restart signal (REST) |
// |
// Revision 1.2 2001/06/05 10:22:37 rudi |
// |
// |
82,6 → 88,8
|
); |
|
parameter rf_addr = 0; |
|
input clk, rst; |
|
// -------------------------------------- |
179,7 → 187,7
); |
|
|
wb_dma_wb_slv u1( |
wb_dma_wb_slv #(rf_addr) u1( |
.clk( clk ), |
.rst( rst ), |
.wb_data_i( wbm_data_i ), |
/trunk/rtl/verilog/wb_dma_rf.v
37,10 → 37,10
|
// CVS Log |
// |
// $Id: wb_dma_rf.v,v 1.2 2001-08-15 05:40:30 rudi Exp $ |
// $Id: wb_dma_rf.v,v 1.3 2001-10-19 04:35:04 rudi Exp $ |
// |
// $Date: 2001-08-15 05:40:30 $ |
// $Revision: 1.2 $ |
// $Date: 2001-10-19 04:35:04 $ |
// $Revision: 1.3 $ |
// $Author: rudi $ |
// $Locker: $ |
// $State: Exp $ |
47,6 → 47,12
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.2 2001/08/15 05:40:30 rudi |
// |
// - Changed IO names to be more clear. |
// - Uniquifyed define names to be core specific. |
// - Added Section 3.10, describing DMA restart. |
// |
// Revision 1.1 2001/07/29 08:57:02 rudi |
// |
// |
132,6 → 138,49
ptr_set |
); |
|
//////////////////////////////////////////////////////////////////// |
// |
// Module Parameters |
// |
|
// chXX_conf = { CBUF, ED, ARS, EN } |
parameter [3:0] ch0_conf = 4'h1; |
parameter [3:0] ch1_conf = 4'h0; |
parameter [3:0] ch2_conf = 4'h0; |
parameter [3:0] ch3_conf = 4'h0; |
parameter [3:0] ch4_conf = 4'h0; |
parameter [3:0] ch5_conf = 4'h0; |
parameter [3:0] ch6_conf = 4'h0; |
parameter [3:0] ch7_conf = 4'h0; |
parameter [3:0] ch8_conf = 4'h0; |
parameter [3:0] ch9_conf = 4'h0; |
parameter [3:0] ch10_conf = 4'h0; |
parameter [3:0] ch11_conf = 4'h0; |
parameter [3:0] ch12_conf = 4'h0; |
parameter [3:0] ch13_conf = 4'h0; |
parameter [3:0] ch14_conf = 4'h0; |
parameter [3:0] ch15_conf = 4'h0; |
parameter [3:0] ch16_conf = 4'h0; |
parameter [3:0] ch17_conf = 4'h0; |
parameter [3:0] ch18_conf = 4'h0; |
parameter [3:0] ch19_conf = 4'h0; |
parameter [3:0] ch20_conf = 4'h0; |
parameter [3:0] ch21_conf = 4'h0; |
parameter [3:0] ch22_conf = 4'h0; |
parameter [3:0] ch23_conf = 4'h0; |
parameter [3:0] ch24_conf = 4'h0; |
parameter [3:0] ch25_conf = 4'h0; |
parameter [3:0] ch26_conf = 4'h0; |
parameter [3:0] ch27_conf = 4'h0; |
parameter [3:0] ch28_conf = 4'h0; |
parameter [3:0] ch29_conf = 4'h0; |
parameter [3:0] ch30_conf = 4'h0; |
|
//////////////////////////////////////////////////////////////////// |
// |
// Module IOs |
// |
|
input clk, rst; |
|
// WISHBONE Access |
296,346 → 345,276
8'he: wb_rf_dout <= #1 pointer0; |
8'hf: wb_rf_dout <= #1 sw_pointer0; |
|
`ifdef WDMA_HAVE_CH1 |
8'h10: wb_rf_dout <= #1 ch1_csr; |
8'h11: wb_rf_dout <= #1 ch1_txsz; |
8'h12: wb_rf_dout <= #1 ch1_adr0; |
8'h13: wb_rf_dout <= #1 ch1_am0; |
8'h14: wb_rf_dout <= #1 ch1_adr1; |
8'h15: wb_rf_dout <= #1 ch1_am1; |
8'h16: wb_rf_dout <= #1 pointer1; |
8'h17: wb_rf_dout <= #1 sw_pointer1; |
`endif |
8'h10: wb_rf_dout <= #1 ch1_conf[0] ? ch1_csr : 32'h0; |
8'h11: wb_rf_dout <= #1 ch1_conf[0] ? ch1_txsz : 32'h0; |
8'h12: wb_rf_dout <= #1 ch1_conf[0] ? ch1_adr0 : 32'h0; |
8'h13: wb_rf_dout <= #1 ch1_conf[0] ? ch1_am0 : 32'h0; |
8'h14: wb_rf_dout <= #1 ch1_conf[0] ? ch1_adr1 : 32'h0; |
8'h15: wb_rf_dout <= #1 ch1_conf[0] ? ch1_am1 : 32'h0; |
8'h16: wb_rf_dout <= #1 ch1_conf[0] ? pointer1 : 32'h0; |
8'h17: wb_rf_dout <= #1 ch1_conf[0] ? sw_pointer1 : 32'h0; |
|
`ifdef WDMA_HAVE_CH2 |
8'h18: wb_rf_dout <= #1 ch2_csr; |
8'h19: wb_rf_dout <= #1 ch2_txsz; |
8'h1a: wb_rf_dout <= #1 ch2_adr0; |
8'h1b: wb_rf_dout <= #1 ch2_am0; |
8'h1c: wb_rf_dout <= #1 ch2_adr1; |
8'h1d: wb_rf_dout <= #1 ch2_am1; |
8'h1e: wb_rf_dout <= #1 pointer2; |
8'h1f: wb_rf_dout <= #1 sw_pointer2; |
`endif |
8'h18: wb_rf_dout <= #1 ch2_conf[0] ? ch2_csr : 32'h0; |
8'h19: wb_rf_dout <= #1 ch2_conf[0] ? ch2_txsz : 32'h0; |
8'h1a: wb_rf_dout <= #1 ch2_conf[0] ? ch2_adr0 : 32'h0; |
8'h1b: wb_rf_dout <= #1 ch2_conf[0] ? ch2_am0 : 32'h0; |
8'h1c: wb_rf_dout <= #1 ch2_conf[0] ? ch2_adr1 : 32'h0; |
8'h1d: wb_rf_dout <= #1 ch2_conf[0] ? ch2_am1 : 32'h0; |
8'h1e: wb_rf_dout <= #1 ch2_conf[0] ? pointer2 : 32'h0; |
8'h1f: wb_rf_dout <= #1 ch2_conf[0] ? sw_pointer2 : 32'h0; |
|
`ifdef WDMA_HAVE_CH3 |
8'h20: wb_rf_dout <= #1 ch3_csr; |
8'h21: wb_rf_dout <= #1 ch3_txsz; |
8'h22: wb_rf_dout <= #1 ch3_adr0; |
8'h23: wb_rf_dout <= #1 ch3_am0; |
8'h24: wb_rf_dout <= #1 ch3_adr1; |
8'h25: wb_rf_dout <= #1 ch3_am1; |
8'h26: wb_rf_dout <= #1 pointer3; |
8'h27: wb_rf_dout <= #1 sw_pointer3; |
`endif |
8'h20: wb_rf_dout <= #1 ch3_conf[0] ? ch3_csr : 32'h0; |
8'h21: wb_rf_dout <= #1 ch3_conf[0] ? ch3_txsz : 32'h0; |
8'h22: wb_rf_dout <= #1 ch3_conf[0] ? ch3_adr0 : 32'h0; |
8'h23: wb_rf_dout <= #1 ch3_conf[0] ? ch3_am0 : 32'h0; |
8'h24: wb_rf_dout <= #1 ch3_conf[0] ? ch3_adr1 : 32'h0; |
8'h25: wb_rf_dout <= #1 ch3_conf[0] ? ch3_am1 : 32'h0; |
8'h26: wb_rf_dout <= #1 ch3_conf[0] ? pointer3 : 32'h0; |
8'h27: wb_rf_dout <= #1 ch3_conf[0] ? sw_pointer3 : 32'h0; |
|
`ifdef WDMA_HAVE_CH4 |
8'h28: wb_rf_dout <= #1 ch4_csr; |
8'h29: wb_rf_dout <= #1 ch4_txsz; |
8'h2a: wb_rf_dout <= #1 ch4_adr0; |
8'h2b: wb_rf_dout <= #1 ch4_am0; |
8'h2c: wb_rf_dout <= #1 ch4_adr1; |
8'h2d: wb_rf_dout <= #1 ch4_am1; |
8'h2e: wb_rf_dout <= #1 pointer4; |
8'h2f: wb_rf_dout <= #1 sw_pointer4; |
`endif |
8'h28: wb_rf_dout <= #1 ch4_conf[0] ? ch4_csr : 32'h0; |
8'h29: wb_rf_dout <= #1 ch4_conf[0] ? ch4_txsz : 32'h0; |
8'h2a: wb_rf_dout <= #1 ch4_conf[0] ? ch4_adr0 : 32'h0; |
8'h2b: wb_rf_dout <= #1 ch4_conf[0] ? ch4_am0 : 32'h0; |
8'h2c: wb_rf_dout <= #1 ch4_conf[0] ? ch4_adr1 : 32'h0; |
8'h2d: wb_rf_dout <= #1 ch4_conf[0] ? ch4_am1 : 32'h0; |
8'h2e: wb_rf_dout <= #1 ch4_conf[0] ? pointer4 : 32'h0; |
8'h2f: wb_rf_dout <= #1 ch4_conf[0] ? sw_pointer4 : 32'h0; |
|
`ifdef WDMA_HAVE_CH5 |
8'h30: wb_rf_dout <= #1 ch5_csr; |
8'h31: wb_rf_dout <= #1 ch5_txsz; |
8'h32: wb_rf_dout <= #1 ch5_adr0; |
8'h33: wb_rf_dout <= #1 ch5_am0; |
8'h34: wb_rf_dout <= #1 ch5_adr1; |
8'h35: wb_rf_dout <= #1 ch5_am1; |
8'h36: wb_rf_dout <= #1 pointer5; |
8'h37: wb_rf_dout <= #1 sw_pointer5; |
`endif |
8'h30: wb_rf_dout <= #1 ch5_conf[0] ? ch5_csr : 32'h0; |
8'h31: wb_rf_dout <= #1 ch5_conf[0] ? ch5_txsz : 32'h0; |
8'h32: wb_rf_dout <= #1 ch5_conf[0] ? ch5_adr0 : 32'h0; |
8'h33: wb_rf_dout <= #1 ch5_conf[0] ? ch5_am0 : 32'h0; |
8'h34: wb_rf_dout <= #1 ch5_conf[0] ? ch5_adr1 : 32'h0; |
8'h35: wb_rf_dout <= #1 ch5_conf[0] ? ch5_am1 : 32'h0; |
8'h36: wb_rf_dout <= #1 ch5_conf[0] ? pointer5 : 32'h0; |
8'h37: wb_rf_dout <= #1 ch5_conf[0] ? sw_pointer5 : 32'h0; |
|
`ifdef WDMA_HAVE_CH6 |
8'h38: wb_rf_dout <= #1 ch6_csr; |
8'h39: wb_rf_dout <= #1 ch6_txsz; |
8'h3a: wb_rf_dout <= #1 ch6_adr0; |
8'h3b: wb_rf_dout <= #1 ch6_am0; |
8'h3c: wb_rf_dout <= #1 ch6_adr1; |
8'h3d: wb_rf_dout <= #1 ch6_am1; |
8'h3e: wb_rf_dout <= #1 pointer6; |
8'h3f: wb_rf_dout <= #1 sw_pointer6; |
`endif |
8'h38: wb_rf_dout <= #1 ch6_conf[0] ? ch6_csr : 32'h0; |
8'h39: wb_rf_dout <= #1 ch6_conf[0] ? ch6_txsz : 32'h0; |
8'h3a: wb_rf_dout <= #1 ch6_conf[0] ? ch6_adr0 : 32'h0; |
8'h3b: wb_rf_dout <= #1 ch6_conf[0] ? ch6_am0 : 32'h0; |
8'h3c: wb_rf_dout <= #1 ch6_conf[0] ? ch6_adr1 : 32'h0; |
8'h3d: wb_rf_dout <= #1 ch6_conf[0] ? ch6_am1 : 32'h0; |
8'h3e: wb_rf_dout <= #1 ch6_conf[0] ? pointer6 : 32'h0; |
8'h3f: wb_rf_dout <= #1 ch6_conf[0] ? sw_pointer6 : 32'h0; |
|
`ifdef WDMA_HAVE_CH7 |
8'h40: wb_rf_dout <= #1 ch7_csr; |
8'h41: wb_rf_dout <= #1 ch7_txsz; |
8'h42: wb_rf_dout <= #1 ch7_adr0; |
8'h43: wb_rf_dout <= #1 ch7_am0; |
8'h44: wb_rf_dout <= #1 ch7_adr1; |
8'h45: wb_rf_dout <= #1 ch7_am1; |
8'h46: wb_rf_dout <= #1 pointer7; |
8'h47: wb_rf_dout <= #1 sw_pointer7; |
`endif |
8'h40: wb_rf_dout <= #1 ch7_conf[0] ? ch7_csr : 32'h0; |
8'h41: wb_rf_dout <= #1 ch7_conf[0] ? ch7_txsz : 32'h0; |
8'h42: wb_rf_dout <= #1 ch7_conf[0] ? ch7_adr0 : 32'h0; |
8'h43: wb_rf_dout <= #1 ch7_conf[0] ? ch7_am0 : 32'h0; |
8'h44: wb_rf_dout <= #1 ch7_conf[0] ? ch7_adr1 : 32'h0; |
8'h45: wb_rf_dout <= #1 ch7_conf[0] ? ch7_am1 : 32'h0; |
8'h46: wb_rf_dout <= #1 ch7_conf[0] ? pointer7 : 32'h0; |
8'h47: wb_rf_dout <= #1 ch7_conf[0] ? sw_pointer7 : 32'h0; |
|
`ifdef WDMA_HAVE_CH8 |
8'h48: wb_rf_dout <= #1 ch8_csr; |
8'h49: wb_rf_dout <= #1 ch8_txsz; |
8'h4a: wb_rf_dout <= #1 ch8_adr0; |
8'h4b: wb_rf_dout <= #1 ch8_am0; |
8'h4c: wb_rf_dout <= #1 ch8_adr1; |
8'h4d: wb_rf_dout <= #1 ch8_am1; |
8'h4e: wb_rf_dout <= #1 pointer8; |
8'h4f: wb_rf_dout <= #1 sw_pointer8; |
`endif |
8'h48: wb_rf_dout <= #1 ch8_conf[0] ? ch8_csr : 32'h0; |
8'h49: wb_rf_dout <= #1 ch8_conf[0] ? ch8_txsz : 32'h0; |
8'h4a: wb_rf_dout <= #1 ch8_conf[0] ? ch8_adr0 : 32'h0; |
8'h4b: wb_rf_dout <= #1 ch8_conf[0] ? ch8_am0 : 32'h0; |
8'h4c: wb_rf_dout <= #1 ch8_conf[0] ? ch8_adr1 : 32'h0; |
8'h4d: wb_rf_dout <= #1 ch8_conf[0] ? ch8_am1 : 32'h0; |
8'h4e: wb_rf_dout <= #1 ch8_conf[0] ? pointer8 : 32'h0; |
8'h4f: wb_rf_dout <= #1 ch8_conf[0] ? sw_pointer8 : 32'h0; |
|
`ifdef WDMA_HAVE_CH9 |
8'h50: wb_rf_dout <= #1 ch9_csr; |
8'h51: wb_rf_dout <= #1 ch9_txsz; |
8'h52: wb_rf_dout <= #1 ch9_adr0; |
8'h53: wb_rf_dout <= #1 ch9_am0; |
8'h54: wb_rf_dout <= #1 ch9_adr1; |
8'h55: wb_rf_dout <= #1 ch9_am1; |
8'h56: wb_rf_dout <= #1 pointer9; |
8'h57: wb_rf_dout <= #1 sw_pointer9; |
`endif |
8'h50: wb_rf_dout <= #1 ch9_conf[0] ? ch9_csr : 32'h0; |
8'h51: wb_rf_dout <= #1 ch9_conf[0] ? ch9_txsz : 32'h0; |
8'h52: wb_rf_dout <= #1 ch9_conf[0] ? ch9_adr0 : 32'h0; |
8'h53: wb_rf_dout <= #1 ch9_conf[0] ? ch9_am0 : 32'h0; |
8'h54: wb_rf_dout <= #1 ch9_conf[0] ? ch9_adr1 : 32'h0; |
8'h55: wb_rf_dout <= #1 ch9_conf[0] ? ch9_am1 : 32'h0; |
8'h56: wb_rf_dout <= #1 ch9_conf[0] ? pointer9 : 32'h0; |
8'h57: wb_rf_dout <= #1 ch9_conf[0] ? sw_pointer9 : 32'h0; |
|
`ifdef WDMA_HAVE_CH10 |
8'h58: wb_rf_dout <= #1 ch10_csr; |
8'h59: wb_rf_dout <= #1 ch10_txsz; |
8'h5a: wb_rf_dout <= #1 ch10_adr0; |
8'h5b: wb_rf_dout <= #1 ch10_am0; |
8'h5c: wb_rf_dout <= #1 ch10_adr1; |
8'h5d: wb_rf_dout <= #1 ch10_am1; |
8'h5e: wb_rf_dout <= #1 pointer10; |
8'h5f: wb_rf_dout <= #1 sw_pointer10; |
`endif |
8'h58: wb_rf_dout <= #1 ch10_conf[0] ? ch10_csr : 32'h0; |
8'h59: wb_rf_dout <= #1 ch10_conf[0] ? ch10_txsz : 32'h0; |
8'h5a: wb_rf_dout <= #1 ch10_conf[0] ? ch10_adr0 : 32'h0; |
8'h5b: wb_rf_dout <= #1 ch10_conf[0] ? ch10_am0 : 32'h0; |
8'h5c: wb_rf_dout <= #1 ch10_conf[0] ? ch10_adr1 : 32'h0; |
8'h5d: wb_rf_dout <= #1 ch10_conf[0] ? ch10_am1 : 32'h0; |
8'h5e: wb_rf_dout <= #1 ch10_conf[0] ? pointer10 : 32'h0; |
8'h5f: wb_rf_dout <= #1 ch10_conf[0] ? sw_pointer10 : 32'h0; |
|
`ifdef WDMA_HAVE_CH11 |
8'h60: wb_rf_dout <= #1 ch11_csr; |
8'h61: wb_rf_dout <= #1 ch11_txsz; |
8'h62: wb_rf_dout <= #1 ch11_adr0; |
8'h63: wb_rf_dout <= #1 ch11_am0; |
8'h64: wb_rf_dout <= #1 ch11_adr1; |
8'h65: wb_rf_dout <= #1 ch11_am1; |
8'h66: wb_rf_dout <= #1 pointer11; |
8'h67: wb_rf_dout <= #1 sw_pointer11; |
`endif |
8'h60: wb_rf_dout <= #1 ch11_conf[0] ? ch11_csr : 32'h0; |
8'h61: wb_rf_dout <= #1 ch11_conf[0] ? ch11_txsz : 32'h0; |
8'h62: wb_rf_dout <= #1 ch11_conf[0] ? ch11_adr0 : 32'h0; |
8'h63: wb_rf_dout <= #1 ch11_conf[0] ? ch11_am0 : 32'h0; |
8'h64: wb_rf_dout <= #1 ch11_conf[0] ? ch11_adr1 : 32'h0; |
8'h65: wb_rf_dout <= #1 ch11_conf[0] ? ch11_am1 : 32'h0; |
8'h66: wb_rf_dout <= #1 ch11_conf[0] ? pointer11 : 32'h0; |
8'h67: wb_rf_dout <= #1 ch11_conf[0] ? sw_pointer11 : 32'h0; |
|
`ifdef WDMA_HAVE_CH12 |
8'h68: wb_rf_dout <= #1 ch12_csr; |
8'h69: wb_rf_dout <= #1 ch12_txsz; |
8'h6a: wb_rf_dout <= #1 ch12_adr0; |
8'h6b: wb_rf_dout <= #1 ch12_am0; |
8'h6c: wb_rf_dout <= #1 ch12_adr1; |
8'h6d: wb_rf_dout <= #1 ch12_am1; |
8'h6e: wb_rf_dout <= #1 pointer12; |
8'h6f: wb_rf_dout <= #1 sw_pointer12; |
`endif |
8'h68: wb_rf_dout <= #1 ch12_conf[0] ? ch12_csr : 32'h0; |
8'h69: wb_rf_dout <= #1 ch12_conf[0] ? ch12_txsz : 32'h0; |
8'h6a: wb_rf_dout <= #1 ch12_conf[0] ? ch12_adr0 : 32'h0; |
8'h6b: wb_rf_dout <= #1 ch12_conf[0] ? ch12_am0 : 32'h0; |
8'h6c: wb_rf_dout <= #1 ch12_conf[0] ? ch12_adr1 : 32'h0; |
8'h6d: wb_rf_dout <= #1 ch12_conf[0] ? ch12_am1 : 32'h0; |
8'h6e: wb_rf_dout <= #1 ch12_conf[0] ? pointer12 : 32'h0; |
8'h6f: wb_rf_dout <= #1 ch12_conf[0] ? sw_pointer12 : 32'h0; |
|
`ifdef WDMA_HAVE_CH13 |
8'h70: wb_rf_dout <= #1 ch13_csr; |
8'h71: wb_rf_dout <= #1 ch13_txsz; |
8'h72: wb_rf_dout <= #1 ch13_adr0; |
8'h73: wb_rf_dout <= #1 ch13_am0; |
8'h74: wb_rf_dout <= #1 ch13_adr1; |
8'h75: wb_rf_dout <= #1 ch13_am1; |
8'h76: wb_rf_dout <= #1 pointer13; |
8'h77: wb_rf_dout <= #1 sw_pointer13; |
`endif |
8'h70: wb_rf_dout <= #1 ch13_conf[0] ? ch13_csr : 32'h0; |
8'h71: wb_rf_dout <= #1 ch13_conf[0] ? ch13_txsz : 32'h0; |
8'h72: wb_rf_dout <= #1 ch13_conf[0] ? ch13_adr0 : 32'h0; |
8'h73: wb_rf_dout <= #1 ch13_conf[0] ? ch13_am0 : 32'h0; |
8'h74: wb_rf_dout <= #1 ch13_conf[0] ? ch13_adr1 : 32'h0; |
8'h75: wb_rf_dout <= #1 ch13_conf[0] ? ch13_am1 : 32'h0; |
8'h76: wb_rf_dout <= #1 ch13_conf[0] ? pointer13 : 32'h0; |
8'h77: wb_rf_dout <= #1 ch13_conf[0] ? sw_pointer13 : 32'h0; |
|
`ifdef WDMA_HAVE_CH14 |
8'h78: wb_rf_dout <= #1 ch14_csr; |
8'h79: wb_rf_dout <= #1 ch14_txsz; |
8'h7a: wb_rf_dout <= #1 ch14_adr0; |
8'h7b: wb_rf_dout <= #1 ch14_am0; |
8'h7c: wb_rf_dout <= #1 ch14_adr1; |
8'h7d: wb_rf_dout <= #1 ch14_am1; |
8'h7e: wb_rf_dout <= #1 pointer14; |
8'h7f: wb_rf_dout <= #1 sw_pointer14; |
`endif |
8'h78: wb_rf_dout <= #1 ch14_conf[0] ? ch14_csr : 32'h0; |
8'h79: wb_rf_dout <= #1 ch14_conf[0] ? ch14_txsz : 32'h0; |
8'h7a: wb_rf_dout <= #1 ch14_conf[0] ? ch14_adr0 : 32'h0; |
8'h7b: wb_rf_dout <= #1 ch14_conf[0] ? ch14_am0 : 32'h0; |
8'h7c: wb_rf_dout <= #1 ch14_conf[0] ? ch14_adr1 : 32'h0; |
8'h7d: wb_rf_dout <= #1 ch14_conf[0] ? ch14_am1 : 32'h0; |
8'h7e: wb_rf_dout <= #1 ch14_conf[0] ? pointer14 : 32'h0; |
8'h7f: wb_rf_dout <= #1 ch14_conf[0] ? sw_pointer14 : 32'h0; |
|
`ifdef WDMA_HAVE_CH15 |
8'h80: wb_rf_dout <= #1 ch15_csr; |
8'h81: wb_rf_dout <= #1 ch15_txsz; |
8'h82: wb_rf_dout <= #1 ch15_adr0; |
8'h83: wb_rf_dout <= #1 ch15_am0; |
8'h84: wb_rf_dout <= #1 ch15_adr1; |
8'h85: wb_rf_dout <= #1 ch15_am1; |
8'h86: wb_rf_dout <= #1 pointer15; |
8'h87: wb_rf_dout <= #1 sw_pointer15; |
`endif |
8'h80: wb_rf_dout <= #1 ch15_conf[0] ? ch15_csr : 32'h0; |
8'h81: wb_rf_dout <= #1 ch15_conf[0] ? ch15_txsz : 32'h0; |
8'h82: wb_rf_dout <= #1 ch15_conf[0] ? ch15_adr0 : 32'h0; |
8'h83: wb_rf_dout <= #1 ch15_conf[0] ? ch15_am0 : 32'h0; |
8'h84: wb_rf_dout <= #1 ch15_conf[0] ? ch15_adr1 : 32'h0; |
8'h85: wb_rf_dout <= #1 ch15_conf[0] ? ch15_am1 : 32'h0; |
8'h86: wb_rf_dout <= #1 ch15_conf[0] ? pointer15 : 32'h0; |
8'h87: wb_rf_dout <= #1 ch15_conf[0] ? sw_pointer15 : 32'h0; |
|
`ifdef WDMA_HAVE_CH16 |
8'h88: wb_rf_dout <= #1 ch16_csr; |
8'h89: wb_rf_dout <= #1 ch16_txsz; |
8'h8a: wb_rf_dout <= #1 ch16_adr0; |
8'h8b: wb_rf_dout <= #1 ch16_am0; |
8'h8c: wb_rf_dout <= #1 ch16_adr1; |
8'h8d: wb_rf_dout <= #1 ch16_am1; |
8'h8e: wb_rf_dout <= #1 pointer16; |
8'h8f: wb_rf_dout <= #1 sw_pointer16; |
`endif |
8'h88: wb_rf_dout <= #1 ch16_conf[0] ? ch16_csr : 32'h0; |
8'h89: wb_rf_dout <= #1 ch16_conf[0] ? ch16_txsz : 32'h0; |
8'h8a: wb_rf_dout <= #1 ch16_conf[0] ? ch16_adr0 : 32'h0; |
8'h8b: wb_rf_dout <= #1 ch16_conf[0] ? ch16_am0 : 32'h0; |
8'h8c: wb_rf_dout <= #1 ch16_conf[0] ? ch16_adr1 : 32'h0; |
8'h8d: wb_rf_dout <= #1 ch16_conf[0] ? ch16_am1 : 32'h0; |
8'h8e: wb_rf_dout <= #1 ch16_conf[0] ? pointer16 : 32'h0; |
8'h8f: wb_rf_dout <= #1 ch16_conf[0] ? sw_pointer16 : 32'h0; |
|
`ifdef WDMA_HAVE_CH17 |
8'h90: wb_rf_dout <= #1 ch17_csr; |
8'h91: wb_rf_dout <= #1 ch17_txsz; |
8'h92: wb_rf_dout <= #1 ch17_adr0; |
8'h93: wb_rf_dout <= #1 ch17_am0; |
8'h94: wb_rf_dout <= #1 ch17_adr1; |
8'h95: wb_rf_dout <= #1 ch17_am1; |
8'h96: wb_rf_dout <= #1 pointer17; |
8'h97: wb_rf_dout <= #1 sw_pointer17; |
`endif |
8'h90: wb_rf_dout <= #1 ch17_conf[0] ? ch17_csr : 32'h0; |
8'h91: wb_rf_dout <= #1 ch17_conf[0] ? ch17_txsz : 32'h0; |
8'h92: wb_rf_dout <= #1 ch17_conf[0] ? ch17_adr0 : 32'h0; |
8'h93: wb_rf_dout <= #1 ch17_conf[0] ? ch17_am0 : 32'h0; |
8'h94: wb_rf_dout <= #1 ch17_conf[0] ? ch17_adr1 : 32'h0; |
8'h95: wb_rf_dout <= #1 ch17_conf[0] ? ch17_am1 : 32'h0; |
8'h96: wb_rf_dout <= #1 ch17_conf[0] ? pointer17 : 32'h0; |
8'h97: wb_rf_dout <= #1 ch17_conf[0] ? sw_pointer17 : 32'h0; |
|
`ifdef WDMA_HAVE_CH18 |
8'h98: wb_rf_dout <= #1 ch18_csr; |
8'h99: wb_rf_dout <= #1 ch18_txsz; |
8'h9a: wb_rf_dout <= #1 ch18_adr0; |
8'h9b: wb_rf_dout <= #1 ch18_am0; |
8'h9c: wb_rf_dout <= #1 ch18_adr1; |
8'h9d: wb_rf_dout <= #1 ch18_am1; |
8'h9e: wb_rf_dout <= #1 pointer18; |
8'h9f: wb_rf_dout <= #1 sw_pointer18; |
`endif |
8'h98: wb_rf_dout <= #1 ch18_conf[0] ? ch18_csr : 32'h0; |
8'h99: wb_rf_dout <= #1 ch18_conf[0] ? ch18_txsz : 32'h0; |
8'h9a: wb_rf_dout <= #1 ch18_conf[0] ? ch18_adr0 : 32'h0; |
8'h9b: wb_rf_dout <= #1 ch18_conf[0] ? ch18_am0 : 32'h0; |
8'h9c: wb_rf_dout <= #1 ch18_conf[0] ? ch18_adr1 : 32'h0; |
8'h9d: wb_rf_dout <= #1 ch18_conf[0] ? ch18_am1 : 32'h0; |
8'h9e: wb_rf_dout <= #1 ch18_conf[0] ? pointer18 : 32'h0; |
8'h9f: wb_rf_dout <= #1 ch18_conf[0] ? sw_pointer18 : 32'h0; |
|
`ifdef WDMA_HAVE_CH19 |
8'ha0: wb_rf_dout <= #1 ch19_csr; |
8'ha1: wb_rf_dout <= #1 ch19_txsz; |
8'ha2: wb_rf_dout <= #1 ch19_adr0; |
8'ha3: wb_rf_dout <= #1 ch19_am0; |
8'ha4: wb_rf_dout <= #1 ch19_adr1; |
8'ha5: wb_rf_dout <= #1 ch19_am1; |
8'ha6: wb_rf_dout <= #1 pointer19; |
8'ha7: wb_rf_dout <= #1 sw_pointer19; |
`endif |
8'ha0: wb_rf_dout <= #1 ch19_conf[0] ? ch19_csr : 32'h0; |
8'ha1: wb_rf_dout <= #1 ch19_conf[0] ? ch19_txsz : 32'h0; |
8'ha2: wb_rf_dout <= #1 ch19_conf[0] ? ch19_adr0 : 32'h0; |
8'ha3: wb_rf_dout <= #1 ch19_conf[0] ? ch19_am0 : 32'h0; |
8'ha4: wb_rf_dout <= #1 ch19_conf[0] ? ch19_adr1 : 32'h0; |
8'ha5: wb_rf_dout <= #1 ch19_conf[0] ? ch19_am1 : 32'h0; |
8'ha6: wb_rf_dout <= #1 ch19_conf[0] ? pointer19 : 32'h0; |
8'ha7: wb_rf_dout <= #1 ch19_conf[0] ? sw_pointer19 : 32'h0; |
|
`ifdef WDMA_HAVE_CH20 |
8'ha8: wb_rf_dout <= #1 ch20_csr; |
8'ha9: wb_rf_dout <= #1 ch20_txsz; |
8'haa: wb_rf_dout <= #1 ch20_adr0; |
8'hab: wb_rf_dout <= #1 ch20_am0; |
8'hac: wb_rf_dout <= #1 ch20_adr1; |
8'had: wb_rf_dout <= #1 ch20_am1; |
8'hae: wb_rf_dout <= #1 pointer20; |
8'haf: wb_rf_dout <= #1 sw_pointer20; |
`endif |
8'ha8: wb_rf_dout <= #1 ch20_conf[0] ? ch20_csr : 32'h0; |
8'ha9: wb_rf_dout <= #1 ch20_conf[0] ? ch20_txsz : 32'h0; |
8'haa: wb_rf_dout <= #1 ch20_conf[0] ? ch20_adr0 : 32'h0; |
8'hab: wb_rf_dout <= #1 ch20_conf[0] ? ch20_am0 : 32'h0; |
8'hac: wb_rf_dout <= #1 ch20_conf[0] ? ch20_adr1 : 32'h0; |
8'had: wb_rf_dout <= #1 ch20_conf[0] ? ch20_am1 : 32'h0; |
8'hae: wb_rf_dout <= #1 ch20_conf[0] ? pointer20 : 32'h0; |
8'haf: wb_rf_dout <= #1 ch20_conf[0] ? sw_pointer20 : 32'h0; |
|
`ifdef WDMA_HAVE_CH21 |
8'hb0: wb_rf_dout <= #1 ch21_csr; |
8'hb1: wb_rf_dout <= #1 ch21_txsz; |
8'hb2: wb_rf_dout <= #1 ch21_adr0; |
8'hb3: wb_rf_dout <= #1 ch21_am0; |
8'hb4: wb_rf_dout <= #1 ch21_adr1; |
8'hb5: wb_rf_dout <= #1 ch21_am1; |
8'hb6: wb_rf_dout <= #1 pointer21; |
8'hb7: wb_rf_dout <= #1 sw_pointer21; |
`endif |
8'hb0: wb_rf_dout <= #1 ch21_conf[0] ? ch21_csr : 32'h0; |
8'hb1: wb_rf_dout <= #1 ch21_conf[0] ? ch21_txsz : 32'h0; |
8'hb2: wb_rf_dout <= #1 ch21_conf[0] ? ch21_adr0 : 32'h0; |
8'hb3: wb_rf_dout <= #1 ch21_conf[0] ? ch21_am0 : 32'h0; |
8'hb4: wb_rf_dout <= #1 ch21_conf[0] ? ch21_adr1 : 32'h0; |
8'hb5: wb_rf_dout <= #1 ch21_conf[0] ? ch21_am1 : 32'h0; |
8'hb6: wb_rf_dout <= #1 ch21_conf[0] ? pointer21 : 32'h0; |
8'hb7: wb_rf_dout <= #1 ch21_conf[0] ? sw_pointer21 : 32'h0; |
|
`ifdef WDMA_HAVE_CH22 |
8'hb8: wb_rf_dout <= #1 ch22_csr; |
8'hb9: wb_rf_dout <= #1 ch22_txsz; |
8'hba: wb_rf_dout <= #1 ch22_adr0; |
8'hbb: wb_rf_dout <= #1 ch22_am0; |
8'hbc: wb_rf_dout <= #1 ch22_adr1; |
8'hbd: wb_rf_dout <= #1 ch22_am1; |
8'hbe: wb_rf_dout <= #1 pointer22; |
8'hbf: wb_rf_dout <= #1 sw_pointer22; |
`endif |
8'hb8: wb_rf_dout <= #1 ch22_conf[0] ? ch22_csr : 32'h0; |
8'hb9: wb_rf_dout <= #1 ch22_conf[0] ? ch22_txsz : 32'h0; |
8'hba: wb_rf_dout <= #1 ch22_conf[0] ? ch22_adr0 : 32'h0; |
8'hbb: wb_rf_dout <= #1 ch22_conf[0] ? ch22_am0 : 32'h0; |
8'hbc: wb_rf_dout <= #1 ch22_conf[0] ? ch22_adr1 : 32'h0; |
8'hbd: wb_rf_dout <= #1 ch22_conf[0] ? ch22_am1 : 32'h0; |
8'hbe: wb_rf_dout <= #1 ch22_conf[0] ? pointer22 : 32'h0; |
8'hbf: wb_rf_dout <= #1 ch22_conf[0] ? sw_pointer22 : 32'h0; |
|
`ifdef WDMA_HAVE_CH23 |
8'hc0: wb_rf_dout <= #1 ch23_csr; |
8'hc1: wb_rf_dout <= #1 ch23_txsz; |
8'hc2: wb_rf_dout <= #1 ch23_adr0; |
8'hc3: wb_rf_dout <= #1 ch23_am0; |
8'hc4: wb_rf_dout <= #1 ch23_adr1; |
8'hc5: wb_rf_dout <= #1 ch23_am1; |
8'hc6: wb_rf_dout <= #1 pointer23; |
8'hc7: wb_rf_dout <= #1 sw_pointer23; |
`endif |
8'hc0: wb_rf_dout <= #1 ch23_conf[0] ? ch23_csr : 32'h0; |
8'hc1: wb_rf_dout <= #1 ch23_conf[0] ? ch23_txsz : 32'h0; |
8'hc2: wb_rf_dout <= #1 ch23_conf[0] ? ch23_adr0 : 32'h0; |
8'hc3: wb_rf_dout <= #1 ch23_conf[0] ? ch23_am0 : 32'h0; |
8'hc4: wb_rf_dout <= #1 ch23_conf[0] ? ch23_adr1 : 32'h0; |
8'hc5: wb_rf_dout <= #1 ch23_conf[0] ? ch23_am1 : 32'h0; |
8'hc6: wb_rf_dout <= #1 ch23_conf[0] ? pointer23 : 32'h0; |
8'hc7: wb_rf_dout <= #1 ch23_conf[0] ? sw_pointer23 : 32'h0; |
|
`ifdef WDMA_HAVE_CH24 |
8'hc8: wb_rf_dout <= #1 ch24_csr; |
8'hc9: wb_rf_dout <= #1 ch24_txsz; |
8'hca: wb_rf_dout <= #1 ch24_adr0; |
8'hcb: wb_rf_dout <= #1 ch24_am0; |
8'hcc: wb_rf_dout <= #1 ch24_adr1; |
8'hcd: wb_rf_dout <= #1 ch24_am1; |
8'hce: wb_rf_dout <= #1 pointer24; |
8'hcf: wb_rf_dout <= #1 sw_pointer24; |
`endif |
8'hc8: wb_rf_dout <= #1 ch24_conf[0] ? ch24_csr : 32'h0; |
8'hc9: wb_rf_dout <= #1 ch24_conf[0] ? ch24_txsz : 32'h0; |
8'hca: wb_rf_dout <= #1 ch24_conf[0] ? ch24_adr0 : 32'h0; |
8'hcb: wb_rf_dout <= #1 ch24_conf[0] ? ch24_am0 : 32'h0; |
8'hcc: wb_rf_dout <= #1 ch24_conf[0] ? ch24_adr1 : 32'h0; |
8'hcd: wb_rf_dout <= #1 ch24_conf[0] ? ch24_am1 : 32'h0; |
8'hce: wb_rf_dout <= #1 ch24_conf[0] ? pointer24 : 32'h0; |
8'hcf: wb_rf_dout <= #1 ch24_conf[0] ? sw_pointer24 : 32'h0; |
|
`ifdef WDMA_HAVE_CH25 |
8'hd0: wb_rf_dout <= #1 ch25_csr; |
8'hd1: wb_rf_dout <= #1 ch25_txsz; |
8'hd2: wb_rf_dout <= #1 ch25_adr0; |
8'hd3: wb_rf_dout <= #1 ch25_am0; |
8'hd4: wb_rf_dout <= #1 ch25_adr1; |
8'hd5: wb_rf_dout <= #1 ch25_am1; |
8'hd6: wb_rf_dout <= #1 pointer25; |
8'hd7: wb_rf_dout <= #1 sw_pointer25; |
`endif |
8'hd0: wb_rf_dout <= #1 ch25_conf[0] ? ch25_csr : 32'h0; |
8'hd1: wb_rf_dout <= #1 ch25_conf[0] ? ch25_txsz : 32'h0; |
8'hd2: wb_rf_dout <= #1 ch25_conf[0] ? ch25_adr0 : 32'h0; |
8'hd3: wb_rf_dout <= #1 ch25_conf[0] ? ch25_am0 : 32'h0; |
8'hd4: wb_rf_dout <= #1 ch25_conf[0] ? ch25_adr1 : 32'h0; |
8'hd5: wb_rf_dout <= #1 ch25_conf[0] ? ch25_am1 : 32'h0; |
8'hd6: wb_rf_dout <= #1 ch25_conf[0] ? pointer25 : 32'h0; |
8'hd7: wb_rf_dout <= #1 ch25_conf[0] ? sw_pointer25 : 32'h0; |
|
`ifdef WDMA_HAVE_CH26 |
8'hd8: wb_rf_dout <= #1 ch26_csr; |
8'hd9: wb_rf_dout <= #1 ch26_txsz; |
8'hda: wb_rf_dout <= #1 ch26_adr0; |
8'hdb: wb_rf_dout <= #1 ch26_am0; |
8'hdc: wb_rf_dout <= #1 ch26_adr1; |
8'hdd: wb_rf_dout <= #1 ch26_am1; |
8'hde: wb_rf_dout <= #1 pointer26; |
8'hdf: wb_rf_dout <= #1 sw_pointer26; |
`endif |
8'hd8: wb_rf_dout <= #1 ch26_conf[0] ? ch26_csr : 32'h0; |
8'hd9: wb_rf_dout <= #1 ch26_conf[0] ? ch26_txsz : 32'h0; |
8'hda: wb_rf_dout <= #1 ch26_conf[0] ? ch26_adr0 : 32'h0; |
8'hdb: wb_rf_dout <= #1 ch26_conf[0] ? ch26_am0 : 32'h0; |
8'hdc: wb_rf_dout <= #1 ch26_conf[0] ? ch26_adr1 : 32'h0; |
8'hdd: wb_rf_dout <= #1 ch26_conf[0] ? ch26_am1 : 32'h0; |
8'hde: wb_rf_dout <= #1 ch26_conf[0] ? pointer26 : 32'h0; |
8'hdf: wb_rf_dout <= #1 ch26_conf[0] ? sw_pointer26 : 32'h0; |
|
`ifdef WDMA_HAVE_CH27 |
8'he0: wb_rf_dout <= #1 ch27_csr; |
8'he1: wb_rf_dout <= #1 ch27_txsz; |
8'he2: wb_rf_dout <= #1 ch27_adr0; |
8'he3: wb_rf_dout <= #1 ch27_am0; |
8'he4: wb_rf_dout <= #1 ch27_adr1; |
8'he5: wb_rf_dout <= #1 ch27_am1; |
8'he6: wb_rf_dout <= #1 pointer27; |
8'he7: wb_rf_dout <= #1 sw_pointer27; |
`endif |
8'he0: wb_rf_dout <= #1 ch27_conf[0] ? ch27_csr : 32'h0; |
8'he1: wb_rf_dout <= #1 ch27_conf[0] ? ch27_txsz : 32'h0; |
8'he2: wb_rf_dout <= #1 ch27_conf[0] ? ch27_adr0 : 32'h0; |
8'he3: wb_rf_dout <= #1 ch27_conf[0] ? ch27_am0 : 32'h0; |
8'he4: wb_rf_dout <= #1 ch27_conf[0] ? ch27_adr1 : 32'h0; |
8'he5: wb_rf_dout <= #1 ch27_conf[0] ? ch27_am1 : 32'h0; |
8'he6: wb_rf_dout <= #1 ch27_conf[0] ? pointer27 : 32'h0; |
8'he7: wb_rf_dout <= #1 ch27_conf[0] ? sw_pointer27 : 32'h0; |
|
`ifdef WDMA_HAVE_CH28 |
8'he8: wb_rf_dout <= #1 ch28_csr; |
8'he9: wb_rf_dout <= #1 ch28_txsz; |
8'hea: wb_rf_dout <= #1 ch28_adr0; |
8'heb: wb_rf_dout <= #1 ch28_am0; |
8'hec: wb_rf_dout <= #1 ch28_adr1; |
8'hed: wb_rf_dout <= #1 ch28_am1; |
8'hee: wb_rf_dout <= #1 pointer28; |
8'hef: wb_rf_dout <= #1 sw_pointer28; |
`endif |
8'he8: wb_rf_dout <= #1 ch28_conf[0] ? ch28_csr : 32'h0; |
8'he9: wb_rf_dout <= #1 ch28_conf[0] ? ch28_txsz : 32'h0; |
8'hea: wb_rf_dout <= #1 ch28_conf[0] ? ch28_adr0 : 32'h0; |
8'heb: wb_rf_dout <= #1 ch28_conf[0] ? ch28_am0 : 32'h0; |
8'hec: wb_rf_dout <= #1 ch28_conf[0] ? ch28_adr1 : 32'h0; |
8'hed: wb_rf_dout <= #1 ch28_conf[0] ? ch28_am1 : 32'h0; |
8'hee: wb_rf_dout <= #1 ch28_conf[0] ? pointer28 : 32'h0; |
8'hef: wb_rf_dout <= #1 ch28_conf[0] ? sw_pointer28 : 32'h0; |
|
`ifdef WDMA_HAVE_CH29 |
8'hf0: wb_rf_dout <= #1 ch29_csr; |
8'hf1: wb_rf_dout <= #1 ch29_txsz; |
8'hf2: wb_rf_dout <= #1 ch29_adr0; |
8'hf3: wb_rf_dout <= #1 ch29_am0; |
8'hf4: wb_rf_dout <= #1 ch29_adr1; |
8'hf5: wb_rf_dout <= #1 ch29_am1; |
8'hf6: wb_rf_dout <= #1 pointer29; |
8'hf7: wb_rf_dout <= #1 sw_pointer29; |
`endif |
8'hf0: wb_rf_dout <= #1 ch29_conf[0] ? ch29_csr : 32'h0; |
8'hf1: wb_rf_dout <= #1 ch29_conf[0] ? ch29_txsz : 32'h0; |
8'hf2: wb_rf_dout <= #1 ch29_conf[0] ? ch29_adr0 : 32'h0; |
8'hf3: wb_rf_dout <= #1 ch29_conf[0] ? ch29_am0 : 32'h0; |
8'hf4: wb_rf_dout <= #1 ch29_conf[0] ? ch29_adr1 : 32'h0; |
8'hf5: wb_rf_dout <= #1 ch29_conf[0] ? ch29_am1 : 32'h0; |
8'hf6: wb_rf_dout <= #1 ch29_conf[0] ? pointer29 : 32'h0; |
8'hf7: wb_rf_dout <= #1 ch29_conf[0] ? sw_pointer29 : 32'h0; |
|
`ifdef WDMA_HAVE_CH30 |
8'hf8: wb_rf_dout <= #1 ch30_csr; |
8'hf9: wb_rf_dout <= #1 ch30_txsz; |
8'hfa: wb_rf_dout <= #1 ch30_adr0; |
8'hfb: wb_rf_dout <= #1 ch30_am0; |
8'hfc: wb_rf_dout <= #1 ch30_adr1; |
8'hfd: wb_rf_dout <= #1 ch30_am1; |
8'hfe: wb_rf_dout <= #1 pointer30; |
8'hff: wb_rf_dout <= #1 sw_pointer30; |
`endif |
8'hf8: wb_rf_dout <= #1 ch30_conf[0] ? ch30_csr : 32'h0; |
8'hf9: wb_rf_dout <= #1 ch30_conf[0] ? ch30_txsz : 32'h0; |
8'hfa: wb_rf_dout <= #1 ch30_conf[0] ? ch30_adr0 : 32'h0; |
8'hfb: wb_rf_dout <= #1 ch30_conf[0] ? ch30_am0 : 32'h0; |
8'hfc: wb_rf_dout <= #1 ch30_conf[0] ? ch30_adr1 : 32'h0; |
8'hfd: wb_rf_dout <= #1 ch30_conf[0] ? ch30_am1 : 32'h0; |
8'hfe: wb_rf_dout <= #1 ch30_conf[0] ? pointer30 : 32'h0; |
8'hff: wb_rf_dout <= #1 ch30_conf[0] ? sw_pointer30 : 32'h0; |
|
`ifdef WDMA_HAVE_CH31 |
8'h100: wb_rf_dout <= #1 ch31_csr; |
8'h101: wb_rf_dout <= #1 ch31_txsz; |
8'h102: wb_rf_dout <= #1 ch31_adr0; |
8'h103: wb_rf_dout <= #1 ch31_am0; |
8'h104: wb_rf_dout <= #1 ch31_adr1; |
8'h105: wb_rf_dout <= #1 ch31_am1; |
8'h106: wb_rf_dout <= #1 pointer31; |
8'h107: wb_rf_dout <= #1 sw_pointer31; |
`endif |
endcase |
|
|
689,7 → 668,9
// Channel Register File |
// |
|
wb_dma_ch_rf #(0, `WDMA_HAVE_ARS0, `WDMA_HAVE_ED0, `WDMA_HAVE_CBUF0) u0( |
// chXX_conf = { CBUF, ED, ARS, EN } |
|
wb_dma_ch_rf #(0, ch0_conf[0], ch0_conf[1], ch0_conf[2], ch0_conf[3]) u0( |
.clk( clk ), |
.rst( rst ), |
.pointer( pointer0 ), |
727,8 → 708,7
.ptr_set( ptr_set ) |
); |
|
`ifdef WDMA_HAVE_CH1 |
wb_dma_ch_rf #(1, `WDMA_HAVE_ARS1, `WDMA_HAVE_ED1, `WDMA_HAVE_CBUF1) u1( |
wb_dma_ch_rf #(1, ch1_conf[0], ch1_conf[1], ch1_conf[2], ch1_conf[3]) u1( |
.clk( clk ), |
.rst( rst ), |
.pointer( pointer1 ), |
765,49 → 745,8
.dma_rest( dma_rest[1] ), |
.ptr_set( ptr_set ) |
); |
`else |
wb_dma_ch_rf_dummy #(1, `WDMA_HAVE_ARS1, `WDMA_HAVE_ED1, `WDMA_HAVE_CBUF1) u1( |
.clk( clk ), |
.rst( rst ), |
.pointer( pointer1 ), |
.pointer_s( pointer1_s ), |
.ch_csr( ch1_csr ), |
.ch_txsz( ch1_txsz ), |
.ch_adr0( ch1_adr0 ), |
.ch_adr1( ch1_adr1 ), |
.ch_am0( ch1_am0 ), |
.ch_am1( ch1_am1 ), |
.sw_pointer( sw_pointer1 ), |
.ch_stop( ch_stop[1] ), |
.ch_dis( ch_dis[1] ), |
.int( ch_int[1] ), |
.wb_rf_din( wb_rf_din ), |
.wb_rf_adr( wb_rf_adr ), |
.wb_rf_we( wb_rf_we ), |
.wb_rf_re( wb_rf_re ), |
.ch_sel( ch_sel ), |
.ndnr( ndnr[1] ), |
.dma_busy( dma_busy ), |
.dma_err( dma_err ), |
.dma_done( dma_done ), |
.dma_done_all( dma_done_all ), |
.de_csr( de_csr ), |
.de_txsz( de_txsz ), |
.de_adr0( de_adr0 ), |
.de_adr1( de_adr1 ), |
.de_csr_we( de_csr_we ), |
.de_txsz_we( de_txsz_we ), |
.de_adr0_we( de_adr0_we ), |
.de_adr1_we( de_adr1_we ), |
.de_fetch_descr(de_fetch_descr ), |
.dma_rest( dma_rest[1] ), |
.ptr_set( ptr_set ) |
); |
`endif |
|
|
`ifdef WDMA_HAVE_CH2 |
wb_dma_ch_rf #(2, `WDMA_HAVE_ARS2, `WDMA_HAVE_ED2, `WDMA_HAVE_CBUF2) u2( |
wb_dma_ch_rf #(2, ch2_conf[0], ch2_conf[1], ch2_conf[2], ch2_conf[3]) u2( |
.clk( clk ), |
.rst( rst ), |
.pointer( pointer2 ), |
844,49 → 783,8
.dma_rest( dma_rest[2] ), |
.ptr_set( ptr_set ) |
); |
`else |
wb_dma_ch_rf_dummy #(2, `WDMA_HAVE_ARS2, `WDMA_HAVE_ED2, `WDMA_HAVE_CBUF2) u2( |
.clk( clk ), |
.rst( rst ), |
.pointer( pointer2 ), |
.pointer_s( pointer2_s ), |
.ch_csr( ch2_csr ), |
.ch_txsz( ch2_txsz ), |
.ch_adr0( ch2_adr0 ), |
.ch_adr1( ch2_adr1 ), |
.ch_am0( ch2_am0 ), |
.ch_am1( ch2_am1 ), |
.sw_pointer( sw_pointer2 ), |
.ch_stop( ch_stop[2] ), |
.ch_dis( ch_dis[2] ), |
.int( ch_int[2] ), |
.wb_rf_din( wb_rf_din ), |
.wb_rf_adr( wb_rf_adr ), |
.wb_rf_we( wb_rf_we ), |
.wb_rf_re( wb_rf_re ), |
.ch_sel( ch_sel ), |
.ndnr( ndnr[2] ), |
.dma_busy( dma_busy ), |
.dma_err( dma_err ), |
.dma_done( dma_done ), |
.dma_done_all( dma_done_all ), |
.de_csr( de_csr ), |
.de_txsz( de_txsz ), |
.de_adr0( de_adr0 ), |
.de_adr1( de_adr1 ), |
.de_csr_we( de_csr_we ), |
.de_txsz_we( de_txsz_we ), |
.de_adr0_we( de_adr0_we ), |
.de_adr1_we( de_adr1_we ), |
.de_fetch_descr(de_fetch_descr ), |
.dma_rest( dma_rest[2] ), |
.ptr_set( ptr_set ) |
); |
`endif |
|
|
`ifdef WDMA_HAVE_CH3 |
wb_dma_ch_rf #(3, `WDMA_HAVE_ARS3, `WDMA_HAVE_ED3, `WDMA_HAVE_CBUF3) u3( |
wb_dma_ch_rf #(3, ch3_conf[0], ch3_conf[1], ch3_conf[2], ch3_conf[3]) u3( |
.clk( clk ), |
.rst( rst ), |
.pointer( pointer3 ), |
923,49 → 821,8
.dma_rest( dma_rest[3] ), |
.ptr_set( ptr_set ) |
); |
`else |
wb_dma_ch_rf_dummy #(3, `WDMA_HAVE_ARS3, `WDMA_HAVE_ED3, `WDMA_HAVE_CBUF3) u3( |
.clk( clk ), |
.rst( rst ), |
.pointer( pointer3 ), |
.pointer_s( pointer3_s ), |
.ch_csr( ch3_csr ), |
.ch_txsz( ch3_txsz ), |
.ch_adr0( ch3_adr0 ), |
.ch_adr1( ch3_adr1 ), |
.ch_am0( ch3_am0 ), |
.ch_am1( ch3_am1 ), |
.sw_pointer( sw_pointer3 ), |
.ch_stop( ch_stop[3] ), |
.ch_dis( ch_dis[3] ), |
.int( ch_int[3] ), |
.wb_rf_din( wb_rf_din ), |
.wb_rf_adr( wb_rf_adr ), |
.wb_rf_we( wb_rf_we ), |
.wb_rf_re( wb_rf_re ), |
.ch_sel( ch_sel ), |
.ndnr( ndnr[3] ), |
.dma_busy( dma_busy ), |
.dma_err( dma_err ), |
.dma_done( dma_done ), |
.dma_done_all( dma_done_all ), |
.de_csr( de_csr ), |
.de_txsz( de_txsz ), |
.de_adr0( de_adr0 ), |
.de_adr1( de_adr1 ), |
.de_csr_we( de_csr_we ), |
.de_txsz_we( de_txsz_we ), |
.de_adr0_we( de_adr0_we ), |
.de_adr1_we( de_adr1_we ), |
.de_fetch_descr(de_fetch_descr ), |
.dma_rest( dma_rest[3] ), |
.ptr_set( ptr_set ) |
); |
`endif |
|
|
`ifdef WDMA_HAVE_CH4 |
wb_dma_ch_rf #(4, `WDMA_HAVE_ARS4, `WDMA_HAVE_ED4, `WDMA_HAVE_CBUF4) u4( |
wb_dma_ch_rf #(4, ch4_conf[0], ch4_conf[1], ch4_conf[2], ch4_conf[3]) u4( |
.clk( clk ), |
.rst( rst ), |
.pointer( pointer4 ), |
1002,49 → 859,8
.dma_rest( dma_rest[4] ), |
.ptr_set( ptr_set ) |
); |
`else |
wb_dma_ch_rf_dummy #(4, `WDMA_HAVE_ARS4, `WDMA_HAVE_ED4, `WDMA_HAVE_CBUF4) u4( |
.clk( clk ), |
.rst( rst ), |
.pointer( pointer4 ), |
.pointer_s( pointer4_s ), |
.ch_csr( ch4_csr ), |
.ch_txsz( ch4_txsz ), |
.ch_adr0( ch4_adr0 ), |
.ch_adr1( ch4_adr1 ), |
.ch_am0( ch4_am0 ), |
.ch_am1( ch4_am1 ), |
.sw_pointer( sw_pointer4 ), |
.ch_stop( ch_stop[4] ), |
.ch_dis( ch_dis[4] ), |
.int( ch_int[4] ), |
.wb_rf_din( wb_rf_din ), |
.wb_rf_adr( wb_rf_adr ), |
.wb_rf_we( wb_rf_we ), |
.wb_rf_re( wb_rf_re ), |
.ch_sel( ch_sel ), |
.ndnr( ndnr[4] ), |
.dma_busy( dma_busy ), |
.dma_err( dma_err ), |
.dma_done( dma_done ), |
.dma_done_all( dma_done_all ), |
.de_csr( de_csr ), |
.de_txsz( de_txsz ), |
.de_adr0( de_adr0 ), |
.de_adr1( de_adr1 ), |
.de_csr_we( de_csr_we ), |
.de_txsz_we( de_txsz_we ), |
.de_adr0_we( de_adr0_we ), |
.de_adr1_we( de_adr1_we ), |
.de_fetch_descr(de_fetch_descr ), |
.dma_rest( dma_rest[4] ), |
.ptr_set( ptr_set ) |
); |
`endif |
|
|
`ifdef WDMA_HAVE_CH5 |
wb_dma_ch_rf #(5, `WDMA_HAVE_ARS5, `WDMA_HAVE_ED5, `WDMA_HAVE_CBUF5) u5( |
wb_dma_ch_rf #(5, ch5_conf[0], ch5_conf[1], ch5_conf[2], ch5_conf[3]) u5( |
.clk( clk ), |
.rst( rst ), |
.pointer( pointer5 ), |
1081,49 → 897,8
.dma_rest( dma_rest[5] ), |
.ptr_set( ptr_set ) |
); |
`else |
wb_dma_ch_rf_dummy #(5, `WDMA_HAVE_ARS5, `WDMA_HAVE_ED5, `WDMA_HAVE_CBUF5) u5( |
.clk( clk ), |
.rst( rst ), |
.pointer( pointer5 ), |
.pointer_s( pointer5_s ), |
.ch_csr( ch5_csr ), |
.ch_txsz( ch5_txsz ), |
.ch_adr0( ch5_adr0 ), |
.ch_adr1( ch5_adr1 ), |
.ch_am0( ch5_am0 ), |
.ch_am1( ch5_am1 ), |
.sw_pointer( sw_pointer5 ), |
.ch_stop( ch_stop[5] ), |
.ch_dis( ch_dis[5] ), |
.int( ch_int[5] ), |
.wb_rf_din( wb_rf_din ), |
.wb_rf_adr( wb_rf_adr ), |
.wb_rf_we( wb_rf_we ), |
.wb_rf_re( wb_rf_re ), |
.ch_sel( ch_sel ), |
.ndnr( ndnr[5] ), |
.dma_busy( dma_busy ), |
.dma_err( dma_err ), |
.dma_done( dma_done ), |
.dma_done_all( dma_done_all ), |
.de_csr( de_csr ), |
.de_txsz( de_txsz ), |
.de_adr0( de_adr0 ), |
.de_adr1( de_adr1 ), |
.de_csr_we( de_csr_we ), |
.de_txsz_we( de_txsz_we ), |
.de_adr0_we( de_adr0_we ), |
.de_adr1_we( de_adr1_we ), |
.de_fetch_descr(de_fetch_descr ), |
.dma_rest( dma_rest[5] ), |
.ptr_set( ptr_set ) |
); |
`endif |
|
|
`ifdef WDMA_HAVE_CH6 |
wb_dma_ch_rf #(6, `WDMA_HAVE_ARS6, `WDMA_HAVE_ED6, `WDMA_HAVE_CBUF6) u6( |
wb_dma_ch_rf #(6, ch6_conf[0], ch6_conf[1], ch6_conf[2], ch6_conf[3]) u6( |
.clk( clk ), |
.rst( rst ), |
.pointer( pointer6 ), |
1160,49 → 935,8
.dma_rest( dma_rest[6] ), |
.ptr_set( ptr_set ) |
); |
`else |
wb_dma_ch_rf_dummy #(6, `WDMA_HAVE_ARS6, `WDMA_HAVE_ED6, `WDMA_HAVE_CBUF6) u6( |
.clk( clk ), |
.rst( rst ), |
.pointer( pointer6 ), |
.pointer_s( pointer6_s ), |
.ch_csr( ch6_csr ), |
.ch_txsz( ch6_txsz ), |
.ch_adr0( ch6_adr0 ), |
.ch_adr1( ch6_adr1 ), |
.ch_am0( ch6_am0 ), |
.ch_am1( ch6_am1 ), |
.sw_pointer( sw_pointer6 ), |
.ch_stop( ch_stop[6] ), |
.ch_dis( ch_dis[6] ), |
.int( ch_int[6] ), |
.wb_rf_din( wb_rf_din ), |
.wb_rf_adr( wb_rf_adr ), |
.wb_rf_we( wb_rf_we ), |
.wb_rf_re( wb_rf_re ), |
.ch_sel( ch_sel ), |
.ndnr( ndnr[6] ), |
.dma_busy( dma_busy ), |
.dma_err( dma_err ), |
.dma_done( dma_done ), |
.dma_done_all( dma_done_all ), |
.de_csr( de_csr ), |
.de_txsz( de_txsz ), |
.de_adr0( de_adr0 ), |
.de_adr1( de_adr1 ), |
.de_csr_we( de_csr_we ), |
.de_txsz_we( de_txsz_we ), |
.de_adr0_we( de_adr0_we ), |
.de_adr1_we( de_adr1_we ), |
.de_fetch_descr(de_fetch_descr ), |
.dma_rest( dma_rest[6] ), |
.ptr_set( ptr_set ) |
); |
`endif |
|
|
`ifdef WDMA_HAVE_CH7 |
wb_dma_ch_rf #(7, `WDMA_HAVE_ARS7, `WDMA_HAVE_ED7, `WDMA_HAVE_CBUF7) u7( |
wb_dma_ch_rf #(7, ch7_conf[0], ch7_conf[1], ch7_conf[2], ch7_conf[3]) u7( |
.clk( clk ), |
.rst( rst ), |
.pointer( pointer7 ), |
1239,49 → 973,8
.dma_rest( dma_rest[7] ), |
.ptr_set( ptr_set ) |
); |
`else |
wb_dma_ch_rf_dummy #(7, `WDMA_HAVE_ARS7, `WDMA_HAVE_ED7, `WDMA_HAVE_CBUF7) u7( |
.clk( clk ), |
.rst( rst ), |
.pointer( pointer7 ), |
.pointer_s( pointer7_s ), |
.ch_csr( ch7_csr ), |
.ch_txsz( ch7_txsz ), |
.ch_adr0( ch7_adr0 ), |
.ch_adr1( ch7_adr1 ), |
.ch_am0( ch7_am0 ), |
.ch_am1( ch7_am1 ), |
.sw_pointer( sw_pointer7 ), |
.ch_stop( ch_stop[7] ), |
.ch_dis( ch_dis[7] ), |
.int( ch_int[7] ), |
.wb_rf_din( wb_rf_din ), |
.wb_rf_adr( wb_rf_adr ), |
.wb_rf_we( wb_rf_we ), |
.wb_rf_re( wb_rf_re ), |
.ch_sel( ch_sel ), |
.ndnr( ndnr[7] ), |
.dma_busy( dma_busy ), |
.dma_err( dma_err ), |
.dma_done( dma_done ), |
.dma_done_all( dma_done_all ), |
.de_csr( de_csr ), |
.de_txsz( de_txsz ), |
.de_adr0( de_adr0 ), |
.de_adr1( de_adr1 ), |
.de_csr_we( de_csr_we ), |
.de_txsz_we( de_txsz_we ), |
.de_adr0_we( de_adr0_we ), |
.de_adr1_we( de_adr1_we ), |
.de_fetch_descr(de_fetch_descr ), |
.dma_rest( dma_rest[7] ), |
.ptr_set( ptr_set ) |
); |
`endif |
|
|
`ifdef WDMA_HAVE_CH8 |
wb_dma_ch_rf #(8, `WDMA_HAVE_ARS8, `WDMA_HAVE_ED8, `WDMA_HAVE_CBUF8) u8( |
wb_dma_ch_rf #(8, ch8_conf[0], ch8_conf[1], ch8_conf[2], ch8_conf[3]) u8( |
.clk( clk ), |
.rst( rst ), |
.pointer( pointer8 ), |
1318,49 → 1011,8
.dma_rest( dma_rest[8] ), |
.ptr_set( ptr_set ) |
); |
`else |
wb_dma_ch_rf_dummy #(8, `WDMA_HAVE_ARS8, `WDMA_HAVE_ED8, `WDMA_HAVE_CBUF8) u8( |
.clk( clk ), |
.rst( rst ), |
.pointer( pointer8 ), |
.pointer_s( pointer8_s ), |
.ch_csr( ch8_csr ), |
.ch_txsz( ch8_txsz ), |
.ch_adr0( ch8_adr0 ), |
.ch_adr1( ch8_adr1 ), |
.ch_am0( ch8_am0 ), |
.ch_am1( ch8_am1 ), |
.sw_pointer( sw_pointer8 ), |
.ch_stop( ch_stop[8] ), |
.ch_dis( ch_dis[8] ), |
.int( ch_int[8] ), |
.wb_rf_din( wb_rf_din ), |
.wb_rf_adr( wb_rf_adr ), |
.wb_rf_we( wb_rf_we ), |
.wb_rf_re( wb_rf_re ), |
.ch_sel( ch_sel ), |
.ndnr( ndnr[8] ), |
.dma_busy( dma_busy ), |
.dma_err( dma_err ), |
.dma_done( dma_done ), |
.dma_done_all( dma_done_all ), |
.de_csr( de_csr ), |
.de_txsz( de_txsz ), |
.de_adr0( de_adr0 ), |
.de_adr1( de_adr1 ), |
.de_csr_we( de_csr_we ), |
.de_txsz_we( de_txsz_we ), |
.de_adr0_we( de_adr0_we ), |
.de_adr1_we( de_adr1_we ), |
.de_fetch_descr(de_fetch_descr ), |
.dma_rest( dma_rest[8] ), |
.ptr_set( ptr_set ) |
); |
`endif |
|
|
`ifdef WDMA_HAVE_CH9 |
wb_dma_ch_rf #(9, `WDMA_HAVE_ARS9, `WDMA_HAVE_ED9, `WDMA_HAVE_CBUF9) u9( |
wb_dma_ch_rf #(9, ch9_conf[0], ch9_conf[1], ch9_conf[2], ch9_conf[3]) u9( |
.clk( clk ), |
.rst( rst ), |
.pointer( pointer9 ), |
1397,49 → 1049,8
.dma_rest( dma_rest[9] ), |
.ptr_set( ptr_set ) |
); |
`else |
wb_dma_ch_rf_dummy #(9, `WDMA_HAVE_ARS9, `WDMA_HAVE_ED9, `WDMA_HAVE_CBUF9) u9( |
.clk( clk ), |
.rst( rst ), |
.pointer( pointer9 ), |
.pointer_s( pointer9_s ), |
.ch_csr( ch9_csr ), |
.ch_txsz( ch9_txsz ), |
.ch_adr0( ch9_adr0 ), |
.ch_adr1( ch9_adr1 ), |
.ch_am0( ch9_am0 ), |
.ch_am1( ch9_am1 ), |
.sw_pointer( sw_pointer9 ), |
.ch_stop( ch_stop[9] ), |
.ch_dis( ch_dis[9] ), |
.int( ch_int[9] ), |
.wb_rf_din( wb_rf_din ), |
.wb_rf_adr( wb_rf_adr ), |
.wb_rf_we( wb_rf_we ), |
.wb_rf_re( wb_rf_re ), |
.ch_sel( ch_sel ), |
.ndnr( ndnr[9] ), |
.dma_busy( dma_busy ), |
.dma_err( dma_err ), |
.dma_done( dma_done ), |
.dma_done_all( dma_done_all ), |
.de_csr( de_csr ), |
.de_txsz( de_txsz ), |
.de_adr0( de_adr0 ), |
.de_adr1( de_adr1 ), |
.de_csr_we( de_csr_we ), |
.de_txsz_we( de_txsz_we ), |
.de_adr0_we( de_adr0_we ), |
.de_adr1_we( de_adr1_we ), |
.de_fetch_descr(de_fetch_descr ), |
.dma_rest( dma_rest[9] ), |
.ptr_set( ptr_set ) |
); |
`endif |
|
|
`ifdef WDMA_HAVE_CH10 |
wb_dma_ch_rf #(10, `WDMA_HAVE_ARS10, `WDMA_HAVE_ED10, `WDMA_HAVE_CBUF10) u10( |
wb_dma_ch_rf #(10, ch10_conf[0], ch10_conf[1], ch10_conf[2], ch10_conf[3]) u10( |
.clk( clk ), |
.rst( rst ), |
.pointer( pointer10 ), |
1476,49 → 1087,8
.dma_rest( dma_rest[10] ), |
.ptr_set( ptr_set ) |
); |
`else |
wb_dma_ch_rf_dummy #(10, `WDMA_HAVE_ARS10, `WDMA_HAVE_ED10, `WDMA_HAVE_CBUF10) u10( |
.clk( clk ), |
.rst( rst ), |
.pointer( pointer10 ), |
.pointer_s( pointer10_s ), |
.ch_csr( ch10_csr ), |
.ch_txsz( ch10_txsz ), |
.ch_adr0( ch10_adr0 ), |
.ch_adr1( ch10_adr1 ), |
.ch_am0( ch10_am0 ), |
.ch_am1( ch10_am1 ), |
.sw_pointer( sw_pointer10 ), |
.ch_stop( ch_stop[10] ), |
.ch_dis( ch_dis[10] ), |
.int( ch_int[10] ), |
.wb_rf_din( wb_rf_din ), |
.wb_rf_adr( wb_rf_adr ), |
.wb_rf_we( wb_rf_we ), |
.wb_rf_re( wb_rf_re ), |
.ch_sel( ch_sel ), |
.ndnr( ndnr[10] ), |
.dma_busy( dma_busy ), |
.dma_err( dma_err ), |
.dma_done( dma_done ), |
.dma_done_all( dma_done_all ), |
.de_csr( de_csr ), |
.de_txsz( de_txsz ), |
.de_adr0( de_adr0 ), |
.de_adr1( de_adr1 ), |
.de_csr_we( de_csr_we ), |
.de_txsz_we( de_txsz_we ), |
.de_adr0_we( de_adr0_we ), |
.de_adr1_we( de_adr1_we ), |
.de_fetch_descr(de_fetch_descr ), |
.dma_rest( dma_rest[10] ), |
.ptr_set( ptr_set ) |
); |
`endif |
|
|
`ifdef WDMA_HAVE_CH11 |
wb_dma_ch_rf #(11, `WDMA_HAVE_ARS11, `WDMA_HAVE_ED11, `WDMA_HAVE_CBUF11) u11( |
wb_dma_ch_rf #(11, ch11_conf[0], ch11_conf[1], ch11_conf[2], ch11_conf[3]) u11( |
.clk( clk ), |
.rst( rst ), |
.pointer( pointer11 ), |
1555,49 → 1125,8
.dma_rest( dma_rest[11] ), |
.ptr_set( ptr_set ) |
); |
`else |
wb_dma_ch_rf_dummy #(11, `WDMA_HAVE_ARS11, `WDMA_HAVE_ED11, `WDMA_HAVE_CBUF11) u11( |
.clk( clk ), |
.rst( rst ), |
.pointer( pointer11 ), |
.pointer_s( pointer11_s ), |
.ch_csr( ch11_csr ), |
.ch_txsz( ch11_txsz ), |
.ch_adr0( ch11_adr0 ), |
.ch_adr1( ch11_adr1 ), |
.ch_am0( ch11_am0 ), |
.ch_am1( ch11_am1 ), |
.sw_pointer( sw_pointer11 ), |
.ch_stop( ch_stop[11] ), |
.ch_dis( ch_dis[11] ), |
.int( ch_int[11] ), |
.wb_rf_din( wb_rf_din ), |
.wb_rf_adr( wb_rf_adr ), |
.wb_rf_we( wb_rf_we ), |
.wb_rf_re( wb_rf_re ), |
.ch_sel( ch_sel ), |
.ndnr( ndnr[11] ), |
.dma_busy( dma_busy ), |
.dma_err( dma_err ), |
.dma_done( dma_done ), |
.dma_done_all( dma_done_all ), |
.de_csr( de_csr ), |
.de_txsz( de_txsz ), |
.de_adr0( de_adr0 ), |
.de_adr1( de_adr1 ), |
.de_csr_we( de_csr_we ), |
.de_txsz_we( de_txsz_we ), |
.de_adr0_we( de_adr0_we ), |
.de_adr1_we( de_adr1_we ), |
.de_fetch_descr(de_fetch_descr ), |
.dma_rest( dma_rest[11] ), |
.ptr_set( ptr_set ) |
); |
`endif |
|
|
`ifdef WDMA_HAVE_CH12 |
wb_dma_ch_rf #(12, `WDMA_HAVE_ARS12, `WDMA_HAVE_ED12, `WDMA_HAVE_CBUF12) u12( |
wb_dma_ch_rf #(12, ch12_conf[0], ch12_conf[1], ch12_conf[2], ch12_conf[3]) u12( |
.clk( clk ), |
.rst( rst ), |
.pointer( pointer12 ), |
1634,49 → 1163,8
.dma_rest( dma_rest[12] ), |
.ptr_set( ptr_set ) |
); |
`else |
wb_dma_ch_rf_dummy #(12, `WDMA_HAVE_ARS12, `WDMA_HAVE_ED12, `WDMA_HAVE_CBUF12) u12( |
.clk( clk ), |
.rst( rst ), |
.pointer( pointer12 ), |
.pointer_s( pointer12_s ), |
.ch_csr( ch12_csr ), |
.ch_txsz( ch12_txsz ), |
.ch_adr0( ch12_adr0 ), |
.ch_adr1( ch12_adr1 ), |
.ch_am0( ch12_am0 ), |
.ch_am1( ch12_am1 ), |
.sw_pointer( sw_pointer12 ), |
.ch_stop( ch_stop[12] ), |
.ch_dis( ch_dis[12] ), |
.int( ch_int[12] ), |
.wb_rf_din( wb_rf_din ), |
.wb_rf_adr( wb_rf_adr ), |
.wb_rf_we( wb_rf_we ), |
.wb_rf_re( wb_rf_re ), |
.ch_sel( ch_sel ), |
.ndnr( ndnr[12] ), |
.dma_busy( dma_busy ), |
.dma_err( dma_err ), |
.dma_done( dma_done ), |
.dma_done_all( dma_done_all ), |
.de_csr( de_csr ), |
.de_txsz( de_txsz ), |
.de_adr0( de_adr0 ), |
.de_adr1( de_adr1 ), |
.de_csr_we( de_csr_we ), |
.de_txsz_we( de_txsz_we ), |
.de_adr0_we( de_adr0_we ), |
.de_adr1_we( de_adr1_we ), |
.de_fetch_descr(de_fetch_descr ), |
.dma_rest( dma_rest[12] ), |
.ptr_set( ptr_set ) |
); |
`endif |
|
|
`ifdef WDMA_HAVE_CH13 |
wb_dma_ch_rf #(13, `WDMA_HAVE_ARS13, `WDMA_HAVE_ED13, `WDMA_HAVE_CBUF13) u13( |
wb_dma_ch_rf #(13, ch13_conf[0], ch13_conf[1], ch13_conf[2], ch13_conf[3]) u13( |
.clk( clk ), |
.rst( rst ), |
.pointer( pointer13 ), |
1713,49 → 1201,8
.dma_rest( dma_rest[13] ), |
.ptr_set( ptr_set ) |
); |
`else |
wb_dma_ch_rf_dummy #(13, `WDMA_HAVE_ARS13, `WDMA_HAVE_ED13, `WDMA_HAVE_CBUF13) u13( |
.clk( clk ), |
.rst( rst ), |
.pointer( pointer13 ), |
.pointer_s( pointer13_s ), |
.ch_csr( ch13_csr ), |
.ch_txsz( ch13_txsz ), |
.ch_adr0( ch13_adr0 ), |
.ch_adr1( ch13_adr1 ), |
.ch_am0( ch13_am0 ), |
.ch_am1( ch13_am1 ), |
.sw_pointer( sw_pointer13 ), |
.ch_stop( ch_stop[13] ), |
.ch_dis( ch_dis[13] ), |
.int( ch_int[13] ), |
.wb_rf_din( wb_rf_din ), |
.wb_rf_adr( wb_rf_adr ), |
.wb_rf_we( wb_rf_we ), |
.wb_rf_re( wb_rf_re ), |
.ch_sel( ch_sel ), |
.ndnr( ndnr[13] ), |
.dma_busy( dma_busy ), |
.dma_err( dma_err ), |
.dma_done( dma_done ), |
.dma_done_all( dma_done_all ), |
.de_csr( de_csr ), |
.de_txsz( de_txsz ), |
.de_adr0( de_adr0 ), |
.de_adr1( de_adr1 ), |
.de_csr_we( de_csr_we ), |
.de_txsz_we( de_txsz_we ), |
.de_adr0_we( de_adr0_we ), |
.de_adr1_we( de_adr1_we ), |
.de_fetch_descr(de_fetch_descr ), |
.dma_rest( dma_rest[13] ), |
.ptr_set( ptr_set ) |
); |
`endif |
|
|
`ifdef WDMA_HAVE_CH14 |
wb_dma_ch_rf #(14, `WDMA_HAVE_ARS14, `WDMA_HAVE_ED14, `WDMA_HAVE_CBUF14) u14( |
wb_dma_ch_rf #(14, ch14_conf[0], ch14_conf[1], ch14_conf[2], ch14_conf[3]) u14( |
.clk( clk ), |
.rst( rst ), |
.pointer( pointer14 ), |
1792,49 → 1239,8
.dma_rest( dma_rest[14] ), |
.ptr_set( ptr_set ) |
); |
`else |
wb_dma_ch_rf_dummy #(14, `WDMA_HAVE_ARS14, `WDMA_HAVE_ED14, `WDMA_HAVE_CBUF14) u14( |
.clk( clk ), |
.rst( rst ), |
.pointer( pointer14 ), |
.pointer_s( pointer14_s ), |
.ch_csr( ch14_csr ), |
.ch_txsz( ch14_txsz ), |
.ch_adr0( ch14_adr0 ), |
.ch_adr1( ch14_adr1 ), |
.ch_am0( ch14_am0 ), |
.ch_am1( ch14_am1 ), |
.sw_pointer( sw_pointer14 ), |
.ch_stop( ch_stop[14] ), |
.ch_dis( ch_dis[14] ), |
.int( ch_int[14] ), |
.wb_rf_din( wb_rf_din ), |
.wb_rf_adr( wb_rf_adr ), |
.wb_rf_we( wb_rf_we ), |
.wb_rf_re( wb_rf_re ), |
.ch_sel( ch_sel ), |
.ndnr( ndnr[14] ), |
.dma_busy( dma_busy ), |
.dma_err( dma_err ), |
.dma_done( dma_done ), |
.dma_done_all( dma_done_all ), |
.de_csr( de_csr ), |
.de_txsz( de_txsz ), |
.de_adr0( de_adr0 ), |
.de_adr1( de_adr1 ), |
.de_csr_we( de_csr_we ), |
.de_txsz_we( de_txsz_we ), |
.de_adr0_we( de_adr0_we ), |
.de_adr1_we( de_adr1_we ), |
.de_fetch_descr(de_fetch_descr ), |
.dma_rest( dma_rest[14] ), |
.ptr_set( ptr_set ) |
); |
`endif |
|
|
`ifdef WDMA_HAVE_CH15 |
wb_dma_ch_rf #(15, `WDMA_HAVE_ARS15, `WDMA_HAVE_ED15, `WDMA_HAVE_CBUF15) u15( |
wb_dma_ch_rf #(15, ch15_conf[0], ch15_conf[1], ch15_conf[2], ch15_conf[3]) u15( |
.clk( clk ), |
.rst( rst ), |
.pointer( pointer15 ), |
1871,49 → 1277,8
.dma_rest( dma_rest[15] ), |
.ptr_set( ptr_set ) |
); |
`else |
wb_dma_ch_rf_dummy #(15, `WDMA_HAVE_ARS15, `WDMA_HAVE_ED15, `WDMA_HAVE_CBUF15) u15( |
.clk( clk ), |
.rst( rst ), |
.pointer( pointer15 ), |
.pointer_s( pointer15_s ), |
.ch_csr( ch15_csr ), |
.ch_txsz( ch15_txsz ), |
.ch_adr0( ch15_adr0 ), |
.ch_adr1( ch15_adr1 ), |
.ch_am0( ch15_am0 ), |
.ch_am1( ch15_am1 ), |
.sw_pointer( sw_pointer15 ), |
.ch_stop( ch_stop[15] ), |
.ch_dis( ch_dis[15] ), |
.int( ch_int[15] ), |
.wb_rf_din( wb_rf_din ), |
.wb_rf_adr( wb_rf_adr ), |
.wb_rf_we( wb_rf_we ), |
.wb_rf_re( wb_rf_re ), |
.ch_sel( ch_sel ), |
.ndnr( ndnr[15] ), |
.dma_busy( dma_busy ), |
.dma_err( dma_err ), |
.dma_done( dma_done ), |
.dma_done_all( dma_done_all ), |
.de_csr( de_csr ), |
.de_txsz( de_txsz ), |
.de_adr0( de_adr0 ), |
.de_adr1( de_adr1 ), |
.de_csr_we( de_csr_we ), |
.de_txsz_we( de_txsz_we ), |
.de_adr0_we( de_adr0_we ), |
.de_adr1_we( de_adr1_we ), |
.de_fetch_descr(de_fetch_descr ), |
.dma_rest( dma_rest[15] ), |
.ptr_set( ptr_set ) |
); |
`endif |
|
|
`ifdef WDMA_HAVE_CH16 |
wb_dma_ch_rf #(16, `WDMA_HAVE_ARS16, `WDMA_HAVE_ED16, `WDMA_HAVE_CBUF16) u16( |
wb_dma_ch_rf #(16, ch16_conf[0], ch16_conf[1], ch16_conf[2], ch16_conf[3]) u16( |
.clk( clk ), |
.rst( rst ), |
.pointer( pointer16 ), |
1950,49 → 1315,8
.dma_rest( dma_rest[16] ), |
.ptr_set( ptr_set ) |
); |
`else |
wb_dma_ch_rf_dummy #(16, `WDMA_HAVE_ARS16, `WDMA_HAVE_ED16, `WDMA_HAVE_CBUF16) u16( |
.clk( clk ), |
.rst( rst ), |
.pointer( pointer16 ), |
.pointer_s( pointer16_s ), |
.ch_csr( ch16_csr ), |
.ch_txsz( ch16_txsz ), |
.ch_adr0( ch16_adr0 ), |
.ch_adr1( ch16_adr1 ), |
.ch_am0( ch16_am0 ), |
.ch_am1( ch16_am1 ), |
.sw_pointer( sw_pointer16 ), |
.ch_stop( ch_stop[16] ), |
.ch_dis( ch_dis[16] ), |
.int( ch_int[16] ), |
.wb_rf_din( wb_rf_din ), |
.wb_rf_adr( wb_rf_adr ), |
.wb_rf_we( wb_rf_we ), |
.wb_rf_re( wb_rf_re ), |
.ch_sel( ch_sel ), |
.ndnr( ndnr[16] ), |
.dma_busy( dma_busy ), |
.dma_err( dma_err ), |
.dma_done( dma_done ), |
.dma_done_all( dma_done_all ), |
.de_csr( de_csr ), |
.de_txsz( de_txsz ), |
.de_adr0( de_adr0 ), |
.de_adr1( de_adr1 ), |
.de_csr_we( de_csr_we ), |
.de_txsz_we( de_txsz_we ), |
.de_adr0_we( de_adr0_we ), |
.de_adr1_we( de_adr1_we ), |
.de_fetch_descr(de_fetch_descr ), |
.dma_rest( dma_rest[16] ), |
.ptr_set( ptr_set ) |
); |
`endif |
|
|
`ifdef WDMA_HAVE_CH17 |
wb_dma_ch_rf #(17, `WDMA_HAVE_ARS17, `WDMA_HAVE_ED17, `WDMA_HAVE_CBUF17) u17( |
wb_dma_ch_rf #(17, ch17_conf[0], ch17_conf[1], ch17_conf[2], ch17_conf[3]) u17( |
.clk( clk ), |
.rst( rst ), |
.pointer( pointer17 ), |
2029,49 → 1353,8
.dma_rest( dma_rest[17] ), |
.ptr_set( ptr_set ) |
); |
`else |
wb_dma_ch_rf_dummy #(17, `WDMA_HAVE_ARS17, `WDMA_HAVE_ED17, `WDMA_HAVE_CBUF17) u17( |
.clk( clk ), |
.rst( rst ), |
.pointer( pointer17 ), |
.pointer_s( pointer17_s ), |
.ch_csr( ch17_csr ), |
.ch_txsz( ch17_txsz ), |
.ch_adr0( ch17_adr0 ), |
.ch_adr1( ch17_adr1 ), |
.ch_am0( ch17_am0 ), |
.ch_am1( ch17_am1 ), |
.sw_pointer( sw_pointer17 ), |
.ch_stop( ch_stop[17] ), |
.ch_dis( ch_dis[17] ), |
.int( ch_int[17] ), |
.wb_rf_din( wb_rf_din ), |
.wb_rf_adr( wb_rf_adr ), |
.wb_rf_we( wb_rf_we ), |
.wb_rf_re( wb_rf_re ), |
.ch_sel( ch_sel ), |
.ndnr( ndnr[17] ), |
.dma_busy( dma_busy ), |
.dma_err( dma_err ), |
.dma_done( dma_done ), |
.dma_done_all( dma_done_all ), |
.de_csr( de_csr ), |
.de_txsz( de_txsz ), |
.de_adr0( de_adr0 ), |
.de_adr1( de_adr1 ), |
.de_csr_we( de_csr_we ), |
.de_txsz_we( de_txsz_we ), |
.de_adr0_we( de_adr0_we ), |
.de_adr1_we( de_adr1_we ), |
.de_fetch_descr(de_fetch_descr ), |
.dma_rest( dma_rest[17] ), |
.ptr_set( ptr_set ) |
); |
`endif |
|
|
`ifdef WDMA_HAVE_CH18 |
wb_dma_ch_rf #(18, `WDMA_HAVE_ARS18, `WDMA_HAVE_ED18, `WDMA_HAVE_CBUF18) u18( |
wb_dma_ch_rf #(18, ch18_conf[0], ch18_conf[1], ch18_conf[2], ch18_conf[3]) u18( |
.clk( clk ), |
.rst( rst ), |
.pointer( pointer18 ), |
2108,49 → 1391,8
.dma_rest( dma_rest[18] ), |
.ptr_set( ptr_set ) |
); |
`else |
wb_dma_ch_rf_dummy #(18, `WDMA_HAVE_ARS18, `WDMA_HAVE_ED18, `WDMA_HAVE_CBUF18) u18( |
.clk( clk ), |
.rst( rst ), |
.pointer( pointer18 ), |
.pointer_s( pointer18_s ), |
.ch_csr( ch18_csr ), |
.ch_txsz( ch18_txsz ), |
.ch_adr0( ch18_adr0 ), |
.ch_adr1( ch18_adr1 ), |
.ch_am0( ch18_am0 ), |
.ch_am1( ch18_am1 ), |
.sw_pointer( sw_pointer18 ), |
.ch_stop( ch_stop[18] ), |
.ch_dis( ch_dis[18] ), |
.int( ch_int[18] ), |
.wb_rf_din( wb_rf_din ), |
.wb_rf_adr( wb_rf_adr ), |
.wb_rf_we( wb_rf_we ), |
.wb_rf_re( wb_rf_re ), |
.ch_sel( ch_sel ), |
.ndnr( ndnr[18] ), |
.dma_busy( dma_busy ), |
.dma_err( dma_err ), |
.dma_done( dma_done ), |
.dma_done_all( dma_done_all ), |
.de_csr( de_csr ), |
.de_txsz( de_txsz ), |
.de_adr0( de_adr0 ), |
.de_adr1( de_adr1 ), |
.de_csr_we( de_csr_we ), |
.de_txsz_we( de_txsz_we ), |
.de_adr0_we( de_adr0_we ), |
.de_adr1_we( de_adr1_we ), |
.de_fetch_descr(de_fetch_descr ), |
.dma_rest( dma_rest[18] ), |
.ptr_set( ptr_set ) |
); |
`endif |
|
|
`ifdef WDMA_HAVE_CH19 |
wb_dma_ch_rf #(19, `WDMA_HAVE_ARS19, `WDMA_HAVE_ED19, `WDMA_HAVE_CBUF19) u19( |
wb_dma_ch_rf #(19, ch19_conf[0], ch19_conf[1], ch19_conf[2], ch19_conf[3]) u19( |
.clk( clk ), |
.rst( rst ), |
.pointer( pointer19 ), |
2187,49 → 1429,8
.dma_rest( dma_rest[19] ), |
.ptr_set( ptr_set ) |
); |
`else |
wb_dma_ch_rf_dummy #(19, `WDMA_HAVE_ARS19, `WDMA_HAVE_ED19, `WDMA_HAVE_CBUF19) u19( |
.clk( clk ), |
.rst( rst ), |
.pointer( pointer19 ), |
.pointer_s( pointer19_s ), |
.ch_csr( ch19_csr ), |
.ch_txsz( ch19_txsz ), |
.ch_adr0( ch19_adr0 ), |
.ch_adr1( ch19_adr1 ), |
.ch_am0( ch19_am0 ), |
.ch_am1( ch19_am1 ), |
.sw_pointer( sw_pointer19 ), |
.ch_stop( ch_stop[19] ), |
.ch_dis( ch_dis[19] ), |
.int( ch_int[19] ), |
.wb_rf_din( wb_rf_din ), |
.wb_rf_adr( wb_rf_adr ), |
.wb_rf_we( wb_rf_we ), |
.wb_rf_re( wb_rf_re ), |
.ch_sel( ch_sel ), |
.ndnr( ndnr[19] ), |
.dma_busy( dma_busy ), |
.dma_err( dma_err ), |
.dma_done( dma_done ), |
.dma_done_all( dma_done_all ), |
.de_csr( de_csr ), |
.de_txsz( de_txsz ), |
.de_adr0( de_adr0 ), |
.de_adr1( de_adr1 ), |
.de_csr_we( de_csr_we ), |
.de_txsz_we( de_txsz_we ), |
.de_adr0_we( de_adr0_we ), |
.de_adr1_we( de_adr1_we ), |
.de_fetch_descr(de_fetch_descr ), |
.dma_rest( dma_rest[19] ), |
.ptr_set( ptr_set ) |
); |
`endif |
|
|
`ifdef WDMA_HAVE_CH20 |
wb_dma_ch_rf #(20, `WDMA_HAVE_ARS20, `WDMA_HAVE_ED20, `WDMA_HAVE_CBUF20) u20( |
wb_dma_ch_rf #(20, ch20_conf[0], ch20_conf[1], ch20_conf[2], ch20_conf[3]) u20( |
.clk( clk ), |
.rst( rst ), |
.pointer( pointer20 ), |
2266,49 → 1467,8
.dma_rest( dma_rest[20] ), |
.ptr_set( ptr_set ) |
); |
`else |
wb_dma_ch_rf_dummy #(20, `WDMA_HAVE_ARS20, `WDMA_HAVE_ED20, `WDMA_HAVE_CBUF20) u20( |
.clk( clk ), |
.rst( rst ), |
.pointer( pointer20 ), |
.pointer_s( pointer20_s ), |
.ch_csr( ch20_csr ), |
.ch_txsz( ch20_txsz ), |
.ch_adr0( ch20_adr0 ), |
.ch_adr1( ch20_adr1 ), |
.ch_am0( ch20_am0 ), |
.ch_am1( ch20_am1 ), |
.sw_pointer( sw_pointer20 ), |
.ch_stop( ch_stop[20] ), |
.ch_dis( ch_dis[20] ), |
.int( ch_int[20] ), |
.wb_rf_din( wb_rf_din ), |
.wb_rf_adr( wb_rf_adr ), |
.wb_rf_we( wb_rf_we ), |
.wb_rf_re( wb_rf_re ), |
.ch_sel( ch_sel ), |
.ndnr( ndnr[20] ), |
.dma_busy( dma_busy ), |
.dma_err( dma_err ), |
.dma_done( dma_done ), |
.dma_done_all( dma_done_all ), |
.de_csr( de_csr ), |
.de_txsz( de_txsz ), |
.de_adr0( de_adr0 ), |
.de_adr1( de_adr1 ), |
.de_csr_we( de_csr_we ), |
.de_txsz_we( de_txsz_we ), |
.de_adr0_we( de_adr0_we ), |
.de_adr1_we( de_adr1_we ), |
.de_fetch_descr(de_fetch_descr ), |
.dma_rest( dma_rest[20] ), |
.ptr_set( ptr_set ) |
); |
`endif |
|
|
`ifdef WDMA_HAVE_CH21 |
wb_dma_ch_rf #(21, `WDMA_HAVE_ARS21, `WDMA_HAVE_ED21, `WDMA_HAVE_CBUF21) u21( |
wb_dma_ch_rf #(21, ch21_conf[0], ch21_conf[1], ch21_conf[2], ch21_conf[3]) u21( |
.clk( clk ), |
.rst( rst ), |
.pointer( pointer21 ), |
2345,49 → 1505,8
.dma_rest( dma_rest[21] ), |
.ptr_set( ptr_set ) |
); |
`else |
wb_dma_ch_rf_dummy #(21, `WDMA_HAVE_ARS21, `WDMA_HAVE_ED21, `WDMA_HAVE_CBUF21) u21( |
.clk( clk ), |
.rst( rst ), |
.pointer( pointer21 ), |
.pointer_s( pointer21_s ), |
.ch_csr( ch21_csr ), |
.ch_txsz( ch21_txsz ), |
.ch_adr0( ch21_adr0 ), |
.ch_adr1( ch21_adr1 ), |
.ch_am0( ch21_am0 ), |
.ch_am1( ch21_am1 ), |
.sw_pointer( sw_pointer21 ), |
.ch_stop( ch_stop[21] ), |
.ch_dis( ch_dis[21] ), |
.int( ch_int[21] ), |
.wb_rf_din( wb_rf_din ), |
.wb_rf_adr( wb_rf_adr ), |
.wb_rf_we( wb_rf_we ), |
.wb_rf_re( wb_rf_re ), |
.ch_sel( ch_sel ), |
.ndnr( ndnr[21] ), |
.dma_busy( dma_busy ), |
.dma_err( dma_err ), |
.dma_done( dma_done ), |
.dma_done_all( dma_done_all ), |
.de_csr( de_csr ), |
.de_txsz( de_txsz ), |
.de_adr0( de_adr0 ), |
.de_adr1( de_adr1 ), |
.de_csr_we( de_csr_we ), |
.de_txsz_we( de_txsz_we ), |
.de_adr0_we( de_adr0_we ), |
.de_adr1_we( de_adr1_we ), |
.de_fetch_descr(de_fetch_descr ), |
.dma_rest( dma_rest[21] ), |
.ptr_set( ptr_set ) |
); |
`endif |
|
|
`ifdef WDMA_HAVE_CH22 |
wb_dma_ch_rf #(22, `WDMA_HAVE_ARS22, `WDMA_HAVE_ED22, `WDMA_HAVE_CBUF22) u22( |
wb_dma_ch_rf #(22, ch22_conf[0], ch22_conf[1], ch22_conf[2], ch22_conf[3]) u22( |
.clk( clk ), |
.rst( rst ), |
.pointer( pointer22 ), |
2424,49 → 1543,8
.dma_rest( dma_rest[22] ), |
.ptr_set( ptr_set ) |
); |
`else |
wb_dma_ch_rf_dummy #(22, `WDMA_HAVE_ARS22, `WDMA_HAVE_ED22, `WDMA_HAVE_CBUF22) u22( |
.clk( clk ), |
.rst( rst ), |
.pointer( pointer22 ), |
.pointer_s( pointer22_s ), |
.ch_csr( ch22_csr ), |
.ch_txsz( ch22_txsz ), |
.ch_adr0( ch22_adr0 ), |
.ch_adr1( ch22_adr1 ), |
.ch_am0( ch22_am0 ), |
.ch_am1( ch22_am1 ), |
.sw_pointer( sw_pointer22 ), |
.ch_stop( ch_stop[22] ), |
.ch_dis( ch_dis[22] ), |
.int( ch_int[22] ), |
.wb_rf_din( wb_rf_din ), |
.wb_rf_adr( wb_rf_adr ), |
.wb_rf_we( wb_rf_we ), |
.wb_rf_re( wb_rf_re ), |
.ch_sel( ch_sel ), |
.ndnr( ndnr[22] ), |
.dma_busy( dma_busy ), |
.dma_err( dma_err ), |
.dma_done( dma_done ), |
.dma_done_all( dma_done_all ), |
.de_csr( de_csr ), |
.de_txsz( de_txsz ), |
.de_adr0( de_adr0 ), |
.de_adr1( de_adr1 ), |
.de_csr_we( de_csr_we ), |
.de_txsz_we( de_txsz_we ), |
.de_adr0_we( de_adr0_we ), |
.de_adr1_we( de_adr1_we ), |
.de_fetch_descr(de_fetch_descr ), |
.dma_rest( dma_rest[22] ), |
.ptr_set( ptr_set ) |
); |
`endif |
|
|
`ifdef WDMA_HAVE_CH23 |
wb_dma_ch_rf #(23, `WDMA_HAVE_ARS23, `WDMA_HAVE_ED23, `WDMA_HAVE_CBUF23) u23( |
wb_dma_ch_rf #(23, ch23_conf[0], ch23_conf[1], ch23_conf[2], ch23_conf[3]) u23( |
.clk( clk ), |
.rst( rst ), |
.pointer( pointer23 ), |
2503,49 → 1581,8
.dma_rest( dma_rest[23] ), |
.ptr_set( ptr_set ) |
); |
`else |
wb_dma_ch_rf_dummy #(23, `WDMA_HAVE_ARS23, `WDMA_HAVE_ED23, `WDMA_HAVE_CBUF23) u23( |
.clk( clk ), |
.rst( rst ), |
.pointer( pointer23 ), |
.pointer_s( pointer23_s ), |
.ch_csr( ch23_csr ), |
.ch_txsz( ch23_txsz ), |
.ch_adr0( ch23_adr0 ), |
.ch_adr1( ch23_adr1 ), |
.ch_am0( ch23_am0 ), |
.ch_am1( ch23_am1 ), |
.sw_pointer( sw_pointer23 ), |
.ch_stop( ch_stop[23] ), |
.ch_dis( ch_dis[23] ), |
.int( ch_int[23] ), |
.wb_rf_din( wb_rf_din ), |
.wb_rf_adr( wb_rf_adr ), |
.wb_rf_we( wb_rf_we ), |
.wb_rf_re( wb_rf_re ), |
.ch_sel( ch_sel ), |
.ndnr( ndnr[23] ), |
.dma_busy( dma_busy ), |
.dma_err( dma_err ), |
.dma_done( dma_done ), |
.dma_done_all( dma_done_all ), |
.de_csr( de_csr ), |
.de_txsz( de_txsz ), |
.de_adr0( de_adr0 ), |
.de_adr1( de_adr1 ), |
.de_csr_we( de_csr_we ), |
.de_txsz_we( de_txsz_we ), |
.de_adr0_we( de_adr0_we ), |
.de_adr1_we( de_adr1_we ), |
.de_fetch_descr(de_fetch_descr ), |
.dma_rest( dma_rest[23] ), |
.ptr_set( ptr_set ) |
); |
`endif |
|
|
`ifdef WDMA_HAVE_CH24 |
wb_dma_ch_rf #(24, `WDMA_HAVE_ARS24, `WDMA_HAVE_ED24, `WDMA_HAVE_CBUF24) u24( |
wb_dma_ch_rf #(24, ch24_conf[0], ch24_conf[1], ch24_conf[2], ch24_conf[3]) u24( |
.clk( clk ), |
.rst( rst ), |
.pointer( pointer24 ), |
2582,49 → 1619,8
.dma_rest( dma_rest[24] ), |
.ptr_set( ptr_set ) |
); |
`else |
wb_dma_ch_rf_dummy #(24, `WDMA_HAVE_ARS24, `WDMA_HAVE_ED24, `WDMA_HAVE_CBUF24) u24( |
.clk( clk ), |
.rst( rst ), |
.pointer( pointer24 ), |
.pointer_s( pointer24_s ), |
.ch_csr( ch24_csr ), |
.ch_txsz( ch24_txsz ), |
.ch_adr0( ch24_adr0 ), |
.ch_adr1( ch24_adr1 ), |
.ch_am0( ch24_am0 ), |
.ch_am1( ch24_am1 ), |
.sw_pointer( sw_pointer24 ), |
.ch_stop( ch_stop[24] ), |
.ch_dis( ch_dis[24] ), |
.int( ch_int[24] ), |
.wb_rf_din( wb_rf_din ), |
.wb_rf_adr( wb_rf_adr ), |
.wb_rf_we( wb_rf_we ), |
.wb_rf_re( wb_rf_re ), |
.ch_sel( ch_sel ), |
.ndnr( ndnr[24] ), |
.dma_busy( dma_busy ), |
.dma_err( dma_err ), |
.dma_done( dma_done ), |
.dma_done_all( dma_done_all ), |
.de_csr( de_csr ), |
.de_txsz( de_txsz ), |
.de_adr0( de_adr0 ), |
.de_adr1( de_adr1 ), |
.de_csr_we( de_csr_we ), |
.de_txsz_we( de_txsz_we ), |
.de_adr0_we( de_adr0_we ), |
.de_adr1_we( de_adr1_we ), |
.de_fetch_descr(de_fetch_descr ), |
.dma_rest( dma_rest[24] ), |
.ptr_set( ptr_set ) |
); |
`endif |
|
|
`ifdef WDMA_HAVE_CH25 |
wb_dma_ch_rf #(25, `WDMA_HAVE_ARS25, `WDMA_HAVE_ED25, `WDMA_HAVE_CBUF25) u25( |
wb_dma_ch_rf #(25, ch25_conf[0], ch25_conf[1], ch25_conf[2], ch25_conf[3]) u25( |
.clk( clk ), |
.rst( rst ), |
.pointer( pointer25 ), |
2661,49 → 1657,8
.dma_rest( dma_rest[25] ), |
.ptr_set( ptr_set ) |
); |
`else |
wb_dma_ch_rf_dummy #(25, `WDMA_HAVE_ARS25, `WDMA_HAVE_ED25, `WDMA_HAVE_CBUF25) u25( |
.clk( clk ), |
.rst( rst ), |
.pointer( pointer25 ), |
.pointer_s( pointer25_s ), |
.ch_csr( ch25_csr ), |
.ch_txsz( ch25_txsz ), |
.ch_adr0( ch25_adr0 ), |
.ch_adr1( ch25_adr1 ), |
.ch_am0( ch25_am0 ), |
.ch_am1( ch25_am1 ), |
.sw_pointer( sw_pointer25 ), |
.ch_stop( ch_stop[25] ), |
.ch_dis( ch_dis[25] ), |
.int( ch_int[25] ), |
.wb_rf_din( wb_rf_din ), |
.wb_rf_adr( wb_rf_adr ), |
.wb_rf_we( wb_rf_we ), |
.wb_rf_re( wb_rf_re ), |
.ch_sel( ch_sel ), |
.ndnr( ndnr[25] ), |
.dma_busy( dma_busy ), |
.dma_err( dma_err ), |
.dma_done( dma_done ), |
.dma_done_all( dma_done_all ), |
.de_csr( de_csr ), |
.de_txsz( de_txsz ), |
.de_adr0( de_adr0 ), |
.de_adr1( de_adr1 ), |
.de_csr_we( de_csr_we ), |
.de_txsz_we( de_txsz_we ), |
.de_adr0_we( de_adr0_we ), |
.de_adr1_we( de_adr1_we ), |
.de_fetch_descr(de_fetch_descr ), |
.dma_rest( dma_rest[25] ), |
.ptr_set( ptr_set ) |
); |
`endif |
|
|
`ifdef WDMA_HAVE_CH26 |
wb_dma_ch_rf #(26, `WDMA_HAVE_ARS26, `WDMA_HAVE_ED26, `WDMA_HAVE_CBUF26) u26( |
wb_dma_ch_rf #(26, ch26_conf[0], ch26_conf[1], ch26_conf[2], ch26_conf[3]) u26( |
.clk( clk ), |
.rst( rst ), |
.pointer( pointer26 ), |
2740,49 → 1695,8
.dma_rest( dma_rest[26] ), |
.ptr_set( ptr_set ) |
); |
`else |
wb_dma_ch_rf_dummy #(26, `WDMA_HAVE_ARS26, `WDMA_HAVE_ED26, `WDMA_HAVE_CBUF26) u26( |
.clk( clk ), |
.rst( rst ), |
.pointer( pointer26 ), |
.pointer_s( pointer26_s ), |
.ch_csr( ch26_csr ), |
.ch_txsz( ch26_txsz ), |
.ch_adr0( ch26_adr0 ), |
.ch_adr1( ch26_adr1 ), |
.ch_am0( ch26_am0 ), |
.ch_am1( ch26_am1 ), |
.sw_pointer( sw_pointer26 ), |
.ch_stop( ch_stop[26] ), |
.ch_dis( ch_dis[26] ), |
.int( ch_int[26] ), |
.wb_rf_din( wb_rf_din ), |
.wb_rf_adr( wb_rf_adr ), |
.wb_rf_we( wb_rf_we ), |
.wb_rf_re( wb_rf_re ), |
.ch_sel( ch_sel ), |
.ndnr( ndnr[26] ), |
.dma_busy( dma_busy ), |
.dma_err( dma_err ), |
.dma_done( dma_done ), |
.dma_done_all( dma_done_all ), |
.de_csr( de_csr ), |
.de_txsz( de_txsz ), |
.de_adr0( de_adr0 ), |
.de_adr1( de_adr1 ), |
.de_csr_we( de_csr_we ), |
.de_txsz_we( de_txsz_we ), |
.de_adr0_we( de_adr0_we ), |
.de_adr1_we( de_adr1_we ), |
.de_fetch_descr(de_fetch_descr ), |
.dma_rest( dma_rest[26] ), |
.ptr_set( ptr_set ) |
); |
`endif |
|
|
`ifdef WDMA_HAVE_CH27 |
wb_dma_ch_rf #(27, `WDMA_HAVE_ARS27, `WDMA_HAVE_ED27, `WDMA_HAVE_CBUF27) u27( |
wb_dma_ch_rf #(27, ch27_conf[0], ch27_conf[1], ch27_conf[2], ch27_conf[3]) u27( |
.clk( clk ), |
.rst( rst ), |
.pointer( pointer27 ), |
2819,49 → 1733,8
.dma_rest( dma_rest[27] ), |
.ptr_set( ptr_set ) |
); |
`else |
wb_dma_ch_rf_dummy #(27, `WDMA_HAVE_ARS27, `WDMA_HAVE_ED27, `WDMA_HAVE_CBUF27) u27( |
.clk( clk ), |
.rst( rst ), |
.pointer( pointer27 ), |
.pointer_s( pointer27_s ), |
.ch_csr( ch27_csr ), |
.ch_txsz( ch27_txsz ), |
.ch_adr0( ch27_adr0 ), |
.ch_adr1( ch27_adr1 ), |
.ch_am0( ch27_am0 ), |
.ch_am1( ch27_am1 ), |
.sw_pointer( sw_pointer27 ), |
.ch_stop( ch_stop[27] ), |
.ch_dis( ch_dis[27] ), |
.int( ch_int[27] ), |
.wb_rf_din( wb_rf_din ), |
.wb_rf_adr( wb_rf_adr ), |
.wb_rf_we( wb_rf_we ), |
.wb_rf_re( wb_rf_re ), |
.ch_sel( ch_sel ), |
.ndnr( ndnr[27] ), |
.dma_busy( dma_busy ), |
.dma_err( dma_err ), |
.dma_done( dma_done ), |
.dma_done_all( dma_done_all ), |
.de_csr( de_csr ), |
.de_txsz( de_txsz ), |
.de_adr0( de_adr0 ), |
.de_adr1( de_adr1 ), |
.de_csr_we( de_csr_we ), |
.de_txsz_we( de_txsz_we ), |
.de_adr0_we( de_adr0_we ), |
.de_adr1_we( de_adr1_we ), |
.de_fetch_descr(de_fetch_descr ), |
.dma_rest( dma_rest[27] ), |
.ptr_set( ptr_set ) |
); |
`endif |
|
|
`ifdef WDMA_HAVE_CH28 |
wb_dma_ch_rf #(28, `WDMA_HAVE_ARS28, `WDMA_HAVE_ED28, `WDMA_HAVE_CBUF28) u28( |
wb_dma_ch_rf #(28, ch28_conf[0], ch28_conf[1], ch28_conf[2], ch28_conf[3]) u28( |
.clk( clk ), |
.rst( rst ), |
.pointer( pointer28 ), |
2898,49 → 1771,8
.dma_rest( dma_rest[28] ), |
.ptr_set( ptr_set ) |
); |
`else |
wb_dma_ch_rf_dummy #(28, `WDMA_HAVE_ARS28, `WDMA_HAVE_ED28, `WDMA_HAVE_CBUF28) u28( |
.clk( clk ), |
.rst( rst ), |
.pointer( pointer28 ), |
.pointer_s( pointer28_s ), |
.ch_csr( ch28_csr ), |
.ch_txsz( ch28_txsz ), |
.ch_adr0( ch28_adr0 ), |
.ch_adr1( ch28_adr1 ), |
.ch_am0( ch28_am0 ), |
.ch_am1( ch28_am1 ), |
.sw_pointer( sw_pointer28 ), |
.ch_stop( ch_stop[28] ), |
.ch_dis( ch_dis[28] ), |
.int( ch_int[28] ), |
.wb_rf_din( wb_rf_din ), |
.wb_rf_adr( wb_rf_adr ), |
.wb_rf_we( wb_rf_we ), |
.wb_rf_re( wb_rf_re ), |
.ch_sel( ch_sel ), |
.ndnr( ndnr[28] ), |
.dma_busy( dma_busy ), |
.dma_err( dma_err ), |
.dma_done( dma_done ), |
.dma_done_all( dma_done_all ), |
.de_csr( de_csr ), |
.de_txsz( de_txsz ), |
.de_adr0( de_adr0 ), |
.de_adr1( de_adr1 ), |
.de_csr_we( de_csr_we ), |
.de_txsz_we( de_txsz_we ), |
.de_adr0_we( de_adr0_we ), |
.de_adr1_we( de_adr1_we ), |
.de_fetch_descr(de_fetch_descr ), |
.dma_rest( dma_rest[28] ), |
.ptr_set( ptr_set ) |
); |
`endif |
|
|
`ifdef WDMA_HAVE_CH29 |
wb_dma_ch_rf #(29, `WDMA_HAVE_ARS29, `WDMA_HAVE_ED29, `WDMA_HAVE_CBUF29) u29( |
wb_dma_ch_rf #(29, ch29_conf[0], ch29_conf[1], ch29_conf[2], ch29_conf[3]) u29( |
.clk( clk ), |
.rst( rst ), |
.pointer( pointer29 ), |
2977,49 → 1809,8
.dma_rest( dma_rest[29] ), |
.ptr_set( ptr_set ) |
); |
`else |
wb_dma_ch_rf_dummy #(29, `WDMA_HAVE_ARS29, `WDMA_HAVE_ED29, `WDMA_HAVE_CBUF29) u29( |
.clk( clk ), |
.rst( rst ), |
.pointer( pointer29 ), |
.pointer_s( pointer29_s ), |
.ch_csr( ch29_csr ), |
.ch_txsz( ch29_txsz ), |
.ch_adr0( ch29_adr0 ), |
.ch_adr1( ch29_adr1 ), |
.ch_am0( ch29_am0 ), |
.ch_am1( ch29_am1 ), |
.sw_pointer( sw_pointer29 ), |
.ch_stop( ch_stop[29] ), |
.ch_dis( ch_dis[29] ), |
.int( ch_int[29] ), |
.wb_rf_din( wb_rf_din ), |
.wb_rf_adr( wb_rf_adr ), |
.wb_rf_we( wb_rf_we ), |
.wb_rf_re( wb_rf_re ), |
.ch_sel( ch_sel ), |
.ndnr( ndnr[29] ), |
.dma_busy( dma_busy ), |
.dma_err( dma_err ), |
.dma_done( dma_done ), |
.dma_done_all( dma_done_all ), |
.de_csr( de_csr ), |
.de_txsz( de_txsz ), |
.de_adr0( de_adr0 ), |
.de_adr1( de_adr1 ), |
.de_csr_we( de_csr_we ), |
.de_txsz_we( de_txsz_we ), |
.de_adr0_we( de_adr0_we ), |
.de_adr1_we( de_adr1_we ), |
.de_fetch_descr(de_fetch_descr ), |
.dma_rest( dma_rest[29] ), |
.ptr_set( ptr_set ) |
); |
`endif |
|
|
`ifdef WDMA_HAVE_CH30 |
wb_dma_ch_rf #(30, `WDMA_HAVE_ARS30, `WDMA_HAVE_ED30, `WDMA_HAVE_CBUF30) u30( |
wb_dma_ch_rf #(30, ch30_conf[0], ch30_conf[1], ch30_conf[2], ch30_conf[3]) u30( |
.clk( clk ), |
.rst( rst ), |
.pointer( pointer30 ), |
3056,44 → 1847,5
.dma_rest( dma_rest[30] ), |
.ptr_set( ptr_set ) |
); |
`else |
wb_dma_ch_rf_dummy #(30, `WDMA_HAVE_ARS30, `WDMA_HAVE_ED30, `WDMA_HAVE_CBUF30) u30( |
.clk( clk ), |
.rst( rst ), |
.pointer( pointer30 ), |
.pointer_s( pointer30_s ), |
.ch_csr( ch30_csr ), |
.ch_txsz( ch30_txsz ), |
.ch_adr0( ch30_adr0 ), |
.ch_adr1( ch30_adr1 ), |
.ch_am0( ch30_am0 ), |
.ch_am1( ch30_am1 ), |
.sw_pointer( sw_pointer30 ), |
.ch_stop( ch_stop[30] ), |
.ch_dis( ch_dis[30] ), |
.int( ch_int[30] ), |
.wb_rf_din( wb_rf_din ), |
.wb_rf_adr( wb_rf_adr ), |
.wb_rf_we( wb_rf_we ), |
.wb_rf_re( wb_rf_re ), |
.ch_sel( ch_sel ), |
.ndnr( ndnr[30] ), |
.dma_busy( dma_busy ), |
.dma_err( dma_err ), |
.dma_done( dma_done ), |
.dma_done_all( dma_done_all ), |
.de_csr( de_csr ), |
.de_txsz( de_txsz ), |
.de_adr0( de_adr0 ), |
.de_adr1( de_adr1 ), |
.de_csr_we( de_csr_we ), |
.de_txsz_we( de_txsz_we ), |
.de_adr0_we( de_adr0_we ), |
.de_adr1_we( de_adr1_we ), |
.de_fetch_descr(de_fetch_descr ), |
.dma_rest( dma_rest[30] ), |
.ptr_set( ptr_set ) |
); |
`endif |
|
endmodule |
/trunk/rtl/verilog/wb_dma_pri_enc_sub.v
37,10 → 37,10
|
// CVS Log |
// |
// $Id: wb_dma_pri_enc_sub.v,v 1.2 2001-08-15 05:40:30 rudi Exp $ |
// $Id: wb_dma_pri_enc_sub.v,v 1.3 2001-10-19 04:35:04 rudi Exp $ |
// |
// $Date: 2001-08-15 05:40:30 $ |
// $Revision: 1.2 $ |
// $Date: 2001-10-19 04:35:04 $ |
// $Revision: 1.3 $ |
// $Author: rudi $ |
// $Locker: $ |
// $State: Exp $ |
47,6 → 47,12
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.2 2001/08/15 05:40:30 rudi |
// |
// - Changed IO names to be more clear. |
// - Uniquifyed define names to be core specific. |
// - Added Section 3.10, describing DMA restart. |
// |
// Revision 1.1 2001/08/07 08:00:43 rudi |
// |
// |
66,49 → 72,66
// the valid bit in consideration |
|
module wb_dma_pri_enc_sub(valid, pri_in, pri_out); |
|
parameter [3:0] ch_conf = 4'b0000; |
parameter [1:0] pri_sel = 2'd0; |
|
input valid; |
input [2:0] pri_in; |
output [7:0] pri_out; |
|
reg [7:0] pri_out; |
wire [7:0] pri_out; |
reg [7:0] pri_out_d; |
reg [7:0] pri_out_d0; |
reg [7:0] pri_out_d1; |
reg [7:0] pri_out_d2; |
|
`ifdef WDMA_PRI_8 |
assign pri_out = ch_conf[0] ? pri_out_d : 8'h0; |
|
// Select Configured Priority |
always @(pri_sel or pri_out_d0 or pri_out_d1 or pri_out_d2) |
case(pri_sel) // synopsys parallel_case full_case |
2'd0: pri_out_d = pri_out_d0; |
2'd1: pri_out_d = pri_out_d1; |
2'd2: pri_out_d = pri_out_d2; |
endcase |
|
// 8 Priority Levels |
always @(valid or pri_in) |
if(!valid) pri_out = 8'b0000_0001; |
if(!valid) pri_out_d2 = 8'b0000_0001; |
else |
if(pri_in==3'h0) pri_out = 8'b0000_0001; |
if(pri_in==3'h0) pri_out_d2 = 8'b0000_0001; |
else |
if(pri_in==3'h1) pri_out = 8'b0000_0010; |
if(pri_in==3'h1) pri_out_d2 = 8'b0000_0010; |
else |
if(pri_in==3'h2) pri_out = 8'b0000_0100; |
if(pri_in==3'h2) pri_out_d2 = 8'b0000_0100; |
else |
if(pri_in==3'h3) pri_out = 8'b0000_1000; |
if(pri_in==3'h3) pri_out_d2 = 8'b0000_1000; |
else |
if(pri_in==3'h4) pri_out = 8'b0001_0000; |
if(pri_in==3'h4) pri_out_d2 = 8'b0001_0000; |
else |
if(pri_in==3'h5) pri_out = 8'b0010_0000; |
if(pri_in==3'h5) pri_out_d2 = 8'b0010_0000; |
else |
if(pri_in==3'h6) pri_out = 8'b0100_0000; |
else pri_out = 8'b1000_0000; |
`else |
`ifdef WDMA_PRI_4 |
if(pri_in==3'h6) pri_out_d2 = 8'b0100_0000; |
else pri_out_d2 = 8'b1000_0000; |
|
// 4 Priority Levels |
always @(valid or pri_in) |
if(!valid) pri_out = 8'b0000_0001; |
if(!valid) pri_out_d1 = 8'b0000_0001; |
else |
if(pri_in==3'h0) pri_out = 8'b0000_0001; |
if(pri_in==3'h0) pri_out_d1 = 8'b0000_0001; |
else |
if(pri_in==3'h1) pri_out = 8'b0000_0010; |
if(pri_in==3'h1) pri_out_d1 = 8'b0000_0010; |
else |
if(pri_in==3'h2) pri_out = 8'b0000_0100; |
else pri_out = 8'b0000_1000; |
`else |
if(pri_in==3'h2) pri_out_d1 = 8'b0000_0100; |
else pri_out_d1 = 8'b0000_1000; |
|
// 2 Priority Levels |
always @(valid or pri_in) |
if(!valid) pri_out = 8'b0000_0001; |
if(!valid) pri_out_d0 = 8'b0000_0001; |
else |
if(pri_in==3'h0) pri_out = 8'b0000_0001; |
else pri_out = 8'b0000_0010; |
`endif |
`endif |
if(pri_in==3'h0) pri_out_d0 = 8'b0000_0001; |
else pri_out_d0 = 8'b0000_0010; |
|
endmodule |
|
/trunk/rtl/verilog/wb_dma_ch_pri_enc.v
37,10 → 37,10
|
// CVS Log |
// |
// $Id: wb_dma_ch_pri_enc.v,v 1.3 2001-08-15 05:40:30 rudi Exp $ |
// $Id: wb_dma_ch_pri_enc.v,v 1.4 2001-10-19 04:35:04 rudi Exp $ |
// |
// $Date: 2001-08-15 05:40:30 $ |
// $Revision: 1.3 $ |
// $Date: 2001-10-19 04:35:04 $ |
// $Revision: 1.4 $ |
// $Author: rudi $ |
// $Locker: $ |
// $State: Exp $ |
47,6 → 47,12
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.3 2001/08/15 05:40:30 rudi |
// |
// - Changed IO names to be more clear. |
// - Uniquifyed define names to be core specific. |
// - Added Section 3.10, describing DMA restart. |
// |
// Revision 1.2 2001/08/07 08:00:43 rudi |
// |
// |
91,6 → 97,50
pri28, pri29, pri30, |
pri_out); |
|
//////////////////////////////////////////////////////////////////// |
// |
// Module Parameters |
// |
|
// chXX_conf = { CBUF, ED, ARS, EN } |
parameter [1:0] pri_sel = 2'd0; |
parameter [3:0] ch0_conf = 4'h1; |
parameter [3:0] ch1_conf = 4'h0; |
parameter [3:0] ch2_conf = 4'h0; |
parameter [3:0] ch3_conf = 4'h0; |
parameter [3:0] ch4_conf = 4'h0; |
parameter [3:0] ch5_conf = 4'h0; |
parameter [3:0] ch6_conf = 4'h0; |
parameter [3:0] ch7_conf = 4'h0; |
parameter [3:0] ch8_conf = 4'h0; |
parameter [3:0] ch9_conf = 4'h0; |
parameter [3:0] ch10_conf = 4'h0; |
parameter [3:0] ch11_conf = 4'h0; |
parameter [3:0] ch12_conf = 4'h0; |
parameter [3:0] ch13_conf = 4'h0; |
parameter [3:0] ch14_conf = 4'h0; |
parameter [3:0] ch15_conf = 4'h0; |
parameter [3:0] ch16_conf = 4'h0; |
parameter [3:0] ch17_conf = 4'h0; |
parameter [3:0] ch18_conf = 4'h0; |
parameter [3:0] ch19_conf = 4'h0; |
parameter [3:0] ch20_conf = 4'h0; |
parameter [3:0] ch21_conf = 4'h0; |
parameter [3:0] ch22_conf = 4'h0; |
parameter [3:0] ch23_conf = 4'h0; |
parameter [3:0] ch24_conf = 4'h0; |
parameter [3:0] ch25_conf = 4'h0; |
parameter [3:0] ch26_conf = 4'h0; |
parameter [3:0] ch27_conf = 4'h0; |
parameter [3:0] ch28_conf = 4'h0; |
parameter [3:0] ch29_conf = 4'h0; |
parameter [3:0] ch30_conf = 4'h0; |
|
//////////////////////////////////////////////////////////////////// |
// |
// Module IOs |
// |
|
input clk; |
input [30:0] valid; // Channel Valid bits |
input [2:0] pri0, pri1, pri2, pri3; // Channel Priorities |
114,313 → 164,165
|
wire [7:0] pri_out_tmp; |
reg [2:0] pri_out; |
reg [2:0] pri_out2; |
reg [2:0] pri_out1; |
reg [2:0] pri_out0; |
|
`ifdef WDMA_HAVE_CH1 |
wb_dma_pri_enc_sub u0( |
wb_dma_pri_enc_sub #(ch1_conf,pri_sel) u0( // Use channel config 1 for channel 0 encoder |
.valid( valid[0] ), |
.pri_in( pri0 ), |
.pri_out( pri0_out ) |
); |
|
wb_dma_pri_enc_sub u1( |
wb_dma_pri_enc_sub #(ch1_conf,pri_sel) u1( |
.valid( valid[1] ), |
.pri_in( pri1 ), |
.pri_out( pri1_out ) |
); |
`else |
assign pri0_out = 0; |
assign pri1_out = 0; |
`endif |
|
`ifdef WDMA_HAVE_CH2 |
wb_dma_pri_enc_sub u2( |
wb_dma_pri_enc_sub #(ch2_conf,pri_sel) u2( |
.valid( valid[2] ), |
.pri_in( pri2 ), |
.pri_out( pri2_out ) |
); |
`else |
assign pri2_out = 0; |
`endif |
|
`ifdef WDMA_HAVE_CH3 |
wb_dma_pri_enc_sub u3( |
wb_dma_pri_enc_sub #(ch3_conf,pri_sel) u3( |
.valid( valid[3] ), |
.pri_in( pri3 ), |
.pri_out( pri3_out ) |
); |
`else |
assign pri3_out = 0; |
`endif |
|
`ifdef WDMA_HAVE_CH4 |
wb_dma_pri_enc_sub u4( |
wb_dma_pri_enc_sub #(ch4_conf,pri_sel) u4( |
.valid( valid[4] ), |
.pri_in( pri4 ), |
.pri_out( pri4_out ) |
); |
`else |
assign pri4_out = 0; |
`endif |
|
`ifdef WDMA_HAVE_CH5 |
wb_dma_pri_enc_sub u5( |
wb_dma_pri_enc_sub #(ch5_conf,pri_sel) u5( |
.valid( valid[5] ), |
.pri_in( pri5 ), |
.pri_out( pri5_out ) |
); |
`else |
assign pri5_out = 0; |
`endif |
|
`ifdef WDMA_HAVE_CH6 |
wb_dma_pri_enc_sub u6( |
wb_dma_pri_enc_sub #(ch6_conf,pri_sel) u6( |
.valid( valid[6] ), |
.pri_in( pri6 ), |
.pri_out( pri6_out ) |
); |
`else |
assign pri6_out = 0; |
`endif |
|
`ifdef WDMA_HAVE_CH7 |
wb_dma_pri_enc_sub u7( |
wb_dma_pri_enc_sub #(ch7_conf,pri_sel) u7( |
.valid( valid[7] ), |
.pri_in( pri7 ), |
.pri_out( pri7_out ) |
); |
`else |
assign pri7_out = 0; |
`endif |
|
`ifdef WDMA_HAVE_CH8 |
wb_dma_pri_enc_sub u8( |
wb_dma_pri_enc_sub #(ch8_conf,pri_sel) u8( |
.valid( valid[8] ), |
.pri_in( pri8 ), |
.pri_out( pri8_out ) |
); |
`else |
assign pri8_out = 0; |
`endif |
|
`ifdef WDMA_HAVE_CH9 |
wb_dma_pri_enc_sub u9( |
wb_dma_pri_enc_sub #(ch9_conf,pri_sel) u9( |
.valid( valid[9] ), |
.pri_in( pri9 ), |
.pri_out( pri9_out ) |
); |
`else |
assign pri9_out = 0; |
`endif |
|
`ifdef WDMA_HAVE_CH10 |
wb_dma_pri_enc_sub u10( |
wb_dma_pri_enc_sub #(ch10_conf,pri_sel) u10( |
.valid( valid[10] ), |
.pri_in( pri10 ), |
.pri_out( pri10_out ) |
); |
`else |
assign pri10_out = 0; |
`endif |
|
`ifdef WDMA_HAVE_CH11 |
wb_dma_pri_enc_sub u11( |
wb_dma_pri_enc_sub #(ch11_conf,pri_sel) u11( |
.valid( valid[11] ), |
.pri_in( pri11 ), |
.pri_out( pri11_out ) |
); |
`else |
assign pri11_out = 0; |
`endif |
|
`ifdef WDMA_HAVE_CH12 |
wb_dma_pri_enc_sub u12( |
wb_dma_pri_enc_sub #(ch12_conf,pri_sel) u12( |
.valid( valid[12] ), |
.pri_in( pri12 ), |
.pri_out( pri12_out ) |
); |
`else |
assign pri12_out = 0; |
`endif |
|
`ifdef WDMA_HAVE_CH13 |
wb_dma_pri_enc_sub u13( |
wb_dma_pri_enc_sub #(ch13_conf,pri_sel) u13( |
.valid( valid[13] ), |
.pri_in( pri13 ), |
.pri_out( pri13_out ) |
); |
`else |
assign pri13_out = 0; |
`endif |
|
`ifdef WDMA_HAVE_CH14 |
wb_dma_pri_enc_sub u14( |
wb_dma_pri_enc_sub #(ch14_conf,pri_sel) u14( |
.valid( valid[14] ), |
.pri_in( pri14 ), |
.pri_out( pri14_out ) |
); |
`else |
assign pri14_out = 0; |
`endif |
|
`ifdef WDMA_HAVE_CH15 |
wb_dma_pri_enc_sub u15( |
wb_dma_pri_enc_sub #(ch15_conf,pri_sel) u15( |
.valid( valid[15] ), |
.pri_in( pri15 ), |
.pri_out( pri15_out ) |
); |
`else |
assign pri15_out = 0; |
`endif |
|
`ifdef WDMA_HAVE_CH16 |
wb_dma_pri_enc_sub u16( |
wb_dma_pri_enc_sub #(ch16_conf,pri_sel) u16( |
.valid( valid[16] ), |
.pri_in( pri16 ), |
.pri_out( pri16_out ) |
); |
`else |
assign pri16_out = 0; |
`endif |
|
`ifdef WDMA_HAVE_CH17 |
wb_dma_pri_enc_sub u17( |
wb_dma_pri_enc_sub #(ch17_conf,pri_sel) u17( |
.valid( valid[17] ), |
.pri_in( pri17 ), |
.pri_out( pri17_out ) |
); |
`else |
assign pri17_out = 0; |
`endif |
|
`ifdef WDMA_HAVE_CH18 |
wb_dma_pri_enc_sub u18( |
wb_dma_pri_enc_sub #(ch18_conf,pri_sel) u18( |
.valid( valid[18] ), |
.pri_in( pri18 ), |
.pri_out( pri18_out ) |
); |
`else |
assign pri18_out = 0; |
`endif |
|
`ifdef WDMA_HAVE_CH19 |
wb_dma_pri_enc_sub u19( |
wb_dma_pri_enc_sub #(ch19_conf,pri_sel) u19( |
.valid( valid[19] ), |
.pri_in( pri19 ), |
.pri_out( pri19_out ) |
); |
`else |
assign pri19_out = 0; |
`endif |
|
`ifdef WDMA_HAVE_CH20 |
wb_dma_pri_enc_sub u20( |
wb_dma_pri_enc_sub #(ch20_conf,pri_sel) u20( |
.valid( valid[20] ), |
.pri_in( pri20 ), |
.pri_out( pri20_out ) |
); |
`else |
assign pri20_out = 0; |
`endif |
|
`ifdef WDMA_HAVE_CH21 |
wb_dma_pri_enc_sub u21( |
wb_dma_pri_enc_sub #(ch21_conf,pri_sel) u21( |
.valid( valid[21] ), |
.pri_in( pri21 ), |
.pri_out( pri21_out ) |
); |
`else |
assign pri21_out = 0; |
`endif |
|
`ifdef WDMA_HAVE_CH22 |
wb_dma_pri_enc_sub u22( |
wb_dma_pri_enc_sub #(ch22_conf,pri_sel) u22( |
.valid( valid[22] ), |
.pri_in( pri22 ), |
.pri_out( pri22_out ) |
); |
`else |
assign pri22_out = 0; |
`endif |
|
`ifdef WDMA_HAVE_CH23 |
wb_dma_pri_enc_sub u23( |
wb_dma_pri_enc_sub #(ch23_conf,pri_sel) u23( |
.valid( valid[23] ), |
.pri_in( pri23 ), |
.pri_out( pri23_out ) |
); |
`else |
assign pri23_out = 0; |
`endif |
|
`ifdef WDMA_HAVE_CH24 |
wb_dma_pri_enc_sub u24( |
wb_dma_pri_enc_sub #(ch24_conf,pri_sel) u24( |
.valid( valid[24] ), |
.pri_in( pri24 ), |
.pri_out( pri24_out ) |
); |
`else |
assign pri24_out = 0; |
`endif |
|
`ifdef WDMA_HAVE_CH25 |
wb_dma_pri_enc_sub u25( |
wb_dma_pri_enc_sub #(ch25_conf,pri_sel) u25( |
.valid( valid[25] ), |
.pri_in( pri25 ), |
.pri_out( pri25_out ) |
); |
`else |
assign pri25_out = 0; |
`endif |
|
`ifdef WDMA_HAVE_CH26 |
wb_dma_pri_enc_sub u26( |
wb_dma_pri_enc_sub #(ch26_conf,pri_sel) u26( |
.valid( valid[26] ), |
.pri_in( pri26 ), |
.pri_out( pri26_out ) |
); |
`else |
assign pri26_out = 0; |
`endif |
|
`ifdef WDMA_HAVE_CH27 |
wb_dma_pri_enc_sub u27( |
wb_dma_pri_enc_sub #(ch27_conf,pri_sel) u27( |
.valid( valid[27] ), |
.pri_in( pri27 ), |
.pri_out( pri27_out ) |
); |
`else |
assign pri27_out = 0; |
`endif |
|
`ifdef WDMA_HAVE_CH28 |
wb_dma_pri_enc_sub u28( |
wb_dma_pri_enc_sub #(ch28_conf,pri_sel) u28( |
.valid( valid[28] ), |
.pri_in( pri28 ), |
.pri_out( pri28_out ) |
); |
`else |
assign pri28_out = 0; |
`endif |
|
`ifdef WDMA_HAVE_CH29 |
wb_dma_pri_enc_sub u29( |
wb_dma_pri_enc_sub #(ch29_conf,pri_sel) u29( |
.valid( valid[29] ), |
.pri_in( pri29 ), |
.pri_out( pri29_out ) |
); |
`else |
assign pri29_out = 0; |
`endif |
|
`ifdef WDMA_HAVE_CH30 |
wb_dma_pri_enc_sub u30( |
wb_dma_pri_enc_sub #(ch30_conf,pri_sel) u30( |
.valid( valid[30] ), |
.pri_in( pri30 ), |
.pri_out( pri30_out ) |
); |
`else |
assign pri30_out = 0; |
`endif |
|
assign pri_out_tmp = pri0_out | pri1_out | pri2_out | pri3_out | |
pri4_out | pri5_out | pri6_out | pri7_out | |
431,28 → 333,43
pri24_out | pri25_out | pri26_out | pri27_out | |
pri28_out | pri29_out | pri30_out; |
|
// 8 Priority Levels |
always @(posedge clk) |
`ifdef WDMA_PRI_8 |
if(pri_out_tmp[7]) pri_out <= #1 3'h7; |
if(pri_out_tmp[7]) pri_out2 <= #1 3'h7; |
else |
if(pri_out_tmp[6]) pri_out <= #1 3'h6; |
if(pri_out_tmp[6]) pri_out2 <= #1 3'h6; |
else |
if(pri_out_tmp[5]) pri_out <= #1 3'h5; |
if(pri_out_tmp[5]) pri_out2 <= #1 3'h5; |
else |
if(pri_out_tmp[4]) pri_out <= #1 3'h4; |
if(pri_out_tmp[4]) pri_out2 <= #1 3'h4; |
else |
if(pri_out_tmp[3]) pri_out <= #1 3'h3; |
if(pri_out_tmp[3]) pri_out2 <= #1 3'h3; |
else |
if(pri_out_tmp[2]) pri_out <= #1 3'h2; |
if(pri_out_tmp[2]) pri_out2 <= #1 3'h2; |
else |
`endif |
`ifdef WDMA_PRI_4 |
if(pri_out_tmp[3]) pri_out <= #1 3'h3; |
if(pri_out_tmp[1]) pri_out2 <= #1 3'h1; |
else pri_out2 <= #1 3'h0; |
|
// 4 Priority Levels |
always @(posedge clk) |
if(pri_out_tmp[3]) pri_out1 <= #1 3'h3; |
else |
if(pri_out_tmp[2]) pri_out <= #1 3'h2; |
if(pri_out_tmp[2]) pri_out1 <= #1 3'h2; |
else |
`endif |
if(pri_out_tmp[1]) pri_out <= #1 3'h1; |
else pri_out <= #1 3'h0; |
if(pri_out_tmp[1]) pri_out1 <= #1 3'h1; |
else pri_out1 <= #1 3'h0; |
|
// 2 Priority Levels |
always @(posedge clk) |
if(pri_out_tmp[1]) pri_out0 <= #1 3'h1; |
else pri_out0 <= #1 3'h0; |
|
// Select configured priority |
always @(pri_sel or pri_out0 or pri_out1 or pri_out2) |
case(pri_sel) // synopsys parallel_case full_case |
2'd0: pri_out = pri_out0; |
2'd1: pri_out = pri_out1; |
2'd2: pri_out = pri_out2; |
endcase |
|
endmodule |
/trunk/rtl/verilog/wb_dma_wb_slv.v
37,10 → 37,10
|
// CVS Log |
// |
// $Id: wb_dma_wb_slv.v,v 1.2 2001-08-15 05:40:30 rudi Exp $ |
// $Id: wb_dma_wb_slv.v,v 1.3 2001-10-19 04:35:04 rudi Exp $ |
// |
// $Date: 2001-08-15 05:40:30 $ |
// $Revision: 1.2 $ |
// $Date: 2001-10-19 04:35:04 $ |
// $Revision: 1.3 $ |
// $Author: rudi $ |
// $Locker: $ |
// $State: Exp $ |
47,6 → 47,12
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.2 2001/08/15 05:40:30 rudi |
// |
// - Changed IO names to be more clear. |
// - Uniquifyed define names to be core specific. |
// - Added Section 3.10, describing DMA restart. |
// |
// Revision 1.1 2001/07/29 08:57:02 rudi |
// |
// |
83,6 → 89,8
|
); |
|
parameter rf_addr = 0; |
|
input clk, rst; |
|
// -------------------------------------- |
/trunk/rtl/verilog/wb_dma_ch_sel.v
37,10 → 37,10
|
// CVS Log |
// |
// $Id: wb_dma_ch_sel.v,v 1.2 2001-08-15 05:40:30 rudi Exp $ |
// $Id: wb_dma_ch_sel.v,v 1.3 2001-10-19 04:35:04 rudi Exp $ |
// |
// $Date: 2001-08-15 05:40:30 $ |
// $Revision: 1.2 $ |
// $Date: 2001-10-19 04:35:04 $ |
// $Revision: 1.3 $ |
// $Author: rudi $ |
// $Locker: $ |
// $State: Exp $ |
47,6 → 47,12
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.2 2001/08/15 05:40:30 rudi |
// |
// - Changed IO names to be more clear. |
// - Uniquifyed define names to be core specific. |
// - Added Section 3.10, describing DMA restart. |
// |
// Revision 1.1 2001/07/29 08:57:02 rudi |
// |
// |
126,6 → 132,50
pointer_s, next_ch, de_ack, dma_busy |
); |
|
//////////////////////////////////////////////////////////////////// |
// |
// Module Parameters |
// |
|
// chXX_conf = { CBUF, ED, ARS, EN } |
parameter [1:0] pri_sel = 2'h0; |
parameter [3:0] ch0_conf = 4'h1; |
parameter [3:0] ch1_conf = 4'h0; |
parameter [3:0] ch2_conf = 4'h0; |
parameter [3:0] ch3_conf = 4'h0; |
parameter [3:0] ch4_conf = 4'h0; |
parameter [3:0] ch5_conf = 4'h0; |
parameter [3:0] ch6_conf = 4'h0; |
parameter [3:0] ch7_conf = 4'h0; |
parameter [3:0] ch8_conf = 4'h0; |
parameter [3:0] ch9_conf = 4'h0; |
parameter [3:0] ch10_conf = 4'h0; |
parameter [3:0] ch11_conf = 4'h0; |
parameter [3:0] ch12_conf = 4'h0; |
parameter [3:0] ch13_conf = 4'h0; |
parameter [3:0] ch14_conf = 4'h0; |
parameter [3:0] ch15_conf = 4'h0; |
parameter [3:0] ch16_conf = 4'h0; |
parameter [3:0] ch17_conf = 4'h0; |
parameter [3:0] ch18_conf = 4'h0; |
parameter [3:0] ch19_conf = 4'h0; |
parameter [3:0] ch20_conf = 4'h0; |
parameter [3:0] ch21_conf = 4'h0; |
parameter [3:0] ch22_conf = 4'h0; |
parameter [3:0] ch23_conf = 4'h0; |
parameter [3:0] ch24_conf = 4'h0; |
parameter [3:0] ch25_conf = 4'h0; |
parameter [3:0] ch26_conf = 4'h0; |
parameter [3:0] ch27_conf = 4'h0; |
parameter [3:0] ch28_conf = 4'h0; |
parameter [3:0] ch29_conf = 4'h0; |
parameter [3:0] ch30_conf = 4'h0; |
|
//////////////////////////////////////////////////////////////////// |
// |
// Module IOs |
// |
|
input clk, rst; |
|
// DMA Request Lines |
227,6 → 277,8
wire [30:0] req_p24, req_p25, req_p26, req_p27; |
wire [30:0] req_p28, req_p29, req_p30; |
// Arbiter Grant Outputs |
wire [4:0] gnt_p0_d, gnt_p1_d, gnt_p2_d, gnt_p3_d; |
wire [4:0] gnt_p4_d, gnt_p5_d, gnt_p6_d, gnt_p7_d; |
wire [4:0] gnt_p0, gnt_p1, gnt_p2, gnt_p3; |
wire [4:0] gnt_p4, gnt_p5, gnt_p6, gnt_p7; |
wire [4:0] gnt_p8, gnt_p9, gnt_p10, gnt_p11; |
242,105 → 294,99
// Aliases |
// |
|
`ifdef WDMA_PRI_8 |
assign pri0 = ch0_csr[15:13]; |
assign pri1 = ch1_csr[15:13]; |
assign pri2 = ch2_csr[15:13]; |
assign pri3 = ch3_csr[15:13]; |
assign pri4 = ch4_csr[15:13]; |
assign pri5 = ch5_csr[15:13]; |
assign pri6 = ch6_csr[15:13]; |
assign pri7 = ch7_csr[15:13]; |
assign pri8 = ch8_csr[15:13]; |
assign pri9 = ch9_csr[15:13]; |
assign pri10 = ch10_csr[15:13]; |
assign pri11 = ch11_csr[15:13]; |
assign pri12 = ch12_csr[15:13]; |
assign pri13 = ch13_csr[15:13]; |
assign pri14 = ch14_csr[15:13]; |
assign pri15 = ch15_csr[15:13]; |
assign pri16 = ch16_csr[15:13]; |
assign pri17 = ch17_csr[15:13]; |
assign pri18 = ch18_csr[15:13]; |
assign pri19 = ch19_csr[15:13]; |
assign pri20 = ch20_csr[15:13]; |
assign pri21 = ch21_csr[15:13]; |
assign pri22 = ch22_csr[15:13]; |
assign pri23 = ch23_csr[15:13]; |
assign pri24 = ch24_csr[15:13]; |
assign pri25 = ch25_csr[15:13]; |
assign pri26 = ch26_csr[15:13]; |
assign pri27 = ch27_csr[15:13]; |
assign pri28 = ch28_csr[15:13]; |
assign pri29 = ch29_csr[15:13]; |
assign pri30 = ch30_csr[15:13]; |
`else |
`ifdef WDMA_PRI_4 |
assign pri0 = {1'b0, ch0_csr[14:13]}; |
assign pri1 = {1'b0, ch1_csr[14:13]}; |
assign pri2 = {1'b0, ch2_csr[14:13]}; |
assign pri3 = {1'b0, ch3_csr[14:13]}; |
assign pri4 = {1'b0, ch4_csr[14:13]}; |
assign pri5 = {1'b0, ch5_csr[14:13]}; |
assign pri6 = {1'b0, ch6_csr[14:13]}; |
assign pri7 = {1'b0, ch7_csr[14:13]}; |
assign pri8 = {1'b0, ch8_csr[14:13]}; |
assign pri9 = {1'b0, ch9_csr[14:13]}; |
assign pri10 = {1'b0, ch10_csr[14:13]}; |
assign pri11 = {1'b0, ch11_csr[14:13]}; |
assign pri12 = {1'b0, ch12_csr[14:13]}; |
assign pri13 = {1'b0, ch13_csr[14:13]}; |
assign pri14 = {1'b0, ch14_csr[14:13]}; |
assign pri15 = {1'b0, ch15_csr[14:13]}; |
assign pri16 = {1'b0, ch16_csr[14:13]}; |
assign pri17 = {1'b0, ch17_csr[14:13]}; |
assign pri18 = {1'b0, ch18_csr[14:13]}; |
assign pri19 = {1'b0, ch19_csr[14:13]}; |
assign pri20 = {1'b0, ch20_csr[14:13]}; |
assign pri21 = {1'b0, ch21_csr[14:13]}; |
assign pri22 = {1'b0, ch22_csr[14:13]}; |
assign pri23 = {1'b0, ch23_csr[14:13]}; |
assign pri24 = {1'b0, ch24_csr[14:13]}; |
assign pri25 = {1'b0, ch25_csr[14:13]}; |
assign pri26 = {1'b0, ch26_csr[14:13]}; |
assign pri27 = {1'b0, ch27_csr[14:13]}; |
assign pri28 = {1'b0, ch28_csr[14:13]}; |
assign pri29 = {1'b0, ch29_csr[14:13]}; |
assign pri30 = {1'b0, ch30_csr[14:13]}; |
`else |
assign pri0 = {2'b0, ch0_csr[13]}; |
assign pri1 = {2'b0, ch1_csr[13]}; |
assign pri2 = {2'b0, ch2_csr[13]}; |
assign pri3 = {2'b0, ch3_csr[13]}; |
assign pri4 = {2'b0, ch4_csr[13]}; |
assign pri5 = {2'b0, ch5_csr[13]}; |
assign pri6 = {2'b0, ch6_csr[13]}; |
assign pri7 = {2'b0, ch7_csr[13]}; |
assign pri8 = {2'b0, ch8_csr[13]}; |
assign pri9 = {2'b0, ch9_csr[13]}; |
assign pri10 = {2'b0, ch10_csr[13]}; |
assign pri11 = {2'b0, ch11_csr[13]}; |
assign pri12 = {2'b0, ch12_csr[13]}; |
assign pri13 = {2'b0, ch13_csr[13]}; |
assign pri14 = {2'b0, ch14_csr[13]}; |
assign pri15 = {2'b0, ch15_csr[13]}; |
assign pri16 = {2'b0, ch16_csr[13]}; |
assign pri17 = {2'b0, ch17_csr[13]}; |
assign pri18 = {2'b0, ch18_csr[13]}; |
assign pri19 = {2'b0, ch19_csr[13]}; |
assign pri20 = {2'b0, ch20_csr[13]}; |
assign pri21 = {2'b0, ch21_csr[13]}; |
assign pri22 = {2'b0, ch22_csr[13]}; |
assign pri23 = {2'b0, ch23_csr[13]}; |
assign pri24 = {2'b0, ch24_csr[13]}; |
assign pri25 = {2'b0, ch25_csr[13]}; |
assign pri26 = {2'b0, ch26_csr[13]}; |
assign pri27 = {2'b0, ch27_csr[13]}; |
assign pri28 = {2'b0, ch28_csr[13]}; |
assign pri29 = {2'b0, ch29_csr[13]}; |
assign pri30 = {2'b0, ch30_csr[13]}; |
`endif |
`endif |
assign pri0[0] = ch0_csr[13]; |
assign pri0[1] = (pri_sel == 2'd0) ? 1'b0 : ch0_csr[14]; |
assign pri0[2] = (pri_sel == 2'd2) ? ch0_csr[15] : 1'b0; |
assign pri1[0] = ch1_csr[13]; |
assign pri1[1] = (pri_sel == 2'd0) ? 1'b0 : ch1_csr[14]; |
assign pri1[2] = (pri_sel == 2'd2) ? ch1_csr[15] : 1'b0; |
assign pri2[0] = ch2_csr[13]; |
assign pri2[1] = (pri_sel == 2'd0) ? 1'b0 : ch2_csr[14]; |
assign pri2[2] = (pri_sel == 2'd2) ? ch2_csr[15] : 1'b0; |
assign pri3[0] = ch3_csr[13]; |
assign pri3[1] = (pri_sel == 2'd0) ? 1'b0 : ch3_csr[14]; |
assign pri3[2] = (pri_sel == 2'd2) ? ch3_csr[15] : 1'b0; |
assign pri4[0] = ch4_csr[13]; |
assign pri4[1] = (pri_sel == 2'd0) ? 1'b0 : ch4_csr[14]; |
assign pri4[2] = (pri_sel == 2'd2) ? ch4_csr[15] : 1'b0; |
assign pri5[0] = ch5_csr[13]; |
assign pri5[1] = (pri_sel == 2'd0) ? 1'b0 : ch5_csr[14]; |
assign pri5[2] = (pri_sel == 2'd2) ? ch5_csr[15] : 1'b0; |
assign pri6[0] = ch6_csr[13]; |
assign pri6[1] = (pri_sel == 2'd0) ? 1'b0 : ch6_csr[14]; |
assign pri6[2] = (pri_sel == 2'd2) ? ch6_csr[15] : 1'b0; |
assign pri7[0] = ch7_csr[13]; |
assign pri7[1] = (pri_sel == 2'd0) ? 1'b0 : ch7_csr[14]; |
assign pri7[2] = (pri_sel == 2'd2) ? ch7_csr[15] : 1'b0; |
assign pri8[0] = ch8_csr[13]; |
assign pri8[1] = (pri_sel == 2'd0) ? 1'b0 : ch8_csr[14]; |
assign pri8[2] = (pri_sel == 2'd2) ? ch8_csr[15] : 1'b0; |
assign pri9[0] = ch9_csr[13]; |
assign pri9[1] = (pri_sel == 2'd0) ? 1'b0 : ch9_csr[14]; |
assign pri9[2] = (pri_sel == 2'd2) ? ch9_csr[15] : 1'b0; |
assign pri10[0] = ch10_csr[13]; |
assign pri10[1] = (pri_sel == 2'd0) ? 1'b0 : ch10_csr[14]; |
assign pri10[2] = (pri_sel == 2'd2) ? ch10_csr[15] : 1'b0; |
assign pri11[0] = ch11_csr[13]; |
assign pri11[1] = (pri_sel == 2'd0) ? 1'b0 : ch11_csr[14]; |
assign pri11[2] = (pri_sel == 2'd2) ? ch11_csr[15] : 1'b0; |
assign pri12[0] = ch12_csr[13]; |
assign pri12[1] = (pri_sel == 2'd0) ? 1'b0 : ch12_csr[14]; |
assign pri12[2] = (pri_sel == 2'd2) ? ch12_csr[15] : 1'b0; |
assign pri13[0] = ch13_csr[13]; |
assign pri13[1] = (pri_sel == 2'd0) ? 1'b0 : ch13_csr[14]; |
assign pri13[2] = (pri_sel == 2'd2) ? ch13_csr[15] : 1'b0; |
assign pri14[0] = ch14_csr[13]; |
assign pri14[1] = (pri_sel == 2'd0) ? 1'b0 : ch14_csr[14]; |
assign pri14[2] = (pri_sel == 2'd2) ? ch14_csr[15] : 1'b0; |
assign pri15[0] = ch15_csr[13]; |
assign pri15[1] = (pri_sel == 2'd0) ? 1'b0 : ch15_csr[14]; |
assign pri15[2] = (pri_sel == 2'd2) ? ch15_csr[15] : 1'b0; |
assign pri16[0] = ch16_csr[13]; |
assign pri16[1] = (pri_sel == 2'd0) ? 1'b0 : ch16_csr[14]; |
assign pri16[2] = (pri_sel == 2'd2) ? ch16_csr[15] : 1'b0; |
assign pri17[0] = ch17_csr[13]; |
assign pri17[1] = (pri_sel == 2'd0) ? 1'b0 : ch17_csr[14]; |
assign pri17[2] = (pri_sel == 2'd2) ? ch17_csr[15] : 1'b0; |
assign pri18[0] = ch18_csr[13]; |
assign pri18[1] = (pri_sel == 2'd0) ? 1'b0 : ch18_csr[14]; |
assign pri18[2] = (pri_sel == 2'd2) ? ch18_csr[15] : 1'b0; |
assign pri19[0] = ch19_csr[13]; |
assign pri19[1] = (pri_sel == 2'd0) ? 1'b0 : ch19_csr[14]; |
assign pri19[2] = (pri_sel == 2'd2) ? ch19_csr[15] : 1'b0; |
assign pri20[0] = ch20_csr[13]; |
assign pri20[1] = (pri_sel == 2'd0) ? 1'b0 : ch20_csr[14]; |
assign pri20[2] = (pri_sel == 2'd2) ? ch20_csr[15] : 1'b0; |
assign pri21[0] = ch21_csr[13]; |
assign pri21[1] = (pri_sel == 2'd0) ? 1'b0 : ch21_csr[14]; |
assign pri21[2] = (pri_sel == 2'd2) ? ch21_csr[15] : 1'b0; |
assign pri22[0] = ch22_csr[13]; |
assign pri22[1] = (pri_sel == 2'd0) ? 1'b0 : ch22_csr[14]; |
assign pri22[2] = (pri_sel == 2'd2) ? ch22_csr[15] : 1'b0; |
assign pri23[0] = ch23_csr[13]; |
assign pri23[1] = (pri_sel == 2'd0) ? 1'b0 : ch23_csr[14]; |
assign pri23[2] = (pri_sel == 2'd2) ? ch23_csr[15] : 1'b0; |
assign pri24[0] = ch24_csr[13]; |
assign pri24[1] = (pri_sel == 2'd0) ? 1'b0 : ch24_csr[14]; |
assign pri24[2] = (pri_sel == 2'd2) ? ch24_csr[15] : 1'b0; |
assign pri25[0] = ch25_csr[13]; |
assign pri25[1] = (pri_sel == 2'd0) ? 1'b0 : ch25_csr[14]; |
assign pri25[2] = (pri_sel == 2'd2) ? ch25_csr[15] : 1'b0; |
assign pri26[0] = ch26_csr[13]; |
assign pri26[1] = (pri_sel == 2'd0) ? 1'b0 : ch26_csr[14]; |
assign pri26[2] = (pri_sel == 2'd2) ? ch26_csr[15] : 1'b0; |
assign pri27[0] = ch27_csr[13]; |
assign pri27[1] = (pri_sel == 2'd0) ? 1'b0 : ch27_csr[14]; |
assign pri27[2] = (pri_sel == 2'd2) ? ch27_csr[15] : 1'b0; |
assign pri28[0] = ch28_csr[13]; |
assign pri28[1] = (pri_sel == 2'd0) ? 1'b0 : ch28_csr[14]; |
assign pri28[2] = (pri_sel == 2'd2) ? ch28_csr[15] : 1'b0; |
assign pri29[0] = ch29_csr[13]; |
assign pri29[1] = (pri_sel == 2'd0) ? 1'b0 : ch29_csr[14]; |
assign pri29[2] = (pri_sel == 2'd2) ? ch29_csr[15] : 1'b0; |
assign pri30[0] = ch30_csr[13]; |
assign pri30[1] = (pri_sel == 2'd0) ? 1'b0 : ch30_csr[14]; |
assign pri30[2] = (pri_sel == 2'd2) ? ch30_csr[15] : 1'b0; |
|
//////////////////////////////////////////////////////////////////// |
// |
356,37 → 402,37
always @(posedge clk) |
req_r <= #1 req_i & ~ack_o; |
|
assign valid[0] = ch0_csr[`WDMA_CH_EN] & (ch0_csr[`WDMA_MODE] ? (req_r[0] & !ack_o[0]) : 1'b1); |
assign valid[1] = ch1_csr[`WDMA_CH_EN] & (ch1_csr[`WDMA_MODE] ? (req_r[1] & !ack_o[1]) : 1'b1); |
assign valid[2] = ch2_csr[`WDMA_CH_EN] & (ch2_csr[`WDMA_MODE] ? (req_r[2] & !ack_o[2]) : 1'b1); |
assign valid[3] = ch3_csr[`WDMA_CH_EN] & (ch3_csr[`WDMA_MODE] ? (req_r[3] & !ack_o[3]) : 1'b1); |
assign valid[4] = ch4_csr[`WDMA_CH_EN] & (ch4_csr[`WDMA_MODE] ? (req_r[4] & !ack_o[4]) : 1'b1); |
assign valid[5] = ch5_csr[`WDMA_CH_EN] & (ch5_csr[`WDMA_MODE] ? (req_r[5] & !ack_o[5]) : 1'b1); |
assign valid[6] = ch6_csr[`WDMA_CH_EN] & (ch6_csr[`WDMA_MODE] ? (req_r[6] & !ack_o[6]) : 1'b1); |
assign valid[7] = ch7_csr[`WDMA_CH_EN] & (ch7_csr[`WDMA_MODE] ? (req_r[7] & !ack_o[7]) : 1'b1); |
assign valid[8] = ch8_csr[`WDMA_CH_EN] & (ch8_csr[`WDMA_MODE] ? (req_r[8] & !ack_o[8]) : 1'b1); |
assign valid[9] = ch9_csr[`WDMA_CH_EN] & (ch9_csr[`WDMA_MODE] ? (req_r[9] & !ack_o[9]) : 1'b1); |
assign valid[10] = ch10_csr[`WDMA_CH_EN] & (ch10_csr[`WDMA_MODE] ? (req_r[10] & !ack_o[10]) : 1'b1); |
assign valid[11] = ch11_csr[`WDMA_CH_EN] & (ch11_csr[`WDMA_MODE] ? (req_r[11] & !ack_o[11]) : 1'b1); |
assign valid[12] = ch12_csr[`WDMA_CH_EN] & (ch12_csr[`WDMA_MODE] ? (req_r[12] & !ack_o[12]) : 1'b1); |
assign valid[13] = ch13_csr[`WDMA_CH_EN] & (ch13_csr[`WDMA_MODE] ? (req_r[13] & !ack_o[13]) : 1'b1); |
assign valid[14] = ch14_csr[`WDMA_CH_EN] & (ch14_csr[`WDMA_MODE] ? (req_r[14] & !ack_o[14]) : 1'b1); |
assign valid[15] = ch15_csr[`WDMA_CH_EN] & (ch15_csr[`WDMA_MODE] ? (req_r[15] & !ack_o[15]) : 1'b1); |
assign valid[16] = ch16_csr[`WDMA_CH_EN] & (ch16_csr[`WDMA_MODE] ? (req_r[16] & !ack_o[16]) : 1'b1); |
assign valid[17] = ch17_csr[`WDMA_CH_EN] & (ch17_csr[`WDMA_MODE] ? (req_r[17] & !ack_o[17]) : 1'b1); |
assign valid[18] = ch18_csr[`WDMA_CH_EN] & (ch18_csr[`WDMA_MODE] ? (req_r[18] & !ack_o[18]) : 1'b1); |
assign valid[19] = ch19_csr[`WDMA_CH_EN] & (ch19_csr[`WDMA_MODE] ? (req_r[19] & !ack_o[19]) : 1'b1); |
assign valid[20] = ch20_csr[`WDMA_CH_EN] & (ch20_csr[`WDMA_MODE] ? (req_r[20] & !ack_o[20]) : 1'b1); |
assign valid[21] = ch21_csr[`WDMA_CH_EN] & (ch21_csr[`WDMA_MODE] ? (req_r[21] & !ack_o[21]) : 1'b1); |
assign valid[22] = ch22_csr[`WDMA_CH_EN] & (ch22_csr[`WDMA_MODE] ? (req_r[22] & !ack_o[22]) : 1'b1); |
assign valid[23] = ch23_csr[`WDMA_CH_EN] & (ch23_csr[`WDMA_MODE] ? (req_r[23] & !ack_o[23]) : 1'b1); |
assign valid[24] = ch24_csr[`WDMA_CH_EN] & (ch24_csr[`WDMA_MODE] ? (req_r[24] & !ack_o[24]) : 1'b1); |
assign valid[25] = ch25_csr[`WDMA_CH_EN] & (ch25_csr[`WDMA_MODE] ? (req_r[25] & !ack_o[25]) : 1'b1); |
assign valid[26] = ch26_csr[`WDMA_CH_EN] & (ch26_csr[`WDMA_MODE] ? (req_r[26] & !ack_o[26]) : 1'b1); |
assign valid[27] = ch27_csr[`WDMA_CH_EN] & (ch27_csr[`WDMA_MODE] ? (req_r[27] & !ack_o[27]) : 1'b1); |
assign valid[28] = ch28_csr[`WDMA_CH_EN] & (ch28_csr[`WDMA_MODE] ? (req_r[28] & !ack_o[28]) : 1'b1); |
assign valid[29] = ch29_csr[`WDMA_CH_EN] & (ch29_csr[`WDMA_MODE] ? (req_r[29] & !ack_o[29]) : 1'b1); |
assign valid[30] = ch30_csr[`WDMA_CH_EN] & (ch30_csr[`WDMA_MODE] ? (req_r[30] & !ack_o[30]) : 1'b1); |
assign valid[0] = ch0_conf[0] & ch0_csr[`WDMA_CH_EN] & (ch0_csr[`WDMA_MODE] ? (req_r[0] & !ack_o[0]) : 1'b1); |
assign valid[1] = ch1_conf[0] & ch1_csr[`WDMA_CH_EN] & (ch1_csr[`WDMA_MODE] ? (req_r[1] & !ack_o[1]) : 1'b1); |
assign valid[2] = ch2_conf[0] & ch2_csr[`WDMA_CH_EN] & (ch2_csr[`WDMA_MODE] ? (req_r[2] & !ack_o[2]) : 1'b1); |
assign valid[3] = ch3_conf[0] & ch3_csr[`WDMA_CH_EN] & (ch3_csr[`WDMA_MODE] ? (req_r[3] & !ack_o[3]) : 1'b1); |
assign valid[4] = ch4_conf[0] & ch4_csr[`WDMA_CH_EN] & (ch4_csr[`WDMA_MODE] ? (req_r[4] & !ack_o[4]) : 1'b1); |
assign valid[5] = ch5_conf[0] & ch5_csr[`WDMA_CH_EN] & (ch5_csr[`WDMA_MODE] ? (req_r[5] & !ack_o[5]) : 1'b1); |
assign valid[6] = ch6_conf[0] & ch6_csr[`WDMA_CH_EN] & (ch6_csr[`WDMA_MODE] ? (req_r[6] & !ack_o[6]) : 1'b1); |
assign valid[7] = ch7_conf[0] & ch7_csr[`WDMA_CH_EN] & (ch7_csr[`WDMA_MODE] ? (req_r[7] & !ack_o[7]) : 1'b1); |
assign valid[8] = ch8_conf[0] & ch8_csr[`WDMA_CH_EN] & (ch8_csr[`WDMA_MODE] ? (req_r[8] & !ack_o[8]) : 1'b1); |
assign valid[9] = ch9_conf[0] & ch9_csr[`WDMA_CH_EN] & (ch9_csr[`WDMA_MODE] ? (req_r[9] & !ack_o[9]) : 1'b1); |
assign valid[10] = ch10_conf[0] & ch10_csr[`WDMA_CH_EN] & (ch10_csr[`WDMA_MODE] ? (req_r[10] & !ack_o[10]) : 1'b1); |
assign valid[11] = ch11_conf[0] & ch11_csr[`WDMA_CH_EN] & (ch11_csr[`WDMA_MODE] ? (req_r[11] & !ack_o[11]) : 1'b1); |
assign valid[12] = ch12_conf[0] & ch12_csr[`WDMA_CH_EN] & (ch12_csr[`WDMA_MODE] ? (req_r[12] & !ack_o[12]) : 1'b1); |
assign valid[13] = ch13_conf[0] & ch13_csr[`WDMA_CH_EN] & (ch13_csr[`WDMA_MODE] ? (req_r[13] & !ack_o[13]) : 1'b1); |
assign valid[14] = ch14_conf[0] & ch14_csr[`WDMA_CH_EN] & (ch14_csr[`WDMA_MODE] ? (req_r[14] & !ack_o[14]) : 1'b1); |
assign valid[15] = ch15_conf[0] & ch15_csr[`WDMA_CH_EN] & (ch15_csr[`WDMA_MODE] ? (req_r[15] & !ack_o[15]) : 1'b1); |
assign valid[16] = ch16_conf[0] & ch16_csr[`WDMA_CH_EN] & (ch16_csr[`WDMA_MODE] ? (req_r[16] & !ack_o[16]) : 1'b1); |
assign valid[17] = ch17_conf[0] & ch17_csr[`WDMA_CH_EN] & (ch17_csr[`WDMA_MODE] ? (req_r[17] & !ack_o[17]) : 1'b1); |
assign valid[18] = ch18_conf[0] & ch18_csr[`WDMA_CH_EN] & (ch18_csr[`WDMA_MODE] ? (req_r[18] & !ack_o[18]) : 1'b1); |
assign valid[19] = ch19_conf[0] & ch19_csr[`WDMA_CH_EN] & (ch19_csr[`WDMA_MODE] ? (req_r[19] & !ack_o[19]) : 1'b1); |
assign valid[20] = ch20_conf[0] & ch20_csr[`WDMA_CH_EN] & (ch20_csr[`WDMA_MODE] ? (req_r[20] & !ack_o[20]) : 1'b1); |
assign valid[21] = ch21_conf[0] & ch21_csr[`WDMA_CH_EN] & (ch21_csr[`WDMA_MODE] ? (req_r[21] & !ack_o[21]) : 1'b1); |
assign valid[22] = ch22_conf[0] & ch22_csr[`WDMA_CH_EN] & (ch22_csr[`WDMA_MODE] ? (req_r[22] & !ack_o[22]) : 1'b1); |
assign valid[23] = ch23_conf[0] & ch23_csr[`WDMA_CH_EN] & (ch23_csr[`WDMA_MODE] ? (req_r[23] & !ack_o[23]) : 1'b1); |
assign valid[24] = ch24_conf[0] & ch24_csr[`WDMA_CH_EN] & (ch24_csr[`WDMA_MODE] ? (req_r[24] & !ack_o[24]) : 1'b1); |
assign valid[25] = ch25_conf[0] & ch25_csr[`WDMA_CH_EN] & (ch25_csr[`WDMA_MODE] ? (req_r[25] & !ack_o[25]) : 1'b1); |
assign valid[26] = ch26_conf[0] & ch26_csr[`WDMA_CH_EN] & (ch26_csr[`WDMA_MODE] ? (req_r[26] & !ack_o[26]) : 1'b1); |
assign valid[27] = ch27_conf[0] & ch27_csr[`WDMA_CH_EN] & (ch27_csr[`WDMA_MODE] ? (req_r[27] & !ack_o[27]) : 1'b1); |
assign valid[28] = ch28_conf[0] & ch28_csr[`WDMA_CH_EN] & (ch28_csr[`WDMA_MODE] ? (req_r[28] & !ack_o[28]) : 1'b1); |
assign valid[29] = ch29_conf[0] & ch29_csr[`WDMA_CH_EN] & (ch29_csr[`WDMA_MODE] ? (req_r[29] & !ack_o[29]) : 1'b1); |
assign valid[30] = ch30_conf[0] & ch30_csr[`WDMA_CH_EN] & (ch30_csr[`WDMA_MODE] ? (req_r[30] & !ack_o[30]) : 1'b1); |
|
always @(posedge clk) |
ndr_r <= #1 nd_i & req_i; |
405,97 → 451,97
|
// Ack outputs for HW handshake mode |
always @(posedge clk) |
ack_o[0] <= #1 (ch_sel == 5'h0) & ch0_csr[`WDMA_MODE] & de_ack; |
ack_o[0] <= #1 ch0_conf[0] & (ch_sel == 5'h0) & ch0_csr[`WDMA_MODE] & de_ack; |
|
always @(posedge clk) |
ack_o[1] <= #1 (ch_sel == 5'h1) & ch1_csr[`WDMA_MODE] & de_ack; |
ack_o[1] <= #1 ch1_conf[0] & (ch_sel == 5'h1) & ch1_csr[`WDMA_MODE] & de_ack; |
|
always @(posedge clk) |
ack_o[2] <= #1 (ch_sel == 5'h2) & ch2_csr[`WDMA_MODE] & de_ack; |
ack_o[2] <= #1 ch2_conf[0] & (ch_sel == 5'h2) & ch2_csr[`WDMA_MODE] & de_ack; |
|
always @(posedge clk) |
ack_o[3] <= #1 (ch_sel == 5'h3) & ch3_csr[`WDMA_MODE] & de_ack; |
ack_o[3] <= #1 ch3_conf[0] & (ch_sel == 5'h3) & ch3_csr[`WDMA_MODE] & de_ack; |
|
always @(posedge clk) |
ack_o[4] <= #1 (ch_sel == 5'h4) & ch4_csr[`WDMA_MODE] & de_ack; |
ack_o[4] <= #1 ch4_conf[0] & (ch_sel == 5'h4) & ch4_csr[`WDMA_MODE] & de_ack; |
|
always @(posedge clk) |
ack_o[5] <= #1 (ch_sel == 5'h5) & ch5_csr[`WDMA_MODE] & de_ack; |
ack_o[5] <= #1 ch5_conf[0] & (ch_sel == 5'h5) & ch5_csr[`WDMA_MODE] & de_ack; |
|
always @(posedge clk) |
ack_o[6] <= #1 (ch_sel == 5'h6) & ch6_csr[`WDMA_MODE] & de_ack; |
ack_o[6] <= #1 ch6_conf[0] & (ch_sel == 5'h6) & ch6_csr[`WDMA_MODE] & de_ack; |
|
always @(posedge clk) |
ack_o[7] <= #1 (ch_sel == 5'h7) & ch7_csr[`WDMA_MODE] & de_ack; |
ack_o[7] <= #1 ch7_conf[0] & (ch_sel == 5'h7) & ch7_csr[`WDMA_MODE] & de_ack; |
|
always @(posedge clk) |
ack_o[8] <= #1 (ch_sel == 5'h8) & ch8_csr[`WDMA_MODE] & de_ack; |
ack_o[8] <= #1 ch8_conf[0] & (ch_sel == 5'h8) & ch8_csr[`WDMA_MODE] & de_ack; |
|
always @(posedge clk) |
ack_o[9] <= #1 (ch_sel == 5'h9) & ch9_csr[`WDMA_MODE] & de_ack; |
ack_o[9] <= #1 ch9_conf[0] & (ch_sel == 5'h9) & ch9_csr[`WDMA_MODE] & de_ack; |
|
always @(posedge clk) |
ack_o[10] <= #1 (ch_sel == 5'ha) & ch10_csr[`WDMA_MODE] & de_ack; |
ack_o[10] <= #1 ch10_conf[0] & (ch_sel == 5'ha) & ch10_csr[`WDMA_MODE] & de_ack; |
|
always @(posedge clk) |
ack_o[11] <= #1 (ch_sel == 5'hb) & ch11_csr[`WDMA_MODE] & de_ack; |
ack_o[11] <= #1 ch11_conf[0] & (ch_sel == 5'hb) & ch11_csr[`WDMA_MODE] & de_ack; |
|
always @(posedge clk) |
ack_o[12] <= #1 (ch_sel == 5'hc) & ch12_csr[`WDMA_MODE] & de_ack; |
ack_o[12] <= #1 ch12_conf[0] & (ch_sel == 5'hc) & ch12_csr[`WDMA_MODE] & de_ack; |
|
always @(posedge clk) |
ack_o[13] <= #1 (ch_sel == 5'hd) & ch13_csr[`WDMA_MODE] & de_ack; |
ack_o[13] <= #1 ch13_conf[0] & (ch_sel == 5'hd) & ch13_csr[`WDMA_MODE] & de_ack; |
|
always @(posedge clk) |
ack_o[14] <= #1 (ch_sel == 5'he) & ch14_csr[`WDMA_MODE] & de_ack; |
ack_o[14] <= #1 ch14_conf[0] & (ch_sel == 5'he) & ch14_csr[`WDMA_MODE] & de_ack; |
|
always @(posedge clk) |
ack_o[15] <= #1 (ch_sel == 5'hf) & ch15_csr[`WDMA_MODE] & de_ack; |
ack_o[15] <= #1 ch15_conf[0] & (ch_sel == 5'hf) & ch15_csr[`WDMA_MODE] & de_ack; |
|
always @(posedge clk) |
ack_o[16] <= #1 (ch_sel == 5'h10) & ch16_csr[`WDMA_MODE] & de_ack; |
ack_o[16] <= #1 ch16_conf[0] & (ch_sel == 5'h10) & ch16_csr[`WDMA_MODE] & de_ack; |
|
always @(posedge clk) |
ack_o[17] <= #1 (ch_sel == 5'h11) & ch17_csr[`WDMA_MODE] & de_ack; |
ack_o[17] <= #1 ch17_conf[0] & (ch_sel == 5'h11) & ch17_csr[`WDMA_MODE] & de_ack; |
|
always @(posedge clk) |
ack_o[18] <= #1 (ch_sel == 5'h12) & ch18_csr[`WDMA_MODE] & de_ack; |
ack_o[18] <= #1 ch18_conf[0] & (ch_sel == 5'h12) & ch18_csr[`WDMA_MODE] & de_ack; |
|
always @(posedge clk) |
ack_o[19] <= #1 (ch_sel == 5'h13) & ch19_csr[`WDMA_MODE] & de_ack; |
ack_o[19] <= #1 ch19_conf[0] & (ch_sel == 5'h13) & ch19_csr[`WDMA_MODE] & de_ack; |
|
always @(posedge clk) |
ack_o[20] <= #1 (ch_sel == 5'h14) & ch20_csr[`WDMA_MODE] & de_ack; |
ack_o[20] <= #1 ch20_conf[0] & (ch_sel == 5'h14) & ch20_csr[`WDMA_MODE] & de_ack; |
|
always @(posedge clk) |
ack_o[21] <= #1 (ch_sel == 5'h15) & ch21_csr[`WDMA_MODE] & de_ack; |
ack_o[21] <= #1 ch21_conf[0] & (ch_sel == 5'h15) & ch21_csr[`WDMA_MODE] & de_ack; |
|
always @(posedge clk) |
ack_o[22] <= #1 (ch_sel == 5'h16) & ch22_csr[`WDMA_MODE] & de_ack; |
ack_o[22] <= #1 ch22_conf[0] & (ch_sel == 5'h16) & ch22_csr[`WDMA_MODE] & de_ack; |
|
always @(posedge clk) |
ack_o[23] <= #1 (ch_sel == 5'h17) & ch23_csr[`WDMA_MODE] & de_ack; |
ack_o[23] <= #1 ch23_conf[0] & (ch_sel == 5'h17) & ch23_csr[`WDMA_MODE] & de_ack; |
|
always @(posedge clk) |
ack_o[24] <= #1 (ch_sel == 5'h18) & ch24_csr[`WDMA_MODE] & de_ack; |
ack_o[24] <= #1 ch24_conf[0] & (ch_sel == 5'h18) & ch24_csr[`WDMA_MODE] & de_ack; |
|
always @(posedge clk) |
ack_o[25] <= #1 (ch_sel == 5'h19) & ch25_csr[`WDMA_MODE] & de_ack; |
ack_o[25] <= #1 ch25_conf[0] & (ch_sel == 5'h19) & ch25_csr[`WDMA_MODE] & de_ack; |
|
always @(posedge clk) |
ack_o[26] <= #1 (ch_sel == 5'h1a) & ch26_csr[`WDMA_MODE] & de_ack; |
ack_o[26] <= #1 ch26_conf[0] & (ch_sel == 5'h1a) & ch26_csr[`WDMA_MODE] & de_ack; |
|
always @(posedge clk) |
ack_o[27] <= #1 (ch_sel == 5'h1b) & ch27_csr[`WDMA_MODE] & de_ack; |
ack_o[27] <= #1 ch27_conf[0] & (ch_sel == 5'h1b) & ch27_csr[`WDMA_MODE] & de_ack; |
|
always @(posedge clk) |
ack_o[28] <= #1 (ch_sel == 5'h1c) & ch28_csr[`WDMA_MODE] & de_ack; |
ack_o[28] <= #1 ch28_conf[0] & (ch_sel == 5'h1c) & ch28_csr[`WDMA_MODE] & de_ack; |
|
always @(posedge clk) |
ack_o[29] <= #1 (ch_sel == 5'h1d) & ch29_csr[`WDMA_MODE] & de_ack; |
ack_o[29] <= #1 ch29_conf[0] & (ch_sel == 5'h1d) & ch29_csr[`WDMA_MODE] & de_ack; |
|
always @(posedge clk) |
ack_o[30] <= #1 (ch_sel == 5'h1e) & ch30_csr[`WDMA_MODE] & de_ack; |
ack_o[30] <= #1 ch30_conf[0] & (ch_sel == 5'h1e) & ch30_csr[`WDMA_MODE] & de_ack; |
|
// Channel Select |
always @(posedge clk or negedge rst) |
929,7 → 975,40
|
|
// Priority Encoder |
wb_dma_ch_pri_enc u0( |
wb_dma_ch_pri_enc |
#( pri_sel, |
ch0_conf, |
ch1_conf, |
ch2_conf, |
ch3_conf, |
ch4_conf, |
ch5_conf, |
ch6_conf, |
ch7_conf, |
ch8_conf, |
ch9_conf, |
ch10_conf, |
ch11_conf, |
ch12_conf, |
ch13_conf, |
ch14_conf, |
ch15_conf, |
ch16_conf, |
ch17_conf, |
ch18_conf, |
ch19_conf, |
ch20_conf, |
ch21_conf, |
ch22_conf, |
ch23_conf, |
ch24_conf, |
ch25_conf, |
ch26_conf, |
ch27_conf, |
ch28_conf, |
ch29_conf, |
ch30_conf) |
u0( |
.clk( clk ), |
.valid( valid ), |
.pri0( pri0 ), |
1230,7 → 1309,7
.clk( clk ), |
.rst( rst ), |
.req( req_p0 ), |
.gnt( gnt_p0 ), |
.gnt( gnt_p0_d ), |
.advance( next_ch ) |
); |
// RR Arbiter for priority 1 |
1238,17 → 1317,16
.clk( clk ), |
.rst( rst ), |
.req( req_p1 ), |
.gnt( gnt_p1 ), |
.gnt( gnt_p1_d ), |
.advance( next_ch ) |
); |
|
`ifdef WDMA_PRI_4 |
// RR Arbiter for priority 2 |
wb_dma_ch_arb u3( |
.clk( clk ), |
.rst( rst ), |
.req( req_p2 ), |
.gnt( gnt_p2 ), |
.gnt( gnt_p2_d ), |
.advance( next_ch ) |
); |
// RR Arbiter for priority 3 |
1256,34 → 1334,15
.clk( clk ), |
.rst( rst ), |
.req( req_p3 ), |
.gnt( gnt_p3 ), |
.gnt( gnt_p3_d ), |
.advance( next_ch ) |
); |
`endif |
|
`ifdef WDMA_PRI_8 |
// RR Arbiter for priority 2 |
wb_dma_ch_arb u3( |
.clk( clk ), |
.rst( rst ), |
.req( req_p2 ), |
.gnt( gnt_p2 ), |
.advance( next_ch ) |
); |
// RR Arbiter for priority 3 |
wb_dma_ch_arb u4( |
.clk( clk ), |
.rst( rst ), |
.req( req_p3 ), |
.gnt( gnt_p3 ), |
.advance( next_ch ) |
); |
// RR Arbiter for priority 4 |
wb_dma_ch_arb u5( |
.clk( clk ), |
.rst( rst ), |
.req( req_p4 ), |
.gnt( gnt_p4 ), |
.gnt( gnt_p4_d ), |
.advance( next_ch ) |
); |
// RR Arbiter for priority 5 |
1291,7 → 1350,7
.clk( clk ), |
.rst( rst ), |
.req( req_p5 ), |
.gnt( gnt_p5 ), |
.gnt( gnt_p5_d ), |
.advance( next_ch ) |
); |
// RR Arbiter for priority 6 |
1299,7 → 1358,7
.clk( clk ), |
.rst( rst ), |
.req( req_p6 ), |
.gnt( gnt_p6 ), |
.gnt( gnt_p6_d ), |
.advance( next_ch ) |
); |
// RR Arbiter for priority 7 |
1307,25 → 1366,18
.clk( clk ), |
.rst( rst ), |
.req( req_p7 ), |
.gnt( gnt_p7 ), |
.gnt( gnt_p7_d ), |
.advance( next_ch ) |
); |
`endif |
|
// Ground unused outputs |
`ifdef WDMA_PRI_8 |
// Do nothing |
`else |
assign gnt_p4 = 0; |
assign gnt_p5 = 0; |
assign gnt_p6 = 0; |
assign gnt_p7 = 0; |
`ifdef WDMA_PRI_4 |
// Do nothing |
`else |
assign gnt_p2 = 0; |
assign gnt_p3 = 0; |
`endif |
`endif |
// Select grant based on number of priorities |
assign gnt_p0 = gnt_p0_d; |
assign gnt_p1 = gnt_p1_d; |
assign gnt_p2 = (pri_sel==2'd0) ? 5'h0 : gnt_p2_d; |
assign gnt_p3 = (pri_sel==2'd0) ? 5'h0 : gnt_p3_d; |
assign gnt_p4 = (pri_sel==2'd2) ? gnt_p4_d : 5'h0; |
assign gnt_p5 = (pri_sel==2'd2) ? gnt_p5_d : 5'h0; |
assign gnt_p6 = (pri_sel==2'd2) ? gnt_p6_d : 5'h0; |
assign gnt_p7 = (pri_sel==2'd2) ? gnt_p7_d : 5'h0; |
|
endmodule |
/trunk/rtl/verilog/wb_dma_defines.v
37,10 → 37,10
|
// CVS Log |
// |
// $Id: wb_dma_defines.v,v 1.3 2001-09-07 15:34:38 rudi Exp $ |
// $Id: wb_dma_defines.v,v 1.4 2001-10-19 04:35:04 rudi Exp $ |
// |
// $Date: 2001-09-07 15:34:38 $ |
// $Revision: 1.3 $ |
// $Date: 2001-10-19 04:35:04 $ |
// $Revision: 1.4 $ |
// $Author: rudi $ |
// $Locker: $ |
// $State: Exp $ |
47,6 → 47,10
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.3 2001/09/07 15:34:38 rudi |
// |
// Changed reset to active high. |
// |
// Revision 1.2 2001/08/15 05:40:30 rudi |
// |
// - Changed IO names to be more clear. |
76,150 → 80,6
|
`timescale 1ns / 10ps |
|
// Identify how many channels are in this implementation |
`define WDMA_CH_COUNT 4 |
|
`define WDMA_HAVE_CH1 1 |
`define WDMA_HAVE_CH2 1 |
`define WDMA_HAVE_CH3 1 |
|
/* |
`define WDMA_HAVE_CH4 1 |
`define WDMA_HAVE_CH5 1 |
`define WDMA_HAVE_CH6 1 |
`define WDMA_HAVE_CH7 1 |
`define WDMA_HAVE_CH8 1 |
`define WDMA_HAVE_CH9 1 |
`define WDMA_HAVE_CH10 1 |
`define WDMA_HAVE_CH11 1 |
`define WDMA_HAVE_CH12 1 |
`define WDMA_HAVE_CH13 1 |
`define WDMA_HAVE_CH14 1 |
`define WDMA_HAVE_CH15 1 |
`define WDMA_HAVE_CH16 1 |
`define WDMA_HAVE_CH17 1 |
`define WDMA_HAVE_CH18 1 |
`define WDMA_HAVE_CH19 1 |
`define WDMA_HAVE_CH20 1 |
`define WDMA_HAVE_CH21 1 |
`define WDMA_HAVE_CH22 1 |
`define WDMA_HAVE_CH23 1 |
`define WDMA_HAVE_CH24 1 |
`define WDMA_HAVE_CH25 1 |
`define WDMA_HAVE_CH26 1 |
`define WDMA_HAVE_CH27 1 |
`define WDMA_HAVE_CH28 1 |
`define WDMA_HAVE_CH29 1 |
`define WDMA_HAVE_CH30 1 |
*/ |
|
`define WDMA_HAVE_ARS0 1 |
`define WDMA_HAVE_ARS1 1 |
`define WDMA_HAVE_ARS2 1 |
`define WDMA_HAVE_ARS3 1 |
`define WDMA_HAVE_ARS4 1 |
`define WDMA_HAVE_ARS5 1 |
`define WDMA_HAVE_ARS6 1 |
`define WDMA_HAVE_ARS7 1 |
`define WDMA_HAVE_ARS8 1 |
`define WDMA_HAVE_ARS9 1 |
`define WDMA_HAVE_ARS10 1 |
`define WDMA_HAVE_ARS11 1 |
`define WDMA_HAVE_ARS12 1 |
`define WDMA_HAVE_ARS13 1 |
`define WDMA_HAVE_ARS14 1 |
`define WDMA_HAVE_ARS15 1 |
`define WDMA_HAVE_ARS16 1 |
`define WDMA_HAVE_ARS17 1 |
`define WDMA_HAVE_ARS18 1 |
`define WDMA_HAVE_ARS19 1 |
`define WDMA_HAVE_ARS20 1 |
`define WDMA_HAVE_ARS21 1 |
`define WDMA_HAVE_ARS22 1 |
`define WDMA_HAVE_ARS23 1 |
`define WDMA_HAVE_ARS24 1 |
`define WDMA_HAVE_ARS25 1 |
`define WDMA_HAVE_ARS26 1 |
`define WDMA_HAVE_ARS27 1 |
`define WDMA_HAVE_ARS28 1 |
`define WDMA_HAVE_ARS29 1 |
`define WDMA_HAVE_ARS30 1 |
|
`define WDMA_HAVE_ED0 1 |
`define WDMA_HAVE_ED1 1 |
`define WDMA_HAVE_ED2 1 |
`define WDMA_HAVE_ED3 1 |
`define WDMA_HAVE_ED4 1 |
`define WDMA_HAVE_ED5 1 |
`define WDMA_HAVE_ED6 1 |
`define WDMA_HAVE_ED7 1 |
`define WDMA_HAVE_ED8 1 |
`define WDMA_HAVE_ED9 1 |
`define WDMA_HAVE_ED10 1 |
`define WDMA_HAVE_ED11 1 |
`define WDMA_HAVE_ED12 1 |
`define WDMA_HAVE_ED13 1 |
`define WDMA_HAVE_ED14 1 |
`define WDMA_HAVE_ED15 1 |
`define WDMA_HAVE_ED16 1 |
`define WDMA_HAVE_ED17 1 |
`define WDMA_HAVE_ED18 1 |
`define WDMA_HAVE_ED19 1 |
`define WDMA_HAVE_ED20 1 |
`define WDMA_HAVE_ED21 1 |
`define WDMA_HAVE_ED22 1 |
`define WDMA_HAVE_ED23 1 |
`define WDMA_HAVE_ED24 1 |
`define WDMA_HAVE_ED25 1 |
`define WDMA_HAVE_ED26 1 |
`define WDMA_HAVE_ED27 1 |
`define WDMA_HAVE_ED28 1 |
`define WDMA_HAVE_ED29 1 |
`define WDMA_HAVE_ED30 1 |
|
`define WDMA_HAVE_CBUF0 1 |
`define WDMA_HAVE_CBUF1 1 |
`define WDMA_HAVE_CBUF2 1 |
`define WDMA_HAVE_CBUF3 1 |
`define WDMA_HAVE_CBUF4 1 |
`define WDMA_HAVE_CBUF5 1 |
`define WDMA_HAVE_CBUF6 1 |
`define WDMA_HAVE_CBUF7 1 |
`define WDMA_HAVE_CBUF8 1 |
`define WDMA_HAVE_CBUF9 1 |
`define WDMA_HAVE_CBUF10 1 |
`define WDMA_HAVE_CBUF11 1 |
`define WDMA_HAVE_CBUF12 1 |
`define WDMA_HAVE_CBUF13 1 |
`define WDMA_HAVE_CBUF14 1 |
`define WDMA_HAVE_CBUF15 1 |
`define WDMA_HAVE_CBUF16 1 |
`define WDMA_HAVE_CBUF17 1 |
`define WDMA_HAVE_CBUF18 1 |
`define WDMA_HAVE_CBUF19 1 |
`define WDMA_HAVE_CBUF20 1 |
`define WDMA_HAVE_CBUF21 1 |
`define WDMA_HAVE_CBUF22 1 |
`define WDMA_HAVE_CBUF23 1 |
`define WDMA_HAVE_CBUF24 1 |
`define WDMA_HAVE_CBUF25 1 |
`define WDMA_HAVE_CBUF26 1 |
`define WDMA_HAVE_CBUF27 1 |
`define WDMA_HAVE_CBUF28 1 |
`define WDMA_HAVE_CBUF29 1 |
`define WDMA_HAVE_CBUF30 1 |
|
// The two define statements below select the number of priorities |
// that the DMA engine supports. |
// if WDMA_PRI_8 is defined, 8 levels of priorities are supported. If |
// WDMA_PRI_4 is defined then 4 levels of priorities are supported. |
// If neither is defined then two levels of priorities are supported. |
// WDMA_PRI_4 and WDMA_PRI_8 should never be both defined at the same |
// time. |
|
//`define WDMA_PRI_8 1 |
`define WDMA_PRI_4 1 |
|
// This define selects how the slave interface determines if |
// the internal register file or pass through mode are selected. |
// This should be a simple address decoder. "wb_addr_i" is the |
229,10 → 89,10
// the higher will be the initial delay when pass-through mode is selected. |
// Here we look at the top 8 address bit. If they are all 1, the |
// register file is selected. Use this with caution !!! |
//`define WDMA_REG_SEL (wb_addr_i[31:24] == 8'hff) |
`define WDMA_REG_SEL (wb_addr_i[31:28] == 4'hb) |
`define WDMA_REG_SEL (wb_addr_i[31:28] == rf_addr) |
|
|
// DO NOT MODIFY BEYOND THIS POINT |
// CSR Bits |
`define WDMA_CH_EN 0 |
`define WDMA_DST_SEL 1 |
/trunk/rtl/verilog/wb_dma_ch_rf.v
37,10 → 37,10
|
// CVS Log |
// |
// $Id: wb_dma_ch_rf.v,v 1.2 2001-08-15 05:40:30 rudi Exp $ |
// $Id: wb_dma_ch_rf.v,v 1.3 2001-10-19 04:35:04 rudi Exp $ |
// |
// $Date: 2001-08-15 05:40:30 $ |
// $Revision: 1.2 $ |
// $Date: 2001-10-19 04:35:04 $ |
// $Revision: 1.3 $ |
// $Author: rudi $ |
// $Locker: $ |
// $State: Exp $ |
47,6 → 47,12
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.2 2001/08/15 05:40:30 rudi |
// |
// - Changed IO names to be more clear. |
// - Uniquifyed define names to be core specific. |
// - Added Section 3.10, describing DMA restart. |
// |
// Revision 1.1 2001/07/29 08:57:02 rudi |
// |
// |
94,6 → 100,7
); |
|
parameter [4:0] CH_NO = 5'h0; // This Instances Channel ID |
parameter [0:0] CH_EN = 1'b1; // This channel exists |
parameter [0:0] HAVE_ARS = 1'b1; // 1=this Instance Supports ARS |
parameter [0:0] HAVE_ED = 1'b1; // 1=this Instance Supports External Descriptors |
parameter [0:0] HAVE_CBUF= 1'b1; // 1=this Instance Supports Cyclic Buffers |
193,19 → 200,19
// Aliases |
// |
|
assign ch_adr0 = {ch_adr0_r, 2'h0}; |
assign ch_adr1 = {ch_adr1_r, 2'h0}; |
assign ch_am0 = {ch_am0_r, 4'h0}; |
assign ch_am1 = {ch_am1_r, 4'h0}; |
assign sw_pointer = {sw_pointer_r,2'h0}; |
assign ch_adr0 = CH_EN ? {ch_adr0_r, 2'h0} : 32'h0; |
assign ch_adr1 = CH_EN ? {ch_adr1_r, 2'h0} : 32'h0; |
assign ch_am0 = CH_EN ? {ch_am0_r, 4'h0} : 32'h0; |
assign ch_am1 = CH_EN ? {ch_am1_r, 4'h0} : 32'h0; |
assign sw_pointer = CH_EN ? {sw_pointer_r,2'h0} : 32'h0; |
|
assign pointer = {pointer_r, 3'h0, ptr_valid}; |
assign pointer_s = {pointer_sr, 4'h0}; |
assign ch_csr = {9'h0, int_src_r, ch_csr_r3, rest_en, ch_csr_r2, |
ch_err, ch_done, ch_busy, 1'b0, ch_csr_r[8:1], ch_enable}; |
assign ch_txsz = {5'h0, ch_chk_sz_r, ch_sz_inf, 3'h0, ch_tot_sz_r}; |
assign pointer = CH_EN ? {pointer_r, 3'h0, ptr_valid} : 32'h0; |
assign pointer_s = CH_EN ? {pointer_sr, 4'h0} : 32'h0; |
assign ch_csr = CH_EN ? {9'h0, int_src_r, ch_csr_r3, rest_en, ch_csr_r2, |
ch_err, ch_done, ch_busy, 1'b0, ch_csr_r[8:1], ch_enable} : 32'h0; |
assign ch_txsz = CH_EN ? {5'h0, ch_chk_sz_r, ch_sz_inf, 3'h0, ch_tot_sz_r} : 32'h0; |
|
assign ch_enable = ch_csr_r[`WDMA_CH_EN] & (HAVE_CBUF ? !ch_dis : 1'b1); |
assign ch_enable = CH_EN ? (ch_csr_r[`WDMA_CH_EN] & (HAVE_CBUF ? !ch_dis : 1'b1) ) : 1'b0; |
|
//////////////////////////////////////////////////////////////////// |
// |
214,30 → 221,30
|
parameter [4:0] CH_ADR = CH_NO + 5'h1; |
|
assign ch_csr_we = wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h0); |
assign ch_csr_re = wb_rf_re & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h0); |
assign ch_txsz_we = wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h1); |
assign ch_adr0_we = wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h2); |
assign ch_am0_we = wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h3); |
assign ch_adr1_we = wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h4); |
assign ch_am1_we = wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h5); |
assign pointer_we = wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h6); |
assign sw_pointer_we = wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h7); |
assign ch_csr_we = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h0); |
assign ch_csr_re = CH_EN & wb_rf_re & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h0); |
assign ch_txsz_we = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h1); |
assign ch_adr0_we = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h2); |
assign ch_am0_we = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h3); |
assign ch_adr1_we = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h4); |
assign ch_am1_we = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h5); |
assign pointer_we = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h6); |
assign sw_pointer_we = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h7); |
|
assign ch_done_we = (((ch_sel==CH_NO) & dma_done_all) | ndnr) & |
assign ch_done_we = CH_EN & (((ch_sel==CH_NO) & dma_done_all) | ndnr) & |
(ch_csr[`WDMA_USE_ED] ? ch_eol : !ch_csr[`WDMA_ARS]); |
assign chunk_done_we = (ch_sel==CH_NO) & dma_done; |
assign ch_err_we = (ch_sel==CH_NO) & dma_err; |
assign ch_csr_dewe = de_csr_we & (ch_sel==CH_NO); |
assign ch_txsz_dewe = de_txsz_we & (ch_sel==CH_NO); |
assign ch_adr0_dewe = de_adr0_we & (ch_sel==CH_NO); |
assign ch_adr1_dewe = de_adr1_we & (ch_sel==CH_NO); |
assign chunk_done_we = CH_EN & (ch_sel==CH_NO) & dma_done; |
assign ch_err_we = CH_EN & (ch_sel==CH_NO) & dma_err; |
assign ch_csr_dewe = CH_EN & de_csr_we & (ch_sel==CH_NO); |
assign ch_txsz_dewe = CH_EN & de_txsz_we & (ch_sel==CH_NO); |
assign ch_adr0_dewe = CH_EN & de_adr0_we & (ch_sel==CH_NO); |
assign ch_adr1_dewe = CH_EN & de_adr1_we & (ch_sel==CH_NO); |
|
assign ptr_inv = ((ch_sel==CH_NO) & dma_done_all) | ndnr; |
assign this_ptr_set = ptr_set & (ch_sel==CH_NO); |
assign ptr_inv = CH_EN & ((ch_sel==CH_NO) & dma_done_all) | ndnr; |
assign this_ptr_set = CH_EN & ptr_set & (ch_sel==CH_NO); |
|
always @(posedge clk) |
ch_rl <= #1 HAVE_ARS & ( |
ch_rl <= #1 CH_EN & HAVE_ARS & ( |
(rest_en & dma_rest) | |
((ch_sel==CH_NO) & dma_done_all & ch_csr[`WDMA_ARS] & !ch_csr[`WDMA_USE_ED]) |
); |
248,7 → 255,7
always @(posedge clk or negedge rst) |
if(!rst) ptr_valid <= #1 1'b0; |
else |
if(HAVE_ED) |
if(CH_EN & HAVE_ED) |
begin |
if( this_ptr_set | (rest_en & dma_rest) ) |
ptr_valid <= #1 1'b1; |
260,7 → 267,7
always @(posedge clk or negedge rst) |
if(!rst) ch_eol <= #1 1'b0; |
else |
if(HAVE_ED) |
if(CH_EN & HAVE_ED) |
begin |
if(ch_csr_dewe) ch_eol <= #1 de_csr[`WDMA_ED_EOL]; |
else |
269,7 → 276,7
else ch_eol <= #1 1'b0; |
|
always @(posedge clk) |
if(HAVE_ED) |
if(CH_EN & HAVE_ED) |
begin |
if(pointer_we) pointer_r <= #1 wb_rf_din[31:4]; |
else |
278,7 → 285,7
else pointer_r <= #1 1'b0; |
|
always @(posedge clk) |
if(HAVE_ED) |
if(CH_EN & HAVE_ED) |
begin |
if(this_ptr_set) pointer_sr <= #1 pointer_r; |
end |
288,13 → 295,16
// CSR |
|
always @(posedge clk or negedge rst) |
if(!rst) ch_csr_r <= #1 1'b0; |
if(!rst) ch_csr_r <= #1 1'b0; |
else |
if(ch_csr_we) ch_csr_r <= #1 wb_rf_din[8:0]; |
else |
if(CH_EN) |
begin |
if(ch_done_we) ch_csr_r[`WDMA_CH_EN] <= #1 1'b0; |
if(ch_csr_dewe) ch_csr_r[4:1] <= #1 de_csr[19:16]; |
if(ch_csr_we) ch_csr_r <= #1 wb_rf_din[8:0]; |
else |
begin |
if(ch_done_we) ch_csr_r[`WDMA_CH_EN] <= #1 1'b0; |
if(ch_csr_dewe) ch_csr_r[4:1] <= #1 de_csr[19:16]; |
end |
end |
|
// done bit |
301,65 → 311,80
always @(posedge clk or negedge rst) |
if(!rst) ch_done <= #1 1'b0; |
else |
if(ch_csr_we) ch_done <= #1 !wb_rf_din[`WDMA_CH_EN]; |
else |
if(ch_done_we) ch_done <= #1 1'b1; |
if(CH_EN) |
begin |
if(ch_csr_we) ch_done <= #1 !wb_rf_din[`WDMA_CH_EN]; |
else |
if(ch_done_we) ch_done <= #1 1'b1; |
end |
|
// busy bit |
always @(posedge clk) |
ch_busy <= #1 (ch_sel==CH_NO) & dma_busy; |
ch_busy <= #1 CH_EN & (ch_sel==CH_NO) & dma_busy; |
|
// stop bit |
always @(posedge clk) |
ch_stop <= #1 ch_csr_we & wb_rf_din[`WDMA_STOP]; |
ch_stop <= #1 CH_EN & ch_csr_we & wb_rf_din[`WDMA_STOP]; |
|
// error bit |
always @(posedge clk or negedge rst) |
if(!rst) ch_err <= #1 1'b0; |
if(!rst) ch_err <= #1 1'b0; |
else |
if(ch_err_we) ch_err <= #1 1'b1; |
else |
if(ch_csr_re) ch_err <= #1 1'b0; |
if(CH_EN) |
begin |
if(ch_err_we) ch_err <= #1 1'b1; |
else |
if(ch_csr_re) ch_err <= #1 1'b0; |
end |
|
// Priority Bits |
always @(posedge clk or negedge rst) |
if(!rst) ch_csr_r2 <= #1 3'h0; |
if(!rst) ch_csr_r2 <= #1 3'h0; |
else |
if(ch_csr_we) ch_csr_r2 <= #1 wb_rf_din[15:13]; |
if(CH_EN & ch_csr_we) ch_csr_r2 <= #1 wb_rf_din[15:13]; |
|
// Restart Enable Bit (REST) |
always @(posedge clk or negedge rst) |
if(!rst) rest_en <= #1 1'b0; |
if(!rst) rest_en <= #1 1'b0; |
else |
if(ch_csr_we) rest_en <= #1 wb_rf_din[16]; |
if(CH_EN & ch_csr_we) rest_en <= #1 wb_rf_din[16]; |
|
// INT Mask |
always @(posedge clk or negedge rst) |
if(!rst) ch_csr_r3 <= #1 3'h0; |
if(!rst) ch_csr_r3 <= #1 3'h0; |
else |
if(ch_csr_we) ch_csr_r3 <= #1 wb_rf_din[19:17]; |
if(CH_EN & ch_csr_we) ch_csr_r3 <= #1 wb_rf_din[19:17]; |
|
// INT Source |
always @(posedge clk or negedge rst) |
if(!rst) int_src_r[2] <= #1 1'b0; |
if(!rst) int_src_r[2] <= #1 1'b0; |
else |
if(chunk_done_we) int_src_r[2] <= #1 1'b1; |
else |
if(ch_csr_re) int_src_r[2] <= #1 1'b0; |
if(CH_EN) |
begin |
if(chunk_done_we) int_src_r[2] <= #1 1'b1; |
else |
if(ch_csr_re) int_src_r[2] <= #1 1'b0; |
end |
|
always @(posedge clk or negedge rst) |
if(!rst) int_src_r[1] <= #1 1'b0; |
if(!rst) int_src_r[1] <= #1 1'b0; |
else |
if(ch_done_we) int_src_r[1] <= #1 1'b1; |
else |
if(ch_csr_re) int_src_r[1] <= #1 1'b0; |
if(CH_EN) |
begin |
if(ch_done_we) int_src_r[1] <= #1 1'b1; |
else |
if(ch_csr_re) int_src_r[1] <= #1 1'b0; |
end |
|
always @(posedge clk or negedge rst) |
if(!rst) int_src_r[0] <= #1 1'b0; |
if(!rst) int_src_r[0] <= #1 1'b0; |
else |
if(ch_err_we) int_src_r[0] <= #1 1'b1; |
else |
if(ch_csr_re) int_src_r[0] <= #1 1'b0; |
if(CH_EN) |
begin |
if(ch_err_we) int_src_r[0] <= #1 1'b1; |
else |
if(ch_csr_re) int_src_r[0] <= #1 1'b0; |
end |
|
// Interrupt Output |
assign int = |(int_src_r & ch_csr_r3); |
367,18 → 392,21
// --------------------------------------------------- |
// TXZS |
always @(posedge clk) |
if(ch_txsz_we) |
{ch_chk_sz_r, ch_tot_sz_r} <= #1 {wb_rf_din[26:16], wb_rf_din[11:0]}; |
else |
if(ch_txsz_dewe) |
ch_tot_sz_r <= #1 de_txsz; |
else |
if(ch_rl) |
{ch_chk_sz_r, ch_tot_sz_r} <= #1 ch_txsz_s; |
if(CH_EN) |
begin |
if(ch_txsz_we) |
{ch_chk_sz_r, ch_tot_sz_r} <= #1 {wb_rf_din[26:16], wb_rf_din[11:0]}; |
else |
if(ch_txsz_dewe) |
ch_tot_sz_r <= #1 de_txsz; |
else |
if(ch_rl) |
{ch_chk_sz_r, ch_tot_sz_r} <= #1 ch_txsz_s; |
end |
|
// txsz shadow register |
always @(posedge clk) |
if(HAVE_ARS) |
if(CH_EN & HAVE_ARS) |
begin |
|
if(ch_txsz_we) ch_txsz_s <= #1 {wb_rf_din[26:16], wb_rf_din[11:0]}; |
389,20 → 417,26
|
// Infinite Size indicator |
always @(posedge clk) |
if(ch_txsz_we) ch_sz_inf <= #1 wb_rf_din[15]; |
if(CH_EN) |
begin |
if(ch_txsz_we) ch_sz_inf <= #1 wb_rf_din[15]; |
end |
|
// --------------------------------------------------- |
// ADR0 |
always @(posedge clk) |
if(ch_adr0_we) ch_adr0_r <= #1 wb_rf_din[31:2]; |
else |
if(ch_adr0_dewe) ch_adr0_r <= #1 de_adr0[31:2]; |
else |
if(ch_rl) ch_adr0_r <= #1 ch_adr0_s; |
if(CH_EN) |
begin |
if(ch_adr0_we) ch_adr0_r <= #1 wb_rf_din[31:2]; |
else |
if(ch_adr0_dewe) ch_adr0_r <= #1 de_adr0[31:2]; |
else |
if(ch_rl) ch_adr0_r <= #1 ch_adr0_s; |
end |
|
// Adr0 shadow register |
always @(posedge clk) |
if(HAVE_ARS) |
if(CH_EN & HAVE_ARS) |
begin |
if(ch_adr0_we) ch_adr0_s <= #1 wb_rf_din[31:2]; |
else |
420,15 → 454,18
// --------------------------------------------------- |
// ADR1 |
always @(posedge clk) |
if(ch_adr1_we) ch_adr1_r <= #1 wb_rf_din[31:2]; |
else |
if(ch_adr1_dewe) ch_adr1_r <= #1 de_adr1[31:2]; |
else |
if(ch_rl) ch_adr1_r <= #1 ch_adr1_s; |
if(CH_EN) |
begin |
if(ch_adr1_we) ch_adr1_r <= #1 wb_rf_din[31:2]; |
else |
if(ch_adr1_dewe) ch_adr1_r <= #1 de_adr1[31:2]; |
else |
if(ch_rl) ch_adr1_r <= #1 ch_adr1_s; |
end |
|
// Adr1 shadow register |
always @(posedge clk) |
if(HAVE_ARS) |
if(CH_EN & HAVE_ARS) |
begin |
if(ch_adr1_we) ch_adr1_s <= #1 wb_rf_din[31:2]; |
else |
439,16 → 476,16
// --------------------------------------------------- |
// AM1 |
always @(posedge clk or negedge rst) |
if(!rst) ch_am1_r <= #1 28'hfffffff; |
if(!rst) ch_am1_r <= #1 28'hfffffff; |
else |
if(ch_am1_we & HAVE_CBUF) ch_am1_r <= #1 wb_rf_din[31:4]; |
if(ch_am1_we & CH_EN & HAVE_CBUF) ch_am1_r <= #1 wb_rf_din[31:4]; |
|
// --------------------------------------------------- |
// Software Pointer |
always @(posedge clk or negedge rst) |
if(!rst) sw_pointer_r <= #1 28'h0; |
if(!rst) sw_pointer_r <= #1 28'h0; |
else |
if(sw_pointer_we & HAVE_CBUF) sw_pointer_r <= #1 wb_rf_din[31:4]; |
if(sw_pointer_we & CH_EN & HAVE_CBUF) sw_pointer_r <= #1 wb_rf_din[31:4]; |
|
// --------------------------------------------------- |
// Software Pointer Match logic |
456,7 → 493,7
assign cmp_adr = ch_csr[2] ? ch_adr1[30:2] : ch_adr0[30:2]; |
|
always @(posedge clk) |
ch_dis <= #1 HAVE_CBUF ? ((sw_pointer[30:2] == cmp_adr) & sw_pointer[31]) : 1'b0; |
ch_dis <= #1 (CH_EN & HAVE_CBUF) ? ((sw_pointer[30:2] == cmp_adr) & sw_pointer[31]) : 1'b0; |
|
endmodule |
|
/trunk/doc/STATUS.txt
13,7 → 13,13
STATUS |
====== |
|
Latest Release (7/27/2001) |
Latest Release (10/19/2001) |
--------------------------- |
- Made the core parameterizable - no more editing of the |
wb_defines.v file, just pass the configuration to the core |
when instantiating it ! |
|
Third Release (7/27/2001) |
-------------------------- |
- Added dma_rest_i. It allows to restart the current transfer at |
the beginning. Beginning is defined as the original values that |
/trunk/doc/dma_doc.pdf
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