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URL https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk

Subversion Repositories sdhc-sc-core

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  • This comparison shows the changes necessary to convert path 
    /
    from Rev 100 to Rev 101
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  •

Rev 100 → Rev 101

/sdhc-sc-core/trunk/src/grpSd/unitSdData/src/SdData-Rtl-a.vhdl
24,7 → 24,8
Data : aDataOutput;
Enable : std_ulogic;
Controller : aSdDataToController;
Mode : aSdDataBusMode;
Mode : aSdDataBusMode;
Crc : std_ulogic_vector(15 downto 0);
end record aReg;
 
constant cDefaultReg : aReg := (
35,7 → 36,8
Data => "0000",
Enable => cInactivated,
Controller => cDefaultSdDataToController,
Mode => standard);
Mode => standard,
Crc => (others => '0'));
 
type aCrcOut is record
Clear : std_ulogic;
69,6 → 71,8
 
CrcDataIn <= (others => CrcOut.DataIn) when R.Mode = wide else
"000" & CrcOut.DataIn;
 
oCrc <= R.Crc;
oSdDataToController <= R.Controller;
 
114,12 → 118,16
 
elsif (R.Mode = wide and ioData = std_logic_vector(cSdStartBits)) or
(R.Mode = standard and ioData(0) = cSdStartBit) then
NextR.Region <= data;
NextR.Region <= data;
NextR.State <= receive;
NextR.BitCounter <= to_unsigned(7,aBitCounter'length);
 
if (iSdDataFromController.DataMode = widewidth) then
NextR.ByteCounter <= to_unsigned(511,aByteCounter'length);
if (iSdDataFromController.ExpectBits = ScrBits) then
NextR.ByteCounter <= to_unsigned(63, aByteCounter'length);
else
NextR.ByteCounter <= to_unsigned(511, aByteCounter'length);
end if;
end if;
 
elsif (iSdDataFromController.Valid = cActivated) then
248,6 → 256,7
case R.Mode is
when standard =>
ShiftIntoCrc("000" & ioData(0));
NextR.Crc(to_integer(15 - R.ByteCounter)) <= ioData(0);
 
when wide =>
ShiftIntoCrc(std_ulogic_vector(ioData));
256,6 → 265,7
report "Unhandled mode" severity error;
end case;
 
 
if (R.ByteCounter = 15) then
NextR.Region <= endbit;
else
263,15 → 273,15
end if;
 
when endbit =>
-- if (CrcIn.Correct = "1111" and R.Mode = wide) or
-- (CrcIn.Correct(0) = cActivated and R.Mode = standard) then
if (CrcIn.Correct = "1111" and R.Mode = wide) or
(CrcIn.Correct(0) = cActivated and R.Mode = standard) then
NextR.Controller.Valid <= cActivated;
--
-- else
-- NextR.Controller.Err <= cActivated;
--
-- end if;
 
else
NextR.Controller.Err <= cActivated;
 
end if;
 
NextR.ByteCounter <= to_unsigned(0, aByteCounter'length);
NextR.Region <= startbit;
NextR.State <= idle;
/sdhc-sc-core/trunk/src/grpSd/unitSdData/src/SdData-e.vhdl
23,6 → 23,7
-- Controller
iSdDataFromController : in aSdDataFromController;
oSdDataToController : out aSdDataToController;
oCrc : out std_ulogic_vector(15 downto 0);
 
-- Card
ioData : inout std_logic_vector(3 downto 0)
/sdhc-sc-core/trunk/src/grpSd/unitTbdSd/src/TbdSd-Rtl-ea.vhdl
49,7 → 49,7
signal iRs232Tx : aiRs232Tx;
signal oRs232Tx : aoRs232Tx;
 
type aState is (id, arg, waitforchange);
type aState is (id, arg, waitforchange, data, crc);
type aReg is record
State : aState;
Counter : natural;
60,7 → 60,7
end record aReg;
 
constant cDefaultReg : aReg := (
State => id,
State => waitforchange,
Counter => 3,
ReceivedContent => cDefaultSdCmdContent,
ValidContent => cDefaultSdCmdContent,
71,6 → 71,9
signal NextR : aReg;
signal ReceivedContent : aSdCmdContent;
signal oReceivedContentValid : std_ulogic;
signal ReceivedData : std_ulogic_vector(511 downto 0);
signal ReceivedDataValid : std_ulogic;
signal ReceivedCrc : std_ulogic_vector(15 downto 0);
 
begin
 
77,8 → 80,8
oDigitAdr <= "101"; -- DIGIT_6
oTx <= oRs232Tx.Tx;
 
iRs232Tx.Transmit <= cActivated;
iRs232Tx.Data <= R.Data;
iRs232Tx.Transmit <= cActivated;
iRs232Tx.Data <= R.Data;
iRs232Tx.DataAvailable <= R.DataAvailable;
 
-- Send ReceivedContent via Rs232
93,7 → 96,7
end if;
end process Rs232_Send;
 
Rs232_comb : process (oRs232Tx.DataWasRead, ReceivedContent, oReceivedContentValid, R)
Rs232_comb : process (oRs232Tx.DataWasRead, ReceivedContent, oReceivedContentValid, ReceivedDataValid, ReceivedData, ReceivedCrc, R)
begin
NextR <= R;
 
101,9 → 104,14
when waitforchange =>
NextR.DataAvailable <= cInactivated;
 
if (R.ReceivedContent /= R.ValidContent) then
NextR.ReceivedContent <= R.ValidContent;
NextR.State <= id;
-- if (R.ReceivedContent /= R.ValidContent) then
-- NextR.ReceivedContent <= R.ValidContent;
-- NextR.State <= id;
-- end if;
 
if (ReceivedDataValid = cActivated) then
NextR.Counter <= 63;
NextR.State <= data;
end if;
 
when id =>
129,6 → 137,34
end if;
end if;
 
when data =>
NextR.DataAvailable <= cActivated;
NextR.Data <= ReceivedData(R.Counter * 8 + 7 downto R.Counter * 8);
if (oRs232Tx.DataWasRead = cActivated) then
NextR.DataAvailable <= cInactivated;
if (R.Counter = 0) then
NextR.Counter <= 1;
NextR.State <= crc;
else
NextR.Counter <= R.Counter - 1;
end if;
end if;
 
when crc =>
NextR.DataAvailable <= cActivated;
NextR.Data <= ReceivedCrc(R.Counter * 8 + 7 downto R.Counter * 8);
if (oRs232Tx.DataWasRead = cActivated) then
NextR.DataAvailable <= cInactivated;
if (R.Counter = 0) then
NextR.Counter <= 0;
NextR.State <= waitforchange;
else
NextR.Counter <= R.Counter - 1;
end if;
end if;
 
when others =>
report "Unhandled state" severity error;
end case;
141,7 → 177,7
SDTop_inst : entity work.SdTop(Rtl)
port map (
iClk => iClk,
iClk => iClk,
inResetAsync => inResetAsync,
ioCmd => ioCmd,
oSclk => oSclk,
148,6 → 184,9
ioData => ioData,
oReceivedContent => ReceivedContent,
oReceivedContentValid => oReceivedContentValid,
oReceivedData => ReceivedData,
oReceivedDataValid => ReceivedDataValid,
oCrc => ReceivedCrc,
oLedBank => oLedBank
);
 
/sdhc-sc-core/trunk/src/grpSd/unitSdCardModel/src/SdCardModel.sv
192,11 → 192,11
repeat(2) @ICmd.cb;
 
// send dummy SCR
for (int i = 0; i < 512; i++)
for (int i = 0; i < 64; i++)
data.push_back(0);
data[511-50] = 1;
data[511-48] = 1;
data[63-50] = 1;
data[63-48] = 1;
 
sddata = new(standard, widewidth);
sddata.send(ICmd, data);
/sdhc-sc-core/trunk/src/grpSd/pkgSd/src/Sd-p.vhdl
110,6 → 110,7
 
type aSdDataBusMode is (standard, wide);
type aSdDataMode is (usual, widewidth);
type aSdDataBits is (ScrBits);
 
-- Types for entities
-- between SdController and SdCmd
139,19 → 140,21
 
-- between SdController and SdData
type aSdDataFromController is record
Mode : aSdDataBusMode; -- select 1 bit or 4 bit mode
DataMode : aSdDataMode; -- select usual or wide width data
DataBlock : aSdDataBlock; -- DataBlock to send to card
Valid : std_ulogic; -- valid, when the datablock is valid and has to be sent
CheckBusy : std_ulogic; -- check for busy signaling
Mode : aSdDataBusMode; -- select 1 bit or 4 bit mode
DataMode : aSdDataMode; -- select usual or wide width data
ExpectBits : aSdDataBits; -- how many bits are expected in wide with data mode
DataBlock : aSdDataBlock; -- DataBlock to send to card
Valid : std_ulogic; -- valid, when the datablock is valid and has to be sent
CheckBusy : std_ulogic; -- check for busy signaling
end record aSdDataFromController;
 
constant cDefaultSdDataFromController : aSdDataFromController := (
Mode => standard,
DataMode => usual,
DataBlock => (others => '0'),
Valid => cInactivated,
CheckBusy => cInactivated);
Mode => standard,
DataMode => usual,
DataBlock => (others => '0'),
ExpectBits => ScrBits,
Valid => cInactivated,
CheckBusy => cInactivated);
 
type aSdDataToController is record
Ack : std_ulogic; -- gets asserted when a datablock was sent to the card
/sdhc-sc-core/trunk/src/grpSd/unitSdTop/src/SdTop-Rtl-ea.vhdl
24,6 → 24,9
-- Status
oReceivedContent : out aSdCmdContent;
oReceivedContentValid : out std_ulogic;
oReceivedData : out std_ulogic_vector(511 downto 0);
oReceivedDataValid : out std_ulogic;
oCrc : out std_ulogic_vector(15 downto 0);
oLedBank : out aLedBank
);
end entity SdTop;
40,6 → 43,8
oSclk <= iClk;
oReceivedContent <= SdCmdToController.Content;
oReceivedContentValid <= SdCmdToController.Valid;
oReceivedData <= SdDataToController.DataBlock(511 downto 0);
oReceivedDataValid <= SdDataToController.Valid;
 
SdController_inst: entity work.SdController(Rtl)
port map (
68,7 → 73,8
inResetAsync => inResetAsync,
iSdDataFromController => SdDataFromController,
oSdDataToController => SdDataToController,
ioData => ioData
ioData => ioData,
oCrc => oCrc
);
 
end architecture Rtl;
/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/sim/wave.do
15,6 → 15,9
add wave -noupdate -format Literal /Testbed/top/nextr
add wave -noupdate -format Literal /Testbed/top/receivedcontent
add wave -noupdate -format Logic /Testbed/top/oreceivedcontentvalid
add wave -noupdate -format Literal /Testbed/top/receiveddata
add wave -noupdate -format Logic /Testbed/top/receiveddatavalid
add wave -noupdate -format Literal /Testbed/top/receivedcrc
add wave -noupdate -divider controller
add wave -noupdate -format Literal /Testbed/top/sdtop_inst/sdcontroller_inst/isdcmd
add wave -noupdate -format Literal /Testbed/top/sdtop_inst/sdcontroller_inst/osdcmd
33,7 → 36,7
add wave -noupdate -format Literal /Testbed/top/sdtop_inst/sdcmd_inst/o
add wave -noupdate -divider data
add wave -noupdate -format Literal /Testbed/top/sdtop_inst/sddata_inst/isddatafromcontroller
add wave -noupdate -format Literal /Testbed/top/sdtop_inst/sddata_inst/osddatatocontroller
add wave -noupdate -format Literal -expand /Testbed/top/sdtop_inst/sddata_inst/osddatatocontroller
add wave -noupdate -format Literal /Testbed/top/sdtop_inst/sddata_inst/crcin
add wave -noupdate -format Literal /Testbed/top/sdtop_inst/sddata_inst/crcout
add wave -noupdate -format Literal /Testbed/top/sdtop_inst/sddata_inst/crcdatain
42,7 → 45,7
add wave -noupdate -divider rs232
add wave -noupdate -format Literal /Testbed/top/rs232tx_inst/r
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {1545140 ns} 0}
WaveRestoreCursors {{Cursor 1} {100845269 ns} 0}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
57,4 → 60,4
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {0 ns} {7401261 ns}
WaveRestoreZoom {100038863 ns} {107440124 ns}
/sdhc-sc-core/trunk/src/grpSd/unitSdController/src/SdController-Rtl-a.vhdl
306,6 → 306,7
when CheckBusWidth =>
if (R.SendCMD55 = cInactivated) then
NextR.ToSdData.DataMode <= widewidth;
NextR.ToSdData.ExpectBits <= ScrBits;
 
case R.Region is
when send =>

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