URL
https://opencores.org/ocsvn/xgate/xgate/trunk
Subversion Repositories xgate
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- from Rev 100 to Rev 101
- ↔ Reverse comparison
Rev 100 → Rev 101
/xgate/trunk/sw/xgate_test_code/pc_rollover/pc_rollover.s
0,0 → 1,135
; 345678901234567890123456789012345678901234567890123456789012345678901234567890 |
; PC underflow/overflow test for xgate RISC processor core |
; Bob Hayes - Jan 21 2012 |
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CPU XGATE |
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;------------------------------------------------------------------------------- |
; Error Code - Program should never get here |
;------------------------------------------------------------------------------- |
ORG $0000 ; |
_START_OF_MEM |
LDL R2,#$04 ; Sent Message to Testbench Error Register |
LDH R2,#$80 |
LDL R3,#$08 |
STB R3,(R2,#0) |
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SIF |
RTS |
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BRA _START_OF_MEM ; Final hex code for test will need hack |
BRA _START_OF_MEM ; Final hex code for test will need hack |
BRA _START_OF_MEM ; Final hex code for test will need hack |
BRA _START_OF_MEM ; Final hex code for test will need hack |
BRA _START_OF_MEM ; Final hex code for test will need hack |
BRA _START_OF_MEM ; Final hex code for test will need hack |
BRA _START_OF_MEM ; Final hex code for test will need hack |
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;------------------------------------------------------------------------------- |
; Backward branch past #$0000 |
;------------------------------------------------------------------------------- |
ORG $0200 ; |
_START3 |
LDL R2,#$00 ; Sent Message to Testbench Check Point Register |
LDH R2,#$80 |
LDL R3,#$01 |
STB R3,(R2,#0) |
STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register |
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BRA _START_OF_MEM ; Final hex code for test will need hack |
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;------------------------------------------------------------------------------- |
; Dummy space to store initial variables for default interrupts |
ORG $2000 ; with comment |
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V_PTR DC.W $0000 ; All Variable Pointers are set to here |
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DC.W $AAAA |
DS.W 8 |
DC.B $56 |
DS.B 11 |
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ALIGN 1 |
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;------------------------------------------------------------------------------- |
; Place where undefined interrupts go |
;------------------------------------------------------------------------------- |
_ERROR |
LDL R2,#$04 ; Sent Message to Testbench Error Register |
LDH R2,#$80 |
LDL R3,#$ff |
STB R3,(R2,#0) |
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SIF |
RTS |
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;------------------------------------------------------------------------------- |
ORG $8800 ; $8000 reserved for testbench |
DC.W $5555 ; reserve two words at channel 0 |
DC.W $AAAA |
; channel 1 |
DC.W _START ; point to start address |
DC.W V_PTR ; point to initial variables |
; channel 2 |
DC.W _START2 ; point to start address |
DC.W V_PTR ; point to initial variables |
; channel 3 |
DC.W _START3 ; point to start address |
DC.W V_PTR ; point to initial variables |
; channel 4 |
DC.W _ERROR ; point to start address |
DC.W V_PTR ; point to initial variables |
; channel 5 |
DC.W _ERROR ; point to start address |
DC.W V_PTR ; point to initial variables |
; channel 6 |
DC.W _ERROR ; point to start address |
DC.W V_PTR ; point to initial variables |
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;------------------------------------------------------------------------------- |
ORG $fe00 |
DC.W $3c3c |
DC.W $9696 |
DC.W $a5a5 |
DC.W $5a5a |
DC.W $7878 |
DC.W $8181 |
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;------------------------------------------------------------------------------- |
; Foward branch past #$ffff |
;------------------------------------------------------------------------------- |
ORG $FFC0 ; |
_START2 |
LDL R2,#$00 ; Sent Message to Testbench Check Point Register |
LDH R2,#$80 |
LDL R3,#$01 |
STB R3,(R2,#0) |
STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register |
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BRA _END_OFCODE ; Final hex code for test will need hack |
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;------------------------------------------------------------------------------- |
; Test PC single step past #$ffff |
;------------------------------------------------------------------------------- |
ORG $FFE8 ; |
_START |
LDL R2,#$00 ; Sent Message to Testbench Check Point Register |
LDH R2,#$80 |
LDL R3,#$01 |
STB R3,(R2,#0) |
STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register |
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NOP |
NOP |
NOP |
NOP |
NOP |
_END_OFCODE |
NOP |
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/xgate/trunk/sw/xgate_test_code/pc_rollover/make_core.scr
0,0 → 1,3
../../tools/HSW12ASM/hsw12asm.pl pc_rollover.s |
../../tools/s_2_verilog pc_rollover_pag.s28 |
mv pc_rollover_pag.v ../../../bench/verilog/pc_rollover.v |
xgate/trunk/sw/xgate_test_code/pc_rollover/make_core.scr
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
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