URL
https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk
Subversion Repositories openrisc_2011-10-31
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 99 to Rev 100
- ↔ Reverse comparison
Rev 99 → Rev 100
/openrisc/trunk/or1ksim/sim-config.h
113,6 → 113,7
int hazards; /* dependency hazards analysis */ |
int dependstats; /* dependency statistics */ |
int sbuf_len; /* length of store buffer, 0=disabled */ |
int hardfloat; /* whether hardfloat is enabled */ |
} cpu; |
|
struct |
/openrisc/trunk/or1ksim/cpu/or32/insnset.c
3,9 → 3,11
Copyright (C) 1999 Damjan Lampret, lampret@opencores.org |
2000-2002 Marko Mlinar, markom@opencores.org |
Copyright (C) 2008 Embecosm Limited |
Copyright (C) 2009 Jungsook yang, jungsook.yang@uci.edu |
|
Contributor Jeremy Bennett <jeremy.bennett@embecosm.com> |
|
Contributor Julius Baxter julius@orsoc.se |
|
This file is part of OpenRISC 1000 Architectural Simulator. |
|
This program is free software; you can redistribute it and/or modify it |
541,65 → 543,139
/******* Floating point instructions *******/ |
/* Single precision */ |
INSTRUCTION (lf_add_s) { |
SET_PARAM0((float)PARAM1 + (float)PARAM2); |
if (config.cpu.hardfloat) { |
FLOAT param0, param1, param2; |
param1.hval = (uorreg_t)PARAM1; |
param2.hval = (uorreg_t)PARAM2; |
param0.fval = param1.fval + param2.fval; |
SET_PARAM0(param0.hval); |
} else l_invalid(); |
} |
INSTRUCTION (lf_div_s) { |
SET_PARAM0((float)PARAM1 / (float)PARAM2); |
if (config.cpu.hardfloat) { |
FLOAT param0, param1, param2; |
param1.hval = (uorreg_t)PARAM1; |
param2.hval = (uorreg_t)PARAM2; |
param0.fval = param1.fval / param2.fval; |
SET_PARAM0(param0.hval); |
} else l_invalid(); |
} |
INSTRUCTION (lf_ftoi_s) { |
// set_operand32(0, freg[get_operand(1)], &breakpoint); |
if (config.cpu.hardfloat) { |
// no other way appeared to work --jb |
float tmp_f; memcpy((void*)&tmp_f, (void*)&PARAM1, sizeof(float)); |
SET_PARAM0((int)tmp_f); |
} else l_invalid(); |
} |
INSTRUCTION (lf_itof_s) { |
// freg[get_operand(0)] = eval_operand32(1, &breakpoint); |
if (config.cpu.hardfloat) { |
FLOAT param0; |
param0.fval = (float)((int)PARAM1); |
SET_PARAM0(param0.hval); |
} else l_invalid(); |
} |
INSTRUCTION (lf_madd_s) { |
SET_PARAM0((float)PARAM0 + (float)PARAM1 * (float)PARAM2); |
if (config.cpu.hardfloat) { |
FLOAT param0,param1, param2; |
param0.hval = PARAM0; |
param1.hval = PARAM1; |
param2.hval = PARAM2; |
param0.fval += param1.fval * param2.fval; |
SET_PARAM0(param0.hval); |
} else l_invalid(); |
} |
INSTRUCTION (lf_mul_s) { |
SET_PARAM0((float)PARAM1 * (float)PARAM2); |
if (config.cpu.hardfloat) { |
FLOAT param0, param1, param2; |
param1.hval = (uorreg_t)PARAM1; |
param2.hval = (uorreg_t)PARAM2; |
param0.fval = param1.fval * param2.fval; |
SET_PARAM0(param0.hval); |
} else l_invalid(); |
} |
INSTRUCTION (lf_rem_s) { |
float temp = (float)PARAM1 / (float)PARAM2; |
SET_PARAM0(temp - (uint32_t)temp); |
if (config.cpu.hardfloat) { |
FLOAT param0, param1, param2; |
param1.hval = PARAM1; |
param2.hval = PARAM2; |
param0.fval = param1.fval / param2.fval; |
SET_PARAM0(param0.hval); |
} else l_invalid(); |
} |
INSTRUCTION (lf_sfeq_s) { |
if((float)PARAM0 == (float)PARAM1) |
if (config.cpu.hardfloat) { |
FLOAT param0, param1; |
param0.hval = PARAM0; |
param1.hval = PARAM1; |
if(param0.fval == param1.fval) |
cpu_state.sprs[SPR_SR] |= SPR_SR_F; |
else |
cpu_state.sprs[SPR_SR] &= ~SPR_SR_F; |
} else l_invalid(); |
} |
INSTRUCTION (lf_sfge_s) { |
if((float)PARAM0 >= (float)PARAM1) |
if (config.cpu.hardfloat) { |
FLOAT param0, param1; |
param0.hval = PARAM0; |
param1.hval = PARAM1; |
if(param0.fval >= param1.fval) |
cpu_state.sprs[SPR_SR] |= SPR_SR_F; |
else |
cpu_state.sprs[SPR_SR] &= ~SPR_SR_F; |
} else l_invalid(); |
} |
INSTRUCTION (lf_sfgt_s) { |
if((float)PARAM0 > (float)PARAM1) |
if (config.cpu.hardfloat) { |
FLOAT param0, param1; |
param0.hval = PARAM0; |
param1.hval = PARAM1; |
if(param0.fval > param1.fval) |
cpu_state.sprs[SPR_SR] |= SPR_SR_F; |
else |
cpu_state.sprs[SPR_SR] &= ~SPR_SR_F; |
} else l_invalid(); |
} |
INSTRUCTION (lf_sfle_s) { |
if((float)PARAM0 <= (float)PARAM1) |
if (config.cpu.hardfloat) { |
FLOAT param0, param1; |
param0.hval = PARAM0; |
param1.hval = PARAM1; |
if(param0.fval <= param1.fval) |
cpu_state.sprs[SPR_SR] |= SPR_SR_F; |
else |
cpu_state.sprs[SPR_SR] &= ~SPR_SR_F; |
} else l_invalid(); |
} |
INSTRUCTION (lf_sflt_s) { |
if((float)PARAM0 < (float)PARAM1) |
if (config.cpu.hardfloat) { |
FLOAT param0, param1; |
param0.hval = PARAM0; |
param1.hval = PARAM1; |
if(param0.fval < param1.fval) |
cpu_state.sprs[SPR_SR] |= SPR_SR_F; |
else |
cpu_state.sprs[SPR_SR] &= ~SPR_SR_F; |
} else l_invalid(); |
} |
INSTRUCTION (lf_sfne_s) { |
if((float)PARAM0 != (float)PARAM1) |
if (config.cpu.hardfloat) { |
FLOAT param0, param1; |
param0.hval = PARAM0; |
param1.hval = PARAM1; |
if(param0.fval != param1.fval) |
cpu_state.sprs[SPR_SR] |= SPR_SR_F; |
else |
cpu_state.sprs[SPR_SR] &= ~SPR_SR_F; |
} else l_invalid(); |
} |
INSTRUCTION (lf_sub_s) { |
SET_PARAM0((float)PARAM1 - (float)PARAM2); |
if (config.cpu.hardfloat) { |
FLOAT param0, param1, param2; |
param1.hval = PARAM1; |
param2.hval = PARAM2; |
param0.fval = param1.fval - param2.fval; |
SET_PARAM0(param0.hval); |
} else l_invalid(); |
} |
|
/******* Custom instructions *******/ |
614,3 → 690,11
} |
INSTRUCTION (l_cust4) { |
} |
INSTRUCTION (lf_cust1) { |
} |
INSTRUCTION (lf_cust2) { |
} |
INSTRUCTION (lf_cust3) { |
} |
INSTRUCTION (lf_cust4) { |
} |
/openrisc/trunk/or1ksim/cpu/or32/generate.c
314,6 → 314,7
|
fprintf (fo, "/* This file was automatically generated by generate (see\n"); |
fprintf (fo, " cpu/or32/generate.c) */\n\n"); |
fprintf (fo, "typedef union {\n\tfloat fval;\n\tuint32_t hval;\n} FLOAT;\n\n"); |
fprintf (fo, "static void decode_execute (struct iqueue_entry *current)\n{\n"); |
fprintf (fo, " uint32_t insn = current->insn;\n"); |
out_lines = 5; |
/openrisc/trunk/or1ksim/cpu/common/labels.c
58,10 → 58,10
add_label (oraddr_t addr, char *name) |
{ |
struct label_entry **tmp; |
tmp = &(label_hash[addr % LABELS_HASH_SIZE]); |
for (; *tmp; tmp = &((*tmp)->next)); |
*tmp = malloc (sizeof (**tmp)); |
(*tmp)->name = malloc (strlen (name) + 1); |
tmp = &(label_hash[addr % LABELS_HASH_SIZE]); |
for (; *tmp; tmp = &((*tmp)->next)); // Find the next NULL label entry pointer (loop while the pointer de-refernce is non-NULL) |
*tmp = malloc (sizeof (**tmp)); // allocate space for the pointer to the hash entry pointer |
(*tmp)->name = malloc (strlen (name) + 1); // now allocate space for the name string |
(*tmp)->addr = addr; |
strcpy ((*tmp)->name, name); |
(*tmp)->next = NULL; |
/openrisc/trunk/or1ksim/doc/or1ksim.info
1,5 → 1,7
This is ../../doc/or1ksim.info, produced by makeinfo version 4.13 from |
../../doc/or1ksim.texi. |
This is |
/home/jules/Documents/openrisc_svn/openrisc/trunk/or1ksim/doc/or1ksim.info, |
produced by makeinfo version 4.13 from |
/home/jules/Documents/openrisc_svn/openrisc/trunk/or1ksim/doc/or1ksim.texi. |
|
INFO-DIR-SECTION Embedded development |
START-INFO-DIR-ENTRY |
1091,6 → 1093,8
When the store buffer is active, stores are accumulated and |
committed when I/O is idle. |
|
`hardfloat = 0|1' |
If 1, hardfloat instructions are enabled. Default value 0. |
|
|
File: or1ksim.info, Node: Memory Configuration, Next: Memory Management Configuration, Prev: CPU Configuration, Up: Core OpenRISC Configuration |
3666,6 → 3670,7
* GPIO_VAPI_INTE (GPIO verification): Verification API. (line 110) |
* GPIO_VAPI_PTRIG (GPIO verification): Verification API. (line 113) |
* GPIO_VAPI_RGPIO (GPIO verification): Verification API. (line 107) |
* hardfloat (CPU configuration): CPU Configuration. (line 110) |
* hazards (CPU configuration): CPU Configuration. (line 74) |
* heads (ATA/ATAPI device configuration): Disc Interface Configuration. |
(line 121) |
4122,54 → 4127,54
|
|
Tag Table: |
Node: Top814 |
Node: Installation1224 |
Node: Preparation1471 |
Node: Configuring the Build1766 |
Node: Build and Install7245 |
Node: Known Issues8091 |
Node: Usage10232 |
Node: Standalone Simulator10446 |
Node: Profiling Utility13349 |
Node: Memory Profiling Utility14259 |
Node: Simulator Library15624 |
Node: Configuration21816 |
Node: Configuration File Format22425 |
Node: Configuration File Preprocessing22717 |
Node: Configuration File Syntax23088 |
Node: Simulator Configuration25873 |
Node: Simulator Behavior26164 |
Node: Verification API Configuration30208 |
Node: CUC Configuration32148 |
Node: Core OpenRISC Configuration34065 |
Node: CPU Configuration34567 |
Node: Memory Configuration38602 |
Node: Memory Management Configuration45060 |
Node: Cache Configuration47437 |
Node: Interrupt Configuration49823 |
Node: Power Management Configuration50559 |
Node: Branch Prediction Configuration51836 |
Node: Debug Interface Configuration53196 |
Node: Peripheral Configuration57416 |
Node: Memory Controller Configuration58042 |
Node: UART Configuration61456 |
Node: DMA Configuration64975 |
Node: Ethernet Configuration66842 |
Node: GPIO Configuration70818 |
Node: Display Interface Configuration72451 |
Node: Frame Buffer Configuration74760 |
Node: Keyboard Configuration76624 |
Node: Disc Interface Configuration78862 |
Node: Generic Peripheral Configuration83805 |
Node: Interactive Command Line86100 |
Node: Verification API93074 |
Node: Code Internals97504 |
Node: Coding Conventions98064 |
Node: Global Data Structures102491 |
Node: Concepts105148 |
Ref: Output Redirection105293 |
Node: Internal Debugging105832 |
Node: GNU Free Documentation License106329 |
Node: Index128736 |
Node: Top918 |
Node: Installation1328 |
Node: Preparation1575 |
Node: Configuring the Build1870 |
Node: Build and Install7349 |
Node: Known Issues8195 |
Node: Usage10336 |
Node: Standalone Simulator10550 |
Node: Profiling Utility13453 |
Node: Memory Profiling Utility14363 |
Node: Simulator Library15728 |
Node: Configuration21920 |
Node: Configuration File Format22529 |
Node: Configuration File Preprocessing22821 |
Node: Configuration File Syntax23192 |
Node: Simulator Configuration25977 |
Node: Simulator Behavior26268 |
Node: Verification API Configuration30312 |
Node: CUC Configuration32252 |
Node: Core OpenRISC Configuration34169 |
Node: CPU Configuration34671 |
Node: Memory Configuration38788 |
Node: Memory Management Configuration45246 |
Node: Cache Configuration47623 |
Node: Interrupt Configuration50009 |
Node: Power Management Configuration50745 |
Node: Branch Prediction Configuration52022 |
Node: Debug Interface Configuration53382 |
Node: Peripheral Configuration57602 |
Node: Memory Controller Configuration58228 |
Node: UART Configuration61642 |
Node: DMA Configuration65161 |
Node: Ethernet Configuration67028 |
Node: GPIO Configuration71004 |
Node: Display Interface Configuration72637 |
Node: Frame Buffer Configuration74946 |
Node: Keyboard Configuration76810 |
Node: Disc Interface Configuration79048 |
Node: Generic Peripheral Configuration83991 |
Node: Interactive Command Line86286 |
Node: Verification API93260 |
Node: Code Internals97690 |
Node: Coding Conventions98250 |
Node: Global Data Structures102677 |
Node: Concepts105334 |
Ref: Output Redirection105479 |
Node: Internal Debugging106018 |
Node: GNU Free Documentation License106515 |
Node: Index128922 |
|
End Tag Table |
/openrisc/trunk/or1ksim/doc/or1ksim.texi
1315,6 → 1315,9
When the store buffer is active, stores are accumulated and committed |
when I/O is idle. |
|
@item hardfloat = 0|1 |
@cindex @code{hardfloat} (CPU configuration) |
If 1, hardfloat instructions are enabled. Default value 0. |
@end table |
|
@node Memory Configuration |
/openrisc/trunk/or1ksim/doc/version.texi
1,4 → 1,4
@set UPDATED 19 May 2010 |
@set UPDATED 25 May 2010 |
@set UPDATED-MONTH May 2010 |
@set EDITION 2010-05-20 |
@set VERSION 2010-05-20 |
/openrisc/trunk/or1ksim/cpu-config.c
207,6 → 207,11
config.cpu.sbuf_len = val.int_val; |
} |
|
static void |
cpu_hardfloat (union param_val val, void *dat) |
{ |
config.cpu.hardfloat = val.int_val; |
} |
/*---------------------------------------------------------------------------*/ |
/*!Register the functions to handle a section cpu |
|
231,5 → 236,6
reg_config_param (sec, "hazards", paramt_int, cpu_hazards); |
reg_config_param (sec, "dependstats", paramt_int, cpu_dependstats); |
reg_config_param (sec, "sbuf_len", paramt_int, cpu_sbuf_len); |
reg_config_param (sec, "hardfloat", paramt_int, cpu_hardfloat); |
|
} /* reg_cpu_sec() */ |
/openrisc/trunk/or1ksim/profiler.c
27,6 → 27,7
by or1ksim. (use profile command interactively, when running or1ksim, or |
separate psim command). */ |
|
#define PROF_DEBUG 0 |
|
/* Autoconf and/or portability configuration */ |
#include "config.h" |
38,7 → 39,7
#include "argtable2.h" |
|
/*! Maximum stack frames that can be profiled */ |
#define MAX_STACK 1024 |
#define MAX_STACK 262144 |
|
/*! Data structure representing information about a stack frame */ |
struct stack_struct |
100,6 → 101,7
{ |
fprof = runtime.sim.fprof; |
reopened = 1; |
if (PROF_DEBUG) printf("reopened=1\n"); |
rewind (fprof); |
} |
else |
110,9 → 112,10
fprintf (stderr, "Cannot open profile file: %s\n", fprofname); |
return 1; |
} |
|
int ctr =0; |
while (1) |
{ |
if (PROF_DEBUG) printf("%d ",ctr++); |
char dir = fgetc (fprof); |
line++; |
if (dir == '+') |
126,6 → 129,7
{ |
prof_cycles = stack[nstack].cycles; |
nstack++; |
if (PROF_DEBUG) printf("+ 0x%.8x nstack %d\n",stack[nstack-1].raddr, nstack); |
if (nstack > maxstack) |
maxstack = nstack; |
} |
140,6 → 144,7
{ |
int i; |
prof_cycles = s.cycles; |
if (PROF_DEBUG) printf("- 0x%.8x nstack %d\n",s.raddr ,nstack); |
for (i = nstack - 1; i >= 0; i--) |
if (stack[i].raddr == s.raddr) |
break; |
204,7 → 209,7
|
/* If we have reopened the file, we need to add end of "[outside functions]" */ |
if (reopened) |
{ |
{ |
prof_cycles = runtime.sim.cycles; |
/* pop everything above current from stack, |
if more than one, something went wrong */ |
/openrisc/trunk/or1ksim/profiler.h
28,7 → 28,7
#define PROFILER__H |
|
/*! Maximum number of functions that can be profiled */ |
#define MAX_FUNCS 1024 |
#define MAX_FUNCS 8192 |
|
/*! Data structure for information about functions */ |
struct func_struct { |
/openrisc/trunk/or1ksim/sim-config.c
142,6 → 142,7
config.cpu.hazards = 0; |
config.cpu.dependstats = 0; |
config.cpu.sbuf_len = 0; |
config.cpu.hardfloat = 0; |
|
/* Data cache (IC is set dynamically). Also set relevant SPR bits */ |
config.dc.enabled = 0; |