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URL https://opencores.org/ocsvn/or1k/or1k/trunk

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  • This comparison shows the changes necessary to convert path 
    /
    from Rev 1000 to Rev 1001
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Rev 1000 → Rev 1001

/trunk/or1ksim/cuc/verilog.c
185,7 → 185,7
{
while (dep) {
assert (f->INSN(dep->ref).type & IT_MEMORY || f->INSN(dep->ref).index == II_CALL);
GEN (" %c_stb[%i] <= #Tp 1'b0;\n", f->INSN(dep->ref).index == II_CALL ? 'f'
GEN (" %c_stb[%i] <= #Tp 1'b0;\n", f->INSN(dep->ref).index == II_CALL ? 'f'
: II_IS_LOAD (f->INSN(dep->ref).index) ? 'l' : 's', find_lsc_index (f, dep->ref));
dep = dep->next;
}
533,18 → 533,19
for (i = 0; i < f->nmsched; i++)
if (f->mtype[i] & MT_STORE) {
char t[30];
GEN ("%s%s", cur_store++ ? ", " : "", print_op_v (f, t, f->msched[i], 0));
GEN ("%s%s", cur_store++ ? " or " : "", print_op_v (f, t, f->msched[i], 0));
}
cur_store = 0;
GEN (")\nbegin\n");
for (i = 0; i < f->nmsched; i++)
if (f->mtype[i] & MT_STORE) {
char t[30];
GEN (" %sif (s_stb[%i]) swb_dat_o = %s;\n", i ? "else " : "", cur_store++,
print_op_v (f, t, f->msched[i], 0));
//PRINTF ("msched[%i] = %x (mtype %x) %x\n", i, f->msched[i], f->mtype[i], f->INSN(f->msched[i]).op[0]);
}
for (i = 0; i < f->nmsched; i++) if (f->mtype[i] & MT_STORE) {
char t[30];
GEN (" %sif (s_stb[%i]) swb_dat_o = %s;\n", cur_store == 0 ? "" : "else ", cur_store,
print_op_v (f, t, f->msched[i], 0));
cur_store++;
//PRINTF ("msched[%i] = %x (mtype %x) %x\n", i, f->msched[i], f->mtype[i], f->INSN(f->msched[i]).op[0]);
}
GEN (" else swb_dat_o = 32'hx;\n");
GEN ("end\n");
}
 
564,16 → 565,36
int cur = 0;
char t[30];
GEN ("\n/* %s state machine */\n", s);
GEN ("always @(posedge clk or posedge rst)\n");
GEN (" if (rst) %c_stb <= #Tp %i'h0;\n", c, j == 0 ? nloads : j == 1 ? nstores : ncalls);
GEN (" else begin\n");
for (i = 0; i < f->nmsched; i++)
if (j == 0 && f->mtype[i] & MT_LOAD
|| j == 1 && f->mtype[i] & MT_STORE
|| j == 2 && f->mtype[i] & MT_CALL) {
dep_list *dep = f->INSN(f->msched[i]).dep;
assert (f->INSN(f->msched[i]).opt[1] & (OPT_REF | OPT_REGISTER));
GEN (" if (");
print_deps (fo, f, REF_BB(f->msched[i]), f->INSN(f->msched[i]).dep, 1);
GEN (") begin\n");
print_turn_off_dep (fo, f, dep);
GEN (" %c_stb[%i] <= #Tp 1'b1;\n", c, cur++);
GEN (" end\n");
}
GEN (" if (%c_end[%i]) %c_stb <= #Tp %i'h0;\n", c, cur - 1, c, cur);
GEN (" end\n");
 
GEN ("\n/* %s state generator machine */\n", s);
GEN ("always @(");
for (i = 0; i < f->nmsched; i++) {
print_op_v (f, t, f->msched[i], 1); break;
GEN (" or ");
GEN ("t%x_%x", REF_BB(f->INSN(f->msched[i]).op[1]), REF_I(f->INSN(f->msched[i]).op[1]));
GEN (" or ");
print_op_v (f, t, f->msched[i], 1);
GEN ("%s or ", t);
}
print_deps (fo, f, REF_BB(f->msched[i]), f->INSN(f->msched[i]).dep, 1);
GEN (" or %c_end)\n", c);
GEN ("begin\n");
GEN ("bb_start_r");
if (nloads) GEN (" or l_end");
if (nstores) GEN (" or s_end");
GEN (")\n");
GEN ("begin\n ");
cucdebug (1, "%s\n", s);
for (i = 0; i < f->nmsched; i++)
if (j == 0 && f->mtype[i] & MT_LOAD
582,13 → 603,11
dep_list *dep = f->INSN(f->msched[i]).dep;
cucdebug (1, "msched[%i] = %x (mtype %x)\n", i, f->msched[i], f->mtype[i]);
assert (f->INSN(f->msched[i]).opt[1] & (OPT_REF | OPT_REGISTER));
GEN (" if (");
GEN ("if (");
print_deps (fo, f, REF_BB(f->msched[i]), f->INSN(f->msched[i]).dep, 1);
GEN (") begin\n");
print_turn_off_dep (fo, f, dep);
GEN (" %c_stb[%i] <= #Tp 1'b1;\n", c, cur++);
GEN (" %cwb_cycstb_o <= #Tp 1'b1;\n", c);
GEN (" %cwb_sel_o[3:0] <= #Tp 4'b", c);
GEN (" %cwb_cycstb_o = 1'b1;\n", c);
GEN (" %cwb_sel_o[3:0] = 4'b", c);
switch (f->mtype[i] & MT_WIDTH) {
case 1: GEN ("0001 << (%s & 32'h3);\n",
print_op_v (f, t, f->msched[i], 1)); break;
597,18 → 616,22
case 4: GEN ("1111;\n"); break;
default: assert (0);
}
GEN (" %cwb_linbrst_o <= #Tp 1'b%i;\n", c,
GEN (" %cwb_linbrst_o = 1'b%i;\n", c,
(f->mtype[i] & MT_BURST) && !(f->mtype[i] & MT_BURSTE) ? 1 : 0);
GEN (" %cwb_adr_o <= #Tp t%x_%x & ~32'h3;\n", c,
GEN (" %cwb_adr_o = t%x_%x & ~32'h3;\n", c,
REF_BB(f->INSN(f->msched[i]).op[1]), REF_I(f->INSN(f->msched[i]).op[1]));
GEN (" end\n");
GEN (" end else ");
}
GEN (" if (%c_end[%i]) begin\n", c, cur - 1);
GEN (" %c_stb <= #Tp %i'h0;\n", c, cur);
GEN (" %cwb_cycstb_o <= #Tp 1'b0;\n", c);
GEN (" %cwb_sel_o[3:0] <= #Tp 4'b0000;\n", c);
GEN (" %cwb_linbrst_o <= #Tp 1'b0;\n", c);
GEN (" %cwb_adr_o <= #Tp 32'h0;\n", c);
GEN ("if (%c_end[%i]) begin\n", c, cur - 1);
GEN (" %cwb_cycstb_o = 1'b0;\n", c);
GEN (" %cwb_sel_o[3:0] = 4'bx;\n", c);
GEN (" %cwb_linbrst_o = 1'b0;\n", c);
GEN (" %cwb_adr_o = 32'hx;\n", c);
GEN (" end else begin\n");
GEN (" %cwb_cycstb_o = 1'b0;\n", c);
GEN (" %cwb_sel_o[3:0] = 4'bx;\n", c);
GEN (" %cwb_linbrst_o = 1'b0;\n", c);
GEN (" %cwb_adr_o = 32'hx;\n", c);
GEN (" end\n");
GEN ("end\n");
}
854,6 → 877,7
GEN ("assign cuc_ack_o = cuc_stb_i && cuc_we_i && |(i_selected & main_end);\n");
}
 
/* Store/load Wishbone bridge */
for (j = 0; j < 2; j++) {
char t = j ? 's' : 'l';
GEN ("\n/* %s Wishbone bridge */\n", j ? "store" : "load");

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