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URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

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    from Rev 101 to Rev 102
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Rev 101 → Rev 102

/t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v
170,10 → 170,11
fake_mem[333] = STA_IDY; // testing IDY mode WRITE TYPE, page crossed;
fake_mem[334] = 8'h00;
fake_mem[335] = STA_IDY; // testing IDY mode WRITE TYPE, page not crossed;
fake_mem[336] = 8'h0e;
fake_mem[337] = JMP_IND; // testing absolute indirect addressing. page crossed when updating pointer.
fake_mem[338] = 8'hff;
fake_mem[339] = 8'h00;
fake_mem[336] = 8'h0e;
fake_mem[337] = INX_IMP;
fake_mem[338] = JMP_IND; // testing absolute indirect addressing. page crossed when updating pointer.
fake_mem[339] = 8'hff;
fake_mem[340] = 8'h00;
//fake_mem[337] = JMP_IND; // testing absolute indirect addressing. no page crossed when updating pointer.
//fake_mem[338] = 8'h3b;
//fake_mem[339] = 8'h00;
187,7 → 188,7
reset_n=1'b1;
 
#3000;
#4000;
$finish; // to shut down the simulation
end //initial
 
/t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
96,7 → 96,7
localparam MEM_WRITE = 1'b1;
 
reg [ADDR_SIZE_:0] pc; // program counter
reg [DATA_SIZE_:0] sp; // stack pointer
reg [ADDR_SIZE_:0] sp; // stack pointer
reg [DATA_SIZE_:0] ir; // instruction register
reg [ADDR_SIZE_:0] temp_addr; // temporary address
reg [DATA_SIZE_:0] temp_data; // temporary data
174,9 → 174,9
if (reset_n == 1'b0) begin
// all registers must assume default values
pc <= 0; // TODO: this is written somewhere. something about a reset vector. must be checked.
sp <= 0; // TODO: the default is not 0. maybe $0100 or something like that. must be checked.
sp <= 13'h100; // TODO: the default is not 0. maybe $0100 or something like that. must be checked.
ir <= 8'h00;
temp_addr <= 0;
temp_addr <= 13'h00;
temp_data <= 8'h00;
state <= RESET;
// registered outputs also receive default values
250,6 → 250,9
temp_data <= data_in;
control <= MEM_READ;
end
else begin // the special instructions will fall here: BRK, RTI, RTS...
end
end
FETCH_HIGH_CALC_INDEX: begin
pc <= next_pc;
509,6 → 512,9
else if (indirectx || indirecty) begin
next_state = READ_FROM_POINTER;
end
else begin // all the special instructions will fall here
next_state = RESET;
end
end
READ_FROM_POINTER: begin
if (indirectx) begin
529,7 → 535,7
next_state = READ_MEM_FIX_ADDR;
end
else begin
if (read || read_modify_write) begin
if (read) begin // read_modify_write was showing up here for no reason. no instruction using pointers is from that type.
next_state = READ_MEM;
end
else if (write) begin
658,7 → 664,7
branch = 1'b0;
 
case (ir)
BRK_IMP, CLC_IMP, CLD_IMP, CLI_IMP, CLV_IMP, DEX_IMP, DEY_IMP, INX_IMP, INY_IMP, NOP_IMP, PHA_IMP, PHP_IMP, PLA_IMP,
CLC_IMP, CLD_IMP, CLI_IMP, CLV_IMP, DEX_IMP, DEY_IMP, INX_IMP, INY_IMP, NOP_IMP, PHA_IMP, PHP_IMP, PLA_IMP,
PLP_IMP, RTI_IMP, RTS_IMP, SEC_IMP, SED_IMP, SEI_IMP, TAX_IMP, TAY_IMP, TSX_IMP, TXA_IMP, TXS_IMP, TYA_IMP: begin
implied = 1'b1;
end
797,6 → 803,9
JMP_IND: begin
jump_indirect = 1'b1;
end
BRK_IMP: begin
// something goes in here
end
default: begin
$write("state : %b", state);
if (reset_n == 1 && state != FETCH_OP_FIX_PC) begin // the processor is NOT being reset neither it is fixing the pc

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