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Rev 1010 → Rev 1011

/trunk/or1200/rtl/verilog/or1200_cpu.v
45,6 → 45,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.10 2002/07/14 22:17:17 lampret
// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
//
// Revision 1.9 2002/03/29 16:29:37 lampret
// Fixed some ports in instnatiations that were removed from the modules
//
302,8 → 305,10
wire pc_we;
wire [31:0] epcr;
wire [31:0] eear;
wire [`OR1200_SR_WIDTH-1:0] esr;
wire [`OR1200_SR_WIDTH-1:0] sr;
wire [`OR1200_SR_WIDTH-1:0] esr;
wire sr_we;
wire [`OR1200_SR_WIDTH-1:0] to_sr;
wire [`OR1200_SR_WIDTH-1:0] sr;
wire except_start;
wire except_started;
wire [31:0] wb_insn;
598,6 → 603,8
.esr(esr),
.except_started(except_started),
 
.sr_we(sr_we),
.to_sr(to_sr),
.sr(sr),
.branch_op(branch_op)
);
726,6 → 733,8
.esr(esr),
 
.lsu_addr(dcpu_adr_o),
.sr_we(sr_we),
.to_sr(to_sr),
.sr(sr),
.abort_ex(abort_ex)
);
/trunk/or1200/rtl/verilog/or1200_sprs.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.7 2002/03/29 15:16:56 lampret
// Some of the warnings fixed.
//
// Revision 1.6 2002/03/11 01:26:57 lampret
// Changed generation of SPR address. Now it is ORed from base and offset instead of a sum.
//
103,7 → 106,7
// Internal CPU interface
flagforw, flag_we, flag, addrbase, addrofs, dat_i, alu_op, branch_op,
epcr, eear, esr, except_started,
to_wbmux, epcr_we, eear_we, esr_we, pc_we, sr,
to_wbmux, epcr_we, eear_we, esr_we, pc_we, sr_we, to_sr, sr,
spr_dat_cfgr, spr_dat_rf, spr_dat_npc, spr_dat_ppc, spr_dat_mac,
 
// From/to other RISC units
144,7 → 147,9
output eear_we; // EEAR0 write enable
output esr_we; // ESR0 write enable
output pc_we; // PC write enable
output [`OR1200_SR_WIDTH-1:0] sr; // SR
output sr_we; // Write enable SR
output [`OR1200_SR_WIDTH-1:0] to_sr; // Data to SR
output [`OR1200_SR_WIDTH-1:0] sr; // SR
input [31:0] spr_dat_cfgr; // Data from CFGR
input [31:0] spr_dat_rf; // Data from RF
input [31:0] spr_dat_npc; // Data from NPC
181,7 → 186,6
reg write_spr; // Write SPR
reg read_spr; // Read SPR
reg [width-1:0] to_wbmux; // For l.mfspr
wire sr_we; // Write enable SR
wire cfgr_sel; // Select for cfg regs
wire rf_sel; // Select for RF
wire npc_sel; // Select for NPC
191,7 → 195,6
wire eear_sel; // Select for EEAR0
wire esr_sel; // Select for ESR0
wire [31:0] sys_data; // Read data from system SPRs
wire [`OR1200_SR_WIDTH-1:0] to_sr; // Data to SR
wire du_access; // Debug unit access
wire [`OR1200_ALUOP_WIDTH-1:0] sprs_op; // ALU operation
reg [31:0] unqualified_cs; // Unqualified chip selects
281,7 → 284,8
//
// What to write into SR
//
assign to_sr = (branch_op == `OR1200_BRANCHOP_RFE) ? esr : {1'b1, spr_dat_o[`OR1200_SR_WIDTH-2:0]};
assign to_sr = (branch_op == `OR1200_BRANCHOP_RFE) ? esr :
flag_we ? {sr[`OR1200_SR_FO:`OR1200_SR_CY], flagforw, sr[`OR1200_SR_CE:`OR1200_SR_SM]} : {1'b1, spr_dat_o[`OR1200_SR_WIDTH-2:0]};
 
//
// Selects for system SPRs
298,7 → 302,7
//
// Write enables for system SPRs
//
assign sr_we = (write_spr && sr_sel) | (branch_op == `OR1200_BRANCHOP_RFE);
assign sr_we = (write_spr && sr_sel) | (branch_op == `OR1200_BRANCHOP_RFE) | flag_we;
assign pc_we = (write_spr && (npc_sel | ppc_sel));
assign epcr_we = (write_spr && epcr_sel);
assign eear_we = (write_spr && eear_sel);
336,8 → 340,6
end
else if (sr_we)
sr <= #1 to_sr[`OR1200_SR_WIDTH-1:0];
else if (flag_we)
sr[`OR1200_SR_F] <= #1 flagforw;
 
//
// MTSPR/MFSPR interface
/trunk/or1200/rtl/verilog/or1200_except.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.12 2002/08/22 02:16:45 lampret
// Fixed IMMU bug.
//
// Revision 1.11 2002/08/18 19:54:28 lampret
// Added store buffer.
//
143,7 → 146,7
if_pc, lr_sav, flushpipe, extend_flush, except_type, except_start,
except_started, except_stop, ex_void,
spr_dat_ppc, spr_dat_npc, datain, du_dsr, epcr_we, eear_we, esr_we, pc_we, epcr, eear,
esr, sr, lsu_addr, abort_ex, icpu_ack_i, icpu_err_i, dcpu_ack_i, dcpu_err_i
esr, sr_we, to_sr, sr, lsu_addr, abort_ex, icpu_ack_i, icpu_err_i, dcpu_ack_i, dcpu_err_i
);
 
//
180,8 → 183,10
input pc_we;
output [31:0] epcr;
output [31:0] eear;
output [`OR1200_SR_WIDTH-1:0] esr;
input [`OR1200_SR_WIDTH-1:0] sr;
output [`OR1200_SR_WIDTH-1:0] esr;
input [`OR1200_SR_WIDTH-1:0] to_sr;
input sr_we;
input [`OR1200_SR_WIDTH-1:0] sr;
input [31:0] lsu_addr;
output flushpipe;
output extend_flush;
231,11 → 236,8
assign lr_sav = ex_pc[31:2];
assign spr_dat_ppc = wb_pc;
assign spr_dat_npc = ex_void ? id_pc : ex_pc;
//assign except_start = (except_type != `OR1200_EXCEPT_NONE); // damjan
assign except_start = (except_type != `OR1200_EXCEPT_NONE) & extend_flush;
assign int_pending = sig_int & sr[`OR1200_SR_IEE] & delayed_iee[2] & ~ex_freeze & ~branch_taken & ~ex_dslot;
//assign tick_pending = sig_tick & sr[`OR1200_SR_TEE] & delayed_tee[2] & ~ex_freeze & ~branch_taken & ~ex_dslot; // works with uclinux. except_test fails
//assign tick_pending = sig_tick & sr[`OR1200_SR_TEE] & ~ex_freeze & ~branch_taken & ~ex_dslot; // works with uclinux, except_tets almost works (priority fails)
assign tick_pending = sig_tick & sr[`OR1200_SR_TEE] & ~ex_freeze & ~branch_taken & ~ex_dslot;
assign abort_ex = sig_dbuserr | sig_dmmufault | sig_dtlbmiss | sig_align | sig_illegal; // Abort write into RF by load & other instructions
 
349,11 → 351,6
delayed2_ex_dslot <= #1 delayed1_ex_dslot;
end
else if (!ex_freeze) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
$display("%t: ex_pc <= %h", $time, id_pc);
// synopsys translate_on
`endif
ex_dslot <= #1 branch_taken;
ex_pc <= #1 id_pc;
ex_exceptflags <= #1 id_exceptflags;
408,36 → 405,7
if (except_flushpipe) begin
state <= #1 `OR1200_EXCEPTFSM_FLU1;
extend_flush <= #1 1'b1;
if (ex_dslot) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
$display(" INFO: Exception during first delay slot instruction.");
// synopsys translate_on
`endif
end
else if (delayed1_ex_dslot) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
$display(" INFO: Exception during second (NOP) delay slot instruction.");
// synopsys translate_on
`endif
end
else if (delayed2_ex_dslot) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
$display(" INFO: Exception during third delay slot (SHOULD NOT HAPPEN).");
// synopsys translate_on
`endif
end
else begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
$display(" INFO: Exception during normal (no delay slot) instruction.");
// synopsys translate_on
`endif
end
 
esr <= #1 sr;
esr <= #1 sr_we ? to_sr : sr;
casex (except_trig)
13'b1_xxxx_xxxx_xxxx: begin
except_type <= #1 `OR1200_EXCEPT_TICK;
527,7 → 495,6
end
`OR1200_EXCEPTFSM_FLU1:
if (icpu_ack_i | icpu_err_i | genpc_freeze)
// if (!if_stall | genpc_freeze)
state <= #1 `OR1200_EXCEPTFSM_FLU2;
`OR1200_EXCEPTFSM_FLU2:
if (except_type == `OR1200_EXCEPT_TRAP) begin
537,17 → 504,9
except_type <= #1 `OR1200_EXCEPT_NONE;
end
else
// if (!if_stall & !id_freeze)
state <= #1 `OR1200_EXCEPTFSM_FLU3;
`OR1200_EXCEPTFSM_FLU3:
// if (!if_stall && !id_freeze)
begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
if (except_flushpipe)
$display(" INFO: EPCR0 %h EEAR %h ESR %h", epcr, eear, esr);
// synopsys translate_on
`endif
state <= #1 `OR1200_EXCEPTFSM_FLU4;
end
`OR1200_EXCEPTFSM_FLU4: begin
557,16 → 516,11
end
`OR1200_EXCEPTFSM_FLU5: begin
if (!if_stall && !id_freeze) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
$display(" INFO: Just finished flushing pipeline.");
// synopsys translate_on
`endif
state <= #1 `OR1200_EXCEPTFSM_IDLE;
except_type <= #1 `OR1200_EXCEPT_NONE;
extend_flush_last <= #1 1'b0;
state <= #1 `OR1200_EXCEPTFSM_IDLE;
except_type <= #1 `OR1200_EXCEPT_NONE;
extend_flush_last <= #1 1'b0;
end
end
end
endcase
end
end

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