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https://opencores.org/ocsvn/pci/pci/trunk
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- from Rev 103 to Rev 104
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Rev 103 → Rev 104
/trunk/bench/verilog/system.v
39,6 → 39,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.16 2003/06/12 02:30:39 mihad |
// Update! |
// |
// Revision 1.15 2003/03/14 15:33:55 mihad |
// Updated acording to RTL changes. |
// |
82,6 → 85,14
`define TEST_CONF_CYCLE_TYPE1_REFERENCE |
`endif |
|
`ifdef WB_CLOCK_FOLLOWS_PCI_CLOCK |
`define DO_CORNER_CASE_TESTS |
`endif |
|
`ifdef PCI_CLOCK_FOLLOWS_WB_CLOCK |
`define DO_CORNER_CASE_TESTS |
`endif |
|
module SYSTEM ; |
|
`include "pci_blue_constants.vh" |
626,7 → 637,7
|
`else |
always |
#(((1/`WB_FREQ)/2)) wb_clock = !wb_clock ; |
#(`WB_PERIOD/2) wb_clock = !wb_clock ; |
`endif |
|
// Make test name visible when the Master starts working on it |
680,7 → 691,7
next_test_name[79:0] <= "Nowhere___"; |
reset = 1'b1 ; |
pci_clock = 1'b0 ; |
wb_clock = 1'b1 ; |
wb_clock = 1'b0 ; |
target_message = 32'h0000_0000 ; |
// num_of_retries = 8'h01 ; |
// ack_err_rty_termination = 3'b100 ; |
964,7 → 975,7
master_completion_expiration ; |
`endif |
|
`ifdef PCI_CLOCK_FOLLOWS_WB_CLOCK |
`ifdef DO_CORNER_CASE_TESTS |
master_special_corner_case_test ; |
`endif |
|
979,6 → 990,7
|
$display("Testing PCI target images' features!") ; |
configure_bridge_target_base_addresses ; |
|
`ifdef TEST_CONF_CYCLE_TYPE1_REFERENCE |
test_conf_cycle_type1_reference ; |
`endif |
1056,7 → 1068,7
wb_subseq_waits = 0 ; |
pci_subseq_waits = 0 ; |
|
`ifdef WB_CLOCK_FOLLOWS_PCI_CLOCK |
`ifdef DO_CORNER_CASE_TESTS |
test_target_response[`TARGET_ENCODED_PARAMATERS_ENABLE] = 1 ; |
test_target_response[`TARGET_ENCODED_INIT_WAITSTATES] = 0 ; |
test_target_response[`TARGET_ENCODED_SUBS_WAITSTATES] = 0 ; |
9238,7 → 9250,7
`endif |
|
// time used for maximum transaction length on WB |
deadlock_max_val = deadlock_max_val * ( 1/`WB_FREQ ) ; |
deadlock_max_val = deadlock_max_val * ( `WB_PERIOD ) ; |
|
// maximum pci clock cycles |
`ifdef PCI33 |
9454,7 → 9466,7
`endif |
|
// maximum wb clock cycles |
deadlock_max_val = deadlock_max_val / (1/`WB_FREQ) ; |
deadlock_max_val = deadlock_max_val / (`WB_PERIOD) ; |
|
in_use = 1 ; |
ok = 1 ; |
9626,7 → 9638,7
`endif |
|
// maximum wb clock cycles |
deadlock_max_val = deadlock_max_val / (1/`WB_FREQ) ; |
deadlock_max_val = deadlock_max_val / (`WB_PERIOD) ; |
|
in_use = 1 ; |
ok = 1 ; |
16256,7 → 16268,7
// [3:0]Set_size, Set_addr_translation, Set_prefetch_enable, [7:0]Cache_lsize, Set_wb_wait_states, |
// MemRdLn_or_MemRd_when_cache_lsize_read. |
test_normal_wr_rd( `Test_Master_2, Target_Base_Addr_R[image_num], 32'h1234_5678, `Test_All_Bytes, image_num, |
`Test_One_Word, 1'b0, 1'b1, cache_lsize, 1'b0, 1'b0 ); |
`Test_One_Word, 1'b0, 1'b0, cache_lsize, 1'b0, 1'b0 ); |
|
// TEST NORMAL BURST WRITE READ THROUGH IMAGE WITHOUT ADDRESS TRANSLATION AND WITH PREFETCABLE IMAGES |
// Set Cache Line Size |
16279,7 → 16291,7
test_normal_wr_rd( `Test_Master_2, Target_Base_Addr_R[image_num] + 32'h4, 32'h5a5a_5a5a, `Test_Half_0, image_num, |
`Test_Two_Words, 1'b0, 1'b1, cache_lsize, 1'b1, 1'b0 ); |
|
// TEST NORMAL BURST WRITE READ THROUGH IMAGE WITH ADDRESS TRANSLATION AND WITH PREFETCABLE IMAGES |
// TEST NORMAL BURST WRITE READ THROUGH IMAGE WITH ADDRESS TRANSLATION AND WITH PREFETCHABLE IMAGES |
// Set Cache Line Size |
cache_lsize = 8'h8 ; |
|
19515,7 → 19527,7
endtask // run_bist_test |
`endif |
|
`ifdef WB_CLOCK_FOLLOWS_PCI_CLOCK |
`ifdef DO_CORNER_CASE_TESTS |
task target_special_corner_case_test ; |
reg [11:0] pci_ctrl_offset ; |
reg [11:0] ctrl_offset ; |
19979,7 → 19991,7
endtask // target_special_corner_case_test |
`endif |
|
`ifdef PCI_CLOCK_FOLLOWS_WB_CLOCK |
`ifdef DO_CORNER_CASE_TESTS |
task master_special_corner_case_test ; |
reg [11:0] ctrl_offset ; |
reg [11:0] ba_offset ; |
/trunk/bench/verilog/wb_master32.v
42,6 → 42,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.2 2003/06/12 02:30:39 mihad |
// Update! |
// |
// Revision 1.1 2002/02/01 13:39:43 mihad |
// Initial testbench import. Still under development |
// |
349,7 → 352,7
|
initial |
begin |
Tp = 1 / `WB_FREQ ; |
Tp = `WB_PERIOD ; |
in_use = 0 ; |
cycle_in_progress = 0 ; |
cab = 0 ; |
/trunk/bench/verilog/wb_slave_behavioral.v
42,6 → 42,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.4 2003/06/12 02:30:39 mihad |
// Update! |
// |
// Revision 1.3 2002/10/11 10:08:58 mihad |
// Added additional testcase and changed rst name in BIST to trst |
// |
119,6 → 122,7
end |
end //reset |
|
reg retry_expired; |
task cycle_response; |
input [2:0] ack_err_rty_resp; // acknowledge, error or retry response input flags |
input [3:0] wait_cycles; // if wait cycles before each data termination cycle (ack, err or rty) |
125,9 → 129,10
input [7:0] retry_cycles; // noumber of retry cycles before acknowledge cycle |
begin |
// assign values |
a_e_r_resp <= #1 ack_err_rty_resp; |
wait_cyc <= #1 wait_cycles; |
max_retry <= #1 retry_cycles; |
a_e_r_resp <= #1 ack_err_rty_resp; |
wait_cyc <= #1 wait_cycles; |
max_retry <= #1 retry_cycles; |
retry_expired <= #1 0 ; |
end |
endtask // cycle_response |
|
208,7 → 213,6
|
reg [7:0] retry_cnt; |
reg [7:0] retry_num; |
reg retry_expired; |
|
// Retry counter |
always@(posedge RST_I or posedge CLK_I) |
/trunk/bench/verilog/pci_testbench_defines.v
14,10 → 14,10
// they are used to generate both clocks with same period and phase shift of define's value in nano seconds |
|
//`define PCI_CLOCK_FOLLOWS_WB_CLOCK 2 |
//`define WB_CLOCK_FOLLOWS_PCI_CLOCK 2 |
`define WB_CLOCK_FOLLOWS_PCI_CLOCK 2 |
|
// wishbone frequncy in GHz |
`define WB_FREQ 0.033 |
// wishbone period in ns |
`define WB_PERIOD 30.0 |
|
// values of image registers of PCI bridge device - valid are only upper 20 bits, others must be ZERO ! |
`define TAR0_BASE_ADDR_0 32'h1000_0000 |
67,7 → 67,7
`define TAR1_IDSEL_ADDR (32'h0000_0001 << `TAR1_IDSEL_INDEX) |
`define TAR2_IDSEL_ADDR (32'h0000_0001 << `TAR2_IDSEL_INDEX) |
|
//`define DISABLE_COMPLETION_EXPIRED_TESTS |
`define DISABLE_COMPLETION_EXPIRED_TESTS |
`endif |
|
//=================================================================================== |
/trunk/bench/verilog/pci_regression_constants.v
39,6 → 39,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.3 2002/08/13 11:03:51 mihad |
// Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image |
// |
// Revision 1.2 2002/02/19 16:32:29 mihad |
// Modified testbench and fixed some bugs |
// |
67,151 → 70,90
// If RAM_DONT_SHARE is defined, then all RAM address lengths must be specified accordingly, otherwise there are two relevant lengths - PCI_FIFO_RAM_ADDR_LENGTH and |
// WB_FIFO_RAM_ADDR_LENGTH. |
|
`ifdef REGR_FIFO_SMALL_XILINX // with Xilinx FPGA parameters only |
`define WBW_ADDR_LENGTH 3 |
`define WBR_ADDR_LENGTH 4 |
`define PCIW_ADDR_LENGTH 4 |
`define PCIR_ADDR_LENGTH 3 |
`ifdef REGR_FIFO_SMALL_XILINX // with Xilinx FPGA parameters only |
`define WBW_ADDR_LENGTH 3 |
`define WBR_ADDR_LENGTH 4 |
`define PCIW_ADDR_LENGTH 4 |
`define PCIR_ADDR_LENGTH 3 |
|
`define FPGA |
`define XILINX |
|
`define WB_RAM_DONT_SHARE |
`define PCI_RAM_DONT_SHARE |
|
`define FPGA |
`define XILINX |
`define PCI_FIFO_RAM_ADDR_LENGTH 4 // PCI target unit fifo storage definition |
`define WB_FIFO_RAM_ADDR_LENGTH 4 // WB slave unit fifo storage definition |
`define PCI_XILINX_DIST_RAM |
`define WB_XILINX_DIST_RAM |
`endif |
|
`ifdef REGR_FIFO_MEDIUM_XILINX |
`define WBW_ADDR_LENGTH 8 |
`define WBR_ADDR_LENGTH 8 |
`define PCIW_ADDR_LENGTH 8 |
`define PCIR_ADDR_LENGTH 8 |
|
`define FPGA |
`define XILINX |
|
`define WB_RAM_DONT_SHARE |
`define PCI_RAM_DONT_SHARE |
|
`define WB_RAM_DONT_SHARE |
`define PCI_RAM_DONT_SHARE |
`define PCI_FIFO_RAM_ADDR_LENGTH 8 // PCI target unit fifo storage definition |
`define WB_FIFO_RAM_ADDR_LENGTH 8 // WB slave unit fifo storage definition |
`define PCI_XILINX_RAMB4 |
`define WB_XILINX_RAMB4 |
`endif |
|
`ifdef FPGA |
`ifdef XILINX |
`define PCI_FIFO_RAM_ADDR_LENGTH 4 // PCI target unit fifo storage definition |
`define WB_FIFO_RAM_ADDR_LENGTH 4 // WB slave unit fifo storage definition |
//`define PCI_XILINX_RAMB4 |
//`define WB_XILINX_RAMB4 |
`define PCI_XILINX_DIST_RAM |
`define WB_XILINX_DIST_RAM |
`endif |
`else |
`define PCI_FIFO_RAM_ADDR_LENGTH 8 // PCI target unit fifo storage definition when RAM sharing is used ( both pcir and pciw fifo use same instance of RAM ) |
`define WB_FIFO_RAM_ADDR_LENGTH 8 // WB slave unit fifo storage definition when RAM sharing is used ( both wbr and wbw fifo use same instance of RAM ) |
`define WB_ARTISAN_SDP |
`define PCI_ARTISAN_SDP |
`endif |
`else |
`ifdef REGR_FIFO_MEDIUM_ARTISAN // with Artisan parameter only |
`define WBW_ADDR_LENGTH 7 |
`define WBR_ADDR_LENGTH 6 |
`define PCIW_ADDR_LENGTH 7 |
`define PCIR_ADDR_LENGTH 8 |
`ifdef REGR_FIFO_MEDIUM_ARTISAN // with Artisan parameter only |
`define WBW_ADDR_LENGTH 7 |
`define WBR_ADDR_LENGTH 6 |
`define PCIW_ADDR_LENGTH 7 |
`define PCIR_ADDR_LENGTH 8 |
|
`define PCI_RAM_DONT_SHARE |
|
`define PCI_FIFO_RAM_ADDR_LENGTH 8 // PCI target unit fifo storage definition when RAM sharing is used ( both pcir and pciw fifo use same instance of RAM ) |
`define WB_FIFO_RAM_ADDR_LENGTH 8 // WB slave unit fifo storage definition when RAM sharing is used ( both wbr and wbw fifo use same instance of RAM ) |
`define WB_ARTISAN_SDP |
`define PCI_ARTISAN_SDP |
`endif |
|
`ifdef REGR_FIFO_SMALL_GENERIC // without any parameters only (generic) |
`define WBW_ADDR_LENGTH 3 |
`define WBR_ADDR_LENGTH 4 |
`define PCIW_ADDR_LENGTH 4 |
`define PCIR_ADDR_LENGTH 3 |
|
`define WB_RAM_DONT_SHARE |
|
//`define FPGA |
//`define XILINX |
|
//`define WB_RAM_DONT_SHARE |
`define PCI_RAM_DONT_SHARE |
|
`ifdef FPGA |
`ifdef XILINX |
`define PCI_FIFO_RAM_ADDR_LENGTH 8 // PCI target unit fifo storage definition |
`define WB_FIFO_RAM_ADDR_LENGTH 8 // WB slave unit fifo storage definition |
`define PCI_XILINX_RAMB4 |
`define WB_XILINX_RAMB4 |
//`define PCI_XILINX_DIST_RAM |
//`define WB_XILINX_DIST_RAM |
`endif |
`else |
`define PCI_FIFO_RAM_ADDR_LENGTH 8 // PCI target unit fifo storage definition when RAM sharing is used ( both pcir and pciw fifo use same instance of RAM ) |
`define WB_FIFO_RAM_ADDR_LENGTH 8 // WB slave unit fifo storage definition when RAM sharing is used ( both wbr and wbw fifo use same instance of RAM ) |
`define WB_ARTISAN_SDP |
`define PCI_ARTISAN_SDP |
`endif |
`else |
`ifdef REGR_FIFO_SMALL_GENERIC // without any parameters only (generic) |
`define WBW_ADDR_LENGTH 3 |
`define WBR_ADDR_LENGTH 4 |
`define PCIW_ADDR_LENGTH 4 |
`define PCIR_ADDR_LENGTH 3 |
|
//`define FPGA |
//`define XILINX |
|
`define WB_RAM_DONT_SHARE |
//`define PCI_RAM_DONT_SHARE |
|
`ifdef FPGA |
`ifdef XILINX |
`define PCI_FIFO_RAM_ADDR_LENGTH 8 // PCI target unit fifo storage definition |
`define WB_FIFO_RAM_ADDR_LENGTH 8 // WB slave unit fifo storage definition |
`define PCI_XILINX_RAMB4 |
`define WB_XILINX_RAMB4 |
//`define PCI_XILINX_DIST_RAM |
//`define WB_XILINX_DIST_RAM |
`endif |
`else |
`define PCI_FIFO_RAM_ADDR_LENGTH 5 // PCI target unit fifo storage definition when RAM sharing is used ( both pcir and pciw fifo use same instance of RAM ) |
`define WB_FIFO_RAM_ADDR_LENGTH 4 // WB slave unit fifo storage definition when RAM sharing is used ( both wbr and wbw fifo use same instance of RAM ) |
//`define WB_ARTISAN_SDP |
//`define PCI_ARTISAN_SDP |
`endif |
`else |
`ifdef REGR_FIFO_MEDIUM_GENERIC // without any parameters only (generic) |
`define WBW_ADDR_LENGTH 7 |
`define WBR_ADDR_LENGTH 6 |
`define PCIW_ADDR_LENGTH 7 |
`define PCIR_ADDR_LENGTH 8 |
|
//`define FPGA |
//`define XILINX |
|
//`define WB_RAM_DONT_SHARE |
`define PCI_RAM_DONT_SHARE |
|
`ifdef FPGA |
`ifdef XILINX |
`define PCI_FIFO_RAM_ADDR_LENGTH 8 // PCI target unit fifo storage definition |
`define WB_FIFO_RAM_ADDR_LENGTH 8 // WB slave unit fifo storage definition |
`define PCI_XILINX_RAMB4 |
`define WB_XILINX_RAMB4 |
//`define PCI_XILINX_DIST_RAM |
//`define WB_XILINX_DIST_RAM |
`endif |
`else |
`define PCI_FIFO_RAM_ADDR_LENGTH 8 // PCI target unit fifo storage definition when RAM sharing is used ( both pcir and pciw fifo use same instance of RAM ) |
`define WB_FIFO_RAM_ADDR_LENGTH 8 // WB slave unit fifo storage definition when RAM sharing is used ( both wbr and wbw fifo use same instance of RAM ) |
//`define WB_ARTISAN_SDP |
//`define PCI_ARTISAN_SDP |
`endif |
`else |
`ifdef REGR_FIFO_LARGE_GENERIC // without any parameters only (generic) |
`define PCI_FIFO_RAM_ADDR_LENGTH 5 // PCI target unit fifo storage definition when RAM sharing is used ( both pcir and pciw fifo use same instance of RAM ) |
`define WB_FIFO_RAM_ADDR_LENGTH 4 // WB slave unit fifo storage definition when RAM sharing is used ( both wbr and wbw fifo use same instance of RAM ) |
|
`endif |
|
`ifdef REGR_FIFO_MEDIUM_GENERIC // without any parameters only (generic) |
`define WBW_ADDR_LENGTH 7 |
`define WBR_ADDR_LENGTH 6 |
`define PCIW_ADDR_LENGTH 7 |
`define PCIR_ADDR_LENGTH 8 |
|
`define PCI_RAM_DONT_SHARE |
|
`define PCI_FIFO_RAM_ADDR_LENGTH 8 // PCI target unit fifo storage definition when RAM sharing is used ( both pcir and pciw fifo use same instance of RAM ) |
`define WB_FIFO_RAM_ADDR_LENGTH 8 // WB slave unit fifo storage definition when RAM sharing is used ( both wbr and wbw fifo use same instance of RAM ) |
`endif |
|
`ifdef REGR_FIFO_LARGE_GENERIC // without any parameters only (generic) |
`define WBW_ADDR_LENGTH 9 |
`define WBR_ADDR_LENGTH 9 |
`define PCIW_ADDR_LENGTH 9 |
`define PCIR_ADDR_LENGTH 9 |
|
//`define FPGA |
//`define XILINX |
|
//`define WB_RAM_DONT_SHARE |
//`define PCI_RAM_DONT_SHARE |
|
`ifdef FPGA |
`ifdef XILINX |
`define PCI_FIFO_RAM_ADDR_LENGTH 8 // PCI target unit fifo storage definition |
`define WB_FIFO_RAM_ADDR_LENGTH 8 // WB slave unit fifo storage definition |
`define PCI_XILINX_RAMB4 |
`define WB_XILINX_RAMB4 |
//`define PCI_XILINX_DIST_RAM |
//`define WB_XILINX_DIST_RAM |
`endif |
`else |
`define PCI_FIFO_RAM_ADDR_LENGTH 10 // PCI target unit fifo storage definition when RAM sharing is used ( both pcir and pciw fifo use same instance of RAM ) |
`define WB_FIFO_RAM_ADDR_LENGTH 10 // WB slave unit fifo storage definition when RAM sharing is used ( both wbr and wbw fifo use same instance of RAM ) |
//`define WB_ARTISAN_SDP |
//`define PCI_ARTISAN_SDP |
`endif |
`else |
`endif |
`endif |
`endif |
`endif |
`endif |
`define PCI_FIFO_RAM_ADDR_LENGTH 10 // PCI target unit fifo storage definition when RAM sharing is used ( both pcir and pciw fifo use same instance of RAM ) |
`define WB_FIFO_RAM_ADDR_LENGTH 10 // WB slave unit fifo storage definition when RAM sharing is used ( both wbr and wbw fifo use same instance of RAM ) |
`endif |
|
// number defined here specifies how many MS bits in PCI address are compared with base address, to decode |
// accesses. Maximum number allows for minimum image size ( number = 20, image size = 4KB ), minimum number |
229,36 → 171,37
// then IMAGE with that base address points to MEMORY space, othervise it points ti IO space. D |
// Device independent software sets the base addresses acording to MEMORY or IO maping! |
|
`ifdef PCI_DECODE_MIN |
`ifdef PCI_DECODE_MIN |
|
`define PCI_NUM_OF_DEC_ADDR_LINES 3 |
`define PCI_NUM_OF_DEC_ADDR_LINES 3 |
|
|
// don't disable AM0 if GUEST bridge, otherwise there is no other way of accesing configuration space |
`ifdef HOST |
`define PCI_AM0 20'h0000_0 |
`else |
`define PCI_AM0 20'hE000_0 |
`endif |
// don't disable AM0 if GUEST bridge, otherwise there is no other way of accesing configuration space |
`ifdef HOST |
`define PCI_AM0 20'h0000_0 |
`else |
`define PCI_AM0 20'hE000_0 |
`endif |
|
`define PCI_AM1 20'hE000_0 |
`define PCI_AM2 20'h0000_0 |
`define PCI_AM3 20'hE000_0 |
`define PCI_AM4 20'h0000_0 |
`define PCI_AM5 20'hE000_0 |
`define PCI_AM1 20'hE000_0 |
`define PCI_AM2 20'h0000_0 |
`define PCI_AM3 20'hE000_0 |
`define PCI_AM4 20'h0000_0 |
`define PCI_AM5 20'hE000_0 |
|
`define PCI_BA0_MEM_IO 1'b1 // considered only when PCI_IMAGE0 is used as general PCI-WB image! |
`define PCI_BA1_MEM_IO 1'b0 |
`define PCI_BA2_MEM_IO 1'b1 |
`define PCI_BA3_MEM_IO 1'b0 |
`define PCI_BA4_MEM_IO 1'b1 |
`define PCI_BA5_MEM_IO 1'b0 |
`define PCI_BA0_MEM_IO 1'b1 // considered only when PCI_IMAGE0 is used as general PCI-WB image! |
`define PCI_BA1_MEM_IO 1'b0 |
`define PCI_BA2_MEM_IO 1'b1 |
`define PCI_BA3_MEM_IO 1'b0 |
`define PCI_BA4_MEM_IO 1'b1 |
`define PCI_BA5_MEM_IO 1'b0 |
|
`else |
`ifdef PCI_DECODE_MED |
`endif |
|
`define PCI_NUM_OF_DEC_ADDR_LINES 12 |
`ifdef PCI_DECODE_MED |
|
`define PCI_NUM_OF_DEC_ADDR_LINES 12 |
|
`define PCI_AM0 20'hfff0_0 |
`define PCI_AM1 20'h0000_0 |
`define PCI_AM2 20'hfff0_0 |
273,60 → 216,57
`define PCI_BA4_MEM_IO 1'b1 |
`define PCI_BA5_MEM_IO 1'b0 |
|
`else |
`ifdef PCI_DECODE_MAX |
`endif |
|
`define PCI_NUM_OF_DEC_ADDR_LINES 20 |
`ifdef PCI_DECODE_MAX |
|
`define PCI_AM0 20'hffff_e |
`define PCI_AM1 20'hffff_c |
`define PCI_AM2 20'hffff_8 |
`define PCI_AM3 20'hfffe_0 |
`define PCI_AM4 20'hfffc_0 |
`define PCI_AM5 20'hfff8_0 |
`define PCI_NUM_OF_DEC_ADDR_LINES 20 |
|
`define PCI_BA0_MEM_IO 1'b0 // considered only when PCI_IMAGE0 is used as general PCI-WB image! |
`define PCI_BA1_MEM_IO 1'b0 |
`define PCI_BA2_MEM_IO 1'b1 |
`define PCI_BA3_MEM_IO 1'b1 |
`define PCI_BA4_MEM_IO 1'b0 |
`define PCI_BA5_MEM_IO 1'b0 |
`define PCI_AM0 20'hffff_e |
`define PCI_AM1 20'hffff_c |
`define PCI_AM2 20'hffff_8 |
`define PCI_AM3 20'hfffe_0 |
`define PCI_AM4 20'hfffc_0 |
`define PCI_AM5 20'hfff8_0 |
|
`endif |
`endif |
`endif |
`define PCI_BA0_MEM_IO 1'b0 // considered only when PCI_IMAGE0 is used as general PCI-WB image! |
`define PCI_BA1_MEM_IO 1'b0 |
`define PCI_BA2_MEM_IO 1'b1 |
`define PCI_BA3_MEM_IO 1'b1 |
`define PCI_BA4_MEM_IO 1'b0 |
`define PCI_BA5_MEM_IO 1'b0 |
|
`endif |
|
|
|
// number defined here specifies how many MS bits in WB address are compared with base address, to decode |
// accesses. Maximum number allows for minimum image size ( number = 20, image size = 4KB ), minimum number |
// allows for maximum image size ( number = 1, image size = 2GB ). If you intend on using different sizes of WB images, |
// you have to define a number of minimum sized image and enlarge others by specifying different address mask. |
// smaller the number here, faster the decoder operation |
`ifdef WB_DECODE_MIN |
`define WB_NUM_OF_DEC_ADDR_LINES 4 |
`else |
`ifdef WB_DECODE_MED |
`define WB_NUM_OF_DEC_ADDR_LINES 12 |
`else |
`ifdef WB_DECODE_MAX |
`define WB_NUM_OF_DEC_ADDR_LINES 20 |
`endif |
`endif |
`endif |
`ifdef WB_DECODE_MIN |
`define WB_NUM_OF_DEC_ADDR_LINES 4 |
`endif |
|
`ifdef WB_DECODE_MED |
`define WB_NUM_OF_DEC_ADDR_LINES 12 |
`endif |
|
// Base address for Configuration space access from WB bus. This value cannot be changed during runtime |
`ifdef WB_CNF_BASE_ZERO |
`define WB_CONFIGURATION_BASE 20'h0000_0 |
`else |
`define WB_CONFIGURATION_BASE 20'hB000_0 |
`endif |
`ifdef WB_DECODE_MAX |
`define WB_NUM_OF_DEC_ADDR_LINES 20 |
`endif |
|
// Base address for Configuration space access from WB bus. This value cannot be changed during runtime |
`ifdef WB_CNF_BASE_ZERO |
`define WB_CONFIGURATION_BASE 20'h0000_0 |
`else |
`define WB_CONFIGURATION_BASE 20'hB000_0 |
`endif |
|
/*----------------------------------------------------------------------------------------------------------- |
[000h-00Ch] First 4 DWORDs (32-bit) of PCI configuration header - the same regardless of the HEADER type ! |
Vendor_ID is an ID for a specific vendor defined by PCI_SIG - 2321h does not belong to anyone (e.g. |
Xilinx's Vendor_ID is 10EEh and Altera's Vendor_ID is 1172h). Device_ID and Revision_ID should be used |
together by application. |
Vendor_ID is an ID for a specific vendor defined by PCI_SIG - 2321h does not belong to anyone (e.g. |
Xilinx's Vendor_ID is 10EEh and Altera's Vendor_ID is 1172h). Device_ID and Revision_ID should be used |
together by application. |
-----------------------------------------------------------------------------------------------------------*/ |
`define HEADER_VENDOR_ID 16'h2321 |
`define HEADER_DEVICE_ID 16'h0001 |
333,8 → 273,8
`define HEADER_REVISION_ID 8'h01 |
|
// MAX Retry counter value for WISHBONE Master state-machine |
// This value is 8-bit because of 8-bit retry counter !!! |
`define WB_RTY_CNT_MAX 8'hff |
// This value is 8-bit because of 8-bit retry counter !!! |
`define WB_RTY_CNT_MAX 8'hff |
|
///////////////////////////////////////////////////////////////////////////////// |
//// ======================================================================= //// |
347,38 → 287,36
|
// wishbone frequncy in GHz |
`ifdef WB_CLK10 |
`define WB_FREQ 0.01 |
`else |
`ifdef WB_CLK66 |
`define WB_FREQ 0.066 |
`else |
`ifdef WB_CLK220 |
`define WB_FREQ 0.22 |
`endif |
`endif |
`define WB_PERIOD 100.0 |
`endif |
`ifdef WB_CLK66 |
`define WB_PERIOD 15.0 |
`endif |
`ifdef WB_CLK220 |
`define WB_PERIOD 4.5 |
`endif |
|
// values of image registers of PCI bridge device - valid are only upper 20 bits, others must be ZERO ! |
`define TAR0_BASE_ADDR_0 32'h1000_0000 |
`define TAR0_BASE_ADDR_1 32'h2000_0000 |
`define TAR0_BASE_ADDR_2 32'h4000_0000 |
`define TAR0_BASE_ADDR_3 32'h6000_0000 |
`define TAR0_BASE_ADDR_4 32'h8000_0000 |
`define TAR0_BASE_ADDR_5 32'hA000_0000 |
`define TAR0_BASE_ADDR_0 32'h1000_0000 |
`define TAR0_BASE_ADDR_1 32'h2000_0000 |
`define TAR0_BASE_ADDR_2 32'h4000_0000 |
`define TAR0_BASE_ADDR_3 32'h6000_0000 |
`define TAR0_BASE_ADDR_4 32'h8000_0000 |
`define TAR0_BASE_ADDR_5 32'hA000_0000 |
|
`define TAR0_ADDR_MASK_0 32'hFFFF_F000 // when BA0 is used to access configuration space, this is NOT important! |
`define TAR0_ADDR_MASK_1 32'hFFFF_F000 |
`define TAR0_ADDR_MASK_2 32'hFFFF_F000 |
`define TAR0_ADDR_MASK_3 32'hFFFF_F000 |
`define TAR0_ADDR_MASK_4 32'hFFFF_F000 |
`define TAR0_ADDR_MASK_5 32'hFFFF_F000 |
`define TAR0_ADDR_MASK_0 32'hFFFF_F000 // when BA0 is used to access configuration space, this is NOT important! |
`define TAR0_ADDR_MASK_1 32'hFFFF_F000 |
`define TAR0_ADDR_MASK_2 32'hFFFF_F000 |
`define TAR0_ADDR_MASK_3 32'hFFFF_F000 |
`define TAR0_ADDR_MASK_4 32'hFFFF_F000 |
`define TAR0_ADDR_MASK_5 32'hFFFF_F000 |
|
`define TAR0_TRAN_ADDR_0 32'hC000_0000 // when BA0 is used to access configuration space, this is NOT important! |
`define TAR0_TRAN_ADDR_1 32'hA000_0000 |
`define TAR0_TRAN_ADDR_2 32'h8000_0000 |
`define TAR0_TRAN_ADDR_3 32'h6000_0000 |
`define TAR0_TRAN_ADDR_4 32'h4000_0000 |
`define TAR0_TRAN_ADDR_5 32'h2000_0000 |
`define TAR0_TRAN_ADDR_0 32'hC000_0000 // when BA0 is used to access configuration space, this is NOT important! |
`define TAR0_TRAN_ADDR_1 32'hA000_0000 |
`define TAR0_TRAN_ADDR_2 32'h8000_0000 |
`define TAR0_TRAN_ADDR_3 32'h6000_0000 |
`define TAR0_TRAN_ADDR_4 32'h4000_0000 |
`define TAR0_TRAN_ADDR_5 32'h2000_0000 |
|
// values of image registers of PCI behavioral target devices ! |
`define BEH_TAR1_MEM_START 32'hC000_0000 |
410,9 → 348,9
========================================================================================= |
|
REGRESSION |
HOST GUEST |
REGR_FIFO_SMALL_XILINX REGR_FIFO_MEDIUM_ARTISAN REGR_FIFO_LARGE_GENERIC |
(REGR_FIFO_SMALL_GENERIC) (REGR_FIFO_MEDIUM_GENERIC) |
HOST GUEST |
REGR_FIFO_SMALL_XILINX REGR_FIFO_MEDIUM_ARTISAN REGR_FIFO_LARGE_GENERIC |
(REGR_FIFO_SMALL_GENERIC) (REGR_FIFO_MEDIUM_GENERIC) |
ADDR_TRAN_IMPL |
WB_RETRY_MAX |
WB_CNF_BASE_ZERO |
426,14 → 364,14
WB_IMAGE3 |
WB_IMAGE4 |
WB_IMAGE5 |
WB_DECODE_FAST WB_DECODE_MEDIUM WB_DECODE_SLOW |
WB_DECODE_FAST WB_DECODE_MEDIUM WB_DECODE_SLOW |
REGISTER_WBM_OUTPUTS |
REGISTER_WBS_OUTPUTS |
PCI_DECODE_MIN PCI_DECODE_MED PCI_DECODE_MAX |
WB_DECODE_MIN WB_DECODE_MED WB_DECODE_MAX |
PCI33 PCI66 |
WB_CLK10 WB_CLK66 WB_CLK100 |
ACTIVE_LOW_OE ACTIVE_HIGH_OE |
PCI_DECODE_MIN PCI_DECODE_MED PCI_DECODE_MAX |
WB_DECODE_MIN WB_DECODE_MED WB_DECODE_MAX |
PCI33 PCI66 |
WB_CLK10 WB_CLK66 WB_CLK100 |
ACTIVE_LOW_OE ACTIVE_HIGH_OE |
|
----------------------------------------------------------------------------------------- |
Follows combinations of defines used in a script file for regression testing !!! |
/trunk/rtl/verilog/pci_wbr_fifo_control.v
42,6 → 42,11
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.2 2003/03/26 13:16:18 mihad |
// Added the reset value parameter to the synchronizer flop module. |
// Added resets to all synchronizer flop instances. |
// Repaired initial sync value in fifos. |
// |
// Revision 1.1 2003/01/27 16:49:31 mihad |
// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. |
// |
210,12 → 215,12
begin |
if (clear) |
begin |
wgrey_addr <= #`FF_DELAY 0 ; |
wgrey_addr <= #1 0 ; |
end |
else |
if (wallow) |
begin |
wgrey_addr <= #`FF_DELAY {waddr[(ADDR_LENGTH - 1)], calc_wgrey_next} ; |
wgrey_addr <= #1 {waddr[(ADDR_LENGTH - 1)], calc_wgrey_next} ; |
end |
end |
|
/trunk/rtl/verilog/pci_pcir_fifo_control.v
42,6 → 42,11
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.2 2003/03/26 13:16:18 mihad |
// Added the reset value parameter to the synchronizer flop module. |
// Added resets to all synchronizer flop instances. |
// Repaired initial sync value in fifos. |
// |
// Revision 1.1 2003/01/27 16:49:31 mihad |
// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. |
// |
219,7 → 224,7
begin |
if (clear) |
begin |
rgrey_addr <= #`FF_DELAY 0 ; |
rgrey_addr <= #1 0 ; |
rgrey_next <= #`FF_DELAY 1 ; // this grey code is calculated from the current binary address and loaded any time data is read from fifo |
end |
else if (flush_in) |
226,13 → 231,13
begin |
// when fifo is flushed, load the register values from the write clock domain. |
// must be no problem, because write pointers are stable for at least 3 clock cycles before flush can occur. |
rgrey_addr <= #`FF_DELAY wgrey_addr ; |
rgrey_addr <= #1 wgrey_addr ; |
rgrey_next <= #`FF_DELAY wgrey_next ; |
end |
else if (rallow) |
begin |
// move the pipeline when data is read from fifo and calculate new value for first stage of pipeline from current binary fifo address |
rgrey_addr <= #`FF_DELAY rgrey_next ; |
rgrey_addr <= #1 rgrey_next ; |
rgrey_next <= #`FF_DELAY {raddr[ADDR_LENGTH - 1], calc_rgrey_next} ; |
end |
end |
247,13 → 252,13
begin |
if (clear) |
begin |
wgrey_addr <= #`FF_DELAY 0 ; |
wgrey_addr <= #1 0 ; |
wgrey_next <= #`FF_DELAY 1 ; |
end |
else |
if (wallow) |
begin |
wgrey_addr <= #`FF_DELAY wgrey_next ; |
wgrey_addr <= #1 wgrey_next ; |
wgrey_next <= #`FF_DELAY {waddr[(ADDR_LENGTH - 1)], calc_wgrey_next} ; |
end |
end |
/trunk/rtl/verilog/pci_wbw_fifo_control.v
42,6 → 42,11
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.2 2003/03/26 13:16:18 mihad |
// Added the reset value parameter to the synchronizer flop module. |
// Added resets to all synchronizer flop instances. |
// Repaired initial sync value in fifos. |
// |
// Revision 1.1 2003/01/27 16:49:31 mihad |
// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. |
// |
81,7 → 86,6
renable_in, |
wenable_in, |
reset_in, |
// flush_in, // not used |
almost_full_out, |
full_out, |
empty_out, |
126,6 → 130,7
assign waddr_out = waddr ; |
|
// grey code registers |
reg [(ADDR_LENGTH - 1):0] wgrey_addr ; // current |
// grey code register for next write address |
reg [(ADDR_LENGTH - 1):0] wgrey_next ; // next |
|
140,39 → 145,15
// next read gray address calculation - bitwise xor between address and shifted address |
wire [(ADDR_LENGTH - 2):0] calc_rgrey_next = raddr[(ADDR_LENGTH - 1):1] ^ raddr[(ADDR_LENGTH - 2):0] ; |
|
// FFs for registered empty and full flags |
wire empty ; |
wire full ; |
|
// almost_full tag |
wire almost_full ; |
|
// write allow wire - writes are allowed when fifo is not full |
wire wallow = wenable_in && !full ; |
assign wallow_out = wenable_in & ~full_out ; |
|
// write allow output assignment |
assign wallow_out = wallow && !full ; |
|
// read allow wire |
wire rallow ; |
|
// full output assignment |
assign full_out = full ; |
|
// almost full output assignment |
assign almost_full_out = almost_full && !full ; |
|
// clear generation for FFs and registers |
wire clear = reset_in /*|| flush_in*/ ; // flush not used |
wire clear = reset_in ; |
|
assign empty_out = empty ; |
|
//rallow generation |
assign rallow = renable_in && !empty ; // reads allowed if read enable is high and FIFO is not empty |
assign rallow_out = renable_in & ~empty_out ; // reads allowed if read enable is high and FIFO is not empty |
|
// rallow output assignment |
assign rallow_out = rallow ; |
|
// at any clock edge that rallow is high, this register provides next read address, so wait cycles are not necessary |
// when FIFO is empty, this register provides actual read address, so first location can be read |
reg [(ADDR_LENGTH - 1):0] raddr_plus_one ; |
179,7 → 160,7
|
// address output mux - when FIFO is empty, current actual address is driven out, when it is non - empty next address is driven out |
// done for zero wait state burst |
assign raddr_out = rallow ? raddr_plus_one : raddr ; |
assign raddr_out = rallow_out ? raddr_plus_one : raddr ; |
|
always@(posedge rclock_in or posedge clear) |
begin |
188,7 → 169,7
raddr_plus_one <= #`FF_DELAY 4 ; |
raddr <= #`FF_DELAY 3 ; |
end |
else if (rallow) |
else if (rallow_out) |
begin |
raddr_plus_one <= #`FF_DELAY raddr_plus_one + 1'b1 ; |
raddr <= #`FF_DELAY raddr_plus_one ; |
208,15 → 189,15
if (clear) |
begin |
// initial value is 0 |
rgrey_minus1 <= #`FF_DELAY 0 ; |
rgrey_addr <= #`FF_DELAY 1 ; |
rgrey_minus1 <= #1 0 ; |
rgrey_addr <= #1 1 ; |
rgrey_next <= #`FF_DELAY 3 ; |
end |
else |
if (rallow) |
if (rallow_out) |
begin |
rgrey_minus1 <= #`FF_DELAY rgrey_addr ; |
rgrey_addr <= #`FF_DELAY rgrey_next ; |
rgrey_minus1 <= #1 rgrey_addr ; |
rgrey_addr <= #1 rgrey_next ; |
rgrey_next <= #`FF_DELAY {raddr[ADDR_LENGTH - 1], calc_rgrey_next} ; |
end |
end |
229,12 → 210,14
begin |
if (clear) |
begin |
wgrey_next <= #`FF_DELAY 3 ; |
wgrey_addr <= #`FF_DELAY 1 ; |
wgrey_next <= #1 3 ; |
end |
else |
if (wallow) |
if (wallow_out) |
begin |
wgrey_next <= #`FF_DELAY {waddr[(ADDR_LENGTH - 1)], calc_wgrey_next} ; |
wgrey_addr <= #`FF_DELAY wgrey_next ; |
wgrey_next <= #1 {waddr[(ADDR_LENGTH - 1)], calc_wgrey_next} ; |
end |
end |
|
245,32 → 228,20
// initial value 4 |
waddr <= #`FF_DELAY 3 ; |
else |
if (wallow) |
if (wallow_out) |
waddr <= #`FF_DELAY waddr + 1'b1 ; |
end |
|
/*------------------------------------------------------------------------------------------------------------------------------ |
Full control: |
Gray coded read address pointer is synchronized to write clock domain and compared to Gray coded next write address. |
If they are equal, fifo is full. |
Gray coded address of read address decremented by 1 is synchronized to write clock domain and compared to: |
|
Almost full control: |
Gray coded address of read address decremented by 1 is synchronized to write clock domain and compared to Gray coded next write |
address. If they are equal, fifo is almost full. |
- Gray coded write address. If they are equal, fifo is full. |
|
- Gray coded next write address. If they are equal, fifo is almost full. |
--------------------------------------------------------------------------------------------------------------------------------*/ |
wire [(ADDR_LENGTH - 1):0] wclk_sync_rgrey_addr ; |
reg [(ADDR_LENGTH - 1):0] wclk_rgrey_addr ; |
wire [(ADDR_LENGTH - 1):0] wclk_sync_rgrey_minus1 ; |
reg [(ADDR_LENGTH - 1):0] wclk_rgrey_minus1 ; |
|
synchronizer_flop #(ADDR_LENGTH, 1) i_synchronizer_reg_rgrey_addr |
( |
.data_in (rgrey_addr), |
.clk_out (wclock_in), |
.sync_data_out (wclk_sync_rgrey_addr), |
.async_reset (clear) |
) ; |
|
synchronizer_flop #(ADDR_LENGTH, 0) i_synchronizer_reg_rgrey_minus1 |
( |
.data_in (rgrey_minus1), |
283,18 → 254,16
begin |
if (clear) |
begin |
wclk_rgrey_addr <= #`FF_DELAY 1 ; |
wclk_rgrey_minus1 <= #`FF_DELAY 0 ; |
end |
else |
begin |
wclk_rgrey_addr <= #`FF_DELAY wclk_sync_rgrey_addr ; |
wclk_rgrey_minus1 <= #`FF_DELAY wclk_sync_rgrey_minus1 ; |
end |
end |
|
assign full = (wgrey_next == wclk_rgrey_addr) ; |
assign almost_full = (wgrey_next == wclk_rgrey_minus1) ; |
assign full_out = (wgrey_addr == wclk_rgrey_minus1) ; |
assign almost_full_out = (wgrey_next == wclk_rgrey_minus1) ; |
|
/*------------------------------------------------------------------------------------------------------------------------------ |
Empty control: |
319,6 → 288,6
rclk_wgrey_next <= #`FF_DELAY rclk_sync_wgrey_next ; |
end |
|
assign empty = (rgrey_next == rclk_wgrey_next) ; |
assign empty_out = (rgrey_next == rclk_wgrey_next) ; |
|
endmodule |
/trunk/rtl/verilog/pci_pciw_fifo_control.v
41,7 → 41,7
// |
// CVS Revision History |
// |
// $Log |
// $Log: not supported by cvs2svn $ |
// |
|
/* FIFO_CONTROL module provides read/write address and status generation for |
58,7 → 58,6
renable_in, |
wenable_in, |
reset_in, |
// flush_in, // not used |
almost_full_out, |
full_out, |
almost_empty_out, |
82,9 → 81,6
// reset input |
input reset_in; |
|
// flush input |
//input flush_in ; // not used |
|
// almost full and empy status outputs |
output almost_full_out, almost_empty_out; |
|
109,8 → 105,9
|
// grey code registers |
// grey code pipeline for write address |
reg [(ADDR_LENGTH - 1):0] wgrey_addr ; // current |
reg [(ADDR_LENGTH - 1):0] wgrey_next ; // next |
reg [(ADDR_LENGTH - 1):0] wgrey_minus1 ; // previous |
reg [(ADDR_LENGTH - 1):0] wgrey_addr ; // current |
reg [(ADDR_LENGTH - 1):0] wgrey_next ; // next |
|
// next write gray address calculation - bitwise xor between address and shifted address |
wire [(ADDR_LENGTH - 2):0] calc_wgrey_next = waddr[(ADDR_LENGTH - 1):1] ^ waddr[(ADDR_LENGTH - 2):0] ; |
124,43 → 121,15
// next read gray address calculation - bitwise xor between address and shifted address |
wire [(ADDR_LENGTH - 2):0] calc_rgrey_next = raddr[(ADDR_LENGTH - 1):1] ^ raddr[(ADDR_LENGTH - 2):0] ; |
|
// FFs for registered empty and full flags |
wire empty ; |
wire full ; |
// write allow - writes are allowed when fifo is not full |
assign wallow_out = wenable_in & ~full_out ; |
|
// registered almost_empty and almost_full flags |
wire almost_empty ; |
wire almost_full ; |
|
// write allow wire - writes are allowed when fifo is not full |
wire wallow = wenable_in && !full ; |
|
// write allow output assignment |
assign wallow_out = wallow ; |
|
// read allow wire |
wire rallow ; |
|
// full output assignment |
assign full_out = full ; |
|
// almost full output assignment |
assign almost_full_out = almost_full && !full ; |
|
// clear generation for FFs and registers |
wire clear = reset_in /*|| flush_in*/ ; // flush not used for write fifo |
wire clear = reset_in ; |
|
assign empty_out = empty ; |
|
//rallow generation |
assign rallow = renable_in && !empty ; // reads allowed if read enable is high and FIFO is not empty |
assign rallow_out = renable_in & ~empty_out ; // reads allowed if read enable is high and FIFO is not empty |
|
// rallow output assignment |
assign rallow_out = rallow ; |
|
// almost empty output assignment |
assign almost_empty_out = almost_empty && !empty ; |
|
// at any clock edge that rallow is high, this register provides next read address, so wait cycles are not necessary |
// when FIFO is empty, this register provides actual read address, so first location can be read |
reg [(ADDR_LENGTH - 1):0] raddr_plus_one ; |
168,7 → 137,7
|
// read address mux - when read is performed, next address is driven, so next data is available immediately after read |
// this is convenient for zero wait stait bursts |
assign raddr_out = rallow ? raddr_plus_one : raddr ; |
assign raddr_out = rallow_out ? raddr_plus_one : raddr ; |
|
always@(posedge rclock_in or posedge clear) |
begin |
178,7 → 147,7
raddr_plus_one <= #`FF_DELAY 5 ; |
raddr <= #`FF_DELAY 4 ; |
end |
else if (rallow) |
else if (rallow_out) |
begin |
raddr_plus_one <= #`FF_DELAY raddr_plus_one + 1'b1 ; |
raddr <= #`FF_DELAY raddr_plus_one ; |
198,25 → 167,26
begin |
if (clear) |
begin |
rgrey_minus2 <= #`FF_DELAY 0 ; |
rgrey_minus2 <= #1 0 ; |
rgrey_minus1 <= #`FF_DELAY 1 ; |
rgrey_addr <= #`FF_DELAY 3 ; |
rgrey_addr <= #1 3 ; |
rgrey_next <= #`FF_DELAY 2 ; |
end |
else |
if (rallow) |
if (rallow_out) |
begin |
rgrey_minus2 <= #`FF_DELAY rgrey_minus1 ; |
rgrey_minus2 <= #1 rgrey_minus1 ; |
rgrey_minus1 <= #`FF_DELAY rgrey_addr ; |
rgrey_addr <= #`FF_DELAY rgrey_next ; |
rgrey_addr <= #1 rgrey_next ; |
rgrey_next <= #`FF_DELAY {raddr[ADDR_LENGTH - 1], calc_rgrey_next} ; |
end |
end |
|
/*-------------------------------------------------------------------------------------------- |
Write address control consists of write address counter and 2 Grey Code Registers: |
- wgrey_addr represents current Grey Coded write address |
- wgrey_next represents Grey Coded next write address |
Write address control consists of write address counter and 3 Grey Code Registers: |
- wgrey_minus1 represents previous Grey coded write address |
- wgrey_addr represents current Grey Coded write address |
- wgrey_next represents Grey Coded next write address |
----------------------------------------------------------------------------------------------*/ |
// grey coded address pipeline for status generation in write clock domain |
always@(posedge wclock_in or posedge clear) |
223,13 → 193,15
begin |
if (clear) |
begin |
wgrey_addr <= #`FF_DELAY 3 ; |
wgrey_minus1 <= #`FF_DELAY 1 ; |
wgrey_addr <= #1 3 ; |
wgrey_next <= #`FF_DELAY 2 ; |
end |
else |
if (wallow) |
if (wallow_out) |
begin |
wgrey_addr <= #`FF_DELAY wgrey_next ; |
wgrey_minus1 <= #`FF_DELAY wgrey_addr ; |
wgrey_addr <= #1 wgrey_next ; |
wgrey_next <= #`FF_DELAY {waddr[(ADDR_LENGTH - 1)], calc_wgrey_next} ; |
end |
end |
241,36 → 213,21
// initial value 5 |
waddr <= #`FF_DELAY 4 ; |
else |
if (wallow) |
if (wallow_out) |
waddr <= #`FF_DELAY waddr + 1'b1 ; |
end |
|
/*------------------------------------------------------------------------------------------------------------------------------ |
Full control: |
Gray coded read address pointer is synchronized to write clock domain and compared to Gray coded next write address. |
If they are equal, fifo is full. |
Gray coded address of read address decremented by two is synchronized to write clock domain and compared to: |
- previous grey coded write address - if they are equal, the fifo is full |
|
Almost full control: |
Gray coded address of read address decremented by two is synchronized to write clock domain and compared to Gray coded write |
address. If they are equal, fifo is almost full. |
- gray coded write address. If they are equal, fifo is almost full. |
|
Two left control: |
If Gray coded next write address is equal to Gray coded address of read address decremented by two, the fifo has two free |
locations left. |
- grey coded next write address. If they are equal, the fifo has two free locations left. |
--------------------------------------------------------------------------------------------------------------------------------*/ |
wire [(ADDR_LENGTH - 1):0] wclk_sync_rgrey_addr ; |
reg [(ADDR_LENGTH - 1):0] wclk_rgrey_addr ; |
wire [(ADDR_LENGTH - 1):0] wclk_sync_rgrey_minus2 ; |
reg [(ADDR_LENGTH - 1):0] wclk_rgrey_minus2 ; |
|
synchronizer_flop #(ADDR_LENGTH, 3) i_synchronizer_reg_rgrey_addr |
( |
.data_in (rgrey_addr), |
.clk_out (wclock_in), |
.sync_data_out (wclk_sync_rgrey_addr), |
.async_reset (clear) |
) ; |
|
synchronizer_flop #(ADDR_LENGTH, 0) i_synchronizer_reg_rgrey_minus2 |
( |
.data_in (rgrey_minus2), |
283,19 → 240,17
begin |
if (clear) |
begin |
wclk_rgrey_addr <= #`FF_DELAY 3 ; |
wclk_rgrey_minus2 <= #`FF_DELAY 0 ; |
end |
else |
begin |
wclk_rgrey_addr <= #`FF_DELAY wclk_sync_rgrey_addr ; |
wclk_rgrey_minus2 <= #`FF_DELAY wclk_sync_rgrey_minus2 ; |
end |
end |
|
assign full = (wgrey_next == wclk_rgrey_addr) ; |
assign almost_full = (wgrey_addr == wclk_rgrey_minus2) ; |
assign two_left_out = (wgrey_next == wclk_rgrey_minus2) ; |
assign full_out = (wgrey_minus1 == wclk_rgrey_minus2) ; |
assign almost_full_out = (wgrey_addr == wclk_rgrey_minus2) ; |
assign two_left_out = (wgrey_next == wclk_rgrey_minus2) ; |
|
/*------------------------------------------------------------------------------------------------------------------------------ |
Empty control: |
324,6 → 279,6
rclk_wgrey_addr <= #`FF_DELAY rclk_sync_wgrey_addr ; |
end |
|
assign almost_empty = (rgrey_next == rclk_wgrey_addr) ; |
assign empty = (rgrey_addr == rclk_wgrey_addr) ; |
assign almost_empty_out = (rgrey_next == rclk_wgrey_addr) ; |
assign empty_out = (rgrey_addr == rclk_wgrey_addr) ; |
endmodule |
/trunk/sim/rtl_sim/log/parse_monitor_logs.scr
0,0 → 1,75
#!/bin/bash |
|
for pci_mon_log in `ls *pci_mon.log` ; do |
|
echo "Parsing:" $pci_mon_log |
|
# split log file into sections |
csplit -s -f "pci_mon_part" \ |
./$pci_mon_log /"Monitor will complain in following section for a few times - testbench is intentionally causing parity errors"/ {*} |
|
for pci_mon_log_part in `ls pci_mon_part*` ; do |
|
if [ $pci_mon_log_part == "pci_mon_part00" ] ; then |
lines_in_part0=`wc -l < ./pci_mon_part00` |
if [ $lines_in_part0 -ne 1 ] ; then |
echo "WARNING! Error detected before the first section of pci monitor expected messages!" |
fi |
|
rm $pci_mon_log_part |
continue |
|
fi |
|
# parts of log file should now consist of sections between start and end marker of monitor complaining |
# check if the last line contains an end complaining section marker |
|
last_line_is_end_marker=$(tail -n 1 $pci_mon_log_part | grep -c "End of Monitor complaining section") |
|
if [ $last_line_is_end_marker -ne 1 ] ; then |
echo "WARNING! Unexpected warning or error detected in the "$pci_mon_log" file!" |
fi |
rm $pci_mon_log_part |
done |
done |
|
for pciu_mon_log in `ls *pciu_mon.log` ; do |
|
echo "Parsing:" $pciu_mon_log |
|
# split log file into sections |
csplit -s -f "pciu_mon_part" \ |
./$pciu_mon_log /"Monitor should complain in following section for two times about STB de-asserted without slave response"/ {*} |
|
for pciu_mon_log_part in `ls pciu_mon_part*` ; do |
|
if [ $pciu_mon_log_part == "pciu_mon_part00" ] ; then |
lines_in_part0=`wc -l < ./pciu_mon_part00` |
if [ $lines_in_part0 -ne 1 ] ; then |
echo "WARNING! Error detected before the first section of pciu monitor expected messages!" |
fi |
|
rm $pciu_mon_log_part |
continue |
|
fi |
|
# parts of log file should now consist of sections between start and end marker of monitor complaining |
# check if the last line contains an end complaining section marker |
|
last_line_is_end_marker=$(tail -n 1 $pciu_mon_log_part | grep -c "Monitor should NOT complain any more") |
|
if [ $last_line_is_end_marker -ne 1 ] ; then |
echo "WARNING! Unexpected warning or error detected in the "$pciu_mon_log" file!" |
fi |
rm $pciu_mon_log_part |
done |
done |
|
for wbu_mon_log in `ls *wbu_mon.log` ; do |
echo "Parsing: "$wbu_mon_log |
num_of_lines_in_wbu_log=$(wc -l < $wbu_mon_log) |
if [ $num_of_lines_in_wbu_log -ne 1 ] ; then |
echo "WARNING! Unexpected warning or error detected in the "$wbu_mon_log" file!" |
fi |
done |
trunk/sim/rtl_sim/log/parse_monitor_logs.scr
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/sim/rtl_sim/run/run_pci_sim_regr.scr
===================================================================
--- trunk/sim/rtl_sim/run/run_pci_sim_regr.scr (revision 103)
+++ trunk/sim/rtl_sim/run/run_pci_sim_regr.scr (revision 104)
@@ -2,20 +2,10 @@
set arg_num = $#argv; # number of arguments
-if ($arg_num > 4) then
- echo " Too many parameters ( $arg_num )"
- echo " Maximum number of parameters is 4:"
- echo " - xilinx"
- echo " - artisan"
- echo " - regression"
- echo " - waves"
- exit
-endif
-
# current iterration
set iter = 1;
# number of tests with DEFINES + test with user defined constants!
-set all_iterations = 13;
+set all_iterations = 14;
# variables
set iter_failed = 0;
@@ -37,38 +27,45 @@
set arg_check = 0
while($arg_num <= $#argv)
- if ($argv[$arg_num] == "help") then
+ if ($argv[$arg_num] == "help") then
goto help
- endif
+ endif
- if ($argv[$arg_num] == "regression") then
+ if ($argv[$arg_num] == "regression") then
@ arg_regression = 1
@ arg_check = $arg_check + 1
- endif
-
- if ($argv[$arg_num] == "xilinx") then
+ endif
+
+ if ($argv[$arg_num] == "xilinx") then
@ arg_xilinx = 1
@ arg_check = $arg_check + 1
- endif
+ endif
- if($argv[$arg_num] == "artisan") then
+ if($argv[$arg_num] == "artisan") then
@ arg_artisan = 1
@ arg_check = $arg_check + 1
- endif
-
- if ($argv[$arg_num] == "waves") then
+ endif
+
+ if ($argv[$arg_num] == "waves") then
@ arg_waves = 1
@ arg_check = $arg_check + 1
- endif
+ endif
- if ($argv[$arg_num] == "vs_two_port") then
+ if ($argv[$arg_num] == "vs_two_port") then
@ arg_vs_hdtp = 1
@ arg_check = $arg_check + 1
- endif
+ endif
- if ($argv[$arg_num] == "disable_completion_expired_tests") then
+ if ($argv[$arg_num] == "disable_completion_expired_tests") then
@ arg_dis_comp_exp_test = 1
@ arg_check = $arg_check + 1
+ endif
+
+ if ($argv[$arg_num] == "iter") then
+ @ arg_num = $arg_num + 1
+ @ arg_check = $arg_check + 2
+ @ iter = $argv[$arg_num]
+ @ all_iterations = $iter
endif
if ($arg_check != $arg_num) then
@@ -88,389 +85,441 @@
echo "<<<"
-# Preparing defines into file
-
if ($arg_regression == 1) then
- if ($iter < $all_iterations) then
- if (($arg_xilinx == 0) && ($arg_artisan == 0)) then
- if ($iter == 1) then
- echo "<<< Defines:"
- echo "\tHOST, REGR_FIFO_SMALL_GENERIC, WB_DECODE_FAST, PCI_DECODE_MAX, "
- echo "\tWB_DECODE_MIN, PCI33, WB_CLK10, ACTIVE_LOW_OE, REGISTER_WBM_OUTPUTS, "
- echo "\tREGISTER_WBS_OUTPUTS, ADDR_TRAN_IMPL, PCI_IMAGE0, PCI_IMAGE2. "
- echo "-DEFINE REGRESSION -DEFINE HOST -DEFINE REGR_FIFO_SMALL_GENERIC -DEFINE WB_DECODE_FAST -DEFINE PCI_DECODE_MAX -DEFINE WB_DECODE_MIN -DEFINE PCI33 -DEFINE WB_CLK10 -DEFINE ACTIVE_LOW_OE -DEFINE REGISTER_WBM_OUTPUTS -DEFINE REGISTER_WBS_OUTPUTS -DEFINE ADDR_TRAN_IMPL -DEFINE PCI_IMAGE0 -DEFINE PCI_IMAGE2" > ./defines.args
- endif
- if ($iter == 2) then
- echo "<<< Defines:"
- echo "\tHOST, REGR_FIFO_MEDIUM_GENERIC, WB_DECODE_MEDIUM, PCI_DECODE_MED, "
- echo "\tWB_DECODE_MED, PCI33, WB_CLK66, ACTIVE_LOW_OE, REGISTER_WBM_OUTPUTS, "
- echo "\tREGISTER_WBS_OUTPUTS, ADDR_TRAN_IMPL, PCI_IMAGE0, PCI_IMAGE2, "
- echo "\tPCI_IMAGE3, PCI_IMAGE4, PCI_IMAGE5, WB_IMAGE2, WB_IMAGE5. "
- echo "-DEFINE REGRESSION -DEFINE HOST -DEFINE REGR_FIFO_MEDIUM_GENERIC -DEFINE WB_DECODE_MEDIUM -DEFINE PCI_DECODE_MED -DEFINE WB_DECODE_MED -DEFINE PCI33 -DEFINE WB_CLK66 -DEFINE ACTIVE_LOW_OE -DEFINE REGISTER_WBM_OUTPUTS -DEFINE REGISTER_WBS_OUTPUTS -DEFINE ADDR_TRAN_IMPL -DEFINE PCI_IMAGE0 -DEFINE PCI_IMAGE2 -DEFINE PCI_IMAGE3 -DEFINE PCI_IMAGE4 -DEFINE PCI_IMAGE5 -DEFINE WB_IMAGE2 -DEFINE WB_IMAGE5" > ./defines.args
- endif
- if ($iter == 3) then
- echo "<<< Defines:"
- echo "\tHOST, REGR_FIFO_LARGE_GENERIC, WB_DECODE_SLOW, PCI_DECODE_MIN, "
- echo "\tWB_DECODE_MAX, PCI66, WB_CLK66, ACTIVE_LOW_OE, REGISTER_WBM_OUTPUTS, "
- echo "\tREGISTER_WBS_OUTPUTS, WB_IMAGE5. "
- echo "-DEFINE REGRESSION -DEFINE HOST -DEFINE REGR_FIFO_LARGE_GENERIC -DEFINE WB_DECODE_SLOW -DEFINE PCI_DECODE_MIN -DEFINE WB_DECODE_MAX -DEFINE PCI66 -DEFINE WB_CLK66 -DEFINE ACTIVE_LOW_OE -DEFINE REGISTER_WBM_OUTPUTS -DEFINE REGISTER_WBS_OUTPUTS -DEFINE WB_IMAGE5" > ./defines.args
- endif
- if ($iter == 4) then
- echo "<<< Defines:"
- echo "\tGUEST, REGR_FIFO_SMALL_GENERIC, WB_DECODE_SLOW, PCI_DECODE_MED, "
- echo "\tWB_DECODE_MIN, PCI66, WB_CLK220, ACTIVE_LOW_OE, REGISTER_WBM_OUTPUTS, "
- echo "\tREGISTER_WBS_OUTPUTS, PCI_IMAGE0, PCI_IMAGE5, WB_IMAGE4. "
- echo "-DEFINE REGRESSION -DEFINE GUEST -DEFINE REGR_FIFO_SMALL_GENERIC -DEFINE WB_DECODE_SLOW -DEFINE PCI_DECODE_MED -DEFINE WB_DECODE_MIN -DEFINE PCI66 -DEFINE WB_CLK220 -DEFINE ACTIVE_LOW_OE -DEFINE REGISTER_WBM_OUTPUTS -DEFINE REGISTER_WBS_OUTPUTS -DEFINE PCI_IMAGE0 -DEFINE PCI_IMAGE5 -DEFINE WB_IMAGE4" > ./defines.args
- endif
- if ($iter == 5) then
- echo "<<< Defines:"
- echo "\tGUEST, REGR_FIFO_MEDIUM_GENERIC, WB_DECODE_FAST, PCI_DECODE_MIN, "
- echo "\tWB_DECODE_MAX, PCI33, WB_CLK220, ACTIVE_LOW_OE, REGISTER_WBM_OUTPUTS, "
- echo "\tREGISTER_WBS_OUTPUTS, ADDR_TRAN_IMPL, PCI_IMAGE0, PCI_IMAGE2, "
- echo "\tWB_IMAGE2, WB_IMAGE3, WB_IMAGE4. "
- echo "-DEFINE REGRESSION -DEFINE GUEST -DEFINE REGR_FIFO_MEDIUM_GENERIC -DEFINE WB_DECODE_FAST -DEFINE PCI_DECODE_MIN -DEFINE WB_DECODE_MAX -DEFINE PCI33 -DEFINE WB_CLK220 -DEFINE ACTIVE_LOW_OE -DEFINE REGISTER_WBM_OUTPUTS -DEFINE REGISTER_WBS_OUTPUTS -DEFINE ADDR_TRAN_IMPL -DEFINE PCI_IMAGE0 -DEFINE PCI_IMAGE2 -DEFINE WB_IMAGE2 -DEFINE WB_IMAGE3 -DEFINE WB_IMAGE4" > ./defines.args
- endif
- if ($iter == 6) then
- echo "<<< Defines:"
- echo "\tGUEST, REGR_FIFO_LARGE_GENERIC, WB_DECODE_MEDIUM, PCI_DECODE_MAX, "
- echo "\tWB_DECODE_MED, PCI66, WB_CLK10, ACTIVE_LOW_OE, REGISTER_WBM_OUTPUTS, "
- echo "\tREGISTER_WBS_OUTPUTS, ADDR_TRAN_IMPL. "
- echo "-DEFINE REGRESSION -DEFINE GUEST -DEFINE REGR_FIFO_LARGE_GENERIC -DEFINE WB_DECODE_MEDIUM -DEFINE PCI_DECODE_MAX -DEFINE WB_DECODE_MED -DEFINE PCI66 -DEFINE WB_CLK10 -DEFINE ACTIVE_LOW_OE -DEFINE REGISTER_WBM_OUTPUTS -DEFINE REGISTER_WBS_OUTPUTS -DEFINE ADDR_TRAN_IMPL" > ./defines.args
- endif
- if ($iter == 7) then
- echo "<<< Defines:"
- echo "\tHOST, REGR_FIFO_SMALL_GENERIC, WB_DECODE_FAST, PCI_DECODE_MAX, "
- echo "\tWB_DECODE_MIN, PCI66, WB_CLK220, ACTIVE_HIGH_OE, WB_CNF_BASE_ZERO, "
- echo "\tNO_CNF_IMAGE, PCI_IMAGE0, PCI_IMAGE4. "
- echo "-DEFINE REGRESSION -DEFINE HOST -DEFINE REGR_FIFO_SMALL_GENERIC -DEFINE WB_DECODE_FAST -DEFINE PCI_DECODE_MAX -DEFINE WB_DECODE_MIN -DEFINE PCI66 -DEFINE WB_CLK220 -DEFINE ACTIVE_HIGH_OE -DEFINE WB_CNF_BASE_ZERO -DEFINE NO_CNF_IMAGE -DEFINE PCI_IMAGE0 -DEFINE PCI_IMAGE4" > ./defines.args
- endif
- if ($iter == 8) then
- echo "<<< Defines:"
- echo "\tHOST, REGR_FIFO_MEDIUM_GENERIC, WB_DECODE_MEDIUM, PCI_DECODE_MED, "
- echo "\tWB_DECODE_MED, PCI66, WB_CLK10, ACTIVE_HIGH_OE, WB_CNF_BASE_ZERO, "
- echo "\tNO_CNF_IMAGE, PCI_IMAGE0, PCI_IMAGE2, PCI_IMAGE3, PCI_IMAGE4, "
- echo "\tPCI_IMAGE5, WB_IMAGE2, WB_IMAGE3, WB_IMAGE4, WB_IMAGE5. "
- echo "-DEFINE REGRESSION -DEFINE HOST -DEFINE REGR_FIFO_MEDIUM_GENERIC -DEFINE WB_DECODE_MEDIUM -DEFINE PCI_DECODE_MED -DEFINE WB_DECODE_MED -DEFINE PCI66 -DEFINE WB_CLK10 -DEFINE ACTIVE_HIGH_OE -DEFINE WB_CNF_BASE_ZERO -DEFINE NO_CNF_IMAGE -DEFINE PCI_IMAGE0 -DEFINE PCI_IMAGE2 -DEFINE PCI_IMAGE3 -DEFINE PCI_IMAGE4 -DEFINE PCI_IMAGE5 -DEFINE WB_IMAGE2 -DEFINE WB_IMAGE3 -DEFINE WB_IMAGE4 -DEFINE WB_IMAGE5" > ./defines.args
- endif
- if ($iter == 9) then
- echo "<<< Defines:"
- echo "\tHOST, REGR_FIFO_LARGE_GENERIC, WB_DECODE_SLOW, PCI_DECODE_MIN, "
- echo "\tWB_DECODE_MAX, PCI33, WB_CLK220, ACTIVE_HIGH_OE, ADDR_TRAN_IMPL, "
- echo "\tWB_CNF_BASE_ZERO, NO_CNF_IMAGE, WB_IMAGE3. "
- echo "-DEFINE REGRESSION -DEFINE HOST -DEFINE REGR_FIFO_LARGE_GENERIC -DEFINE WB_DECODE_SLOW -DEFINE PCI_DECODE_MIN -DEFINE WB_DECODE_MAX -DEFINE PCI33 -DEFINE WB_CLK220 -DEFINE ACTIVE_HIGH_OE -DEFINE ADDR_TRAN_IMPL -DEFINE WB_CNF_BASE_ZERO -DEFINE NO_CNF_IMAGE -DEFINE WB_IMAGE3" > ./defines.args
- endif
- if ($iter == 10) then
- echo "<<< Defines:"
- echo "\tGUEST, REGR_FIFO_SMALL_GENERIC, WB_DECODE_SLOW, PCI_DECODE_MED, "
- echo "\tWB_DECODE_MIN, PCI33, WB_CLK66, ACTIVE_HIGH_OE, ADDR_TRAN_IMPL, "
- echo "\tWB_CNF_BASE_ZERO, NO_CNF_IMAGE, PCI_IMAGE0, PCI_IMAGE3. "
- echo "-DEFINE REGRESSION -DEFINE GUEST -DEFINE REGR_FIFO_SMALL_GENERIC -DEFINE WB_DECODE_SLOW -DEFINE PCI_DECODE_MED -DEFINE WB_DECODE_MIN -DEFINE PCI33 -DEFINE WB_CLK66 -DEFINE ACTIVE_HIGH_OE -DEFINE ADDR_TRAN_IMPL -DEFINE WB_CNF_BASE_ZERO -DEFINE NO_CNF_IMAGE -DEFINE PCI_IMAGE0 -DEFINE PCI_IMAGE3" > ./defines.args
- endif
- if ($iter == 11) then
- echo "<<< Defines:"
- echo "\tGUEST, REGR_FIFO_MEDIUM_GENERIC, WB_DECODE_FAST, PCI_DECODE_MIN, "
- echo "\tWB_DECODE_MAX, PCI66, WB_CLK66, ACTIVE_HIGH_OE, WB_CNF_BASE_ZERO, "
- echo "\tNO_CNF_IMAGE, PCI_IMAGE0, PCI_IMAGE2, PCI_IMAGE3, PCI_IMAGE4, "
- echo "\tPCI_IMAGE5, WB_IMAGE2. "
- echo "-DEFINE REGRESSION -DEFINE GUEST -DEFINE REGR_FIFO_MEDIUM_GENERIC -DEFINE WB_DECODE_FAST -DEFINE PCI_DECODE_MIN -DEFINE WB_DECODE_MAX -DEFINE PCI66 -DEFINE WB_CLK66 -DEFINE ACTIVE_HIGH_OE -DEFINE WB_CNF_BASE_ZERO -DEFINE NO_CNF_IMAGE -DEFINE PCI_IMAGE0 -DEFINE PCI_IMAGE2 -DEFINE PCI_IMAGE3 -DEFINE PCI_IMAGE4 -DEFINE PCI_IMAGE5 -DEFINE WB_IMAGE2" > ./defines.args
- endif
- if ($iter == 12) then
- echo "<<< Defines:"
- echo "\tGUEST, REGR_FIFO_LARGE_GENERIC, WB_DECODE_MEDIUM, PCI_DECODE_MAX, "
- echo "\tWB_DECODE_MED, PCI33, WB_CLK10, ACTIVE_HIGH_OE, WB_CNF_BASE_ZERO, "
- echo "\tNO_CNF_IMAGE, WB_IMAGE2, WB_IMAGE3, WB_IMAGE4, WB_IMAGE5. "
- echo "-DEFINE REGRESSION -DEFINE GUEST -DEFINE REGR_FIFO_LARGE_GENERIC -DEFINE WB_DECODE_MEDIUM -DEFINE PCI_DECODE_MAX -DEFINE WB_DECODE_MED -DEFINE PCI33 -DEFINE WB_CLK10 -DEFINE ACTIVE_HIGH_OE -DEFINE WB_CNF_BASE_ZERO -DEFINE NO_CNF_IMAGE -DEFINE WB_IMAGE2 -DEFINE WB_IMAGE3 -DEFINE WB_IMAGE4 -DEFINE WB_IMAGE5" > ./defines.args
- endif
+ # Preparing defines into file
+ if ($iter <= $all_iterations) then
- if ($arg_dis_comp_exp_test) then
- echo "-DEFINE DISABLE_COMPLETION_EXPIRED_TESTS" >> ./defines.args
+ if ($iter == 1) then
+ echo "<<< Defines:"
+
+ if ($arg_xilinx == 0) then
+ echo "\tREGR_FIFO_SMALL_GENERIC, "
+ else
+ echo "\tREGR_FIFO_SMALL_XILINX, "
+ endif
+
+ echo "\tHOST, WB_DECODE_FAST, PCI_DECODE_MAX, "
+ echo "\tWB_DECODE_MIN, PCI33, WB_CLK10, ACTIVE_LOW_OE, REGISTER_WBM_OUTPUTS, "
+ echo "\tREGISTER_WBS_OUTPUTS, ADDR_TRAN_IMPL, PCI_IMAGE0, PCI_IMAGE2. "
+
+ echo "-DEFINE REGRESSION" > ./defines.args
+
+ if ($arg_xilinx == 0) then
+ echo "-DEFINE REGR_FIFO_SMALL_GENERIC" >> ./defines.args
+ else
+ echo "-DEFINE REGR_FIFO_SMALL_XILINX" >> ./defines.args
+ endif
+
+ echo "-DEFINE HOST " >> ./defines.args
+ echo "-DEFINE WB_DECODE_FAST " >> ./defines.args
+ echo "-DEFINE PCI_DECODE_MAX " >> ./defines.args
+ echo "-DEFINE WB_DECODE_MIN " >> ./defines.args
+ echo "-DEFINE PCI33 " >> ./defines.args
+ echo "-DEFINE WB_CLK10 " >> ./defines.args
+ echo "-DEFINE ACTIVE_LOW_OE " >> ./defines.args
+ echo "-DEFINE REGISTER_WBM_OUTPUTS" >> ./defines.args
+ echo "-DEFINE REGISTER_WBS_OUTPUTS" >> ./defines.args
+ echo "-DEFINE ADDR_TRAN_IMPL " >> ./defines.args
+ echo "-DEFINE PCI_IMAGE0 " >> ./defines.args
+ echo "-DEFINE PCI_IMAGE2 " >> ./defines.args
+
endif
- else
- if (($arg_xilinx == 0) && ($arg_artisan == 1)) then
- if ($iter == 1) then
- echo "<<< Defines:"
- echo "\tHOST, REGR_FIFO_SMALL_GENERIC, WB_DECODE_FAST, PCI_DECODE_MAX, "
- echo "\tWB_DECODE_MIN, PCI33, WB_CLK10, ACTIVE_LOW_OE, REGISTER_WBM_OUTPUTS, "
- echo "\tREGISTER_WBS_OUTPUTS, ADDR_TRAN_IMPL, PCI_IMAGE0, PCI_IMAGE2. "
- echo "-DEFINE REGRESSION -DEFINE HOST -DEFINE REGR_FIFO_SMALL_GENERIC -DEFINE WB_DECODE_FAST -DEFINE PCI_DECODE_MAX -DEFINE WB_DECODE_MIN -DEFINE PCI33 -DEFINE WB_CLK10 -DEFINE ACTIVE_LOW_OE -DEFINE REGISTER_WBM_OUTPUTS -DEFINE REGISTER_WBS_OUTPUTS -DEFINE ADDR_TRAN_IMPL -DEFINE PCI_IMAGE0 -DEFINE PCI_IMAGE2" > ./defines.args
- endif
- if ($iter == 2) then
- echo "<<< Defines:"
- echo "\tHOST, REGR_FIFO_MEDIUM_ARTISAN, WB_DECODE_MEDIUM, PCI_DECODE_MED, "
- echo "\tWB_DECODE_MED, PCI33, WB_CLK66, ACTIVE_LOW_OE, REGISTER_WBM_OUTPUTS, "
- echo "\tREGISTER_WBS_OUTPUTS, ADDR_TRAN_IMPL, PCI_IMAGE0, PCI_IMAGE2, "
- echo "\tPCI_IMAGE3, PCI_IMAGE4, PCI_IMAGE5, WB_IMAGE2, WB_IMAGE5. "
- echo "-DEFINE REGRESSION -DEFINE HOST -DEFINE REGR_FIFO_MEDIUM_ARTISAN -DEFINE WB_DECODE_MEDIUM -DEFINE PCI_DECODE_MED -DEFINE WB_DECODE_MED -DEFINE PCI33 -DEFINE WB_CLK66 -DEFINE ACTIVE_LOW_OE -DEFINE REGISTER_WBM_OUTPUTS -DEFINE REGISTER_WBS_OUTPUTS -DEFINE ADDR_TRAN_IMPL -DEFINE PCI_IMAGE0 -DEFINE PCI_IMAGE2 -DEFINE PCI_IMAGE3 -DEFINE PCI_IMAGE4 -DEFINE PCI_IMAGE5 -DEFINE WB_IMAGE2 -DEFINE WB_IMAGE5" > ./defines.args
- endif
- if ($iter == 3) then
- echo "<<< Defines:"
- echo "\tHOST, REGR_FIFO_LARGE_GENERIC, WB_DECODE_SLOW, PCI_DECODE_MIN, "
- echo "\tWB_DECODE_MAX, PCI66, WB_CLK66, ACTIVE_LOW_OE, REGISTER_WBM_OUTPUTS, "
- echo "\tREGISTER_WBS_OUTPUTS, WB_IMAGE5. "
- echo "-DEFINE REGRESSION -DEFINE HOST -DEFINE REGR_FIFO_LARGE_GENERIC -DEFINE WB_DECODE_SLOW -DEFINE PCI_DECODE_MIN -DEFINE WB_DECODE_MAX -DEFINE PCI66 -DEFINE WB_CLK66 -DEFINE ACTIVE_LOW_OE -DEFINE REGISTER_WBM_OUTPUTS -DEFINE REGISTER_WBS_OUTPUTS -DEFINE WB_IMAGE5" > ./defines.args
- endif
- if ($iter == 4) then
- echo "<<< Defines:"
- echo "\tGUEST, REGR_FIFO_SMALL_GENERIC, WB_DECODE_SLOW, PCI_DECODE_MED, "
- echo "\tWB_DECODE_MIN, PCI66, WB_CLK220, ACTIVE_LOW_OE, REGISTER_WBM_OUTPUTS, "
- echo "\tREGISTER_WBS_OUTPUTS, PCI_IMAGE0, PCI_IMAGE5, WB_IMAGE4. "
- echo "-DEFINE REGRESSION -DEFINE GUEST -DEFINE REGR_FIFO_SMALL_GENERIC -DEFINE WB_DECODE_SLOW -DEFINE PCI_DECODE_MED -DEFINE WB_DECODE_MIN -DEFINE PCI66 -DEFINE WB_CLK220 -DEFINE ACTIVE_LOW_OE -DEFINE REGISTER_WBM_OUTPUTS -DEFINE REGISTER_WBS_OUTPUTS -DEFINE PCI_IMAGE0 -DEFINE PCI_IMAGE5 -DEFINE WB_IMAGE4" > ./defines.args
- endif
- if ($iter == 5) then
- echo "<<< Defines:"
- echo "\tGUEST, REGR_FIFO_MEDIUM_ARTISAN, WB_DECODE_FAST, PCI_DECODE_MIN, "
- echo "\tWB_DECODE_MAX, PCI33, WB_CLK220, ACTIVE_LOW_OE, REGISTER_WBM_OUTPUTS, "
- echo "\tREGISTER_WBS_OUTPUTS, ADDR_TRAN_IMPL, PCI_IMAGE0, PCI_IMAGE2, "
- echo "\tWB_IMAGE2, WB_IMAGE3, WB_IMAGE4. "
- echo "-DEFINE REGRESSION -DEFINE GUEST -DEFINE REGR_FIFO_MEDIUM_ARTISAN -DEFINE WB_DECODE_FAST -DEFINE PCI_DECODE_MIN -DEFINE WB_DECODE_MAX -DEFINE PCI33 -DEFINE WB_CLK220 -DEFINE ACTIVE_LOW_OE -DEFINE REGISTER_WBM_OUTPUTS -DEFINE REGISTER_WBS_OUTPUTS -DEFINE ADDR_TRAN_IMPL -DEFINE PCI_IMAGE0 -DEFINE PCI_IMAGE2 -DEFINE WB_IMAGE2 -DEFINE WB_IMAGE3 -DEFINE WB_IMAGE4" > ./defines.args
- endif
- if ($iter == 6) then
- echo "<<< Defines:"
- echo "\tGUEST, REGR_FIFO_LARGE_GENERIC, WB_DECODE_MEDIUM, PCI_DECODE_MAX, "
- echo "\tWB_DECODE_MED, PCI66, WB_CLK10, ACTIVE_LOW_OE, REGISTER_WBM_OUTPUTS, "
- echo "\tREGISTER_WBS_OUTPUTS, ADDR_TRAN_IMPL. "
- echo "-DEFINE REGRESSION -DEFINE GUEST -DEFINE REGR_FIFO_LARGE_GENERIC -DEFINE WB_DECODE_MEDIUM -DEFINE PCI_DECODE_MAX -DEFINE WB_DECODE_MED -DEFINE PCI66 -DEFINE WB_CLK10 -DEFINE ACTIVE_LOW_OE -DEFINE REGISTER_WBM_OUTPUTS -DEFINE REGISTER_WBS_OUTPUTS -DEFINE ADDR_TRAN_IMPL" > ./defines.args
- endif
- if ($iter == 7) then
- echo "<<< Defines:"
- echo "\tHOST, REGR_FIFO_SMALL_GENERIC, WB_DECODE_FAST, PCI_DECODE_MAX, "
- echo "\tWB_DECODE_MIN, PCI66, WB_CLK220, ACTIVE_HIGH_OE, WB_CNF_BASE_ZERO, "
- echo "\tNO_CNF_IMAGE, PCI_IMAGE0, PCI_IMAGE4. "
- echo "-DEFINE REGRESSION -DEFINE HOST -DEFINE REGR_FIFO_SMALL_GENERIC -DEFINE WB_DECODE_FAST -DEFINE PCI_DECODE_MAX -DEFINE WB_DECODE_MIN -DEFINE PCI66 -DEFINE WB_CLK220 -DEFINE ACTIVE_HIGH_OE -DEFINE WB_CNF_BASE_ZERO -DEFINE NO_CNF_IMAGE -DEFINE PCI_IMAGE0 -DEFINE PCI_IMAGE4" > ./defines.args
- endif
- if ($iter == 8) then
- echo "<<< Defines:"
- echo "\tHOST, REGR_FIFO_MEDIUM_ARTISAN, WB_DECODE_MEDIUM, PCI_DECODE_MED, "
- echo "\tWB_DECODE_MED, PCI66, WB_CLK10, ACTIVE_HIGH_OE, WB_CNF_BASE_ZERO, "
- echo "\tNO_CNF_IMAGE, PCI_IMAGE0, PCI_IMAGE2, PCI_IMAGE3, PCI_IMAGE4, "
- echo "\tPCI_IMAGE5, WB_IMAGE2, WB_IMAGE3, WB_IMAGE4, WB_IMAGE5. "
- echo "-DEFINE REGRESSION -DEFINE HOST -DEFINE REGR_FIFO_MEDIUM_ARTISAN -DEFINE WB_DECODE_MEDIUM -DEFINE PCI_DECODE_MED -DEFINE WB_DECODE_MED -DEFINE PCI66 -DEFINE WB_CLK10 -DEFINE ACTIVE_HIGH_OE -DEFINE WB_CNF_BASE_ZERO -DEFINE NO_CNF_IMAGE -DEFINE PCI_IMAGE0 -DEFINE PCI_IMAGE2 -DEFINE PCI_IMAGE3 -DEFINE PCI_IMAGE4 -DEFINE PCI_IMAGE5 -DEFINE WB_IMAGE2 -DEFINE WB_IMAGE3 -DEFINE WB_IMAGE4 -DEFINE WB_IMAGE5" > ./defines.args
- endif
- if ($iter == 9) then
- echo "<<< Defines:"
- echo "\tHOST, REGR_FIFO_LARGE_GENERIC, WB_DECODE_SLOW, PCI_DECODE_MIN, "
- echo "\tWB_DECODE_MAX, PCI33, WB_CLK220, ACTIVE_HIGH_OE, ADDR_TRAN_IMPL, "
- echo "\tWB_CNF_BASE_ZERO, NO_CNF_IMAGE, WB_IMAGE3. "
- echo "-DEFINE REGRESSION -DEFINE HOST -DEFINE REGR_FIFO_LARGE_GENERIC -DEFINE WB_DECODE_SLOW -DEFINE PCI_DECODE_MIN -DEFINE WB_DECODE_MAX -DEFINE PCI33 -DEFINE WB_CLK220 -DEFINE ACTIVE_HIGH_OE -DEFINE ADDR_TRAN_IMPL -DEFINE WB_CNF_BASE_ZERO -DEFINE NO_CNF_IMAGE -DEFINE WB_IMAGE3" > ./defines.args
- endif
- if ($iter == 10) then
- echo "<<< Defines:"
- echo "\tGUEST, REGR_FIFO_SMALL_GENERIC, WB_DECODE_SLOW, PCI_DECODE_MED, "
- echo "\tWB_DECODE_MIN, PCI33, WB_CLK66, ACTIVE_HIGH_OE, ADDR_TRAN_IMPL, "
- echo "\tWB_CNF_BASE_ZERO, NO_CNF_IMAGE, PCI_IMAGE0, PCI_IMAGE3. "
- echo "-DEFINE REGRESSION -DEFINE GUEST -DEFINE REGR_FIFO_SMALL_GENERIC -DEFINE WB_DECODE_SLOW -DEFINE PCI_DECODE_MED -DEFINE WB_DECODE_MIN -DEFINE PCI33 -DEFINE WB_CLK66 -DEFINE ACTIVE_HIGH_OE -DEFINE ADDR_TRAN_IMPL -DEFINE WB_CNF_BASE_ZERO -DEFINE NO_CNF_IMAGE -DEFINE PCI_IMAGE0 -DEFINE PCI_IMAGE3" > ./defines.args
- endif
- if ($iter == 11) then
- echo "<<< Defines:"
- echo "\tGUEST, REGR_FIFO_MEDIUM_ARTISAN, WB_DECODE_FAST, PCI_DECODE_MIN, "
- echo "\tWB_DECODE_MAX, PCI66, WB_CLK66, ACTIVE_HIGH_OE, WB_CNF_BASE_ZERO, "
- echo "\tNO_CNF_IMAGE, PCI_IMAGE0, PCI_IMAGE2, PCI_IMAGE3, PCI_IMAGE4, "
- echo "\tPCI_IMAGE5, WB_IMAGE2. "
- echo "-DEFINE REGRESSION -DEFINE GUEST -DEFINE REGR_FIFO_MEDIUM_ARTISAN -DEFINE WB_DECODE_FAST -DEFINE PCI_DECODE_MIN -DEFINE WB_DECODE_MAX -DEFINE PCI66 -DEFINE WB_CLK66 -DEFINE ACTIVE_HIGH_OE -DEFINE WB_CNF_BASE_ZERO -DEFINE NO_CNF_IMAGE -DEFINE PCI_IMAGE0 -DEFINE PCI_IMAGE2 -DEFINE PCI_IMAGE3 -DEFINE PCI_IMAGE4 -DEFINE PCI_IMAGE5 -DEFINE WB_IMAGE2" > ./defines.args
- endif
- if ($iter == 12) then
- echo "<<< Defines:"
- echo "\tGUEST, REGR_FIFO_LARGE_GENERIC, WB_DECODE_MEDIUM, PCI_DECODE_MAX, "
- echo "\tWB_DECODE_MED, PCI33, WB_CLK10, ACTIVE_HIGH_OE, WB_CNF_BASE_ZERO, "
- echo "\tNO_CNF_IMAGE, WB_IMAGE2, WB_IMAGE3, WB_IMAGE4, WB_IMAGE5. "
- echo "-DEFINE REGRESSION -DEFINE GUEST -DEFINE REGR_FIFO_LARGE_GENERIC -DEFINE WB_DECODE_MEDIUM -DEFINE PCI_DECODE_MAX -DEFINE WB_DECODE_MED -DEFINE PCI33 -DEFINE WB_CLK10 -DEFINE ACTIVE_HIGH_OE -DEFINE WB_CNF_BASE_ZERO -DEFINE NO_CNF_IMAGE -DEFINE WB_IMAGE2 -DEFINE WB_IMAGE3 -DEFINE WB_IMAGE4 -DEFINE WB_IMAGE5" > ./defines.args
- endif
+
+ if ($iter == 2) then
+
+ echo "<<< Defines:"
+
+ if ($arg_xilinx == 1) then
+ echo "\tREGR_FIFO_MEDIUM_XILINX, "
+ else if ($arg_artisan == 1) then
+ echo "\tREGR_FIFO_MEDIUM_ARTISAN, "
+ else
+ echo "\tREGR_FIFO_MEDIUM_GENERIC, "
+ endif
+
+ echo "\tHOST, WB_DECODE_MEDIUM, PCI_DECODE_MED, "
+ echo "\tWB_DECODE_MED, PCI33, WB_CLK66, ACTIVE_LOW_OE, REGISTER_WBM_OUTPUTS, "
+ echo "\tREGISTER_WBS_OUTPUTS, ADDR_TRAN_IMPL, PCI_IMAGE0, PCI_IMAGE2, "
+ echo "\tPCI_IMAGE3, PCI_IMAGE4, PCI_IMAGE5, WB_IMAGE2, WB_IMAGE5. "
+
+ echo "-DEFINE REGRESSION " > ./defines.args
+
+ if ($arg_xilinx == 1) then
+ echo "-DEFINE REGR_FIFO_MEDIUM_XILINX" >> ./defines.args
+ else if ($arg_artisan == 1) then
+ echo "-DEFINE REGR_FIFO_MEDIUM_ARTISAN" >> ./defines.args
+ else
+ echo "-DEFINE REGR_FIFO_MEDIUM_GENERIC" >> ./defines.args
+ endif
+
+ echo "-DEFINE HOST " >> ./defines.args
+ echo "-DEFINE WB_DECODE_MEDIUM " >> ./defines.args
+ echo "-DEFINE PCI_DECODE_MED " >> ./defines.args
+ echo "-DEFINE WB_DECODE_MED " >> ./defines.args
+ echo "-DEFINE PCI33 " >> ./defines.args
+ echo "-DEFINE WB_CLK66 " >> ./defines.args
+ echo "-DEFINE ACTIVE_LOW_OE " >> ./defines.args
+ echo "-DEFINE REGISTER_WBM_OUTPUTS" >> ./defines.args
+ echo "-DEFINE REGISTER_WBS_OUTPUTS" >> ./defines.args
+ echo "-DEFINE ADDR_TRAN_IMPL " >> ./defines.args
+ echo "-DEFINE PCI_IMAGE0 " >> ./defines.args
+ echo "-DEFINE PCI_IMAGE2 " >> ./defines.args
+ echo "-DEFINE PCI_IMAGE3 " >> ./defines.args
+ echo "-DEFINE PCI_IMAGE4 " >> ./defines.args
+ echo "-DEFINE PCI_IMAGE5 " >> ./defines.args
+ echo "-DEFINE WB_IMAGE2 " >> ./defines.args
+ echo "-DEFINE WB_IMAGE5 " >> ./defines.args
- if ($arg_dis_comp_exp_test) then
- echo "-DEFINE DISABLE_COMPLETION_EXPIRED_TESTS" >> ./defines.args
- endif
- else
- if (($arg_xilinx == 1) && ($arg_artisan == 1)) then
- if ($iter == 1) then
- echo "<<< Defines:"
- echo "\tHOST, REGR_FIFO_SMALL_XILINX, WB_DECODE_FAST, PCI_DECODE_MAX, "
- echo "\tWB_DECODE_MIN, PCI33, WB_CLK10, ACTIVE_LOW_OE, REGISTER_WBM_OUTPUTS, "
- echo "\tREGISTER_WBS_OUTPUTS, ADDR_TRAN_IMPL, PCI_IMAGE0, PCI_IMAGE2. "
- echo "-DEFINE REGRESSION -DEFINE HOST -DEFINE REGR_FIFO_SMALL_XILINX -DEFINE WB_DECODE_FAST -DEFINE PCI_DECODE_MAX -DEFINE WB_DECODE_MIN -DEFINE PCI33 -DEFINE WB_CLK10 -DEFINE ACTIVE_LOW_OE -DEFINE REGISTER_WBM_OUTPUTS -DEFINE REGISTER_WBS_OUTPUTS -DEFINE ADDR_TRAN_IMPL -DEFINE PCI_IMAGE0 -DEFINE PCI_IMAGE2" > ./defines.args
- endif
- if ($iter == 2) then
- echo "<<< Defines:"
- echo "\tHOST, REGR_FIFO_MEDIUM_ARTISAN, WB_DECODE_MEDIUM, PCI_DECODE_MED, "
- echo "\tWB_DECODE_MED, PCI33, WB_CLK66, ACTIVE_LOW_OE, REGISTER_WBM_OUTPUTS, "
- echo "\tREGISTER_WBS_OUTPUTS, ADDR_TRAN_IMPL, PCI_IMAGE0, PCI_IMAGE2, "
- echo "\tPCI_IMAGE3, PCI_IMAGE4, PCI_IMAGE5, WB_IMAGE2, WB_IMAGE5. "
- echo "-DEFINE REGRESSION -DEFINE HOST -DEFINE REGR_FIFO_MEDIUM_ARTISAN -DEFINE WB_DECODE_MEDIUM -DEFINE PCI_DECODE_MED -DEFINE WB_DECODE_MED -DEFINE PCI33 -DEFINE WB_CLK66 -DEFINE ACTIVE_LOW_OE -DEFINE REGISTER_WBM_OUTPUTS -DEFINE REGISTER_WBS_OUTPUTS -DEFINE ADDR_TRAN_IMPL -DEFINE PCI_IMAGE0 -DEFINE PCI_IMAGE2 -DEFINE PCI_IMAGE3 -DEFINE PCI_IMAGE4 -DEFINE PCI_IMAGE5 -DEFINE WB_IMAGE2 -DEFINE WB_IMAGE5" > ./defines.args
- endif
- if ($iter == 3) then
- echo "<<< Defines:"
- echo "\tHOST, REGR_FIFO_LARGE_GENERIC, WB_DECODE_SLOW, PCI_DECODE_MIN, "
- echo "\tWB_DECODE_MAX, PCI66, WB_CLK66, ACTIVE_LOW_OE, REGISTER_WBM_OUTPUTS, "
- echo "\tREGISTER_WBS_OUTPUTS, WB_IMAGE5. "
- echo "-DEFINE REGRESSION -DEFINE HOST -DEFINE REGR_FIFO_LARGE_GENERIC -DEFINE WB_DECODE_SLOW -DEFINE PCI_DECODE_MIN -DEFINE WB_DECODE_MAX -DEFINE PCI66 -DEFINE WB_CLK66 -DEFINE ACTIVE_LOW_OE -DEFINE REGISTER_WBM_OUTPUTS -DEFINE REGISTER_WBS_OUTPUTS -DEFINE WB_IMAGE5" > ./defines.args
- endif
- if ($iter == 4) then
- echo "<<< Defines:"
- echo "\tGUEST, REGR_FIFO_SMALL_XILINX, WB_DECODE_SLOW, PCI_DECODE_MED, "
- echo "\tWB_DECODE_MIN, PCI66, WB_CLK220, ACTIVE_LOW_OE, REGISTER_WBM_OUTPUTS, "
- echo "\tREGISTER_WBS_OUTPUTS, PCI_IMAGE0, PCI_IMAGE5, WB_IMAGE4. "
- echo "-DEFINE REGRESSION -DEFINE GUEST -DEFINE REGR_FIFO_SMALL_XILINX -DEFINE WB_DECODE_SLOW -DEFINE PCI_DECODE_MED -DEFINE WB_DECODE_MIN -DEFINE PCI66 -DEFINE WB_CLK220 -DEFINE ACTIVE_LOW_OE -DEFINE REGISTER_WBM_OUTPUTS -DEFINE REGISTER_WBS_OUTPUTS -DEFINE PCI_IMAGE0 -DEFINE PCI_IMAGE5 -DEFINE WB_IMAGE4" > ./defines.args
- endif
- if ($iter == 5) then
- echo "<<< Defines:"
- echo "\tGUEST, REGR_FIFO_MEDIUM_ARTISAN, WB_DECODE_FAST, PCI_DECODE_MIN, "
- echo "\tWB_DECODE_MAX, PCI33, WB_CLK220, ACTIVE_LOW_OE, REGISTER_WBM_OUTPUTS, "
- echo "\tREGISTER_WBS_OUTPUTS, ADDR_TRAN_IMPL, PCI_IMAGE0, PCI_IMAGE2, "
- echo "\tWB_IMAGE2, WB_IMAGE3, WB_IMAGE4. "
- echo "-DEFINE REGRESSION -DEFINE GUEST -DEFINE REGR_FIFO_MEDIUM_ARTISAN -DEFINE WB_DECODE_FAST -DEFINE PCI_DECODE_MIN -DEFINE WB_DECODE_MAX -DEFINE PCI33 -DEFINE WB_CLK220 -DEFINE ACTIVE_LOW_OE -DEFINE REGISTER_WBM_OUTPUTS -DEFINE REGISTER_WBS_OUTPUTS -DEFINE ADDR_TRAN_IMPL -DEFINE PCI_IMAGE0 -DEFINE PCI_IMAGE2 -DEFINE WB_IMAGE2 -DEFINE WB_IMAGE3 -DEFINE WB_IMAGE4" > ./defines.args
- endif
- if ($iter == 6) then
- echo "<<< Defines:"
- echo "\tGUEST, REGR_FIFO_LARGE_GENERIC, WB_DECODE_MEDIUM, PCI_DECODE_MAX, "
- echo "\tWB_DECODE_MED, PCI66, WB_CLK10, ACTIVE_LOW_OE, REGISTER_WBM_OUTPUTS, "
- echo "\tREGISTER_WBS_OUTPUTS, ADDR_TRAN_IMPL. "
- echo "-DEFINE REGRESSION -DEFINE GUEST -DEFINE REGR_FIFO_LARGE_GENERIC -DEFINE WB_DECODE_MEDIUM -DEFINE PCI_DECODE_MAX -DEFINE WB_DECODE_MED -DEFINE PCI66 -DEFINE WB_CLK10 -DEFINE ACTIVE_LOW_OE -DEFINE REGISTER_WBM_OUTPUTS -DEFINE REGISTER_WBS_OUTPUTS -DEFINE ADDR_TRAN_IMPL" > ./defines.args
- endif
- if ($iter == 7) then
- echo "<<< Defines:"
- echo "\tHOST, REGR_FIFO_SMALL_XILINX, WB_DECODE_FAST, PCI_DECODE_MAX, "
- echo "\tWB_DECODE_MIN, PCI66, WB_CLK220, ACTIVE_HIGH_OE, WB_CNF_BASE_ZERO, "
- echo "\tNO_CNF_IMAGE, PCI_IMAGE0, PCI_IMAGE4. "
- echo "-DEFINE REGRESSION -DEFINE HOST -DEFINE REGR_FIFO_SMALL_XILINX -DEFINE WB_DECODE_FAST -DEFINE PCI_DECODE_MAX -DEFINE WB_DECODE_MIN -DEFINE PCI66 -DEFINE WB_CLK220 -DEFINE ACTIVE_HIGH_OE -DEFINE WB_CNF_BASE_ZERO -DEFINE NO_CNF_IMAGE -DEFINE PCI_IMAGE0 -DEFINE PCI_IMAGE4" > ./defines.args
- endif
- if ($iter == 8) then
- echo "<<< Defines:"
- echo "\tHOST, REGR_FIFO_MEDIUM_ARTISAN, WB_DECODE_MEDIUM, PCI_DECODE_MED, "
- echo "\tWB_DECODE_MED, PCI66, WB_CLK10, ACTIVE_HIGH_OE, WB_CNF_BASE_ZERO, "
- echo "\tNO_CNF_IMAGE, PCI_IMAGE0, PCI_IMAGE2, PCI_IMAGE3, PCI_IMAGE4, "
- echo "\tPCI_IMAGE5, WB_IMAGE2, WB_IMAGE3, WB_IMAGE4, WB_IMAGE5. "
- echo "-DEFINE REGRESSION -DEFINE HOST -DEFINE REGR_FIFO_MEDIUM_ARTISAN -DEFINE WB_DECODE_MEDIUM -DEFINE PCI_DECODE_MED -DEFINE WB_DECODE_MED -DEFINE PCI66 -DEFINE WB_CLK10 -DEFINE ACTIVE_HIGH_OE -DEFINE WB_CNF_BASE_ZERO -DEFINE NO_CNF_IMAGE -DEFINE PCI_IMAGE0 -DEFINE PCI_IMAGE2 -DEFINE PCI_IMAGE3 -DEFINE PCI_IMAGE4 -DEFINE PCI_IMAGE5 -DEFINE WB_IMAGE2 -DEFINE WB_IMAGE3 -DEFINE WB_IMAGE4 -DEFINE WB_IMAGE5" > ./defines.args
- endif
- if ($iter == 9) then
- echo "<<< Defines:"
- echo "\tHOST, REGR_FIFO_LARGE_GENERIC, WB_DECODE_SLOW, PCI_DECODE_MIN, "
- echo "\tWB_DECODE_MAX, PCI33, WB_CLK220, ACTIVE_HIGH_OE, ADDR_TRAN_IMPL, "
- echo "\tWB_CNF_BASE_ZERO, NO_CNF_IMAGE, WB_IMAGE3. "
- echo "-DEFINE REGRESSION -DEFINE HOST -DEFINE REGR_FIFO_LARGE_GENERIC -DEFINE WB_DECODE_SLOW -DEFINE PCI_DECODE_MIN -DEFINE WB_DECODE_MAX -DEFINE PCI33 -DEFINE WB_CLK220 -DEFINE ACTIVE_HIGH_OE -DEFINE ADDR_TRAN_IMPL -DEFINE WB_CNF_BASE_ZERO -DEFINE NO_CNF_IMAGE -DEFINE WB_IMAGE3" > ./defines.args
- endif
- if ($iter == 10) then
- echo "<<< Defines:"
- echo "\tGUEST, REGR_FIFO_SMALL_XILINX, WB_DECODE_SLOW, PCI_DECODE_MED, "
- echo "\tWB_DECODE_MIN, PCI33, WB_CLK66, ACTIVE_HIGH_OE, ADDR_TRAN_IMPL, "
- echo "\tWB_CNF_BASE_ZERO, NO_CNF_IMAGE, PCI_IMAGE0, PCI_IMAGE3. "
- echo "-DEFINE REGRESSION -DEFINE GUEST -DEFINE REGR_FIFO_SMALL_XILINX -DEFINE WB_DECODE_SLOW -DEFINE PCI_DECODE_MED -DEFINE WB_DECODE_MIN -DEFINE PCI33 -DEFINE WB_CLK66 -DEFINE ACTIVE_HIGH_OE -DEFINE ADDR_TRAN_IMPL -DEFINE WB_CNF_BASE_ZERO -DEFINE NO_CNF_IMAGE -DEFINE PCI_IMAGE0 -DEFINE PCI_IMAGE3" > ./defines.args
- endif
- if ($iter == 11) then
- echo "<<< Defines:"
- echo "\tGUEST, REGR_FIFO_MEDIUM_ARTISAN, WB_DECODE_FAST, PCI_DECODE_MIN, "
- echo "\tWB_DECODE_MAX, PCI66, WB_CLK66, ACTIVE_HIGH_OE, WB_CNF_BASE_ZERO, "
- echo "\tNO_CNF_IMAGE, PCI_IMAGE0, PCI_IMAGE2, PCI_IMAGE3, PCI_IMAGE4, "
- echo "\tPCI_IMAGE5, WB_IMAGE2. "
- echo "-DEFINE REGRESSION -DEFINE GUEST -DEFINE REGR_FIFO_MEDIUM_ARTISAN -DEFINE WB_DECODE_FAST -DEFINE PCI_DECODE_MIN -DEFINE WB_DECODE_MAX -DEFINE PCI66 -DEFINE WB_CLK66 -DEFINE ACTIVE_HIGH_OE -DEFINE WB_CNF_BASE_ZERO -DEFINE NO_CNF_IMAGE -DEFINE PCI_IMAGE0 -DEFINE PCI_IMAGE2 -DEFINE PCI_IMAGE3 -DEFINE PCI_IMAGE4 -DEFINE PCI_IMAGE5 -DEFINE WB_IMAGE2" > ./defines.args
- endif
- if ($iter == 12) then
- echo "<<< Defines:"
- echo "\tGUEST, REGR_FIFO_LARGE_GENERIC, WB_DECODE_MEDIUM, PCI_DECODE_MAX, "
- echo "\tWB_DECODE_MED, PCI33, WB_CLK10, ACTIVE_HIGH_OE, WB_CNF_BASE_ZERO, "
- echo "\tNO_CNF_IMAGE, WB_IMAGE2, WB_IMAGE3, WB_IMAGE4, WB_IMAGE5. "
- echo "-DEFINE REGRESSION -DEFINE GUEST -DEFINE REGR_FIFO_LARGE_GENERIC -DEFINE WB_DECODE_MEDIUM -DEFINE PCI_DECODE_MAX -DEFINE WB_DECODE_MED -DEFINE PCI33 -DEFINE WB_CLK10 -DEFINE ACTIVE_HIGH_OE -DEFINE WB_CNF_BASE_ZERO -DEFINE NO_CNF_IMAGE -DEFINE WB_IMAGE2 -DEFINE WB_IMAGE3 -DEFINE WB_IMAGE4 -DEFINE WB_IMAGE5" > ./defines.args
- endif
+ endif
- if ($arg_dis_comp_exp_test) then
- echo "-DEFINE DISABLE_COMPLETION_EXPIRED_TESTS" >> ./defines.args
- endif
- else
- if ($iter == 1) then
- echo "<<< Defines:"
- echo "\tHOST, REGR_FIFO_SMALL_XILINX, WB_DECODE_FAST, PCI_DECODE_MAX, "
- echo "\tWB_DECODE_MIN, PCI33, WB_CLK10, ACTIVE_LOW_OE, REGISTER_WBM_OUTPUTS, "
- echo "\tREGISTER_WBS_OUTPUTS, ADDR_TRAN_IMPL, PCI_IMAGE0, PCI_IMAGE2. "
- echo "-DEFINE REGRESSION -DEFINE HOST -DEFINE REGR_FIFO_SMALL_XILINX -DEFINE WB_DECODE_FAST -DEFINE PCI_DECODE_MAX -DEFINE WB_DECODE_MIN -DEFINE PCI33 -DEFINE WB_CLK10 -DEFINE ACTIVE_LOW_OE -DEFINE REGISTER_WBM_OUTPUTS -DEFINE REGISTER_WBS_OUTPUTS -DEFINE ADDR_TRAN_IMPL -DEFINE PCI_IMAGE0 -DEFINE PCI_IMAGE2" > ./defines.args
- endif
- if ($iter == 2) then
- echo "<<< Defines:"
- echo "\tHOST, REGR_FIFO_MEDIUM_GENERIC, WB_DECODE_MEDIUM, PCI_DECODE_MED, "
- echo "\tWB_DECODE_MED, PCI33, WB_CLK66, ACTIVE_LOW_OE, REGISTER_WBM_OUTPUTS, "
- echo "\tREGISTER_WBS_OUTPUTS, ADDR_TRAN_IMPL, PCI_IMAGE0, PCI_IMAGE2, "
- echo "\tPCI_IMAGE3, PCI_IMAGE4, PCI_IMAGE5, WB_IMAGE2, WB_IMAGE5. "
- echo "-DEFINE REGRESSION -DEFINE HOST -DEFINE REGR_FIFO_MEDIUM_GENERIC -DEFINE WB_DECODE_MEDIUM -DEFINE PCI_DECODE_MED -DEFINE WB_DECODE_MED -DEFINE PCI33 -DEFINE WB_CLK66 -DEFINE ACTIVE_LOW_OE -DEFINE REGISTER_WBM_OUTPUTS -DEFINE REGISTER_WBS_OUTPUTS -DEFINE ADDR_TRAN_IMPL -DEFINE PCI_IMAGE0 -DEFINE PCI_IMAGE2 -DEFINE PCI_IMAGE3 -DEFINE PCI_IMAGE4 -DEFINE PCI_IMAGE5 -DEFINE WB_IMAGE2 -DEFINE WB_IMAGE5" > ./defines.args
- endif
- if ($iter == 3) then
- echo "<<< Defines:"
- echo "\tHOST, REGR_FIFO_LARGE_GENERIC, WB_DECODE_SLOW, PCI_DECODE_MIN, "
- echo "\tWB_DECODE_MAX, PCI66, WB_CLK66, ACTIVE_LOW_OE, REGISTER_WBM_OUTPUTS, "
- echo "\tREGISTER_WBS_OUTPUTS, WB_IMAGE5. "
- echo "-DEFINE REGRESSION -DEFINE HOST -DEFINE REGR_FIFO_LARGE_GENERIC -DEFINE WB_DECODE_SLOW -DEFINE PCI_DECODE_MIN -DEFINE WB_DECODE_MAX -DEFINE PCI66 -DEFINE WB_CLK66 -DEFINE ACTIVE_LOW_OE -DEFINE REGISTER_WBM_OUTPUTS -DEFINE REGISTER_WBS_OUTPUTS -DEFINE WB_IMAGE5" > ./defines.args
- endif
- if ($iter == 4) then
- echo "<<< Defines:"
- echo "\tGUEST, REGR_FIFO_SMALL_XILINX, WB_DECODE_SLOW, PCI_DECODE_MED, "
- echo "\tWB_DECODE_MIN, PCI66, WB_CLK220, ACTIVE_LOW_OE, REGISTER_WBM_OUTPUTS, "
- echo "\tREGISTER_WBS_OUTPUTS, PCI_IMAGE0, PCI_IMAGE5, WB_IMAGE4. "
- echo "-DEFINE REGRESSION -DEFINE GUEST -DEFINE REGR_FIFO_SMALL_XILINX -DEFINE WB_DECODE_SLOW -DEFINE PCI_DECODE_MED -DEFINE WB_DECODE_MIN -DEFINE PCI66 -DEFINE WB_CLK220 -DEFINE ACTIVE_LOW_OE -DEFINE REGISTER_WBM_OUTPUTS -DEFINE REGISTER_WBS_OUTPUTS -DEFINE PCI_IMAGE0 -DEFINE PCI_IMAGE5 -DEFINE WB_IMAGE4" > ./defines.args
- endif
- if ($iter == 5) then
- echo "<<< Defines:"
- echo "\tGUEST, REGR_FIFO_MEDIUM_GENERIC, WB_DECODE_FAST, PCI_DECODE_MIN, "
- echo "\tWB_DECODE_MAX, PCI33, WB_CLK220, ACTIVE_LOW_OE, REGISTER_WBM_OUTPUTS, "
- echo "\tREGISTER_WBS_OUTPUTS, ADDR_TRAN_IMPL, PCI_IMAGE0, PCI_IMAGE2, "
- echo "\tWB_IMAGE2, WB_IMAGE3, WB_IMAGE4. "
- echo "-DEFINE REGRESSION -DEFINE GUEST -DEFINE REGR_FIFO_MEDIUM_GENERIC -DEFINE WB_DECODE_FAST -DEFINE PCI_DECODE_MIN -DEFINE WB_DECODE_MAX -DEFINE PCI33 -DEFINE WB_CLK220 -DEFINE ACTIVE_LOW_OE -DEFINE REGISTER_WBM_OUTPUTS -DEFINE REGISTER_WBS_OUTPUTS -DEFINE ADDR_TRAN_IMPL -DEFINE PCI_IMAGE0 -DEFINE PCI_IMAGE2 -DEFINE WB_IMAGE2 -DEFINE WB_IMAGE3 -DEFINE WB_IMAGE4" > ./defines.args
- endif
- if ($iter == 6) then
- echo "<<< Defines:"
- echo "\tGUEST, REGR_FIFO_LARGE_GENERIC, WB_DECODE_MEDIUM, PCI_DECODE_MAX, "
- echo "\tWB_DECODE_MED, PCI66, WB_CLK10, ACTIVE_LOW_OE, REGISTER_WBM_OUTPUTS, "
- echo "\tREGISTER_WBS_OUTPUTS, ADDR_TRAN_IMPL. "
- echo "-DEFINE REGRESSION -DEFINE GUEST -DEFINE REGR_FIFO_LARGE_GENERIC -DEFINE WB_DECODE_MEDIUM -DEFINE PCI_DECODE_MAX -DEFINE WB_DECODE_MED -DEFINE PCI66 -DEFINE WB_CLK10 -DEFINE ACTIVE_LOW_OE -DEFINE REGISTER_WBM_OUTPUTS -DEFINE REGISTER_WBS_OUTPUTS -DEFINE ADDR_TRAN_IMPL" > ./defines.args
- endif
- if ($iter == 7) then
- echo "<<< Defines:"
- echo "\tHOST, REGR_FIFO_SMALL_XILINX, WB_DECODE_FAST, PCI_DECODE_MAX, "
- echo "\tWB_DECODE_MIN, PCI66, WB_CLK220, ACTIVE_HIGH_OE, WB_CNF_BASE_ZERO, "
- echo "\tNO_CNF_IMAGE, PCI_IMAGE0, PCI_IMAGE4. "
- echo "-DEFINE REGRESSION -DEFINE HOST -DEFINE REGR_FIFO_SMALL_XILINX -DEFINE WB_DECODE_FAST -DEFINE PCI_DECODE_MAX -DEFINE WB_DECODE_MIN -DEFINE PCI66 -DEFINE WB_CLK220 -DEFINE ACTIVE_HIGH_OE -DEFINE WB_CNF_BASE_ZERO -DEFINE NO_CNF_IMAGE -DEFINE PCI_IMAGE0 -DEFINE PCI_IMAGE4" > ./defines.args
- endif
- if ($iter == 8) then
- echo "<<< Defines:"
- echo "\tHOST, REGR_FIFO_MEDIUM_GENERIC, WB_DECODE_MEDIUM, PCI_DECODE_MED, "
- echo "\tWB_DECODE_MED, PCI66, WB_CLK10, ACTIVE_HIGH_OE, WB_CNF_BASE_ZERO, "
- echo "\tNO_CNF_IMAGE, PCI_IMAGE0, PCI_IMAGE2, PCI_IMAGE3, PCI_IMAGE4, "
- echo "\tPCI_IMAGE5, WB_IMAGE2, WB_IMAGE3, WB_IMAGE4, WB_IMAGE5. "
- echo "-DEFINE REGRESSION -DEFINE HOST -DEFINE REGR_FIFO_MEDIUM_GENERIC -DEFINE WB_DECODE_MEDIUM -DEFINE PCI_DECODE_MED -DEFINE WB_DECODE_MED -DEFINE PCI66 -DEFINE WB_CLK10 -DEFINE ACTIVE_HIGH_OE -DEFINE WB_CNF_BASE_ZERO -DEFINE NO_CNF_IMAGE -DEFINE PCI_IMAGE0 -DEFINE PCI_IMAGE2 -DEFINE PCI_IMAGE3 -DEFINE PCI_IMAGE4 -DEFINE PCI_IMAGE5 -DEFINE WB_IMAGE2 -DEFINE WB_IMAGE3 -DEFINE WB_IMAGE4 -DEFINE WB_IMAGE5" > ./defines.args
- endif
- if ($iter == 9) then
- echo "<<< Defines:"
- echo "\tHOST, REGR_FIFO_LARGE_GENERIC, WB_DECODE_SLOW, PCI_DECODE_MIN, "
- echo "\tWB_DECODE_MAX, PCI33, WB_CLK220, ACTIVE_HIGH_OE, ADDR_TRAN_IMPL, "
- echo "\tWB_CNF_BASE_ZERO, NO_CNF_IMAGE, WB_IMAGE3. "
- echo "-DEFINE REGRESSION -DEFINE HOST -DEFINE REGR_FIFO_LARGE_GENERIC -DEFINE WB_DECODE_SLOW -DEFINE PCI_DECODE_MIN -DEFINE WB_DECODE_MAX -DEFINE PCI33 -DEFINE WB_CLK220 -DEFINE ACTIVE_HIGH_OE -DEFINE ADDR_TRAN_IMPL -DEFINE WB_CNF_BASE_ZERO -DEFINE NO_CNF_IMAGE -DEFINE WB_IMAGE3" > ./defines.args
- endif
- if ($iter == 10) then
- echo "<<< Defines:"
- echo "\tGUEST, REGR_FIFO_SMALL_XILINX, WB_DECODE_SLOW, PCI_DECODE_MED, "
- echo "\tWB_DECODE_MIN, PCI33, WB_CLK66, ACTIVE_HIGH_OE, ADDR_TRAN_IMPL, "
- echo "\tWB_CNF_BASE_ZERO, NO_CNF_IMAGE, PCI_IMAGE0, PCI_IMAGE3. "
- echo "-DEFINE REGRESSION -DEFINE GUEST -DEFINE REGR_FIFO_SMALL_XILINX -DEFINE WB_DECODE_SLOW -DEFINE PCI_DECODE_MED -DEFINE WB_DECODE_MIN -DEFINE PCI33 -DEFINE WB_CLK66 -DEFINE ACTIVE_HIGH_OE -DEFINE ADDR_TRAN_IMPL -DEFINE WB_CNF_BASE_ZERO -DEFINE NO_CNF_IMAGE -DEFINE PCI_IMAGE0 -DEFINE PCI_IMAGE3" > ./defines.args
- endif
- if ($iter == 11) then
- echo "<<< Defines:"
- echo "\tGUEST, REGR_FIFO_MEDIUM_GENERIC, WB_DECODE_FAST, PCI_DECODE_MIN, "
- echo "\tWB_DECODE_MAX, PCI66, WB_CLK66, ACTIVE_HIGH_OE, WB_CNF_BASE_ZERO, "
- echo "\tNO_CNF_IMAGE, PCI_IMAGE0, PCI_IMAGE2, PCI_IMAGE3, PCI_IMAGE4, "
- echo "\tPCI_IMAGE5, WB_IMAGE2. "
- echo "-DEFINE REGRESSION -DEFINE GUEST -DEFINE REGR_FIFO_MEDIUM_GENERIC -DEFINE WB_DECODE_FAST -DEFINE PCI_DECODE_MIN -DEFINE WB_DECODE_MAX -DEFINE PCI66 -DEFINE WB_CLK66 -DEFINE ACTIVE_HIGH_OE -DEFINE WB_CNF_BASE_ZERO -DEFINE NO_CNF_IMAGE -DEFINE PCI_IMAGE0 -DEFINE PCI_IMAGE2 -DEFINE PCI_IMAGE3 -DEFINE PCI_IMAGE4 -DEFINE PCI_IMAGE5 -DEFINE WB_IMAGE2" > ./defines.args
- endif
- if ($iter == 12) then
- echo "<<< Defines:"
- echo "\tGUEST, REGR_FIFO_LARGE_GENERIC, WB_DECODE_MEDIUM, PCI_DECODE_MAX, "
- echo "\tWB_DECODE_MED, PCI33, WB_CLK10, ACTIVE_HIGH_OE, WB_CNF_BASE_ZERO, "
- echo "\tNO_CNF_IMAGE, WB_IMAGE2, WB_IMAGE3, WB_IMAGE4, WB_IMAGE5. "
- echo "-DEFINE REGRESSION -DEFINE GUEST -DEFINE REGR_FIFO_LARGE_GENERIC -DEFINE WB_DECODE_MEDIUM -DEFINE PCI_DECODE_MAX -DEFINE WB_DECODE_MED -DEFINE PCI33 -DEFINE WB_CLK10 -DEFINE ACTIVE_HIGH_OE -DEFINE WB_CNF_BASE_ZERO -DEFINE NO_CNF_IMAGE -DEFINE WB_IMAGE2 -DEFINE WB_IMAGE3 -DEFINE WB_IMAGE4 -DEFINE WB_IMAGE5" > ./defines.args
- endif
+ if ($iter == 3) then
+ echo "<<< Defines:"
+ echo "\tHOST, REGR_FIFO_LARGE_GENERIC, WB_DECODE_SLOW, PCI_DECODE_MIN, "
+ echo "\tWB_DECODE_MAX, PCI66, WB_CLK66, ACTIVE_LOW_OE, REGISTER_WBM_OUTPUTS, "
+ echo "\tREGISTER_WBS_OUTPUTS, WB_IMAGE5. "
+
+ echo "-DEFINE REGRESSION " > ./defines.args
- if ($arg_dis_comp_exp_test) then
+ echo "-DEFINE HOST " >> ./defines.args
+ echo "-DEFINE REGR_FIFO_LARGE_GENERIC" >> ./defines.args
+ echo "-DEFINE WB_DECODE_SLOW " >> ./defines.args
+ echo "-DEFINE PCI_DECODE_MIN " >> ./defines.args
+ echo "-DEFINE WB_DECODE_MAX " >> ./defines.args
+ echo "-DEFINE PCI66 " >> ./defines.args
+ echo "-DEFINE WB_CLK66 " >> ./defines.args
+ echo "-DEFINE ACTIVE_LOW_OE " >> ./defines.args
+ echo "-DEFINE REGISTER_WBM_OUTPUTS " >> ./defines.args
+ echo "-DEFINE REGISTER_WBS_OUTPUTS " >> ./defines.args
+ echo "-DEFINE WB_IMAGE5 " >> ./defines.args
+
+ endif
+
+ if ($iter == 4) then
+ echo "<<< Defines:"
+ echo "\tGUEST, REGR_FIFO_SMALL_GENERIC, WB_DECODE_SLOW, PCI_DECODE_MED, "
+ echo "\tWB_DECODE_MIN, PCI66, WB_CLK220, ACTIVE_LOW_OE, REGISTER_WBM_OUTPUTS, "
+ echo "\tREGISTER_WBS_OUTPUTS, PCI_IMAGE0, PCI_IMAGE5, WB_IMAGE4. "
+
+ echo "-DEFINE REGRESSION" > ./defines.args
+
+ echo "-DEFINE GUEST " >> ./defines.args
+ echo "-DEFINE REGR_FIFO_SMALL_GENERIC" >> ./defines.args
+ echo "-DEFINE WB_DECODE_SLOW " >> ./defines.args
+ echo "-DEFINE PCI_DECODE_MED " >> ./defines.args
+ echo "-DEFINE WB_DECODE_MIN " >> ./defines.args
+ echo "-DEFINE PCI66 " >> ./defines.args
+ echo "-DEFINE WB_CLK220 " >> ./defines.args
+ echo "-DEFINE ACTIVE_LOW_OE " >> ./defines.args
+ echo "-DEFINE REGISTER_WBM_OUTPUTS " >> ./defines.args
+ echo "-DEFINE REGISTER_WBS_OUTPUTS " >> ./defines.args
+ echo "-DEFINE PCI_IMAGE0 " >> ./defines.args
+ echo "-DEFINE PCI_IMAGE5 " >> ./defines.args
+ echo "-DEFINE WB_IMAGE4 " >> ./defines.args
+ endif
+
+ if ($iter == 5) then
+ echo "<<< Defines:"
+
+ if ($arg_artisan == 1) then
+ echo "\tREGR_FIFO_MEDIUM_ARTISAN, "
+ else
+ echo "\tREGR_FIFO_MEDIUM_GENERIC, "
+ endif
+
+ echo "\tGUEST, WB_DECODE_FAST, PCI_DECODE_MIN, "
+ echo "\tWB_DECODE_MAX, PCI33, WB_CLK220, ACTIVE_LOW_OE, REGISTER_WBM_OUTPUTS, "
+ echo "\tREGISTER_WBS_OUTPUTS, ADDR_TRAN_IMPL, PCI_IMAGE0, PCI_IMAGE2, "
+ echo "\tWB_IMAGE2, WB_IMAGE3, WB_IMAGE4. "
+
+ echo "-DEFINE REGRESSION" > ./defines.args
+
+ if ($arg_artisan == 1) then
+ echo "-DEFINE REGR_FIFO_MEDIUM_ARTISAN" >> ./defines.args
+ else
+ echo "-DEFINE REGR_FIFO_MEDIUM_GENERIC" >> ./defines.args
+ endif
+
+ echo "-DEFINE GUEST " >> ./defines.args
+ echo "-DEFINE WB_DECODE_FAST " >> ./defines.args
+ echo "-DEFINE PCI_DECODE_MIN " >> ./defines.args
+ echo "-DEFINE WB_DECODE_MAX " >> ./defines.args
+ echo "-DEFINE PCI33 " >> ./defines.args
+ echo "-DEFINE WB_CLK220 " >> ./defines.args
+ echo "-DEFINE ACTIVE_LOW_OE " >> ./defines.args
+ echo "-DEFINE REGISTER_WBM_OUTPUTS " >> ./defines.args
+ echo "-DEFINE REGISTER_WBS_OUTPUTS " >> ./defines.args
+ echo "-DEFINE ADDR_TRAN_IMPL " >> ./defines.args
+ echo "-DEFINE PCI_IMAGE0 " >> ./defines.args
+ echo "-DEFINE PCI_IMAGE2 " >> ./defines.args
+ echo "-DEFINE WB_IMAGE2 " >> ./defines.args
+ echo "-DEFINE WB_IMAGE3 " >> ./defines.args
+ echo "-DEFINE WB_IMAGE4 " >> ./defines.args
+ endif
+
+ if ($iter == 6) then
+ echo "<<< Defines:"
+ echo "\tGUEST, REGR_FIFO_LARGE_GENERIC, WB_DECODE_MEDIUM, PCI_DECODE_MAX, "
+ echo "\tWB_DECODE_MED, PCI66, WB_CLK10, ACTIVE_LOW_OE, REGISTER_WBM_OUTPUTS, "
+ echo "\tREGISTER_WBS_OUTPUTS, ADDR_TRAN_IMPL. "
+
+ echo "-DEFINE REGRESSION" > ./defines.args
+
+ echo "-DEFINE GUEST " >> ./defines.args
+ echo "-DEFINE REGR_FIFO_LARGE_GENERIC" >> ./defines.args
+ echo "-DEFINE WB_DECODE_MEDIUM " >> ./defines.args
+ echo "-DEFINE PCI_DECODE_MAX " >> ./defines.args
+ echo "-DEFINE WB_DECODE_MED " >> ./defines.args
+ echo "-DEFINE PCI66 " >> ./defines.args
+ echo "-DEFINE WB_CLK10 " >> ./defines.args
+ echo "-DEFINE ACTIVE_LOW_OE " >> ./defines.args
+ echo "-DEFINE REGISTER_WBM_OUTPUTS " >> ./defines.args
+ echo "-DEFINE REGISTER_WBS_OUTPUTS " >> ./defines.args
+ echo "-DEFINE ADDR_TRAN_IMPL " >> ./defines.args
+ endif
+
+ if ($iter == 7) then
+ echo "<<< Defines:"
+
+ if ($arg_xilinx == 0) then
+ echo "\tREGR_FIFO_SMALL_GENERIC, "
+ else
+ echo "\tREGR_FIFO_SMALL_XILINX, "
+ endif
+
+ echo "\tHOST, WB_DECODE_FAST, PCI_DECODE_MAX, "
+ echo "\tWB_DECODE_MIN, PCI66, WB_CLK220, ACTIVE_HIGH_OE, WB_CNF_BASE_ZERO, "
+ echo "\tNO_CNF_IMAGE, PCI_IMAGE0, PCI_IMAGE4. "
+
+ echo "-DEFINE REGRESSION" > ./defines.args
+
+ if ($arg_xilinx == 0) then
+ echo "-DEFINE REGR_FIFO_SMALL_GENERIC" >> ./defines.args
+ else
+ echo "-DEFINE REGR_FIFO_SMALL_XILINX" >> ./defines.args
+ endif
+
+ echo "-DEFINE HOST " >> ./defines.args
+ echo "-DEFINE WB_DECODE_FAST " >> ./defines.args
+ echo "-DEFINE PCI_DECODE_MAX " >> ./defines.args
+ echo "-DEFINE WB_DECODE_MIN " >> ./defines.args
+ echo "-DEFINE PCI66 " >> ./defines.args
+ echo "-DEFINE WB_CLK220 " >> ./defines.args
+ echo "-DEFINE ACTIVE_HIGH_OE " >> ./defines.args
+ echo "-DEFINE WB_CNF_BASE_ZERO" >> ./defines.args
+ echo "-DEFINE NO_CNF_IMAGE " >> ./defines.args
+ echo "-DEFINE PCI_IMAGE0 " >> ./defines.args
+ echo "-DEFINE PCI_IMAGE4 " >> ./defines.args
+ endif
+
+ if ($iter == 8) then
+ echo "<<< Defines:"
+ echo "\tHOST, REGR_FIFO_MEDIUM_GENERIC, WB_DECODE_MEDIUM, PCI_DECODE_MED, "
+ echo "\tWB_DECODE_MED, PCI66, WB_CLK10, ACTIVE_HIGH_OE, WB_CNF_BASE_ZERO, "
+ echo "\tNO_CNF_IMAGE, PCI_IMAGE0, PCI_IMAGE2, PCI_IMAGE3, PCI_IMAGE4, "
+ echo "\tPCI_IMAGE5, WB_IMAGE2, WB_IMAGE3, WB_IMAGE4, WB_IMAGE5. "
+
+ echo "-DEFINE REGRESSION" > ./defines.args
+
+ echo "-DEFINE HOST " >> ./defines.args
+ echo "-DEFINE REGR_FIFO_MEDIUM_GENERIC" >> ./defines.args
+ echo "-DEFINE WB_DECODE_MEDIUM " >> ./defines.args
+ echo "-DEFINE PCI_DECODE_MED " >> ./defines.args
+ echo "-DEFINE WB_DECODE_MED " >> ./defines.args
+ echo "-DEFINE PCI66 " >> ./defines.args
+ echo "-DEFINE WB_CLK10 " >> ./defines.args
+ echo "-DEFINE ACTIVE_HIGH_OE " >> ./defines.args
+ echo "-DEFINE WB_CNF_BASE_ZERO " >> ./defines.args
+ echo "-DEFINE NO_CNF_IMAGE " >> ./defines.args
+ echo "-DEFINE PCI_IMAGE0 " >> ./defines.args
+ echo "-DEFINE PCI_IMAGE2 " >> ./defines.args
+ echo "-DEFINE PCI_IMAGE3 " >> ./defines.args
+ echo "-DEFINE PCI_IMAGE4 " >> ./defines.args
+ echo "-DEFINE PCI_IMAGE5 " >> ./defines.args
+ echo "-DEFINE WB_IMAGE2 " >> ./defines.args
+ echo "-DEFINE WB_IMAGE3 " >> ./defines.args
+ echo "-DEFINE WB_IMAGE4 " >> ./defines.args
+ echo "-DEFINE WB_IMAGE5 " >> ./defines.args
+ endif
+
+ if ($iter == 9) then
+ echo "<<< Defines:"
+ echo "\tHOST, REGR_FIFO_LARGE_GENERIC, WB_DECODE_SLOW, PCI_DECODE_MIN, "
+ echo "\tWB_DECODE_MAX, PCI33, WB_CLK220, ACTIVE_HIGH_OE, ADDR_TRAN_IMPL, "
+ echo "\tWB_CNF_BASE_ZERO, NO_CNF_IMAGE, WB_IMAGE3. "
+
+ echo "-DEFINE REGRESSION" > ./defines.args
+
+ echo "-DEFINE HOST " >> ./defines.args
+ echo "-DEFINE REGR_FIFO_LARGE_GENERIC" >> ./defines.args
+ echo "-DEFINE WB_DECODE_SLOW " >> ./defines.args
+ echo "-DEFINE PCI_DECODE_MIN " >> ./defines.args
+ echo "-DEFINE WB_DECODE_MAX " >> ./defines.args
+ echo "-DEFINE PCI33 " >> ./defines.args
+ echo "-DEFINE WB_CLK220 " >> ./defines.args
+ echo "-DEFINE ACTIVE_HIGH_OE " >> ./defines.args
+ echo "-DEFINE ADDR_TRAN_IMPL " >> ./defines.args
+ echo "-DEFINE WB_CNF_BASE_ZERO " >> ./defines.args
+ echo "-DEFINE NO_CNF_IMAGE " >> ./defines.args
+ echo "-DEFINE WB_IMAGE3 " >> ./defines.args
+ endif
+
+ if ($iter == 10) then
+ echo "<<< Defines:"
+ echo "\tGUEST, REGR_FIFO_SMALL_GENERIC, WB_DECODE_SLOW, PCI_DECODE_MED, "
+ echo "\tWB_DECODE_MIN, PCI33, WB_CLK66, ACTIVE_HIGH_OE, ADDR_TRAN_IMPL, "
+ echo "\tWB_CNF_BASE_ZERO, NO_CNF_IMAGE, PCI_IMAGE0, PCI_IMAGE3. "
+
+ echo "-DEFINE REGRESSION" > ./defines.args
+
+ echo "-DEFINE GUEST " >> ./defines.args
+ echo "-DEFINE REGR_FIFO_SMALL_GENERIC" >> ./defines.args
+ echo "-DEFINE WB_DECODE_SLOW " >> ./defines.args
+ echo "-DEFINE PCI_DECODE_MED " >> ./defines.args
+ echo "-DEFINE WB_DECODE_MIN " >> ./defines.args
+ echo "-DEFINE PCI33 " >> ./defines.args
+ echo "-DEFINE WB_CLK66 " >> ./defines.args
+ echo "-DEFINE ACTIVE_HIGH_OE " >> ./defines.args
+ echo "-DEFINE ADDR_TRAN_IMPL " >> ./defines.args
+ echo "-DEFINE WB_CNF_BASE_ZERO " >> ./defines.args
+ echo "-DEFINE NO_CNF_IMAGE " >> ./defines.args
+ echo "-DEFINE PCI_IMAGE0 " >> ./defines.args
+ echo "-DEFINE PCI_IMAGE3 " >> ./defines.args
+ endif
+
+ if ($iter == 11) then
+ echo "<<< Defines:"
+
+ if ($arg_xilinx == 1) then
+ echo "\tREGR_FIFO_MEDIUM_XILINX, "
+ else if ($arg_artisan == 1) then
+ echo "\tREGR_FIFO_MEDIUM_ARTISAN, "
+ else
+ echo "\tREGR_FIFO_MEDIUM_GENERIC, "
+ endif
+
+ echo "\tGUEST, WB_DECODE_FAST, PCI_DECODE_MIN, "
+ echo "\tWB_DECODE_MAX, PCI66, WB_CLK66, ACTIVE_HIGH_OE, WB_CNF_BASE_ZERO, "
+ echo "\tNO_CNF_IMAGE, PCI_IMAGE0, PCI_IMAGE2, PCI_IMAGE3, PCI_IMAGE4, "
+ echo "\tPCI_IMAGE5, WB_IMAGE2. "
+
+ echo "-DEFINE REGRESSION" > ./defines.args
+
+ if ($arg_xilinx == 1) then
+ echo "-DEFINE REGR_FIFO_MEDIUM_XILINX" >> ./defines.args
+ else if ($arg_artisan == 1) then
+ echo "-DEFINE REGR_FIFO_MEDIUM_ARTISAN" >> ./defines.args
+ else
+ echo "-DEFINE REGR_FIFO_MEDIUM_GENERIC" >> ./defines.args
+ endif
+
+ echo "-DEFINE GUEST " >> ./defines.args
+ echo "-DEFINE WB_DECODE_FAST " >> ./defines.args
+ echo "-DEFINE PCI_DECODE_MIN " >> ./defines.args
+ echo "-DEFINE WB_DECODE_MAX " >> ./defines.args
+ echo "-DEFINE PCI66 " >> ./defines.args
+ echo "-DEFINE WB_CLK66 " >> ./defines.args
+ echo "-DEFINE ACTIVE_HIGH_OE " >> ./defines.args
+ echo "-DEFINE WB_CNF_BASE_ZERO" >> ./defines.args
+ echo "-DEFINE NO_CNF_IMAGE " >> ./defines.args
+ echo "-DEFINE PCI_IMAGE0 " >> ./defines.args
+ echo "-DEFINE PCI_IMAGE2 " >> ./defines.args
+ echo "-DEFINE PCI_IMAGE3 " >> ./defines.args
+ echo "-DEFINE PCI_IMAGE4 " >> ./defines.args
+ echo "-DEFINE PCI_IMAGE5 " >> ./defines.args
+ echo "-DEFINE WB_IMAGE2 " >> ./defines.args
+ endif
+
+ if ($iter == 12) then
+ echo "<<< Defines:"
+ echo "\tGUEST, REGR_FIFO_LARGE_GENERIC, WB_DECODE_MEDIUM, PCI_DECODE_MAX, "
+ echo "\tWB_DECODE_MED, PCI33, WB_CLK10, ACTIVE_HIGH_OE, WB_CNF_BASE_ZERO, "
+ echo "\tNO_CNF_IMAGE, WB_IMAGE2, WB_IMAGE3, WB_IMAGE4, WB_IMAGE5. "
+
+ echo "-DEFINE REGRESSION" > ./defines.args
+
+ echo "-DEFINE GUEST " >> ./defines.args
+ echo "-DEFINE REGR_FIFO_LARGE_GENERIC" >> ./defines.args
+ echo "-DEFINE WB_DECODE_MEDIUM " >> ./defines.args
+ echo "-DEFINE PCI_DECODE_MAX " >> ./defines.args
+ echo "-DEFINE WB_DECODE_MED " >> ./defines.args
+ echo "-DEFINE PCI33 " >> ./defines.args
+ echo "-DEFINE WB_CLK10 " >> ./defines.args
+ echo "-DEFINE ACTIVE_HIGH_OE " >> ./defines.args
+ echo "-DEFINE WB_CNF_BASE_ZERO " >> ./defines.args
+ echo "-DEFINE NO_CNF_IMAGE " >> ./defines.args
+ echo "-DEFINE WB_IMAGE2 " >> ./defines.args
+ echo "-DEFINE WB_IMAGE3 " >> ./defines.args
+ echo "-DEFINE WB_IMAGE4 " >> ./defines.args
+ echo "-DEFINE WB_IMAGE5 " >> ./defines.args
+
+ endif
+
+ if ($iter == 13) then
+
+ echo "<<< Defines:"
+
+ if ($arg_xilinx == 0) then
+ echo "\tREGR_FIFO_SMALL_GENERIC, "
+ else
+ echo "\tREGR_FIFO_SMALL_XILINX, "
+ endif
+
+ echo "\tGUEST, WB_DECODE_FAST, PCI_DECODE_MAX, "
+ echo "\tWB_DECODE_MED, PCI66, WB_CLOCK_FOLLOWS_PCI_CLOCK, ACTIVE_HIGH_OE, WB_CNF_BASE_ZERO, "
+ echo "\tNO_CNF_IMAGE "
+
+ echo "-DEFINE REGRESSION" > ./defines.args
+
+ if ($arg_xilinx == 0) then
+ echo "-DEFINE REGR_FIFO_SMALL_GENERIC" >> ./defines.args
+ else
+ echo "-DEFINE REGR_FIFO_SMALL_XILINX" >> ./defines.args
+ endif
+
+ echo "-DEFINE GUEST " >> ./defines.args
+ echo "-DEFINE WB_DECODE_FAST " >> ./defines.args
+ echo "-DEFINE PCI_DECODE_MAX " >> ./defines.args
+ echo "-DEFINE WB_DECODE_MED " >> ./defines.args
+ echo "-DEFINE PCI66 " >> ./defines.args
+ echo "-DEFINE WB_CLK66 " >> ./defines.args
+ echo "-DEFINE ACTIVE_HIGH_OE " >> ./defines.args
+ echo "-DEFINE WB_CNF_BASE_ZERO " >> ./defines.args
+ echo "-DEFINE NO_CNF_IMAGE " >> ./defines.args
+ echo "-DEFINE WB_CLOCK_FOLLOWS_PCI_CLOCK=2" >> ./defines.args
+
+ endif
+
+ if ($iter == 14) then
+
+ echo "<<< Defines:"
+
+ echo "\tREGR_FIFO_SMALL_GENERIC, "
+
+ echo "\tGUEST, WB_DECODE_FAST, PCI_DECODE_MAX, "
+ echo "\tWB_DECODE_MED, PCI66, WB_CLOCK_FOLLOWS_PCI_CLOCK, ACTIVE_HIGH_OE, WB_CNF_BASE_ZERO, "
+ echo "\tNO_CNF_IMAGE "
+
+ echo "-DEFINE REGRESSION" > ./defines.args
+
+ echo "-DEFINE REGR_FIFO_SMALL_GENERIC" >> ./defines.args
+
+ echo "-DEFINE GUEST " >> ./defines.args
+ echo "-DEFINE WB_DECODE_FAST " >> ./defines.args
+ echo "-DEFINE PCI_DECODE_MAX " >> ./defines.args
+ echo "-DEFINE WB_DECODE_MED " >> ./defines.args
+ echo "-DEFINE PCI66 " >> ./defines.args
+ echo "-DEFINE WB_CLK66 " >> ./defines.args
+ echo "-DEFINE ACTIVE_HIGH_OE " >> ./defines.args
+ echo "-DEFINE WB_CNF_BASE_ZERO " >> ./defines.args
+ echo "-DEFINE NO_CNF_IMAGE " >> ./defines.args
+ echo "-DEFINE PCI_CLOCK_FOLLOWS_WB_CLOCK=2" >> ./defines.args
+
+ endif
+
+ if ($arg_dis_comp_exp_test) then
echo "-DEFINE DISABLE_COMPLETION_EXPIRED_TESTS" >> ./defines.args
- endif
-
- endif
- endif
- endif
- endif
+ endif
+ endif
endif
@@ -489,7 +538,7 @@
echo "-INCDIR ../../../bench/verilog" >> ./ncvlog.args
echo "-INCDIR ../../../rtl/verilog" >> ./ncvlog.args
# adding defines to .args file
-if (($arg_regression == 1) && ($iter < $all_iterations)) then
+if (($arg_regression == 1) && ($iter <= $all_iterations)) then
cat ./defines.args >> ./ncvlog.args
endif
# adding RTL and Sim files to .args file
@@ -571,7 +620,7 @@
@ all_iters += 1;
endif
- if (($arg_regression == 1) && ($iter < $all_iterations)) then
+ if (($arg_regression == 1) && ($iter <= $all_iterations)) then
if ($arg_waves == 1) then
mv ../out/waves.shm ../out/i${iter}_waves.shm
endif
@@ -580,6 +629,8 @@
mv ../log/pciu_mon.log ../log/i${iter}_pciu_mon.log
mv ../log/wbu_mon.log ../log/i${iter}_wbu_mon.log
mv ../log/ncsim.log ../log/i${iter}_ncsim.log
+ mv ../log/ncvlog.log ../log/i${iter}_ncvlog.log
+ mv ../log/ncelab.log ../log/i${iter}_ncelab.log
endif
endif
echo ""