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URL https://opencores.org/ocsvn/8051/8051/trunk

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  • This comparison shows the changes necessary to convert path
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    from Rev 104 to Rev 105
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Rev 104 → Rev 105

/trunk/rtl/verilog/oc8051_ram_top.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.7 2003/04/02 11:26:21 simont
// updating...
//
// Revision 1.6 2003/01/26 14:19:22 rherveille
// Replaced oc8051_ram by generic_dpram.
//
100,11 → 103,6
assign bit_data_out = rd_data[bit_select];
 
 
 
oc8051_ram oc8051_ram1(.clk(clk), .rst(rst), .rd_addr(rd_addr_m), .rd_data(rd_data), .wr_addr(wr_addr_m),
.wr_data(wr_data_m), .wr(wr));
 
/*
generic_dpram #(ram_aw, 8) oc8051_ram1(
.rclk ( clk ),
.rrst ( rst ),
120,8 → 118,8
.waddr ( wr_addr_m ),
.di ( wr_data_m )
);
*/
 
 
always @(posedge clk or posedge rst)
if (rst) begin
bit_addr_r <= #1 1'b0;

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