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/tags/rel_13/rtl/verilog/dbg_cpu.v
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//////////////////////////////////////////////////////////////////////
//// ////
//// dbg_cpu.v ////
//// ////
//// ////
//// This file is part of the SoC/OpenRISC Development Interface ////
//// http://www.opencores.org/projects/DebugInterface/ ////
//// ////
//// Author(s): ////
//// Igor Mohor (igorm@opencores.org) ////
//// ////
//// ////
//// All additional information is avaliable in the README.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 - 2004 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3 2004/01/17 18:01:24 mohor
// New version.
//
// Revision 1.2 2004/01/17 17:01:14 mohor
// Almost finished.
//
// Revision 1.1 2004/01/16 14:53:31 mohor
// *** empty log message ***
//
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "dbg_cpu_defines.v"
 
// Top module
module dbg_cpu(
// JTAG signals
tck_i,
tdi_i,
tdo_o,
 
// TAP states
shift_dr_i,
pause_dr_i,
update_dr_i,
 
cpu_ce_i,
crc_match_i,
crc_en_o,
shift_crc_o,
rst_i,
 
// CPU signals
cpu_clk_i,
cpu_addr_o,
cpu_data_i,
cpu_data_o,
cpu_bp_i,
cpu_stall_o,
cpu_stall_all_o,
cpu_stb_o,
cpu_sel_o, // Not synchronized
cpu_we_o,
cpu_ack_i,
cpu_rst_o
 
 
);
 
// JTAG signals
input tck_i;
input tdi_i;
output tdo_o;
 
// TAP states
input shift_dr_i;
input pause_dr_i;
input update_dr_i;
 
input cpu_ce_i;
input crc_match_i;
output crc_en_o;
output shift_crc_o;
input rst_i;
 
 
// CPU signals
input cpu_clk_i;
output [31:0] cpu_addr_o;
input [31:0] cpu_data_i;
output [31:0] cpu_data_o;
input cpu_bp_i;
output cpu_stall_o;
output cpu_stall_all_o;
output cpu_stb_o;
output [`CPU_NUM -1:0] cpu_sel_o;
output cpu_we_o;
input cpu_ack_i;
output cpu_rst_o;
 
 
reg tdo_o;
reg [799:0] tdo_text;
 
wire cmd_cnt_en;
reg [1:0] cmd_cnt;
wire cmd_cnt_end;
reg cmd_cnt_end_q;
wire addr_cnt_en;
reg [5:0] addr_cnt;
reg [5:0] addr_cnt_limit;
wire addr_cnt_end;
wire crc_cnt_en;
reg [5:0] crc_cnt;
wire crc_cnt_end;
reg crc_cnt_end_q;
wire data_cnt_en;
reg [5:0] data_cnt;
reg [5:0] data_cnt_limit;
wire data_cnt_end;
reg data_cnt_end_q;
wire status_cnt_end;
reg status_cnt1, status_cnt2, status_cnt3, status_cnt4;
reg [3:0] status;
reg [199:0] status_text;
 
reg crc_match_reg;
wire enable;
 
reg read_cycle_reg;
reg read_cycle_reg_q;
reg read_cycle_cpu;
reg read_cycle_cpu_q;
reg write_cycle_reg;
reg write_cycle_cpu;
wire read_cycle;
wire write_cycle;
 
reg [34:0] dr;
wire [7:0] reg_data_out;
 
wire dr_read_reg;
wire dr_write_reg;
wire dr_read_cpu8;
wire dr_read_cpu32;
wire dr_write_cpu8;
wire dr_write_cpu32;
wire dr_go;
reg dr_read_reg_latched;
reg dr_write_reg_latched;
reg dr_read_cpu8_latched;
reg dr_read_cpu32_latched;
reg dr_write_cpu8_latched;
reg dr_write_cpu32_latched;
reg dr_go_latched;
reg cmd_read_reg;
reg cmd_read_cpu;
reg cmd_write_reg;
reg cmd_write_cpu;
reg cycle_32_bit;
reg reg_access;
 
reg [31:0] adr;
reg set_addr;
reg [199:0] latching_data_text;
reg cpu_ack_sync;
reg cpu_ack_tck;
reg cpu_ack_tck_q;
reg cpu_stb;
reg cpu_stb_sync;
reg cpu_stb_o;
wire cpu_stall_tmp;
 
wire go_prelim;
wire crc_cnt_31;
 
 
 
assign enable = cpu_ce_i & shift_dr_i;
assign crc_en_o = enable & crc_cnt_end & (~status_cnt_end);
assign shift_crc_o = enable & status_cnt_end; // Signals dbg module to shift out the CRC
 
 
assign cmd_cnt_en = enable & (~cmd_cnt_end);
 
 
// Command counter
always @ (posedge tck_i or posedge rst_i)
begin
if (rst_i)
cmd_cnt <= #1 'h0;
else if (update_dr_i)
cmd_cnt <= #1 'h0;
else if (cmd_cnt_en)
cmd_cnt <= #1 cmd_cnt + 1'b1;
end
 
 
assign addr_cnt_en = enable & cmd_cnt_end & (~addr_cnt_end);
 
 
// Address/length counter
always @ (posedge tck_i or posedge rst_i)
begin
if (rst_i)
addr_cnt <= #1 'h0;
else if (update_dr_i)
addr_cnt <= #1 'h0;
else if (addr_cnt_en)
addr_cnt <= #1 addr_cnt + 1'b1;
end
 
 
assign data_cnt_en = enable & (~data_cnt_end) & (cmd_cnt_end & write_cycle | crc_cnt_end & read_cycle);
 
 
// Data counter
always @ (posedge tck_i or posedge rst_i)
begin
if (rst_i)
data_cnt <= #1 'h0;
else if (update_dr_i)
data_cnt <= #1 'h0;
else if (data_cnt_en)
data_cnt <= #1 data_cnt + 1'b1;
end
 
 
assign crc_cnt_en = enable & (~crc_cnt_end) & (cmd_cnt_end & addr_cnt_end & (~write_cycle) | (data_cnt_end & write_cycle));
 
 
// crc counter
always @ (posedge tck_i or posedge rst_i)
begin
if (rst_i)
crc_cnt <= #1 'h0;
else if(crc_cnt_en)
crc_cnt <= #1 crc_cnt + 1'b1;
else if (update_dr_i)
crc_cnt <= #1 'h0;
end
 
 
// Upper limit. Address/length counter counts until this value is reached
always @ (posedge tck_i)
begin
if (cmd_cnt == 2'h2)
begin
if ((~dr[0]) & (~tdi_i)) // (current command is WB_STATUS or WB_GO)
addr_cnt_limit = 6'd0;
else // (current command is WB_WRITEx or WB_READx)
addr_cnt_limit = 6'd32;
end
end
 
assign cmd_cnt_end = cmd_cnt == 2'h3;
assign addr_cnt_end = addr_cnt == addr_cnt_limit;
assign crc_cnt_end = crc_cnt == 6'd32;
assign crc_cnt_31 = crc_cnt == 6'd31;
assign data_cnt_end = (data_cnt == data_cnt_limit);
 
always @ (posedge tck_i)
begin
crc_cnt_end_q <= #1 crc_cnt_end;
cmd_cnt_end_q <= #1 cmd_cnt_end;
data_cnt_end_q <= #1 data_cnt_end;
end
 
 
// Status counter is made of 4 serialy connected registers
always @ (posedge tck_i or posedge rst_i)
begin
if (rst_i)
status_cnt1 <= #1 1'b0;
else if (update_dr_i)
status_cnt1 <= #1 1'b0;
else if (data_cnt_end & read_cycle |
crc_cnt_end & (~read_cycle)
)
status_cnt1 <= #1 1'b1;
end
 
 
always @ (posedge tck_i or posedge rst_i)
begin
if (rst_i)
begin
status_cnt2 <= #1 1'b0;
status_cnt3 <= #1 1'b0;
status_cnt4 <= #1 1'b0;
end
else if (update_dr_i)
begin
status_cnt2 <= #1 1'b0;
status_cnt3 <= #1 1'b0;
status_cnt4 <= #1 1'b0;
end
else
begin
status_cnt2 <= #1 status_cnt1;
status_cnt3 <= #1 status_cnt2;
status_cnt4 <= #1 status_cnt3;
end
end
 
 
assign status_cnt_end = status_cnt4;
 
 
 
 
// Latching address
always @ (posedge tck_i)
begin
if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i)
begin
if (~dr_go_latched)
begin
adr <= #1 dr[31:0];
set_addr <= #1 1'b1;
end
end
else
set_addr <= #1 1'b0;
end
 
 
assign cpu_addr_o = adr;
 
 
// Shift register for shifting in and out the data
always @ (posedge tck_i)
begin
if (reg_access)
begin
dr[31:24] <= #1 reg_data_out;
latching_data_text = "Latch reg data";
end
else if (cpu_ack_tck & (~cpu_ack_tck_q) & read_cycle_cpu)
begin
if (cycle_32_bit)
dr[31:0] <= #1 cpu_data_i;
else
dr[31:24] <= #1 cpu_data_i[7:0];
latching_data_text = "Latch cpu data";
end
else if (enable & ((~addr_cnt_end) | (~cmd_cnt_end) | ((~data_cnt_end) & write_cycle) | (crc_cnt_end & (~data_cnt_end) & read_cycle)))
begin
dr <= #1 {dr[33:0], tdi_i};
latching_data_text = "shifting data";
end
else
latching_data_text = "nothing";
end
 
 
assign dr_read_reg = dr[2:0] == `CPU_READ_REG;
assign dr_write_reg = dr[2:0] == `CPU_WRITE_REG;
assign dr_read_cpu8 = dr[2:0] == `CPU_READ8;
assign dr_read_cpu32 = dr[2:0] == `CPU_READ32;
assign dr_write_cpu8 = dr[2:0] == `CPU_WRITE8;
assign dr_write_cpu32 = dr[2:0] == `CPU_WRITE32;
assign dr_go = dr[2:0] == `CPU_GO;
 
 
// Latching instruction
always @ (posedge tck_i)
begin
if (update_dr_i)
begin
dr_read_reg_latched <= #1 1'b0;
dr_read_cpu8_latched <= #1 1'b0;
dr_read_cpu32_latched <= #1 1'b0;
dr_write_reg_latched <= #1 1'b0;
dr_write_cpu8_latched <= #1 1'b0;
dr_write_cpu32_latched <= #1 1'b0;
dr_go_latched <= #1 1'b0;
end
else if (cmd_cnt_end & (~cmd_cnt_end_q))
begin
dr_read_reg_latched <= #1 dr_read_reg;
dr_read_cpu8_latched <= #1 dr_read_cpu8;
dr_read_cpu32_latched <= #1 dr_read_cpu32;
dr_write_reg_latched <= #1 dr_write_reg;
dr_write_cpu8_latched <= #1 dr_write_cpu8;
dr_write_cpu32_latched <= #1 dr_write_cpu32;
dr_go_latched <= #1 dr_go;
end
end
 
// Latching instruction
always @ (posedge tck_i or posedge rst_i)
begin
if (rst_i)
begin
cmd_read_reg <= #1 1'b0;
cmd_read_cpu <= #1 1'b0;
cmd_write_reg <= #1 1'b0;
cmd_write_cpu <= #1 1'b0;
cycle_32_bit <= #1 1'b0;
end
else if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i)
begin
cmd_read_reg <= #1 dr_read_reg_latched;
cmd_read_cpu <= #1 dr_read_cpu8_latched | dr_read_cpu32_latched;
cmd_write_reg <= #1 dr_write_reg_latched;
cmd_write_cpu <= #1 dr_write_cpu8_latched | dr_write_cpu32_latched;
cycle_32_bit <= #1 dr_read_cpu32_latched | dr_write_cpu32_latched;
end
end
 
 
// Upper limit. Data counter counts until this value is reached.
always @ (posedge tck_i or posedge rst_i)
begin
if (rst_i)
data_cnt_limit <= #1 6'h0;
else if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i & (~dr_go_latched))
begin
if (dr_read_cpu32_latched | dr_write_cpu32_latched)
data_cnt_limit <= #1 6'd32;
else
data_cnt_limit <= #1 6'd8;
end
end
 
 
assign go_prelim = (cmd_cnt == 2'h2) & dr[1] & (~dr[0]) & (~tdi_i);
 
 
always @ (posedge tck_i)
begin
if (update_dr_i)
read_cycle_reg <= #1 1'b0;
else if (cmd_read_reg & go_prelim)
read_cycle_reg <= #1 1'b1;
end
 
 
always @ (posedge tck_i)
begin
if (update_dr_i)
read_cycle_cpu <= #1 1'b0;
else if (cmd_read_cpu & go_prelim)
read_cycle_cpu <= #1 1'b1;
end
 
 
always @ (posedge tck_i)
begin
read_cycle_reg_q <= #1 read_cycle_reg;
read_cycle_cpu_q <= #1 read_cycle_cpu;
end
 
 
always @ (posedge tck_i)
begin
if (update_dr_i)
write_cycle_reg <= #1 1'b0;
else if (cmd_write_reg & go_prelim)
write_cycle_reg <= #1 1'b1;
end
 
 
always @ (posedge tck_i)
begin
if (update_dr_i)
write_cycle_cpu <= #1 1'b0;
else if (cmd_write_cpu & go_prelim)
write_cycle_cpu <= #1 1'b1;
end
 
 
assign read_cycle = read_cycle_reg | read_cycle_cpu;
assign write_cycle = write_cycle_reg | write_cycle_cpu;
 
 
 
// Start register access cycle
always @ (posedge tck_i)
begin
if (write_cycle_reg & data_cnt_end & (~data_cnt_end_q) | read_cycle_reg & (~read_cycle_reg_q))
begin
reg_access <= #1 1'b1;
end
else
reg_access <= #1 1'b0;
end
 
 
 
// Connecting dbg_cpu_registers
dbg_cpu_registers i_dbg_cpu_registers
(
.data_i (dr[7:0]),
.data_o (reg_data_out),
.addr_i (adr[1:0]),
.we_i (write_cycle_reg),
.en_i (reg_access),
.clk_i (tck_i),
.bp_i (cpu_bp_i),
.rst_i (rst_i),
.cpu_clk_i (cpu_clk_i),
.cpu_stall_o (cpu_stall_tmp),
.cpu_stall_all_o (cpu_stall_all_o),
.cpu_sel_o (cpu_sel_o),
.cpu_rst_o (cpu_rst_o)
);
 
 
 
assign cpu_we_o = write_cycle_cpu;
assign cpu_data_o = dr[31:0];
assign cpu_stall_o = cpu_stb_o | cpu_stall_tmp;
 
 
 
// Synchronizing ack signal from cpu
always @ (posedge tck_i)
begin
cpu_ack_sync <= #1 cpu_ack_i;
cpu_ack_tck <= #1 cpu_ack_sync;
cpu_ack_tck_q <= #1 cpu_ack_tck;
end
 
 
 
// Start cpu access cycle
always @ (posedge tck_i)
begin
if (update_dr_i)
cpu_stb <= #1 1'b0;
else if (cpu_ack_tck)
cpu_stb <= #1 1'b0;
else if (write_cycle_cpu & data_cnt_end & (~data_cnt_end_q) | read_cycle_cpu & (~read_cycle_cpu_q))
cpu_stb <= #1 1'b1;
end
 
 
 
// Synchronizing cpu_stb to cpu_clk_i clock
always @ (posedge cpu_clk_i)
begin
cpu_stb_sync <= #1 cpu_stb;
cpu_stb_o <= #1 cpu_stb_sync;
end
 
 
// Latching crc
always @ (posedge tck_i)
begin
if(crc_cnt_end & (~crc_cnt_end_q))
crc_match_reg <= #1 crc_match_i;
end
 
 
 
// Status register
always @ (posedge tck_i or posedge rst_i)
begin
if (rst_i)
begin
status <= #1 'h0;
status_text <= #1 "reset";
end
else if(crc_cnt_end & (~crc_cnt_end_q) & (~read_cycle))
begin
status <= #1 {crc_match_i, 1'b0, 1'b1, 1'b0};
status_text <= #1 "!!!READ";
end
else if (data_cnt_end & (~data_cnt_end_q) & read_cycle)
begin
status <= #1 {crc_match_reg, 1'b0, 1'b1, 1'b0};
status_text <= #1 "READ";
end
else if (shift_dr_i & (~status_cnt_end))
begin
status <= #1 {status[0], status[3:1]};
status_text <= #1 "shift";
end
end
// Following status is shifted out:
// 1. bit: 1 if crc is OK, else 0
// 2. bit: 1'b0
// 3. bit: 1'b1
// 4. bit: 1'b0
 
 
 
// TDO multiplexer
always @ (crc_cnt_end or crc_cnt_end_q or crc_match_i or data_cnt_end or data_cnt_end_q or
read_cycle or crc_match_reg or status or dr)
begin
if (crc_cnt_end & (~crc_cnt_end_q) & (~(read_cycle)))
begin
tdo_o = crc_match_i;
tdo_text = "crc_match_i";
end
else if (read_cycle & crc_cnt_end & (~data_cnt_end))
begin
tdo_o = dr[31];
tdo_text = "read data";
end
else if (read_cycle & data_cnt_end & (~data_cnt_end_q)) // cmd is already updated
begin
tdo_o = crc_match_reg;
tdo_text = "crc_match_reg";
end
else if (crc_cnt_end)
begin
tdo_o = status[0];
tdo_text = "status";
end
else
begin
tdo_o = 1'b0;
tdo_text = "zero while CRC is shifted in";
end
end
 
 
 
 
 
 
 
endmodule
 
tags/rel_13/rtl/verilog/dbg_cpu.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/rel_13/rtl/verilog/dbg_wb.v =================================================================== --- tags/rel_13/rtl/verilog/dbg_wb.v (nonexistent) +++ tags/rel_13/rtl/verilog/dbg_wb.v (revision 105) @@ -0,0 +1,1043 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// dbg_wb.v //// +//// //// +//// //// +//// This file is part of the SoC/OpenRISC Development Interface //// +//// http://www.opencores.org/projects/DebugInterface/ //// +//// //// +//// Author(s): //// +//// Igor Mohor (igorm@opencores.org) //// +//// //// +//// //// +//// All additional information is avaliable in the README.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 - 2003 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.14 2004/01/16 14:51:33 mohor +// cpu registers added. +// +// Revision 1.13 2004/01/15 12:09:43 mohor +// Working. +// +// Revision 1.12 2004/01/14 22:59:18 mohor +// Temp version. +// +// Revision 1.11 2004/01/14 12:29:40 mohor +// temp version. Resets will be changed in next version. +// +// Revision 1.10 2004/01/13 11:28:14 mohor +// tmp version. +// +// Revision 1.9 2004/01/10 07:50:24 mohor +// temp version. +// +// Revision 1.8 2004/01/09 12:48:44 mohor +// tmp version. +// +// Revision 1.7 2004/01/08 17:53:36 mohor +// tmp version. +// +// Revision 1.6 2004/01/07 11:58:56 mohor +// temp4 version. +// +// Revision 1.5 2004/01/06 17:15:19 mohor +// temp3 version. +// +// Revision 1.4 2004/01/05 12:16:00 mohor +// tmp2 version. +// +// Revision 1.3 2003/12/23 16:22:46 mohor +// Tmp version. +// +// Revision 1.2 2003/12/23 15:26:26 mohor +// Small fix. +// +// Revision 1.1 2003/12/23 15:09:04 mohor +// New directory structure. New version of the debug interface. +// +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "dbg_wb_defines.v" + +// Top module +module dbg_wb( + // JTAG signals + tck_i, + tdi_i, + tdo_o, + + // TAP states + shift_dr_i, + pause_dr_i, + update_dr_i, + + wishbone_ce_i, + crc_match_i, + crc_en_o, + shift_crc_o, + rst_i, + + // WISHBONE common signals + wb_clk_i, + + // WISHBONE master interface + wb_adr_o, wb_dat_o, wb_dat_i, wb_cyc_o, wb_stb_o, wb_sel_o, + wb_we_o, wb_ack_i, wb_cab_o, wb_err_i, wb_cti_o, wb_bte_o + + ); + +// JTAG signals +input tck_i; +input tdi_i; +output tdo_o; + +// TAP states +input shift_dr_i; +input pause_dr_i; +input update_dr_i; + +input wishbone_ce_i; +input crc_match_i; +output crc_en_o; +output shift_crc_o; +input rst_i; +// WISHBONE common signals +input wb_clk_i; + +// WISHBONE master interface +output [31:0] wb_adr_o; +output [31:0] wb_dat_o; +input [31:0] wb_dat_i; +output wb_cyc_o; +output wb_stb_o; +output [3:0] wb_sel_o; +output wb_we_o; +input wb_ack_i; +output wb_cab_o; +input wb_err_i; +output [2:0] wb_cti_o; +output [1:0] wb_bte_o; + +reg wb_cyc_o; +reg [31:0] wb_adr_o; +reg [31:0] wb_dat_o; +reg [3:0] wb_sel_o; + +reg tdo_o; + +reg [50:0] dr; +wire enable; +wire cmd_cnt_en; +reg [1:0] cmd_cnt; +wire cmd_cnt_end; +reg cmd_cnt_end_q; +wire addr_len_cnt_en; +reg [5:0] addr_len_cnt; +reg [5:0] addr_len_cnt_limit; +wire addr_len_cnt_end; +wire crc_cnt_en; +reg [5:0] crc_cnt; +wire crc_cnt_end; +reg crc_cnt_end_q; +wire data_cnt_en; +reg [18:0] data_cnt; +reg [18:0] data_cnt_limit; +wire data_cnt_end; +reg data_cnt_end_q; +reg status_reset_en; + +reg crc_match_reg; + +reg [2:0] cmd, cmd_old, dr_cmd_latched; +reg [31:0] adr; +reg [15:0] len; +reg start_rd_tck; +reg rd_tck_started; +reg start_rd_sync1; +reg start_wb_rd; +reg start_wb_rd_q; +reg start_wr_tck; +reg start_wr_sync1; +reg start_wb_wr; +reg start_wb_wr_q; + +wire dr_read; +wire dr_write; +wire dr_go; + +reg dr_write_latched; +reg dr_read_latched; +reg dr_go_latched; + +wire status_cnt_end; + +wire byte, half, long; +reg byte_q, half_q, long_q; +reg byte_q2, half_q2, long_q2; +reg cmd_read; +reg cmd_write; +reg cmd_go; + +reg status_cnt1, status_cnt2, status_cnt3, status_cnt4; + +reg [`STATUS_LEN -1:0] status; + +reg wb_error, wb_error_sync, wb_error_tck; +reg wb_overrun, wb_overrun_sync, wb_overrun_tck; +reg underrun_tck; + +reg busy_wb; +reg busy_tck; +reg wb_end; +reg wb_end_rst; +reg wb_end_rst_sync; +reg wb_end_sync; +reg wb_end_tck, wb_end_tck_q; +reg busy_sync; +reg [799:0] tdo_text; +reg [399:0] latching_data_text; +reg latch_data; +reg [199:0] status_text; + +reg set_addr, set_addr_sync, set_addr_wb, set_addr_wb_q; +reg read_cycle; +reg write_cycle; +reg [2:0] rw_type; +wire [31:0] input_data; + +wire len_eq_0; +wire crc_cnt_31; + +reg [1:0] ptr; +reg [2:0] fifo_cnt; +wire fifo_full; +wire fifo_empty; +reg [7:0] mem [0:3]; +reg [2:0] mem_ptr; +reg wishbone_ce_sync; +reg wishbone_ce_rst; +wire go_prelim; + + + +assign enable = wishbone_ce_i & shift_dr_i; +assign crc_en_o = enable & crc_cnt_end & (~status_cnt_end); +assign shift_crc_o = enable & status_cnt_end; // Signals dbg module to shift out the CRC + + +// Selecting where to take the data from +always @ (posedge tck_i) +begin + if (update_dr_i) + ptr <= #1 2'h0; + else if (read_cycle & crc_cnt_31) // first latch + ptr <= #1 ptr + 1'b1; + else if (read_cycle & byte & (~byte_q)) + ptr <= ptr + 1'd1; +end + + +// Shift register for shifting in and out the data +always @ (posedge tck_i) +begin + if (read_cycle & crc_cnt_31) + begin + dr[31:0] <= #1 input_data[31:0]; + latch_data <= #1 1'b1; + latching_data_text <= #1 "First latch"; + end + else if (read_cycle & crc_cnt_end) + begin + case (rw_type) // synthesis parallel_case full_case + `WB_READ8 : begin + if(byte & (~byte_q)) + begin + case (ptr) // synthesis parallel_case + 2'b00 : dr[31:24] <= #1 input_data[31:24]; + 2'b01 : dr[31:24] <= #1 input_data[23:16]; + 2'b10 : dr[31:24] <= #1 input_data[15:8]; + 2'b11 : dr[31:24] <= #1 input_data[7:0]; + endcase + latch_data <= #1 1'b1; + latching_data_text <= #1 "8 bit latched"; + end + else + begin + dr[31:24] <= #1 {dr[30:24], 1'b0}; + latch_data <= #1 1'b0; + latching_data_text <= #1 "8 bit shifted"; + end + end + `WB_READ16: begin + if(half & (~half_q)) + begin + if (ptr[1]) + dr[31:16] <= #1 input_data[15:0]; + else + dr[31:16] <= #1 input_data[31:16]; + latching_data_text <= #1 "16 bit latched"; + latch_data <= #1 1'b1; + end + else + begin + dr[31:16] <= #1 {dr[30:16], 1'b0}; + latch_data <= #1 1'b0; + latching_data_text <= #1 "16 bit shifted"; + end + end + `WB_READ32: begin + if(long & (~long_q)) + begin + dr[31:0] <= #1 input_data[31:0]; + latch_data <= #1 1'b1; + latching_data_text <= #1 "32 bit latched"; + end + else + begin + dr[31:0] <= #1 {dr[30:0], 1'b0}; + latch_data <= #1 1'b0; + latching_data_text <= #1 "32 bit shifted"; + end + end + endcase + end + else if (enable & ((~addr_len_cnt_end) | (~cmd_cnt_end) | ((~data_cnt_end) & write_cycle))) + begin + dr <= #1 {dr[49:0], tdi_i}; + latch_data <= #1 1'b0; + latching_data_text <= #1 "tdi shifted in"; + end + else + latching_data_text <= #1 "nothing"; +end + + +assign cmd_cnt_en = enable & (~cmd_cnt_end); + + +// Command counter +always @ (posedge tck_i or posedge rst_i) +begin + if (rst_i) + cmd_cnt <= #1 'h0; + else if (update_dr_i) + cmd_cnt <= #1 'h0; + else if (cmd_cnt_en) + cmd_cnt <= #1 cmd_cnt + 1'b1; +end + + +assign addr_len_cnt_en = enable & cmd_cnt_end & (~addr_len_cnt_end); + + +// Address/length counter +always @ (posedge tck_i or posedge rst_i) +begin + if (rst_i) + addr_len_cnt <= #1 'h0; + else if (update_dr_i) + addr_len_cnt <= #1 'h0; + else if (addr_len_cnt_en) + addr_len_cnt <= #1 addr_len_cnt + 1'b1; +end + + +assign data_cnt_en = enable & (~data_cnt_end) & (cmd_cnt_end & write_cycle | crc_cnt_end & read_cycle); + + +// Data counter +always @ (posedge tck_i or posedge rst_i) +begin + if (rst_i) + data_cnt <= #1 'h0; + else if (update_dr_i) + data_cnt <= #1 'h0; + else if (data_cnt_en) + data_cnt <= #1 data_cnt + 1'b1; +end + + + +assign byte = data_cnt[2:0] == 3'd7; +assign half = data_cnt[3:0] == 4'd15; +assign long = data_cnt[4:0] == 5'd31; + + +always @ (posedge tck_i) +begin + byte_q <= #1 byte; + half_q <= #1 half; + long_q <= #1 long; + byte_q2 <= #1 byte_q; + half_q2 <= #1 half_q; + long_q2 <= #1 long_q; +end + + +assign dr_read = (dr[2:0] == `WB_READ8) | (dr[2:0] == `WB_READ16) | (dr[2:0] == `WB_READ32); +assign dr_write = (dr[2:0] == `WB_WRITE8) | (dr[2:0] == `WB_WRITE16) | (dr[2:0] == `WB_WRITE32); +assign dr_go = dr[2:0] == `WB_GO; + + +// Latching instruction +always @ (posedge tck_i) +begin + if (update_dr_i) + begin + dr_cmd_latched <= #1 3'h0; + dr_read_latched <= #1 1'b0; + dr_write_latched <= #1 1'b0; + dr_go_latched <= #1 1'b0; + end + else if (cmd_cnt_end & (~cmd_cnt_end_q)) + begin + dr_cmd_latched <= #1 dr[2:0]; + dr_read_latched <= #1 dr_read; + dr_write_latched <= #1 dr_write; + dr_go_latched <= #1 dr_go; + end +end + + +// Upper limit. Address/length counter counts until this value is reached +always @ (posedge tck_i) +begin + if (cmd_cnt == 2'h2) + begin + if ((~dr[0]) & (~tdi_i)) // (current command is WB_STATUS or WB_GO) + addr_len_cnt_limit <= #1 6'd0; + else // (current command is WB_WRITEx or WB_READx) + addr_len_cnt_limit <= #1 6'd48; + end +end + + +assign go_prelim = (cmd_cnt == 2'h2) & dr[1] & (~dr[0]) & (~tdi_i); + + +// Upper limit. Data counter counts until this value is reached. +always @ (posedge tck_i) +begin + if (update_dr_i) + data_cnt_limit <= #1 {len, 3'b000}; +end + + +assign crc_cnt_en = enable & (~crc_cnt_end) & (cmd_cnt_end & addr_len_cnt_end & (~write_cycle) | (data_cnt_end & write_cycle)); + + +// crc counter +always @ (posedge tck_i or posedge rst_i) +begin + if (rst_i) + crc_cnt <= #1 'h0; + else if(crc_cnt_en) + crc_cnt <= #1 crc_cnt + 1'b1; + else if (update_dr_i) + crc_cnt <= #1 'h0; +end + +assign cmd_cnt_end = cmd_cnt == 2'h3; +assign addr_len_cnt_end = addr_len_cnt == addr_len_cnt_limit; +assign crc_cnt_end = crc_cnt == 6'd32; +assign crc_cnt_31 = crc_cnt == 6'd31; +assign data_cnt_end = (data_cnt == data_cnt_limit); + +always @ (posedge tck_i) +begin + crc_cnt_end_q <= #1 crc_cnt_end; + cmd_cnt_end_q <= #1 cmd_cnt_end; + data_cnt_end_q <= #1 data_cnt_end; +end + + +// Status counter is made of 4 serialy connected registers +always @ (posedge tck_i or posedge rst_i) +begin + if (rst_i) + status_cnt1 <= #1 1'b0; + else if (update_dr_i) + status_cnt1 <= #1 1'b0; + else if (data_cnt_end & read_cycle | + crc_cnt_end & (~read_cycle) + ) + status_cnt1 <= #1 1'b1; +end + + +always @ (posedge tck_i or posedge rst_i) +begin + if (rst_i) + begin + status_cnt2 <= #1 1'b0; + status_cnt3 <= #1 1'b0; + status_cnt4 <= #1 1'b0; + end + else if (update_dr_i) + begin + status_cnt2 <= #1 1'b0; + status_cnt3 <= #1 1'b0; + status_cnt4 <= #1 1'b0; + end + else + begin + status_cnt2 <= #1 status_cnt1; + status_cnt3 <= #1 status_cnt2; + status_cnt4 <= #1 status_cnt3; + end +end + + +assign status_cnt_end = status_cnt4; + + +// Status register +always @ (posedge tck_i or posedge rst_i) +begin + if (rst_i) + begin + status <= #1 'h0; + status_text <= #1 "reset"; + end + else if(crc_cnt_end & (~crc_cnt_end_q) & (~read_cycle)) + begin + status <= #1 {crc_match_i, wb_error_tck, wb_overrun_tck, busy_tck}; + status_text <= #1 "!!!READ"; + end + else if (data_cnt_end & (~data_cnt_end_q) & read_cycle) + begin + status <= #1 {crc_match_reg, wb_error_tck, underrun_tck, busy_tck}; + status_text <= #1 "READ"; + end + else if (shift_dr_i & (~status_cnt_end)) + begin + status <= #1 {status[0], status[`STATUS_LEN -1:1]}; + status_text <= #1 "shift"; + end +end +// Following status is shifted out: +// 1. bit: 1 if crc is OK, else 0 +// 2. bit: 1 while WB access is in progress (busy_tck), else 0 +// 3. bit: 1 if overrun occured during write (data couldn't be written fast enough) +// or underrun occured during read (data couldn't be read fast enough) +// 4. bit: 1 if WB error occured, else 0 + + +// TDO multiplexer +always @ (pause_dr_i or busy_tck or crc_cnt_end or crc_cnt_end_q or crc_match_i or + data_cnt_end or data_cnt_end_q or read_cycle or crc_match_reg or status or dr) +begin + if (pause_dr_i) + begin + tdo_o = busy_tck; + tdo_text = "busy_tck"; + end + else if (crc_cnt_end & (~crc_cnt_end_q) & (~(read_cycle))) + begin + tdo_o = crc_match_i; + tdo_text = "crc_match_i"; + end + else if (read_cycle & crc_cnt_end & (~data_cnt_end)) + begin + tdo_o = dr[31]; + tdo_text = "read data"; + end + else if (read_cycle & data_cnt_end & (~data_cnt_end_q)) // cmd is already updated + begin + tdo_o = crc_match_reg; + tdo_text = "crc_match_reg"; + end + else if (crc_cnt_end & data_cnt_end) // cmd is already updated + begin + tdo_o = status[0]; + tdo_text = "status"; + end + else + begin + tdo_o = 1'b0; + tdo_text = "zero while CRC is shifted in"; + end +end + + + +always @ (posedge tck_i) +begin + if(crc_cnt_end & (~crc_cnt_end_q)) + crc_match_reg <= #1 crc_match_i; +end + + +// Latching instruction +always @ (posedge tck_i or posedge rst_i) +begin + if (rst_i) + begin + cmd <= #1 'h0; + cmd_old <= #1 'h0; + cmd_read <= #1 1'b0; + cmd_write <= #1 1'b0; + cmd_go <= #1 1'b0; + end + else if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i) + begin + cmd <= #1 dr_cmd_latched; + cmd_old <= #1 cmd; + cmd_read <= #1 dr_read_latched; + cmd_write <= #1 dr_write_latched; + cmd_go <= #1 dr_go_latched; + end +end + + +// Latching address +always @ (posedge tck_i) +begin + if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i) + begin + if (dr_write_latched | dr_read_latched) + begin + adr <= #1 dr[47:16]; + set_addr <= #1 1'b1; + end + end + else + set_addr <= #1 1'b0; +end + + +// Length counter +always @ (posedge tck_i) +begin + if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i & (dr_write_latched | dr_read_latched)) + len <= #1 dr[15:0]; + else if (start_rd_tck) + begin + case (rw_type) // synthesis parallel_case full_case + `WB_READ8 : len <= #1 len - 1'd1; + `WB_READ16: len <= #1 len - 2'd2; + `WB_READ32: len <= #1 len - 3'd4; + endcase + end +end + + +assign len_eq_0 = len == 16'h0; + + +// Start wishbone read cycle +always @ (posedge tck_i) +begin + if (read_cycle & (~dr_go_latched) & (~len_eq_0)) // First read after cmd is entered + start_rd_tck <= #1 1'b1; + else if ((~start_rd_tck) & read_cycle & (~len_eq_0) & (~fifo_full) & (~rd_tck_started)) + start_rd_tck <= #1 1'b1; + else + start_rd_tck <= #1 1'b0; +end + + +always @ (posedge tck_i) +begin + if (update_dr_i) + rd_tck_started <= #1 1'b0; + else if (start_rd_tck) + rd_tck_started <= #1 1'b1; + else if (wb_end_tck & (~wb_end_tck_q)) + rd_tck_started <= #1 1'b0; +end + + +always @ (posedge tck_i) +begin + if (update_dr_i) + read_cycle <= #1 1'b0; + else if (cmd_read & go_prelim) + read_cycle <= #1 1'b1; +end + + +always @ (posedge tck_i) +begin + if ((cmd_read | cmd_write) & go_prelim) + rw_type <= #1 cmd; +end + + +always @ (posedge tck_i) +begin + if (update_dr_i) + write_cycle <= #1 1'b0; + else if (cmd_write & go_prelim) + write_cycle <= #1 1'b1; +end + + +// Start wishbone write cycle +always @ (posedge tck_i) +begin + if (write_cycle) + begin + case (rw_type) // synthesis parallel_case full_case + `WB_WRITE8 : begin + if (byte_q & (~byte_q2)) + begin + start_wr_tck <= #1 1'b1; + wb_dat_o <= #1 {4{dr[7:0]}}; + end + else + begin + start_wr_tck <= #1 1'b0; + end + end + `WB_WRITE16 : begin + if (half_q & (~half_q2)) + begin + start_wr_tck <= #1 1'b1; + wb_dat_o <= #1 {2{dr[15:0]}}; + end + else + begin + start_wr_tck <= #1 1'b0; + end + end + `WB_WRITE32 : begin + if (long_q & (~long_q2)) + begin + start_wr_tck <= #1 1'b1; + wb_dat_o <= #1 dr[31:0]; + end + else + begin + start_wr_tck <= #1 1'b0; + end + end + endcase + end + else + start_wr_tck <= #1 1'b0; +end + + +always @ (posedge wb_clk_i) +begin + start_rd_sync1 <= #1 start_rd_tck; + start_wb_rd <= #1 start_rd_sync1; + start_wb_rd_q <= #1 start_wb_rd; + + start_wr_sync1 <= #1 start_wr_tck; + start_wb_wr <= #1 start_wr_sync1; + start_wb_wr_q <= #1 start_wb_wr; + + set_addr_sync <= #1 set_addr; + set_addr_wb <= #1 set_addr_sync; + set_addr_wb_q <= #1 set_addr_wb; +end + + +// wb_cyc_o +always @ (posedge wb_clk_i or posedge rst_i) +begin + if (rst_i) + wb_cyc_o <= #1 1'b0; + else if ((start_wb_wr & (~start_wb_wr_q)) | (start_wb_rd & (~start_wb_rd_q))) + wb_cyc_o <= #1 1'b1; + else if (wb_ack_i | wb_err_i) + wb_cyc_o <= #1 1'b0; +end + + +// wb_adr_o logic +always @ (posedge wb_clk_i) +begin + if (set_addr_wb & (~set_addr_wb_q)) // Setting starting address + wb_adr_o <= #1 adr; + else if (wb_ack_i) + begin + if ((rw_type == `WB_WRITE8) | (rw_type == `WB_READ8)) + wb_adr_o <= #1 wb_adr_o + 1'd1; + else if ((rw_type == `WB_WRITE16) | (rw_type == `WB_READ16)) + wb_adr_o <= #1 wb_adr_o + 2'd2; + else + wb_adr_o <= #1 wb_adr_o + 3'd4; + end +end + + + +// adr byte | short | long +// 0 1000 1100 1111 +// 1 0100 err err +// 2 0010 0011 err +// 3 0001 err err +// wb_sel_o logic +always @ (posedge wb_clk_i or posedge rst_i) +begin + if (rst_i) + wb_sel_o[3:0] <= #1 4'h0; + else + begin + wb_sel_o[0] <= #1 (rw_type[1:0] == 2'b11) & (wb_adr_o[1:0] == 2'b00) | (rw_type[1:0] == 2'b01) & (wb_adr_o[1:0] == 2'b11) | + (rw_type[1:0] == 2'b10) & (wb_adr_o[1:0] == 2'b10); + wb_sel_o[1] <= #1 (rw_type[1:0] == 2'b11) & (wb_adr_o[1:0] == 2'b00) | (rw_type[1] ^ rw_type[0]) & (wb_adr_o[1:0] == 2'b10); + wb_sel_o[2] <= #1 (rw_type[1]) & (wb_adr_o[1:0] == 2'b00) | (rw_type[1:0] == 2'b01) & (wb_adr_o[1:0] == 2'b01); + wb_sel_o[3] <= #1 (wb_adr_o[1:0] == 2'b00); + end +end + + +assign wb_we_o = write_cycle; +assign wb_cab_o = 1'b0; +assign wb_stb_o = wb_cyc_o; +assign wb_cti_o = 3'h0; // always performing single access +assign wb_bte_o = 2'h0; // always performing single access + + +// Logic for detecting end of transaction +always @ (posedge wb_clk_i or posedge rst_i) +begin + if (rst_i) + wb_end <= #1 1'b0; + else if (wb_ack_i | wb_err_i) + wb_end <= #1 1'b1; + else if (wb_end_rst) + wb_end <= #1 1'b0; +end + + +always @ (posedge tck_i or posedge rst_i) +begin + if (rst_i) + begin + wb_end_sync <= #1 1'b0; + wb_end_tck <= #1 1'b0; + wb_end_tck_q<= #1 1'b0; + end + else + begin + wb_end_sync <= #1 wb_end; + wb_end_tck <= #1 wb_end_sync; + wb_end_tck_q<= #1 wb_end_tck; + end +end + + +always @ (posedge wb_clk_i or posedge rst_i) +begin + if (rst_i) + busy_wb <= #1 1'b0; + else if (wb_end_rst) + busy_wb <= #1 1'b0; + else if (wb_cyc_o) + busy_wb <= #1 1'b1; +end + + +always @ (posedge tck_i or posedge rst_i) +begin + if (rst_i) + begin + busy_sync <= #1 1'b0; + busy_tck <= #1 1'b0; + end + else + begin + busy_sync <= #1 busy_wb; + busy_tck <= #1 busy_sync; + end +end + + +always @ (posedge wb_clk_i) +begin + wb_end_rst_sync <= #1 wb_end_tck; + wb_end_rst <= #1 wb_end_rst_sync; +end + + +// Detecting WB error +always @ (posedge wb_clk_i or posedge rst_i) +begin + if (rst_i) + wb_error <= #1 1'b0; + else if(wb_err_i) + wb_error <= #1 1'b1; + else if(wb_ack_i & status_reset_en) // error remains active until STATUS read is performed + wb_error <= #1 1'b0; +end + + +always @ (posedge tck_i) +begin + wb_error_sync <= #1 wb_error; + wb_error_tck <= #1 wb_error_sync; +end + + +// Detecting overrun when write operation. +always @ (posedge wb_clk_i or posedge rst_i) +begin + if (rst_i) + wb_overrun <= #1 1'b0; + else if(start_wb_wr & (~start_wb_wr_q) & wb_cyc_o) + wb_overrun <= #1 1'b1; + else if((wb_ack_i | wb_err_i) & status_reset_en) // error remains active until STATUS read is performed + wb_overrun <= #1 1'b0; +end + +always @ (posedge tck_i) +begin + wb_overrun_sync <= #1 wb_overrun; + wb_overrun_tck <= #1 wb_overrun_sync; +end + + +// Detecting underrun when read operation +always @ (posedge tck_i or posedge rst_i) +begin + if (rst_i) + underrun_tck <= #1 1'b0; + else if(latch_data & fifo_empty & (~data_cnt_end)) + underrun_tck <= #1 1'b1; + else if(read_cycle & status_reset_en) // error remains active until STATUS read is performed + underrun_tck <= #1 1'b0; +end + + + +// wb_error is locked until WB_STATUS is performed +always @ (posedge tck_i or posedge rst_i) +begin + if (rst_i) + status_reset_en <= 1'b0; + else if((cmd_old == `WB_STATUS) & (cmd !== `WB_STATUS)) + status_reset_en <= #1 1'b1; + else + status_reset_en <= #1 1'b0; +end + + +always @ (posedge wb_clk_i) +begin + wishbone_ce_sync <= #1 wishbone_ce_i; + wishbone_ce_rst <= #1 ~wishbone_ce_sync; +end + + +// Logic for latching data that is read from wishbone +always @ (posedge wb_clk_i) +begin + if(wishbone_ce_rst) + mem_ptr <= #1 'h0; + else if (wb_ack_i) + begin + if (rw_type == `WB_READ8) + mem_ptr <= #1 mem_ptr + 1'd1; + else if (rw_type == `WB_READ16) + mem_ptr <= #1 mem_ptr + 2'd2; + end +end + + +// Logic for latching data that is read from wishbone +always @ (posedge wb_clk_i) +begin + if (wb_ack_i) + begin + case (wb_sel_o) // synthesis parallel_case full_case + 4'b1000 : mem[mem_ptr[1:0]] <= #1 wb_dat_i[31:24]; // byte + 4'b0100 : mem[mem_ptr[1:0]] <= #1 wb_dat_i[23:16]; // byte + 4'b0010 : mem[mem_ptr[1:0]] <= #1 wb_dat_i[15:08]; // byte + 4'b0001 : mem[mem_ptr[1:0]] <= #1 wb_dat_i[07:00]; // byte + + 4'b1100 : // half + begin + mem[mem_ptr[1:0]] <= #1 wb_dat_i[31:24]; + mem[mem_ptr[1:0]+1'b1] <= #1 wb_dat_i[23:16]; + end + 4'b0011 : // half + begin + mem[mem_ptr[1:0]] <= #1 wb_dat_i[15:08]; + mem[mem_ptr[1:0]+1'b1] <= #1 wb_dat_i[07:00]; + end + 4'b1111 : // long + begin + mem[0] <= #1 wb_dat_i[31:24]; + mem[1] <= #1 wb_dat_i[23:16]; + mem[2] <= #1 wb_dat_i[15:08]; + mem[3] <= #1 wb_dat_i[07:00]; + end + endcase + end +end + + +assign input_data = {mem[0], mem[1], mem[2], mem[3]}; + + +// Fifo counter and empty/full detection +always @ (posedge tck_i) +begin + if (update_dr_i) + fifo_cnt <= #1 'h0; + else if (wb_end_tck & (~wb_end_tck_q) & (~latch_data)) // incrementing + begin + case (rw_type) // synthesis parallel_case full_case + `WB_READ8 : fifo_cnt <= #1 fifo_cnt + 1'd1; + `WB_READ16: fifo_cnt <= #1 fifo_cnt + 2'd2; + `WB_READ32: fifo_cnt <= #1 fifo_cnt + 3'd4; + endcase + end + else if (~(wb_end_tck & (~wb_end_tck_q)) & latch_data) // decrementing + begin + case (rw_type) // synthesis parallel_case full_case + `WB_READ8 : fifo_cnt <= #1 fifo_cnt - 1'd1; + `WB_READ16: fifo_cnt <= #1 fifo_cnt - 2'd2; + `WB_READ32: fifo_cnt <= #1 fifo_cnt - 3'd4; + endcase + end +end + + +assign fifo_full = fifo_cnt == 3'h4; +assign fifo_empty = fifo_cnt == 3'h0; + + + + +endmodule +
tags/rel_13/rtl/verilog/dbg_wb.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/rel_13/rtl/verilog/dbg_top.v =================================================================== --- tags/rel_13/rtl/verilog/dbg_top.v (nonexistent) +++ tags/rel_13/rtl/verilog/dbg_top.v (revision 105) @@ -0,0 +1,625 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// dbg_top.v //// +//// //// +//// //// +//// This file is part of the SoC/OpenRISC Development Interface //// +//// http://www.opencores.org/projects/DebugInterface/ //// +//// //// +//// Author(s): //// +//// Igor Mohor (igorm@opencores.org) //// +//// //// +//// //// +//// All additional information is avaliable in the README.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 - 2003 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.36 2004/01/16 14:51:33 mohor +// cpu registers added. +// +// Revision 1.35 2004/01/14 22:59:16 mohor +// Temp version. +// +// Revision 1.34 2003/12/23 15:07:34 mohor +// New directory structure. New version of the debug interface. +// Files that are not needed removed. +// +// Revision 1.33 2003/10/23 16:17:01 mohor +// CRC logic changed. +// +// Revision 1.32 2003/09/18 14:00:47 simons +// Lower two address lines must be always zero. +// +// Revision 1.31 2003/09/17 14:38:57 simons +// WB_CNTL register added, some syncronization fixes. +// +// Revision 1.30 2003/08/28 13:55:22 simons +// Three more chains added for cpu debug access. +// +// Revision 1.29 2003/07/31 12:19:49 simons +// Multiple cpu support added. +// +// Revision 1.28 2002/11/06 14:22:41 mohor +// Trst signal is not inverted here any more. Inverted on higher layer !!!. +// +// Revision 1.27 2002/10/10 02:42:55 mohor +// WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). +// Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, +// wb_cyc_o is negated. +// +// Revision 1.26 2002/05/07 14:43:59 mohor +// mon_cntl_o signals that controls monitor mux added. +// +// Revision 1.25 2002/04/22 12:54:11 mohor +// Signal names changed to lower case. +// +// Revision 1.24 2002/04/17 13:17:01 mohor +// Intentional error removed. +// +// Revision 1.23 2002/04/17 11:16:33 mohor +// A block for checking possible simulation/synthesis missmatch added. +// +// Revision 1.22 2002/03/12 10:31:53 mohor +// tap_top and dbg_top modules are put into two separate modules. tap_top +// contains only tap state machine and related logic. dbg_top contains all +// logic necessery for debugging. +// +// Revision 1.21 2002/03/08 15:28:16 mohor +// Structure changed. Hooks for jtag chain added. +// +// Revision 1.20 2002/02/06 12:23:09 mohor +// latched_jtag_ir used when muxing TDO instead of JTAG_IR. +// +// Revision 1.19 2002/02/05 13:34:51 mohor +// Stupid bug that was entered by previous update fixed. +// +// Revision 1.18 2002/02/05 12:41:01 mohor +// trst synchronization is not needed and was removed. +// +// Revision 1.17 2002/01/25 07:58:35 mohor +// IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in +// not filled-in. Tested in hw. +// +// Revision 1.16 2001/12/20 11:17:26 mohor +// TDO and TDO Enable signal are separated into two signals. +// +// Revision 1.15 2001/12/05 13:28:21 mohor +// trst signal is synchronized to wb_clk_i. +// +// Revision 1.14 2001/11/28 09:36:15 mohor +// Register length fixed. +// +// Revision 1.13 2001/11/27 13:37:43 mohor +// CRC is returned when chain selection data is transmitted. +// +// Revision 1.12 2001/11/26 10:47:09 mohor +// Crc generation is different for read or write commands. Small synthesys fixes. +// +// Revision 1.11 2001/11/14 10:10:41 mohor +// Wishbone data latched on wb_clk_i instead of risc_clk. +// +// Revision 1.10 2001/11/12 01:11:27 mohor +// Reset signals are not combined any more. +// +// Revision 1.9 2001/10/19 11:40:01 mohor +// dbg_timescale.v changed to timescale.v This is done for the simulation of +// few different cores in a single project. +// +// Revision 1.8 2001/10/17 10:39:03 mohor +// bs_chain_o added. +// +// Revision 1.7 2001/10/16 10:09:56 mohor +// Signal names changed to lowercase. +// +// +// Revision 1.6 2001/10/15 09:55:47 mohor +// Wishbone interface added, few fixes for better performance, +// hooks for boundary scan testing added. +// +// Revision 1.5 2001/09/24 14:06:42 mohor +// Changes connected to the OpenRISC access (SPR read, SPR write). +// +// Revision 1.4 2001/09/20 10:11:25 mohor +// Working version. Few bugs fixed, comments added. +// +// Revision 1.3 2001/09/19 11:55:13 mohor +// Asynchronous set/reset not used in trace any more. +// +// Revision 1.2 2001/09/18 14:13:47 mohor +// Trace fixed. Some registers changed, trace simplified. +// +// Revision 1.1.1.1 2001/09/13 13:49:19 mohor +// Initial official release. +// +// Revision 1.3 2001/06/01 22:22:35 mohor +// This is a backup. It is not a fully working version. Not for use, yet. +// +// Revision 1.2 2001/05/18 13:10:00 mohor +// Headers changed. All additional information is now avaliable in the README.txt file. +// +// Revision 1.1.1.1 2001/05/18 06:35:02 mohor +// Initial release +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "dbg_defines.v" +`include "dbg_cpu_defines.v" + +// Top module +module dbg_top( + // JTAG signals + tck_i, + tdi_i, + tdo_o, + + // TAP states + shift_dr_i, + pause_dr_i, + update_dr_i, + + // Instructions + debug_select_i, + + // WISHBONE common signals + wb_rst_i, + wb_clk_i, + + // WISHBONE master interface + wb_adr_o, + wb_dat_o, + wb_dat_i, + wb_cyc_o, + wb_stb_o, + wb_sel_o, + wb_we_o, + wb_ack_i, + wb_cab_o, + wb_err_i, + wb_cti_o, + wb_bte_o, + + // CPU signals + cpu_clk_i, + cpu_addr_o, + cpu_data_i, + cpu_data_o, + cpu_bp_i, + cpu_stall_o, + cpu_stall_all_o, + cpu_stb_o, + cpu_sel_o, + cpu_we_o, + cpu_ack_i, + cpu_rst_o + ); + + +// JTAG signals +input tck_i; +input tdi_i; +output tdo_o; + +// TAP states +input shift_dr_i; +input pause_dr_i; +input update_dr_i; + +// Instructions +input debug_select_i; + +// WISHBONE common signals +input wb_rst_i; // WISHBONE reset +input wb_clk_i; // WISHBONE clock + +// WISHBONE master interface +output [31:0] wb_adr_o; +output [31:0] wb_dat_o; +input [31:0] wb_dat_i; +output wb_cyc_o; +output wb_stb_o; +output [3:0] wb_sel_o; +output wb_we_o; +input wb_ack_i; +output wb_cab_o; +input wb_err_i; +output [2:0] wb_cti_o; +output [1:0] wb_bte_o; + +// CPU signals +input cpu_clk_i; +output [31:0] cpu_addr_o; +input [31:0] cpu_data_i; +output [31:0] cpu_data_o; +input cpu_bp_i; +output cpu_stall_o; +output cpu_stall_all_o; +output cpu_stb_o; +output [`CPU_NUM -1:0] cpu_sel_o; +output cpu_we_o; +input cpu_ack_i; +output cpu_rst_o; + +reg cpu_debug_scan_chain; +reg wishbone_scan_chain; + +reg [`DATA_CNT -1:0] data_cnt; +reg [`CRC_CNT -1:0] crc_cnt; +reg [`STATUS_CNT -1:0] status_cnt; +reg [`CHAIN_DATA_LEN -1:0] chain_dr; +reg [`CHAIN_ID_LENGTH -1:0] chain; + +wire chain_latch_en; +wire data_cnt_end; +wire crc_cnt_end; +wire status_cnt_end; +reg crc_cnt_end_q; +reg crc_cnt_end_q2; +reg crc_cnt_end_q3; +reg chain_select; +reg chain_select_error; +wire crc_out; +wire crc_match; +wire crc_en_wb; +wire crc_en_cpu; +wire shift_crc_wb; +wire shift_crc_cpu; + +wire data_shift_en; +wire selecting_command; + +reg tdo_o; +reg wishbone_ce; +reg cpu_ce; + +wire tdi_wb; +wire tdi_cpu; + +wire tdo_wb; +wire tdo_cpu; + +wire shift_crc; + +// data counter +always @ (posedge tck_i or posedge wb_rst_i) +begin + if (wb_rst_i) + data_cnt <= #1 'h0; + else if(shift_dr_i & (~data_cnt_end)) + data_cnt <= #1 data_cnt + 1'b1; + else if (update_dr_i) + data_cnt <= #1 'h0; +end + + +assign data_cnt_end = data_cnt == `CHAIN_DATA_LEN; + + +// crc counter +always @ (posedge tck_i or posedge wb_rst_i) +begin + if (wb_rst_i) + crc_cnt <= #1 'h0; + else if(shift_dr_i & data_cnt_end & (~crc_cnt_end) & chain_select) + crc_cnt <= #1 crc_cnt + 1'b1; + else if (update_dr_i) + crc_cnt <= #1 'h0; +end + +assign crc_cnt_end = crc_cnt == `CRC_LEN; + + +always @ (posedge tck_i) + begin + crc_cnt_end_q <= #1 crc_cnt_end; + crc_cnt_end_q2 <= #1 crc_cnt_end_q; + crc_cnt_end_q3 <= #1 crc_cnt_end_q2; + end + + +// status counter +always @ (posedge tck_i or posedge wb_rst_i) +begin + if (wb_rst_i) + status_cnt <= #1 'h0; + else if(shift_dr_i & crc_cnt_end & (~status_cnt_end)) + status_cnt <= #1 status_cnt + 1'b1; + else if (update_dr_i) + status_cnt <= #1 'h0; +end + +assign status_cnt_end = status_cnt == `STATUS_LEN; + + +assign selecting_command = shift_dr_i & (data_cnt == `DATA_CNT'h0) & debug_select_i; + + +always @ (posedge tck_i or posedge wb_rst_i) +begin + if (wb_rst_i) + chain_select <= #1 1'b0; + else if(selecting_command & tdi_i) // Chain select + chain_select <= #1 1'b1; + else if (update_dr_i) + chain_select <= #1 1'b0; +end + + +always @ (chain) +begin + cpu_debug_scan_chain <= #1 1'b0; + wishbone_scan_chain <= #1 1'b0; + chain_select_error <= #1 1'b0; + + case (chain) /* synthesis parallel_case */ + `CPU_DEBUG_CHAIN : cpu_debug_scan_chain <= #1 1'b1; + `WISHBONE_SCAN_CHAIN : wishbone_scan_chain <= #1 1'b1; + default : chain_select_error <= #1 1'b1; + endcase +end + + +assign chain_latch_en = chain_select & crc_cnt_end & (~crc_cnt_end_q); + + +always @ (posedge tck_i or posedge wb_rst_i) +begin + if (wb_rst_i) + chain <= `CHAIN_ID_LENGTH'b111; + else if(chain_latch_en & crc_match) + chain <= #1 chain_dr[`CHAIN_DATA_LEN -1:1]; +end + + +assign data_shift_en = shift_dr_i & (~data_cnt_end); + + +always @ (posedge tck_i) +begin + if (data_shift_en) + chain_dr[`CHAIN_DATA_LEN -1:0] <= #1 {tdi_i, chain_dr[`CHAIN_DATA_LEN -1:1]}; +end + + +// Calculating crc for input data +dbg_crc32_d1 i_dbg_crc32_d1_in + ( + .data (tdi_i), + .enable (shift_dr_i), + .shift (1'b0), + .rst (wb_rst_i), + .sync_rst (update_dr_i), + .crc_out (), + .clk (tck_i), + .crc_match (crc_match) + ); + + +reg tdo_chain_select; +wire crc_en; +wire crc_en_dbg; +reg crc_started; +assign crc_en = crc_en_dbg | crc_en_wb | crc_en_cpu; +assign crc_en_dbg = shift_dr_i & crc_cnt_end & (~status_cnt_end); + +always @ (posedge tck_i) +begin + if (crc_en) + crc_started <= #1 1'b1; + else if (update_dr_i) + crc_started <= #1 1'b0; +end + + +reg tdo_tmp; + + +// Calculating crc for input data +dbg_crc32_d1 i_dbg_crc32_d1_out + ( + .data (tdo_tmp), + .enable (crc_en), // enable has priority +// .shift (1'b0), + .shift (shift_dr_i & crc_started & (~crc_en)), + .rst (wb_rst_i), + .sync_rst (update_dr_i), + .crc_out (crc_out), + .clk (tck_i), + .crc_match () + ); + +// Following status is shifted out: +// 1. bit: 1 if crc is OK, else 0 +// 2. bit: 1 if command is "chain select", else 0 +// 3. bit: 1 if non-existing chain is selected else 0 +// 4. bit: always 1 + +reg [799:0] current_on_tdo; + +always @ (status_cnt or chain_select or crc_match or chain_select_error or crc_out) +begin + case (status_cnt) /* synthesis full_case parallel_case */ + `STATUS_CNT'd0 : begin + tdo_chain_select = crc_match; + current_on_tdo = "crc_match"; + end + `STATUS_CNT'd1 : begin + tdo_chain_select = chain_select; + current_on_tdo = "chain_select"; + end + `STATUS_CNT'd2 : begin + tdo_chain_select = chain_select_error; + current_on_tdo = "chain_select_error"; + end + `STATUS_CNT'd3 : begin + tdo_chain_select = 1'b1; + current_on_tdo = "one 1"; + end + `STATUS_CNT'd4 : begin + tdo_chain_select = crc_out; + // tdo_chain_select = 1'hz; + current_on_tdo = "crc_out"; + end + endcase +end + + + + +assign shift_crc = shift_crc_wb | shift_crc_cpu; + +always @ (shift_crc or crc_out or wishbone_ce or tdo_wb or tdo_cpu or tdo_chain_select) +begin + if (shift_crc) // shifting crc + tdo_tmp = crc_out; + else if (wishbone_ce) // shifting data from wb + tdo_tmp = tdo_wb; + else if (cpu_ce) // shifting data from cpu + tdo_tmp = tdo_cpu; + else + tdo_tmp = tdo_chain_select; +end + + +always @ (negedge tck_i) +begin + tdo_o <= #1 tdo_tmp; +end + + + + +// Signals for WISHBONE module + + +always @ (posedge tck_i or posedge wb_rst_i) +begin + if (wb_rst_i) + begin + wishbone_ce <= #1 1'b0; + cpu_ce <= #1 1'b0; + end + else if(selecting_command & (~tdi_i)) + begin + if (wishbone_scan_chain) // wishbone CE + wishbone_ce <= #1 1'b1; + if (cpu_debug_scan_chain) // CPU CE + cpu_ce <= #1 1'b1; + end + else if (update_dr_i) // igor !!! This needs to be changed? + begin + wishbone_ce <= #1 1'b0; + cpu_ce <= #1 1'b0; + end +end + + +assign tdi_wb = wishbone_ce & tdi_i; +assign tdi_cpu = cpu_ce & tdi_i; + + +// Connecting wishbone module +dbg_wb i_dbg_wb ( + // JTAG signals + .tck_i (tck_i), + .tdi_i (tdi_wb), + .tdo_o (tdo_wb), + + // TAP states + .shift_dr_i (shift_dr_i), + .pause_dr_i (pause_dr_i), + .update_dr_i (update_dr_i), + + .wishbone_ce_i (wishbone_ce), + .crc_match_i (crc_match), + .crc_en_o (crc_en_wb), + .shift_crc_o (shift_crc_wb), + .rst_i (wb_rst_i), + + // WISHBONE common signals + .wb_clk_i (wb_clk_i), + + // WISHBONE master interface + .wb_adr_o (wb_adr_o), + .wb_dat_o (wb_dat_o), + .wb_dat_i (wb_dat_i), + .wb_cyc_o (wb_cyc_o), + .wb_stb_o (wb_stb_o), + .wb_sel_o (wb_sel_o), + .wb_we_o (wb_we_o), + .wb_ack_i (wb_ack_i), + .wb_cab_o (wb_cab_o), + .wb_err_i (wb_err_i), + .wb_cti_o (wb_cti_o), + .wb_bte_o (wb_bte_o) + ); + + +// Connecting cpu module +dbg_cpu i_dbg_cpu ( + // JTAG signals + .tck_i (tck_i), + .tdi_i (tdi_cpu), + .tdo_o (tdo_cpu), + + // TAP states + .shift_dr_i (shift_dr_i), + .pause_dr_i (pause_dr_i), + .update_dr_i (update_dr_i), + + .cpu_ce_i (cpu_ce), + .crc_match_i (crc_match), + .crc_en_o (crc_en_cpu), + .shift_crc_o (shift_crc_cpu), + .rst_i (wb_rst_i), + + // CPU signals + .cpu_clk_i (cpu_clk_i), + .cpu_addr_o (cpu_addr_o), + .cpu_data_i (cpu_data_i), + .cpu_data_o (cpu_data_o), + .cpu_bp_i (cpu_bp_i), + .cpu_stall_o (cpu_stall_o), + .cpu_stall_all_o (cpu_stall_all_o), + .cpu_stb_o (cpu_stb_o), + .cpu_sel_o (cpu_sel_o), + .cpu_we_o (cpu_we_o), + .cpu_ack_i (cpu_ack_i), + .cpu_rst_o (cpu_rst_o) + + + ); + + +endmodule Index: tags/rel_13/rtl/verilog/dbg_cpu_defines.v =================================================================== --- tags/rel_13/rtl/verilog/dbg_cpu_defines.v (nonexistent) +++ tags/rel_13/rtl/verilog/dbg_cpu_defines.v (revision 105) @@ -0,0 +1,75 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// dbg_cpu_defines.v //// +//// //// +//// //// +//// This file is part of the SoC/OpenRISC Development Interface //// +//// http://www.opencores.org/projects/DebugInterface/ //// +//// //// +//// Author(s): //// +//// Igor Mohor (igorm@opencores.org) //// +//// //// +//// //// +//// All additional information is avaliable in the README.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 - 2004 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.1 2004/01/16 14:53:33 mohor +// *** empty log message *** +// +// +// + + +// Defining commands for cpu module +//`define CPU_STATUS 3'h0 +`define CPU_WRITE8 3'h1 +`define CPU_WRITE32 3'h2 +`define CPU_WRITE_REG 3'h3 +`define CPU_GO 3'h4 +`define CPU_READ8 3'h5 +`define CPU_READ32 3'h6 +`define CPU_READ_REG 3'h7 + + + + + +// Number of supported cpus +`define CPU_NUM 2 + + +// Registers addresses +`define CPU_OP_ADR 2'd0 +`define CPU_SEL_ADR 2'd1 + +
tags/rel_13/rtl/verilog/dbg_cpu_defines.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/rel_13/rtl/verilog/dbg_cpu_registers.v =================================================================== --- tags/rel_13/rtl/verilog/dbg_cpu_registers.v (nonexistent) +++ tags/rel_13/rtl/verilog/dbg_cpu_registers.v (revision 105) @@ -0,0 +1,174 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// dbg_cpu_registers.v //// +//// //// +//// //// +//// This file is part of the SoC/OpenRISC Development Interface //// +//// http://www.opencores.org/projects/DebugInterface/ //// +//// //// +//// Author(s): //// +//// Igor Mohor (igorm@opencores.org) //// +//// //// +//// //// +//// All additional information is avaliable in the README.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 - 2004 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.1 2004/01/16 14:53:33 mohor +// *** empty log message *** +// +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "dbg_cpu_defines.v" + +module dbg_cpu_registers ( + data_i, + data_o, + addr_i, + we_i, + en_i, + clk_i, + bp_i, + rst_i, + cpu_clk_i, + cpu_stall_o, + cpu_stall_all_o, + cpu_sel_o, + cpu_rst_o + ); + + +input [7:0] data_i; +input [1:0] addr_i; + +input we_i; +input en_i; +input clk_i; +input bp_i; +input rst_i; +input cpu_clk_i; + +output [7:0] data_o; +reg [7:0] data_o; + +output cpu_stall_o; +output cpu_stall_all_o; +output [`CPU_NUM -1:0] cpu_sel_o; +output cpu_rst_o; + +wire cpu_stall; +wire cpu_stall_all; +wire cpu_reset; +wire [2:1] cpu_op_out; +wire [`CPU_NUM -1:0] cpu_sel_out; + +wire cpuop_wr; +wire cpusel_wr; + +reg cpusel_wr_sync; +reg cpusel_wr_cpu; +reg cpu_stall_bp; +reg cpu_stall_sync; +reg cpu_stall_o; +reg cpu_stall_all_sync; +reg cpu_stall_all_o; +reg cpu_reset_sync; +reg cpu_rst_o; + + + + +assign cpuop_wr = en_i & we_i & (addr_i == `CPU_OP_ADR); +assign cpusel_wr = en_i & we_i & (addr_i == `CPU_SEL_ADR); + + +// Synchronising we for cpu_sel register that works in cpu_clk clock domain +always @ (posedge cpu_clk_i) +begin + cpusel_wr_sync <= #1 cpusel_wr; + cpusel_wr_cpu <= #1 cpusel_wr_sync; +end + + + +always @(posedge clk_i or posedge rst_i) +begin + if(rst_i) + cpu_stall_bp <= 1'b0; + else if(bp_i) // Breakpoint sets bit + cpu_stall_bp <= 1'b1; + else if(cpuop_wr) // Register access can set or clear bit + cpu_stall_bp <= data_i[0]; +end + + +dbg_register #(2, 0) CPUOP (.data_in(data_i[2:1]), .data_out(cpu_op_out[2:1]), .write(cpuop_wr), .clk(clk_i), .reset(rst_i)); +dbg_register #(`CPU_NUM, 0) CPUSEL (.data_in(data_i[`CPU_NUM-1:0]), .data_out(cpu_sel_out), .write(cpusel_wr_cpu), .clk(cpu_clk_i), .reset(rst_i)); // cpu_cli_i + + +always @ (posedge clk_i) +begin + case (addr_i) // Synthesis parallel_case + `CPU_OP_ADR : data_o <= #1 {5'h0, cpu_op_out[2:1], cpu_stall}; + `CPU_SEL_ADR : data_o <= #1 {{(8-`CPU_NUM){1'b0}}, cpu_sel_out}; + default : data_o <= #1 8'h0; + endcase +end + + +assign cpu_stall = bp_i | cpu_stall_bp; // bp asynchronously sets the cpu_stall, then cpu_stall_bp (from register) holds it active +assign cpu_stall_all = cpu_op_out[2]; // this signal is used to stall all the cpus except the one that is selected in cpusel register +assign cpu_sel_o = cpu_sel_out; +assign cpu_reset = cpu_op_out[1]; + + + + +// Synchronizing signals from registers +always @ (posedge cpu_clk_i) +begin + cpu_stall_sync <= #1 cpu_stall; + cpu_stall_o <= #1 cpu_stall_sync; + cpu_stall_all_sync <= #1 cpu_stall_all; + cpu_stall_all_o <= #1 cpu_stall_all_sync; + cpu_reset_sync <= #1 cpu_reset; + cpu_rst_o <= #1 cpu_reset_sync; +end + + + +endmodule + Index: tags/rel_13/rtl/verilog/dbg_register.v =================================================================== --- tags/rel_13/rtl/verilog/dbg_register.v (nonexistent) +++ tags/rel_13/rtl/verilog/dbg_register.v (revision 105) @@ -0,0 +1,87 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// dbg_register.v //// +//// //// +//// //// +//// This file is part of the SoC/OpenRISC Development Interface //// +//// http://www.opencores.org/projects/DebugInterface/ //// +//// //// +//// Author(s): //// +//// Igor Mohor (igorm@opencores.org) //// +//// //// +//// //// +//// All additional information is avaliable in the README.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 - 2004 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on + +module dbg_register ( + data_in, + data_out, + write, + clk, + reset + ); + + +parameter WIDTH = 8; // default parameter of the register width +parameter RESET_VALUE = 0; + + +input [WIDTH-1:0] data_in; +input write; +input clk; +input reset; + +output [WIDTH-1:0] data_out; +reg [WIDTH-1:0] data_out; + + + +always @ (posedge clk or posedge reset) +//always @ (posedge clk) +begin + if(reset) + data_out[WIDTH-1:0] <= #1 RESET_VALUE; + else if(write) + data_out[WIDTH-1:0] <= #1 data_in[WIDTH-1:0]; +end + + +endmodule // Register + Index: tags/rel_13/rtl/verilog/dbg_wb_defines.v =================================================================== --- tags/rel_13/rtl/verilog/dbg_wb_defines.v (nonexistent) +++ tags/rel_13/rtl/verilog/dbg_wb_defines.v (revision 105) @@ -0,0 +1,72 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// dbg_wb_defines.v //// +//// //// +//// //// +//// This file is part of the SoC/OpenRISC Development Interface //// +//// http://www.opencores.org/projects/DebugInterface/ //// +//// //// +//// Author(s): //// +//// Igor Mohor (igorm@opencores.org) //// +//// //// +//// //// +//// All additional information is avaliable in the README.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 - 2003 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.3 2004/01/08 17:53:36 mohor +// tmp version. +// +// Revision 1.2 2004/01/06 17:15:19 mohor +// temp3 version. +// +// Revision 1.1 2003/12/23 15:09:04 mohor +// New directory structure. New version of the debug interface. +// +// +// + + +// Defining commands for wishbone +`define WB_STATUS 3'h0 +`define WB_WRITE8 3'h1 +`define WB_WRITE16 3'h2 +`define WB_WRITE32 3'h3 +`define WB_GO 3'h4 +`define WB_READ8 3'h5 +`define WB_READ16 3'h6 +`define WB_READ32 3'h7 + + +// Length of status +`define STATUS_LEN 4 +
tags/rel_13/rtl/verilog/dbg_wb_defines.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/rel_13/rtl/verilog/dbg_crc32_d1.v =================================================================== --- tags/rel_13/rtl/verilog/dbg_crc32_d1.v (nonexistent) +++ tags/rel_13/rtl/verilog/dbg_crc32_d1.v (revision 105) @@ -0,0 +1,145 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// dbg_crc32_d1.v //// +//// //// +//// //// +//// This file is part of the SoC/OpenRISC Development Interface //// +//// http://www.opencores.org/projects/DebugInterface/ //// +//// //// +//// Author(s): //// +//// Igor Mohor (igorm@opencores.org) //// +//// //// +//// //// +//// All additional information is avaliable in the README.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 - 2003 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// File: CRC32_D1.v +// Date: Thu Nov 27 13:56:49 2003 +// +// Copyright (C) 1999-2003 Easics NV. +// This source file may be used and distributed without restriction +// provided that this copyright statement is not removed from the file +// and that any derivative work contains the original copyright notice +// and the associated disclaimer. +// +// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS +// OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED +// WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. +// +// Purpose: Verilog module containing a synthesizable CRC function +// * polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32) +// * data width: 1 +// +// Info: janz@easics.be (Jan Zegers) +// http://www.easics.com +/////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.1 2003/12/23 15:09:04 mohor +// New directory structure. New version of the debug interface. +// +// +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on + +module dbg_crc32_d1 (data, enable, shift, rst, sync_rst, crc_out, clk, crc_match); + +input data; +input enable; +input shift; +input rst; +input sync_rst; +input clk; + + +output crc_out; +output crc_match; + +reg [31:0] crc; + +wire [31:0] new_crc; + + +assign new_crc[0] = data ^ crc[31]; +assign new_crc[1] = data ^ crc[0] ^ crc[31]; +assign new_crc[2] = data ^ crc[1] ^ crc[31]; +assign new_crc[3] = crc[2]; +assign new_crc[4] = data ^ crc[3] ^ crc[31]; +assign new_crc[5] = data ^ crc[4] ^ crc[31]; +assign new_crc[6] = crc[5]; +assign new_crc[7] = data ^ crc[6] ^ crc[31]; +assign new_crc[8] = data ^ crc[7] ^ crc[31]; +assign new_crc[9] = crc[8]; +assign new_crc[10] = data ^ crc[9] ^ crc[31]; +assign new_crc[11] = data ^ crc[10] ^ crc[31]; +assign new_crc[12] = data ^ crc[11] ^ crc[31]; +assign new_crc[13] = crc[12]; +assign new_crc[14] = crc[13]; +assign new_crc[15] = crc[14]; +assign new_crc[16] = data ^ crc[15] ^ crc[31]; +assign new_crc[17] = crc[16]; +assign new_crc[18] = crc[17]; +assign new_crc[19] = crc[18]; +assign new_crc[20] = crc[19]; +assign new_crc[21] = crc[20]; +assign new_crc[22] = data ^ crc[21] ^ crc[31]; +assign new_crc[23] = data ^ crc[22] ^ crc[31]; +assign new_crc[24] = crc[23]; +assign new_crc[25] = crc[24]; +assign new_crc[26] = data ^ crc[25] ^ crc[31]; +assign new_crc[27] = crc[26]; +assign new_crc[28] = crc[27]; +assign new_crc[29] = crc[28]; +assign new_crc[30] = crc[29]; +assign new_crc[31] = crc[30]; + + +always @ (posedge clk or posedge rst) +begin + if(rst) + crc[31:0] <= #1 32'hffffffff; + else if(sync_rst) + crc[31:0] <= #1 32'hffffffff; + else if(enable) + crc[31:0] <= #1 new_crc; + else if (shift) + crc[31:0] <= #1 {crc[30:0], 1'b0}; +end + + +assign crc_match = (crc == 32'h0); +assign crc_out = crc[31]; + +endmodule
tags/rel_13/rtl/verilog/dbg_crc32_d1.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/rel_13/rtl/verilog/dbg_defines.v =================================================================== --- tags/rel_13/rtl/verilog/dbg_defines.v (nonexistent) +++ tags/rel_13/rtl/verilog/dbg_defines.v (revision 105) @@ -0,0 +1,120 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// dbg_defines.v //// +//// //// +//// //// +//// This file is part of the SoC/OpenRISC Development Interface //// +//// http://www.opencores.org/projects/DebugInterface/ //// +//// //// +//// Author(s): //// +//// Igor Mohor (igorm@opencores.org) //// +//// //// +//// //// +//// All additional information is avaliable in the README.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 - 2003 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.14 2003/10/23 16:17:00 mohor +// CRC logic changed. +// +// Revision 1.13 2003/10/21 09:48:31 simons +// Mbist support added. +// +// Revision 1.12 2003/09/17 14:38:57 simons +// WB_CNTL register added, some syncronization fixes. +// +// Revision 1.11 2003/08/28 13:55:21 simons +// Three more chains added for cpu debug access. +// +// Revision 1.10 2003/07/31 12:19:49 simons +// Multiple cpu support added. +// +// Revision 1.9 2002/05/07 14:43:59 mohor +// mon_cntl_o signals that controls monitor mux added. +// +// Revision 1.8 2002/01/25 07:58:34 mohor +// IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in +// not filled-in. Tested in hw. +// +// Revision 1.7 2001/12/06 10:08:06 mohor +// Warnings from synthesys tools fixed. +// +// Revision 1.6 2001/11/28 09:38:30 mohor +// Trace disabled by default. +// +// Revision 1.5 2001/10/15 09:55:47 mohor +// Wishbone interface added, few fixes for better performance, +// hooks for boundary scan testing added. +// +// Revision 1.4 2001/09/24 14:06:42 mohor +// Changes connected to the OpenRISC access (SPR read, SPR write). +// +// Revision 1.3 2001/09/20 10:11:25 mohor +// Working version. Few bugs fixed, comments added. +// +// Revision 1.2 2001/09/18 14:13:47 mohor +// Trace fixed. Some registers changed, trace simplified. +// +// Revision 1.1.1.1 2001/09/13 13:49:19 mohor +// Initial official release. +// +// Revision 1.3 2001/06/01 22:22:35 mohor +// This is a backup. It is not a fully working version. Not for use, yet. +// +// Revision 1.2 2001/05/18 13:10:00 mohor +// Headers changed. All additional information is now avaliable in the README.txt file. +// +// Revision 1.1.1.1 2001/05/18 06:35:08 mohor +// Initial release +// +// + + +// Length of the CHAIN ID register +`define CHAIN_ID_LENGTH 3 + +// Length of data +`define CHAIN_DATA_LEN `CHAIN_ID_LENGTH + 1 +`define DATA_CNT 3 + +// Length of status +`define STATUS_LEN 4 +`define STATUS_CNT 3 + +// Length of the CRC +`define CRC_LEN 32 +`define CRC_CNT 6 + +// Chains +`define CPU_DEBUG_CHAIN 3'b000 +`define WISHBONE_SCAN_CHAIN 3'b001 + Index: tags/rel_13/rtl/verilog/jtag_chain.v =================================================================== --- tags/rel_13/rtl/verilog/jtag_chain.v (nonexistent) +++ tags/rel_13/rtl/verilog/jtag_chain.v (revision 105) @@ -0,0 +1,75 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// jtag_chain.v //// +//// //// +//// //// +//// This file is part of the SoC/OpenRISC Development Interface //// +//// http://www.opencores.org/projects/DebugInterface/ //// +//// //// +//// //// +//// Author(s): //// +//// Igor Mohor //// +//// igorm@opencores.org //// +//// //// +//// //// +//// All additional information is avaliable in the README.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000, 2001, 2002 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "dbg_defines.v" + +// Top module +module jtag_chain ( capture_dr_i, shift_dr_i, update_dr_i, extest_selected_i, + bs_chain_i, bs_chain_o + ); + +parameter Tp = 1; + + +input capture_dr_i; +input shift_dr_i; +input update_dr_i; +input extest_selected_i; +input bs_chain_i; + +output bs_chain_o; + +assign bs_chain_o = 0; + +endmodule Index: tags/rel_13/rtl/README.txt =================================================================== --- tags/rel_13/rtl/README.txt (nonexistent) +++ tags/rel_13/rtl/README.txt (revision 105) @@ -0,0 +1,114 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// README.txt //// +//// //// +//// //// +//// This file is part of the SoC/OpenRISC Development Interface //// +//// http://www.opencores.org/cores/DebugInterface/ //// +//// //// +//// //// +//// Author(s): //// +//// Igor Mohor //// +//// igorm@opencores.org //// +//// //// +//// //// +//// All additional information is avaliable in this README.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000,2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.1.1.1 2001/09/13 13:49:19 mohor +// Initial official release. +// +// Revision 1.2 2001/06/01 22:22:35 mohor +// This is a backup. It is not a fully working version. Not for use, yet. +// +// Revision 1.1 2001/05/18 13:12:09 mohor +// Header changed. All additional information is now avaliable in this README.txt file. +// +// + + + +PROJECT: +SoC/OpenRISC Development (debug) Interface + + +PROJECT AND DOCUMENTATION ON THE WEB: + +The project that this files are part of is avaliable on the opencores +web page: + +http://www.opencores.org/cores/DebugInterface/ + +Documentation can also be found there. For direct download of the +documentation go to: + +http://www.opencores.org/cgi-bin/cvsget.cgi/dbg_interface/doc/DbgSupp.pdf + + + + +OVERVIEW (main Features): + +Development Interface is used for development purposes +(Boundary Scan testing and debugging). It is an interface +between the RISC, peripheral cores and any commercial +debugger/emulator or BS testing device. The external +debugger or BS tester connects to the core via JTAG port. +The Development Port also contains a trace and support for +tracing the program flow, execution coverage and profiling +the code. + +dbg_tb.v is a testbench file. +file_communication.v is used for simulating the whole design together with the + debugger through two files that make a JTAG interface +dbg_top.v is top level module of the development interface design + + + +COMPATIBILITY: + +- WISHBONE rev B.1 +- IEEE 1149.1 (JTAG) + + + +KNOWN PROBLEMS (limits): +- RISC changes Watchpoints and breakpoints on rising edge of the +Mclk clock signal. Simulation should do the same. + + + +TO DO: +- Add a WISHBONE master support if needed +- Add support for boundary scan (This is already done, but not yet incorporated in the design) + Index: tags/rel_13/bench/verilog/dbg_tb.v =================================================================== --- tags/rel_13/bench/verilog/dbg_tb.v (nonexistent) +++ tags/rel_13/bench/verilog/dbg_tb.v (revision 105) @@ -0,0 +1,1474 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// dbg_tb.v //// +//// //// +//// //// +//// This file is part of the SoC/OpenRISC Development Interface //// +//// http://www.opencores.org/projects/DebugInterface/ //// +//// //// +//// Author(s): //// +//// Igor Mohor (igorm@opencores.org) //// +//// //// +//// //// +//// All additional information is avaliable in the README.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 - 2004 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.26 2004/01/17 17:01:25 mohor +// Almost finished. +// +// Revision 1.25 2004/01/16 14:51:24 mohor +// cpu registers added. +// +// Revision 1.24 2004/01/15 10:47:13 mohor +// Working. +// +// Revision 1.23 2004/01/14 22:59:01 mohor +// Temp version. +// +// Revision 1.22 2004/01/13 11:28:30 mohor +// tmp version. +// +// Revision 1.21 2004/01/10 07:50:41 mohor +// temp version. +// +// Revision 1.20 2004/01/09 12:49:23 mohor +// tmp version. +// +// Revision 1.19 2004/01/08 17:53:12 mohor +// tmp version. +// +// Revision 1.18 2004/01/07 11:59:48 mohor +// temp4 version. +// +// Revision 1.17 2004/01/06 17:14:59 mohor +// temp3 version. +// +// Revision 1.16 2004/01/05 12:16:50 mohor +// tmp2 version. +// +// Revision 1.15 2003/12/23 14:26:01 mohor +// New version of the debug interface. Not finished, yet. +// +// Revision 1.14 2003/10/23 16:16:30 mohor +// CRC logic changed. +// +// Revision 1.13 2003/08/28 13:54:33 simons +// Three more chains added for cpu debug access. +// +// Revision 1.12 2002/05/07 14:44:52 mohor +// mon_cntl_o signals that controls monitor mux added. +// +// Revision 1.11 2002/03/12 14:32:26 mohor +// Few outputs for boundary scan chain added. +// +// Revision 1.10 2002/03/08 15:27:08 mohor +// Structure changed. Hooks for jtag chain added. +// +// Revision 1.9 2001/10/19 11:39:20 mohor +// dbg_timescale.v changed to timescale.v This is done for the simulation of +// few different cores in a single project. +// +// Revision 1.8 2001/10/17 10:39:17 mohor +// bs_chain_o added. +// +// Revision 1.7 2001/10/16 10:10:18 mohor +// Signal names changed to lowercase. +// +// Revision 1.6 2001/10/15 09:52:50 mohor +// Wishbone interface added, few fixes for better performance, +// hooks for boundary scan testing added. +// +// Revision 1.5 2001/09/24 14:06:12 mohor +// Changes connected to the OpenRISC access (SPR read, SPR write). +// +// Revision 1.4 2001/09/20 10:10:29 mohor +// Working version. Few bugs fixed, comments added. +// +// Revision 1.3 2001/09/19 11:54:03 mohor +// Minor changes for simulation. +// +// Revision 1.2 2001/09/18 14:12:43 mohor +// Trace fixed. Some registers changed, trace simplified. +// +// Revision 1.1.1.1 2001/09/13 13:49:19 mohor +// Initial official release. +// +// Revision 1.3 2001/06/01 22:23:40 mohor +// This is a backup. It is not a fully working version. Not for use, yet. +// +// Revision 1.2 2001/05/18 13:10:05 mohor +// Headers changed. All additional information is now avaliable in the README.txt file. +// +// Revision 1.1.1.1 2001/05/18 06:35:15 mohor +// Initial release +// +// + + +`include "timescale.v" +`include "dbg_defines.v" +`include "dbg_wb_defines.v" +`include "dbg_cpu_defines.v" + +// Test bench +module dbg_tb; + +parameter TCLK = 50; // Clock half period (Clok period = 100 ns => 10 MHz) + +reg tms_pad_i; +reg tck_pad_i; +reg trst_pad_i; +reg tdi_pad_i; +wire tdo_pad_o; +wire tdo_padoe_o; + +wire shift_dr_o; +wire pause_dr_o; +wire update_dr_o; +wire capture_dr_o; + +wire extest_select_o; +wire sample_preload_select_o; +wire mbist_select_o; +wire debug_select_o; + +// WISHBONE common signals +reg wb_rst_i; +reg wb_clk_i; + +// WISHBONE master interface +wire [31:0] wb_adr_o; +wire [31:0] wb_dat_o; +wire [31:0] wb_dat_i; +wire wb_cyc_o; +wire wb_stb_o; +wire [3:0] wb_sel_o; +wire wb_we_o; +wire wb_ack_i; +wire wb_cab_o; +wire wb_err_i; +wire [2:0] wb_cti_o; +wire [1:0] wb_bte_o; + +// CPU signals +wire cpu_clk_i; +wire [31:0] cpu_addr_o; +wire [31:0] cpu_data_i; +wire [31:0] cpu_data_o; +wire cpu_bp_i; +wire cpu_stall_o; +wire cpu_stall_all_o; +wire cpu_stb_o; +wire [`CPU_NUM -1:0] cpu_sel_o; +wire cpu_we_o; +wire cpu_ack_i; +wire cpu_rst_o; + +// Text used for easier debugging +reg [199:0] test_text; +reg [2:0] last_wb_cmd; +reg [199:0] last_wb_cmd_text; +reg [31:0] wb_data; + + + +wire tdo_o; + +wire debug_tdi_i; +wire bs_chain_tdi_i; +wire mbist_tdi_i; + +reg test_enabled; + +reg [31:0] result; + +reg crc_out_en; +reg crc_out_shift; +wire crc_out; + + + +wire tdo; + +assign tdo = tdo_padoe_o? tdo_pad_o : 1'hz; + +// Connecting TAP module +tap_top i_tap_top ( + .tms_pad_i (tms_pad_i), + .tck_pad_i (tck_pad_i), + .trst_pad_i (!trst_pad_i), + .tdi_pad_i (tdi_pad_i), + .tdo_pad_o (tdo_pad_o), + .tdo_padoe_o (tdo_padoe_o), + + // TAP states + .shift_dr_o (shift_dr_o), + .pause_dr_o (pause_dr_o), + .update_dr_o (update_dr_o), + .capture_dr_o (capture_dr_o), + + // Select signals for boundary scan or mbist + .extest_select_o (extest_select_o), + .sample_preload_select_o(sample_preload_select_o), + .mbist_select_o (mbist_select_o), + .debug_select_o (debug_select_o), + + // TDO signal that is connected to TDI of sub-modules. + .tdo_o (tdo_o), + + // TDI signals from sub-modules + .debug_tdi_i (debug_tdi_i), // from debug module + .bs_chain_tdi_i (bs_chain_tdi_i), // from Boundary Scan Chain + .mbist_tdi_i (mbist_tdi_i) // from Mbist Chain + + ); + + +// Connecting debug top module +dbg_top i_dbg_top ( + .tck_i (tck_pad_i), + .tdi_i (tdo_o), + .tdo_o (debug_tdi_i), + + // TAP states + .shift_dr_i (shift_dr_o), + .pause_dr_i (pause_dr_o), + .update_dr_i (update_dr_o), + + // Instructions + .debug_select_i (debug_select_o), + + // WISHBONE common signals + .wb_rst_i (wb_rst_i), + .wb_clk_i (wb_clk_i), + + // WISHBONE master interface + .wb_adr_o (wb_adr_o), + .wb_dat_o (wb_dat_o), + .wb_dat_i (wb_dat_i), + .wb_cyc_o (wb_cyc_o), + .wb_stb_o (wb_stb_o), + .wb_sel_o (wb_sel_o), + .wb_we_o (wb_we_o), + .wb_ack_i (wb_ack_i), + .wb_cab_o (wb_cab_o), + .wb_err_i (wb_err_i), + .wb_cti_o (wb_cti_o), + .wb_bte_o (wb_bte_o), + + // CPU signals + .cpu_clk_i (cpu_clk_i), + .cpu_addr_o (cpu_addr_o), + .cpu_data_i (cpu_data_i), + .cpu_data_o (cpu_data_o), + .cpu_bp_i (cpu_bp_i), + .cpu_stall_o (cpu_stall_o), + .cpu_stall_all_o (cpu_stall_all_o), + .cpu_stb_o (cpu_stb_o), + .cpu_sel_o (cpu_sel_o), + .cpu_we_o (cpu_we_o), + .cpu_ack_i (cpu_ack_i), + .cpu_rst_o (cpu_rst_o) + + + + + ); + + + +// Connecting CRC module that calculates CRC that is shifted into debug +dbg_crc32_d1 crc32_bench_out + ( + .data (tdi_pad_i), + .enable (crc_out_en), + .shift (crc_out_shift), + .rst (wb_rst_i), + .sync_rst (update_dr_o), + .crc_out (crc_out), + .clk (tck_pad_i), + .crc_match () + ); + + + + +wb_slave_behavioral wb_slave + ( + .CLK_I (wb_clk_i), + .RST_I (wb_rst_i), + .ACK_O (wb_ack_i), + .ADR_I (wb_adr_o), + .CYC_I (wb_cyc_o), + .DAT_O (wb_dat_i), + .DAT_I (wb_dat_o), + .ERR_O (wb_err_i), + .RTY_O (), // NOT USED for now! + .SEL_I (wb_sel_o), + .STB_I (wb_stb_o), + .WE_I (wb_we_o), + .CAB_I (1'b0) + ); + + + +cpu_behavioral i_cpu_behavioral + ( + // CPU signals + .cpu_rst_i (wb_rst_i), + .cpu_clk_o (cpu_clk_i), + .cpu_addr_i (cpu_addr_o), + .cpu_data_o (cpu_data_i), + .cpu_data_i (cpu_data_o), + .cpu_bp_o (cpu_bp_i), + .cpu_stall_i (cpu_stall_o), + .cpu_stall_all_i (cpu_stall_all_o), + .cpu_stb_i (cpu_stb_o), + .cpu_sel_i (cpu_sel_o), + .cpu_we_i (cpu_we_o), + .cpu_ack_o (cpu_ack_i), + .cpu_rst_o (cpu_rst_o) + ); + + + + +// Initial values +initial +begin + test_enabled = 1'b0; + crc_out_en = 1'b0; + crc_out_shift = 1'b0; + wb_data = 32'h01234567; + trst_pad_i = 1'b1; + tms_pad_i = 1'hz; + tck_pad_i = 1'hz; + tdi_pad_i = 1'hz; + + #100; + trst_pad_i = 1'b0; + #100; + trst_pad_i = 1'b1; + #1 test_enabled<=#1 1'b1; +end + +initial +begin + wb_rst_i = 1'b0; + #1000; + wb_rst_i = 1'b1; + #1000; + wb_rst_i = 1'b0; + + // Initial values for wishbone slave model + wb_slave.cycle_response(`ACK_RESPONSE, 9'h55, 8'h2); // (`ACK_RESPONSE, wbs_waits, wbs_retries); +end + +initial +begin + wb_clk_i = 1'b0; + forever #5 wb_clk_i = ~wb_clk_i; +end + +always @ (posedge test_enabled) +begin + + $display("//////////////////////////////////////////////////////////////////"); + $display("// //"); + $display("// (%0t) dbg_tb starting //", $time); + $display("// //"); + $display("//////////////////////////////////////////////////////////////////"); + + initialize_memory(32'h12340000, 32'h00100000); // Initialize 0x100000 bytes starting from address 0x12340000 + + reset_tap; + + #500; + goto_run_test_idle; + + // Testing read and write to internal registers + #10000; + set_instruction(`IDCODE); + read_id_code; + + set_instruction(`DEBUG); + #10000; + + chain_select(`WISHBONE_SCAN_CHAIN, 1'b0); // {chain, gen_crc_err} + +// #10000; +// xxx(4'b1001, 32'he579b242); + + #10000; + +// debug_wishbone(`WB_READ8, 1'b0, 32'h12345678, 16'h4, 1'b0, result, "abc 1"); // {command, ready, addr, length, gen_crc_err, result, text} +// debug_wishbone(`WB_READ8, 1'b0, 32'h12345679, 16'h4, 1'b0, result, "abc 2"); // {command, ready, addr, length, gen_crc_err, result, text} +// debug_wishbone(`WB_READ8, 1'b0, 32'h1234567a, 16'h4, 1'b0, result, "abc 3"); // {command, ready, addr, length, gen_crc_err, result, text} +// +// debug_wishbone(`WB_READ16, 1'b0, 32'h12345678, 16'h4, 1'b0, result, "abc 4"); // {command, ready, addr, length, gen_crc_err, result, text} +// debug_wishbone(`WB_READ16, 1'b0, 32'h1234567a, 16'h4, 1'b0, result, "abc 5"); // {command, ready, addr, length, gen_crc_err, result, text} +// + debug_wishbone(`WB_READ32, 1'b0, 32'h12345678, 16'h4, 1'b0, result, "read32 1"); // {command, ready, addr, length, gen_crc_err, result, text} +// +// debug_wishbone(`WB_READ16, 1'b0, 32'h12345679, 16'h4, 1'b0, result, "abc 6"); // {command, ready, addr, length, gen_crc_err, result, text} + + #10000; +// xxx(4'b1001, 32'he579b242); + + debug_wishbone(`WB_READ32, 1'b1, 32'h12345678, 16'h4, 1'b0, result, "read32 2"); // {command, ready, addr, length, gen_crc_err, result, text} + + #10000; + wb_slave.cycle_response(`ACK_RESPONSE, 9'h55, 8'h2); // (`ACK_RESPONSE, wbs_waits, wbs_retries); + debug_wishbone(`WB_READ32, 1'b1, 32'h12346668, 16'h4, 1'b0, result, "read32 3"); // {command, ready, addr, length, gen_crc_err, result, text} + + #10000; + wb_slave.cycle_response(`ERR_RESPONSE, 9'h03, 8'h2); // (`ERR_RESPONSE, wbs_waits, wbs_retries); + debug_wishbone(`WB_READ32, 1'b1, 32'h12346668, 16'h4, 1'b0, result, "read32 4"); // {command, ready, addr, length, gen_crc_err, result, text} + + #10000; + debug_wishbone(`WB_STATUS, 1'b0, 32'h0, 16'h0, 1'b0, result, "status 1"); // {command, ready, addr, length, gen_crc_err, result, text} + + #10000; + debug_wishbone(`WB_STATUS, 1'b0, 32'h0, 16'h0, 1'b0, result, "status 2"); // {command, ready, addr, length, gen_crc_err, result, text} + + #10000; + wb_slave.cycle_response(`ACK_RESPONSE, 9'h012, 8'h2); // (`ACK_RESPONSE, wbs_waits, wbs_retries); + debug_wishbone(`WB_READ32, 1'b1, 32'h12347778, 16'hc, 1'b0, result, "read32 5"); // {command, ready, addr, length, gen_crc_err, result, text} + + #10000; + debug_wishbone(`WB_WRITE32, 1'b0, 32'h12346668, 16'h8, 1'b0, result, "wr32 len8"); // {command, ready, addr, length, gen_crc_err, result, text} + + #10000; + debug_wishbone(`WB_WRITE16, 1'b0, 32'h12344446, 16'h8, 1'b0, result, "wr16 len8"); // {command, ready, addr, length, gen_crc_err, result, text} + + #10000; + debug_wishbone(`WB_WRITE8, 1'b0, 32'h1234010e, 16'h8, 1'b0, result, "wr8 len8"); // {command, ready, addr, length, gen_crc_err, result, text} + + #10000; + debug_wishbone(`WB_GO, 1'b0, 32'h0, 16'h0, 1'b0, result, "go 1"); // {command, ready, addr, length, gen_crc_err, result, text} + + #10000; + debug_wishbone(`WB_READ32, 1'b1, 32'h12340100, 16'hc, 1'b0, result, "read32 6"); // {command, ready, addr, length, gen_crc_err, result, text} +// debug_wishbone(`WB_READ32, 1'b1, 32'h12340100, 16'hfffc, 1'b0, result, "read32 6"); // {command, ready, addr, length, gen_crc_err, result, text} + + #10000; +// debug_wishbone(`WB_READ16, 1'b1, 32'h12340102, 16'he, 1'b0, result, "read16 7"); // {command, ready, addr, length, gen_crc_err, result, text} +// debug_wishbone(`WB_READ16, 1'b1, 32'h12340102, 16'hfffe, 1'b0, result, "read16 7"); // {command, ready, addr, length, gen_crc_err, result, text} + + #10000; +// debug_wishbone(`WB_READ8, 1'b1, 32'h12348804, 16'h6, 1'b0, result, "read8 8"); // {command, ready, addr, length, gen_crc_err, result, text} +// debug_wishbone(`WB_READ8, 1'b1, 32'h12348804, 16'hfffc, 1'b0, result, "read8 8"); // {command, ready, addr, length, gen_crc_err, result, text} + + #10000; + debug_wishbone(`WB_GO, 1'b0, 32'h0, 16'h0, 1'b0, result, "go 2"); // {command, ready, addr, length, gen_crc_err, result, text} + + #10000; + chain_select(`CPU_DEBUG_CHAIN, 1'b0); // {chain, gen_crc_err} + + + + + // Select cpu0 + #10000; + debug_cpu(`CPU_WRITE_REG, `CPU_SEL_ADR, 32'h0, 1'b0, result, "select cpu 0"); // {command, addr, data, gen_crc_err, result, text} + + #10000; + debug_cpu(`CPU_GO, 32'h0, 32'h1, 1'b0, result, "go cpu"); // {command, addr, data, gen_crc_err, result, text} + + // Read register + #10000; + debug_cpu(`CPU_READ_REG, `CPU_SEL_ADR, 32'h0, 1'b0, result, "cpu_read_reg"); // {command, addr, data, gen_crc_err, result, text} + + #10000; + debug_cpu(`CPU_GO, 32'h0, 32'hff, 1'b0, result, "go cpu"); // {command, addr, data, gen_crc_err, result, text} + + // Stall cpu0 + #10000; + debug_cpu(`CPU_WRITE_REG, `CPU_OP_ADR, 32'h0, 1'b0, result, "stall cpu0"); // {command, addr, data, gen_crc_err, result, text} + + #10000; + debug_cpu(`CPU_GO, 32'h0, 32'h1, 1'b0, result, "go cpu"); // {command, addr, data, gen_crc_err, result, text} + + // write to cpu 32-bit + #10000; + debug_cpu(`CPU_WRITE32, 32'h32323232, 32'h0, 1'b0, result, "cpu_write_32"); // {command, addr, data, gen_crc_err, result, text} + + #10000; + debug_cpu(`CPU_GO, 32'h0, 32'hdeadbeef, 1'b0, result, "go cpu"); // {command, addr, data, gen_crc_err, result, text} + + // read from cpu 32-bit + #10000; + debug_cpu(`CPU_READ32, 32'h32323232, 32'h0, 1'b0, result, "cpu_read_32"); // {command, addr, data, gen_crc_err, result, text} + + #10000; + debug_cpu(`CPU_GO, 32'h0, 32'hdeadbeef, 1'b0, result, "go cpu"); // {command, addr, data, gen_crc_err, result, text} + + // write to cpu 8-bit + #10000; + debug_cpu(`CPU_WRITE8, 32'h08080808, 32'h0, 1'b0, result, "cpu_write_8"); // {command, addr, data, gen_crc_err, result, text} + + #10000; + debug_cpu(`CPU_GO, 32'h0, 32'hdeadbeef, 1'b0, result, "go cpu"); // {command, addr, data, gen_crc_err, result, text} + + // read from cpu 8-bit + #10000; + debug_cpu(`CPU_READ8, 32'h08080808, 32'h0, 1'b0, result, "cpu_read_8"); // {command, addr, data, gen_crc_err, result, text} + + #10000; + debug_cpu(`CPU_GO, 32'h0, 32'hdeadbeef, 1'b0, result, "go cpu"); // {command, addr, data, gen_crc_err, result, text} + +/* + // Testing read and write to CPU0 registers + #10000; + set_instruction(`CHAIN_SELECT); + chain_select(`CPU_DEBUG_CHAIN_0, 8'h12); // {chain, crc} + set_instruction(`DEBUG); + WriteCPURegister(32'h11001100, 32'h00110011, 8'h86); // {data, addr, crc} + + ReadCPURegister(32'h11001100, 8'hdb); // {addr, crc} + ReadCPURegister(32'h11001100, 8'hdb); // {addr, crc} +*/ + #5000 gen_clk(1); // One extra TCLK for debugging purposes + $display("\n\nSimulation end."); + #1000 $stop; + +end + + +task initialize_memory; + input [31:0] start_addr; + input [31:0] length; + integer i; + reg [31:0] addr; + begin +// for (i=0; i=0; i=i-1) + begin + if (gen_crc_err & (i==0)) // Generate crc error at last crc bit + tdi_pad_i<=#1 ~crc_out; // error crc + else + tdi_pad_i<=#1 crc_out; // ok crc + + gen_clk(1); + end + + crc_out_shift = 0; // Disable CRC shifting + + tdi_pad_i<=#1 'hz; // tri-state + + gen_clk(`STATUS_LEN); // Generating 5 clocks to read out status. + + + for(i=0; i<`CRC_LEN -1; i=i+1) + gen_clk(1); + + tms_pad_i<=#1 1; + gen_clk(1); // to exit1_dr + + tdi_pad_i<=#1 'hz; // tri-state + tms_pad_i<=#1 1; + gen_clk(1); // to update_dr + tms_pad_i<=#1 0; + gen_clk(1); // to run_test_idle + end +endtask // chain_select + + + + + + + +task debug_wishbone; + input [2:0] command; + input ready; + input [31:0] addr; + input [15:0] length; + input gen_crc_err; + output [31:0] result; + input [99:0] text; + integer i; + + begin + $write("(%0t) Task debug_wishbone: ", $time); + + test_text = text; + + case (command) + `WB_STATUS : + begin + $display("wb_status (gen_crc_err=%0d (%0s))", gen_crc_err, text); + debug_wishbone_status(command, gen_crc_err); + last_wb_cmd = `WB_STATUS; last_wb_cmd_text = "WB_STATUS"; + end + `WB_READ8 : + begin + $display("wb_read8 (ready=%0d, adr=0x%0x, length=0x%0x, gen_crc_err=%0d (%0s))", ready, addr, length, gen_crc_err, text); + debug_wishbone_set_addr(command, ready, addr, length, gen_crc_err); + last_wb_cmd = `WB_READ8; last_wb_cmd_text = "WB_READ8"; + end + `WB_READ16 : + begin + $display("wb_read16 (ready=%0d, adr=0x%0x, length=0x%0x, gen_crc_err=%0d (%0s))", ready, addr, length, gen_crc_err, text); + debug_wishbone_set_addr(command, ready, addr, length, gen_crc_err); + last_wb_cmd = `WB_READ16; last_wb_cmd_text = "WB_READ16"; + end + `WB_READ32 : + begin + $display("wb_read32 (ready=%0d, adr=0x%0x, length=0x%0x, gen_crc_err=%0d (%0s))", ready, addr, length, gen_crc_err, text); + debug_wishbone_set_addr(command, ready, addr, length, gen_crc_err); + last_wb_cmd = `WB_READ32; last_wb_cmd_text = "WB_READ32"; + end + `WB_WRITE8 : + begin + $display("wb_write8 (adr=0x%0x, length=0x%0x, gen_crc_err=%0d (%0s))", addr, length, gen_crc_err, text); + debug_wishbone_set_addr(command, ready, addr, length, gen_crc_err); + last_wb_cmd = `WB_WRITE8; last_wb_cmd_text = "WB_WRITE8"; + end + `WB_WRITE16 : + begin + $display("wb_write16 (adr=0x%0x, length=0x%0x, gen_crc_err=%0d (%0s))", addr, length, gen_crc_err, text); + debug_wishbone_set_addr(command, ready, addr, length, gen_crc_err); + last_wb_cmd = `WB_WRITE16; last_wb_cmd_text = "WB_WRITE16"; + end + `WB_WRITE32 : + begin + $display("wb_write32 (adr=0x%0x, length=0x%0x, gen_crc_err=%0d (%0s))", addr, length, gen_crc_err, text); + debug_wishbone_set_addr(command, ready, addr, length, gen_crc_err); + last_wb_cmd = `WB_WRITE32; last_wb_cmd_text = "WB_WRITE32"; + end + `WB_GO : + begin + $display("wb_go, gen_crc_err=%0d (%0s))", gen_crc_err, text); + debug_wishbone_go(command, gen_crc_err); +// $display("wb_go_tmp, gen_crc_err=0x%0x (%0s))", gen_crc_err, text); +// debug_wishbone_go_tmp(command, crc); + last_wb_cmd = `WB_GO; last_wb_cmd_text = "WB_GO"; + end + endcase + end +endtask // debug_wishbone + + + + + + +task debug_wishbone_set_addr; + input [2:0] command; + input wait_for_wb_ready; // igor !!! Change this since access only occurs in the "go" stage. Add condition "fifo_empty". + input [31:0] addr; + input [15:0] length; + input gen_crc_err; + integer i; + + begin + $display("(%0t) Task debug_wishbone_set_addr: ", $time); + + tms_pad_i<=#1 1; + gen_clk(1); + tms_pad_i<=#1 0; + gen_clk(2); // we are in shiftDR + + crc_out_en = 1; // Enable CRC calculation + + tdi_pad_i<=#1 1'b0; // chain_select bit = 0 + gen_clk(1); + + for(i=2; i>=0; i=i-1) + begin + tdi_pad_i<=#1 command[i]; // command + gen_clk(1); + end + + for(i=31; i>=0; i=i-1) // address + begin + tdi_pad_i<=#1 addr[i]; + gen_clk(1); + end + + for(i=15; i>=0; i=i-1) // length + begin + tdi_pad_i<=#1 length[i]; + gen_clk(1); + end + + crc_out_en = 0; // Disable CRC calculation + crc_out_shift = 1; // Enable CRC shifting + + for(i=31; i>=0; i=i-1) + begin + if (gen_crc_err & (i==0)) // Generate crc error at last crc bit + tdi_pad_i<=#1 ~crc_out; // error crc + else + tdi_pad_i<=#1 crc_out; // ok crc + + gen_clk(1); + end + + crc_out_shift = 0; // Disable CRC shifting + + tdi_pad_i<=#1 'hz; + if (wait_for_wb_ready) + begin + gen_clk(`STATUS_LEN -1); // Generating 4 clocks to read out status. Going to pause_dr at the end + tms_pad_i<=#1 1; + gen_clk(1); // to exit1_dr + tms_pad_i<=#1 0; + gen_clk(1); // to pause_dr + + while (dbg_tb.tdo_pad_o) // waiting for wb to send "ready" + begin + gen_clk(1); // staying in pause_dr + end + + tms_pad_i<=#1 1; + gen_clk(1); // to exit2_dr + tms_pad_i<=#1 0; + gen_clk(1); // to shift_dr + end + else + gen_clk(`STATUS_LEN); // Generating 4 clocks to read out status. + + for(i=0; i<`CRC_LEN -1; i=i+1) // Getting in the CRC + begin + gen_clk(1); + end + + tms_pad_i<=#1 1; + gen_clk(1); // to exit1_dr + + tms_pad_i<=#1 1; + gen_clk(1); // to update_dr + tms_pad_i<=#1 0; + gen_clk(1); // to run_test_idle + end +endtask // debug_wishbone_set_addr + + + + + +task debug_wishbone_status; + input [2:0] command; + input gen_crc_err; + integer i; + + begin + $display("(%0t) Task debug_wishbone_status: ", $time); + + tms_pad_i<=#1 1; + gen_clk(1); + tms_pad_i<=#1 0; + gen_clk(2); // we are in shiftDR + + crc_out_en = 1; // Enable CRC calculation + + tdi_pad_i<=#1 1'b0; // chain_select bit = 0 + gen_clk(1); + + for(i=2; i>=0; i=i-1) + begin + tdi_pad_i<=#1 command[i]; // command + gen_clk(1); + end + + crc_out_en = 0; // Disable CRC calculation + crc_out_shift = 1; // Enable CRC shifting + + for(i=31; i>=0; i=i-1) + begin + if (gen_crc_err & (i==0)) // Generate crc error at last crc bit + tdi_pad_i<=#1 ~crc_out; // error crc + else + tdi_pad_i<=#1 crc_out; // ok crc + + gen_clk(1); + end + + crc_out_shift = 0; // Disable CRC shifting + + tdi_pad_i<=#1 1'hz; + gen_clk(`STATUS_LEN); // Generating 4 clocks to read out status. + + for(i=0; i<`CRC_LEN -1; i=i+1) // Getting in the CRC + begin + gen_clk(1); + end + + tms_pad_i<=#1 1; + gen_clk(1); // to exit1_dr + + tms_pad_i<=#1 1; + gen_clk(1); // to update_dr + tms_pad_i<=#1 0; + gen_clk(1); // to run_test_idle + end +endtask // debug_wishbone_status + + + + +task debug_wishbone_go; + input [2:0] command; + input gen_crc_err; + integer i; + reg [4:0] pointer; + + begin + $display("(%0t) Task debug_wishbone_go (previous command was %0s): ", $time, last_wb_cmd_text); + + tms_pad_i<=#1 1; + gen_clk(1); + tms_pad_i<=#1 0; + gen_clk(2); // we are in shiftDR + + crc_out_en = 1; // Enable CRC calculation + + tdi_pad_i<=#1 1'b0; // chain_select bit = 0 + gen_clk(1); + + for(i=2; i>=0; i=i-1) + begin + tdi_pad_i<=#1 command[i]; // command + gen_clk(1); + end + + + if ((last_wb_cmd == `WB_WRITE8) | (last_wb_cmd == `WB_WRITE16) | (last_wb_cmd == `WB_WRITE32)) // When WB_WRITEx was previously activated, data needs to be shifted. + begin + for (i=0; i<(dbg_tb.i_dbg_top.i_dbg_wb.len << 3); i=i+1) + begin + if (!(i%32)) + begin + wb_data = wb_data + 32'h11111111; + $display("\t\twb_data = 0x%x", wb_data); + end + pointer = 31-i[4:0]; + tdi_pad_i<=#1 wb_data[pointer]; + gen_clk(1); + + end + end + + crc_out_en = 0; // Disable CRC calculation + crc_out_shift = 1; // Enable CRC shifting + + for(i=31; i>=0; i=i-1) + begin + if (gen_crc_err & (i==0)) // Generate crc error at last crc bit + tdi_pad_i<=#1 ~crc_out; // error crc + else + tdi_pad_i<=#1 crc_out; // ok crc + + gen_clk(1); + end + + crc_out_shift = 0; // Disable CRC shifting + + tdi_pad_i<=#1 1'hz; + + + + if ((last_wb_cmd == `WB_READ8) | (last_wb_cmd == `WB_READ16) | (last_wb_cmd == `WB_READ32)) // When WB_WRITEx was previously activated, data needs to be shifted. + begin + $display("\t\tGenerating %0d clocks to read %0d data bytes.", dbg_tb.i_dbg_top.i_dbg_wb.data_cnt_limit, dbg_tb.i_dbg_top.i_dbg_wb.data_cnt_limit>>3); + for (i=0; i<(dbg_tb.i_dbg_top.i_dbg_wb.data_cnt_limit); i=i+1) + gen_clk(1); + end + + + gen_clk(`STATUS_LEN); // Generating 4 clocks to read out status. + + for(i=0; i<`CRC_LEN -1; i=i+1) // Getting in the CRC + begin + gen_clk(1); + end + + tms_pad_i<=#1 1; + gen_clk(1); // to exit1_dr + + tms_pad_i<=#1 1; + gen_clk(1); // to update_dr + tms_pad_i<=#1 0; + gen_clk(1); // to run_test_idle + end +endtask // debug_wishbone_go + + + + +task debug_cpu; + input [2:0] command; + input [31:0] addr; + input [31:0] data; + input gen_crc_err; + output [31:0] result; + input [199:0] text; + integer i; + + begin + $write("(%0t) Task debug_cpu: ", $time); + + test_text = text; + + case (command) +// `WB_STATUS : +// begin +// $display("wb_status (gen_crc_err=%0d (%0s))", gen_crc_err, text); +// debug_wishbone_status(command, gen_crc_err); +// last_wb_cmd = `WB_STATUS; last_wb_cmd_text = "WB_STATUS"; +// end + `CPU_READ_REG : + begin + $display("cpu_read_reg (adr=0x%0x, gen_crc_err=%0d (%0s))", addr, gen_crc_err, text); + debug_cpu_set_addr(command, addr, gen_crc_err); + last_wb_cmd = `CPU_READ_REG; last_wb_cmd_text = "CPU_READ_REG"; + end + `CPU_WRITE_REG : + begin + $display("cpu_write_reg (adr=0x%0x, gen_crc_err=%0d (%0s))", addr, gen_crc_err, text); + debug_cpu_set_addr(command, addr, gen_crc_err); + last_wb_cmd = `CPU_WRITE_REG; last_wb_cmd_text = "CPU_WRITE_REG"; + end + `CPU_READ8 : + begin + $display("cpu_read8 (adr=0x%0x, gen_crc_err=%0d (%0s))", addr, gen_crc_err, text); + debug_cpu_set_addr(command, addr, gen_crc_err); + last_wb_cmd = `CPU_READ8; last_wb_cmd_text = "CPU_READ8"; + end + `CPU_READ32 : + begin + $display("cpu_read32 (adr=0x%0x, gen_crc_err=%0d (%0s))", addr, gen_crc_err, text); + debug_cpu_set_addr(command, addr, gen_crc_err); + last_wb_cmd = `CPU_READ32; last_wb_cmd_text = "CPU_READ32"; + end + `CPU_WRITE8 : + begin + $display("cpu_write8 (adr=0x%0x, gen_crc_err=%0d (%0s))", addr, gen_crc_err, text); + debug_cpu_set_addr(command, addr, gen_crc_err); + last_wb_cmd = `CPU_WRITE8; last_wb_cmd_text = "CPU_WRITE8"; + end + `CPU_WRITE32 : + begin + $display("cpu_write32 (adr=0x%0x, gen_crc_err=%0d (%0s))", addr, gen_crc_err, text); + debug_cpu_set_addr(command, addr, gen_crc_err); + last_wb_cmd = `CPU_WRITE32; last_wb_cmd_text = "CPU_WRITE32"; + end + `CPU_GO : + begin + $display("cpu_go, data = 0x%0x, gen_crc_err=%0d (%0s))", data, gen_crc_err, text); + debug_cpu_go(command, data, gen_crc_err); + last_wb_cmd = `CPU_GO; last_wb_cmd_text = "CPU_GO"; + end + default : + begin + $display("\t\tERROR: Non-existing command while debugging %0s", gen_crc_err, text); + $stop; + end + endcase + end +endtask // debug_cpu + + + +task debug_cpu_set_addr; + input [2:0] command; + input [31:0] addr; + input gen_crc_err; + integer i; + + begin + $display("(%0t) Task debug_cpu_set_addr: ", $time); + + tms_pad_i<=#1 1; + gen_clk(1); + tms_pad_i<=#1 0; + gen_clk(2); // we are in shiftDR + + crc_out_en = 1; // Enable CRC calculation + + tdi_pad_i<=#1 1'b0; // chain_select bit = 0 + gen_clk(1); + + for(i=2; i>=0; i=i-1) + begin + tdi_pad_i<=#1 command[i]; // command + gen_clk(1); + end + + for(i=31; i>=0; i=i-1) // address + begin + tdi_pad_i<=#1 addr[i]; + gen_clk(1); + end + + crc_out_en = 0; // Disable CRC calculation + crc_out_shift = 1; // Enable CRC shifting + + for(i=31; i>=0; i=i-1) + begin + if (gen_crc_err & (i==0)) // Generate crc error at last crc bit + tdi_pad_i<=#1 ~crc_out; // error crc + else + tdi_pad_i<=#1 crc_out; // ok crc + + gen_clk(1); + end + + crc_out_shift = 0; // Disable CRC shifting + + tdi_pad_i<=#1 'hz; + gen_clk(`STATUS_LEN); // Generating 4 clocks to read out status. + + for(i=0; i<`CRC_LEN -1; i=i+1) // Getting in the CRC + begin + gen_clk(1); + end + + tms_pad_i<=#1 1; + gen_clk(1); // to exit1_dr + + tms_pad_i<=#1 1; + gen_clk(1); // to update_dr + tms_pad_i<=#1 0; + gen_clk(1); // to run_test_idle + end +endtask // debug_cpu_set_addr + + + + +task debug_cpu_go; + input [2:0] command; + input [31:0] data; + input gen_crc_err; + integer i, len; + + + begin + $display("(%0t) Task debug_cpu_go (previous command was %0s): ", $time, last_wb_cmd_text); + + tms_pad_i<=#1 1; + gen_clk(1); + tms_pad_i<=#1 0; + gen_clk(2); // we are in shiftDR + + crc_out_en = 1; // Enable CRC calculation + + tdi_pad_i<=#1 1'b0; // chain_select bit = 0 + gen_clk(1); + + for(i=2; i>=0; i=i-1) + begin + tdi_pad_i<=#1 command[i]; // command + gen_clk(1); + end + + + if (last_wb_cmd == `CPU_WRITE32) + begin + len = 31; + $display("\t\tdata = 0x%x", data); + end + else if ((last_wb_cmd == `CPU_WRITE8) | (last_wb_cmd == `CPU_WRITE_REG)) + begin + len = 7; + $display("\t\tdata = 0x%x", data[7:0]); + end + else + len = 0; + + if (len>0) // When CPU_WRITEx was previously activated, data needs to be shifted. + begin + for (i=len; i>=0; i=i-1) + begin + tdi_pad_i<=#1 data[i]; + gen_clk(1); + end + end + + crc_out_en = 0; // Disable CRC calculation + crc_out_shift = 1; // Enable CRC shifting + + for(i=31; i>=0; i=i-1) + begin + if (gen_crc_err & (i==0)) // Generate crc error at last crc bit + tdi_pad_i<=#1 ~crc_out; // error crc + else + tdi_pad_i<=#1 crc_out; // ok crc + + gen_clk(1); + end + + crc_out_shift = 0; // Disable CRC shifting + + tdi_pad_i<=#1 1'hz; + + + if (last_wb_cmd == `CPU_READ32) + len = 32; + else if ((last_wb_cmd == `CPU_READ8) | (last_wb_cmd == `CPU_READ_REG)) + len = 8; + else + len = 0; + + if (len>0) // When CPU_WRITEx was previously activated, data needs to be shifted. + begin + $display("\t\tGenerating %0d clocks to read out the data.", len); + for (i=0; i
tags/rel_13/bench/verilog/timescale.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/rel_13/bench/verilog/wb_slave_behavioral.v =================================================================== --- tags/rel_13/bench/verilog/wb_slave_behavioral.v (nonexistent) +++ tags/rel_13/bench/verilog/wb_slave_behavioral.v (revision 105) @@ -0,0 +1,407 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// wb_slave_behavioral.v //// +//// //// +//// //// +//// This file is part of the SoC/OpenRISC Development Interface //// +//// http://www.opencores.org/projects/DebugInterface/ //// +//// //// +//// Author(s): //// +//// Tadej Markovic, tadej@opencores.org //// +//// //// +//// //// +//// All additional information is avaliable in the README.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 - 2003 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.1 2003/12/23 14:26:01 mohor +// New version of the debug interface. Not finished, yet. +// +// +// +// + +`include "timescale.v" +`include "wb_model_defines.v" +module wb_slave_behavioral +( + CLK_I, + RST_I, + ACK_O, + ADR_I, + CYC_I, + DAT_O, + DAT_I, + ERR_O, + RTY_O, + SEL_I, + STB_I, + WE_I, + CAB_I +); + +/*------------------------------------------------------------------------------------------------------ +WISHBONE signals +------------------------------------------------------------------------------------------------------*/ +input CLK_I; +input RST_I; +output ACK_O; +input `WB_ADDR_TYPE ADR_I; +input CYC_I; +output `WB_DATA_TYPE DAT_O; +input `WB_DATA_TYPE DAT_I; +output ERR_O; +output RTY_O; +input `WB_SEL_TYPE SEL_I; +input STB_I; +input WE_I; +input CAB_I; + +reg `WB_DATA_TYPE DAT_O; + +/*------------------------------------------------------------------------------------------------------ +Asynchronous dual-port RAM signals for storing and fetching the data +------------------------------------------------------------------------------------------------------*/ +//reg `WB_DATA_TYPE wb_memory [0:16777215]; // WB memory - 24 addresses connected - 2 LSB not used +reg `WB_DATA_TYPE wb_memory [0:1048575]; // WB memory - 20 addresses connected - 2 LSB not used +reg `WB_DATA_TYPE mem_wr_data_out; +reg `WB_DATA_TYPE mem_rd_data_in; + +/*------------------------------------------------------------------------------------------------------ +Maximum values for WAIT and RETRY counters and which response !!! +------------------------------------------------------------------------------------------------------*/ +reg [2:0] a_e_r_resp; // tells with which cycle_termination_signal must wb_slave respond ! +reg [8:0] wait_cyc; +reg [7:0] max_retry; + +// assign registers to default state while in reset +// always@(RST_I) +// begin +// if (RST_I) +// begin +// a_e_r_resp <= 3'b000; // do not respond +// wait_cyc <= 8'b0; // no wait cycles +// max_retry <= 8'h0; // no retries +// end +// end //reset + +task cycle_response; + input [2:0] ack_err_rty_resp; // acknowledge, error or retry response input flags + input [8:0] wait_cycles; // if wait cycles before each data termination cycle (ack, err or rty) + input [7:0] retry_cycles; // noumber of retry cycles before acknowledge cycle +begin + // assign values + a_e_r_resp <= #1 ack_err_rty_resp; + wait_cyc <= #1 wait_cycles; + max_retry <= #1 retry_cycles; +end +endtask // cycle_response + +/*------------------------------------------------------------------------------------------------------ +Tasks for writing and reading to and from memory !!! +------------------------------------------------------------------------------------------------------*/ +reg `WB_ADDR_TYPE task_wr_adr_i; +reg `WB_ADDR_TYPE task_rd_adr_i; +reg `WB_DATA_TYPE task_dat_i; +reg `WB_DATA_TYPE task_dat_o; +reg `WB_SEL_TYPE task_sel_i; +reg task_wr_data; +reg task_data_written; +reg `WB_DATA_TYPE task_mem_wr_data; + +// write to memory +task wr_mem; + input `WB_ADDR_TYPE adr_i; + input `WB_DATA_TYPE dat_i; + input `WB_SEL_TYPE sel_i; +begin + task_data_written = 0; + task_wr_adr_i = adr_i; + task_dat_i = dat_i; + task_sel_i = sel_i; + task_wr_data = 1; + wait(task_data_written); + task_wr_data = 0; +end +endtask + +// read from memory +task rd_mem; + input `WB_ADDR_TYPE adr_i; + output `WB_DATA_TYPE dat_o; + input `WB_SEL_TYPE sel_i; +begin + task_rd_adr_i = adr_i; + task_sel_i = sel_i; + #1; + dat_o = task_dat_o; +end +endtask + +/*------------------------------------------------------------------------------------------------------ +Internal signals and logic +------------------------------------------------------------------------------------------------------*/ +reg calc_ack; +reg calc_err; +reg calc_rty; + +reg [7:0] retry_cnt; +reg [7:0] retry_num; +reg retry_expired; + +// Retry counter +always@(posedge RST_I or posedge CLK_I) +begin + if (RST_I) + retry_cnt <= #1 8'h00; + else + begin + if (calc_ack || calc_err) + retry_cnt <= #1 8'h00; + else if (calc_rty) + retry_cnt <= #1 retry_num; + end +end + +always@(retry_cnt or max_retry) +begin + if (retry_cnt < max_retry) + begin + retry_num = retry_cnt + 1'b1; + retry_expired = 1'b0; + end + else + begin + retry_num = retry_cnt; + retry_expired = 1'b1; + end +end + +reg [8:0] wait_cnt; +reg [8:0] wait_num; +reg wait_expired; + +// Wait counter +always@(posedge RST_I or posedge CLK_I) +begin + if (RST_I) + wait_cnt <= #1 9'h0; + else + begin + if (wait_expired || ~STB_I) + wait_cnt <= #1 9'h0; + else + wait_cnt <= #1 wait_num; + end +end + +always@(wait_cnt or wait_cyc or STB_I or a_e_r_resp or retry_expired) +begin + if ((wait_cyc > 0) && (STB_I)) + begin + if (wait_cnt < wait_cyc) + begin + wait_num = wait_cnt + 1'b1; + wait_expired = 1'b0; + calc_ack = 1'b0; + calc_err = 1'b0; + calc_rty = 1'b0; + end + else + begin + wait_num = wait_cnt; + wait_expired = 1'b1; + if (a_e_r_resp == 3'b100) + begin + calc_ack = 1'b1; + calc_err = 1'b0; + calc_rty = 1'b0; + end + else + if (a_e_r_resp == 3'b010) + begin + calc_ack = 1'b0; + calc_err = 1'b1; + calc_rty = 1'b0; + end + else + if (a_e_r_resp == 3'b001) + begin + calc_err = 1'b0; + if (retry_expired) + begin + calc_ack = 1'b1; + calc_rty = 1'b0; + end + else + begin + calc_ack = 1'b0; + calc_rty = 1'b1; + end + end + else + begin + calc_ack = 1'b0; + calc_err = 1'b0; + calc_rty = 1'b0; + end + end + end + else + if ((wait_cyc == 0) && (STB_I)) + begin + wait_num = 9'h0; + wait_expired = 1'b1; + if (a_e_r_resp == 3'b100) + begin + calc_ack = 1'b1; + calc_err = 1'b0; + calc_rty = 1'b0; + end + else if (a_e_r_resp == 3'b010) + begin + calc_ack = 1'b0; + calc_err = 1'b1; + calc_rty = 1'b0; + end + else if (a_e_r_resp == 3'b001) + begin + calc_err = 1'b0; + if (retry_expired) + begin + calc_ack = 1'b1; + calc_rty = 1'b0; + end + else + begin + calc_ack = 1'b0; + calc_rty = 1'b1; + end + end + else + begin + calc_ack = 1'b0; + calc_err = 1'b0; + calc_rty = 1'b0; + end + end + else + begin + wait_num = 9'h0; + wait_expired = 1'b0; + calc_ack = 1'b0; + calc_err = 1'b0; + calc_rty = 1'b0; + end +end + +wire rd_sel = (CYC_I && STB_I && ~WE_I); +wire wr_sel = (CYC_I && STB_I && WE_I); + +// Generate cycle termination signals +assign ACK_O = calc_ack && STB_I; +assign ERR_O = calc_err && STB_I; +assign RTY_O = calc_rty && STB_I; + +// Assign address to asynchronous memory +always@(RST_I or ADR_I) +begin + if (RST_I) // this is added because at start of test bench we need address change in order to get data! + begin + #1 mem_rd_data_in = `WB_DATA_WIDTH'hxxxx_xxxx; + end + else + begin +// #1 mem_rd_data_in = wb_memory[ADR_I[25:2]]; + #1 mem_rd_data_in = wb_memory[ADR_I[21:2]]; + end +end + +// Data input/output interface +always@(rd_sel or mem_rd_data_in or RST_I) +begin + if (RST_I) + DAT_O <=#1 `WB_DATA_WIDTH'hxxxx_xxxx; // assign outputs to unknown state while in reset + else if (rd_sel) + DAT_O <=#1 mem_rd_data_in; + else + DAT_O <=#1 `WB_DATA_WIDTH'hxxxx_xxxx; +end + + +always@(RST_I or task_rd_adr_i) +begin + if (RST_I) + task_dat_o = `WB_DATA_WIDTH'hxxxx_xxxx; + else + task_dat_o = wb_memory[task_rd_adr_i[21:2]]; +end +always@(CLK_I or wr_sel or task_wr_data or ADR_I or task_wr_adr_i or + mem_wr_data_out or DAT_I or task_mem_wr_data or task_dat_i or + SEL_I or task_sel_i) +begin + if (task_wr_data) + begin + task_mem_wr_data = wb_memory[task_wr_adr_i[21:2]]; + + if (task_sel_i[3]) + task_mem_wr_data[31:24] = task_dat_i[31:24]; + if (task_sel_i[2]) + task_mem_wr_data[23:16] = task_dat_i[23:16]; + if (task_sel_i[1]) + task_mem_wr_data[15: 8] = task_dat_i[15: 8]; + if (task_sel_i[0]) + task_mem_wr_data[ 7: 0] = task_dat_i[ 7: 0]; + + wb_memory[task_wr_adr_i[21:2]] = task_mem_wr_data; // write data + task_data_written = 1; + end + else if (wr_sel && CLK_I) + begin +// mem_wr_data_out = wb_memory[ADR_I[25:2]]; // if no SEL_I is active, old value will be written + mem_wr_data_out = wb_memory[ADR_I[21:2]]; // if no SEL_I is active, old value will be written + + if (SEL_I[3]) + mem_wr_data_out[31:24] = DAT_I[31:24]; + if (SEL_I[2]) + mem_wr_data_out[23:16] = DAT_I[23:16]; + if (SEL_I[1]) + mem_wr_data_out[15: 8] = DAT_I[15: 8]; + if (SEL_I[0]) + mem_wr_data_out[ 7: 0] = DAT_I[ 7: 0]; + +// wb_memory[ADR_I[25:2]] <= mem_wr_data_out; // write data + wb_memory[ADR_I[21:2]] = mem_wr_data_out; // write data + end +end + +endmodule Index: tags/rel_13/bench/verilog/dbg_tb_defines.v =================================================================== --- tags/rel_13/bench/verilog/dbg_tb_defines.v (nonexistent) +++ tags/rel_13/bench/verilog/dbg_tb_defines.v (revision 105) @@ -0,0 +1,171 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// dbg_tb_defines.v //// +//// //// +//// //// +//// This file is part of the SoC/OpenRISC Development Interface //// +//// http://www.opencores.org/projects/DebugInterface/ //// +//// //// +//// Author(s): //// +//// Igor Mohor (igorm@opencores.org) //// +//// //// +//// //// +//// All additional information is avaliable in the README.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 - 2003 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.2 2001/09/18 14:12:43 mohor +// Trace fixed. Some registers changed, trace simplified. +// +// Revision 1.1.1.1 2001/09/13 13:49:19 mohor +// Initial official release. +// +// Revision 1.3 2001/06/01 22:23:40 mohor +// This is a backup. It is not a fully working version. Not for use, yet. +// +// Revision 1.2 2001/05/18 13:10:05 mohor +// Headers changed. All additional information is now avaliable in the README.txt file. +// +// Revision 1.1.1.1 2001/05/18 06:35:12 mohor +// Initial release +// +// + +// Following defines are used in the testbench only + + // MODER register + `define ENABLE 32'h00010000 + `define CONTIN 32'h00020000 + + // TSEL register + `define WPTRIG_0 32'h00000001 + `define WPTRIG_1 32'h00000002 + `define WPTRIG_2 32'h00000004 + `define WPTRIG_3 32'h00000008 + `define WPTRIG_4 32'h00000010 + `define WPTRIG_5 32'h00000020 + `define WPTRIG_6 32'h00000040 + `define WPTRIG_7 32'h00000080 + `define WPTRIG_8 32'h00000100 + `define WPTRIG_9 32'h00000200 + `define WPTRIG_10 32'h00000400 + `define WPTRIGVALID 32'h00000800 + + `define BPTRIG 32'h00001000 + `define BPTRIGVALID 32'h00002000 + + `define LSSTRIG_0 32'h00010000 + `define LSSTRIG_1 32'h00020000 + `define LSSTRIG_2 32'h00040000 + `define LSSTRIG_3 32'h00080000 + `define LSSTRIGVALID 32'h00100000 + + `define ISTRIGVALID 32'h00800000 + + `define TRIGOP_AND 32'hc0000000 + `define TRIGOP_OR 32'h80000000 + + // QSEL register + `define WPQUALIF_0 32'h00000001 + `define WPQUALIF_1 32'h00000002 + `define WPQUALIF_2 32'h00000004 + `define WPQUALIF_3 32'h00000008 + `define WPQUALIF_4 32'h00000010 + `define WPQUALIF_5 32'h00000020 + `define WPQUALIF_6 32'h00000040 + `define WPQUALIF_7 32'h00000080 + `define WPQUALIF_8 32'h00000100 + `define WPQUALIF_9 32'h00000200 + `define WPQUALIF_10 32'h00000400 + `define WPQUALIFVALID 32'h00000800 + + `define BPQUALIF 32'h00001000 + `define BPQUALIFVALID 32'h00002000 + + `define LSSQUALIF_0 32'h00010000 + `define LSSQUALIF_1 32'h00020000 + `define LSSQUALIF_2 32'h00040000 + `define LSSQUALIF_3 32'h00080000 + `define LSSQUALIFVALID 32'h00100000 + + `define ISQUALIFVALID 32'h00800000 + + `define QUALIFOP_AND 32'hc0000000 + `define QUALIFOP_OR 32'h80000000 + + + // SSEL register + `define WPSTOP_0 32'h00000001 + `define WPSTOP_1 32'h00000002 + `define WPSTOP_2 32'h00000004 + `define WPSTOP_3 32'h00000008 + `define WPSTOP_4 32'h00000010 + `define WPSTOP_5 32'h00000020 + `define WPSTOP_6 32'h00000040 + `define WPSTOP_7 32'h00000080 + `define WPSTOP_8 32'h00000100 + `define WPSTOP_9 32'h00000200 + `define WPSTOP_10 32'h00000400 + `define WPSTOPVALID 32'h00000800 + + `define BPSTOP 32'h00001000 + `define BPSTOPVALID 32'h00002000 + + `define LSSSTOP_0 32'h00010000 + `define LSSSTOP_1 32'h00020000 + `define LSSSTOP_2 32'h00040000 + `define LSSSTOP_3 32'h00080000 + `define LSSSTOPVALID 32'h00100000 + + `define ISSTOPVALID 32'h00800000 + + `define STOPOP_AND 32'hc0000000 + `define STOPOP_OR 32'h80000000 + + `define IS_NO_FETCH 32'h00000000 + `define IS_FETCH 32'h00200000 + `define IS_BRANCH 32'h00400000 + `define IS_FETCH_DELAY 32'h00600000 + + `define LSS_NO_LOADSTORE 32'h00000000 + `define LSS_LOADBYTE_ZEROEXT 32'h00020000 + `define LSS_LOADBYTE_SIGNEXT 32'h00030000 + `define LSS_LOADHALF_ZEROEXT 32'h00040000 + `define LSS_LOADHALF_SIGNEXT 32'h00050000 + `define LSS_LOADWORD_ZEROEXT 32'h00060000 + `define LSS_LOADWORD_SIGNEXT 32'h00070000 + `define LSS_STORE_BYTE 32'h000A0000 + `define LSS_STORE_HALF 32'h000C0000 + +// End: Following defines are used in the testbench only + + Index: tags/rel_13/bench/verilog/wb_model_defines.v =================================================================== --- tags/rel_13/bench/verilog/wb_model_defines.v (nonexistent) +++ tags/rel_13/bench/verilog/wb_model_defines.v (revision 105) @@ -0,0 +1,148 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// dbg_tb_defines.v //// +//// //// +//// //// +//// This file is part of the SoC/OpenRISC Development Interface //// +//// http://www.opencores.org/projects/DebugInterface/ //// +//// //// +//// Author(s): //// +//// - Miha Dolenc (mihad@opencores.org) //// +//// //// +//// //// +//// All additional information is avaliable in the README.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 - 2003 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// +// + +// WISHBONE frequency in GHz +`define WB_FREQ 0.100 + +// memory frequency in GHz +`define MEM_FREQ 0.100 + +// setup and hold time definitions for WISHBONE - used in BFMs for signal generation +`define Tsetup 4 +`define Thold 1 + +// how many clock cycles should model wait for design's response - integer 32 bit value +`define WAIT_FOR_RESPONSE 1023 + +// maximum number of transactions allowed in single call to block or cab transfer routines +`define MAX_BLK_SIZE 1024 + +// maximum retry terminations allowed for WISHBONE master to repeat an access +`define WB_TB_MAX_RTY 0 + + +// some common types and defines +`define WB_ADDR_WIDTH 32 +`define WB_DATA_WIDTH 32 +`define WB_SEL_WIDTH `WB_DATA_WIDTH/8 +`define WB_TAG_WIDTH 5 +`define WB_ADDR_TYPE [(`WB_ADDR_WIDTH - 1):0] +`define WB_DATA_TYPE [(`WB_DATA_WIDTH - 1):0] +`define WB_SEL_TYPE [(`WB_SEL_WIDTH - 1):0] +`define WB_TAG_TYPE [(`WB_TAG_WIDTH - 1):0] + +// read cycle stimulus - consists of: +// - address field - which address read will be performed from +// - sel field - what byte select value should be +// - tag field - what tag values should be put on the bus +`define READ_STIM_TYPE [(`WB_ADDR_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH - 1):0] +`define READ_STIM_LENGTH (`WB_ADDR_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH) +`define READ_ADDRESS [(`WB_ADDR_WIDTH - 1):0] +`define READ_SEL [(`WB_ADDR_WIDTH + `WB_SEL_WIDTH - 1):`WB_ADDR_WIDTH] +`define READ_TAG_STIM [(`WB_ADDR_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH - 1):(`WB_ADDR_WIDTH + `WB_SEL_WIDTH)] + +// read cycle return type consists of: +// - read data field +// - tag field received from WISHBONE +// - wishbone slave response fields - ACK, ERR and RTY +// - test bench error indicator (when testcase has not used wb master model properly) +// - how much data was actually transfered +`define READ_RETURN_TYPE [(32 + 4 + `WB_DATA_WIDTH + `WB_TAG_WIDTH - 1):0] +`define READ_DATA [(32 + `WB_DATA_WIDTH + 4 - 1):32 + 4] +`define READ_TAG_RET [(32 + 4 + `WB_DATA_WIDTH + `WB_TAG_WIDTH - 1):(`WB_DATA_WIDTH + 32 + 4)] +`define READ_RETURN_LENGTH (32 + 4 + `WB_DATA_WIDTH + `WB_TAG_WIDTH - 1) + +// write cycle stimulus type consists of +// - address field +// - data field +// - sel field +// - tag field +`define WRITE_STIM_TYPE [(`WB_ADDR_WIDTH + `WB_DATA_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH - 1):0] +`define WRITE_ADDRESS [(`WB_ADDR_WIDTH - 1):0] +`define WRITE_DATA [(`WB_ADDR_WIDTH + `WB_DATA_WIDTH - 1):`WB_ADDR_WIDTH] +`define WRITE_SEL [(`WB_ADDR_WIDTH + `WB_DATA_WIDTH + `WB_SEL_WIDTH - 1):(`WB_ADDR_WIDTH + `WB_DATA_WIDTH)] +`define WRITE_TAG_STIM [(`WB_ADDR_WIDTH + `WB_DATA_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH - 1):(`WB_ADDR_WIDTH + `WB_DATA_WIDTH + `WB_SEL_WIDTH)] + +// length of WRITE_STIMULUS +`define WRITE_STIM_LENGTH (`WB_ADDR_WIDTH + `WB_DATA_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH) + +// write cycle return type consists of: +// - test bench error indicator (when testcase has not used wb master model properly) +// - wishbone slave response fields - ACK, ERR and RTY +// - tag field received from WISHBONE +// - how much data was actually transfered +`define WRITE_RETURN_TYPE [(32 + 4 + `WB_TAG_WIDTH - 1):0] +`define WRITE_TAG_RET [(32 + 4 + `WB_TAG_WIDTH - 1):32 + 4] + +// this four fields are common to both read and write routines return values +`define TB_ERROR_BIT [0] +`define CYC_ACK [1] +`define CYC_RTY [2] +`define CYC_ERR [3] +`define CYC_RESPONSE [3:1] +`define CYC_ACTUAL_TRANSFER [35:4] + +// block transfer flags +`define WB_TRANSFER_FLAGS [41:0] +// consists of: +// - number of transfer cycles to perform +// - flag that enables retry termination handling - if disabled, block transfer routines will return on any termination other than acknowledge +// - flag indicating CAB transfer is to be performed - ignored by all single transfer routines +// - number of initial wait states to insert +// - number of subsequent wait states to insert +`define WB_TRANSFER_SIZE [41:10] +`define WB_TRANSFER_AUTO_RTY [8] +`define WB_TRANSFER_CAB [9] +`define INIT_WAITS [3:0] +`define SUBSEQ_WAITS [7:4] + +// wb slave response +`define ACK_RESPONSE 3'b100 +`define ERR_RESPONSE 3'b010 +`define RTY_RESPONSE 3'b001 +`define NO_RESPONSE 3'b000 Index: tags/rel_13/sim/rtl_sim/run/wave.do =================================================================== --- tags/rel_13/sim/rtl_sim/run/wave.do (nonexistent) +++ tags/rel_13/sim/rtl_sim/run/wave.do (revision 105) @@ -0,0 +1,591 @@ +// Signalscan Version 6.7p1 + + +define noactivityindicator +define analog waveform lines +define add variable default overlay off +define waveform window analogheight 1 +define terminal automatic +define buttons control \ + 1 opensimmulationfile \ + 2 executedofile \ + 3 designbrowser \ + 4 waveform \ + 5 source \ + 6 breakpoints \ + 7 definesourcessearchpath \ + 8 exit \ + 9 createbreakpoint \ + 10 creategroup \ + 11 createmarker \ + 12 closesimmulationfile \ + 13 renamesimmulationfile \ + 14 replacesimulationfiledata \ + 15 listopensimmulationfiles \ + 16 savedofile +define buttons waveform \ + 1 undo \ + 2 cut \ + 3 copy \ + 4 paste \ + 5 delete \ + 6 zoomin \ + 7 zoomout \ + 8 zoomoutfull \ + 9 expand \ + 10 createmarker \ + 11 designbrowser:1 \ + 12 variableradixbinary \ + 13 variableradixoctal \ + 14 variableradixdecimal \ + 15 variableradixhexadecimal \ + 16 variableradixascii +define buttons designbrowser \ + 1 undo \ + 2 cut \ + 3 copy \ + 4 paste \ + 5 delete \ + 6 cdupscope \ + 7 getallvariables \ + 8 getdeepallvariables \ + 9 addvariables \ + 10 addvarsandclosewindow \ + 11 closewindow \ + 12 scopefiltermodule \ + 13 scopefiltertask \ + 14 scopefilterfunction \ + 15 scopefilterblock \ + 16 scopefilterprimitive +define buttons event \ + 1 undo \ + 2 cut \ + 3 copy \ + 4 paste \ + 5 delete \ + 6 move \ + 7 closewindow \ + 8 duplicate \ + 9 defineasrisingedge \ + 10 defineasfallingedge \ + 11 defineasanyedge \ + 12 variableradixbinary \ + 13 variableradixoctal \ + 14 variableradixdecimal \ + 15 variableradixhexadecimal \ + 16 variableradixascii +define buttons source \ + 1 undo \ + 2 cut \ + 3 copy \ + 4 paste \ + 5 delete \ + 6 createbreakpoint \ + 7 creategroup \ + 8 createmarker \ + 9 createevent \ + 10 createregisterpage \ + 11 closewindow \ + 12 opensimmulationfile \ + 13 closesimmulationfile \ + 14 renamesimmulationfile \ + 15 replacesimulationfiledata \ + 16 listopensimmulationfiles +define buttons register \ + 1 undo \ + 2 cut \ + 3 copy \ + 4 paste \ + 5 delete \ + 6 createregisterpage \ + 7 closewindow \ + 8 continuefor \ + 9 continueuntil \ + 10 continueforever \ + 11 stop \ + 12 previous \ + 13 next \ + 14 variableradixbinary \ + 15 variableradixhexadecimal \ + 16 variableradixascii +define show related transactions +define exit prompt +define event search direction forward +define variable nofullhierarchy +define variable nofilenames +define variable nofullpathfilenames +include bookmark with filenames +include scope history without filenames +define waveform window listpane 5.97 +define waveform window namepane 13.98 +define multivalueindication +define pattern curpos dot +define pattern cursor1 dot +define pattern cursor2 dot +define pattern marker dot +define print designer "Igor Mohor" +define print border +define print color blackonwhite +define print command "/usr/ucb/lpr -P%P" +define print printer lp +define print range visible +define print variable visible +define rise fall time low threshold percentage 10 +define rise fall time high threshold percentage 90 +define rise fall time low value 0 +define rise fall time high value 3.3 +define sendmail command "/usr/lib/sendmail" +define sequence time width 30.00 +define snap + +define source noprompt +define time units default +define userdefinedbussymbol +define user guide directory "/usr/local/designacc/signalscan-6.7p1/doc/html" +define waveform window grid off +define waveform window waveheight 14 +define waveform window wavespace 6 +define web browser command netscape +define zoom outfull on initial add off +add group \ + tap_top \ + dbg_tb.debug_wishbone_set_addr.i's \ + dbg_tb.i_tap_top.tck_pad_i \ + dbg_tb.i_tap_top.tms_pad_i \ + dbg_tb.i_tap_top.tdi_pad_i \ + dbg_tb.i_tap_top.tms_reset \ + dbg_tb.i_tap_top.tdo_pad_o \ + dbg_tb.i_tap_top.tdo_padoe_o \ + dbg_tb.i_tap_top.idcode_tdo \ + dbg_tb.i_tap_top.test_logic_reset \ + dbg_tb.i_tap_top.run_test_idle \ + dbg_tb.i_tap_top.select_dr_scan \ + dbg_tb.i_tap_top.capture_dr \ + dbg_tb.i_tap_top.shift_dr \ + dbg_tb.i_tap_top.exit1_dr \ + dbg_tb.i_tap_top.pause_dr \ + dbg_tb.i_tap_top.exit2_dr \ + dbg_tb.i_tap_top.update_dr \ + dbg_tb.i_tap_top.select_ir_scan \ + dbg_tb.i_tap_top.capture_ir \ + dbg_tb.i_tap_top.shift_ir \ + dbg_tb.i_tap_top.exit1_ir \ + dbg_tb.i_tap_top.pause_ir \ + dbg_tb.i_tap_top.exit2_ir \ + dbg_tb.i_tap_top.update_ir \ + dbg_tb.i_tap_top.bypass_reg \ + dbg_tb.i_tap_top.bypass_select \ + dbg_tb.i_tap_top.bypassed_tdo \ + dbg_tb.i_tap_top.debug_select \ + dbg_tb.i_tap_top.extest_select \ + dbg_tb.i_tap_top.idcode_reg[31:0]'h \ + dbg_tb.i_tap_top.idcode_select \ + dbg_tb.i_tap_top.idcode_tdo \ + dbg_tb.i_tap_top.instruction_tdo \ + dbg_tb.i_tap_top.jtag_ir[3:0]'h \ + dbg_tb.i_tap_top.latched_jtag_ir[3:0]'h \ + dbg_tb.i_tap_top.mbist_select \ + dbg_tb.i_tap_top.sample_preload_select \ + dbg_tb.i_tap_top.trst_pad_i \ + dbg_tb.i_tap_top.tck_pad_i \ + +add group \ + dbg_top \ + dbg_tb.i_dbg_top.current_on_tdo[799:0]'a \ + dbg_tb.i_dbg_top.chain_select \ + dbg_tb.i_dbg_top.chain_select_error \ + dbg_tb.i_dbg_top.chain_select \ + dbg_tb.i_dbg_top.crc_cnt_end \ + dbg_tb.i_dbg_top.crc_cnt_end_q \ + dbg_tb.i_dbg_top.crc_cnt_end_q2 \ + dbg_tb.i_dbg_top.data_cnt[2:0]'h \ + dbg_tb.i_dbg_top.data_cnt_end \ + dbg_tb.i_dbg_top.crc_cnt[5:0]'h \ + dbg_tb.i_dbg_top.crc_cnt_end \ + dbg_tb.i_dbg_top.crc_match \ + dbg_tb.i_dbg_top.data_cnt_end \ + dbg_tb.i_dbg_top.debug_select_i \ + dbg_tb.i_dbg_top.shift_dr_i \ + dbg_tb.i_dbg_top.status_cnt[2:0]'h \ + dbg_tb.i_dbg_top.status_cnt_end \ + dbg_tb.i_dbg_top.tck_i \ + dbg_tb.i_dbg_top.tdi_i \ + dbg_tb.i_dbg_top.tdo_o \ + dbg_tb.i_dbg_top.update_dr_i \ + dbg_tb.i_dbg_top.wishbone_scan_chain \ + dbg_tb.i_dbg_top.wishbone_ce \ + dbg_tb.i_dbg_top.crc_en \ + dbg_tb.i_dbg_top.crc_en_dbg \ + dbg_tb.i_dbg_top.crc_en_wb \ + +add group \ + crc_out \ + dbg_tb.i_dbg_top.i_dbg_crc32_d1_out.clk \ + dbg_tb.i_dbg_top.i_dbg_crc32_d1_out.crc[31:0]'h \ + dbg_tb.i_dbg_top.i_dbg_crc32_d1_out.crc_match \ + dbg_tb.i_dbg_top.i_dbg_crc32_d1_out.crc_out \ + dbg_tb.i_dbg_top.i_dbg_crc32_d1_out.data \ + dbg_tb.i_dbg_top.i_dbg_crc32_d1_out.enable \ + dbg_tb.i_dbg_top.i_dbg_crc32_d1_out.shift \ + dbg_tb.i_dbg_top.i_dbg_crc32_d1_out.new_crc[31:0]'h \ + dbg_tb.i_dbg_top.i_dbg_crc32_d1_out.rst \ + dbg_tb.i_dbg_top.i_dbg_crc32_d1_out.sync_rst \ + +add group \ + crc_in \ + dbg_tb.i_dbg_top.i_dbg_crc32_d1_in.clk \ + dbg_tb.i_dbg_top.i_dbg_crc32_d1_in.crc_match \ + dbg_tb.i_dbg_top.i_dbg_crc32_d1_in.data \ + dbg_tb.i_dbg_top.i_dbg_crc32_d1_in.enable \ + dbg_tb.i_dbg_top.i_dbg_crc32_d1_in.new_crc[31:0]'h \ + dbg_tb.i_dbg_top.i_dbg_crc32_d1_in.rst \ + dbg_tb.i_dbg_top.i_dbg_crc32_d1_in.shift \ + dbg_tb.i_dbg_top.i_dbg_crc32_d1_in.sync_rst \ + dbg_tb.i_dbg_top.i_dbg_crc32_d1_in.crc[31:0]'h \ + +add group \ + tttmp \ + dbg_tb.i_dbg_top.i_dbg_wb.cmd_cnt[1:0]'h \ + dbg_tb.i_dbg_top.i_dbg_wb.cmd_cnt_end \ + dbg_tb.i_dbg_top.i_dbg_wb.data_cnt[5:0]'d \ + dbg_tb.i_dbg_top.i_dbg_wb.data_cnt_end \ + dbg_tb.i_dbg_top.i_dbg_wb.crc_cnt[5:0]'d \ + dbg_tb.i_dbg_top.i_dbg_wb.crc_cnt_end \ + +add group \ + wishbone \ + dbg_tb.i_dbg_top.tdi_i \ + dbg_tb.test_text[99:0]'a \ + dbg_tb.i_dbg_top.i_dbg_wb.len[15:0]'d \ + dbg_tb.i_dbg_top.i_dbg_wb.adr[31:0]'h \ + dbg_tb.i_dbg_top.i_dbg_wb.cmd[2:0]'h \ + dbg_tb.i_dbg_top.i_dbg_wb.cmd_old[2:0]'h \ + dbg_tb.i_dbg_top.i_dbg_wb.enable \ + dbg_tb.i_dbg_top.i_dbg_wb.cmd_cnt[1:0]'h \ + dbg_tb.i_dbg_top.i_dbg_wb.addr_len_cnt[5:0]'d \ + dbg_tb.i_dbg_top.i_dbg_wb.addr_len_cnt_end \ + dbg_tb.i_dbg_top.i_dbg_wb.data_cnt[18:0]'d \ + dbg_tb.i_dbg_top.i_dbg_wb.data_cnt_end \ + dbg_tb.i_dbg_top.i_dbg_wb.crc_cnt[5:0]'d \ + dbg_tb.i_dbg_top.i_dbg_wb.crc_cnt_end \ + dbg_tb.i_dbg_top.i_dbg_wb.write_cycle \ + dbg_tb.i_dbg_top.i_dbg_wb.read_cycle \ + dbg_tb.i_dbg_top.i_dbg_wb.len[15:0]'h \ + dbg_tb.i_dbg_top.i_dbg_wb.pause_dr_i \ + dbg_tb.i_dbg_top.i_dbg_wb.cmd_cnt_end \ + dbg_tb.i_dbg_top.i_dbg_wb.data_cnt_end \ + dbg_tb.i_dbg_top.i_dbg_wb.addr_len_cnt_end \ + dbg_tb.i_dbg_top.i_dbg_wb.data_cnt_end \ + dbg_tb.i_dbg_top.i_dbg_wb.shift_dr_i \ + dbg_tb.i_dbg_top.i_dbg_wb.wb_error_tck \ + dbg_tb.i_dbg_top.i_dbg_wb.status[3:0]'h \ + dbg_tb.i_dbg_top.i_dbg_wb.status_cnt_end \ + dbg_tb.i_dbg_top.i_dbg_wb.status_reset_en \ + dbg_tb.i_dbg_top.i_dbg_wb.cmd[2:0]'h \ + dbg_tb.i_dbg_top.i_dbg_wb.cmd[2:0]'h \ + dbg_tb.i_dbg_top.i_dbg_wb.len[15:0]'h \ + dbg_tb.i_dbg_top.i_dbg_wb.adr[31:0]'h \ + dbg_tb.i_dbg_top.i_dbg_wb.dr[50:0]'h \ + dbg_tb.i_dbg_top.i_dbg_wb.addr_len_cnt_limit[5:0]'d \ + dbg_tb.i_dbg_top.i_dbg_wb.byte \ + dbg_tb.i_dbg_top.i_dbg_wb.half \ + dbg_tb.i_dbg_top.i_dbg_wb.long \ + dbg_tb.i_dbg_top.i_dbg_wb.start_wr_tck \ + dbg_tb.i_dbg_top.i_dbg_wb.cmd[2:0]'h \ + dbg_tb.i_dbg_top.i_dbg_wb.data_cnt_limit[18:0]'d \ + dbg_tb.i_dbg_top.i_dbg_wb.dr[50:0]'h \ + dbg_tb.i_dbg_top.i_dbg_wb.cmd_cnt_end \ + dbg_tb.i_dbg_top.i_dbg_wb.crc_cnt_end \ + dbg_tb.i_dbg_top.i_dbg_wb.wb_error \ + dbg_tb.i_dbg_top.i_dbg_wb.wb_error_sync \ + dbg_tb.i_dbg_top.i_dbg_wb.wb_error_tck \ + dbg_tb.i_dbg_top.i_dbg_wb.status_reset_en \ + dbg_tb.i_dbg_top.i_dbg_wb.tck_i \ + dbg_tb.i_dbg_top.i_dbg_wb.tdo_o \ + dbg_tb.i_dbg_top.i_dbg_wb.update_dr_i \ + dbg_tb.i_dbg_top.i_dbg_wb.set_addr \ + dbg_tb.i_dbg_top.i_dbg_wb.set_addr_sync \ + dbg_tb.i_dbg_top.i_dbg_wb.len[15:0]'h \ + dbg_tb.i_dbg_top.i_dbg_wb.data_cnt_limit[18:0]'h \ + dbg_tb.i_dbg_top.i_dbg_wb.set_addr_wb \ + dbg_tb.i_dbg_top.i_dbg_wb.set_addr_wb_q \ + dbg_tb.i_dbg_top.i_dbg_wb.adr[31:0]'h \ + dbg_tb.i_dbg_top.i_dbg_wb.cmd_write \ + dbg_tb.i_dbg_top.i_dbg_wb.cmd_read \ + dbg_tb.i_dbg_top.i_dbg_wb.crc_cnt_end \ + dbg_tb.i_dbg_top.i_dbg_wb.crc_cnt_end_q \ + dbg_tb.i_dbg_top.i_dbg_wb.crc_match_i \ + dbg_tb.i_dbg_top.i_dbg_wb.wb_ack_i \ + dbg_tb.i_dbg_top.i_dbg_wb.wb_cti_o[2:0]'h \ + dbg_tb.i_dbg_top.i_dbg_wb.ptr[1:0]'h \ + dbg_tb.i_dbg_top.i_dbg_wb.wb_cyc_o \ + dbg_tb.i_dbg_top.i_dbg_wb.wb_adr_o[31:0]'h \ + dbg_tb.i_dbg_top.i_dbg_wb.wb_dat_i[31:0]'h \ + dbg_tb.i_dbg_top.i_dbg_wb.input_data[31:0]'h \ + dbg_tb.i_dbg_top.i_dbg_wb.wb_dat_o[31:0]'h \ + dbg_tb.i_dbg_top.i_dbg_wb.wb_err_i \ + dbg_tb.i_dbg_top.i_dbg_wb.wb_sel_o[3:0]'h \ + dbg_tb.i_dbg_top.i_dbg_wb.wb_stb_o \ + dbg_tb.i_dbg_top.i_dbg_wb.wb_we_o \ + dbg_tb.i_dbg_top.i_dbg_wb.wishbone_ce_i \ + dbg_tb.i_dbg_top.i_dbg_wb.wb_overrun \ + dbg_tb.i_dbg_top.i_dbg_wb.wb_overrun_sync \ + dbg_tb.i_dbg_top.i_dbg_wb.wb_overrun_tck \ + dbg_tb.i_dbg_top.i_dbg_wb.status_reset_en \ + dbg_tb.i_dbg_top.i_dbg_wb.read_cycle \ + dbg_tb.i_dbg_top.i_dbg_wb.write_cycle \ + dbg_tb.i_dbg_top.i_dbg_wb.crc_en_o \ + dbg_tb.i_dbg_top.i_dbg_wb.crc_cnt_end \ + dbg_tb.i_dbg_top.i_dbg_wb.status_cnt_end \ + dbg_tb.i_dbg_top.i_dbg_wb.status_cnt1 \ + dbg_tb.i_dbg_top.tdi_i \ + dbg_tb.i_dbg_top.i_dbg_wb.tdo_o \ + dbg_tb.i_dbg_top.i_dbg_wb.crc_cnt[5:0]'h \ + dbg_tb.i_dbg_top.i_dbg_wb.data_cnt[18:0]'d \ + dbg_tb.i_dbg_top.i_dbg_wb.data_cnt_end \ + dbg_tb.i_dbg_top.i_dbg_wb.crc_en_o \ + dbg_tb.test_text[99:0]'a \ + dbg_tb.i_dbg_top.i_dbg_wb.cmd_write \ + dbg_tb.i_dbg_top.i_dbg_wb.dr_go_latched \ + dbg_tb.i_dbg_top.i_dbg_wb.read_cycle \ + dbg_tb.i_dbg_top.i_dbg_wb.len[15:0]'h \ + dbg_tb.i_dbg_top.i_dbg_wb.write_cycle \ + dbg_tb.i_dbg_top.i_dbg_wb.byte \ + dbg_tb.i_dbg_top.i_dbg_wb.half \ + dbg_tb.i_dbg_top.i_dbg_wb.long \ + dbg_tb.i_dbg_top.i_dbg_wb.input_data[31:0]'h \ + { \ + dr[31:0] descendingorder \ + dbg_tb.i_dbg_top.i_dbg_wb.dr[31] \ + dbg_tb.i_dbg_top.i_dbg_wb.dr[30] \ + dbg_tb.i_dbg_top.i_dbg_wb.dr[29] \ + dbg_tb.i_dbg_top.i_dbg_wb.dr[28] \ + dbg_tb.i_dbg_top.i_dbg_wb.dr[27] \ + dbg_tb.i_dbg_top.i_dbg_wb.dr[26] \ + dbg_tb.i_dbg_top.i_dbg_wb.dr[25] \ + dbg_tb.i_dbg_top.i_dbg_wb.dr[24] \ + dbg_tb.i_dbg_top.i_dbg_wb.dr[23] \ + dbg_tb.i_dbg_top.i_dbg_wb.dr[22] \ + dbg_tb.i_dbg_top.i_dbg_wb.dr[21] \ + dbg_tb.i_dbg_top.i_dbg_wb.dr[20] \ + dbg_tb.i_dbg_top.i_dbg_wb.dr[19] \ + dbg_tb.i_dbg_top.i_dbg_wb.dr[18] \ + dbg_tb.i_dbg_top.i_dbg_wb.dr[17] \ + dbg_tb.i_dbg_top.i_dbg_wb.dr[16] \ + dbg_tb.i_dbg_top.i_dbg_wb.dr[15] \ + dbg_tb.i_dbg_top.i_dbg_wb.dr[14] \ + dbg_tb.i_dbg_top.i_dbg_wb.dr[13] \ + dbg_tb.i_dbg_top.i_dbg_wb.dr[12] \ + dbg_tb.i_dbg_top.i_dbg_wb.dr[11] \ + dbg_tb.i_dbg_top.i_dbg_wb.dr[10] \ + dbg_tb.i_dbg_top.i_dbg_wb.dr[9] \ + dbg_tb.i_dbg_top.i_dbg_wb.dr[8] \ + dbg_tb.i_dbg_top.i_dbg_wb.dr[7] \ + dbg_tb.i_dbg_top.i_dbg_wb.dr[6] \ + dbg_tb.i_dbg_top.i_dbg_wb.dr[5] \ + dbg_tb.i_dbg_top.i_dbg_wb.dr[4] \ + dbg_tb.i_dbg_top.i_dbg_wb.dr[3] \ + dbg_tb.i_dbg_top.i_dbg_wb.dr[2] \ + dbg_tb.i_dbg_top.i_dbg_wb.dr[1] \ + dbg_tb.i_dbg_top.i_dbg_wb.dr[0] \ + }'h \ + dbg_tb.i_dbg_top.i_dbg_wb.ptr[1:0]'h \ + dbg_tb.i_dbg_top.i_dbg_wb.wb_cyc_o \ + dbg_tb.i_dbg_top.i_dbg_wb.wb_ack_i \ + dbg_tb.i_dbg_top.i_dbg_wb.wb_sel_o[3:0]'h \ + dbg_tb.i_dbg_top.i_dbg_wb.wb_dat_i[31:0]'h \ + dbg_tb.i_dbg_top.i_dbg_wb.start_rd_tck \ + dbg_tb.i_dbg_top.i_dbg_wb.rd_tck_started \ + dbg_tb.i_dbg_top.i_dbg_wb.wb_end_tck \ + dbg_tb.i_dbg_top.i_dbg_wb.rw_type[2:0]'h \ + dbg_tb.i_dbg_top.i_dbg_wb.read_cycle \ + dbg_tb.i_dbg_top.i_dbg_wb.crc_cnt_31 \ + dbg_tb.i_dbg_top.i_dbg_wb.rw_type[2:0]'h \ + dbg_tb.i_dbg_top.i_dbg_wb.fifo_cnt[2:0]'h \ + dbg_tb.i_dbg_top.i_dbg_wb.fifo_empty \ + dbg_tb.i_dbg_top.i_dbg_wb.fifo_full \ + dbg_tb.i_dbg_top.i_dbg_wb.latch_data \ + dbg_tb.i_dbg_top.i_dbg_wb.underrun_tck \ + dbg_tb.i_dbg_top.i_dbg_wb.wb_end_tck \ + dbg_tb.i_dbg_top.i_dbg_wb.wb_end_tck_q \ + dbg_tb.i_dbg_top.i_dbg_wb.latch_data \ + dbg_tb.i_dbg_top.i_dbg_wb.len[15:0]'h \ + +add group \ + cpu_debug \ + dbg_tb.test_text[199:0]'a \ + dbg_tb.i_tap_top.tdi_pad_i \ + dbg_tb.i_dbg_top.i_dbg_cpu.tdo_o \ + dbg_tb.i_dbg_top.i_dbg_cpu.tdo_text[799:0]'a \ + dbg_tb.i_dbg_top.i_dbg_cpu.crc_en_o \ + dbg_tb.i_dbg_top.i_dbg_cpu.shift_crc_o \ + dbg_tb.i_dbg_top.i_dbg_cpu.status[3:0]'h \ + dbg_tb.i_dbg_top.i_dbg_cpu.status_text[199:0]'a \ + dbg_tb.i_dbg_top.i_dbg_cpu.latching_data_text[199:0]'a \ + dbg_tb.i_dbg_top.i_dbg_cpu.dr[31] \ + dbg_tb.i_dbg_top.i_dbg_cpu.cpu_stall_o \ + dbg_tb.i_dbg_top.i_dbg_cpu.cpu_stb_o \ + dbg_tb.i_dbg_top.i_dbg_cpu.cpu_we_o \ + dbg_tb.i_dbg_top.i_dbg_cpu.cpu_data_o[31:0]'h \ + dbg_tb.i_dbg_top.i_dbg_cpu.cpu_data_i[31:0]'h \ + dbg_tb.i_dbg_top.i_dbg_cpu.cpu_ack_i \ + dbg_tb.i_dbg_top.i_dbg_cpu.cpu_stb \ + dbg_tb.i_dbg_top.i_dbg_cpu.cpu_stb_sync \ + dbg_tb.i_dbg_top.i_dbg_cpu.cpu_stb_o \ + dbg_tb.i_dbg_top.i_dbg_cpu.cpu_ack_i \ + dbg_tb.i_dbg_top.i_dbg_cpu.cpu_ack_sync \ + dbg_tb.i_dbg_top.i_dbg_cpu.cpu_ack_tck \ + dbg_tb.i_dbg_top.cpu_debug_scan_chain \ + dbg_tb.i_dbg_top.i_dbg_cpu.cpu_ce_i \ + dbg_tb.i_dbg_top.i_dbg_cpu.crc_en_o \ + dbg_tb.i_dbg_top.i_dbg_cpu.crc_match_i \ + dbg_tb.i_dbg_top.i_dbg_cpu.pause_dr_i \ + dbg_tb.i_dbg_top.i_dbg_cpu.rst_i \ + dbg_tb.i_dbg_top.i_dbg_cpu.shift_crc_o \ + dbg_tb.i_dbg_top.i_dbg_cpu.shift_dr_i \ + dbg_tb.i_dbg_top.i_dbg_cpu.tck_i \ + dbg_tb.i_dbg_top.i_dbg_cpu.tdi_i \ + dbg_tb.i_dbg_top.i_dbg_cpu.tdo_o \ + dbg_tb.i_dbg_top.i_dbg_cpu.update_dr_i \ + dbg_tb.i_dbg_top.i_dbg_cpu.cmd_cnt_en \ + dbg_tb.i_dbg_top.i_dbg_cpu.cmd_cnt_end \ + dbg_tb.i_dbg_top.i_dbg_cpu.addr_cnt_en \ + dbg_tb.i_dbg_top.i_dbg_cpu.addr_cnt_end \ + dbg_tb.i_dbg_top.i_dbg_cpu.crc_cnt_en \ + dbg_tb.i_dbg_top.i_dbg_cpu.crc_cnt_end \ + dbg_tb.i_dbg_top.i_dbg_cpu.cmd_cnt[1:0]'h \ + dbg_tb.i_dbg_top.i_dbg_cpu.addr_cnt[5:0]'h \ + dbg_tb.i_dbg_top.i_dbg_cpu.data_cnt[5:0]'h \ + dbg_tb.i_dbg_top.i_dbg_cpu.data_cnt_en \ + dbg_tb.i_dbg_top.i_dbg_cpu.data_cnt_end \ + dbg_tb.i_dbg_top.i_dbg_cpu.crc_cnt[5:0]'h \ + dbg_tb.i_dbg_top.i_dbg_cpu.addr_cnt_limit[5:0]'h \ + dbg_tb.i_dbg_top.i_dbg_cpu.data_cnt_limit[5:0]'h \ + dbg_tb.i_dbg_top.i_dbg_cpu.status_cnt1 \ + dbg_tb.i_dbg_top.i_dbg_cpu.status_cnt2 \ + dbg_tb.i_dbg_top.i_dbg_cpu.status_cnt3 \ + dbg_tb.i_dbg_top.i_dbg_cpu.status_cnt4 \ + dbg_tb.i_dbg_top.i_dbg_cpu.status_cnt_end \ + dbg_tb.i_dbg_top.i_dbg_cpu.adr[31:0]'h \ + dbg_tb.i_dbg_top.i_dbg_cpu.set_addr \ + dbg_tb.i_dbg_top.i_dbg_cpu.reg_access \ + dbg_tb.i_dbg_top.i_dbg_cpu.dr[34:0]'h \ + dbg_tb.i_dbg_top.i_dbg_cpu.latching_data_text[199:0]'a \ + dbg_tb.i_dbg_top.i_dbg_cpu.read_cycle \ + dbg_tb.i_dbg_top.i_dbg_cpu.read_cycle_reg \ + dbg_tb.i_dbg_top.i_dbg_cpu.reg_access \ + dbg_tb.i_dbg_top.cpu_sel_o[1:0]'h \ + dbg_tb.i_dbg_top.cpu_stall_o \ + dbg_tb.i_dbg_top.i_dbg_cpu.write_cycle \ + dbg_tb.i_dbg_top.i_dbg_cpu.addr_cnt_end \ + dbg_tb.i_dbg_top.i_dbg_cpu.cmd_cnt_end \ + dbg_tb.i_dbg_top.i_dbg_cpu.data_cnt_end \ + dbg_tb.i_dbg_top.i_dbg_cpu.read_cycle \ + dbg_tb.i_dbg_top.i_dbg_cpu.crc_cnt_end \ + dbg_tb.i_dbg_top.i_dbg_cpu.data_cnt_limit[5:0]'h \ + dbg_tb.i_dbg_top.i_dbg_cpu.data_cnt[5:0]'h \ + dbg_tb.i_dbg_top.cpu_ack_i \ + dbg_tb.i_dbg_top.cpu_addr_o[31:0]'h \ + dbg_tb.i_dbg_top.cpu_bp_i \ + dbg_tb.i_dbg_top.cpu_clk_i \ + dbg_tb.i_dbg_top.cpu_data_i[31:0]'h \ + dbg_tb.i_dbg_top.cpu_data_o[31:0]'h \ + dbg_tb.i_dbg_top.cpu_sel_o[1:0]'h \ + dbg_tb.i_dbg_top.cpu_stall_all_o \ + dbg_tb.i_dbg_top.cpu_stall_o \ + dbg_tb.i_dbg_top.i_dbg_cpu.cpu_stb \ + dbg_tb.i_dbg_top.i_dbg_cpu.cpu_ack_i \ + dbg_tb.i_dbg_top.i_dbg_cpu.cpu_stb_sync \ + dbg_tb.i_dbg_top.cpu_stb_o \ + dbg_tb.i_dbg_top.cpu_we_o \ + +add group \ + registers \ + dbg_tb.i_dbg_top.i_dbg_cpu.i_dbg_cpu_registers.addr_i[1:0]'h \ + dbg_tb.i_dbg_top.i_dbg_cpu.i_dbg_cpu_registers.bp_i \ + dbg_tb.i_dbg_top.i_dbg_cpu.i_dbg_cpu_registers.clk_i \ + dbg_tb.i_dbg_top.i_dbg_cpu.i_dbg_cpu_registers.cpu_clk_i \ + dbg_tb.i_dbg_top.i_dbg_cpu.i_dbg_cpu_registers.cpu_sel_o[1:0]'h \ + dbg_tb.i_dbg_top.i_dbg_cpu.i_dbg_cpu_registers.cpu_stall_all_o \ + dbg_tb.i_dbg_top.i_dbg_cpu.i_dbg_cpu_registers.cpu_stall_o \ + dbg_tb.i_dbg_top.i_dbg_cpu.i_dbg_cpu_registers.data_i[7:0]'h \ + dbg_tb.i_dbg_top.i_dbg_cpu.i_dbg_cpu_registers.data_o[7:0]'h \ + dbg_tb.i_dbg_top.i_dbg_cpu.i_dbg_cpu_registers.en_i \ + dbg_tb.i_dbg_top.i_dbg_cpu.i_dbg_cpu_registers.cpusel_wr \ + dbg_tb.i_dbg_top.i_dbg_cpu.i_dbg_cpu_registers.cpusel_wr_sync \ + dbg_tb.i_dbg_top.i_dbg_cpu.i_dbg_cpu_registers.cpusel_wr_cpu \ + dbg_tb.i_dbg_top.i_dbg_cpu.i_dbg_cpu_registers.rst_i \ + dbg_tb.i_dbg_top.i_dbg_cpu.i_dbg_cpu_registers.we_i \ + +add group \ + cpu_behav \ + dbg_tb.i_cpu_behavioral.cpu_ack_o \ + dbg_tb.i_cpu_behavioral.cpu_addr_i[31:0]'h \ + dbg_tb.i_cpu_behavioral.cpu_bp_o \ + dbg_tb.i_cpu_behavioral.cpu_clk_o \ + dbg_tb.i_cpu_behavioral.cpu_data_i[31:0]'h \ + dbg_tb.i_cpu_behavioral.cpu_data_o[31:0]'h \ + dbg_tb.i_cpu_behavioral.cpu_sel_i[1:0]'h \ + dbg_tb.i_cpu_behavioral.cpu_stall_all_i \ + dbg_tb.i_cpu_behavioral.cpu_stall_i \ + dbg_tb.i_cpu_behavioral.cpu_stb_i \ + dbg_tb.i_cpu_behavioral.cpu_we_i \ + +add group \ + tmp \ + dbg_tb.i_dbg_top.i_dbg_wb.wb_clk_i \ + dbg_tb.i_dbg_top.i_dbg_wb.tck_i \ + dbg_tb.i_dbg_top.i_dbg_wb.wb_cyc_o \ + dbg_tb.i_dbg_top.i_dbg_wb.wb_ack_i \ + dbg_tb.i_dbg_top.i_dbg_wb.busy_wb \ + dbg_tb.i_dbg_top.i_dbg_wb.busy_sync \ + dbg_tb.i_dbg_top.i_dbg_wb.busy_tck \ + dbg_tb.i_dbg_top.i_dbg_wb.tdo_o \ + dbg_tb.i_dbg_top.pause_dr_i \ + dbg_tb.i_dbg_top.i_dbg_wb.shift_dr_i \ + dbg_tb.tdo_pad_o \ + dbg_tb.tdo_padoe_o \ + dbg_tb.tdo \ + dbg_tb.i_dbg_top.shift_crc_wb \ + dbg_tb.i_dbg_top.wishbone_ce \ + +add group \ + tdo_tap_top \ + dbg_tb.i_tap_top.tdi_pad_i \ + dbg_tb.i_tap_top.tdo_o \ + "tdo_o je vhod v dbg tdi_i" \ + ( \ + comment \ + ) \ + dbg_tb.i_tap_top.tdo_pad_o \ + dbg_tb.i_tap_top.tdo_padoe_o \ + dbg_tb.i_tap_top.data_tdo \ + dbg_tb.i_tap_top.idcode_tdo \ + dbg_tb.i_tap_top.bypassed_tdo \ + dbg_tb.i_tap_top.instruction_tdo \ + +add group \ + tdo_dbg_top \ + dbg_tb.i_dbg_top.tdi_i \ + dbg_tb.i_dbg_top.tdo_wb \ + "tdo_wb jw vhod v wb tdi_i" \ + ( \ + comment \ + ) \ + dbg_tb.i_dbg_top.tdi_wb \ + dbg_tb.i_dbg_top.tdo_o \ + dbg_tb.i_dbg_top.crc_out \ + +add group \ + tdo_wb \ + dbg_tb.i_dbg_top.i_dbg_wb.tdi_i \ + dbg_tb.i_dbg_top.i_dbg_wb.tdo_o \ + "tdo_o gre na dbg tdi_wb" \ + ( \ + comment \ + ) \ + + +deselect all +open window waveform 1 geometry 10 60 1592 1139 +zoom at 631005(0)ns 0.00123035 0.00000000
tags/rel_13/sim/rtl_sim/run/wave.do Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/rel_13/sim/rtl_sim/run/run_sim.scr =================================================================== --- tags/rel_13/sim/rtl_sim/run/run_sim.scr (nonexistent) +++ tags/rel_13/sim/rtl_sim/run/run_sim.scr (revision 105) @@ -0,0 +1,91 @@ +#!/bin/csh -f + +if ( $# < 1 ) then + echo "First argument must be a top level module name!" + exit +else + set SIM_TOP = $1 +endif + +set current_par = 1 +set output_waveform = 0 +while ( $current_par < $# ) + @ current_par = $current_par + 1 + case wave: + @ output_waveform = 1 + breaksw + default: + echo 'Unknown option "'$argv[$current_par]'"!' + exit + breaksw + endsw +end + +echo "-CDSLIB ../bin/cds.lib" > ncvlog.args +echo "-HDLVAR ../bin/hdl.var" >> ncvlog.args +echo "-MESSAGES" >> ncvlog.args +echo "-INCDIR ../../../bench/verilog" >> ncvlog.args +echo "-INCDIR ../../../rtl/verilog" >> ncvlog.args +echo "-INCDIR ../../../../jtag/tap/rtl/verilog" >> ncvlog.args +echo "-NOCOPYRIGHT" >> ncvlog.args +echo "-LOGFILE ../log/ncvlog.log" >> ncvlog.args + + +#foreach filename ( `cat ../bin/rtl_file_list` ) +# echo "../../../rtl/verilog/"$filename >> ncvlog.args +#end +# +#foreach filename ( `cat ../bin/sim_file_list` ) +# echo "../../../bench/verilog/"$filename >> ncvlog.args +#end + + +# RTL files +echo "../../../rtl/verilog/dbg_crc32_d1.v" >> ncvlog.args +echo "../../../rtl/verilog/dbg_wb.v" >> ncvlog.args +echo "../../../rtl/verilog/dbg_register.v" >> ncvlog.args +echo "../../../rtl/verilog/dbg_cpu_registers.v" >> ncvlog.args +echo "../../../rtl/verilog/dbg_cpu.v" >> ncvlog.args +echo "../../../rtl/verilog/dbg_top.v" >> ncvlog.args +echo "../../../../jtag/tap/rtl/verilog/tap_top.v" >> ncvlog.args + + +# Simulation files +echo "../../../bench/verilog/timescale.v" >> ncvlog.args +echo "../../../bench/verilog/wb_slave_behavioral.v" >> ncvlog.args +echo "../../../bench/verilog/cpu_behavioral.v" >> ncvlog.args +echo "../../../bench/verilog/dbg_tb.v" >> ncvlog.args + +ncvlog -f ncvlog.args + +echo "-MESSAGES" > ncelab.args +echo "-NOCOPYRIGHT" >> ncelab.args +echo "-CDSLIB ../bin/cds.lib" >> ncelab.args +echo "-HDLVAR ../bin/hdl.var" >> ncelab.args +echo "-LOGFILE ../log/ncelab.log" >> ncelab.args +echo "-SNAPSHOT worklib.bench:rtl" >> ncelab.args +echo "-NO_TCHK_MSG" >> ncelab.args +echo "-ACCESS +RWC" >> ncelab.args +echo worklib.$SIM_TOP >> ncelab.args + +ncelab -f ncelab.args + +echo "-MESSAGES" > ncsim.args +echo "-NOCOPYRIGHT" >> ncsim.args +echo "-CDSLIB ../bin/cds.lib" >> ncsim.args +echo "-HDLVAR ../bin/hdl.var" >> ncsim.args +echo "-INPUT ncsim.tcl" >> ncsim.args +echo "-LOGFILE ../log/ncsim.log" >> ncsim.args +echo "worklib.bench:rtl" >> ncsim.args + +if ( $output_waveform ) then + echo "database -open waves -shm -into ../out/waves.shm" > ./ncsim.tcl + echo "probe -create -database waves $SIM_TOP -shm -all -depth all" >> ./ncsim.tcl + echo "run" >> ./ncsim.tcl +else + echo "run" > ./ncsim.tcl +endif + +echo "quit" >> ncsim.tcl + +ncsim -LICQUEUE -f ./ncsim.args
tags/rel_13/sim/rtl_sim/run/run_sim.scr Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/rel_13/sim/rtl_sim/run/clean =================================================================== --- tags/rel_13/sim/rtl_sim/run/clean (nonexistent) +++ tags/rel_13/sim/rtl_sim/run/clean (revision 105) @@ -0,0 +1,4 @@ +rm ../bin/INCA_libs/worklib/* +rm ../bin/INCA_libs/worklib/.* +rm ../log/*.log +rm -rf ../out/*.shm
tags/rel_13/sim/rtl_sim/run/clean Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/rel_13/sim/rtl_sim/bin/INCA_libs/worklib/dir_keeper =================================================================== Index: tags/rel_13/sim/rtl_sim/bin/cds.lib =================================================================== --- tags/rel_13/sim/rtl_sim/bin/cds.lib (nonexistent) +++ tags/rel_13/sim/rtl_sim/bin/cds.lib (revision 105) @@ -0,0 +1,6 @@ +# +# cds.lib: Defines the locations of compiled libraries. +# Created by ncprep on Tue Jul 3 11:40:44 2001 +# + +define worklib ./INCA_libs/worklib
tags/rel_13/sim/rtl_sim/bin/cds.lib Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/rel_13/sim/rtl_sim/bin/hdl.var =================================================================== --- tags/rel_13/sim/rtl_sim/bin/hdl.var (nonexistent) +++ tags/rel_13/sim/rtl_sim/bin/hdl.var (revision 105) @@ -0,0 +1,9 @@ +# +# hdl.var: Defines variables used by the INCA tools. +# Created by ncprep on Tue Jul 3 11:40:44 2001 +# + +softinclude $CDS_INST_DIR/tools/inca/files/hdl.var + +define LIB_MAP ( $LIB_MAP, + => worklib ) +define VIEW_MAP ( $VIEW_MAP, .v => v)
tags/rel_13/sim/rtl_sim/bin/hdl.var Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/rel_13/sim/rtl_sim/log/dir_keeper =================================================================== --- tags/rel_13/sim/rtl_sim/log/dir_keeper (nonexistent) +++ tags/rel_13/sim/rtl_sim/log/dir_keeper (revision 105) @@ -0,0 +1 @@ +Only keeper of empty directories
tags/rel_13/sim/rtl_sim/log/dir_keeper Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/rel_13/sim/rtl_sim/out/dir_keeper =================================================================== --- tags/rel_13/sim/rtl_sim/out/dir_keeper (nonexistent) +++ tags/rel_13/sim/rtl_sim/out/dir_keeper (revision 105) @@ -0,0 +1 @@ +Only keeper of empty directories
tags/rel_13/sim/rtl_sim/out/dir_keeper Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/rel_13/doc/DbgSupp.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: tags/rel_13/doc/DbgSupp.pdf =================================================================== --- tags/rel_13/doc/DbgSupp.pdf (nonexistent) +++ tags/rel_13/doc/DbgSupp.pdf (revision 105)
tags/rel_13/doc/DbgSupp.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: tags/rel_13/doc/src/DbgSupp.doc =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: tags/rel_13/doc/src/DbgSupp.doc =================================================================== --- tags/rel_13/doc/src/DbgSupp.doc (nonexistent) +++ tags/rel_13/doc/src/DbgSupp.doc (revision 105)
tags/rel_13/doc/src/DbgSupp.doc Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: tags/rel_13/doc/src/Debug Support Datasheet (prl.).doc =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: tags/rel_13/doc/src/Debug Support Datasheet (prl.).doc =================================================================== --- tags/rel_13/doc/src/Debug Support Datasheet (prl.).doc (nonexistent) +++ tags/rel_13/doc/src/Debug Support Datasheet (prl.).doc (revision 105)
tags/rel_13/doc/src/Debug Support Datasheet (prl.).doc Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: tags/rel_13/doc/src/DbgSupp_PB.doc =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: tags/rel_13/doc/src/DbgSupp_PB.doc =================================================================== --- tags/rel_13/doc/src/DbgSupp_PB.doc (nonexistent) +++ tags/rel_13/doc/src/DbgSupp_PB.doc (revision 105)
tags/rel_13/doc/src/DbgSupp_PB.doc Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: tags/rel_13/doc/Debug Support Datasheet (prl.).pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: tags/rel_13/doc/Debug Support Datasheet (prl.).pdf =================================================================== --- tags/rel_13/doc/Debug Support Datasheet (prl.).pdf (nonexistent) +++ tags/rel_13/doc/Debug Support Datasheet (prl.).pdf (revision 105)
tags/rel_13/doc/Debug Support Datasheet (prl.).pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: tags/rel_13/doc/DbgSupp_PB.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: tags/rel_13/doc/DbgSupp_PB.pdf =================================================================== --- tags/rel_13/doc/DbgSupp_PB.pdf (nonexistent) +++ tags/rel_13/doc/DbgSupp_PB.pdf (revision 105)
tags/rel_13/doc/DbgSupp_PB.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property

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