URL
https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk
Subversion Repositories versatile_mem_ctrl
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- This comparison shows the changes necessary to convert path
/
- from Rev 104 to Rev 105
- ↔ Reverse comparison
Rev 104 → Rev 105
/versatile_mem_ctrl/trunk/rtl/verilog/sdr_sdram_16_ctrl.v
1,20 → 1,3
module delay_emptyflag ( d, q, emptyflag, clk, rst); |
parameter depth = 10; |
input d; |
output q, emptyflag; |
input clk, rst; |
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reg [1:depth] dffs; |
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always @ (posedge clk or posedge rst) |
if (rst) |
dffs <= {depth{1'b0}}; |
else |
dffs <= {d,dffs[1:depth-1]}; |
assign q = dffs[depth]; |
assign emptyflag = !(|dffs); |
endmodule |
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module sdr_sdram_16_ctrl ( |
// wisbone i/f |
dat_i, adr_i, sel_i, cti_i, bte_i, we_i, cyc_i, stb_i, dat_o, ack_o, |
314,7 → 297,7
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assign ack_wr = (state==`FSM_RW & count0 & we_i); |
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delay_emptyflag # ( .depth(cl+2)) delay0 ( .d(state==`FSM_RW & count0 & !we_i), .q(ack_rd), .emptyflag(rd_ack_emptyflag), .clk(clk), .rst(rst)); |
vl_delay_emptyflag # ( .depth(cl+2)) delay0 ( .d(state==`FSM_RW & count0 & !we_i), .q(ack_rd), .emptyflag(rd_ack_emptyflag), .clk(clk), .rst(rst)); |
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assign ack_o = ack_rd | ack_wr; |
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