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Rev 105 → Rev 106

/trunk/bench/verilog/wb_master_behavioral.v
38,6 → 38,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2003/06/12 02:30:39 mihad
// Update!
//
// Revision 1.1 2002/02/01 13:39:43 mihad
// Initial testbench import. Still under development
//
117,6 → 120,8
integer cyc_count ;
integer rty_count ;
reg retry ;
reg [2:0] use_cti ;
reg [1:0] use_bte ;
begin:main
 
return`TB_ERROR_BIT = 1'b0 ;
136,6 → 141,16
 
retry = 1 ;
 
use_cti = {$random} % 8 ;
if (use_cti === 3'b010)
use_cti = 3'b111 ;
else if (use_cti === 3'b001)
use_cti = 3'b000 ;
 
use_bte = {$random} % 4 ;
 
write_data`WRITE_TAG_STIM = {use_cti, use_bte} ;
 
while (retry === 1)
begin
// synchronize operation to clock
209,6 → 224,8
integer cyc_count ;
integer rty_count ;
reg retry ;
reg [2:0] use_cti ;
reg [1:0] use_bte ;
begin:main
 
return`TB_ERROR_BIT = 1'b0 ;
228,6 → 245,16
 
retry = 1 ;
 
use_cti = {$random} % 8 ;
if (use_cti === 3'b010)
use_cti = 3'b111 ;
else if (use_cti === 3'b001)
use_cti = 3'b000 ;
 
use_bte = {$random} % 4 ;
 
read_data`READ_TAG_STIM = {use_cti, use_bte} ;
 
while (retry === 1)
begin
// synchronize operation to clock
303,6 → 330,8
integer cyc_count ;
integer rty_count ;
reg retry ;
reg [2:0] use_cti ;
reg [1:0] use_bte ;
begin:main
 
return`TB_ERROR_BIT = 1'b0 ;
322,6 → 351,16
 
retry = 1 ;
 
use_cti = {$random} % 8 ;
if (use_cti === 3'b010)
use_cti = 3'b111 ;
else if (use_cti === 3'b001)
use_cti = 3'b000 ;
 
use_bte = {$random} % 4 ;
 
read_data`READ_TAG_STIM = {use_cti, use_bte} ;
 
while (retry === 1)
begin
// synchronize operation to clock
400,6 → 439,8
integer cyc_count ;
integer rty_count ;
reg retry ;
reg [2:0] use_cti ;
reg [1:0] use_bte ;
begin:main
 
return`TB_ERROR_BIT = 1'b0 ;
419,6 → 460,16
 
retry = 1 ;
 
use_cti = {$random} % 8 ;
if (use_cti === 3'b010)
use_cti = 3'b111 ;
else if (use_cti === 3'b001)
use_cti = 3'b000 ;
 
use_bte = {$random} % 4 ;
 
write_data`WRITE_TAG_STIM = {use_cti, use_bte} ;
 
while (retry === 1)
begin
// synchronize operation to clock
496,6 → 547,8
integer cyc_count ;
integer rty_count ;
reg end_blk ;
reg [2:0] use_cti ;
reg [1:0] use_bte ;
begin:main
 
return`CYC_ACTUAL_TRANSFER = 0 ;
521,6 → 574,43
@(posedge CLK_I) ;
 
cab = write_flags`WB_TRANSFER_CAB ;
 
current_write = blk_write_data[0] ;
 
if (cab)
begin:select_burst_type_blk
reg [31:0] burst_start_adr ;
 
use_cti = 3'b010 ;
 
burst_start_adr = current_write`WRITE_ADDRESS ;
if (burst_start_adr[5:2] === 4'b0000)
use_bte = {$random} % 4 ;
else if (burst_start_adr[4:2] === 3'b000)
use_bte = {$random} % 3 ;
else if (burst_start_adr[3:2] === 2'b00)
use_bte = {$random} % 2 ;
else
use_bte = 2'b00 ;
end
else
begin
if ( (current_write`WRITE_TAG_STIM === 0) | (current_write`WRITE_TAG_STIM === {`WB_TAG_WIDTH{1'bx}}) )
begin
use_cti = {$random} % 8 ;
if (use_cti === 3'b010)
use_cti = 3'b111 ;
else if (use_cti === 3'b001)
use_cti = 3'b000 ;
use_bte = {$random} % 4 ;
end
else
begin
{use_cti, use_bte} = current_write`WRITE_TAG_STIM ;
end
end
 
wbm_low_level.start_cycle(cab, 1'b1, write_flags`WB_FAST_B2B, ok) ;
if ( ok !== 1 )
begin
540,8 → 630,18
end_blk = 0 ;
while (end_blk === 0)
begin
// collect data for current data beat
current_write = blk_write_data[return`CYC_ACTUAL_TRANSFER] ;
 
if (cab)
begin
if ((return`CYC_ACTUAL_TRANSFER + 1'b1) >= write_flags`WB_TRANSFER_SIZE)
use_cti = 3'b111 ;
end
 
current_write`WRITE_TAG_STIM = {use_cti, use_bte} ;
 
wbm_low_level.wbm_write(current_write, return) ;
 
// check result of write operation
580,6 → 680,11
end
else
begin
if (cab)
begin
use_bte = 2'b00 ;
end
 
rty_count = rty_count + 1 ;
end
end
639,6 → 744,8
integer rty_count ;
reg end_blk ;
integer transfered ;
reg [2:0] use_cti ;
reg [1:0] use_bte ;
begin:main
 
return`CYC_ACTUAL_TRANSFER = 0 ;
664,6 → 771,24
@(posedge CLK_I) ;
cab = read_flags`WB_TRANSFER_CAB ;
 
if (cab)
begin:select_burst_type_blk
reg [31:0] burst_start_adr ;
 
use_cti = 3'b010 ;
 
current_read = blk_read_data_in[0] ;
burst_start_adr = current_read`READ_ADDRESS ;
if (burst_start_adr[5:2] === 4'b0000)
use_bte = {$random} % 4 ;
else if (burst_start_adr[4:2] === 3'b000)
use_bte = {$random} % 3 ;
else if (burst_start_adr[3:2] === 2'b00)
use_bte = {$random} % 2 ;
else
use_bte = 2'b00 ;
end
 
wbm_low_level.start_cycle(cab, 1'b0, read_flags`WB_FAST_B2B, ok) ;
 
if ( ok !== 1 )
687,6 → 812,14
// collect data for current data beat
current_read = blk_read_data_in[return`CYC_ACTUAL_TRANSFER] ;
 
if (cab)
begin
if ((return`CYC_ACTUAL_TRANSFER + 1'b1) >= read_flags`WB_TRANSFER_SIZE)
use_cti = 3'b111 ;
end
 
current_read`READ_TAG_STIM = {use_cti, use_bte} ;
 
wbm_low_level.wbm_read(current_read, return) ;
 
if ( transfered !== return`CYC_ACTUAL_TRANSFER )
731,6 → 864,11
end
else
begin
if (cab)
begin
use_bte = 2'b00 ;
end
 
rty_count = rty_count + 1 ;
end
end
/trunk/bench/verilog/system.v
39,6 → 39,10
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.17 2003/07/29 08:19:47 mihad
// Found and simulated the problem in the synchronization logic.
// Repaired the synchronization logic in the FIFOs.
//
// Revision 1.16 2003/06/12 02:30:39 mihad
// Update!
//
156,6 → 160,8
wire STB_I ;
wire WE_I ;
wire CAB_I ;
wire [2:0] CTI_I ;
wire [1:0] BTE_I ;
wire ACK_O ;
wire RTY_O ;
wire ERR_O ;
197,6 → 203,9
 
`define PCI_BRIDGE_INSTANCE bridge32_top
 
reg tc_gnt_allow ;
initial tc_gnt_allow = 1'b0 ;
 
TOP `PCI_BRIDGE_INSTANCE
(
.CLK ( pci_clock),
205,7 → 214,7
.RST ( RST ),
.INTA ( INTA ),
.REQ ( MAS0_REQ ),
.GNT ( MAS0_GNT ),
.GNT ( MAS0_GNT | tc_gnt_allow),
.FRAME ( FRAME ),
.IRDY ( IRDY ),
.IDSEL ( TAR0_IDSEL),
231,6 → 240,8
.STB_I ( STB_I ),
.WE_I ( WE_I ),
.CAB_I ( CAB_I),
.CTI_I ( CTI_I),
.BTE_I ( BTE_I),
.ACK_O ( ACK_O ),
.RTY_O ( RTY_O ),
.ERR_O ( ERR_O ),
263,8 → 274,8
(
.CLK_I(wb_clock),
.RST_I(reset_wb),
.TAG_I(4'b0000),
.TAG_O(),
.TAG_I(`WB_TAG_WIDTH'd0),
.TAG_O({CTI_I, BTE_I}),
.ACK_I(ACK_O),
.ADR_O(ADR_I),
.CYC_O(CYC_I),
311,7 → 322,7
.STB_O(STB_I),
.WE_O (WE_I),
.TAG_I({`WB_TAG_WIDTH{1'b0}}),
.TAG_O(),
.TAG_O({CTI_I, BTE_I}),
.CAB_O(CAB_I),
.log_file_desc ( wbu_mon_log_file_desc )
) ;
330,7 → 341,7
.STB_O(STB_O),
.WE_O (WE_O),
.TAG_I({`WB_TAG_WIDTH{1'b0}}),
.TAG_O(),
.TAG_O({`WB_TAG_WIDTH{1'b0}}),
.CAB_O(CAB_O),
.log_file_desc( pciu_mon_log_file_desc )
) ;
429,7 → 440,7
.pci_ext_perr_l (PERR),
.pci_ext_serr_l (SERR),
.pci_real_req_l (MAS0_REQ),
.pci_real_gnt_l (MAS0_GNT),
.pci_real_gnt_l (MAS0_GNT | tc_gnt_allow),
.pci_ext_req_l ({1'b1, MAS3_REQ, MAS2_REQ, MAS1_REQ}),
.pci_ext_gnt_l (~arb_grant_out[4:1]),
.test_error_event (error_event_int),
848,7 → 859,7
run_tests ;
end
 
task fill_memory ;
task fill_memory ; //wb_b3_ok
integer temp_index ;
begin
// fill write memories with random data
874,7 → 885,7
reg [2:0] pci_subseq_waits ;
reg [2:0] tb_target_decode_speed ;
 
task run_tests ;
task run_tests ; //wb_b3_ok
begin
wb_init_waits = 0;
pci_init_waits = 0;
887,8 → 898,8
 
// if BIST is implemented, give it a go
`ifdef PCI_BIST
// run_bist_test ;
scanb_rst <= #1 1'b1 ;
run_bist_test ;
scanb_rst <= #1 1'b1 ;
`endif
test_initial_conf_values ;
 
1084,7 → 1095,7
configure_target(2) ;
 
`ifdef GUEST
configure_bridge_target ;
configure_bridge_target ; // b3ok
`endif
 
target_special_corner_case_test ;
1102,7 → 1113,7
end
endtask // run_tests
 
task do_reset;
task do_reset; //wb_b3_ok
begin
next_test_name[79:0] <= "Reset.....";
 
1134,7 → 1145,7
===================
############################################################################*/
 
task configure_target ;
task configure_target ; //wb_b3_ok
input [1:0] beh_dev_num ;
reg [31:0] base_address1 ;
reg [31:0] base_address2 ;
1174,7 → 1185,7
end
endtask //configure_target
 
task test_wb_image ;
task test_wb_image ; //wb_b3_ok
input [2:0] image_num ;
reg [11:0] ctrl_offset ;
reg [11:0] ba_offset ;
1309,7 → 1320,7
write_data`WRITE_SEL = 4'hF ;
 
// handle retries from now on
write_flags`WB_TRANSFER_AUTO_RTY = 1 ;
write_flags`WB_TRANSFER_AUTO_RTY = 0 ;
 
wishbone_master.wb_single_write( write_data, write_flags, write_status ) ;
test_name = "NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCI" ;
1323,7 → 1334,7
// read written data back
read_data`READ_ADDRESS = target_address ;
read_data`READ_SEL = 4'hF ;
read_data`READ_TAG_STIM = 0 ;
write_flags`WB_TRANSFER_AUTO_RTY = 1'b1 ;
wishbone_master.wb_single_read( read_data, write_flags, read_status ) ;
if (read_status`CYC_ACTUAL_TRANSFER !== 1)
begin
1403,9 → 1414,9
 
fork
begin
write_data`WRITE_ADDRESS = target_address + 4 ;
write_data`WRITE_DATA = wmem_data[1] ;
write_data`WRITE_SEL = 4'hF ;
write_data`WRITE_ADDRESS = target_address + 4 ;
write_data`WRITE_DATA = wmem_data[1] ;
write_data`WRITE_SEL = 4'hF ;
 
write_flags`WB_TRANSFER_AUTO_RTY = 0 ;
 
1426,7 → 1437,6
// read written data back
read_data`READ_ADDRESS = target_address + 4 ;
read_data`READ_SEL = 4'hF ;
read_data`READ_TAG_STIM = 0 ;
 
write_flags`WB_TRANSFER_AUTO_RTY = 1 ;
 
1466,6 → 1476,7
 
// now do one burst write - length of 6 - minimum depth of fifo is 8, one loc. is always free and one is taken up by address entry
// prepare write data
 
for ( i = 0 ; i < 6 ; i = i + 1 )
begin
write_data`WRITE_DATA = wmem_data[2 + i] ;
1608,7 → 1619,6
 
read_data`READ_ADDRESS = target_address ;
read_data`READ_SEL = 4'hF ;
read_data`READ_TAG_STIM = 0 ;
 
test_name = "SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED" ;
fork
1678,7 → 1688,6
 
read_data`READ_ADDRESS = target_address + 4 ;
read_data`READ_SEL = 4'hF ;
read_data`READ_TAG_STIM = 0 ;
 
test_name = "SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED" ;
fork
1748,7 → 1757,6
 
read_data`READ_ADDRESS = target_address + 8 ;
read_data`READ_SEL = 4'hF ;
read_data`READ_TAG_STIM = 0 ;
 
test_name = "SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED" ;
fork
1790,7 → 1798,7
write_data`WRITE_DATA = wmem_data[11] ;
write_data`WRITE_SEL = 4'hF ;
 
// handle retries from now on
// don't handle retries from now on
write_flags`WB_TRANSFER_AUTO_RTY = 0 ;
 
test_name = "I/O WRITE TRANSACTION FROM WB TO PCI TEST" ;
1816,7 → 1824,6
 
read_data`READ_ADDRESS = target_address ;
read_data`READ_SEL = 4'hF ;
read_data`READ_TAG_STIM = 0 ;
 
write_flags`WB_TRANSFER_AUTO_RTY = 1 ;
 
1842,8 → 1849,8
join
 
// test byte addressing
read_data`READ_ADDRESS = target_address + 2 ;
read_data`READ_SEL = 4'b1100 ;
read_data`READ_ADDRESS = target_address + 2 ;
read_data`READ_SEL = 4'b1100 ;
 
fork
begin
1887,9 → 1894,9
disable main ;
end
 
write_data`WRITE_ADDRESS = {target_address[31], 31'h7FFF_FFFF} ;
write_data`WRITE_DATA = wmem_data[11] ;
write_data`WRITE_SEL = 4'b1000 ;
write_data`WRITE_ADDRESS = {target_address[31], 31'h7FFF_FFFF} ;
write_data`WRITE_DATA = wmem_data[11] ;
write_data`WRITE_SEL = 4'b1000 ;
 
// handle retries from now on
write_flags`WB_TRANSFER_AUTO_RTY = 0 ;
1914,8 → 1921,8
end
join
 
read_data`READ_ADDRESS = write_data`WRITE_ADDRESS ;
read_data`READ_SEL = write_data`WRITE_SEL ;
read_data`READ_ADDRESS = write_data`WRITE_ADDRESS ;
read_data`READ_SEL = write_data`WRITE_SEL ;
write_flags`WB_TRANSFER_AUTO_RTY = 1 ;
 
fork
1960,7 → 1967,7
end //main
endtask //test_wb_image
 
task wb_slave_errors ;
task wb_slave_errors ; //wb_b3_ok
reg [11:0] ctrl_offset ;
reg [11:0] ba_offset ;
reg [11:0] am_offset ;
2104,7 → 2111,6
 
read_data`READ_ADDRESS = target_address + 2 ;
read_data`READ_SEL = 4'hF ;
read_data`READ_TAG_STIM = 0 ;
 
wishbone_master.wb_single_read( read_data, write_flags, read_status ) ;
if ( (read_status`CYC_ACTUAL_TRANSFER !== 0) || (read_status`CYC_ERR !== 1) )
2144,6 → 2150,7
end
 
// prepare read data
 
for ( i = 0 ; i < 6 ; i = i + 1 )
begin
read_data`READ_ADDRESS = target_address + 4*i + 3 ;
2184,9 → 2191,9
 
skip = 0 ;
 
write_data`WRITE_ADDRESS = target_address ;
write_data`WRITE_DATA = wmem_data[0] ;
write_data`WRITE_SEL = 4'b1010 ;
write_data`WRITE_ADDRESS = target_address ;
write_data`WRITE_DATA = wmem_data[0] ;
write_data`WRITE_SEL = 4'b1010 ;
 
// don't handle retries
write_flags`WB_TRANSFER_AUTO_RTY = 0 ;
2204,8 → 2211,8
disable main ;
end
 
write_data`WRITE_ADDRESS = target_address + 1 ;
write_data`WRITE_SEL = 4'b0011 ;
write_data`WRITE_ADDRESS = target_address + 1 ;
write_data`WRITE_SEL = 4'b0011 ;
 
wishbone_master.wb_single_write( write_data, write_flags, write_status ) ;
if ( (write_status`CYC_ACTUAL_TRANSFER !== 0) || (write_status`CYC_ERR !== 1) )
2218,8 → 2225,7
disable main ;
end
 
write_data`WRITE_SEL = 4'b1100 ;
 
write_data`WRITE_SEL = 4'b1100 ;
wishbone_master.wb_single_write( write_data, write_flags, write_status ) ;
if ( (write_status`CYC_ACTUAL_TRANSFER !== 0) || (write_status`CYC_ERR !== 1) )
begin
2231,8 → 2237,8
disable main ;
end
 
write_data`WRITE_ADDRESS = target_address + 2 ;
write_data`WRITE_SEL = 4'b0101 ;
write_data`WRITE_ADDRESS = target_address + 2 ;
write_data`WRITE_SEL = 4'b0101 ;
 
wishbone_master.wb_single_write( write_data, write_flags, write_status ) ;
if ( (write_status`CYC_ACTUAL_TRANSFER !== 0) || (write_status`CYC_ERR !== 1) )
2245,7 → 2251,7
disable main ;
end
 
write_data`WRITE_SEL = 4'b1000 ;
write_data`WRITE_SEL = 4'b1000 ;
 
wishbone_master.wb_single_write( write_data, write_flags, write_status ) ;
if ( (write_status`CYC_ACTUAL_TRANSFER !== 0) || (write_status`CYC_ERR !== 1) )
2291,7 → 2297,6
 
read_data`READ_ADDRESS = target_address + 3 ;
read_data`READ_SEL = 4'hF ;
read_data`READ_TAG_STIM = 0 ;
 
wishbone_master.wb_single_read( read_data, write_flags, read_status ) ;
if ( (read_status`CYC_ACTUAL_TRANSFER !== 0) || (read_status`CYC_ERR !== 1) )
2307,6 → 2312,7
test_ok ;
 
test_name = "CAB I/O WRITE TO WB SLAVE" ;
 
// prepare write data
for ( i = 0 ; i < 6 ; i = i + 1 )
begin
2334,6 → 2340,7
test_ok ;
 
test_name = "CAB I/O READ TO WB SLAVE" ;
 
// prepare read data
for ( i = 0 ; i < 6 ; i = i + 1 )
begin
2359,136 → 2366,165
 
$display("************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************") ;
 
target_address = {`WB_CONFIGURATION_BASE, 12'h0} ;
write_data`WRITE_ADDRESS = target_address + 1 ;
write_data`WRITE_DATA = wmem_data[0] ;
write_data`WRITE_SEL = 4'hF ;
begin:test_erroneous_config_access_blk
reg do_write_test ;
reg do_read_test ;
 
// don't handle retries
write_flags`WB_TRANSFER_AUTO_RTY = 0 ;
target_address = {`WB_CONFIGURATION_BASE, 12'h0} ;
 
do_write_test = 1'b0 ;
do_read_test = 1'b0 ;
 
`ifdef HOST
`define DO_W_CONF_TEST
`define DO_R_CONF_TEST
`else
`ifdef WB_CNF_IMAGE
`define DO_R_CONF_TEST
`endif
`endif
 
`ifdef DO_W_CONF_TEST
test_name = "ERRONEOUS WB CONFIGURATION WRITE ACCESS" ;
wishbone_master.wb_single_write( write_data, write_flags, write_status ) ;
if ( (write_status`CYC_ACTUAL_TRANSFER !== 0) || (write_status`CYC_ERR !== 1) )
begin
$display("WISHBONE slave error termination testing failed! WB Slave didn't signal error on access to non-alligned configuration address! Time %t ", $time) ;
$display("WISHBONE slave response: ACK = %b, RTY = %b, ERR = %b ", write_status`CYC_ACK, write_status`CYC_RTY, write_status`CYC_ERR) ;
test_fail("WB Slave state machine didn't reject erroneous Configuration write as expected") ;
disable no_transaction ;
disable main ;
end
do_write_test = 1'b1 ;
do_read_test = 1'b1 ;
 
write_data`WRITE_ADDRESS = target_address + 2 ;
`else
 
wishbone_master.wb_single_write( write_data, write_flags, write_status ) ;
if ( (write_status`CYC_ACTUAL_TRANSFER !== 0) || (write_status`CYC_ERR !== 1) )
begin
$display("WISHBONE slave error termination testing failed! WB Slave didn't signal error on access to non-alligned configuration address! Time %t ", $time) ;
$display("WISHBONE slave response: ACK = %b, RTY = %b, ERR = %b ", write_status`CYC_ACK, write_status`CYC_RTY, write_status`CYC_ERR) ;
test_fail("WB Slave state machine didn't reject erroneous Configuration write as expected") ;
disable no_transaction ;
disable main ;
end
`ifdef WB_CNF_IMAGE
 
write_data`WRITE_ADDRESS = target_address + 3 ;
do_read_test = 1'b1 ;
 
wishbone_master.wb_single_write( write_data, write_flags, write_status ) ;
if ( (write_status`CYC_ACTUAL_TRANSFER !== 0) || (write_status`CYC_ERR !== 1) )
begin
$display("WISHBONE slave error termination testing failed! WB Slave didn't signal error on access to non-alligned configuration address! Time %t ", $time) ;
$display("WISHBONE slave response: ACK = %b, RTY = %b, ERR = %b ", write_status`CYC_ACK, write_status`CYC_RTY, write_status`CYC_ERR) ;
test_fail("WB Slave state machine didn't reject erroneous Configuration write as expected") ;
disable no_transaction ;
disable main ;
end
`endif
 
test_ok ;
`endif
`ifdef PCI_WBS_ALLOW_NON_ALLIGNED_CONFIG_ACCESS
`else
 
`ifdef DO_R_CONF_TEST
test_name = "ERRONEOUS WB CONFIGURATION READ ACCESS" ;
read_data`READ_ADDRESS = target_address + 3 ;
read_data`READ_SEL = 4'hF ;
read_data`READ_TAG_STIM = 0 ;
if (do_write_test)
begin
write_data`WRITE_ADDRESS = target_address + 1 ;
write_data`WRITE_DATA = wmem_data[0] ;
write_data`WRITE_SEL = 4'hF ;
// don't handle retries
write_flags`WB_TRANSFER_AUTO_RTY = 0 ;
 
wishbone_master.wb_single_read( read_data, write_flags, read_status ) ;
if ( (read_status`CYC_ACTUAL_TRANSFER !== 0) || (read_status`CYC_ERR !== 1) )
begin
$display("WISHBONE slave error termination testing failed! WB Slave didn't signal error on access to non-alligned configuration address! Time %t ", $time) ;
$display("WISHBONE slave response: ACK = %b, RTY = %b, ERR = %b ", write_status`CYC_ACK, write_status`CYC_RTY, write_status`CYC_ERR) ;
test_fail("WB Slave state machine didn't reject erroneous Configuration read as expected") ;
disable no_transaction ;
disable main ;
end
test_name = "ERRONEOUS WB CONFIGURATION WRITE ACCESS" ;
wishbone_master.wb_single_write( write_data, write_flags, write_status ) ;
if ( (write_status`CYC_ACTUAL_TRANSFER !== 0) || (write_status`CYC_ERR !== 1) )
begin
$display("WISHBONE slave error termination testing failed! WB Slave didn't signal error on access to non-alligned configuration address! Time %t ", $time) ;
$display("WISHBONE slave response: ACK = %b, RTY = %b, ERR = %b ", write_status`CYC_ACK, write_status`CYC_RTY, write_status`CYC_ERR) ;
test_fail("WB Slave state machine didn't reject erroneous Configuration write as expected") ;
disable no_transaction ;
disable main ;
end
// try write to configuration cycle address register with non alligned address
write_data`WRITE_ADDRESS = target_address + {4'h1, `CNF_ADDR_ADDR, 2'b10} ;
 
test_ok ;
`endif
wishbone_master.wb_single_write( write_data, write_flags, write_status ) ;
if ( (write_status`CYC_ACTUAL_TRANSFER !== 0) || (write_status`CYC_ERR !== 1) )
begin
$display("WISHBONE slave error termination testing failed! WB Slave didn't signal error on access to non-alligned configuration address! Time %t ", $time) ;
$display("WISHBONE slave response: ACK = %b, RTY = %b, ERR = %b ", write_status`CYC_ACK, write_status`CYC_RTY, write_status`CYC_ERR) ;
test_fail("WB Slave state machine didn't reject erroneous Configuration write as expected") ;
disable no_transaction ;
disable main ;
end
write_data`WRITE_ADDRESS = target_address + {4'h1, `CNF_DATA_ADDR, 2'b11} ;
 
`ifdef DO_W_CONF_TEST
// prepare write data
test_name = "WB CAB CONFIGURATION WRITE ACCESS" ;
for ( i = 0 ; i < 6 ; i = i + 1 )
begin
write_data`WRITE_DATA = wmem_data[i] ;
write_data`WRITE_ADDRESS = target_address + 4*i ;
write_data`WRITE_SEL = 4'hF ;
wishbone_master.blk_write_data[i] = write_data ;
end
// try write to configuration cycle data register with non alligned address
wishbone_master.wb_single_write( write_data, write_flags, write_status ) ;
if ( (write_status`CYC_ACTUAL_TRANSFER !== 0) || (write_status`CYC_ERR !== 1) )
begin
$display("WISHBONE slave error termination testing failed! WB Slave didn't signal error on access to non-alligned configuration address! Time %t ", $time) ;
$display("WISHBONE slave response: ACK = %b, RTY = %b, ERR = %b ", write_status`CYC_ACK, write_status`CYC_RTY, write_status`CYC_ERR) ;
test_fail("WB Slave state machine didn't reject erroneous Configuration write as expected") ;
disable no_transaction ;
disable main ;
end
test_ok ;
end
 
write_flags`WB_TRANSFER_AUTO_RTY = 0 ;
write_flags`WB_TRANSFER_CAB = 1 ;
write_flags`WB_TRANSFER_SIZE = 6 ;
if (do_read_test)
begin
test_name = "ERRONEOUS WB CONFIGURATION READ ACCESS" ;
// try read from configuration cycle data register with non alligned address
read_data`READ_ADDRESS = target_address + {4'h1, `CNF_DATA_ADDR, 2'b01} ;
read_data`READ_SEL = 4'hF ;
wishbone_master.wb_single_read( read_data, write_flags, read_status ) ;
if ( (read_status`CYC_ACTUAL_TRANSFER !== 0) || (read_status`CYC_ERR !== 1) )
begin
$display("WISHBONE slave error termination testing failed! WB Slave didn't signal error on access to non-alligned configuration address! Time %t ", $time) ;
$display("WISHBONE slave response: ACK = %b, RTY = %b, ERR = %b ", write_status`CYC_ACK, write_status`CYC_RTY, write_status`CYC_ERR) ;
test_fail("WB Slave state machine didn't reject erroneous Configuration read as expected") ;
disable no_transaction ;
disable main ;
end
test_ok ;
end
 
wishbone_master.wb_block_write(write_flags, write_status) ;
 
if ( (write_status`CYC_ACTUAL_TRANSFER !== 0) || (write_status`CYC_ERR !== 1) )
begin
$display("WISHBONE slave error termination testing failed! WB Slave didn't signal error on CAB access to configuration address! Time %t ", $time) ;
$display("WISHBONE slave response: ACK = %b, RTY = %b, ERR = %b ", write_status`CYC_ACK, write_status`CYC_RTY, write_status`CYC_ERR) ;
test_fail("WB Slave state machine didn't reject CAB Configuration write as expected") ;
disable no_transaction ;
disable main ;
end
test_ok ;
`endif
 
`ifdef DO_R_CONF_TEST
// prepare read data
test_name = "WB CAB CONFIGURATION READ ACCESS" ;
for ( i = 0 ; i < 6 ; i = i + 1 )
begin
read_data`READ_ADDRESS = target_address + 4*i ;
read_data`READ_SEL = 4'hF ;
wishbone_master.blk_read_data_in[i] = read_data ;
end
if (do_write_test)
begin
// prepare write data
test_name = "WB CAB CONFIGURATION WRITE ACCESS" ;
 
wishbone_master.wb_block_read(write_flags, read_status) ;
for ( i = 0 ; i < 6 ; i = i + 1 )
begin
write_data`WRITE_DATA = wmem_data[i] ;
write_data`WRITE_ADDRESS = target_address + 4*i + {4'h1, `CNF_DATA_ADDR, 2'b00};
write_data`WRITE_SEL = 4'hF ;
wishbone_master.blk_write_data[i] = write_data ;
end
write_flags`WB_TRANSFER_AUTO_RTY = 0 ;
write_flags`WB_TRANSFER_CAB = 1 ;
write_flags`WB_TRANSFER_SIZE = 6 ;
wishbone_master.wb_block_write(write_flags, write_status) ;
if ( (write_status`CYC_ACTUAL_TRANSFER !== 0) || (write_status`CYC_ERR !== 1) )
begin
$display("WISHBONE slave error termination testing failed! WB Slave didn't signal error on CAB access to configuration address! Time %t ", $time) ;
$display("WISHBONE slave response: ACK = %b, RTY = %b, ERR = %b ", write_status`CYC_ACK, write_status`CYC_RTY, write_status`CYC_ERR) ;
test_fail("WB Slave state machine didn't reject CAB Configuration write as expected") ;
disable no_transaction ;
disable main ;
end
test_ok ;
end
if (do_read_test)
begin
// prepare read data
test_name = "WB CAB CONFIGURATION READ ACCESS" ;
 
if ( (read_status`CYC_ACTUAL_TRANSFER !== 0) || (read_status`CYC_ERR !== 1) )
begin
$display("WISHBONE slave error termination testing failed! WB Slave didn't signal error on CAB access to configuration address! Time %t ", $time) ;
$display("WISHBONE slave response: ACK = %b, RTY = %b, ERR = %b ", write_status`CYC_ACK, write_status`CYC_RTY, write_status`CYC_ERR) ;
test_fail("WB Slave state machine didn't reject CAB Configuration read as expected") ;
disable no_transaction ;
disable main ;
end
test_ok ;
`endif
for ( i = 0 ; i < 6 ; i = i + 1 )
begin
read_data`READ_ADDRESS = target_address + 4*i + {4'h1, `CNF_DATA_ADDR, 2'b00};
read_data`READ_SEL = 4'hF ;
wishbone_master.blk_read_data_in[i] = read_data ;
end
wishbone_master.wb_block_read(write_flags, read_status) ;
if ( (read_status`CYC_ACTUAL_TRANSFER !== 0) || (read_status`CYC_ERR !== 1) )
begin
$display("WISHBONE slave error termination testing failed! WB Slave didn't signal error on CAB access to configuration address! Time %t ", $time) ;
$display("WISHBONE slave response: ACK = %b, RTY = %b, ERR = %b ", write_status`CYC_ACK, write_status`CYC_RTY, write_status`CYC_ERR) ;
test_fail("WB Slave state machine didn't reject CAB Configuration read as expected") ;
disable no_transaction ;
disable main ;
end
test_ok ;
end
`ifdef GUEST
skip = 1 ;
`endif
end // test_erroneous_config_access_blk
 
`ifdef GUEST
skip = 1 ;
`endif
 
// disable image
test_name = "DISABLE IMAGE" ;
config_write( am_offset, 32'h7FFF_FFFF, 4'hF, ok ) ;
2631,9 → 2667,9
// perform two writes - one to error address and one to OK address
// prepare write buffer
 
write_data`WRITE_ADDRESS = target_address ;
write_data`WRITE_DATA = wmem_data[100] ;
write_data`WRITE_SEL = 4'hF ;
write_data`WRITE_ADDRESS = target_address ;
write_data`WRITE_DATA = wmem_data[100] ;
write_data`WRITE_SEL = 4'hF ;
 
wishbone_master.blk_write_data[0] = write_data ;
 
2686,7 → 2722,6
write_flags`WB_TRANSFER_AUTO_RTY = 1 ;
read_data`READ_ADDRESS = target_address ;
read_data`READ_SEL = 4'hF ;
read_data`READ_TAG_STIM = 0 ;
 
wishbone_master.wb_single_read( read_data, write_flags, read_status ) ;
 
2779,7 → 2814,7
write_data`WRITE_SEL = 4'hF ;
wishbone_master.blk_write_data[i] = write_data ;
end
 
test_name = "CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITE" ;
fork
begin
2989,7 → 3024,7
write_data`WRITE_SEL = 4'hF ;
wishbone_master.blk_write_data[i] = write_data ;
end
 
wishbone_master.wb_block_write(write_flags, write_status) ;
 
if ( write_status`CYC_ACTUAL_TRANSFER !== 3 )
3043,12 → 3078,12
32'h0000_0000 // data
) ;
// set read data
read_data`READ_ADDRESS = target_address ;
read_data`READ_SEL = 4'hF ;
read_data`READ_ADDRESS = target_address ;
read_data`READ_SEL = 4'hF ;
 
// enable automatic retry handling
write_flags`WB_TRANSFER_AUTO_RTY = 1 ;
write_flags`WB_TRANSFER_CAB = 0 ;
write_flags`WB_TRANSFER_CAB = 0 ;
 
test_name = "MASTER ABORT ERROR HANDLING FOR WB TO PCI READS" ;
fork
3101,8 → 3136,8
) ;
 
test_name = "CHECK NORMAL READ AFTER MASTER ABORT TERMINATED READ" ;
read_data`READ_ADDRESS = target_address ;
read_data`READ_SEL = 4'hF ;
read_data`READ_ADDRESS = target_address ;
read_data`READ_SEL = 4'hF ;
 
wishbone_master.wb_single_read(read_data, write_flags, read_status) ;
if ( read_status`CYC_ACTUAL_TRANSFER !== 1 )
3159,6 → 3194,7
32'h0000_0000 // data
) ;
 
 
for ( i = 0 ; i < 3 ; i = i + 1 )
begin
read_data`READ_ADDRESS = target_address + 4*i ;
3167,8 → 3203,8
end
 
write_flags`WB_TRANSFER_AUTO_RTY = 1 ;
write_flags`WB_TRANSFER_SIZE = 3 ;
write_flags`WB_TRANSFER_CAB = 1 ;
write_flags`WB_TRANSFER_SIZE = 3 ;
write_flags`WB_TRANSFER_CAB = 1 ;
 
fork
begin
3461,7 → 3497,7
$display("PCI bus error handling testing failed! Time %t ", $time) ;
$display("Value in W_ERR_CS register was wrong!") ;
$display("Expected BE = %b, BC = %b ; actuals: BE = %b, BC = %b ", 4'b0101, `BC_MEM_WRITE, temp_val1[31:28], temp_val1[27:24]) ;
test_fail("BE Field didn't provided expected value") ;
test_fail("BE Field didn't provide expected value") ;
ok = 0 ;
end
 
3482,11 → 3518,13
end
 
config_read( { 4'h1, `W_ERR_DATA_ADDR, 2'b00}, 4'hF, temp_val1 ) ;
if ( temp_val1 !== wmem_data[120] )
// mask expected and actual values, since all byte enables were not active
if ( (temp_val1 & 32'hff_00_ff_00) !== (wmem_data[120] & 32'hff_00_ff_00) )
begin
$display("PCI bus error handling testing failed! Time %t ", $time) ;
$display("Value in W_ERR_DATA register was wrong!") ;
$display("Expected value = %h, actual value = %h " , wmem_data[120], temp_val1 ) ;
$display("Expected value = %h, actual value = %h " , wmem_data[120] & 32'hff_00_ff_00, temp_val1 & 32'hff_00_ff_00) ;
test_fail("Value in WB Erroneous Data register was wrong") ;
ok = 0 ;
end
3600,7 → 3638,7
begin
$display("PCI bus error handling testing failed! Time %t ", $time) ;
$display("Value in W_ERR_CS register was wrong!") ;
$display("Expected BE = %b, BC = %b ; actuals: BE = %b, BC = %b ", 4'b1010, `BC_MEM_WRITE, temp_val1[31:28], temp_val1[27:24]) ;
$display("Expected BE = %b, BC = %b ; actuals: BE = %b, BC = %b ", 4'b0101, `BC_MEM_WRITE, temp_val1[31:28], temp_val1[27:24]) ;
test_fail("BE or bus command field(s) didn't provide expected value") ;
ok = 0 ;
end
3623,11 → 3661,11
end
 
config_read( { 4'h1, `W_ERR_DATA_ADDR, 2'b00}, 4'hF, temp_val1 ) ;
if ( temp_val1 !== wmem_data[121] )
if ( (temp_val1 & 32'hFF_00_FF_00) !== (wmem_data[121] & 32'hFF_00_FF_00) )
begin
$display("PCI bus error handling testing failed! Time %t ", $time) ;
$display("Value in W_ERR_DATA register was wrong!") ;
$display("Expected value = %h, actual value = %h " , wmem_data[121], temp_val1 ) ;
$display("Expected value = %h, actual value = %h " , wmem_data[121] & 32'hFF_00_FF_00, temp_val1 & 32'hFF_00_FF_00) ;
test_fail("Value in WB Erroneous Data register was wrong") ;
ok = 0 ;
end
4067,11 → 4105,11
end
 
config_read( { 4'h1, `W_ERR_DATA_ADDR, 2'b00}, 4'hF, temp_val1 ) ;
if ( temp_val1 !== 32'hAAAA_AAAA )
if ( (temp_val1 & 32'h00_ff_00_ff) !== 32'h00AA_00AA )
begin
$display("PCI bus error handling testing failed! Time %t ", $time) ;
$display("Value in W_ERR_DATA register was wrong!") ;
$display("Expected value = %h, actual value = %h " , 32'hAAAA_AAAA, temp_val1 ) ;
$display("Expected value = %h, actual value = %h " , 32'h00AA_00AA, temp_val1 & 32'h00_ff_00_ff) ;
test_fail("WB Erroneous Data register didn't provide right value") ;
ok = 0 ;
end
4509,7 → 4547,6
read_data = 0 ;
read_data`READ_ADDRESS = target_address ;
read_data`READ_SEL = 4'hF ;
read_data`READ_TAG_STIM = 0 ;
 
write_flags`WB_TRANSFER_AUTO_RTY = 1 ;
 
7694,25 → 7731,81
disable main ;
end
end
begin
begin:cab_master_write_interrupted_by_latency_timeout2
reg [31:0] ret_adr ; reg [3:0] ret_bc ; reg ret_gnt_deasserted ;
integer ret_num_of_transfers ; integer ret_num_of_cycles ;
 
ok = 1'b1 ;
 
// wait for bridge's master to start transaction
@(posedge pci_clock) ;
while ( FRAME === 1 )
@(posedge pci_clock) ;
monitor32.get_pci_op(ret_adr, ret_bc) ;
 
// start behavioral master request
PCIU_MEM_WRITE("MEM_WRITE ", `Test_Master_1,
target_address, wmem_data[1023], `Test_All_Bytes,
1, 8'h2_0, `Test_One_Zero_Target_WS,
`Test_Devsel_Medium, `Test_Target_Normal_Completion);
if (ret_adr !== target_address)
begin
$display("%m detected an error!") ;
test_fail("invalid address was detected when PCI Master initiated a burst write operation") ;
ok = 0 ;
end
 
do_pause ( 1 ) ;
end
begin
pci_transaction_progress_monitor( target_address, `BC_MEM_WRITE, 0, 2, 1'b0, 1'b1, 0, ok ) ;
if ( ok !== 1 )
test_fail("bridge didn't finish the burst write transaction after latency timer has expired") ;
if (ret_bc !== `BC_MEM_WRITE)
begin
$display("%m detected an error!") ;
test_fail("invalid bus command was detected when PCI Master should initiate a burst write operation") ;
ok = 0 ;
end
 
// remove the grant from PCI Bridge
tc_gnt_allow = 1'b1 ;
 
fork
begin
monitor32.get_pci_op_num_of_transfers(ret_num_of_transfers, ret_gnt_deasserted) ;
end
begin
monitor32.get_pci_op_num_of_cycles(ret_num_of_cycles) ;
end
join
 
// put arbiter back into the control of the grant line
tc_gnt_allow = 1'b0 ;
// check number of cycles bridge kept the frame asserted!
if (ret_gnt_deasserted !== 1'b1)
begin
$display("%m detected an error!") ;
test_fail("GNT line wasn't deasserted during latency timer operation tests") ;
ok = 0 ;
end
else
begin
if (ret_num_of_cycles > 2)
begin
$display("%m detected an error!") ;
test_fail("PCI Master was expected to deassert FRAME after two cycles and it didn't do that!") ;
ok = 0 ;
end
end
 
if (ret_num_of_transfers !== 2)
begin
$display("%m detected an error!") ;
test_fail("PCI Master must didn't transfer 2 words in a burst, latency timer was set to a value of 2 and timeout occured") ;
ok = 0 ;
end
 
// now check the remainder of the transaction!
if (ok === 1'b1)
begin
pci_transaction_progress_monitor(target_address + 4 * ret_num_of_transfers, `BC_MEM_WRITE, 6 - ret_num_of_transfers, 0, 1'b1, 1'b0, 0, ok) ;
if (ok !== 1'b1)
begin
$display("%m detected an error!") ;
test_fail("PCI Master did invalid transaction on PCI bus") ;
ok = 0 ;
end
end
 
if (ok === 1'b1)
test_ok ;
end
join
7730,7 → 7823,7
write_flags`WB_TRANSFER_AUTO_RTY = 1 ;
write_flags`WB_TRANSFER_CAB = 1 ;
 
test_name = "BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUT" ;
test_name = "CHECK VALUES OF BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUT" ;
wishbone_master.wb_block_read( write_flags, read_status ) ;
 
if ( read_status`CYC_ACTUAL_TRANSFER !== 6 )
7774,25 → 7867,68
ok = 0 ;
end
end
begin
begin:cab_memory_read_interrupted_by_latency_timeout2
reg [31:0] ret_adr ; reg [3:0] ret_bc ; reg ret_gnt_deasserted ;
integer ret_num_of_transfers ; integer ret_num_of_cycles ;
 
ok = 1'b1 ;
 
// wait for bridge's master to start transaction
@(posedge pci_clock) ;
while ( FRAME === 1 )
@(posedge pci_clock) ;
monitor32.get_pci_op(ret_adr, ret_bc) ;
 
// start behavioral master request
PCIU_MEM_WRITE("MEM_WRITE ", `Test_Master_1,
target_address, wmem_data[0], `Test_All_Bytes,
1, 8'h3_0, `Test_One_Zero_Target_WS,
`Test_Devsel_Medium, `Test_Target_Normal_Completion);
if (ret_adr !== target_address)
begin
$display("%m detected an error!") ;
test_fail("invalid address was detected when PCI Master initiated a burst read operation") ;
ok = 0 ;
end
 
do_pause ( 1 ) ;
if (ret_bc !== `BC_MEM_READ_MUL)
begin
$display("%m detected an error!") ;
test_fail("invalid bus command was detected when PCI Master should initiate a burst read operation") ;
ok = 0 ;
end
 
// remove the grant from PCI Bridge
tc_gnt_allow = 1'b1 ;
 
fork
begin
monitor32.get_pci_op_num_of_transfers(ret_num_of_transfers, ret_gnt_deasserted) ;
end
begin
monitor32.get_pci_op_num_of_cycles(ret_num_of_cycles) ;
end
join
 
// put arbiter back into the control of the grant line
tc_gnt_allow = 1'b0 ;
// check number of cycles bridge kept the frame asserted!
if (ret_gnt_deasserted !== 1'b1)
begin
$display("%m detected an error!") ;
test_fail("GNT line wasn't deasserted during latency timer operation tests") ;
ok = 0 ;
end
else
begin
if (ret_num_of_cycles > 2)
begin
$display("%m detected an error!") ;
test_fail("PCI Master was expected to deassert FRAME after two cycles and it didn't do that!") ;
ok = 0 ;
end
end
 
if (ret_num_of_transfers !== 2)
begin
$display("%m detected an error!") ;
test_fail("PCI Master must didn't transfer 2 words in a burst, latency timer was set to a value of 2 and timeout occured") ;
ok = 0 ;
end
end
begin
pci_transaction_progress_monitor( target_address, `BC_MEM_READ_MUL, 0, 2, 1'b0, 1'b1, 0, ok ) ;
if ( ok !== 1 )
test_fail("bridge did invalid memory read transaction or none at all or behavioral target didn't respond as expected") ;
end
join
 
// check data provided by target
7811,6 → 7947,7
end
end
end
 
if ( ok )
test_ok ;
 
9226,7 → 9363,6
input doing_fast_back_to_back ;
output ok ;
reg in_use ;
integer deadlock_counter ;
integer transfer_counter ;
integer cycle_counter ;
integer deadlock_max_val ;
9239,188 → 9375,82
disable main ;
end
 
// approximate number of cycles on WB bus for maximum transaction length
deadlock_max_val = wb_init_waits + 100 +
`WBW_DEPTH *
(wb_subseq_waits + 1 +
`ifdef REGISTER_WBS_OUTPUTS
1) ;
`else
0) ;
`endif
// number of ns to wait before timeout occurs
deadlock_max_val = `PCIW_DEPTH * 10 ;
deadlock_max_val = deadlock_max_val + `PCIR_DEPTH * 30 ;
 
// time used for maximum transaction length on WB
deadlock_max_val = deadlock_max_val * ( `WB_PERIOD ) ;
 
// maximum pci clock cycles
// time used for maximum transaction length on PCI
`ifdef PCI33
deadlock_max_val = deadlock_max_val / 30 + 100 ;
deadlock_max_val = deadlock_max_val * ( 30 ) ;
`else
deadlock_max_val = deadlock_max_val / 15 + 100 ;
deadlock_max_val = deadlock_max_val * ( 15 ) ;
`endif
 
deadlock_max_val = deadlock_max_val + (`WBW_DEPTH * 10 * `WB_PERIOD) ;
deadlock_max_val = deadlock_max_val + (`WBR_DEPTH * 30 * `WB_PERIOD) ;
 
in_use = 1 ;
ok = 1 ;
 
fork
begin:wait_start
monitor32.get_pci_op.timeout_val = deadlock_max_val ;
 
deadlock_counter = 0 ;
begin:monitor_blk
reg [31:0 ] returned_adr ;
reg [ 3:0 ] returned_cmd ;
reg ret_gnt_deasserted ;
 
@(posedge pci_clock) ;
monitor32.get_pci_op(returned_adr, returned_cmd) ;
 
if ( doing_fast_back_to_back !== 1 )
begin
while ( (FRAME !== 1) && (deadlock_counter < deadlock_max_val) )
begin
if ( (IRDY == 0) && ((TRDY == 0) || (STOP == 0)) )
deadlock_counter = 0 ;
else
deadlock_counter = deadlock_counter + 1 ;
@(posedge pci_clock) ;
end
if ( FRAME !== 1 )
begin
$display("pci_transaction_progress_monitor task waited for 1000 cycles for previous transaction to complete! Time %t ", $time) ;
in_use = 0 ;
ok = 0 ;
disable main ;
end
end
 
deadlock_counter = 0 ;
while ( (FRAME !== 0) && (deadlock_counter < deadlock_max_val) )
begin
deadlock_counter = deadlock_counter + 1 ;
@(posedge pci_clock) ;
end
 
if ( FRAME !== 0 )
begin
$display("pci_transaction_progress_monitor task waited for 1000 cycles for transaction to start! Time %t ", $time) ;
in_use = 0 ;
ok = 0 ;
disable main ;
end
end //wait_start
 
begin:addr_bc_monitor
 
@(posedge pci_clock) ;
 
if ( doing_fast_back_to_back !== 1 )
begin
while ( FRAME !== 1 )
@(posedge pci_clock) ;
end
 
while( FRAME !== 0 )
@(posedge pci_clock) ;
 
// Address during Interrupt Acknowledge cycle has don't care value - don't check it
if ( bus_command !== `BC_IACK )
begin
if ( AD !== address )
if ( returned_adr !== address )
begin
$display("pci_transaction_progress_monitor detected unexpected address on PCI! Time %t ", $time) ;
$display("Expected address = %h, detected address = %h ", address, AD) ;
$display("Expected address = %h, detected address = %h ", address, returned_adr) ;
ok = 0 ;
end
end
 
if ( CBE !== bus_command )
if ( returned_cmd !== bus_command )
begin
$display("pci_transaction_progress_monitor detected unexpected bus command on PCI! Time %t ", $time) ;
$display("Expected bus command = %b, detected bus command = %b", bus_command, CBE) ;
$display("Expected bus command = %b, detected bus command = %b", bus_command, returned_cmd) ;
ok = 0 ;
end
end //addr_bc_monitor
 
begin:transfer_checker
transfer_counter = 0 ;
 
@(posedge pci_clock) ;
 
if ( doing_fast_back_to_back !== 1 )
fork
begin
while ( FRAME !== 1 )
@(posedge pci_clock) ;
end
 
while( FRAME !== 0 )
@(posedge pci_clock) ;
 
while( FRAME === 0 )
begin
if ( (IRDY === 0) && (TRDY === 0) && (DEVSEL === 0) )
transfer_counter = transfer_counter + 1 ;
@(posedge pci_clock) ;
end
 
while( (IRDY === 0) && (TRDY === 1) && (STOP === 1) )
begin
@(posedge pci_clock) ;
end
 
if ( (TRDY === 0) && (DEVSEL === 0) )
transfer_counter = transfer_counter + 1 ;
 
if ( check_transfers === 1 )
begin
if ( transfer_counter !== num_of_transfers )
if ( check_transfers === 1 )
begin
$display("pci_transaction_progress_monitor detected unexpected transaction! Time %t ", $time) ;
$display("Expected transfers in transaction = %d, actual transfers = %d ", num_of_transfers, transfer_counter) ;
ok = 0 ;
monitor32.get_pci_op_num_of_transfers(transfer_counter, ret_gnt_deasserted) ;
if ( transfer_counter !== num_of_transfers )
begin
$display("pci_transaction_progress_monitor detected unexpected transaction! Time %t ", $time) ;
$display("Expected transfers in transaction = %d, actual transfers = %d ", num_of_transfers, transfer_counter) ;
ok = 0 ;
end
end
end
end //transfer_checker
begin:cycle_checker
if ( check_cycles )
begin
cycle_counter = 0 ;
@(posedge pci_clock) ;
 
if ( doing_fast_back_to_back !== 1)
if ( check_cycles === 1'b1)
begin
while ( FRAME !== 1 )
@(posedge pci_clock) ;
end
 
while( FRAME !== 0 )
@(posedge pci_clock) ;
 
while ( (FRAME !== 1) && (cycle_counter < num_of_cycles) )
begin
cycle_counter = cycle_counter + 1 ;
@(posedge pci_clock) ;
end
 
if ( FRAME !== 1 )
begin
while ((FRAME === 0) && (MAS0_GNT === 0))
@(posedge pci_clock) ;
 
if ( FRAME !== 1 )
monitor32.get_pci_op_num_of_cycles(cycle_counter) ;
if (cycle_counter > num_of_cycles)
begin
while( (IRDY === 1) || ((TRDY === 1) && (STOP === 1)) )
@(posedge pci_clock) ;
 
@(posedge pci_clock) ;
 
if ( FRAME !== 1 )
begin
$display("pci_transaction_progress_monitor detected invalid transaction length! Time %t ", $time) ;
$display("Possibility of wrong operation in latency timer logic exists!") ;
ok = 0 ;
end
$display("pci_transaction_progress_monitor detected invalid transaction length! Time %t ", $time) ;
$display("Possibility of wrong operation in latency timer logic exists!") ;
ok = 0 ;
end
end
end
end // cycle_checker
join
join
 
end //monitor_blk
 
in_use = 0 ;
 
end
endtask //pci_transaction_progress_monitor
 
9440,7 → 9470,6
input check_transfers ;
output ok ;
reg in_use ;
integer deadlock_counter ;
integer transfer_counter ;
integer deadlock_max_val ;
reg [2:0] slave_termination ;
9453,20 → 9482,19
disable main ;
end
 
// number of cycles on WB bus for maximum transaction length
deadlock_max_val = pci_init_waits + 100 +
`PCIW_DEPTH *
(pci_subseq_waits + 1) ;
// number of ns to wait before timeout occurs
deadlock_max_val = `PCIW_DEPTH * 10 ;
deadlock_max_val = deadlock_max_val + `PCIR_DEPTH * 30 ;
 
// time used for maximum transaction length on PCI
`ifdef PCI33
deadlock_max_val = deadlock_max_val * ( 30 ) + 100 ;
deadlock_max_val = deadlock_max_val * ( 30 ) ;
`else
deadlock_max_val = deadlock_max_val * ( 15 ) + 100 ;
deadlock_max_val = deadlock_max_val * ( 15 ) ;
`endif
 
// maximum wb clock cycles
deadlock_max_val = deadlock_max_val / (`WB_PERIOD) ;
deadlock_max_val = deadlock_max_val + (`WBW_DEPTH * 10 * `WB_PERIOD) ;
deadlock_max_val = deadlock_max_val + (`WBR_DEPTH * 30 * `WB_PERIOD) ;
 
in_use = 1 ;
ok = 1 ;
9474,38 → 9502,11
 
fork
begin:wait_start
deadlock_counter = 0 ;
@(posedge wb_clock) ;
while ( (CYC_O !== 0 && CYC_O_previous !== 0) && (deadlock_counter < deadlock_max_val) )
begin
if ((!STB_O) || (!ACK_I && !RTY_I && !ERR_I))
deadlock_counter = deadlock_counter + 1 ;
else
deadlock_counter = 0;
@(posedge wb_clock) ;
end
if ( CYC_O !== 0 && CYC_O_previous !== 0)
begin
$display("wb_transaction_progress_monitor task waited for 1000 cycles for previous transaction to complete! Time %t ", $time) ;
in_use = 0 ;
ok = 0 ;
disable main ;
end
 
deadlock_counter = 0 ;
while ( (CYC_O !== 1) && (deadlock_counter < deadlock_max_val) )
begin
deadlock_counter = deadlock_counter + 1 ;
@(posedge wb_clock) ;
end
 
if ( CYC_O !== 1 )
begin
$display("wb_transaction_progress_monitor task waited for 1000 cycles for transaction to start! Time %t ", $time) ;
in_use = 0 ;
ok = 0 ;
disable main ;
end
#(deadlock_max_val) ;
$display("%m timeout! Time %t ", $time) ;
in_use = 0 ;
ok = 0 ;
disable main ;
end //wait_start
begin:addr_monitor
@(posedge wb_clock) ;
9533,6 → 9534,7
$display("Expected address = %h, detected address = %h ", address, ADR_O) ;
ok = 0 ;
end
disable wait_start ;
end
begin:transfer_checker
transfer_counter = 0 ;
9614,7 → 9616,6
input check_transfers ;
output ok ;
reg in_use ;
integer deadlock_counter ;
integer transfer_counter ;
integer deadlock_max_val ;
begin:main
9625,20 → 9626,19
disable main ;
end
 
// number of cycles on WB bus for maximum transaction length
deadlock_max_val = pci_init_waits + 100 +
`PCIW_DEPTH *
(pci_subseq_waits + 1) ;
// number of ns to wait before timeout occurs
deadlock_max_val = `PCIW_DEPTH * 10 ;
deadlock_max_val = deadlock_max_val + `PCIR_DEPTH * 30 ;
 
// time used for maximum transaction length on PCI
`ifdef PCI33
deadlock_max_val = deadlock_max_val * ( 30 ) + 100 ;
deadlock_max_val = deadlock_max_val * ( 30 ) ;
`else
deadlock_max_val = deadlock_max_val * ( 15 ) + 100 ;
deadlock_max_val = deadlock_max_val * ( 15 ) ;
`endif
 
// maximum wb clock cycles
deadlock_max_val = deadlock_max_val / (`WB_PERIOD) ;
deadlock_max_val = deadlock_max_val + (`WBW_DEPTH * 10 * `WB_PERIOD) ;
deadlock_max_val = deadlock_max_val + (`WBR_DEPTH * 30 * `WB_PERIOD) ;
 
in_use = 1 ;
ok = 1 ;
9645,38 → 9645,11
 
fork
begin:wait_start
deadlock_counter = 0 ;
@(posedge wb_clock) ;
while ( (CYC_O !== 0) && (deadlock_counter < deadlock_max_val) )
begin
if ((!STB_O) || (!ACK_I && !RTY_I && !ERR_I))
deadlock_counter = deadlock_counter + 1 ;
else
deadlock_counter = 0;
@(posedge wb_clock) ;
end
if ( CYC_O !== 0 )
begin
$display("wb_transaction_progress_monitor task waited for 1000 cycles for previous transaction to complete! Time %t ", $time) ;
in_use = 0 ;
ok = 0 ;
disable main ;
end
 
deadlock_counter = 0 ;
while ( (CYC_O !== 1) && (deadlock_counter < deadlock_max_val) )
begin
deadlock_counter = deadlock_counter + 1 ;
@(posedge wb_clock) ;
end
 
if ( CYC_O !== 1 )
begin
$display("wb_transaction_progress_monitor task waited for 1000 cycles for transaction to start! Time %t ", $time) ;
in_use = 0 ;
ok = 0 ;
disable main ;
end
#(deadlock_max_val) ;
$display("%m timeout! Time %t ", $time) ;
in_use = 0 ;
ok = 0 ;
disable main ;
end //wait_start
begin:addr_monitor
@(posedge wb_clock) ;
9704,6 → 9677,7
$display("Expected address = %h, detected address = %h ", address, ADR_O) ;
ok = 0 ;
end
disable wait_start ;
end
begin:transfer_checker
transfer_counter = 0 ;
10319,8 → 10293,12
reg ok ;
 
reg [31:0] temp_var ;
integer i ;
begin:main
 
if (read0_write1 === 1'b0)
data = 32'hxxxx_xxxx ;
 
if ( in_use === 1 )
begin
$display("generate_configuration_cycle task re-entered! Time %t ", $time) ;
10350,9 → 10328,29
 
write_data`WRITE_ADDRESS = temp_var + { 4'h1, `CNF_ADDR_ADDR, 2'b00 } ;
write_data`WRITE_DATA = { 8'h00, bus_num, device_num, func_num, reg_num, type } ;
 
`ifdef PCI_WBS_ALLOW_NON_ALLIGNED_CONFIG_ACCESS
 
write_data`WRITE_SEL = 4'b0001 ;
repeat(4)
begin
wishbone_master.wb_single_write(write_data, flags, write_status) ;
 
// check if write succeeded
if (write_status`CYC_ACTUAL_TRANSFER !== 1)
begin
$display("Configuration cycle generation failed! Couldn't write to configuration address register! Time %t ", $time) ;
in_use = 0 ;
disable main ;
end
 
write_data`WRITE_ADDRESS = write_data`WRITE_ADDRESS + 'h1 ;
write_data`WRITE_SEL = write_data`WRITE_SEL << 1 ;
end
 
`else
write_data`WRITE_SEL = 4'hF ;
write_data`WRITE_TAG_STIM = 0 ;
 
wishbone_master.wb_single_write(write_data, flags, write_status) ;
 
// check if write succeeded
10359,11 → 10357,12
if (write_status`CYC_ACTUAL_TRANSFER !== 1)
begin
$display("Configuration cycle generation failed! Couldn't write to configuration address register! Time %t ", $time) ;
data = 32'hxxxx_xxxx ;
in_use = 0 ;
disable main ;
end
 
`endif
 
// setup flags for wb master to handle retries and read and write data
flags`WB_TRANSFER_AUTO_RTY = 1 ;
 
10371,54 → 10370,95
write_data`WRITE_ADDRESS = read_data`READ_ADDRESS ;
read_data`READ_SEL = byte_enables ;
write_data`WRITE_SEL = byte_enables ;
read_data`READ_TAG_STIM = 0 ;
write_data`WRITE_TAG_STIM = 0 ;
write_data`WRITE_DATA = data ;
 
ok = 0 ;
 
fork
temp_var = 32'hxxxx_xxxx ;
 
`ifdef PCI_WBS_ALLOW_NON_ALLIGNED_CONFIG_ACCESS
 
for (i = 0 ; i < 4 ; i = i + 1)
begin
if (read0_write1 === 0)
wishbone_master.wb_single_read(read_data, flags, read_status) ;
else
if (read0_write1 === 1)
wishbone_master.wb_single_write(write_data, flags, write_status) ;
end
begin
pci_transaction_progress_monitor
(
pci_address, // expected address on PCI bus
read0_write1 ? `BC_CONF_WRITE : `BC_CONF_READ, // expected bus command on PCI bus
1, // expected number of succesfull data phases
0, // expected number of cycles the transaction will take on PCI bus
1'b0, // monitor checking/not checking number of transfers
1'b0, // monitor checking/not checking number of cycles
0, // tell to monitor if it has to expect a fast back to back transaction
ok // status - 1 success, 0 failure
) ;
end
join
 
// check if transfer succeeded
if ((read0_write1 ? write_status`CYC_ACTUAL_TRANSFER : read_status`CYC_ACTUAL_TRANSFER) !== 1)
if (byte_enables[i] === 1'b1)
begin
read_data`READ_SEL = 4'h1 << i ;
write_data`WRITE_SEL = read_data`READ_SEL ;
 
`else
 
begin
$display("Configuration cycle generation failed! Configuration cycle not processed correctly by the bridge! Time %t ", $time) ;
data = 32'hxxxx_xxxx ;
in_use = 0 ;
disable main ;
end
begin
 
if (!ok)
begin
data = 32'hxxxx_xxxx ;
in_use = 0 ;
disable main ;
`endif
 
fork
begin
if (read0_write1 === 0)
wishbone_master.wb_single_read(read_data, flags, read_status) ;
else if (read0_write1 === 1)
wishbone_master.wb_single_write(write_data, flags, write_status) ;
 
// check if transfer succeeded
if ((read0_write1 ? write_status`CYC_ACTUAL_TRANSFER : read_status`CYC_ACTUAL_TRANSFER) !== 1)
begin
$display("Configuration cycle generation failed! Configuration cycle not processed correctly by the bridge! Time %t ", $time) ;
data = 32'hxxxx_xxxx ;
in_use = 0 ;
disable main ;
end
 
end
begin
pci_transaction_progress_monitor
(
pci_address, // expected address on PCI bus
read0_write1 ? `BC_CONF_WRITE : `BC_CONF_READ, // expected bus command on PCI bus
1, // expected number of succesfull data phases
0, // expected number of cycles the transaction will take on PCI bus
1'b0, // monitor checking/not checking number of transfers
1'b0, // monitor checking/not checking number of cycles
0, // tell to monitor if it has to expect a fast back to back transaction
ok // status - 1 success, 0 failure
) ;
 
if (!ok)
begin
data = 32'hxxxx_xxxx ;
in_use = 0 ;
disable main ;
end
end
join
 
`ifdef PCI_WBS_ALLOW_NON_ALLIGNED_CONFIG_ACCESS
 
temp_var = read_status`READ_DATA ;
 
if (read0_write1 === 0)
begin
case(read_data`READ_SEL)
4'b0001:data[ 7:0 ] = temp_var[ 7:0 ] ;
4'b0010:data[15:8 ] = temp_var[15:8 ] ;
4'b0100:data[23:16] = temp_var[23:16] ;
4'b1000:data[31:24] = temp_var[31:24] ;
endcase
end
 
`else
 
if (read0_write1 === 0)
data = read_status`READ_DATA ;
 
`endif
 
end
read_data`READ_ADDRESS = read_data`READ_ADDRESS + 1'b1 ;
write_data`WRITE_ADDRESS = write_data`WRITE_ADDRESS + 1'b1 ;
end
 
if (read0_write1 === 0)
data = read_status`READ_DATA ;
 
in_use = 0 ;
end
endtask // generate_configuration_cycle
10466,7 → 10506,6
temp_var[15:11] = `TAR1_IDSEL_INDEX - 11 ; // device number field
write_data`WRITE_DATA = temp_var ;
write_data`WRITE_SEL = 4'hF ;
write_data`WRITE_TAG_STIM = 0 ;
 
wishbone_master.wb_single_write(write_data, flags, write_status) ;
 
10489,8 → 10528,6
write_data`WRITE_ADDRESS = read_data`READ_ADDRESS ;
read_data`READ_SEL = 4'hF ;
write_data`WRITE_SEL = 4'hF ;
read_data`READ_TAG_STIM = 0 ;
write_data`WRITE_TAG_STIM = 0 ;
write_data`WRITE_DATA = 32'hAAAA_AAAA ;
 
ok_pci = 0 ;
10669,7 → 10706,6
write_data`WRITE_ADDRESS = temp_var + { 4'h1, `CNF_ADDR_ADDR, 2'b00 } ;
write_data`WRITE_DATA = pci_address ;
write_data`WRITE_SEL = 4'hF ;
write_data`WRITE_TAG_STIM = 0 ;
 
wishbone_master.wb_single_write(write_data, flags, write_status) ;
 
10692,8 → 10728,6
write_data`WRITE_ADDRESS = read_data`READ_ADDRESS ;
read_data`READ_SEL = 4'hF ;
write_data`WRITE_SEL = 4'hF ;
read_data`READ_TAG_STIM = 0 ;
write_data`WRITE_TAG_STIM = 0 ;
write_data`WRITE_DATA = 32'hAAAA_AAAA ;
 
ok_pci = 0 ;
10832,7 → 10866,6
write_data`WRITE_ADDRESS = temp_var + { 4'h1, `CNF_ADDR_ADDR, 2'b00 } ;
write_data`WRITE_DATA = pci_address ;
write_data`WRITE_SEL = 4'hF ;
write_data`WRITE_TAG_STIM = 0 ;
 
wishbone_master.wb_single_write(write_data, flags, write_status) ;
 
10855,8 → 10888,6
write_data`WRITE_ADDRESS = read_data`READ_ADDRESS ;
read_data`READ_SEL = 4'hF ;
write_data`WRITE_SEL = 4'hF ;
read_data`READ_TAG_STIM = 0 ;
write_data`WRITE_TAG_STIM = 0 ;
write_data`WRITE_DATA = 32'hAAAA_AAAA ;
 
ok_pci = 0 ;
10995,7 → 11026,6
write_data`WRITE_ADDRESS = temp_var + { 4'h1, `CNF_ADDR_ADDR, 2'b00 } ;
write_data`WRITE_DATA = pci_address ;
write_data`WRITE_SEL = 4'hF ;
write_data`WRITE_TAG_STIM = 0 ;
 
wishbone_master.wb_single_write(write_data, flags, write_status) ;
 
11018,8 → 11048,6
write_data`WRITE_ADDRESS = read_data`READ_ADDRESS ;
read_data`READ_SEL = 4'b0101 ;
write_data`WRITE_SEL = 4'b1010 ;
read_data`READ_TAG_STIM = 0 ;
write_data`WRITE_TAG_STIM = 0 ;
write_data`WRITE_DATA = 32'hAAAA_AAAA ;
 
ok_pci = 0 ;
12490,7 → 12518,6
 
write_data`WRITE_ADDRESS = { `WB_CONFIGURATION_BASE, offset } ;
write_data`WRITE_SEL = 4'h1 ;
write_data`WRITE_TAG_STIM = 0 ;
write_data`WRITE_DATA = data ;
 
next_test_name[79:0] <= "Init_Tar_R";
12510,7 → 12537,6
 
write_data`WRITE_ADDRESS = temp_var + offset ;
write_data`WRITE_SEL = 4'hf ;
write_data`WRITE_TAG_STIM = 0 ;
write_data`WRITE_DATA = data ;
 
`ifdef NO_CNF_IMAGE
12591,7 → 12617,6
 
write_data`WRITE_ADDRESS = temp_var + offset ;
write_data`WRITE_SEL = 4'h1 ;
write_data`WRITE_TAG_STIM = 0 ;
write_data`WRITE_DATA = data ;
 
next_test_name[79:0] <= "Init_Tar_R";
12608,7 → 12633,6
 
write_data`WRITE_ADDRESS = temp_var + offset ;
write_data`WRITE_SEL = 4'hf ;
write_data`WRITE_TAG_STIM = 0 ;
write_data`WRITE_DATA = data ;
 
`ifdef NO_CNF_IMAGE
12635,7 → 12659,6
 
write_data`WRITE_ADDRESS = temp_var + offset ;
write_data`WRITE_SEL = 4'hf ;
write_data`WRITE_TAG_STIM = 0 ;
write_data`WRITE_DATA = data ;
 
$display(" bridge target - Setting base address P_BA1 to 32'h %h !", data);
12651,7 → 12674,6
 
write_data`WRITE_ADDRESS = temp_var + offset ;
write_data`WRITE_SEL = 4'hf ;
write_data`WRITE_TAG_STIM = 0 ;
write_data`WRITE_DATA = data ;
 
$display(" bridge target - Setting base address P_BA2 to 32'h %h !", data);
12667,7 → 12689,6
 
write_data`WRITE_ADDRESS = temp_var + offset ;
write_data`WRITE_SEL = 4'hf ;
write_data`WRITE_TAG_STIM = 0 ;
write_data`WRITE_DATA = data ;
 
$display(" bridge target - Setting base address P_BA3 to 32'h %h !", data);
12683,7 → 12704,6
 
write_data`WRITE_ADDRESS = temp_var + offset ;
write_data`WRITE_SEL = 4'hf ;
write_data`WRITE_TAG_STIM = 0 ;
write_data`WRITE_DATA = data ;
 
$display(" bridge target - Setting base address P_BA4 to 32'h %h !", data);
12699,7 → 12719,6
 
write_data`WRITE_ADDRESS = temp_var + offset ;
write_data`WRITE_SEL = 4'hf ;
write_data`WRITE_TAG_STIM = 0 ;
write_data`WRITE_DATA = data ;
 
$display(" bridge target - Setting base address P_BA5 to 32'h %h !", data);
19170,7 → 19189,6
// initiate a read request
read_data`READ_ADDRESS = target_address ;
read_data`READ_SEL = 4'hF ;
read_data`READ_TAG_STIM = 0 ;
wishbone_master.wb_single_read( read_data, write_flags, read_status ) ;
if ((read_status`CYC_ACTUAL_TRANSFER !== 0) || (read_status`CYC_RTY !== 1'b1))
begin
19201,7 → 19219,6
// now perform a read
read_data`READ_ADDRESS = target_address + 4 ;
read_data`READ_SEL = 4'hF ;
read_data`READ_TAG_STIM = 0 ;
wishbone_master.wb_single_read( read_data, write_flags, read_status ) ;
if (read_status`CYC_ACTUAL_TRANSFER !== 1)
begin
19307,7 → 19324,6
temp_var[(31 - `WB_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
write_data`WRITE_ADDRESS = temp_var + offset ;
write_data`WRITE_SEL = byte_enable ;
write_data`WRITE_TAG_STIM = 0 ;
write_data`WRITE_DATA = data ;
 
wishbone_master.wb_single_write( write_data, write_flags, write_status ) ;
19392,7 → 19408,6
 
read_data`READ_ADDRESS = temp_var + offset ;
read_data`READ_SEL = byte_enable ;
read_data`READ_TAG_STIM = 0 ;
 
wishbone_master.wb_single_read( read_data, read_flags, read_status ) ;
if (read_status`CYC_ACTUAL_TRANSFER !== 1)
20075,7 → 20090,6
// do one dummy read, to receive bus gnt
read_data`READ_ADDRESS = target_address ;
read_data`READ_SEL = 4'hF ;
read_data`READ_TAG_STIM = 0 ;
 
// handle retries
flags`WB_TRANSFER_AUTO_RTY = 1 ;
20116,7 → 20130,6
// read data back
read_data`READ_ADDRESS = target_address + 64 ;
read_data`READ_SEL = 4'hF ;
read_data`READ_TAG_STIM = 0 ;
 
// handle retries
flags`WB_TRANSFER_AUTO_RTY = 1 ;
20139,7 → 20152,6
// read second data back
read_data`READ_ADDRESS = target_address + 128 ;
read_data`READ_SEL = 4'hF ;
read_data`READ_TAG_STIM = 0 ;
 
// handle retries
flags`WB_TRANSFER_AUTO_RTY = 1 ;
20436,18 → 20448,13
endtask // test_target_overload
 
task test_master_overload ;
 
reg ok_pci ;
reg ok_wb ;
reg ok ;
reg [2:0] test_image_num ;
integer transfered ;
reg [2:0] received_termination ;
integer total_transfers ;
reg [31:0] transaction_sizes [0:4095] ;
integer pci_transaction_num ;
integer wb_transaction_num ;
reg [31:0] current_pci_address ;
integer current_size ;
 
reg `WRITE_STIM_TYPE write_data ;
 
20457,10 → 20464,6
reg [31:0] image_base ;
reg [31:0] target_address ;
 
integer i ;
integer j ;
integer k ;
integer l ;
begin:main
 
// set behavioral target to respond normally
20499,7 → 20502,6
write_flags`SUBSEQ_WAITS = wb_subseq_waits ;
write_flags`WB_TRANSFER_AUTO_RTY = 0 ;
write_flags`WB_TRANSFER_CAB = 1'b1 ;
write_flags`WB_FAST_B2B = 1'b1 ;
 
pci_configure_wb_slave_image
(
20524,107 → 20526,150
ok_wb = 1 ;
ok_pci = 1 ;
 
total_transfers = 0 ;
fork
begin:wb_write_overflow_blk
integer current_write_size ;
integer total_wb_transfers ;
reg [11:0] wb_transaction_num ;
integer i ;
 
for (current_size = 1 ; (current_size <= 1024) && ok_pci && ok_wb && ok ; current_size = current_size * 2)
begin
wb_transaction_num = 0 ;
transaction_sizes[wb_transaction_num[11:0]] = 0 ;
 
// fill wishbone master's memory with data - inverted addresses
write_data = 0 ;
write_data`WRITE_SEL = 4'hF ;
for (i = 0 ; i < current_size ; i = i + 1)
for (current_write_size = 1 ; (current_write_size <= 1024) & ok_pci & ok_wb & ok ; current_write_size = current_write_size * 2)
begin
write_data`WRITE_ADDRESS = image_base + ((('d1024 - current_size) * 4) + (i * 4)) ;
write_data`WRITE_DATA = ~(write_data`WRITE_ADDRESS);
wishbone_master.blk_write_data[i] = write_data ;
end
 
total_transfers = 0 ;
pci_transaction_num = 0 ;
wb_transaction_num = 0 ;
 
current_pci_address = image_base + ('d1024 - current_size) * 4 ;
fork
begin
while ((total_transfers < current_size) && ok_pci && ok_wb && ok)
// fill wishbone master's memory with data - inverted addresses
write_data = 0 ;
write_data`WRITE_SEL = 4'hF ;
for (i = 0 ; i < current_write_size ; i = i + 1)
begin
// try transfering 4kB with no wait cycles through the wb slave unit
write_flags`WB_TRANSFER_SIZE = current_size - total_transfers ;
write_data`WRITE_ADDRESS = image_base + ((('d1024 - current_write_size) * 4) + (i * 4)) ;
write_data`WRITE_DATA = ~(write_data`WRITE_ADDRESS);
wishbone_master.blk_write_data[i] = write_data ;
end
total_wb_transfers = 0 ;
write_flags`WB_FAST_B2B = 1'b0 ;
while ((total_wb_transfers < current_write_size) & ok_pci & ok_wb & ok)
begin
write_flags`WB_TRANSFER_SIZE = current_write_size - total_wb_transfers ;
wishbone_master.wb_block_write(write_flags, write_status) ;
if (write_status`CYC_ERR || ((write_status`CYC_ERR !== 1'b1) && (write_status`CYC_RTY !== 1'b1) && (write_status`CYC_ACK !== 1'b1)))
write_flags`WB_FAST_B2B = 1'b1 ;
 
if (write_status`CYC_ERR | ((write_status`CYC_ERR !== 1'b1) & (write_status`CYC_RTY !== 1'b1) & (write_status`CYC_ACK !== 1'b1)))
begin
$display("%m detected an error!") ;
test_fail("Wishbone slave signaled an error or did not respond to normal write access") ;
ok_wb = 0 ;
end
 
transfered = write_status`CYC_ACTUAL_TRANSFER ;
total_transfers = total_transfers + transfered ;
if (transfered > 0)
total_wb_transfers = total_wb_transfers + write_status`CYC_ACTUAL_TRANSFER ;
 
if (write_status`CYC_ACTUAL_TRANSFER > 0)
begin
transaction_sizes[wb_transaction_num[11:0]] = transfered ;
wishbone_master.shift_write_buffer(transfered) ;
transaction_sizes[wb_transaction_num[11:0]] = write_status`CYC_ACTUAL_TRANSFER ;
wishbone_master.shift_write_buffer(write_status`CYC_ACTUAL_TRANSFER) ;
 
wb_transaction_num = wb_transaction_num + 1'b1 ;
transaction_sizes[wb_transaction_num[11:0]] = 0 ;
end
end
end
begin:pci_models_monitoring
while (((total_transfers < current_size) || (wb_transaction_num > pci_transaction_num)) && ok_pci && ok_wb && ok)
end
begin:pci_models_monitoring
reg [31:0] ret_adr ; reg [3:0] ret_bc ; integer ret_num_of_transfers ; integer total_ret_num_of_transfers ;
reg ret_gnt_deasserted ;
integer current_write_size ; reg [11:0] pci_transaction_num ; reg [31:0] current_pci_address ;
integer i ;
 
pci_transaction_num = 0 ;
 
for (current_write_size = 1 ; (current_write_size <= 1024) & ok_pci & ok_wb & ok ; current_write_size = current_write_size * 2)
begin
 
current_pci_address = image_base + ('d1024 - current_write_size) * 4 ;
 
total_ret_num_of_transfers = 0 ;
 
while ( (total_ret_num_of_transfers < current_write_size) & ok_pci & ok_wb & ok )
begin
wait(wb_transaction_num > pci_transaction_num) ;
pci_transaction_progress_monitor
(
current_pci_address, // address
`BC_MEM_WRITE, // bus_command
transaction_sizes[pci_transaction_num[11:0]], // num_of_transfers
0, // num_of_cycles
1'b1, // check_transfers
1'b0, // check_cycles
1'b0, // doing_fast_back_to_back
ok_pci // ok
) ;
monitor32.get_pci_op(ret_adr, ret_bc) ;
monitor32.get_pci_op_num_of_transfers(ret_num_of_transfers, ret_gnt_deasserted) ;
 
wait( transaction_sizes[pci_transaction_num[11:0]] > 0) ;
 
if (ret_adr !== current_pci_address)
begin
$display("%m detected an error!") ;
test_fail("PCI Master provided unexpected address when it initiated write operation") ;
ok_pci = 1'b0 ;
end
 
if (ret_bc !== `BC_MEM_WRITE)
begin
$display("%m detected an error!") ;
test_fail("PCI Master provided unexpected bus command when it should initiate write operation") ;
ok_pci = 1'b0 ;
end
 
if (ret_num_of_transfers !== transaction_sizes[pci_transaction_num[11:0]])
begin
$display("%m detected an error!") ;
test_fail("PCI Master didn't transfer expected number of words during a burst transfer") ;
ok_pci = 1'b0 ;
end
 
total_ret_num_of_transfers = total_ret_num_of_transfers + ret_num_of_transfers ;
 
current_pci_address = current_pci_address + (4 * transaction_sizes[pci_transaction_num[11:0]]) ;
pci_transaction_num = pci_transaction_num + 1'b1 ;
if (ok_pci !== 1'b1)
end
 
// check the written data
@(posedge pci_clock) ;
#1 ;
for (i = 0 ; i < current_write_size ; i = i + 1)
begin:data_chk_blk
reg [31:0] exp_dat ; reg [31:0] act_dat ;
 
exp_dat = image_base + ((('d1024 - current_write_size) * 4) + (i * 4)) ;
exp_dat = ~exp_dat ;
act_dat = pci_behaviorial_device1.pci_behaviorial_target.Test_Device_Mem['d1024 - current_write_size + i] ;
if (exp_dat != act_dat)
begin
test_fail("PCI Transaction progress monitor detected invalid transaction or none at all on PCI bus");
$display("Time %t!", $time) ;
$display("Wrong data written to the target detected! Expected data %h, actual %h", exp_dat, act_dat) ;
test_fail("wrong data was written to the target during the test") ;
ok_pci = 0 ;
disable main ;
end
end
end
 
// wait two cycles for any wrong parity errors etc..
repeat (2)
@(posedge pci_clock) ;
// wait two cycles for any wrong parity errors etc..
repeat (2)
@(posedge pci_clock) ;
 
if (ok)
#1 disable pci_monitoring ;
end
begin:pci_monitoring
@(error_event_int) ;
test_fail("PCI Bus monitor detected invalid operation on PCI bus") ;
ok = 0 ;
ok_pci = 0 ;
ok_wb = 0 ;
end
join
 
// check the written data
for (i = 0 ; i < current_size ; i = i + 1)
begin
write_data`WRITE_ADDRESS = image_base + ((('d1024 - current_size) * 4) + (i * 4)) ;
write_data`WRITE_DATA = ~(write_data`WRITE_ADDRESS);
write_data`WRITE_ADDRESS = pci_behaviorial_device1.pci_behaviorial_target.Test_Device_Mem['d1024 - current_size + i] ;
if (write_data`WRITE_ADDRESS != write_data`WRITE_DATA)
begin
$display("Time %t!", $time) ;
$display("Wrong data written to the target detected! Expected data %h, actual %h", write_data`WRITE_DATA, write_data`WRITE_ADDRESS) ;
test_fail("wrong data was written to the target during the test") ;
disable main ;
end
end
if (ok)
#1 disable pci_monitoring ;
end
begin:pci_monitoring
@(error_event_int) ;
test_fail("PCI Bus monitor detected invalid operation on PCI bus") ;
ok = 0 ;
ok_pci = 0 ;
ok_wb = 0 ;
end
join
if ((ok & ok_wb & ok_pci) === 1'b1)
test_ok ;
 
// next two tests take forever - commented out - they are here, because some bugs were reported
// they are commented out, because no bug could be found with them
/*
20849,32 → 20894,179
test_fail("WB image configuration failed") ;
disable main ;
end
 
if ((ok && ok_wb && ok_pci) === 1'b1)
test_ok ;
end
endtask // test_master_overload
 
`ifdef fofofof
`ifdef PCI_WB_REV_B3
`ifdef PCI_WBS_B3_RTY_DISABLE
task test_wb_slave_with_retry_generation_disabled ;
reg [11:0] ctrl_offset ;
reg [11:0] ba_offset ;
reg [11:0] am_offset ;
reg `WRITE_STIM_TYPE write_data ;
reg `READ_STIM_TYPE read_data ;
reg `READ_RETURN_TYPE read_status ;
 
reg `WRITE_RETURN_TYPE write_status ;
reg `WB_TRANSFER_FLAGS flags ;
reg wb_ok ;
reg pci_ok ;
reg ok ;
reg [11:0] pci_ctrl_offset ;
reg [11:0] cl_size_offset ;
reg [3:0] cl_size_mask ;
reg [31:0] image_base ;
reg [31:0] target_address ;
 
integer i ;
reg [2:0] cur_inc_burst_type ;
 
begin:main
wb_ok = 1'b0 ;
pci_ok = 1'b0 ;
ok = 1'b0 ;
 
test_name = "CONFIGURE WB IMAGE 1 FOR WB SLAVE WITH NO RETRY RESPONSE TESTING" ;
 
pci_ctrl_offset = 12'h4 ;
 
// image 0 can only be configuration image - start with 1
ctrl_offset = {4'h1, `W_IMG_CTRL1_ADDR, 2'b00} ;
ba_offset = {4'h1, `W_BA1_ADDR, 2'b00} ;
am_offset = {4'h1, `W_AM1_ADDR, 2'b00} ;
cl_size_offset = 12'hC ;
cl_size_mask = 4'b0001 ;
 
target_address = `BEH_TAR1_MEM_START ;
image_base = 0 ;
image_base[`PCI_BASE_ADDR0_MATCH_RANGE] = target_address[`PCI_BASE_ADDR0_MATCH_RANGE] ;
 
target_address[31:(32 - `WB_NUM_OF_DEC_ADDR_LINES)] = image_base[31:(32 - `WB_NUM_OF_DEC_ADDR_LINES)] ;
target_address[(31 - `WB_NUM_OF_DEC_ADDR_LINES):0] = image_base[(31 - `WB_NUM_OF_DEC_ADDR_LINES):0] ;
write_flags = 0 ;
write_flags`INIT_WAITS = wb_init_waits ;
write_flags`SUBSEQ_WAITS = wb_subseq_waits ;
write_flags`WB_TRANSFER_AUTO_RTY = 0 ;
 
// enable master & target operation
config_write( pci_ctrl_offset, 32'h0000_0007, 4'h1, ok) ;
if ( ok !== 1 )
begin
$display("No retry response testing failed! Failed to write PCI Device Control register! Time %t ", $time) ;
test_fail("write to PCI Device Control register didn't succeede");
disable main ;
end
 
// prepare image control register
config_write( ctrl_offset, 32'h0000_0000, 4'hF, ok) ;
if ( ok !== 1 )
begin
$display("No retry response testing failed! Failed to write W_IMG_CTRL%d register! Time %t ", 1, $time) ;
test_fail("write to WB Image Control register didn't succeede");
disable main ;
end
 
// prepare base address register
config_write( ba_offset, image_base, 4'hF, ok ) ;
if ( ok !== 1 )
begin
$display("No retry response testing failed! Failed to write W_BA%d register! Time %t ", 1, $time) ;
test_fail("write to WB Base Address register didn't succeede");
disable main ;
end
 
// write address mask register
config_write( am_offset, 32'hFFFF_FFFF, 4'hF, ok ) ;
if ( ok !== 1 )
begin
$display("No retry response testing failed! Failed to write W_AM%d register! Time %t ", 1, $time) ;
test_fail("write to WB Address Mask register didn't succeede");
disable main ;
end
// write cache line size register
config_write( cl_size_offset, 32'h4, cl_size_mask, ok ) ;
if ( ok !== 1 )
begin
$display("No retry response testing failed! Failed to write CACHE LINE SIZE register! Time %t ", $time) ;
test_fail("write to CACHE LINE SIZE register didn't succeede");
disable main ;
end
 
for (cur_inc_burst_type = 0 ; cur_inc_burst_type <= 3 ; cur_inc_burst_type = cur_inc_burst_type + 1'b1)
begin
// prepare write data - prepare enough to fill at least 2 write fifos.
for (i = 0 ; i < ((`PCIW_DEPTH) * 2) ; i = i + 1)
begin
write_data`WRITE_DATA = $random ;
case (cur_inc_burst_type)
2'b00:
begin
write_data`WRITE_ADDRESS = image_base + i * 4 + 'd8 ;
end
2'b01:
begin
write_data`WRITE_ADDRESS = ( image_base[31:4] + (i >> 2) ) << 4 ;
if ( (i % 4) === 0 )
write_data`WRITE_ADDRESS = write_data`WRITE_ADDRESS + 'd8 ;
else
write_data`WRITE_ADDRESS = write_data`WRITE_ADDRESS + (4'd8 + (i * 4 % 4) ;
end
2'b10:
begin
end
2'b11:
begin
end
endcase
 
if (cur_inc_burst_type === 0)
write_data`WRITE_ADDRESS = image_base + i * 4 + 4 ;
 
if ( (i % 4) === 0)
write_data`WRITE_ADDRESS = {image_base[31:4] + (i >> 2), 4'h4}
end
fork
begin
// perform a write with auto retry off, since retries should not be signalled by wishbone slave
flags`WB_TRANSFER_AUTO_RETRY = 1'b0 ;
// check if received termination is not retry nor error
// check if all transfers completed succesfully!
end
begin
// set behavioral target to respond with retry
// check 2 transactions terminated with retry
// set behavioral target to disconnect with data on first transfer
// check the transaction
end
join
end
end
endtask // test_wb_slave_with_retry_generation_disabled
`endif
`endif
`endif
 
task test_fail ;
input [7999:0] failure_reason ;
reg [8007:0] display_failure ;
reg [799:0] display_test ;
begin
tests_failed = tests_failed + 1 ;
 
display_failure = {failure_reason, "!"} ;
while ( display_failure[7999:7992] == 0 )
display_failure = display_failure << 8 ;
 
display_test = test_name ;
while ( display_test[799:792] == 0 )
display_test = display_test << 8 ;
 
$fdisplay( tb_log_file, "************************************************************************************************************************************************************" ) ;
$fdisplay( tb_log_file, " At time %t ", $time ) ;
$fdisplay( tb_log_file, " Test %s", display_test ) ;
$fdisplay( tb_log_file, " Test %0s", test_name ) ;
$fdisplay( tb_log_file, " *FAILED* because") ;
$fdisplay( tb_log_file, " %s", display_failure ) ;
$fdisplay( tb_log_file, " %0s", failure_reason) ;
current_test_parameters ;
$fdisplay( tb_log_file, "************************************************************************************************************************************************************" ) ;
$fdisplay( tb_log_file, " " ) ;
20886,17 → 21078,12
endtask // test_fail
 
task test_ok ;
reg [799:0] display_test ;
begin
tests_successfull = tests_successfull + 1 ;
 
display_test = test_name ;
while ( display_test[799:792] == 0 )
display_test = display_test << 8 ;
 
$fdisplay( tb_log_file, "************************************************************************************************************************************************************" ) ;
$fdisplay( tb_log_file, " At time %t ", $time ) ;
$fdisplay( tb_log_file, " Test %s", display_test ) ;
$fdisplay( tb_log_file, " Test %0s", test_name ) ;
$fdisplay( tb_log_file, " reported *SUCCESSFULL*! ") ;
current_test_parameters ;
$fdisplay( tb_log_file, "************************************************************************************************************************************************************" ) ;
/trunk/bench/verilog/pci_behaviorial_target.v
1,5 → 1,5
//===========================================================================
// $Id: pci_behaviorial_target.v,v 1.4 2002-08-13 11:03:51 mihad Exp $
// $Id: pci_behaviorial_target.v,v 1.5 2003-08-03 18:04:44 mihad Exp $
//
// Copyright 2001 Blue Beaver. All Rights Reserved.
//
205,9 → 205,9
reg [7:0] Latency_Timer;
reg [7:0] Cache_Line_Size;
reg [7:0] Interrupt_Line;
reg [`PCI_BASE_ADDR0_MATCH_RANGE] BAR0; // Base Address Registers, used to match addresses
reg [PCI_BUS_DATA_RANGE:0] BAR0; // Base Address Registers, used to match addresses
`ifdef PCI_BASE_ADDR1_MATCH_ENABLE
reg [`PCI_BASE_ADDR1_MATCH_RANGE] BAR1;
reg [PCI_BUS_DATA_RANGE:0] BAR1;
`endif // PCI_BASE_ADDR1_MATCH_ENABLE
 
wire [15:0] Target_Command =
240,6 → 240,8
task Read_Test_Device_Config_Regs;
input [7:2] reg_number;
output [PCI_BUS_DATA_RANGE:0] Read_Config_Reg;
input [PCI_BUS_CBE_RANGE:0] byte_mask_l ;
 
begin // Addresses except 0, 4, 8, A, 10, 14, 3C all return 0x00
case (reg_number[7:2])
6'h00: Read_Config_Reg = 32'h8000AAAA
252,12 → 254,27
`ifdef PCI_BASE_ADDR1_MATCH_ENABLE
6'h05: Read_Config_Reg = {BAR1[`PCI_BASE_ADDR1_MATCH_RANGE],
`PCI_BASE_ADDR1_FILL, `PCI_BASE_ADDR1_MAP_QUAL};
`else // PCI_BASE_ADDR1_MATCH_ENABLE
6'h05: Read_Config_Reg = 32'h00000000;
`endif // PCI_BASE_ADDR1_MATCH_ENABLE
6'h0F: Read_Config_Reg = {16'h0000, 8'h01, Interrupt_Line[7:0]};
default: Read_Config_Reg = 32'h00000000;
endcase
 
case(reg_number[7:2])
6'h00, 6'h01, 6'h02, 6'h03, 6'h04, 6'h0F `ifdef PCI_BASE_ADDR1_MATCH_ENABLE , 6'h05 `endif :
begin
if (byte_mask_l[3] !== 1'b0)
Read_Config_Reg[31:24] = $random ;
if (byte_mask_l[2] !== 1'b0)
Read_Config_Reg[23:16] = $random ;
if (byte_mask_l[1] !== 1'b0)
Read_Config_Reg[15:8] = $random ;
if (byte_mask_l[0] !== 1'b0)
Read_Config_Reg[7:0] = $random ;
end
endcase
end
endtask
 
301,9 → 318,9
Master_Caused_PERR <= 1'b0;
Latency_Timer <= 8'h00; Cache_Line_Size <= 8'h00;
Interrupt_Line <= 8'h00;
BAR0 <= 8'hXX;
BAR0 <= {PCI_BUS_DATA_RANGE + 1{1'b0}} ;
`ifdef PCI_BASE_ADDR1_MATCH_ENABLE
BAR1 <= 8'hXX;
BAR1 <= {PCI_BUS_DATA_RANGE + 1{1'b0}} ;
`endif // PCI_BASE_ADDR1_MATCH_ENABLE
pending_config_write_request <= 1'b0;
end
365,13 → 382,36
& ~pending_config_reg_write_byte_enables[0])
? pending_config_reg_write_data[7:0] : Cache_Line_Size;
 
BAR0 <= ( (pending_config_reg_write_address[7:2] == 6'h04)
& ~pending_config_reg_write_byte_enables[3])
? pending_config_reg_write_data[`PCI_BASE_ADDR0_MATCH_RANGE] : BAR0;
if (pending_config_reg_write_address[7:2] == 6'h04)
begin
if (~pending_config_reg_write_byte_enables[3])
BAR0[31:24] <= pending_config_reg_write_data[31:24] ;
 
if (~pending_config_reg_write_byte_enables[2])
BAR0[23:16] <= pending_config_reg_write_data[23:16] ;
 
if (~pending_config_reg_write_byte_enables[1])
BAR0[15:8] <= pending_config_reg_write_data[15:8] ;
 
if (~pending_config_reg_write_byte_enables[0])
BAR0[7:0] <= pending_config_reg_write_data[7:0] ;
end
 
`ifdef PCI_BASE_ADDR1_MATCH_ENABLE
BAR1 <= ( (pending_config_reg_write_address[7:2] == 6'h05)
& ~pending_config_reg_write_byte_enables[3])
? pending_config_reg_write_data[`PCI_BASE_ADDR1_MATCH_RANGE] : BAR1;
if (pending_config_reg_write_address[7:2] == 6'h05)
begin
if (~pending_config_reg_write_byte_enables[3])
BAR1[31:24] <= pending_config_reg_write_data[31:24] ;
 
if (~pending_config_reg_write_byte_enables[2])
BAR1[23:16] <= pending_config_reg_write_data[23:16] ;
 
if (~pending_config_reg_write_byte_enables[1])
BAR1[15:8] <= pending_config_reg_write_data[15:8] ;
 
if (~pending_config_reg_write_byte_enables[0])
BAR1[7:0] <= pending_config_reg_write_data[7:0] ;
end
`endif // PCI_BASE_ADDR1_MATCH_ENABLE
Interrupt_Line <= ( (pending_config_reg_write_address[7:2] == 6'h0F)
& ~pending_config_reg_write_byte_enables[0])
575,7 → 615,7
task Fetch_Config_Reg_Data_For_Read_Onto_AD_Bus;
output [PCI_BUS_DATA_RANGE:0] target_read_data;
begin
Read_Test_Device_Config_Regs (hold_target_address[7:2], target_read_data[PCI_BUS_DATA_RANGE:0]);
Read_Test_Device_Config_Regs (hold_target_address[7:2], target_read_data[PCI_BUS_DATA_RANGE:0], cbe_l_now);
hold_target_address[7:2] = hold_target_address[7:2] + 6'h01; // addr++
end
endtask
/trunk/bench/verilog/wb_master32.v
42,6 → 42,10
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3 2003/07/29 08:19:47 mihad
// Found and simulated the problem in the synchronization logic.
// Repaired the synchronization logic in the FIFOs.
//
// Revision 1.2 2003/06/12 02:30:39 mihad
// Update!
//
306,7 → 310,26
num_of_cyc = `WAIT_FOR_RESPONSE ;
 
ADR_O <= #(Tp - `Tsetup) input_data`WRITE_ADDRESS ;
DAT_O <= #(Tp - `Tsetup) input_data`WRITE_DATA ;
 
begin:dat_o_assign_blk
reg [`WB_SEL_WIDTH - 1:0] cur_sel ;
reg [`WB_DATA_WIDTH - 1:0] cur_dat ;
reg [`WB_DATA_WIDTH - 1:0] rnd_dat ;
integer cur_bit ;
 
cur_dat = input_data`WRITE_DATA ;
cur_sel = input_data`WRITE_SEL ;
rnd_dat = $random ;
 
for(cur_bit = 0 ; cur_bit < `WB_DATA_WIDTH ; cur_bit = cur_bit + 1)
begin
if (cur_sel[cur_bit/8] === 1'b1)
DAT_O[cur_bit] <= #(Tp - `Tsetup) cur_dat[cur_bit] ;
else
DAT_O[cur_bit] <= #(Tp - `Tsetup) rnd_dat[cur_bit] ;
end
end
 
SEL_O <= #(Tp - `Tsetup) input_data`WRITE_SEL ;
TAG_O <= #(Tp - `Tsetup) input_data`WRITE_TAG_STIM ;
 
/trunk/bench/verilog/wb_bus_mon.v
43,6 → 43,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2002/08/13 11:03:51 mihad
// Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image
//
// Revision 1.1 2002/02/01 13:39:43 mihad
// Initial testbench import. Still under development
//
90,189 → 93,230
input CAB_O ;
input [31:0] log_file_desc ;
 
always@(posedge CLK_I or posedge RST_I)
always@(posedge CLK_I)
begin
if (RST_I)
if (RST_I !== 1'b0)
begin
// when reset is applied, all control signals must be low
if (CYC_O)
if (CYC_O !== 1'b0)
begin
$display("CYC_O active under reset") ;
$fdisplay(log_file_desc, "CYC_O active under reset") ;
message_out("CYC_O active under reset") ;
end
if (STB_O)
 
if (STB_O !== 1'b0)
begin
$display("STB_O active under reset") ;
$fdisplay(log_file_desc, "STB_O active under reset") ;
message_out("STB_O active under reset") ;
end
/*if (ACK_I)
$display("ACK_I active under reset") ;*/
if (ERR_I)
if (ACK_I !== 1'b0)
message_out("ACK_I active under reset") ;
 
if (ERR_I !== 1'b0)
begin
$display("ERR_I active under reset") ;
$fdisplay(log_file_desc, "ERR_I active under reset") ;
message_out("ERR_I active under reset") ;
end
if (RTY_I)
 
if (RTY_I !== 1'b0)
begin
$display("RTY_I active under reset") ;
$fdisplay(log_file_desc, "RTY_I active under reset") ;
message_out("RTY_I active under reset") ;
end
if (CAB_O)
begin
$display("CAB_O active under reset") ;
$fdisplay(log_file_desc, "CAB_O active under reset") ;
end
 
end // reset
else
if (~CYC_O)
if (CYC_O !== 1'b1)
begin
// when cycle indicator is low, all control signals must be low
if (STB_O)
if (STB_O !== 1'b0)
begin
$display("STB_O active without CYC_O being active") ;
$fdisplay(log_file_desc, "STB_O active without CYC_O being active") ;
message_out("STB_O active without CYC_O being active") ;
end
if (ACK_I)
 
if (ACK_I !== 1'b0)
begin
$display("ACK_I active without CYC_O being active") ;
$fdisplay(log_file_desc, "ACK_I active without CYC_O being active") ;
message_out("ACK_I active without CYC_O being active") ;
end
if (ERR_I)
 
if (ERR_I !== 1'b0)
begin
$display("ERR_I active without CYC_O being active") ;
$fdisplay(log_file_desc, "ERR_I active without CYC_O being active") ;
message_out("ERR_I active without CYC_O being active") ;
end
if (RTY_I)
 
if (RTY_I !== 1'b0)
begin
$display("RTY_I active without CYC_O being active") ;
$fdisplay(log_file_desc, "RTY_I active without CYC_O being active") ;
message_out("RTY_I active without CYC_O being active") ;
end
if (CAB_O)
begin
$display("CAB_O active without CYC_O being active") ;
$fdisplay(log_file_desc, "CAB_O active without CYC_O being active") ;
end
 
end // ~CYC_O
end
 
reg [`WB_DATA_WIDTH-1:0] previous_data ;
reg [`WB_DATA_WIDTH-1:0] previous_data_o ;
reg [`WB_DATA_WIDTH-1:0] previous_data_i ;
reg [`WB_ADDR_WIDTH-1:0] previous_address ;
reg [`WB_SEL_WIDTH-1:0] previous_sel ;
reg [`WB_TAG_WIDTH-1:0] previous_tag ;
reg previous_stb ;
reg previous_ack ;
reg previous_err ;
reg previous_rty ;
reg previous_cyc ;
reg can_change ;
reg previous_we ;
 
always@(posedge CLK_I or posedge RST_I)
begin
if (RST_I)
begin
previous_stb <= 1'b0 ;
previous_ack <= 1'b0 ;
previous_err <= 1'b0 ;
previous_rty <= 1'b0 ;
previous_cyc <= 1'b0 ;
previous_stb <= 1'b0 ;
previous_ack <= 1'b0 ;
previous_err <= 1'b0 ;
previous_rty <= 1'b0 ;
previous_cyc <= 1'b0 ;
previous_tag <= 'd0 ;
previous_we <= 1'b0 ;
previous_data_o <= 0 ;
previous_data_i <= 0 ;
previous_address <= 0 ;
previous_sel <= 0 ;
end
else
begin
previous_stb <= STB_O ;
previous_ack <= ACK_I ;
previous_err <= ERR_I ;
previous_rty <= RTY_I ;
previous_cyc <= CYC_O ;
previous_stb <= STB_O ;
previous_ack <= ACK_I ;
previous_err <= ERR_I ;
previous_rty <= RTY_I ;
previous_cyc <= CYC_O ;
previous_tag <= TAG_O ;
previous_we <= WE_O ;
previous_data_o <= DAT_O ;
previous_data_i <= DAT_I ;
previous_address <= ADDR_O ;
previous_sel <= SEL_O ;
end
end
 
// cycle monitor
always@(posedge CLK_I)
begin
if (CYC_O && ~RST_I) // cycle in progress
begin:cycle_monitor_blk
reg master_can_change ;
reg slave_can_change ;
 
if ((CYC_O !== 1'b0) & (RST_I !== 1'b1)) // cycle in progress
begin
if (STB_O)
// check for two control signals active at same edge
if ( (ACK_I !== 1'b0) & (RTY_I !== 1'b0) )
begin
// check for two control signals active at same edge
if ( ACK_I && RTY_I )
begin
$display("ACK_I and RTY_I asserted at the same time during cycle") ;
$fdisplay(log_file_desc, "ACK_I and RTY_I asserted at the same time during cycle") ;
end
if ( ACK_I && ERR_I )
begin
$display("ACK_I and ERR_I asserted at the same time during cycle") ;
$fdisplay(log_file_desc, "ACK_I and ERR_I asserted at the same time during cycle") ;
end
if ( RTY_I && ERR_I )
begin
$display("RTY_I and ERR_I asserted at the same time during cycle") ;
$fdisplay(log_file_desc, "RTY_I and ERR_I asserted at the same time during cycle") ;
end
message_out("ACK_I and RTY_I asserted at the same time during cycle") ;
end
 
if ( can_change !== 1 )
begin
if ( ADDR_O !== previous_address )
begin
$display("WB bus monitor detected address change in the middle of the cycle!") ;
$fdisplay(log_file_desc, "WB bus monitor detected address change in the middle of the cycle!") ;
end
if ( (ACK_I !== 1'b0) & (ERR_I !== 1'b0) )
begin
message_out("ACK_I and ERR_I asserted at the same time during cycle") ;
end
 
if ( SEL_O !== previous_sel )
begin
$display("WB bus monitor detected select lines changed in the middle of the cycle!") ;
$fdisplay(log_file_desc, "WB bus monitor detected select lines changed in the middle of the cycle!") ;
end
if ( (RTY_I !== 1'b0) & (ERR_I !== 1'b0) )
begin
message_out("RTY_I and ERR_I asserted at the same time during cycle") ;
end
 
if ( (WE_O !== 0) && ( DAT_O !== previous_data ) )
begin
$display("WB bus monitor detected data lines changed in the middle of the cycle!") ;
$fdisplay(log_file_desc, "WB bus monitor detected data lines changed in the middle of the cycle!") ;
end
if (previous_cyc === 1'b1)
begin
if (previous_stb === 1'b1)
begin
if ((previous_ack === 1'b1) | (previous_rty === 1'b1) | (previous_err === 1'b1))
master_can_change = 1'b1 ;
else
master_can_change = 1'b0 ;
end
 
if ( ACK_I || RTY_I || ERR_I )
can_change = 1 ;
else
begin
previous_data = DAT_O ;
previous_address = ADDR_O ;
previous_sel = SEL_O ;
can_change = 0 ;
master_can_change = 1'b1 ;
end
 
end // STB_O
else
begin //~STB_O
// while STB_O is inactive, only ACK_I is allowed to be active
if ( ERR_I )
if ((previous_ack === 1'b1) | (previous_err === 1'b1) | (previous_rty === 1'b1))
begin
$display("ERR_I asserted during cycle without STB_O") ;
$fdisplay(log_file_desc, "ERR_I asserted during cycle without STB_O") ;
if (previous_stb === 1'b1)
slave_can_change = 1'b1 ;
else
slave_can_change = 1'b0 ;
end
if ( RTY_I )
else
begin
$display("RTY_I asserted during cycle without STB_O") ;
$fdisplay(log_file_desc, "RTY_I asserted during cycle without STB_O") ;
slave_can_change = 1'b1 ;
end
end
else
begin
master_can_change = 1'b1 ;
slave_can_change = 1'b1 ;
end
end
else
begin
master_can_change = 1'b1 ;
slave_can_change = 1'b1 ;
end
 
if ((previous_ack !== 1) && (previous_err !== 1) && (previous_rty !== 1) && (previous_stb !== 0))
if (master_can_change !== 1'b1)
begin
if (CYC_O !== previous_cyc)
begin
message_out("Master violated WISHBONE protocol by changing the value of CYC_O signal at inappropriate time!") ;
end
 
if (STB_O !== previous_stb)
begin
message_out("Master violated WISHBONE protocol by changing the value of STB_O signal at inappropriate time!") ;
end
 
if (TAG_O !== previous_tag)
begin
message_out("Master violated WISHBONE protocol by changing the value of TAG_O signals at inappropriate time!") ;
end
 
if (ADDR_O !== previous_address)
begin
message_out("Master violated WISHBONE protocol by changing the value of ADR_O signals at inappropriate time!") ;
end
 
if (SEL_O !== previous_sel)
begin
message_out("Master violated WISHBONE protocol by changing the value of SEL_O signals at inappropriate time!") ;
end
 
if (WE_O !== previous_we)
begin
message_out("Master violated WISHBONE protocol by changing the value of WE_O signal at inappropriate time!") ;
end
 
if (WE_O !== 1'b0)
begin
if (DAT_O !== previous_data_o)
begin
$display("STB_O de-asserted without reception of slave response") ;
$fdisplay(log_file_desc, "STB_O de-asserted without reception of slave response") ;
message_out("Master violated WISHBONE protocol by changing the value of DAT_O signals at inappropriate time!") ;
end
end
end
 
can_change = 1 ;
end // ~STB_O
end // cycle in progress
else if (!RST_I)
if (slave_can_change !== 1'b1)
begin
// cycle not in progress anymore
can_change = 1 ;
if ((previous_ack !== 1) && (previous_err !== 1) && (previous_rty !== 1) && (previous_stb !== 0))
if (previous_ack !== ACK_I)
begin
$display("STB_O de-asserted without reception of slave response") ;
$fdisplay(log_file_desc, "STB_O de-asserted without reception of slave response") ;
message_out("Slave violated WISHBONE protocol by changing the value of ACK_O signal at inappropriate time!") ;
end
 
if (previous_rty !== RTY_I)
begin
message_out("Slave violated WISHBONE protocol by changing the value of RTY_O signal at inappropriate time!") ;
end
 
if (previous_err !== ERR_I)
begin
message_out("Slave violated WISHBONE protocol by changing the value of ERR_O signal at inappropriate time!") ;
end
 
if (previous_data_i !== DAT_I)
begin
message_out("Slave violated WISHBONE protocol by changing the value of DAT_O signals at inappropriate time!") ;
end
end
end // cycle monitor
 
326,16 → 370,18
if (STB_O && ACK_I)
begin
if (address[`WB_ADDR_WIDTH] == 1'b0)
address <= {1'b1, (ADDR_O + `WB_SEL_WIDTH)} ;
begin
address <= (ADDR_O + `WB_SEL_WIDTH) | { 1'b1, {`WB_ADDR_WIDTH{1'b0}} } ;
end
else
begin
if ( address[(`WB_ADDR_WIDTH-1):0] != ADDR_O)
begin
$display("Consecutive address burst address incrementing incorrect") ;
$fdisplay(log_file_desc, "Consecutive address burst address incrementing incorrect") ;
$display("Expected ADR_O = 0x%h, Actual = 0x%h", address[(`WB_ADDR_WIDTH-1):0], ADDR_O) ;
message_out("Consecutive address burst address incrementing incorrect") ;
end
else
address <= {1'b1, (ADDR_O + `WB_SEL_WIDTH)} ;
address <= (ADDR_O + `WB_SEL_WIDTH) | { 1'b1, {`WB_ADDR_WIDTH{1'b0}} } ;
end
end
end
343,53 → 389,78
 
// data monitor
always@(posedge CLK_I or posedge RST_I)
begin
if (CYC_O && STB_O && ~RST_I)
begin:data_monitor_blk
reg last_valid_we ;
reg [`WB_SEL_WIDTH - 1:0] last_valid_sel ;
 
if ((CYC_O !== 1'b0) & (RST_I !== 1'b1))
begin
if ( ((^ADDR_O) !== 1'b1) && ((^ADDR_O) !== 1'b0) )
if (STB_O !== 1'b0)
begin
$display("Master provided invalid address and qualified it with STB_O") ;
$fdisplay(log_file_desc, "Master provided invalid address and qualified it with STB_O") ;
end
if ( WE_O )
begin
if (
(SEL_O[0] && (((^DAT_O[7:0]) !== 1'b0) && ((^DAT_O[7:0]) !== 1'b1))) ||
(SEL_O[1] && (((^DAT_O[15:8]) !== 1'b0) && ((^DAT_O[15:8]) !== 1'b1))) ||
(SEL_O[2] && (((^DAT_O[23:16]) !== 1'b0) && ((^DAT_O[23:16]) !== 1'b1))) ||
(SEL_O[3] && (((^DAT_O[31:24]) !== 1'b0) && ((^DAT_O[31:24]) !== 1'b1)))
)
last_valid_we = WE_O ;
last_valid_sel = SEL_O ;
 
if ( (ADDR_O ^ ADDR_O) !== 0 )
begin
$display("Master provided invalid data during write and qualified it with STB_O") ;
$fdisplay(log_file_desc, "Master provided invalid data during write and qualified it with STB_O") ;
$display("Byte select value: SEL_O = %b, Data bus value: DAT_O = %h ", SEL_O, DAT_O) ;
$fdisplay(log_file_desc, "Byte select value: SEL_O = %b, Data bus value: DAT_O = %h ", SEL_O, DAT_O) ;
message_out("Master provided invalid ADR_O and qualified it with STB_O") ;
end
if ( (SEL_O ^ SEL_O) !== 0 )
begin
message_out("Master provided invalid SEL_O and qualified it with STB_O") ;
end
 
if ( WE_O )
begin
if (
( SEL_O[0] & ((DAT_O[ 7:0 ] ^ DAT_O[ 7:0 ]) !== 0) ) |
( SEL_O[1] & ((DAT_O[15:8 ] ^ DAT_O[15:8 ]) !== 0) ) |
( SEL_O[2] & ((DAT_O[23:16] ^ DAT_O[23:16]) !== 0) ) |
( SEL_O[3] & ((DAT_O[31:24] ^ DAT_O[31:24]) !== 0) )
)
begin
message_out("Master provided invalid data during write and qualified it with STB_O") ;
$display("Byte select value: SEL_O = %b, Data bus value: DAT_O = %h ", SEL_O, DAT_O) ;
$fdisplay(log_file_desc, "Byte select value: SEL_O = %b, Data bus value: DAT_O = %h ", SEL_O, DAT_O) ;
end
end
 
if ((TAG_O ^ TAG_O) !== 0)
begin
message_out("Master provided invalid TAG_O and qualified it with STB_O!") ;
end
end
else
if (~WE_O && ACK_I)
 
if ((last_valid_we !== 1'b1) & (ACK_I !== 1'b0))
begin
if (
(SEL_O[0] && (((^DAT_I[7:0]) !== 1'b0) && ((^DAT_I[7:0]) !== 1'b1))) ||
(SEL_O[1] && (((^DAT_I[15:8]) !== 1'b0) && ((^DAT_I[15:8]) !== 1'b1))) ||
(SEL_O[2] && (((^DAT_I[23:16]) !== 1'b0) && ((^DAT_I[23:16]) !== 1'b1))) ||
(SEL_O[3] && (((^DAT_I[31:24]) !== 1'b0) && ((^DAT_I[31:24]) !== 1'b1)))
( SEL_O[0] & ((DAT_I[ 7:0 ] ^ DAT_I[ 7:0 ]) !== 0) ) |
( SEL_O[1] & ((DAT_I[15:8 ] ^ DAT_I[15:8 ]) !== 0) ) |
( SEL_O[2] & ((DAT_I[23:16] ^ DAT_I[23:16]) !== 0) ) |
( SEL_O[3] & ((DAT_I[31:24] ^ DAT_I[31:24]) !== 0) )
)
begin
$display("Slave provided invalid data during read and qualified it with ACK_I") ;
$fdisplay(log_file_desc, "Slave provided invalid data during read and qualified it with ACK_I") ;
$display("Byte select value: SEL_O = %b, Data bus value: DAT_I = %h ", SEL_O, DAT_I) ;
$fdisplay(log_file_desc, "Byte select value: SEL_O = %b, Data bus value: DAT_I = %h ", SEL_O, DAT_I) ;
message_out("Slave provided invalid data during read and qualified it with ACK_I") ;
$display("Byte select value: SEL_O = %b, Data bus value: DAT_I = %h ", last_valid_sel, DAT_I) ;
$fdisplay(log_file_desc, "Byte select value: SEL_O = %b, Data bus value: DAT_I = %h ", last_valid_sel, DAT_I) ;
end
end
end
else
begin
last_valid_sel = {`WB_SEL_WIDTH{1'bx}} ;
last_valid_we = 1'bx ;
end
end
 
initial
task message_out ;
input [7999:0] message_i ;
begin
previous_data = 0 ;
previous_address = 0 ;
can_change = 1 ;
$display("Time: %t", $time) ;
$display("%m, %0s", message_i) ;
$fdisplay(log_file_desc, "Time: %t", $time) ;
$fdisplay(log_file_desc, "%m, %0s", message_i) ;
end
endtask // display message
 
endmodule // BUS_MON
/trunk/bench/verilog/pci_bus_monitor.v
1,5 → 1,5
//===========================================================================
// $Id: pci_bus_monitor.v,v 1.3 2002-08-13 11:03:51 mihad Exp $
// $Id: pci_bus_monitor.v,v 1.4 2003-08-03 18:04:44 mihad Exp $
//
// Copyright 2001 Blue Beaver. All Rights Reserved.
//
639,6 → 639,8
`NO_ELSE;
end
 
wire [4:0] grant_now = {pci_ext_gnt_l[3:0], pci_real_gnt_l} ;
 
always @(posedge pci_ext_clk or negedge pci_ext_reset_l)
begin
if (pci_ext_reset_l == 1'b0)
656,7 → 658,7
end
else
begin
grant_prev <= {pci_ext_gnt_l[3:0], pci_real_gnt_l};
grant_prev <= grant_now ;
ad_prev[PCI_BUS_DATA_RANGE:0] <= pci_ext_ad[PCI_BUS_DATA_RANGE:0];
cbe_l_prev[PCI_BUS_CBE_RANGE:0] <= pci_ext_cbe_l[PCI_BUS_CBE_RANGE:0];
frame_prev <= frame_now;
1220,7 → 1222,6
begin
$display ("*** monitor - Unknown operation started, AD: 'h%x, CBE: 'h%x, at time %t",
ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
$fdisplay (log_file_desc,
error_detected <= ~error_detected;
end
endcase
1228,5 → 1229,206
`NO_ELSE;
end
`endif // VERBOSE_MONITOR_DEVICE
endmodule
 
initial get_pci_op.timeout_val = 32'hffff ;
 
reg [4:0] cur_transaction_owner ;
 
initial cur_transaction_owner = 5'h1F ;
 
task get_pci_op ;
output [31:0] address_o ;
output [3:0 ] bus_command_o ;
reg [31:0] timeout_val ;
reg in_use ;
begin:main
if (in_use === 1'b1)
begin
$display("%m re-entered!") ;
$fdisplay(log_file_desc, "%m re-entered!") ;
error_detected <= ~error_detected;
disable main ;
end
 
in_use = 1'b1 ;
 
fork
begin:get_op_blk
wait(pci_ext_reset_l === 1'b1) ;
@(posedge pci_ext_clk) ;
while ((frame_now !== 1'b1) | (frame_prev !== 1'b0) )
@(posedge pci_ext_clk) ;
 
disable timeout_blk ;
 
address_o = pci_ext_ad ;
bus_command_o = pci_ext_cbe_l ;
cur_transaction_owner = grant_now ;
 
end
begin:timeout_blk
#(timeout_val) ;
disable get_op_blk ;
address_o = 32'hxxxx_xxxx ;
bus_command_o = 4'hx ;
end
join
 
in_use = 1'b0 ;
 
end
endtask // get_pci_op
 
task get_pci_op_num_of_transfers ;
output [31:0] num_of_transfers_o ;
output gnt_deasserted_o ;
reg [7:0] num_of_cycles_without_transfer ;
reg in_use ;
begin:main
 
if (in_use === 1'b1)
begin
$display("%m re-entered!") ;
$fdisplay(log_file_desc, "%m re-entered!") ;
error_detected <= ~error_detected;
disable main ;
end
 
in_use = 1'b1 ;
 
num_of_transfers_o = 0 ;
num_of_cycles_without_transfer = 0 ;
 
@(posedge pci_ext_clk) ;
while( (frame_now === 1'b1) & (num_of_cycles_without_transfer < 128) )
begin
if ( (irdy_now === 1'b1) & (trdy_now === 1'b1) & (devsel_now === 1'b1))
begin
num_of_transfers_o = num_of_transfers_o + 1'b1 ;
num_of_cycles_without_transfer = 0 ;
end
else
begin
num_of_cycles_without_transfer = num_of_cycles_without_transfer + 1'b1 ;
end
 
@(posedge pci_ext_clk) ;
 
end
 
if (num_of_cycles_without_transfer === 128)
begin
$display("%m, no transfers in 128 pci clock cycles! Terminating!") ;
$fdisplay(log_file_desc, "%m, no transfers in 128 pci clock cycles! Terminating!") ;
error_detected <= ~error_detected ;
num_of_transfers_o = 32'hxxxx_xxxx ;
gnt_deasserted_o = 1'bx ;
end
else
begin
gnt_deasserted_o = ( cur_transaction_owner != grant_now ) ;
 
while ( (irdy_now === 1'b1) & (trdy_now === 1'b0) & (stop_now === 1'b0) )
@(posedge pci_ext_clk) ;
 
if ( (irdy_now === 1'b1) & (trdy_now === 1'b1) & (devsel_now === 1'b1))
num_of_transfers_o = num_of_transfers_o + 1'b1 ;
end
 
in_use = 1'b0 ;
end
endtask // get_pci_op_num_of_transfers
 
task get_pci_op_num_of_cycles ;
output [31:0] frame_asserted_cycles_o ;
reg [31:0] num_of_cycles_after_last_data_phase_termination ;
reg in_use ;
begin:main
if (in_use === 1'b1)
begin
$display("%m re-entered!") ;
$fdisplay(log_file_desc, "%m re-entered!") ;
error_detected <= ~error_detected;
disable main ;
end
 
in_use = 1'b1 ;
 
frame_asserted_cycles_o = 1 ;
num_of_cycles_after_last_data_phase_termination = 1 ;
 
@(posedge pci_ext_clk) ;
while( (frame_now === 1'b1) & (num_of_cycles_after_last_data_phase_termination < 128) )
begin
 
if (irdy_prev & trdy_prev & devsel_prev )
begin
 
frame_asserted_cycles_o = frame_asserted_cycles_o + num_of_cycles_after_last_data_phase_termination ;
 
num_of_cycles_after_last_data_phase_termination = 1 ;
end
else
num_of_cycles_after_last_data_phase_termination = num_of_cycles_after_last_data_phase_termination + 1'b1 ;
 
@(posedge pci_ext_clk) ;
 
end
 
if ( num_of_cycles_after_last_data_phase_termination === 128)
begin
$display("%m, no transfers in 128 pci clock cycles! Terminating!") ;
$fdisplay(log_file_desc, "%m, no transfers in 128 pci clock cycles! Terminating!") ;
error_detected <= ~error_detected ;
frame_asserted_cycles_o = 32'hxxxx_xxxx ;
end
 
in_use = 1'b0 ;
end
endtask // get_pci_op_num_of_cycles
 
task get_pci_master_abort ;
output [31:0 ] ret_adr_o ;
output [ 3:0 ] ret_bc_o ;
output ret_mabort_detected_o ;
begin:main
ret_mabort_detected_o = 1'b0 ;
get_pci_op(ret_adr_o, ret_bc_o) ;
 
if ( (ret_adr_o ^ ret_adr_o) !== 0 )
disable main ;
 
if ( (ret_bc_o ^ ret_bc_o) !== 0 )
disable main ;
 
while (frame_now !== 1'b0)
begin
if (devsel_now !== 1'b0)
begin
// exit immediately on target response detection
ret_mabort_detected_o = 1'b0 ;
disable main ;
end
 
@(posedge pci_ext_clk) ;
end
 
while(irdy_now !== 1'b0)
begin
 
if (devsel_now !== 1'b0)
begin
// exit immediately on target response detection
ret_mabort_detected_o = 1'b0 ;
disable main ;
end
 
@(posedge pci_ext_clk) ;
end
 
ret_mabort_detected_o = 1'b1 ;
end
endtask // get_pci_master_abort
endmodule
/trunk/bench/verilog/pci_blue_options.vh
1,5 → 1,5
//===========================================================================
// $Id: pci_blue_options.vh,v 1.2 2002-08-13 11:03:51 mihad Exp $
// $Id: pci_blue_options.vh,v 1.3 2003-08-03 18:04:44 mihad Exp $
//
// Copyright 2001 Blue Beaver. All Rights Reserved.
//
269,9 → 269,9
// Match plus Fill plus Qual must together be 32 bits
`define PCI_BASE_ADDR1_FILL (16'h0000)
// Address Map Qualifier, described in the PCI specification,
// Revision 2.2, section 6.2.5.1. The value 0x8 indicates
// that the Base Address size is 32 bits, that it is a Memory
// mapped Base Address Register, and that data is pre-fetchable
// Revision 2.2, section 6.2.5.1. The value 0x1 indicates
// that the Base Address size is 32 bits, that it is a IO
// mapped Base Address Register
`define PCI_BASE_ADDR1_MAP_QUAL (4'h1)
`endif // PCI_BASE_ADDR1_MATCH_ENABLE
 
/trunk/bench/verilog/pci_testbench_defines.v
79,7 → 79,7
`define Thold 1
 
// how many clock cycles should model wait for design's response - integer 32 bit value
`define WAIT_FOR_RESPONSE 6
`define WAIT_FOR_RESPONSE 10
 
// maximum number of transactions allowed in single call to block or cab transfer routines
`define MAX_BLK_SIZE 4096
92,7 → 92,7
`define WB_ADDR_WIDTH 32
`define WB_DATA_WIDTH 32
`define WB_SEL_WIDTH `WB_DATA_WIDTH/8
`define WB_TAG_WIDTH 4
`define WB_TAG_WIDTH 5
`define WB_ADDR_TYPE [(`WB_ADDR_WIDTH - 1):0]
`define WB_DATA_TYPE [(`WB_DATA_WIDTH - 1):0]
`define WB_SEL_TYPE [(`WB_SEL_WIDTH - 1):0]
/trunk/rtl/verilog/pci_bridge32.v
43,6 → 43,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.9 2003/01/27 16:49:31 mihad
// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
//
// Revision 1.8 2002/10/21 13:04:33 mihad
// Changed BIST signal names etc..
//
96,7 → 99,18
wbs_cyc_i,
wbs_stb_i,
wbs_we_i,
 
`ifdef PCI_WB_REV_B3
 
wbs_cti_i,
wbs_bte_i,
 
`else
 
wbs_cab_i,
 
`endif
 
wbs_ack_o,
wbs_rty_o,
wbs_err_o,
201,7 → 215,18
input wbs_cyc_i ;
input wbs_stb_i ;
input wbs_we_i ;
input wbs_cab_i ;
 
`ifdef PCI_WB_REV_B3
 
input [2:0] wbs_cti_i ;
input [1:0] wbs_bte_i ;
 
`else
 
input wbs_cab_i ;
 
`endif
 
output wbs_ack_o ;
output wbs_rty_o ;
output wbs_err_o ;
355,12 → 380,6
wire wbu_ad_load_on_transfer_out ;
wire wbu_pciif_frame_load_out ;
 
// assign wishbone slave unit's outputs to top outputs where possible
assign wbs_dat_o = wbu_sdata_out ;
assign wbs_ack_o = wbu_ack_out ;
assign wbs_rty_o = wbu_rty_out ;
assign wbs_err_o = wbu_err_out ;
 
// PCI TARGET UNIT OUTPUTS
wire [31:0] pciu_adr_out ;
wire [31:0] pciu_mdata_out ;
625,7 → 644,82
.conf_isr_int_prop_out (pci_into_conf_isr_int_prop_out)
);
 
 
`ifdef PCI_WB_REV_B3
 
wire wbs_wbb3_2_wbb2_cyc_o ;
wire wbs_wbb3_2_wbb2_stb_o ;
wire [31:0] wbs_wbb3_2_wbb2_adr_o ;
wire [31:0] wbs_wbb3_2_wbb2_dat_i_o ;
wire [31:0] wbs_wbb3_2_wbb2_dat_o_o ;
wire wbs_wbb3_2_wbb2_we_o ;
wire [ 3:0] wbs_wbb3_2_wbb2_sel_o ;
wire wbs_wbb3_2_wbb2_ack_o ;
wire wbs_wbb3_2_wbb2_err_o ;
wire wbs_wbb3_2_wbb2_rty_o ;
wire wbs_wbb3_2_wbb2_cab_o ;
 
// assign wishbone slave unit's outputs to top outputs where possible
assign wbs_dat_o = wbs_wbb3_2_wbb2_dat_o_o ;
assign wbs_ack_o = wbs_wbb3_2_wbb2_ack_o ;
assign wbs_rty_o = wbs_wbb3_2_wbb2_rty_o ;
assign wbs_err_o = wbs_wbb3_2_wbb2_err_o ;
 
wire wbs_wbb3_2_wbb2_cyc_i = wbs_cyc_i ;
wire wbs_wbb3_2_wbb2_stb_i = wbs_stb_i ;
wire wbs_wbb3_2_wbb2_we_i = wbs_we_i ;
wire wbs_wbb3_2_wbb2_ack_i = wbu_ack_out ;
wire wbs_wbb3_2_wbb2_err_i = wbu_err_out ;
wire wbs_wbb3_2_wbb2_rty_i = wbu_rty_out ;
wire [31:0] wbs_wbb3_2_wbb2_adr_i = wbs_adr_i ;
wire [ 3:0] wbs_wbb3_2_wbb2_sel_i = wbs_sel_i ;
wire [31:0] wbs_wbb3_2_wbb2_dat_i_i = wbs_dat_i ;
wire [31:0] wbs_wbb3_2_wbb2_dat_o_i = wbu_sdata_out ;
wire [ 2:0] wbs_wbb3_2_wbb2_cti_i = wbs_cti_i ;
wire [ 1:0] wbs_wbb3_2_wbb2_bte_i = wbs_bte_i ;
 
pci_wbs_wbb3_2_wbb2 i_pci_wbs_wbb3_2_wbb2
(
.wb_clk_i ( wb_clk_i ) ,
.wb_rst_i ( wb_rst_i ) ,
 
.wbs_cyc_i ( wbs_wbb3_2_wbb2_cyc_i ) ,
.wbs_cyc_o ( wbs_wbb3_2_wbb2_cyc_o ) ,
.wbs_stb_i ( wbs_wbb3_2_wbb2_stb_i ) ,
.wbs_stb_o ( wbs_wbb3_2_wbb2_stb_o ) ,
.wbs_adr_i ( wbs_wbb3_2_wbb2_adr_i ) ,
.wbs_adr_o ( wbs_wbb3_2_wbb2_adr_o ) ,
.wbs_dat_i_i ( wbs_wbb3_2_wbb2_dat_i_i ) ,
.wbs_dat_i_o ( wbs_wbb3_2_wbb2_dat_i_o ) ,
.wbs_dat_o_i ( wbs_wbb3_2_wbb2_dat_o_i ) ,
.wbs_dat_o_o ( wbs_wbb3_2_wbb2_dat_o_o ) ,
.wbs_we_i ( wbs_wbb3_2_wbb2_we_i ) ,
.wbs_we_o ( wbs_wbb3_2_wbb2_we_o ) ,
.wbs_sel_i ( wbs_wbb3_2_wbb2_sel_i ) ,
.wbs_sel_o ( wbs_wbb3_2_wbb2_sel_o ) ,
.wbs_ack_i ( wbs_wbb3_2_wbb2_ack_i ) ,
.wbs_ack_o ( wbs_wbb3_2_wbb2_ack_o ) ,
.wbs_err_i ( wbs_wbb3_2_wbb2_err_i ) ,
.wbs_err_o ( wbs_wbb3_2_wbb2_err_o ) ,
.wbs_rty_i ( wbs_wbb3_2_wbb2_rty_i ) ,
.wbs_rty_o ( wbs_wbb3_2_wbb2_rty_o ) ,
.wbs_cti_i ( wbs_wbb3_2_wbb2_cti_i ) ,
.wbs_bte_i ( wbs_wbb3_2_wbb2_bte_i ) ,
.wbs_cab_o ( wbs_wbb3_2_wbb2_cab_o )
) ;
 
// WISHBONE SLAVE UNIT INPUTS
wire [31:0] wbu_addr_in = wbs_wbb3_2_wbb2_adr_o ;
wire [31:0] wbu_sdata_in = wbs_wbb3_2_wbb2_dat_i_o ;
wire wbu_cyc_in = wbs_wbb3_2_wbb2_cyc_o ;
wire wbu_stb_in = wbs_wbb3_2_wbb2_stb_o ;
wire wbu_we_in = wbs_wbb3_2_wbb2_we_o ;
wire [3:0] wbu_sel_in = wbs_wbb3_2_wbb2_sel_o ;
wire wbu_cab_in = wbs_wbb3_2_wbb2_cab_o ;
 
`else
 
// WISHBONE SLAVE UNIT INPUTS
wire [31:0] wbu_addr_in = wbs_adr_i ;
wire [31:0] wbu_sdata_in = wbs_dat_i ;
wire wbu_cyc_in = wbs_cyc_i ;
634,6 → 728,14
wire [3:0] wbu_sel_in = wbs_sel_i ;
wire wbu_cab_in = wbs_cab_i ;
 
// assign wishbone slave unit's outputs to top outputs where possible
assign wbs_dat_o = wbu_sdata_out ;
assign wbs_ack_o = wbu_ack_out ;
assign wbs_rty_o = wbu_rty_out ;
assign wbs_err_o = wbu_err_out ;
 
`endif
 
wire [5:0] wbu_map_in = {
conf_wb_mem_io5_out,
conf_wb_mem_io4_out,
/trunk/rtl/verilog/top.v
42,6 → 42,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.9 2003/01/27 16:49:31 mihad
// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
//
// Revision 1.8 2002/10/18 03:36:37 tadejm
// Changed wrong signal name scanb_sen into scanb_en.
//
110,6 → 113,8
STB_I,
WE_I,
CAB_I,
CTI_I,
BTE_I,
ACK_O,
RTY_O,
ERR_O,
171,6 → 176,8
input STB_I ;
input WE_I ;
input CAB_I ;
input [ 2:0] CTI_I ;
input [ 1:0] BTE_I ;
output ACK_O ;
output RTY_O ;
output ERR_O ;
270,7 → 277,18
.wbs_cyc_i(CYC_I),
.wbs_stb_i(STB_I),
.wbs_we_i (WE_I),
 
`ifdef PCI_WB_REV_B3
 
.wbs_cti_i(CTI_I),
.wbs_bte_i(BTE_I),
 
`else
 
.wbs_cab_i(CAB_I),
 
`endif
 
.wbs_ack_o(ACK_O),
.wbs_rty_o(RTY_O),
.wbs_err_o(ERR_O),
/trunk/rtl/verilog/pci_user_constants.v
39,6 → 39,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.8 2003/03/14 15:31:57 mihad
// Entered the option to disable no response counter in wb master.
//
// Revision 1.7 2003/01/27 17:05:50 mihad
// Updated.
//
233,3 → 236,8
// define the macro below to disable internal retry generation in the wishbone master interface
// used when wb master accesses extremly slow devices.
`define PCI_WBM_NO_RESPONSE_CNT_DISABLE
 
//`define PCI_WB_REV_B3
//`define PCI_WBS_B3_RTY_DISABLE
 
//`define PCI_WBS_ALLOW_NON_ALLIGNED_CONFIG_ACCESS
/trunk/rtl/verilog/pci_wb_slave.v
42,6 → 42,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2003/01/27 16:49:31 mihad
// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
//
// Revision 1.4 2002/08/19 16:54:25 mihad
// Got rid of undef directives
//
445,8 → 448,8
reg current_delayed_is_ccyc ;
reg current_delayed_is_iack ;
 
wire wccyc_hit = (wb_addr_in[8:2] == {1'b1, `CNF_DATA_ADDR}) && alligned_address ;
wire wiack_hit = (wb_addr_in[8:2] == {1'b1, `INT_ACK_ADDR}) && alligned_address ;
wire wccyc_hit = (wb_addr_in[8:2] == {1'b1, `CNF_DATA_ADDR}) `ifdef PCI_WBS_ALLOW_NON_ALLIGNED_CONFIG_ACCESS `else && alligned_address `endif ;
wire wiack_hit = (wb_addr_in[8:2] == {1'b1, `INT_ACK_ADDR}) `ifdef PCI_WBS_ALLOW_NON_ALLIGNED_CONFIG_ACCESS `else && alligned_address `endif ;
reg iack_hit ;
reg ccyc_hit ;
always@(posedge reset_in or posedge wb_clock_in)
865,14 → 868,14
S_CONF_WRITE: begin
`ifdef HOST
wbw_data_out_sel = SEL_CCYC_ADDR ;
del_req = do_ccyc_req && ~burst_transfer && alligned_address ;
del_done = do_ccyc_comp && ~burst_transfer && alligned_address ;
del_in_progress = do_ccyc_comp && ~burst_transfer && alligned_address ;
del_req = do_ccyc_req && ~burst_transfer `ifdef PCI_WBS_ALLOW_NON_ALLIGNED_CONFIG_ACCESS `else && alligned_address `endif ;
del_done = do_ccyc_comp && ~burst_transfer `ifdef PCI_WBS_ALLOW_NON_ALLIGNED_CONFIG_ACCESS `else && alligned_address `endif ;
del_in_progress = do_ccyc_comp && ~burst_transfer `ifdef PCI_WBS_ALLOW_NON_ALLIGNED_CONFIG_ACCESS `else && alligned_address `endif ;
`endif
 
n_state = S_IDLE ; // next state after configuration access is always idle
 
if ( burst_transfer || ~alligned_address )
if ( burst_transfer `ifdef PCI_WBS_ALLOW_NON_ALLIGNED_CONFIG_ACCESS `else | ~alligned_address `endif )
begin
err = 1'b1 ;
end
904,15 → 907,15
S_CONF_READ: begin
`ifdef HOST
wbw_data_out_sel = SEL_CCYC_ADDR ;
del_req = ~burst_transfer && alligned_address && ( do_ccyc_req || do_iack_req );
del_done = ~burst_transfer && alligned_address && ( do_ccyc_comp || do_iack_comp ) ;
del_in_progress = ~burst_transfer && alligned_address && ( do_ccyc_comp || do_iack_comp ) ;
wbr_fifo_renable = ~burst_transfer && alligned_address && ( do_ccyc_comp || do_iack_comp ) ;
del_req = ~burst_transfer `ifdef PCI_WBS_ALLOW_NON_ALLIGNED_CONFIG_ACCESS `else && alligned_address `endif && ( do_ccyc_req || do_iack_req ) ;
del_done = ~burst_transfer `ifdef PCI_WBS_ALLOW_NON_ALLIGNED_CONFIG_ACCESS `else && alligned_address `endif && ( do_ccyc_comp || do_iack_comp ) ;
del_in_progress = ~burst_transfer `ifdef PCI_WBS_ALLOW_NON_ALLIGNED_CONFIG_ACCESS `else && alligned_address `endif && ( do_ccyc_comp || do_iack_comp ) ;
wbr_fifo_renable = ~burst_transfer `ifdef PCI_WBS_ALLOW_NON_ALLIGNED_CONFIG_ACCESS `else && alligned_address `endif && ( do_ccyc_comp || do_iack_comp ) ;
`endif
 
n_state = S_IDLE ; // next state after configuration access is always idle
 
if ( burst_transfer || ~alligned_address )
if ( burst_transfer `ifdef PCI_WBS_ALLOW_NON_ALLIGNED_CONFIG_ACCESS `else | ~alligned_address `endif )
begin
err = 1'b1 ;
end
/trunk/sim/rtl_sim/run/ncvlog.args
5,6 → 5,19
-messages
-INCDIR ../../../bench/verilog
-INCDIR ../../../rtl/verilog
-DEFINE REGRESSION
-DEFINE REGR_FIFO_SMALL_GENERIC
-DEFINE GUEST
-DEFINE WB_DECODE_FAST
-DEFINE PCI_DECODE_MAX
-DEFINE WB_DECODE_MED
-DEFINE PCI66
-DEFINE WB_CLK66
-DEFINE ACTIVE_HIGH_OE
-DEFINE WB_CNF_BASE_ZERO
-DEFINE NO_CNF_IMAGE
-DEFINE PCI_CLOCK_FOLLOWS_WB_CLOCK=2
-DEFINE DISABLE_COMPLETION_EXPIRED_TESTS
../../../rtl/verilog/pci_parity_check.v
../../../rtl/verilog/pci_target_unit.v
../../../rtl/verilog/pci_wb_addr_mux.v
58,7 → 71,7
../../../rtl/verilog/pci_rst_int.v
../../../rtl/verilog/pci_sync_module.v
../../../rtl/verilog/pci_wb_tpram.v
../../../rtl/verilog/meta_flop.v
../../../rtl/verilog/pci_wbs_wbb3_2_wbb2.v
../../../bench/verilog/wb_master32.v
../../../bench/verilog/wb_master_behavioral.v
../../../bench/verilog/system.v
/trunk/sim/rtl_sim/run/run_pci_sim_regr.scr
22,58 → 22,64
set arg_waves = 0;
set arg_vs_hdtp = 0
set arg_dis_comp_exp_test = 0
set arg_wb_b3 = 0
set arg_wbs_non_alligned = 0
 
@ arg_num = 1
set arg_check = 0
 
while($arg_num <= $#argv)
if ($argv[$arg_num] == "help") then
goto help
endif
while($arg_num <= $#)
 
if ($argv[$arg_num] == "regression") then
@ arg_regression = 1
@ arg_check = $arg_check + 1
endif
switch ( $argv[$arg_num] )
case "help":
goto help
breaksw
 
if ($argv[$arg_num] == "xilinx") then
@ arg_xilinx = 1
@ arg_check = $arg_check + 1
endif
case "regression":
@ arg_regression = 1
breaksw
 
if($argv[$arg_num] == "artisan") then
@ arg_artisan = 1
@ arg_check = $arg_check + 1
endif
case "xilinx":
@ arg_xilinx = 1
breaksw
 
if ($argv[$arg_num] == "waves") then
@ arg_waves = 1
@ arg_check = $arg_check + 1
endif
case "artisan":
@ arg_artisan = 1
breaksw
 
if ($argv[$arg_num] == "vs_two_port") then
@ arg_vs_hdtp = 1
@ arg_check = $arg_check + 1
endif
case "waves":
@ arg_waves = 1
breaksw
 
if ($argv[$arg_num] == "disable_completion_expired_tests") then
@ arg_dis_comp_exp_test = 1
@ arg_check = $arg_check + 1
endif
case "vs_two_port":
@ arg_vs_hdtp = 1
breaksw
 
if ($argv[$arg_num] == "iter") then
@ arg_num = $arg_num + 1
@ arg_check = $arg_check + 2
@ iter = $argv[$arg_num]
@ all_iterations = $iter
endif
case "disable_completion_expired_tests":
@ arg_dis_comp_exp_test = 1
breaksw
 
if ($arg_check != $arg_num) then
echo "Invalid argument found: $argv[$arg_num]"
echo
goto help
endif
@ arg_num = $arg_num + 1
case "wb_b3":
@ arg_wb_b3 = 1
breaksw
 
case "wb_na":
@ arg_wbs_non_alligned = 1
breaksw
 
case "iter":
@ arg_num = $arg_num + 1
@ iter = $argv[$arg_num]
@ all_iterations = $iter
breaksw
 
default:
echo "Invalid argument!"
goto help
breaksw
endsw
 
@ arg_num++
end
 
# ITERATION LOOP
519,6 → 525,15
if ($arg_dis_comp_exp_test) then
echo "-DEFINE DISABLE_COMPLETION_EXPIRED_TESTS" >> ./defines.args
endif
 
if ($arg_wb_b3) then
echo "-DEFINE PCI_WB_REV_B3" >> ./defines.args
endif
 
if ($arg_wbs_non_alligned) then
echo "-DEFINE PCI_WBS_ALLOW_NON_ALLIGNED_CONFIG_ACCESS" >> ./defines.args
endif
 
endif
endif
 
594,7 → 609,7
endif
echo "worklib.bridge32:fun" >> ./ncsim.args
 
ncsim -file ./ncsim.args #> /dev/null
ncsim -file ./ncsim.args > /dev/null
 
if ($status != 0) then
echo ""
/trunk/sim/rtl_sim/bin/rtl_file_list.lst
51,4 → 51,4
../../../rtl/verilog/pci_rst_int.v
../../../rtl/verilog/pci_sync_module.v
../../../rtl/verilog/pci_wb_tpram.v
../../../rtl/verilog/meta_flop.v
../../../rtl/verilog/pci_wbs_wbb3_2_wbb2.v

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