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Rev 1052 → Rev 1053
/trunk/or1200/rtl/verilog/or1200_immu_top.v
9,7 → 9,7
//// Instantiation of all IMMU blocks. //// |
//// //// |
//// To Do: //// |
//// - make it smaller and faster //// |
//// - cache inhibit //// |
//// //// |
//// Author(s): //// |
//// - Damjan Lampret, lampret@opencores.org //// |
44,6 → 44,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.9 2002/08/18 19:54:17 lampret |
// Added store buffer. |
// |
// Revision 1.8 2002/08/14 06:23:50 lampret |
// Disabled ITLB translation when 1) doing access to ITLB SPRs or 2) crossing page. This modification was tested only with parts of IMMU test - remaining test cases needs to be run. |
// |
295,7 → 298,12
// |
// Cache Inhibit |
// |
assign icimmu_ci_o = immu_en ? itlb_done & itlb_ci : `OR1200_IMMU_CI; |
// Cache inhibit is not really needed for instruction memory subsystem. |
// If we would do it, we would do it like this. |
// assign icimmu_ci_o = immu_en ? itlb_done & itlb_ci : `OR1200_IMMU_CI; |
// However this causes a async combinational loop so we stick to |
// no cache inhibit. |
assign icimmu_ci_o = `OR1200_IMMU_CI; |
|
// |
// Page cross |