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https://opencores.org/ocsvn/or1k/or1k/trunk
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- This comparison shows the changes necessary to convert path
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- from Rev 1053 to Rev 1054
- ↔ Reverse comparison
Rev 1053 → Rev 1054
/trunk/or1200/rtl/verilog/or1200_wb_biu.v
9,7 → 9,12
//// Implements WISHBONE interface //// |
//// //// |
//// To Do: //// |
//// - add support for wb_err_i //// |
//// - if biu_cyc/stb are deasserted and wb_ack_i is asserted //// |
//// and this happens even before aborted_r is asssrted, //// |
//// wb_ack_i will be delivered even though transfer is //// |
//// internally considered already aborted. However most //// |
//// wb_ack_i are externally registered and delayed. Normally //// |
//// this shouldn't cause any problems. //// |
//// //// |
//// Author(s): //// |
//// - Damjan Lampret, lampret@opencores.org //// |
44,6 → 49,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.3 2002/08/12 05:31:37 lampret |
// Added optional retry counter for wb_rty_i. Added graceful termination for aborted transfers. |
// |
// Revision 1.2 2002/07/14 22:17:17 lampret |
// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized. |
// |
246,7 → 254,7
else |
long_ack_o <= #1 wb_ack_i & ~aborted; |
`else |
assign long_ack_o = wb_ack_i & ~aborted; |
assign long_ack_o = wb_ack_i & ~aborted_r; |
`endif |
|
// |
275,7 → 283,7
else |
long_err_o <= #1 wb_err_i & ~aborted; |
`else |
assign long_err_o = wb_err_i & ~aborted; |
assign long_err_o = wb_err_i & ~aborted_r; |
`endif |
|
// |
307,11 → 315,10
// wb_stb_o would be deasserted (biu_cyc_i and biu_stb_i are low) 3) and |
// there is no termination of current transfer in this WB clock cycle (wb_ack_i |
// and wb_err_i are low). |
// Extend 'aborted' signal with 'aborted_r' until this "aborted" transfer |
// 'aborted_r' is registered 'aborted' and extended until this "aborted" transfer |
// is properly terminated with wb_ack_i/wb_err_i. |
// |
// |
assign aborted = wb_stb_o & ~(biu_cyc_i & biu_stb_i) & ~(wb_ack_i | wb_err_i) | aborted_r; |
assign aborted = wb_stb_o & ~(biu_cyc_i & biu_stb_i) & ~(wb_ack_i | wb_err_i); |
always @(posedge wb_clk_i or posedge wb_rst_i) |
if (wb_rst_i) |
aborted_r <= #1 1'b0; |