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URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

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  • This comparison shows the changes necessary to convert path 
    /
    from Rev 106 to Rev 107
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  •

Rev 106 → Rev 107

/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/driver_7segment.v
52,7 → 52,7
per_addr, // Peripheral address
per_din, // Peripheral data input
per_en, // Peripheral enable (high active)
per_wen, // Peripheral write enable (high active)
per_we, // Peripheral write enable (high active)
puc // Main system reset
);
 
69,7 → 69,7
input [7:0] per_addr; // Peripheral address
input [15:0] per_din; // Peripheral data input
input per_en; // Peripheral enable (high active)
input [1:0] per_wen; // Peripheral write enable (high active)
input [1:0] per_we; // Peripheral write enable (high active)
input puc; // Main system reset
 
 
107,9 → 107,9
endcase
 
// Read/Write probes
wire reg_lo_write = per_wen[0] & per_en;
wire reg_hi_write = per_wen[1] & per_en;
wire reg_read = ~|per_wen & per_en;
wire reg_lo_write = per_we[0] & per_en;
wire reg_hi_write = per_we[1] & per_en;
wire reg_read = ~|per_we & per_en;
 
// Read/Write vectors
wire [255:0] reg_hi_wr = reg_dec & {256{reg_hi_write}};
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_frontend.v
68,6 → 68,7
pc_nxt, // Next PC value (for CALL & IRQ)
 
// INPUTs
cpu_en_s, // Enable CPU code execution (synchronous)
cpuoff, // Turns off the CPU
dbg_halt_cmd, // Halt CPU command
dbg_reg_sel, // Debug selected register for rd/wr access
111,6 → 112,7
 
// INPUTs
//=========
input cpu_en_s; // Enable CPU code execution (synchronous)
input cpuoff; // Turns off the CPU
input dbg_halt_cmd; // Halt CPU command
input [3:0] dbg_reg_sel; // Debug selected register for rd/wr access
173,17 → 175,20
parameter I_EXT2 = 3'h4; // 2nd Extension word
parameter I_IDLE = 3'h5; // CPU is in IDLE mode
 
// CPU on/off through the debug interface or cpu_en port
wire cpu_halt_cmd = dbg_halt_cmd | ~cpu_en_s;
// States Transitions
always @(i_state or inst_sz or inst_sz_nxt or pc_sw_wr or exec_done or
exec_done or irq_detect or cpuoff or dbg_halt_cmd or e_state)
exec_done or irq_detect or cpuoff or cpu_halt_cmd or e_state)
case(i_state)
I_IDLE : i_state_nxt = (irq_detect & ~dbg_halt_cmd) ? I_IRQ_FETCH :
(~cpuoff & ~dbg_halt_cmd) ? I_DEC : I_IDLE;
I_IDLE : i_state_nxt = (irq_detect & ~cpu_halt_cmd) ? I_IRQ_FETCH :
(~cpuoff & ~cpu_halt_cmd) ? I_DEC : I_IDLE;
I_IRQ_FETCH: i_state_nxt = I_IRQ_DONE;
I_IRQ_DONE : i_state_nxt = I_DEC;
I_DEC : i_state_nxt = irq_detect ? I_IRQ_FETCH :
(cpuoff | dbg_halt_cmd) & exec_done ? I_IDLE :
dbg_halt_cmd & (e_state==`E_IDLE) ? I_IDLE :
(cpuoff | cpu_halt_cmd) & exec_done ? I_IDLE :
cpu_halt_cmd & (e_state==`E_IDLE) ? I_IDLE :
pc_sw_wr ? I_DEC :
~exec_done & ~(e_state==`E_IDLE) ? I_DEC : // Wait in decode state
(inst_sz_nxt!=2'b00) ? I_EXT1 : I_DEC; // until execution is completed
208,7 → 213,7
reg dbg_halt_st;
always @(posedge mclk or posedge puc)
if (puc) dbg_halt_st <= 1'b0;
else dbg_halt_st <= dbg_halt_cmd & (i_state_nxt==I_IDLE);
else dbg_halt_st <= cpu_halt_cmd & (i_state_nxt==I_IDLE);
 
 
//=============================================================================
230,7 → 235,7
else if (exec_done) inst_irq_rst <= 1'b0;
 
// Detect other interrupts
assign irq_detect = (inst_nmi | ((|irq | wdt_irq) & gie)) & ~dbg_halt_cmd & ~dbg_halt_st & (exec_done | (i_state==I_IDLE));
assign irq_detect = (inst_nmi | ((|irq | wdt_irq) & gie)) & ~cpu_halt_cmd & ~dbg_halt_st & (exec_done | (i_state==I_IDLE));
 
// Select interrupt vector
reg [3:0] irq_num;
289,7 → 294,7
// Memory interface
wire [15:0] mab = pc_nxt;
wire mb_en = fetch | pc_sw_wr | (i_state==I_IRQ_FETCH) | pmem_busy | (dbg_halt_st & ~dbg_halt_cmd);
wire mb_en = fetch | pc_sw_wr | (i_state==I_IRQ_FETCH) | pmem_busy | (dbg_halt_st & ~cpu_halt_cmd);
 
 
//
566,12 → 571,12
endcase
else if (dest_reg==4'h0) // Addressing mode using R0
case (ir[7])
2'b1 : inst_ad_nxt = 8'b00010000;
1'b1 : inst_ad_nxt = 8'b00010000;
default: inst_ad_nxt = 8'b00000001;
endcase
else // General Addressing mode
case (ir[7])
2'b1 : inst_ad_nxt = 8'b00000010;
1'b1 : inst_ad_nxt = 8'b00000010;
default: inst_ad_nxt = 8'b00000001;
endcase
end
590,7 → 595,7
reg inst_bw;
always @(posedge mclk or posedge puc)
if (puc) inst_bw <= 1'b0;
else if (decode) inst_bw <= ir[6] & ~inst_type_nxt[`INST_JMP] & ~irq_detect & ~dbg_halt_cmd;
else if (decode) inst_bw <= ir[6] & ~inst_type_nxt[`INST_JMP] & ~irq_detect & ~cpu_halt_cmd;
 
// Extended instruction size
assign inst_sz_nxt = {1'b0, (inst_as_nxt[`IDX] | inst_as_nxt[`SYMB] | inst_as_nxt[`ABS] | inst_as_nxt[`IMM])} +
645,9 → 650,8
else if (inst_dext_rdy) exec_dext_rdy <= 1'b1;
 
// Execution first state
//wire [3:0] e_first_state = dbg_halt_cmd ? `E_IDLE :
wire [3:0] e_first_state = ~dbg_halt_st & inst_so_nxt[`IRQ] ? `E_IRQ_0 :
dbg_halt_cmd | (i_state==I_IDLE) ? `E_IDLE :
cpu_halt_cmd | (i_state==I_IDLE) ? `E_IDLE :
cpuoff ? `E_IDLE :
src_acalc_pre ? `E_SRC_AD :
src_rd_pre ? `E_SRC_RD :
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/periph/template_periph_8b.v
40,10 → 40,6
// $LastChangedBy$
// $LastChangedDate$
//----------------------------------------------------------------------------
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_defines.v"
`endif
 
module template_periph_8b (
 
55,7 → 51,7
per_addr, // Peripheral address
per_din, // Peripheral data input
per_en, // Peripheral enable (high active)
per_wen, // Peripheral write enable (high active)
per_we, // Peripheral write enable (high active)
puc // Main system reset
);
 
69,7 → 65,7
input [7:0] per_addr; // Peripheral address
input [15:0] per_din; // Peripheral data input
input per_en; // Peripheral enable (high active)
input [1:0] per_wen; // Peripheral write enable (high active)
input [1:0] per_we; // Peripheral write enable (high active)
input puc; // Main system reset
 
 
107,9 → 103,9
endcase
 
// Read/Write probes
wire reg_lo_write = per_wen[0] & per_en;
wire reg_hi_write = per_wen[1] & per_en;
wire reg_read = ~|per_wen & per_en;
wire reg_lo_write = per_we[0] & per_en;
wire reg_hi_write = per_we[1] & per_en;
wire reg_read = ~|per_we & per_en;
 
// Read/Write vectors
wire [255:0] reg_hi_wr = reg_dec & {256{reg_hi_write}};
187,8 → 183,3
 
endmodule // template_periph_8b
 
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_undefines.v"
`endif
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/periph/omsp_gpio.v
35,10 → 35,6
// $LastChangedBy$
// $LastChangedDate$
//----------------------------------------------------------------------------
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_defines.v"
`endif
 
module omsp_gpio (
 
76,7 → 72,7
per_addr, // Peripheral address
per_din, // Peripheral data input
per_en, // Peripheral enable (high active)
per_wen, // Peripheral write enable (high active)
per_we, // Peripheral write enable (high active)
puc // Main system reset
);
 
126,7 → 122,7
input [7:0] per_addr; // Peripheral address
input [15:0] per_din; // Peripheral data input
input per_en; // Peripheral enable (high active)
input [1:0] per_wen; // Peripheral write enable (high active)
input [1:0] per_we; // Peripheral write enable (high active)
input puc; // Main system reset
 
 
250,9 → 246,9
endcase
 
// Read/Write probes
wire reg_lo_write = per_wen[0] & per_en;
wire reg_hi_write = per_wen[1] & per_en;
wire reg_read = ~|per_wen & per_en;
wire reg_lo_write = per_we[0] & per_en;
wire reg_hi_write = per_we[1] & per_en;
wire reg_read = ~|per_we & per_en;
 
// Read/Write vectors
wire [255:0] reg_hi_wr = reg_dec & {256{reg_hi_write}};
826,8 → 822,3
p6sel_rd;
 
endmodule // omsp_gpio
 
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_undefines.v"
`endif
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/periph/omsp_timerA_defines.v
0,0 → 1,79
//----------------------------------------------------------------------------
// Copyright (C) 2001 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
//
//----------------------------------------------------------------------------
//
// *File Name: omsp_timerA_defines.v
//
// *Module Description:
// omsp_timerA Configuration file
//
// *Author(s):
// - Olivier Girard, olgirard@gmail.com
//
//----------------------------------------------------------------------------
// $Rev: 103 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
//----------------------------------------------------------------------------
//`define OMSP_TA_NO_INCLUDE
`ifdef OMSP_TA_NO_INCLUDE
`else
`include "omsp_timerA_undefines.v"
`endif
 
//----------------------------------------------------------------------------
// TIMER A CONFIGURATION
//----------------------------------------------------------------------------
 
 
 
//==========================================================================//
//==========================================================================//
//==========================================================================//
//==========================================================================//
//===== SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!! =====//
//==========================================================================//
//==========================================================================//
//==========================================================================//
//==========================================================================//
 
// Timer A: TACTL Control Register
`define TASSELx 9:8
`define TAIDx 7:6
`define TAMCx 5:4
`define TACLR 2
`define TAIE 1
`define TAIFG 0
 
// Timer A: TACCTLx Capture/Compare Control Register
`define TACMx 15:14
`define TACCISx 13:12
`define TASCS 11
`define TASCCI 10
`define TACAP 8
`define TAOUTMODx 7:5
`define TACCIE 4
`define TACCI 3
`define TAOUT 2
`define TACOV 1
`define TACCIFG 0
openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/periph/omsp_timerA_defines.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/periph/omsp_timerA.v =================================================================== --- openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/periph/omsp_timerA.v (revision 106) +++ openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/periph/omsp_timerA.v (revision 107) @@ -35,9 +35,9 @@ // $LastChangedBy$ // $LastChangedDate$ //---------------------------------------------------------------------------- -`ifdef OMSP_NO_INCLUDE +`ifdef OMSP_TA_NO_INCLUDE `else -`include "openMSP430_defines.v" +`include "omsp_timerA_defines.v" `endif module omsp_timerA ( @@ -62,7 +62,7 @@ per_addr, // Peripheral address per_din, // Peripheral data input per_en, // Peripheral enable (high active) - per_wen, // Peripheral write enable (high active) + per_we, // Peripheral write enable (high active) puc, // Main system reset smclk_en, // SMCLK enable (from CPU) ta_cci0a, // Timer A capture 0 input A @@ -96,7 +96,7 @@ input [7:0] per_addr; // Peripheral address input [15:0] per_din; // Peripheral data input input per_en; // Peripheral enable (high active) -input [1:0] per_wen; // Peripheral write enable (high active) +input [1:0] per_we; // Peripheral write enable (high active) input puc; // Main system reset input smclk_en; // SMCLK enable (from CPU) input ta_cci0a; // Timer A capture 0 input A @@ -157,8 +157,8 @@ endcase // Read/Write probes -wire reg_write = |per_wen & per_en; -wire reg_read = ~|per_wen & per_en; +wire reg_write = |per_we & per_en; +wire reg_read = ~|per_we & per_en; // Read/Write vectors wire [511:0] reg_wr = reg_dec & {512{reg_write}}; @@ -688,7 +688,7 @@ endmodule // omsp_timerA -`ifdef OMSP_NO_INCLUDE +`ifdef OMSP_TA_NO_INCLUDE `else -`include "openMSP430_undefines.v" +`include "omsp_timerA_undefines.v" `endif
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/periph/omsp_timerA_undefines.v
0,0 → 1,108
//----------------------------------------------------------------------------
// Copyright (C) 2001 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
//
//----------------------------------------------------------------------------
//
// *File Name: omsp_timerA_undefines.v
//
// *Module Description:
// omsp_timerA Verilog `undef file
//
// *Author(s):
// - Olivier Girard, olgirard@gmail.com
//
//----------------------------------------------------------------------------
// $Rev: 23 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $
//----------------------------------------------------------------------------
 
//----------------------------------------------------------------------------
// SYSTEM CONFIGURATION
//----------------------------------------------------------------------------
 
 
 
//==========================================================================//
//==========================================================================//
//==========================================================================//
//==========================================================================//
//===== SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!! =====//
//==========================================================================//
//==========================================================================//
//==========================================================================//
//==========================================================================//
 
// Timer A: TACTL Control Register
`ifdef TASSELx
`undef TASSELx
`endif
`ifdef TAIDx
`undef TAIDx
`endif
`ifdef TAMCx
`undef TAMCx
`endif
`ifdef TACLR
`undef TACLR
`endif
`ifdef TAIE
`undef TAIE
`endif
`ifdef TAIFG
`undef TAIFG
`endif
 
// Timer A: TACCTLx Capture/Compare Control Register
`ifdef TACMx
`undef TACMx
`endif
`ifdef TACCISx
`undef TACCISx
`endif
`ifdef TASCS
`undef TASCS
`endif
`ifdef TASCCI
`undef TASCCI
`endif
`ifdef TACAP
`undef TACAP
`endif
`ifdef TAOUTMODx
`undef TAOUTMODx
`endif
`ifdef TACCIE
`undef TACCIE
`endif
`ifdef TACCI
`undef TACCI
`endif
`ifdef TAOUT
`undef TAOUT
`endif
`ifdef TACOV
`undef TACOV
`endif
`ifdef TACCIFG
`undef TACCIFG
`endif
openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/periph/omsp_timerA_undefines.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/periph/template_periph_16b.v =================================================================== --- openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/periph/template_periph_16b.v (revision 106) +++ openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/periph/template_periph_16b.v (revision 107) @@ -40,10 +40,6 @@ // $LastChangedBy$ // $LastChangedDate$ //---------------------------------------------------------------------------- -`ifdef OMSP_NO_INCLUDE -`else -`include "openMSP430_defines.v" -`endif module template_periph_16b ( @@ -55,7 +51,7 @@ per_addr, // Peripheral address per_din, // Peripheral data input per_en, // Peripheral enable (high active) - per_wen, // Peripheral write enable (high active) + per_we, // Peripheral write enable (high active) puc // Main system reset ); @@ -69,7 +65,7 @@ input [7:0] per_addr; // Peripheral address input [15:0] per_din; // Peripheral data input input per_en; // Peripheral enable (high active) -input [1:0] per_wen; // Peripheral write enable (high active) +input [1:0] per_we; // Peripheral write enable (high active) input puc; // Main system reset @@ -107,8 +103,8 @@ endcase // Read/Write probes -wire reg_write = |per_wen & per_en; -wire reg_read = ~|per_wen & per_en; +wire reg_write = |per_we & per_en; +wire reg_read = ~|per_we & per_en; // Read/Write vectors wire [511:0] reg_wr = reg_dec & {512{reg_write}}; @@ -180,8 +176,3 @@ endmodule // template_periph_16b - -`ifdef OMSP_NO_INCLUDE -`else -`include "openMSP430_undefines.v" -`endif
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_multiplier.v
51,7 → 51,7
per_addr, // Peripheral address
per_din, // Peripheral data input
per_en, // Peripheral enable (high active)
per_wen, // Peripheral write enable (high active)
per_we, // Peripheral write enable (high active)
puc // Main system reset
);
 
65,7 → 65,7
input [7:0] per_addr; // Peripheral address
input [15:0] per_din; // Peripheral data input
input per_en; // Peripheral enable (high active)
input [1:0] per_wen; // Peripheral write enable (high active)
input [1:0] per_we; // Peripheral write enable (high active)
input puc; // Main system reset
 
 
121,8 → 121,8
endcase
 
// Read/Write probes
wire reg_write = |per_wen & per_en;
wire reg_read = ~|per_wen & per_en;
wire reg_write = |per_we & per_en;
wire reg_read = ~|per_we & per_en;
 
// Read/Write vectors
wire [511:0] reg_wr = reg_dec & {512{reg_write}};
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_dbg_uart.v
50,16 → 50,16
dbg_wr, // Debug register data write
// INPUTs
dbg_clk, // Debug unit clock
dbg_dout, // Debug register data output
dbg_rd_rdy, // Debug register data is ready for read
dbg_rst, // Debug unit reset
dbg_uart_rxd, // Debug interface: UART RXD
mclk, // Main system clock
mem_burst, // Burst on going
mem_burst_end, // End TX/RX burst
mem_burst_rd, // Start TX burst
mem_burst_wr, // Start RX burst
mem_bw, // Burst byte width
por // Power on reset
mem_bw // Burst byte width
);
 
// OUTPUTs
72,16 → 72,16
 
// INPUTs
//=========
input dbg_clk; // Debug unit clock
input [15:0] dbg_dout; // Debug register data output
input dbg_rd_rdy; // Debug register data is ready for read
input dbg_rst; // Debug unit reset
input dbg_uart_rxd; // Debug interface: UART RXD
input mclk; // Main system clock
input mem_burst; // Burst on going
input mem_burst_end; // End TX/RX burst
input mem_burst_rd; // Start TX burst
input mem_burst_wr; // Start RX burst
input mem_bw; // Burst byte width
input por; // Power on reset
 
 
//=============================================================================
91,9 → 91,9
// Synchronize RXD input & buffer
//--------------------------------
reg [3:0] rxd_sync;
always @ (posedge mclk or posedge por)
if (por) rxd_sync <= 4'hf;
else rxd_sync <= {rxd_sync[2:0], dbg_uart_rxd};
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) rxd_sync <= 4'hf;
else rxd_sync <= {rxd_sync[2:0], dbg_uart_rxd};
 
// Majority decision
//------------------------
104,9 → 104,9
{1'b0, rxd_sync[3]};
wire rxd_maj_nxt = (rxd_maj_cnt>=2'b10);
always @ (posedge mclk or posedge por)
if (por) rxd_maj <= 1'b0;
else rxd_maj <= rxd_maj_nxt;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) rxd_maj <= 1'b0;
else rxd_maj <= rxd_maj_nxt;
 
wire rxd_s = rxd_maj;
wire rxd_fe = rxd_maj & ~rxd_maj_nxt;
157,8 → 157,8
endcase
// State machine
always @(posedge mclk or posedge por)
if (por) uart_state <= RX_SYNC;
always @(posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) uart_state <= RX_SYNC;
else if (xfer_done | sync_done |
mem_burst_wr | mem_burst_rd) uart_state <= uart_state_nxt;
 
170,13 → 170,13
//=============================================================================
// 3) UART SYNCHRONIZATION
//=============================================================================
// After POR, the host needs to fist send a synchronization character (0x80)
// After DBG_RST, the host needs to fist send a synchronization character (0x80)
// If this feature doesn't work properly, it is possible to disable it by
// commenting the DBG_UART_AUTO_SYNC define in the openMSP430.inc file.
 
reg sync_busy;
always @ (posedge mclk or posedge por)
if (por) sync_busy <= 1'b0;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) sync_busy <= 1'b0;
else if ((uart_state==RX_SYNC) & rxd_fe) sync_busy <= 1'b1;
else if ((uart_state==RX_SYNC) & rxd_re) sync_busy <= 1'b0;
 
185,8 → 185,8
`ifdef DBG_UART_AUTO_SYNC
 
reg [`DBG_UART_XFER_CNT_W+2:0] sync_cnt;
always @ (posedge mclk or posedge por)
if (por) sync_cnt <= {{`DBG_UART_XFER_CNT_W{1'b1}}, 3'b000};
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) sync_cnt <= {{`DBG_UART_XFER_CNT_W{1'b1}}, 3'b000};
else if (sync_busy) sync_cnt <= sync_cnt+{{`DBG_UART_XFER_CNT_W+2{1'b0}}, 1'b1};
 
wire [`DBG_UART_XFER_CNT_W-1:0] bit_cnt_max = sync_cnt[`DBG_UART_XFER_CNT_W+2:3];
209,14 → 209,14
wire xfer_bit_inc = (xfer_bit!=4'h0) & (xfer_cnt=={`DBG_UART_XFER_CNT_W{1'b0}});
assign xfer_done = (xfer_bit==4'hb);
always @ (posedge mclk or posedge por)
if (por) xfer_bit <= 4'h0;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) xfer_bit <= 4'h0;
else if (txd_start | rxd_start) xfer_bit <= 4'h1;
else if (xfer_done) xfer_bit <= 4'h0;
else if (xfer_bit_inc) xfer_bit <= xfer_bit+4'h1;
 
always @ (posedge mclk or posedge por)
if (por) xfer_cnt <= {`DBG_UART_XFER_CNT_W{1'b0}};
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) xfer_cnt <= {`DBG_UART_XFER_CNT_W{1'b0}};
else if (rxd_start) xfer_cnt <= {1'b0, bit_cnt_max[`DBG_UART_XFER_CNT_W-1:1]};
else if (txd_start | xfer_bit_inc) xfer_cnt <= bit_cnt_max;
else xfer_cnt <= xfer_cnt+{`DBG_UART_XFER_CNT_W{1'b1}};
226,8 → 226,8
//-------------------------
wire [19:0] xfer_buf_nxt = {rxd_s, xfer_buf[19:1]};
 
always @ (posedge mclk or posedge por)
if (por) xfer_buf <= 20'h00000;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) xfer_buf <= 20'h00000;
else if (dbg_rd_rdy) xfer_buf <= {1'b1, dbg_dout[15:8], 2'b01, dbg_dout[7:0], 1'b0};
else if (xfer_bit_inc) xfer_buf <= xfer_buf_nxt;
 
236,8 → 236,8
//------------------------
reg dbg_uart_txd;
always @ (posedge mclk or posedge por)
if (por) dbg_uart_txd <= 1'b1;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) dbg_uart_txd <= 1'b1;
else if (xfer_bit_inc & tx_active) dbg_uart_txd <= xfer_buf[0];
 
246,13 → 246,13
//=============================================================================
 
reg [5:0] dbg_addr;
always @ (posedge mclk or posedge por)
if (por) dbg_addr <= 6'h00;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) dbg_addr <= 6'h00;
else if (cmd_valid) dbg_addr <= xfer_buf[`DBG_UART_ADDR];
 
reg dbg_bw;
always @ (posedge mclk or posedge por)
if (por) dbg_bw <= 1'b0;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) dbg_bw <= 1'b0;
else if (cmd_valid) dbg_bw <= xfer_buf[`DBG_UART_BW];
 
wire dbg_din_bw = mem_burst ? mem_bw : dbg_bw;
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_dbg_hwbrk.v
50,7 → 50,9
// INPUTs
brk_reg_rd, // Hardware break/watch-point register read select
brk_reg_wr, // Hardware break/watch-point register write select
dbg_clk, // Debug unit clock
dbg_din, // Debug register data input
dbg_rst, // Debug unit reset
eu_mab, // Execution-Unit Memory address bus
eu_mb_en, // Execution-Unit Memory bus enable
eu_mb_wr, // Execution-Unit Memory bus write transfer
58,9 → 60,7
eu_mdb_out, // Memory data bus output
exec_done, // Execution completed
fe_mb_en, // Frontend Memory bus enable
mclk, // Main system clock
pc, // Program counter
por // Power on reset
pc // Program counter
);
 
// OUTPUTs
73,7 → 73,9
//=========
input [3:0] brk_reg_rd; // Hardware break/watch-point register read select
input [3:0] brk_reg_wr; // Hardware break/watch-point register write select
input dbg_clk; // Debug unit clock
input [15:0] dbg_din; // Debug register data input
input dbg_rst; // Debug unit reset
input [15:0] eu_mab; // Execution-Unit Memory address bus
input eu_mb_en; // Execution-Unit Memory bus enable
input [1:0] eu_mb_wr; // Execution-Unit Memory bus write transfer
81,9 → 83,7
input [15:0] eu_mdb_out; // Memory data bus output
input exec_done; // Execution completed
input fe_mb_en; // Frontend Memory bus enable
input mclk; // Main system clock
input [15:0] pc; // Program counter
input por; // Power on reset
 
 
//=============================================================================
133,8 → 133,8
 
wire brk_ctl_wr = brk_reg_wr[BRK_CTL];
always @ (posedge mclk or posedge por)
if (por) brk_ctl <= 5'h00;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) brk_ctl <= 5'h00;
else if (brk_ctl_wr) brk_ctl <= {`HWBRK_RANGE & dbg_din[4], dbg_din[3:0]};
 
wire [7:0] brk_ctl_full = {3'b000, brk_ctl};
154,8 → 154,8
addr0_wr_set, addr0_rd_set};
wire [5:0] brk_stat_clr = ~dbg_din[5:0];
 
always @ (posedge mclk or posedge por)
if (por) brk_stat <= 6'h00;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) brk_stat <= 6'h00;
else if (brk_stat_wr) brk_stat <= ((brk_stat & brk_stat_clr) | brk_stat_set);
else brk_stat <= (brk_stat | brk_stat_set);
 
169,8 → 169,8
 
wire brk_addr0_wr = brk_reg_wr[BRK_ADDR0];
always @ (posedge mclk or posedge por)
if (por) brk_addr0 <= 16'h0000;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) brk_addr0 <= 16'h0000;
else if (brk_addr0_wr) brk_addr0 <= dbg_din;
 
180,8 → 180,8
 
wire brk_addr1_wr = brk_reg_wr[BRK_ADDR1];
always @ (posedge mclk or posedge por)
if (por) brk_addr1 <= 16'h0000;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) brk_addr1 <= 16'h0000;
else if (brk_addr1_wr) brk_addr1 <= dbg_din;
 
215,9 → 215,9
brk_ctl[`BRK_RANGE] & `HWBRK_RANGE;
 
reg fe_mb_en_buf;
always @ (posedge mclk or posedge por)
if (por) fe_mb_en_buf <= 1'b0;
else fe_mb_en_buf <= fe_mb_en;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) fe_mb_en_buf <= 1'b0;
else fe_mb_en_buf <= fe_mb_en;
 
wire equ_i_addr0 = fe_mb_en_buf & (pc==brk_addr0) & ~brk_ctl[`BRK_RANGE];
wire equ_i_addr1 = fe_mb_en_buf & (pc==brk_addr1) & ~brk_ctl[`BRK_RANGE];
244,8 → 244,8
// In general, We should here make sure no write access occures during the
// same instruction cycle before setting the read flag.
reg [2:0] d_rd_trig;
always @ (posedge mclk or posedge por)
if (por) d_rd_trig <= 3'h0;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) d_rd_trig <= 3'h0;
else if (exec_done) d_rd_trig <= 3'h0;
else d_rd_trig <= {equ_d_range & ~brk_ctl[`BRK_I_EN] & ~|eu_mb_wr,
equ_d_addr1 & ~brk_ctl[`BRK_I_EN] & ~|eu_mb_wr,
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_sfr.v
55,7 → 55,7
per_addr, // Peripheral address
per_din, // Peripheral data input
per_en, // Peripheral enable (high active)
per_wen, // Peripheral write enable (high active)
per_we, // Peripheral write enable (high active)
por, // Power-on reset
puc, // Main system reset
wdtifg_clr, // Clear Watchdog-timer interrupt flag
79,7 → 79,7
input [7:0] per_addr; // Peripheral address
input [15:0] per_din; // Peripheral data input
input per_en; // Peripheral enable (high active)
input [1:0] per_wen; // Peripheral write enable (high active)
input [1:0] per_we; // Peripheral write enable (high active)
input por; // Power-on reset
input puc; // Main system reset
input wdtifg_clr; // Clear Watchdog-timer interrupt flag
115,9 → 115,9
endcase
 
// Read/Write probes
wire reg_lo_write = per_wen[0] & per_en;
wire reg_hi_write = per_wen[1] & per_en;
wire reg_read = ~|per_wen & per_en;
wire reg_lo_write = per_we[0] & per_en;
wire reg_hi_write = per_we[1] & per_en;
wire reg_read = ~|per_we & per_en;
 
// Read/Write vectors
wire [255:0] reg_hi_wr = reg_dec & {256{reg_hi_write}};
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_dbg.v
50,14 → 50,18
dbg_mem_en, // Debug unit memory enable
dbg_mem_wr, // Debug unit memory write
dbg_reg_wr, // Debug unit CPU register write
dbg_reset, // Reset CPU from debug interface
dbg_cpu_reset, // Reset CPU from debug interface
dbg_uart_txd, // Debug interface: UART TXD
// INPUTs
cpu_en_s, // Enable CPU code execution (synchronous)
dbg_clk, // Debug unit clock
dbg_en_s, // Debug interface enable (synchronous)
dbg_halt_st, // Halt/Run status from CPU
dbg_mem_din, // Debug unit Memory data input
dbg_reg_din, // Debug unit CPU register data input
dbg_uart_rxd, // Debug interface: UART RXD
dbg_rst, // Debug unit reset
dbg_uart_rxd, // Debug interface: UART RXD (asynchronous)
decode_noirq, // Frontend decode instruction
eu_mab, // Execution-Unit Memory address bus
eu_mb_en, // Execution-Unit Memory bus enable
67,9 → 71,7
exec_done, // Execution completed
fe_mb_en, // Frontend Memory bus enable
fe_mdb_in, // Frontend Memory data bus input
mclk, // Main system clock
pc, // Program counter
por, // Power on reset
puc // Main system reset
);
 
82,15 → 84,19
output dbg_mem_en; // Debug unit memory enable
output [1:0] dbg_mem_wr; // Debug unit memory write
output dbg_reg_wr; // Debug unit CPU register write
output dbg_reset; // Reset CPU from debug interface
output dbg_cpu_reset; // Reset CPU from debug interface
output dbg_uart_txd; // Debug interface: UART TXD
 
// INPUTs
//=========
input cpu_en_s; // Enable CPU code execution (synchronous)
input dbg_clk; // Debug unit clock
input dbg_en_s; // Debug interface enable (synchronous)
input dbg_halt_st; // Halt/Run status from CPU
input [15:0] dbg_mem_din; // Debug unit Memory data input
input [15:0] dbg_reg_din; // Debug unit CPU register data input
input dbg_uart_rxd; // Debug interface: UART RXD
input dbg_rst; // Debug unit reset
input dbg_uart_rxd; // Debug interface: UART RXD (asynchronous)
input decode_noirq; // Frontend decode instruction
input [15:0] eu_mab; // Execution-Unit Memory address bus
input eu_mb_en; // Execution-Unit Memory bus enable
100,9 → 106,7
input exec_done; // Execution completed
input fe_mb_en; // Frontend Memory bus enable
input [15:0] fe_mdb_in; // Frontend Memory data bus input
input mclk; // Main system clock
input [15:0] pc; // Program counter
input por; // Power on reset
input puc; // Main system reset
 
 
206,10 → 210,10
 
// PUC is localy used as a data.
reg [1:0] puc_sync;
always @ (posedge mclk or posedge por)
if (por) puc_sync <= 2'b11;
else puc_sync <= {puc_sync[0] , puc};
wire puc_s = puc_sync[1];
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) puc_sync <= 2'b11;
else puc_sync <= {puc_sync[0] , puc};
wire puc_s = puc_sync[1];
 
 
//============================================================================
288,8 → 292,12
 
wire cpu_ctl_wr = reg_wr[CPU_CTL];
always @ (posedge mclk or posedge por)
if (por) cpu_ctl <= 4'h0;
always @ (posedge dbg_clk or posedge dbg_rst)
`ifdef DBG_RST_BRK_EN
if (dbg_rst) cpu_ctl <= 4'h4;
`else
if (dbg_rst) cpu_ctl <= 4'h0;
`endif
else if (cpu_ctl_wr) cpu_ctl <= dbg_din[6:3];
 
wire [7:0] cpu_ctl_full = {1'b0, cpu_ctl, 3'b000};
310,8 → 318,8
wire [3:2] cpu_stat_set = {dbg_swbrk, puc_s};
wire [3:2] cpu_stat_clr = ~dbg_din[3:2];
 
always @ (posedge mclk or posedge por)
if (por) cpu_stat <= 2'b00;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) cpu_stat <= 2'b00;
else if (cpu_stat_wr) cpu_stat <= ((cpu_stat & cpu_stat_clr) | cpu_stat_set);
else cpu_stat <= (cpu_stat | cpu_stat_set);
 
345,16 → 353,16
 
wire mem_ctl_wr = reg_wr[MEM_CTL];
always @ (posedge mclk or posedge por)
if (por) mem_ctl <= 3'h0;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) mem_ctl <= 3'h0;
else if (mem_ctl_wr) mem_ctl <= dbg_din[3:1];
 
wire [7:0] mem_ctl_full = {4'b0000, mem_ctl, 1'b0};
 
reg mem_start;
always @ (posedge mclk or posedge por)
if (por) mem_start <= 1'b0;
else mem_start <= mem_ctl_wr & dbg_din[0];
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) mem_start <= 1'b0;
else mem_start <= mem_ctl_wr & dbg_din[0];
 
wire mem_bw = mem_ctl[3];
370,8 → 378,8
mem_addr[0] ? {8'h00, dbg_mem_din[15:8]} :
{8'h00, dbg_mem_din[7:0]};
always @ (posedge mclk or posedge por)
if (por) mem_data <= 16'h0000;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) mem_data <= 16'h0000;
else if (mem_data_wr) mem_data <= dbg_din;
else if (dbg_reg_rd) mem_data <= dbg_reg_din;
else if (dbg_mem_rd_dly) mem_data <= dbg_mem_din_bw;
389,8 → 397,8
(dbg_mem_acc & ~mem_bw) ? 16'h0002 :
(dbg_mem_acc | dbg_reg_acc) ? 16'h0001 : 16'h0000;
always @ (posedge mclk or posedge por)
if (por) mem_addr <= 16'h0000;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) mem_addr <= 16'h0000;
else if (mem_addr_wr) mem_addr <= dbg_din;
else mem_addr <= mem_addr + mem_addr_inc;
402,8 → 410,8
wire [15:0] mem_cnt_dec = (mem_cnt==16'h0000) ? 16'h0000 :
(dbg_mem_acc | dbg_reg_acc) ? 16'hffff : 16'h0000;
always @ (posedge mclk or posedge por)
if (por) mem_cnt <= 16'h0000;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) mem_cnt <= 16'h0000;
else if (mem_cnt_wr) mem_cnt <= dbg_din;
else mem_cnt <= mem_cnt + mem_cnt_dec;
 
435,7 → 443,9
// INPUTs
.brk_reg_rd (brk0_reg_rd), // Hardware break/watch-point register read select
.brk_reg_wr (brk0_reg_wr), // Hardware break/watch-point register write select
.dbg_clk (dbg_clk), // Debug unit clock
.dbg_din (dbg_din), // Debug register data input
.dbg_rst (dbg_rst), // Debug unit reset
.eu_mab (eu_mab), // Execution-Unit Memory address bus
.eu_mb_en (eu_mb_en), // Execution-Unit Memory bus enable
.eu_mb_wr (eu_mb_wr), // Execution-Unit Memory bus write transfer
443,9 → 453,7
.eu_mdb_out (eu_mdb_out), // Memory data bus output
.exec_done (exec_done), // Execution completed
.fe_mb_en (fe_mb_en), // Frontend Memory bus enable
.mclk (mclk), // Main system clock
.pc (pc), // Program counter
.por (por) // Power on reset
.pc (pc) // Program counter
);
 
`else
477,7 → 485,9
// INPUTs
.brk_reg_rd (brk1_reg_rd), // Hardware break/watch-point register read select
.brk_reg_wr (brk1_reg_wr), // Hardware break/watch-point register write select
.dbg_clk (dbg_clk), // Debug unit clock
.dbg_din (dbg_din), // Debug register data input
.dbg_rst (dbg_rst), // Debug unit reset
.eu_mab (eu_mab), // Execution-Unit Memory address bus
.eu_mb_en (eu_mb_en), // Execution-Unit Memory bus enable
.eu_mb_wr (eu_mb_wr), // Execution-Unit Memory bus write transfer
485,9 → 495,7
.eu_mdb_out (eu_mdb_out), // Memory data bus output
.exec_done (exec_done), // Execution completed
.fe_mb_en (fe_mb_en), // Frontend Memory bus enable
.mclk (mclk), // Main system clock
.pc (pc), // Program counter
.por (por) // Power on reset
.pc (pc) // Program counter
);
 
`else
519,7 → 527,9
// INPUTs
.brk_reg_rd (brk2_reg_rd), // Hardware break/watch-point register read select
.brk_reg_wr (brk2_reg_wr), // Hardware break/watch-point register write select
.dbg_clk (dbg_clk), // Debug unit clock
.dbg_din (dbg_din), // Debug register data input
.dbg_rst (dbg_rst), // Debug unit reset
.eu_mab (eu_mab), // Execution-Unit Memory address bus
.eu_mb_en (eu_mb_en), // Execution-Unit Memory bus enable
.eu_mb_wr (eu_mb_wr), // Execution-Unit Memory bus write transfer
527,9 → 537,7
.eu_mdb_out (eu_mdb_out), // Memory data bus output
.exec_done (exec_done), // Execution completed
.fe_mb_en (fe_mb_en), // Frontend Memory bus enable
.mclk (mclk), // Main system clock
.pc (pc), // Program counter
.por (por) // Power on reset
.pc (pc) // Program counter
);
 
`else
561,7 → 569,9
// INPUTs
.brk_reg_rd (brk3_reg_rd), // Hardware break/watch-point register read select
.brk_reg_wr (brk3_reg_wr), // Hardware break/watch-point register write select
.dbg_clk (dbg_clk), // Debug unit clock
.dbg_din (dbg_din), // Debug register data input
.dbg_rst (dbg_rst), // Debug unit reset
.eu_mab (eu_mab), // Execution-Unit Memory address bus
.eu_mb_en (eu_mb_en), // Execution-Unit Memory bus enable
.eu_mb_wr (eu_mb_wr), // Execution-Unit Memory bus write transfer
569,9 → 579,7
.eu_mdb_out (eu_mdb_out), // Memory data bus output
.exec_done (exec_done), // Execution completed
.fe_mb_en (fe_mb_en), // Frontend Memory bus enable
.mclk (mclk), // Main system clock
.pc (pc), // Program counter
.por (por) // Power on reset
.pc (pc) // Program counter
);
 
`else
608,8 → 616,8
brk3_dout;
 
// Tell UART/JTAG interface that the data is ready to be read
always @ (posedge mclk or posedge por)
if (por) dbg_rd_rdy <= 1'b0;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) dbg_rd_rdy <= 1'b0;
else if (mem_burst | mem_burst_rd) dbg_rd_rdy <= (dbg_reg_rd | dbg_mem_rd_dly);
else dbg_rd_rdy <= dbg_rd;
 
620,19 → 628,19
 
// Reset CPU
//--------------------------
wire dbg_reset = cpu_ctl[`CPU_RST];
wire dbg_cpu_reset = cpu_ctl[`CPU_RST];
 
// Break after reset
//--------------------------
wire halt_rst = cpu_ctl[`RST_BRK_EN] & puc_s;
wire halt_rst = cpu_ctl[`RST_BRK_EN] & dbg_en_s & puc_s;
 
// Freeze peripherals
//--------------------------
wire dbg_freeze = dbg_halt_st & cpu_ctl[`FRZ_BRK_EN];
wire dbg_freeze = dbg_halt_st & (cpu_ctl[`FRZ_BRK_EN] | ~cpu_en_s);
 
 
// Software break
//--------------------------
assign dbg_swbrk = (fe_mdb_in==`DBG_SWBRK_OP) & decode_noirq & cpu_ctl[`SW_BRK_EN];
641,8 → 649,8
// Single step
//--------------------------
reg [1:0] inc_step;
always @(posedge mclk or posedge por)
if (por) inc_step <= 2'b00;
always @(posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) inc_step <= 2'b00;
else if (istep) inc_step <= 2'b11;
else inc_step <= {inc_step[0], 1'b0};
 
658,8 → 666,8
wire halt_flag_set = halt_cpu | halt_rst | dbg_swbrk | mem_halt_cpu |
brk0_halt | brk1_halt | brk2_halt | brk3_halt;
 
always @(posedge mclk or posedge por)
if (por) halt_flag <= 1'b0;
always @(posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) halt_flag <= 1'b0;
else if (halt_flag_clr) halt_flag <= 1'b0;
else if (halt_flag_set) halt_flag <= 1'b1;
 
677,8 → 685,8
wire mem_burst_end = ((dbg_wr | dbg_rd_rdy) & ~|mem_cnt);
 
// Detect when burst is on going
always @(posedge mclk or posedge por)
if (por) mem_burst <= 1'b0;
always @(posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) mem_burst <= 1'b0;
else if (mem_burst_start) mem_burst <= 1'b1;
else if (mem_burst_end) mem_burst <= 1'b0;
 
688,9 → 696,9
 
// Trigger CPU Register or memory access during a burst
reg mem_startb;
always @(posedge mclk or posedge por)
if (por) mem_startb <= 1'b0;
else mem_startb <= (mem_burst & (dbg_wr | dbg_rd)) | mem_burst_rd;
always @(posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) mem_startb <= 1'b0;
else mem_startb <= (mem_burst & (dbg_wr | dbg_rd)) | mem_burst_rd;
 
// Combine single and burst memory start of sequence
wire mem_seq_start = ((mem_start & ~|mem_cnt) | mem_startb);
719,9 → 727,9
endcase
 
// State machine
always @(posedge mclk or posedge por)
if (por) mem_state <= M_IDLE;
else mem_state <= mem_state_nxt;
always @(posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) mem_state <= M_IDLE;
else mem_state <= mem_state_nxt;
 
// Utility signals
assign mem_halt_cpu = (mem_state==M_IDLE) & (mem_state_nxt==M_SET_BRK);
748,9 → 756,9
 
 
// It takes one additional cycle to read from Memory as from registers
always @(posedge mclk or posedge por)
if (por) dbg_mem_rd_dly <= 1'b0;
else dbg_mem_rd_dly <= dbg_mem_rd;
always @(posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) dbg_mem_rd_dly <= 1'b0;
else dbg_mem_rd_dly <= dbg_mem_rd;
 
//=============================================================================
767,16 → 775,16
.dbg_wr (dbg_wr), // Debug register data write
// INPUTs
.dbg_clk (dbg_clk), // Debug unit clock
.dbg_dout (dbg_dout), // Debug register data output
.dbg_rd_rdy (dbg_rd_rdy), // Debug register data is ready for read
.dbg_rst (dbg_rst), // Debug unit reset
.dbg_uart_rxd (dbg_uart_rxd), // Debug interface: UART RXD
.mclk (mclk), // Main system clock
.mem_burst (mem_burst), // Burst on going
.mem_burst_end(mem_burst_end), // End TX/RX burst
.mem_burst_rd (mem_burst_rd), // Start TX burst
.mem_burst_wr (mem_burst_wr), // Start RX burst
.mem_bw (mem_bw), // Burst byte width
.por (por) // Power on reset
.mem_bw (mem_bw) // Burst byte width
);
 
`else
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_clock_module.v
48,6 → 48,10
 
// OUTPUTs
aclk_en, // ACLK enable
cpu_en_s, // Enable CPU code execution (synchronous)
dbg_clk, // Debug unit clock
dbg_en_s, // Debug interface enable (synchronous)
dbg_rst, // Debug unit reset
mclk, // Main system clock
per_dout, // Peripheral data output
por, // Power-on reset
55,7 → 59,9
smclk_en, // SMCLK enable
// INPUTs
dbg_reset, // Reset CPU from debug interface
cpu_en, // Enable CPU code execution (asynchronous)
dbg_cpu_reset, // Reset CPU from debug interface
dbg_en, // Debug interface enable (asynchronous)
dco_clk, // Fast oscillator (fast clock)
lfxt_clk, // Low frequency oscillator (typ 32kHz)
oscoff, // Turns off LFXT1 clock input
62,8 → 68,8
per_addr, // Peripheral address
per_din, // Peripheral data input
per_en, // Peripheral enable (high active)
per_wen, // Peripheral write enable (high active)
reset_n, // Reset Pin (low active)
per_we, // Peripheral write enable (high active)
reset_n, // Reset Pin (low active, asynchronous)
scg1, // System clock generator 1. Turns off the SMCLK
wdt_reset // Watchdog-timer reset
);
71,6 → 77,10
// OUTPUTs
//=========
output aclk_en; // ACLK enable
output cpu_en_s; // Enable CPU code execution (synchronous)
output dbg_clk; // Debug unit clock
output dbg_en_s; // Debug unit enable (synchronous)
output dbg_rst; // Debug unit reset
output mclk; // Main system clock
output [15:0] per_dout; // Peripheral data output
output por; // Power-on reset
79,7 → 89,9
 
// INPUTs
//=========
input dbg_reset; // Reset CPU from debug interface
input cpu_en; // Enable CPU code execution (asynchronous)
input dbg_cpu_reset;// Reset CPU from debug interface
input dbg_en; // Debug interface enable (asynchronous)
input dco_clk; // Fast oscillator (fast clock)
input lfxt_clk; // Low frequency oscillator (typ 32kHz)
input oscoff; // Turns off LFXT1 clock input
86,8 → 98,8
input [7:0] per_addr; // Peripheral address
input [15:0] per_din; // Peripheral data input
input per_en; // Peripheral enable (high active)
input [1:0] per_wen; // Peripheral write enable (high active)
input reset_n; // Reset Pin (low active)
input [1:0] per_we; // Peripheral write enable (high active)
input reset_n; // Reset Pin (low active, asynchronous)
input scg1; // System clock generator 1. Turns off the SMCLK
input wdt_reset; // Watchdog-timer reset
 
119,9 → 131,9
endcase
 
// Read/Write probes
wire reg_lo_write = per_wen[0] & per_en;
wire reg_hi_write = per_wen[1] & per_en;
wire reg_read = ~|per_wen & per_en;
wire reg_lo_write = per_we[0] & per_en;
wire reg_hi_write = per_we[1] & per_en;
wire reg_read = ~|per_we & per_en;
 
// Read/Write vectors
wire [255:0] reg_hi_wr = reg_dec & {256{reg_hi_write}};
171,12 → 183,22
// 5) CLOCK GENERATION
//=============================================================================
 
// Synchronize CPU_EN signal
//---------------------------------------
reg [1:0] cpu_en_sync;
always @ (posedge mclk or posedge por)
if (por) cpu_en_sync <= 2'b00;
else cpu_en_sync <= {cpu_en_sync[0], cpu_en};
 
assign cpu_en_s = cpu_en_sync[1];
 
// Synchronize LFXT_CLK & edge detection
//---------------------------------------
reg [2:0] lfxt_clk_s;
always @ (posedge mclk or posedge puc)
if (puc) lfxt_clk_s <= 3'b000;
always @ (posedge mclk or posedge por)
if (por) lfxt_clk_s <= 3'b000;
else lfxt_clk_s <= {lfxt_clk_s[1:0], lfxt_clk};
 
wire lfxt_clk_en = (lfxt_clk_s[1] & ~lfxt_clk_s[2]) & ~(oscoff & ~bcsctl2[`SELS]);
202,7 → 224,7
 
always @ (posedge mclk or posedge puc)
if (puc) aclk_en <= 1'b0;
else aclk_en <= aclk_en_nxt;
else aclk_en <= aclk_en_nxt & cpu_en_s;
 
always @ (posedge mclk or posedge puc)
if (puc) aclk_div <= 3'h0;
224,7 → 246,7
always @ (posedge mclk or posedge puc)
if (puc) smclk_en <= 1'b0;
else smclk_en <= smclk_en_nxt;
else smclk_en <= smclk_en_nxt & cpu_en_s;
 
always @ (posedge mclk or posedge puc)
if (puc) smclk_div <= 3'h0;
231,29 → 253,51
else if ((bcsctl2[`DIVSx]!=2'b00) & smclk_in) smclk_div <= smclk_div+3'h1;
 
 
// Generate DBG_CLK
//----------------------------
 
assign dbg_clk = mclk;
 
 
//=============================================================================
// 6) RESET GENERATION
//=============================================================================
 
// Generate synchronized POR
wire por_reset = !reset_n;
wire por_reset_a = !reset_n;
 
reg [1:0] por_s;
always @(posedge mclk_n or posedge por_reset)
if (por_reset) por_s <= 2'b11;
else por_s <= {por_s[0], 1'b0};
always @(posedge mclk or posedge por_reset_a)
if (por_reset_a) por_s <= 2'b11;
else por_s <= {por_s[0], 1'b0};
wire por = por_s[1];
 
 
// Generate main system reset
wire puc_reset = por_reset | wdt_reset | dbg_reset;
wire puc_reset = por | wdt_reset | dbg_cpu_reset;
 
reg [1:0] puc_s;
always @(posedge mclk_n or posedge puc_reset)
always @(posedge mclk or posedge puc_reset)
if (puc_reset) puc_s <= 2'b11;
else puc_s <= {puc_s[0], 1'b0};
wire puc = puc_s[1];
 
 
// Generate debug unit reset
`ifdef DBG_EN
reg [1:0] dbg_rst_s;
always @(posedge mclk or posedge por)
if (por) dbg_rst_s <= 2'b11;
else dbg_rst_s <= {dbg_rst_s[0], ~dbg_en};
 
`else
wire [1:0] dbg_rst_s = 2'b11;
`endif
 
wire dbg_en_s = ~dbg_rst_s[1];
wire dbg_rst = dbg_rst_s[1];
 
 
endmodule // omsp_clock_module
 
`ifdef OMSP_NO_INCLUDE
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_watchdog.v
58,7 → 58,7
per_addr, // Peripheral address
per_din, // Peripheral data input
per_en, // Peripheral enable (high active)
per_wen, // Peripheral write enable (high active)
per_we, // Peripheral write enable (high active)
puc, // Main system reset
smclk_en, // SMCLK enable
wdtie // Watchdog timer interrupt enable
82,7 → 82,7
input [7:0] per_addr; // Peripheral address
input [15:0] per_din; // Peripheral data input
input per_en; // Peripheral enable (high active)
input [1:0] per_wen; // Peripheral write enable (high active)
input [1:0] per_we; // Peripheral write enable (high active)
input puc; // Main system reset
input smclk_en; // SMCLK enable
input wdtie; // Watchdog timer interrupt enable
113,8 → 113,8
endcase
 
// Read/Write probes
wire reg_write = |per_wen & per_en;
wire reg_read = ~|per_wen & per_en;
wire reg_write = |per_we & per_en;
wire reg_read = ~|per_we & per_en;
 
// Read/Write vectors
wire [511:0] reg_wr = reg_dec & {512{reg_write}};
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_mem_backbone.v
53,7 → 53,7
fe_pmem_wait, // Frontend wait for Instruction fetch
per_addr, // Peripheral address
per_din, // Peripheral data input
per_wen, // Peripheral write enable (high active)
per_we, // Peripheral write enable (high active)
per_en, // Peripheral enable (high active)
pmem_addr, // Program Memory address
pmem_cen, // Program Memory chip enable (low active)
91,7 → 91,7
output fe_pmem_wait; // Frontend wait for Instruction fetch
output [7:0] per_addr; // Peripheral address
output [15:0] per_din; // Peripheral data input
output [1:0] per_wen; // Peripheral write enable (high active)
output [1:0] per_we; // Peripheral write enable (high active)
output per_en; // Peripheral enable (high active)
output [`PMEM_MSB:0] pmem_addr; // Program Memory address
output pmem_cen; // Program Memory chip enable (low active)
177,7 → 177,7
 
wire [7:0] per_addr = dbg_mem_en ? dbg_mem_addr[8:1] : eu_mab[7:0];
wire [15:0] per_din = dbg_mem_en ? dbg_mem_dout : eu_mdb_out;
wire [1:0] per_wen = dbg_mem_en ? dbg_mem_wr : eu_mb_wr;
wire [1:0] per_we = dbg_mem_en ? dbg_mem_wr : eu_mb_wr;
wire per_en = dbg_mem_en ? dbg_per_en : eu_per_en;
 
reg [15:0] per_dout_val;
231,11 → 231,16
//---------------------------------
 
// Select between peripherals, RAM and ROM
reg [1:0] dbg_mem_din_sel;
`ifdef DBG_EN
reg [1:0] dbg_mem_din_sel;
always @(posedge mclk or posedge puc)
if (puc) dbg_mem_din_sel <= 2'b00;
else dbg_mem_din_sel <= {~dbg_pmem_cen, dbg_per_en};
 
`else
wire [1:0] dbg_mem_din_sel = 2'b00;
`endif
// Mux
assign dbg_mem_din = dbg_mem_din_sel[1] ? pmem_dout :
dbg_mem_din_sel[0] ? per_dout_val : dmem_dout;
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/openMSP430_defines.v
114,6 → 114,15
`define DBG_HWBRK_3
 
 
// Defines the debugger CPU_CTL.RST_BRK_EN reset value (CPU break on PUC reset)
//
// When defined, this concretely bring the CPU to break after a PUC
// occurrence by default. This is typically usefull when the program
// memory can only be initialized through the serial debug interface.
//
//`define DBG_RST_BRK_EN
 
 
//==========================================================================//
//==========================================================================//
//==========================================================================//
366,28 → 375,7
`define SELS 3
`define DIVSx 2:1
 
// Timer A: TACTL Control Register
`define TASSELx 9:8
`define TAIDx 7:6
`define TAMCx 5:4
`define TACLR 2
`define TAIE 1
`define TAIFG 0
 
// Timer A: TACCTLx Capture/Compare Control Register
`define TACMx 15:14
`define TACCISx 13:12
`define TASCS 11
`define TASCCI 10
`define TACAP 8
`define TAOUTMODx 7:5
`define TACCIE 4
`define TACCI 3
`define TAOUT 2
`define TACOV 1
`define TACCIFG 0
 
 
//
// DEBUG INTERFACE EXTRA CONFIGURATION
//======================================
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/openMSP430.v
54,7 → 54,7
mclk, // Main system clock
per_addr, // Peripheral address
per_din, // Peripheral data input
per_wen, // Peripheral write enable (high active)
per_we, // Peripheral write enable (high active)
per_en, // Peripheral enable (high active)
pmem_addr, // Program Memory address
pmem_cen, // Program Memory chip enable (low active)
64,7 → 64,9
smclk_en, // SMCLK enable
 
// INPUTs
dbg_uart_rxd, // Debug interface: UART RXD
cpu_en, // Enable CPU code execution (asynchronous)
dbg_en, // Debug interface enable (asynchronous)
dbg_uart_rxd, // Debug interface: UART RXD (asynchronous)
dco_clk, // Fast oscillator (fast clock)
dmem_dout, // Data Memory data output
irq, // Maskable interrupts
72,7 → 74,7
nmi, // Non-maskable interrupt (asynchronous)
per_dout, // Peripheral data output
pmem_dout, // Program Memory data output
reset_n // Reset Pin (low active)
reset_n // Reset Pin (low active, asynchronous)
);
 
// OUTPUTs
88,7 → 90,7
output mclk; // Main system clock
output [7:0] per_addr; // Peripheral address
output [15:0] per_din; // Peripheral data input
output [1:0] per_wen; // Peripheral write enable (high active)
output [1:0] per_we; // Peripheral write enable (high active)
output per_en; // Peripheral enable (high active)
output [`PMEM_MSB:0] pmem_addr; // Program Memory address
output pmem_cen; // Program Memory chip enable (low active)
100,7 → 102,9
 
// INPUTs
//=========
input dbg_uart_rxd; // Debug interface: UART RXD
input cpu_en; // Enable CPU code execution (asynchronous)
input dbg_en; // Debug interface enable (asynchronous)
input dbg_uart_rxd; // Debug interface: UART RXD (asynchronous)
input dco_clk; // Fast oscillator (fast clock)
input [15:0] dmem_dout; // Data Memory data output
input [13:0] irq; // Maskable interrupts
108,7 → 112,7
input nmi; // Non-maskable interrupt (asynchronous)
input [15:0] per_dout; // Peripheral data output
input [15:0] pmem_dout; // Program Memory data output
input reset_n; // Reset Pin (active low)
input reset_n; // Reset Pin (active low, asynchronous)
 
 
 
144,7 → 148,7
wire dbg_halt_cmd;
wire dbg_mem_en;
wire dbg_reg_wr;
wire dbg_reset;
wire dbg_cpu_reset;
wire [15:0] dbg_mem_addr;
wire [15:0] dbg_mem_dout;
wire [15:0] dbg_mem_din;
166,6 → 170,10
 
// OUTPUTs
.aclk_en (aclk_en), // ACLK enablex
.cpu_en_s (cpu_en_s), // Enable CPU code execution (synchronous)
.dbg_clk (dbg_clk), // Debug unit clock
.dbg_en_s (dbg_en_s), // Debug interface enable (synchronous)
.dbg_rst (dbg_rst), // Debug unit reset
.mclk (mclk), // Main system clock
.per_dout (per_dout_clk), // Peripheral data output
.por (por), // Power-on reset
173,7 → 181,9
.smclk_en (smclk_en), // SMCLK enable
// INPUTs
.dbg_reset (dbg_reset), // Reset CPU from debug interface
.cpu_en (cpu_en), // Enable CPU code execution (asynchronous)
.dbg_cpu_reset(dbg_cpu_reset), // Reset CPU from debug interface
.dbg_en (dbg_en), // Debug interface enable (asynchronous)
.dco_clk (dco_clk), // Fast oscillator (fast clock)
.lfxt_clk (lfxt_clk), // Low frequency oscillator (typ 32kHz)
.oscoff (oscoff), // Turns off LFXT1 clock input
180,8 → 190,8
.per_addr (per_addr), // Peripheral address
.per_din (per_din), // Peripheral data input
.per_en (per_en), // Peripheral enable (high active)
.per_wen (per_wen), // Peripheral write enable (high active)
.reset_n (reset_n), // Reset Pin (low active)
.per_we (per_we), // Peripheral write enable (high active)
.reset_n (reset_n), // Reset Pin (low active, asynchronous)
.scg1 (scg1), // System clock generator 1. Turns off the SMCLK
.wdt_reset (wdt_reset) // Watchdog-timer reset
);
219,6 → 229,7
.pc_nxt (pc_nxt), // Next PC value (for CALL & IRQ)
// INPUTs
.cpu_en_s (cpu_en_s), // Enable CPU code execution (synchronous)
.cpuoff (cpuoff), // Turns off the CPU
.dbg_halt_cmd (dbg_halt_cmd), // Halt CPU command
.dbg_reg_sel (dbg_mem_addr[3:0]), // Debug selected register for rd/wr access
298,7 → 309,7
.fe_pmem_wait (fe_pmem_wait), // Frontend wait for Instruction fetch
.per_addr (per_addr), // Peripheral address
.per_din (per_din), // Peripheral data input
.per_wen (per_wen), // Peripheral write enable (high active)
.per_we (per_we), // Peripheral write enable (high active)
.per_en (per_en), // Peripheral enable (high active)
.pmem_addr (pmem_addr), // Program Memory address
.pmem_cen (pmem_cen), // Program Memory chip enable (low active)
344,7 → 355,7
.per_addr (per_addr), // Peripheral address
.per_din (per_din), // Peripheral data input
.per_en (per_en), // Peripheral enable (high active)
.per_wen (per_wen), // Peripheral write enable (high active)
.per_we (per_we), // Peripheral write enable (high active)
.por (por), // Power-on reset
.puc (puc), // Main system reset
.wdtifg_clr (irq_acc[10]), // Clear Watchdog-timer interrupt flag
376,7 → 387,7
.per_addr (per_addr), // Peripheral address
.per_din (per_din), // Peripheral data input
.per_en (per_en), // Peripheral enable (high active)
.per_wen (per_wen), // Peripheral write enable (high active)
.per_we (per_we), // Peripheral write enable (high active)
.puc (puc), // Main system reset
.smclk_en (smclk_en), // SMCLK enable
.wdtie (wdtie) // Watchdog-timer interrupt enable
397,7 → 408,7
.per_addr (per_addr), // Peripheral address
.per_din (per_din), // Peripheral data input
.per_en (per_en), // Peripheral enable (high active)
.per_wen (per_wen), // Peripheral write enable (high active)
.per_we (per_we), // Peripheral write enable (high active)
.puc (puc) // Main system reset
);
`else
430,14 → 441,18
.dbg_mem_en (dbg_mem_en), // Debug unit memory enable
.dbg_mem_wr (dbg_mem_wr), // Debug unit memory write
.dbg_reg_wr (dbg_reg_wr), // Debug unit CPU register write
.dbg_reset (dbg_reset), // Reset CPU from debug interface
.dbg_cpu_reset(dbg_cpu_reset), // Reset CPU from debug interface
.dbg_uart_txd (dbg_uart_txd), // Debug interface: UART TXD
// INPUTs
.cpu_en_s (cpu_en_s), // Enable CPU code execution (synchronous)
.dbg_clk (dbg_clk), // Debug unit clock
.dbg_en_s (dbg_en_s), // Debug interface enable (synchronous)
.dbg_halt_st (dbg_halt_st), // Halt/Run status from CPU
.dbg_mem_din (dbg_mem_din), // Debug unit Memory data input
.dbg_reg_din (dbg_reg_din), // Debug unit CPU register data input
.dbg_uart_rxd (dbg_uart_rxd), // Debug interface: UART RXD
.dbg_rst (dbg_rst), // Debug unit reset
.dbg_uart_rxd (dbg_uart_rxd), // Debug interface: UART RXD (asynchronous)
.decode_noirq (decode_noirq), // Frontend decode instruction
.eu_mab (eu_mab), // Execution-Unit Memory address bus
.eu_mb_en (eu_mb_en), // Execution-Unit Memory bus enable
447,22 → 462,20
.exec_done (exec_done), // Execution completed
.fe_mb_en (fe_mb_en), // Frontend Memory bus enable
.fe_mdb_in (fe_mdb_in), // Frontend Memory data bus input
.mclk (mclk), // Main system clock
.pc (pc), // Program counter
.por (por), // Power on reset
.puc (puc) // Main system reset
);
 
`else
assign dbg_freeze = 1'b0;
assign dbg_halt_cmd = 1'b0;
assign dbg_mem_addr = 16'h0000;
assign dbg_mem_dout = 16'h0000;
assign dbg_mem_en = 1'b0;
assign dbg_mem_wr = 2'b00;
assign dbg_reg_wr = 1'b0;
assign dbg_reset = 1'b0;
assign dbg_uart_txd = 1'b0;
assign dbg_freeze = ~cpu_en_s;
assign dbg_halt_cmd = 1'b0;
assign dbg_mem_addr = 16'h0000;
assign dbg_mem_dout = 16'h0000;
assign dbg_mem_en = 1'b0;
assign dbg_mem_wr = 2'b00;
assign dbg_reg_wr = 1'b0;
assign dbg_cpu_reset = 1'b0;
assign dbg_uart_txd = 1'b0;
`endif
 
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/openMSP430_undefines.v
86,7 → 86,12
`undef DBG_HWBRK_3
`endif
 
// Let the CPU break after a PUC occurrence by default
`ifdef DBG_RST_BRK_EN
`undef DBG_RST_BRK_EN
`endif
 
 
//==========================================================================//
//==========================================================================//
//==========================================================================//
499,61 → 504,7
`undef DIVSx
`endif
 
// Timer A: TACTL Control Register
`ifdef TASSELx
`undef TASSELx
`endif
`ifdef TAIDx
`undef TAIDx
`endif
`ifdef TAMCx
`undef TAMCx
`endif
`ifdef TACLR
`undef TACLR
`endif
`ifdef TAIE
`undef TAIE
`endif
`ifdef TAIFG
`undef TAIFG
`endif
 
// Timer A: TACCTLx Capture/Compare Control Register
`ifdef TACMx
`undef TACMx
`endif
`ifdef TACCISx
`undef TACCISx
`endif
`ifdef TASCS
`undef TASCS
`endif
`ifdef TASCCI
`undef TASCCI
`endif
`ifdef TACAP
`undef TACAP
`endif
`ifdef TAOUTMODx
`undef TAOUTMODx
`endif
`ifdef TACCIE
`undef TACCIE
`endif
`ifdef TACCI
`undef TACCI
`endif
`ifdef TAOUT
`undef TAOUT
`endif
`ifdef TACOV
`undef TACOV
`endif
`ifdef TACCIFG
`undef TACCIFG
`endif
 
//
// DEBUG INTERFACE EXTRA CONFIGURATION
//======================================
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/OpenMSP430_fpga.v
235,7 → 235,7
// openMSP430 output buses
wire [7:0] per_addr;
wire [15:0] per_din;
wire [1:0] per_wen;
wire [1:0] per_we;
wire [`DMEM_MSB:0] dmem_addr;
wire [15:0] dmem_din;
wire [1:0] dmem_wen;
304,7 → 304,7
.mclk (mclk), // Main system clock
.per_addr (per_addr), // Peripheral address
.per_din (per_din), // Peripheral data input
.per_wen (per_wen), // Peripheral write enable (high active)
.per_we (per_we), // Peripheral write enable (high active)
.per_en (per_en), // Peripheral enable (high active)
.pmem_addr (pmem_addr), // Program Memory address
.pmem_cen (pmem_cen), // Program Memory chip enable (low active)
314,6 → 314,8
.smclk_en (smclk_en), // SMCLK enable
 
// INPUTs
.cpu_en (1'b1), // Enable CPU code execution (asynchronous)
.dbg_en (1'b1), // Debug interface enable (asynchronous)
.dbg_uart_rxd (dbg_uart_rxd), // Debug interface: UART RXD
.dco_clk (clk_sys), // Fast oscillator (fast clock)
.dmem_dout (dmem_dout), // Data Memory data output
379,7 → 381,7
.per_addr (per_addr), // Peripheral address
.per_din (per_din), // Peripheral data input
.per_en (per_en), // Peripheral enable (high active)
.per_wen (per_wen), // Peripheral write enable (high active)
.per_we (per_we), // Peripheral write enable (high active)
.puc (puc) // Main system reset
);
 
409,7 → 411,7
.per_addr (per_addr), // Peripheral address
.per_din (per_din), // Peripheral data input
.per_en (per_en), // Peripheral enable (high active)
.per_wen (per_wen), // Peripheral write enable (high active)
.per_we (per_we), // Peripheral write enable (high active)
.puc (puc), // Main system reset
.smclk_en (smclk_en), // SMCLK enable (from CPU)
.ta_cci0a (ta_cci0a), // Timer A capture 0 input A
442,7 → 444,7
.per_addr (per_addr), // Peripheral address
.per_din (per_din), // Peripheral data input
.per_en (per_en), // Peripheral enable (high active)
.per_wen (per_wen), // Peripheral write enable (high active)
.per_we (per_we), // Peripheral write enable (high active)
.puc (puc) // Main system reset
);
 
/openmsp430/trunk/fpga/altera_de1_board/sim/rtl_sim/src/submit.f
69,6 → 69,7
//=============================================================================
 
+incdir+../../../rtl/verilog/openmsp430/
+incdir+../../../rtl/verilog/openmsp430/periph
../../../rtl/verilog/openmsp430/openMSP430.v
../../../rtl/verilog/openmsp430/omsp_frontend.v
../../../rtl/verilog/openmsp430/omsp_execution_unit.v
/openmsp430/trunk/fpga/altera_de1_board/synthesis/altera/main.qsf
503,4 → 503,4
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_global_assignment -name VERILOG_FILE openMSP430_fpga_top.v
set_global_assignment -name CDF_FILE Chain1.cdf
set_global_assignment -name SEARCH_PATH ..\\..\\rtl\\verilog\\openmsp430/
set_global_assignment -name SEARCH_PATH "..\\..\\rtl\\verilog\\openmsp430/ ..\\..\\rtl\\verilog\\openmsp430\\periph/"
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/bench/verilog/tb_openMSP430_fpga.v
59,8 → 59,9
wire [9:0] led;
 
// UART
reg uart_rx;
wire uart_tx;
reg dbg_uart_rxd;
wire dbg_uart_txd;
reg [15:0] dbg_uart_buf;
 
// Core debug signals
wire [8*32-1:0] i_state;
85,6 → 86,9
// CPU & Memory registers
`include "registers.v"
 
// Debug interface tasks
`include "dbg_uart_tasks.v"
 
// Verilog stimulus
`include "stimulus.v"
 
144,7 → 148,7
error = 0;
stimulus_done = 1;
switch = 10'h000;
uart_rx = 1'b0;
dbg_uart_rxd = 1'b1;
end
 
//
161,13 → 165,13
.sclk_y (sclk_y), // SPI Serial Clock
.sync_n_x (sync_n_x), // SPI Frame synchronization signal (low active)
.sync_n_y (sync_n_y), // SPI Frame synchronization signal (low active)
.uart_tx (uart_tx), // Board UART TX pin
.uart_tx (dbg_uart_txd), // Board UART TX pin
 
// INPUTs
.oscclk (oscclk), // Board Oscillator (?? MHz)
.porst_n (porst_n), // Board Power-On reset (active low)
.pbrst_n (pbrst_n), // Board Push-Button reset (active low)
.uart_rx (uart_rx), // Board UART RX pin
.uart_rx (dbg_uart_rxd), // Board UART RX pin
.switch (switch) // Board Switches
);
 
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/dac_spi_if.v
56,7 → 56,7
per_addr, // Peripheral address
per_din, // Peripheral data input
per_en, // Peripheral enable (high active)
per_wen, // Peripheral write enable (high active)
per_we, // Peripheral write enable (high active)
puc // Main system reset
);
 
80,7 → 80,7
input [7:0] per_addr; // Peripheral address
input [15:0] per_din; // Peripheral data input
input per_en; // Peripheral enable (high active)
input [1:0] per_wen; // Peripheral write enable (high active)
input [1:0] per_we; // Peripheral write enable (high active)
input puc; // Main system reset
118,8 → 118,8
endcase
// Read/Write probes
wire reg_write = |per_wen & per_en;
wire reg_read = ~|per_wen & per_en;
wire reg_write = |per_we & per_en;
wire reg_read = ~|per_we & per_en;
// Read/Write vectors
wire [511:0] reg_wr = reg_dec & {512{reg_write}};
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_frontend.v
31,9 → 31,9
// - Olivier Girard, olgirard@gmail.com
//
//----------------------------------------------------------------------------
// $Rev: 103 $
// $Rev: 106 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
// $LastChangedDate: 2011-03-25 23:01:03 +0100 (Fri, 25 Mar 2011) $
//----------------------------------------------------------------------------
`ifdef OMSP_NO_INCLUDE
`else
68,6 → 68,7
pc_nxt, // Next PC value (for CALL & IRQ)
 
// INPUTs
cpu_en_s, // Enable CPU code execution (synchronous)
cpuoff, // Turns off the CPU
dbg_halt_cmd, // Halt CPU command
dbg_reg_sel, // Debug selected register for rd/wr access
111,6 → 112,7
 
// INPUTs
//=========
input cpu_en_s; // Enable CPU code execution (synchronous)
input cpuoff; // Turns off the CPU
input dbg_halt_cmd; // Halt CPU command
input [3:0] dbg_reg_sel; // Debug selected register for rd/wr access
173,17 → 175,20
parameter I_EXT2 = 3'h4; // 2nd Extension word
parameter I_IDLE = 3'h5; // CPU is in IDLE mode
 
// CPU on/off through the debug interface or cpu_en port
wire cpu_halt_cmd = dbg_halt_cmd | ~cpu_en_s;
// States Transitions
always @(i_state or inst_sz or inst_sz_nxt or pc_sw_wr or exec_done or
exec_done or irq_detect or cpuoff or dbg_halt_cmd or e_state)
exec_done or irq_detect or cpuoff or cpu_halt_cmd or e_state)
case(i_state)
I_IDLE : i_state_nxt = (irq_detect & ~dbg_halt_cmd) ? I_IRQ_FETCH :
(~cpuoff & ~dbg_halt_cmd) ? I_DEC : I_IDLE;
I_IDLE : i_state_nxt = (irq_detect & ~cpu_halt_cmd) ? I_IRQ_FETCH :
(~cpuoff & ~cpu_halt_cmd) ? I_DEC : I_IDLE;
I_IRQ_FETCH: i_state_nxt = I_IRQ_DONE;
I_IRQ_DONE : i_state_nxt = I_DEC;
I_DEC : i_state_nxt = irq_detect ? I_IRQ_FETCH :
(cpuoff | dbg_halt_cmd) & exec_done ? I_IDLE :
dbg_halt_cmd & (e_state==`E_IDLE) ? I_IDLE :
(cpuoff | cpu_halt_cmd) & exec_done ? I_IDLE :
cpu_halt_cmd & (e_state==`E_IDLE) ? I_IDLE :
pc_sw_wr ? I_DEC :
~exec_done & ~(e_state==`E_IDLE) ? I_DEC : // Wait in decode state
(inst_sz_nxt!=2'b00) ? I_EXT1 : I_DEC; // until execution is completed
208,7 → 213,7
reg dbg_halt_st;
always @(posedge mclk or posedge puc)
if (puc) dbg_halt_st <= 1'b0;
else dbg_halt_st <= dbg_halt_cmd & (i_state_nxt==I_IDLE);
else dbg_halt_st <= cpu_halt_cmd & (i_state_nxt==I_IDLE);
 
 
//=============================================================================
230,7 → 235,7
else if (exec_done) inst_irq_rst <= 1'b0;
 
// Detect other interrupts
assign irq_detect = (inst_nmi | ((|irq | wdt_irq) & gie)) & ~dbg_halt_cmd & ~dbg_halt_st & (exec_done | (i_state==I_IDLE));
assign irq_detect = (inst_nmi | ((|irq | wdt_irq) & gie)) & ~cpu_halt_cmd & ~dbg_halt_st & (exec_done | (i_state==I_IDLE));
 
// Select interrupt vector
reg [3:0] irq_num;
289,7 → 294,7
// Memory interface
wire [15:0] mab = pc_nxt;
wire mb_en = fetch | pc_sw_wr | (i_state==I_IRQ_FETCH) | pmem_busy | (dbg_halt_st & ~dbg_halt_cmd);
wire mb_en = fetch | pc_sw_wr | (i_state==I_IRQ_FETCH) | pmem_busy | (dbg_halt_st & ~cpu_halt_cmd);
 
 
//
566,12 → 571,12
endcase
else if (dest_reg==4'h0) // Addressing mode using R0
case (ir[7])
2'b1 : inst_ad_nxt = 8'b00010000;
1'b1 : inst_ad_nxt = 8'b00010000;
default: inst_ad_nxt = 8'b00000001;
endcase
else // General Addressing mode
case (ir[7])
2'b1 : inst_ad_nxt = 8'b00000010;
1'b1 : inst_ad_nxt = 8'b00000010;
default: inst_ad_nxt = 8'b00000001;
endcase
end
590,7 → 595,7
reg inst_bw;
always @(posedge mclk or posedge puc)
if (puc) inst_bw <= 1'b0;
else if (decode) inst_bw <= ir[6] & ~inst_type_nxt[`INST_JMP] & ~irq_detect & ~dbg_halt_cmd;
else if (decode) inst_bw <= ir[6] & ~inst_type_nxt[`INST_JMP] & ~irq_detect & ~cpu_halt_cmd;
 
// Extended instruction size
assign inst_sz_nxt = {1'b0, (inst_as_nxt[`IDX] | inst_as_nxt[`SYMB] | inst_as_nxt[`ABS] | inst_as_nxt[`IMM])} +
645,9 → 650,8
else if (inst_dext_rdy) exec_dext_rdy <= 1'b1;
 
// Execution first state
//wire [3:0] e_first_state = dbg_halt_cmd ? `E_IDLE :
wire [3:0] e_first_state = ~dbg_halt_st & inst_so_nxt[`IRQ] ? `E_IRQ_0 :
dbg_halt_cmd | (i_state==I_IDLE) ? `E_IDLE :
cpu_halt_cmd | (i_state==I_IDLE) ? `E_IDLE :
cpuoff ? `E_IDLE :
src_acalc_pre ? `E_SRC_AD :
src_rd_pre ? `E_SRC_RD :
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/periph/template_periph_8b.v
36,14 → 36,10
// - Olivier Girard, olgirard@gmail.com
//
//----------------------------------------------------------------------------
// $Rev: 103 $
// $Rev: 106 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
// $LastChangedDate: 2011-03-25 23:01:03 +0100 (Fri, 25 Mar 2011) $
//----------------------------------------------------------------------------
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_defines.v"
`endif
 
module template_periph_8b (
 
55,7 → 51,7
per_addr, // Peripheral address
per_din, // Peripheral data input
per_en, // Peripheral enable (high active)
per_wen, // Peripheral write enable (high active)
per_we, // Peripheral write enable (high active)
puc // Main system reset
);
 
69,7 → 65,7
input [7:0] per_addr; // Peripheral address
input [15:0] per_din; // Peripheral data input
input per_en; // Peripheral enable (high active)
input [1:0] per_wen; // Peripheral write enable (high active)
input [1:0] per_we; // Peripheral write enable (high active)
input puc; // Main system reset
 
 
107,9 → 103,9
endcase
 
// Read/Write probes
wire reg_lo_write = per_wen[0] & per_en;
wire reg_hi_write = per_wen[1] & per_en;
wire reg_read = ~|per_wen & per_en;
wire reg_lo_write = per_we[0] & per_en;
wire reg_hi_write = per_we[1] & per_en;
wire reg_read = ~|per_we & per_en;
 
// Read/Write vectors
wire [255:0] reg_hi_wr = reg_dec & {256{reg_hi_write}};
187,8 → 183,3
 
endmodule // template_periph_8b
 
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_undefines.v"
`endif
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/periph/omsp_gpio.v
31,14 → 31,10
// - Olivier Girard, olgirard@gmail.com
//
//----------------------------------------------------------------------------
// $Rev: 103 $
// $Rev: 106 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
// $LastChangedDate: 2011-03-25 23:01:03 +0100 (Fri, 25 Mar 2011) $
//----------------------------------------------------------------------------
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_defines.v"
`endif
 
module omsp_gpio (
 
76,7 → 72,7
per_addr, // Peripheral address
per_din, // Peripheral data input
per_en, // Peripheral enable (high active)
per_wen, // Peripheral write enable (high active)
per_we, // Peripheral write enable (high active)
puc // Main system reset
);
 
126,7 → 122,7
input [7:0] per_addr; // Peripheral address
input [15:0] per_din; // Peripheral data input
input per_en; // Peripheral enable (high active)
input [1:0] per_wen; // Peripheral write enable (high active)
input [1:0] per_we; // Peripheral write enable (high active)
input puc; // Main system reset
 
 
250,9 → 246,9
endcase
 
// Read/Write probes
wire reg_lo_write = per_wen[0] & per_en;
wire reg_hi_write = per_wen[1] & per_en;
wire reg_read = ~|per_wen & per_en;
wire reg_lo_write = per_we[0] & per_en;
wire reg_hi_write = per_we[1] & per_en;
wire reg_read = ~|per_we & per_en;
 
// Read/Write vectors
wire [255:0] reg_hi_wr = reg_dec & {256{reg_hi_write}};
826,8 → 822,3
p6sel_rd;
 
endmodule // omsp_gpio
 
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_undefines.v"
`endif
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/periph/omsp_timerA_defines.v
0,0 → 1,79
//----------------------------------------------------------------------------
// Copyright (C) 2001 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
//
//----------------------------------------------------------------------------
//
// *File Name: omsp_timerA_defines.v
//
// *Module Description:
// omsp_timerA Configuration file
//
// *Author(s):
// - Olivier Girard, olgirard@gmail.com
//
//----------------------------------------------------------------------------
// $Rev: 103 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
//----------------------------------------------------------------------------
//`define OMSP_TA_NO_INCLUDE
`ifdef OMSP_TA_NO_INCLUDE
`else
`include "omsp_timerA_undefines.v"
`endif
 
//----------------------------------------------------------------------------
// TIMER A CONFIGURATION
//----------------------------------------------------------------------------
 
 
 
//==========================================================================//
//==========================================================================//
//==========================================================================//
//==========================================================================//
//===== SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!! =====//
//==========================================================================//
//==========================================================================//
//==========================================================================//
//==========================================================================//
 
// Timer A: TACTL Control Register
`define TASSELx 9:8
`define TAIDx 7:6
`define TAMCx 5:4
`define TACLR 2
`define TAIE 1
`define TAIFG 0
 
// Timer A: TACCTLx Capture/Compare Control Register
`define TACMx 15:14
`define TACCISx 13:12
`define TASCS 11
`define TASCCI 10
`define TACAP 8
`define TAOUTMODx 7:5
`define TACCIE 4
`define TACCI 3
`define TAOUT 2
`define TACOV 1
`define TACCIFG 0
openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/periph/omsp_timerA_defines.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/periph/omsp_timerA.v =================================================================== --- openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/periph/omsp_timerA.v (revision 106) +++ openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/periph/omsp_timerA.v (revision 107) @@ -31,13 +31,13 @@ // - Olivier Girard, olgirard@gmail.com // //---------------------------------------------------------------------------- -// $Rev: 103 $ +// $Rev: 106 $ // $LastChangedBy: olivier.girard $ -// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $ +// $LastChangedDate: 2011-03-25 23:01:03 +0100 (Fri, 25 Mar 2011) $ //---------------------------------------------------------------------------- -`ifdef OMSP_NO_INCLUDE +`ifdef OMSP_TA_NO_INCLUDE `else -`include "openMSP430_defines.v" +`include "omsp_timerA_defines.v" `endif module omsp_timerA ( @@ -62,7 +62,7 @@ per_addr, // Peripheral address per_din, // Peripheral data input per_en, // Peripheral enable (high active) - per_wen, // Peripheral write enable (high active) + per_we, // Peripheral write enable (high active) puc, // Main system reset smclk_en, // SMCLK enable (from CPU) ta_cci0a, // Timer A capture 0 input A @@ -96,7 +96,7 @@ input [7:0] per_addr; // Peripheral address input [15:0] per_din; // Peripheral data input input per_en; // Peripheral enable (high active) -input [1:0] per_wen; // Peripheral write enable (high active) +input [1:0] per_we; // Peripheral write enable (high active) input puc; // Main system reset input smclk_en; // SMCLK enable (from CPU) input ta_cci0a; // Timer A capture 0 input A @@ -157,8 +157,8 @@ endcase // Read/Write probes -wire reg_write = |per_wen & per_en; -wire reg_read = ~|per_wen & per_en; +wire reg_write = |per_we & per_en; +wire reg_read = ~|per_we & per_en; // Read/Write vectors wire [511:0] reg_wr = reg_dec & {512{reg_write}}; @@ -688,7 +688,7 @@ endmodule // omsp_timerA -`ifdef OMSP_NO_INCLUDE +`ifdef OMSP_TA_NO_INCLUDE `else -`include "openMSP430_undefines.v" +`include "omsp_timerA_undefines.v" `endif
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/periph/omsp_timerA_undefines.v
0,0 → 1,108
//----------------------------------------------------------------------------
// Copyright (C) 2001 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
//
//----------------------------------------------------------------------------
//
// *File Name: omsp_timerA_undefines.v
//
// *Module Description:
// omsp_timerA Verilog `undef file
//
// *Author(s):
// - Olivier Girard, olgirard@gmail.com
//
//----------------------------------------------------------------------------
// $Rev: 23 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $
//----------------------------------------------------------------------------
 
//----------------------------------------------------------------------------
// SYSTEM CONFIGURATION
//----------------------------------------------------------------------------
 
 
 
//==========================================================================//
//==========================================================================//
//==========================================================================//
//==========================================================================//
//===== SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!! =====//
//==========================================================================//
//==========================================================================//
//==========================================================================//
//==========================================================================//
 
// Timer A: TACTL Control Register
`ifdef TASSELx
`undef TASSELx
`endif
`ifdef TAIDx
`undef TAIDx
`endif
`ifdef TAMCx
`undef TAMCx
`endif
`ifdef TACLR
`undef TACLR
`endif
`ifdef TAIE
`undef TAIE
`endif
`ifdef TAIFG
`undef TAIFG
`endif
 
// Timer A: TACCTLx Capture/Compare Control Register
`ifdef TACMx
`undef TACMx
`endif
`ifdef TACCISx
`undef TACCISx
`endif
`ifdef TASCS
`undef TASCS
`endif
`ifdef TASCCI
`undef TASCCI
`endif
`ifdef TACAP
`undef TACAP
`endif
`ifdef TAOUTMODx
`undef TAOUTMODx
`endif
`ifdef TACCIE
`undef TACCIE
`endif
`ifdef TACCI
`undef TACCI
`endif
`ifdef TAOUT
`undef TAOUT
`endif
`ifdef TACOV
`undef TACOV
`endif
`ifdef TACCIFG
`undef TACCIFG
`endif
openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/periph/omsp_timerA_undefines.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/periph/template_periph_16b.v =================================================================== --- openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/periph/template_periph_16b.v (revision 106) +++ openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/periph/template_periph_16b.v (revision 107) @@ -36,14 +36,10 @@ // - Olivier Girard, olgirard@gmail.com // //---------------------------------------------------------------------------- -// $Rev: 103 $ +// $Rev: 106 $ // $LastChangedBy: olivier.girard $ -// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $ +// $LastChangedDate: 2011-03-25 23:01:03 +0100 (Fri, 25 Mar 2011) $ //---------------------------------------------------------------------------- -`ifdef OMSP_NO_INCLUDE -`else -`include "openMSP430_defines.v" -`endif module template_periph_16b ( @@ -55,7 +51,7 @@ per_addr, // Peripheral address per_din, // Peripheral data input per_en, // Peripheral enable (high active) - per_wen, // Peripheral write enable (high active) + per_we, // Peripheral write enable (high active) puc // Main system reset ); @@ -69,7 +65,7 @@ input [7:0] per_addr; // Peripheral address input [15:0] per_din; // Peripheral data input input per_en; // Peripheral enable (high active) -input [1:0] per_wen; // Peripheral write enable (high active) +input [1:0] per_we; // Peripheral write enable (high active) input puc; // Main system reset @@ -107,8 +103,8 @@ endcase // Read/Write probes -wire reg_write = |per_wen & per_en; -wire reg_read = ~|per_wen & per_en; +wire reg_write = |per_we & per_en; +wire reg_read = ~|per_we & per_en; // Read/Write vectors wire [511:0] reg_wr = reg_dec & {512{reg_write}}; @@ -180,8 +176,3 @@ endmodule // template_periph_16b - -`ifdef OMSP_NO_INCLUDE -`else -`include "openMSP430_undefines.v" -`endif
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_multiplier.v
51,7 → 51,7
per_addr, // Peripheral address
per_din, // Peripheral data input
per_en, // Peripheral enable (high active)
per_wen, // Peripheral write enable (high active)
per_we, // Peripheral write enable (high active)
puc // Main system reset
);
 
65,7 → 65,7
input [7:0] per_addr; // Peripheral address
input [15:0] per_din; // Peripheral data input
input per_en; // Peripheral enable (high active)
input [1:0] per_wen; // Peripheral write enable (high active)
input [1:0] per_we; // Peripheral write enable (high active)
input puc; // Main system reset
 
 
121,8 → 121,8
endcase
 
// Read/Write probes
wire reg_write = |per_wen & per_en;
wire reg_read = ~|per_wen & per_en;
wire reg_write = |per_we & per_en;
wire reg_read = ~|per_we & per_en;
 
// Read/Write vectors
wire [511:0] reg_wr = reg_dec & {512{reg_write}};
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_dbg_uart.v
31,9 → 31,9
// - Olivier Girard, olgirard@gmail.com
//
//----------------------------------------------------------------------------
// $Rev: 103 $
// $Rev: 106 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
// $LastChangedDate: 2011-03-25 23:01:03 +0100 (Fri, 25 Mar 2011) $
//----------------------------------------------------------------------------
`ifdef OMSP_NO_INCLUDE
`else
50,16 → 50,16
dbg_wr, // Debug register data write
// INPUTs
dbg_clk, // Debug unit clock
dbg_dout, // Debug register data output
dbg_rd_rdy, // Debug register data is ready for read
dbg_rst, // Debug unit reset
dbg_uart_rxd, // Debug interface: UART RXD
mclk, // Main system clock
mem_burst, // Burst on going
mem_burst_end, // End TX/RX burst
mem_burst_rd, // Start TX burst
mem_burst_wr, // Start RX burst
mem_bw, // Burst byte width
por // Power on reset
mem_bw // Burst byte width
);
 
// OUTPUTs
72,16 → 72,16
 
// INPUTs
//=========
input dbg_clk; // Debug unit clock
input [15:0] dbg_dout; // Debug register data output
input dbg_rd_rdy; // Debug register data is ready for read
input dbg_rst; // Debug unit reset
input dbg_uart_rxd; // Debug interface: UART RXD
input mclk; // Main system clock
input mem_burst; // Burst on going
input mem_burst_end; // End TX/RX burst
input mem_burst_rd; // Start TX burst
input mem_burst_wr; // Start RX burst
input mem_bw; // Burst byte width
input por; // Power on reset
 
 
//=============================================================================
91,9 → 91,9
// Synchronize RXD input & buffer
//--------------------------------
reg [3:0] rxd_sync;
always @ (posedge mclk or posedge por)
if (por) rxd_sync <= 4'hf;
else rxd_sync <= {rxd_sync[2:0], dbg_uart_rxd};
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) rxd_sync <= 4'hf;
else rxd_sync <= {rxd_sync[2:0], dbg_uart_rxd};
 
// Majority decision
//------------------------
104,9 → 104,9
{1'b0, rxd_sync[3]};
wire rxd_maj_nxt = (rxd_maj_cnt>=2'b10);
always @ (posedge mclk or posedge por)
if (por) rxd_maj <= 1'b0;
else rxd_maj <= rxd_maj_nxt;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) rxd_maj <= 1'b0;
else rxd_maj <= rxd_maj_nxt;
 
wire rxd_s = rxd_maj;
wire rxd_fe = rxd_maj & ~rxd_maj_nxt;
157,8 → 157,8
endcase
// State machine
always @(posedge mclk or posedge por)
if (por) uart_state <= RX_SYNC;
always @(posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) uart_state <= RX_SYNC;
else if (xfer_done | sync_done |
mem_burst_wr | mem_burst_rd) uart_state <= uart_state_nxt;
 
170,13 → 170,13
//=============================================================================
// 3) UART SYNCHRONIZATION
//=============================================================================
// After POR, the host needs to fist send a synchronization character (0x80)
// After DBG_RST, the host needs to fist send a synchronization character (0x80)
// If this feature doesn't work properly, it is possible to disable it by
// commenting the DBG_UART_AUTO_SYNC define in the openMSP430.inc file.
 
reg sync_busy;
always @ (posedge mclk or posedge por)
if (por) sync_busy <= 1'b0;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) sync_busy <= 1'b0;
else if ((uart_state==RX_SYNC) & rxd_fe) sync_busy <= 1'b1;
else if ((uart_state==RX_SYNC) & rxd_re) sync_busy <= 1'b0;
 
185,8 → 185,8
`ifdef DBG_UART_AUTO_SYNC
 
reg [`DBG_UART_XFER_CNT_W+2:0] sync_cnt;
always @ (posedge mclk or posedge por)
if (por) sync_cnt <= {{`DBG_UART_XFER_CNT_W{1'b1}}, 3'b000};
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) sync_cnt <= {{`DBG_UART_XFER_CNT_W{1'b1}}, 3'b000};
else if (sync_busy) sync_cnt <= sync_cnt+{{`DBG_UART_XFER_CNT_W+2{1'b0}}, 1'b1};
 
wire [`DBG_UART_XFER_CNT_W-1:0] bit_cnt_max = sync_cnt[`DBG_UART_XFER_CNT_W+2:3];
209,14 → 209,14
wire xfer_bit_inc = (xfer_bit!=4'h0) & (xfer_cnt=={`DBG_UART_XFER_CNT_W{1'b0}});
assign xfer_done = (xfer_bit==4'hb);
always @ (posedge mclk or posedge por)
if (por) xfer_bit <= 4'h0;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) xfer_bit <= 4'h0;
else if (txd_start | rxd_start) xfer_bit <= 4'h1;
else if (xfer_done) xfer_bit <= 4'h0;
else if (xfer_bit_inc) xfer_bit <= xfer_bit+4'h1;
 
always @ (posedge mclk or posedge por)
if (por) xfer_cnt <= {`DBG_UART_XFER_CNT_W{1'b0}};
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) xfer_cnt <= {`DBG_UART_XFER_CNT_W{1'b0}};
else if (rxd_start) xfer_cnt <= {1'b0, bit_cnt_max[`DBG_UART_XFER_CNT_W-1:1]};
else if (txd_start | xfer_bit_inc) xfer_cnt <= bit_cnt_max;
else xfer_cnt <= xfer_cnt+{`DBG_UART_XFER_CNT_W{1'b1}};
226,8 → 226,8
//-------------------------
wire [19:0] xfer_buf_nxt = {rxd_s, xfer_buf[19:1]};
 
always @ (posedge mclk or posedge por)
if (por) xfer_buf <= 20'h00000;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) xfer_buf <= 20'h00000;
else if (dbg_rd_rdy) xfer_buf <= {1'b1, dbg_dout[15:8], 2'b01, dbg_dout[7:0], 1'b0};
else if (xfer_bit_inc) xfer_buf <= xfer_buf_nxt;
 
236,8 → 236,8
//------------------------
reg dbg_uart_txd;
always @ (posedge mclk or posedge por)
if (por) dbg_uart_txd <= 1'b1;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) dbg_uart_txd <= 1'b1;
else if (xfer_bit_inc & tx_active) dbg_uart_txd <= xfer_buf[0];
 
246,13 → 246,13
//=============================================================================
 
reg [5:0] dbg_addr;
always @ (posedge mclk or posedge por)
if (por) dbg_addr <= 6'h00;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) dbg_addr <= 6'h00;
else if (cmd_valid) dbg_addr <= xfer_buf[`DBG_UART_ADDR];
 
reg dbg_bw;
always @ (posedge mclk or posedge por)
if (por) dbg_bw <= 1'b0;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) dbg_bw <= 1'b0;
else if (cmd_valid) dbg_bw <= xfer_buf[`DBG_UART_BW];
 
wire dbg_din_bw = mem_burst ? mem_bw : dbg_bw;
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_dbg_hwbrk.v
31,9 → 31,9
// - Olivier Girard, olgirard@gmail.com
//
//----------------------------------------------------------------------------
// $Rev: 103 $
// $Rev: 106 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
// $LastChangedDate: 2011-03-25 23:01:03 +0100 (Fri, 25 Mar 2011) $
//----------------------------------------------------------------------------
`ifdef OMSP_NO_INCLUDE
`else
50,7 → 50,9
// INPUTs
brk_reg_rd, // Hardware break/watch-point register read select
brk_reg_wr, // Hardware break/watch-point register write select
dbg_clk, // Debug unit clock
dbg_din, // Debug register data input
dbg_rst, // Debug unit reset
eu_mab, // Execution-Unit Memory address bus
eu_mb_en, // Execution-Unit Memory bus enable
eu_mb_wr, // Execution-Unit Memory bus write transfer
58,9 → 60,7
eu_mdb_out, // Memory data bus output
exec_done, // Execution completed
fe_mb_en, // Frontend Memory bus enable
mclk, // Main system clock
pc, // Program counter
por // Power on reset
pc // Program counter
);
 
// OUTPUTs
73,7 → 73,9
//=========
input [3:0] brk_reg_rd; // Hardware break/watch-point register read select
input [3:0] brk_reg_wr; // Hardware break/watch-point register write select
input dbg_clk; // Debug unit clock
input [15:0] dbg_din; // Debug register data input
input dbg_rst; // Debug unit reset
input [15:0] eu_mab; // Execution-Unit Memory address bus
input eu_mb_en; // Execution-Unit Memory bus enable
input [1:0] eu_mb_wr; // Execution-Unit Memory bus write transfer
81,9 → 83,7
input [15:0] eu_mdb_out; // Memory data bus output
input exec_done; // Execution completed
input fe_mb_en; // Frontend Memory bus enable
input mclk; // Main system clock
input [15:0] pc; // Program counter
input por; // Power on reset
 
 
//=============================================================================
133,8 → 133,8
 
wire brk_ctl_wr = brk_reg_wr[BRK_CTL];
always @ (posedge mclk or posedge por)
if (por) brk_ctl <= 5'h00;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) brk_ctl <= 5'h00;
else if (brk_ctl_wr) brk_ctl <= {`HWBRK_RANGE & dbg_din[4], dbg_din[3:0]};
 
wire [7:0] brk_ctl_full = {3'b000, brk_ctl};
154,8 → 154,8
addr0_wr_set, addr0_rd_set};
wire [5:0] brk_stat_clr = ~dbg_din[5:0];
 
always @ (posedge mclk or posedge por)
if (por) brk_stat <= 6'h00;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) brk_stat <= 6'h00;
else if (brk_stat_wr) brk_stat <= ((brk_stat & brk_stat_clr) | brk_stat_set);
else brk_stat <= (brk_stat | brk_stat_set);
 
169,8 → 169,8
 
wire brk_addr0_wr = brk_reg_wr[BRK_ADDR0];
always @ (posedge mclk or posedge por)
if (por) brk_addr0 <= 16'h0000;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) brk_addr0 <= 16'h0000;
else if (brk_addr0_wr) brk_addr0 <= dbg_din;
 
180,8 → 180,8
 
wire brk_addr1_wr = brk_reg_wr[BRK_ADDR1];
always @ (posedge mclk or posedge por)
if (por) brk_addr1 <= 16'h0000;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) brk_addr1 <= 16'h0000;
else if (brk_addr1_wr) brk_addr1 <= dbg_din;
 
215,9 → 215,9
brk_ctl[`BRK_RANGE] & `HWBRK_RANGE;
 
reg fe_mb_en_buf;
always @ (posedge mclk or posedge por)
if (por) fe_mb_en_buf <= 1'b0;
else fe_mb_en_buf <= fe_mb_en;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) fe_mb_en_buf <= 1'b0;
else fe_mb_en_buf <= fe_mb_en;
 
wire equ_i_addr0 = fe_mb_en_buf & (pc==brk_addr0) & ~brk_ctl[`BRK_RANGE];
wire equ_i_addr1 = fe_mb_en_buf & (pc==brk_addr1) & ~brk_ctl[`BRK_RANGE];
244,8 → 244,8
// In general, We should here make sure no write access occures during the
// same instruction cycle before setting the read flag.
reg [2:0] d_rd_trig;
always @ (posedge mclk or posedge por)
if (por) d_rd_trig <= 3'h0;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) d_rd_trig <= 3'h0;
else if (exec_done) d_rd_trig <= 3'h0;
else d_rd_trig <= {equ_d_range & ~brk_ctl[`BRK_I_EN] & ~|eu_mb_wr,
equ_d_addr1 & ~brk_ctl[`BRK_I_EN] & ~|eu_mb_wr,
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_sfr.v
31,9 → 31,9
// - Olivier Girard, olgirard@gmail.com
//
//----------------------------------------------------------------------------
// $Rev: 103 $
// $Rev: 106 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
// $LastChangedDate: 2011-03-25 23:01:03 +0100 (Fri, 25 Mar 2011) $
//----------------------------------------------------------------------------
`ifdef OMSP_NO_INCLUDE
`else
55,7 → 55,7
per_addr, // Peripheral address
per_din, // Peripheral data input
per_en, // Peripheral enable (high active)
per_wen, // Peripheral write enable (high active)
per_we, // Peripheral write enable (high active)
por, // Power-on reset
puc, // Main system reset
wdtifg_clr, // Clear Watchdog-timer interrupt flag
79,7 → 79,7
input [7:0] per_addr; // Peripheral address
input [15:0] per_din; // Peripheral data input
input per_en; // Peripheral enable (high active)
input [1:0] per_wen; // Peripheral write enable (high active)
input [1:0] per_we; // Peripheral write enable (high active)
input por; // Power-on reset
input puc; // Main system reset
input wdtifg_clr; // Clear Watchdog-timer interrupt flag
115,9 → 115,9
endcase
 
// Read/Write probes
wire reg_lo_write = per_wen[0] & per_en;
wire reg_hi_write = per_wen[1] & per_en;
wire reg_read = ~|per_wen & per_en;
wire reg_lo_write = per_we[0] & per_en;
wire reg_hi_write = per_we[1] & per_en;
wire reg_read = ~|per_we & per_en;
 
// Read/Write vectors
wire [255:0] reg_hi_wr = reg_dec & {256{reg_hi_write}};
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_dbg.v
31,9 → 31,9
// - Olivier Girard, olgirard@gmail.com
//
//----------------------------------------------------------------------------
// $Rev: 103 $
// $Rev: 106 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
// $LastChangedDate: 2011-03-25 23:01:03 +0100 (Fri, 25 Mar 2011) $
//----------------------------------------------------------------------------
`ifdef OMSP_NO_INCLUDE
`else
50,14 → 50,18
dbg_mem_en, // Debug unit memory enable
dbg_mem_wr, // Debug unit memory write
dbg_reg_wr, // Debug unit CPU register write
dbg_reset, // Reset CPU from debug interface
dbg_cpu_reset, // Reset CPU from debug interface
dbg_uart_txd, // Debug interface: UART TXD
// INPUTs
cpu_en_s, // Enable CPU code execution (synchronous)
dbg_clk, // Debug unit clock
dbg_en_s, // Debug interface enable (synchronous)
dbg_halt_st, // Halt/Run status from CPU
dbg_mem_din, // Debug unit Memory data input
dbg_reg_din, // Debug unit CPU register data input
dbg_uart_rxd, // Debug interface: UART RXD
dbg_rst, // Debug unit reset
dbg_uart_rxd, // Debug interface: UART RXD (asynchronous)
decode_noirq, // Frontend decode instruction
eu_mab, // Execution-Unit Memory address bus
eu_mb_en, // Execution-Unit Memory bus enable
67,9 → 71,7
exec_done, // Execution completed
fe_mb_en, // Frontend Memory bus enable
fe_mdb_in, // Frontend Memory data bus input
mclk, // Main system clock
pc, // Program counter
por, // Power on reset
puc // Main system reset
);
 
82,15 → 84,19
output dbg_mem_en; // Debug unit memory enable
output [1:0] dbg_mem_wr; // Debug unit memory write
output dbg_reg_wr; // Debug unit CPU register write
output dbg_reset; // Reset CPU from debug interface
output dbg_cpu_reset; // Reset CPU from debug interface
output dbg_uart_txd; // Debug interface: UART TXD
 
// INPUTs
//=========
input cpu_en_s; // Enable CPU code execution (synchronous)
input dbg_clk; // Debug unit clock
input dbg_en_s; // Debug interface enable (synchronous)
input dbg_halt_st; // Halt/Run status from CPU
input [15:0] dbg_mem_din; // Debug unit Memory data input
input [15:0] dbg_reg_din; // Debug unit CPU register data input
input dbg_uart_rxd; // Debug interface: UART RXD
input dbg_rst; // Debug unit reset
input dbg_uart_rxd; // Debug interface: UART RXD (asynchronous)
input decode_noirq; // Frontend decode instruction
input [15:0] eu_mab; // Execution-Unit Memory address bus
input eu_mb_en; // Execution-Unit Memory bus enable
100,9 → 106,7
input exec_done; // Execution completed
input fe_mb_en; // Frontend Memory bus enable
input [15:0] fe_mdb_in; // Frontend Memory data bus input
input mclk; // Main system clock
input [15:0] pc; // Program counter
input por; // Power on reset
input puc; // Main system reset
 
 
206,10 → 210,10
 
// PUC is localy used as a data.
reg [1:0] puc_sync;
always @ (posedge mclk or posedge por)
if (por) puc_sync <= 2'b11;
else puc_sync <= {puc_sync[0] , puc};
wire puc_s = puc_sync[1];
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) puc_sync <= 2'b11;
else puc_sync <= {puc_sync[0] , puc};
wire puc_s = puc_sync[1];
 
 
//============================================================================
288,8 → 292,12
 
wire cpu_ctl_wr = reg_wr[CPU_CTL];
always @ (posedge mclk or posedge por)
if (por) cpu_ctl <= 4'h0;
always @ (posedge dbg_clk or posedge dbg_rst)
`ifdef DBG_RST_BRK_EN
if (dbg_rst) cpu_ctl <= 4'h4;
`else
if (dbg_rst) cpu_ctl <= 4'h0;
`endif
else if (cpu_ctl_wr) cpu_ctl <= dbg_din[6:3];
 
wire [7:0] cpu_ctl_full = {1'b0, cpu_ctl, 3'b000};
310,8 → 318,8
wire [3:2] cpu_stat_set = {dbg_swbrk, puc_s};
wire [3:2] cpu_stat_clr = ~dbg_din[3:2];
 
always @ (posedge mclk or posedge por)
if (por) cpu_stat <= 2'b00;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) cpu_stat <= 2'b00;
else if (cpu_stat_wr) cpu_stat <= ((cpu_stat & cpu_stat_clr) | cpu_stat_set);
else cpu_stat <= (cpu_stat | cpu_stat_set);
 
345,16 → 353,16
 
wire mem_ctl_wr = reg_wr[MEM_CTL];
always @ (posedge mclk or posedge por)
if (por) mem_ctl <= 3'h0;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) mem_ctl <= 3'h0;
else if (mem_ctl_wr) mem_ctl <= dbg_din[3:1];
 
wire [7:0] mem_ctl_full = {4'b0000, mem_ctl, 1'b0};
 
reg mem_start;
always @ (posedge mclk or posedge por)
if (por) mem_start <= 1'b0;
else mem_start <= mem_ctl_wr & dbg_din[0];
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) mem_start <= 1'b0;
else mem_start <= mem_ctl_wr & dbg_din[0];
 
wire mem_bw = mem_ctl[3];
370,8 → 378,8
mem_addr[0] ? {8'h00, dbg_mem_din[15:8]} :
{8'h00, dbg_mem_din[7:0]};
always @ (posedge mclk or posedge por)
if (por) mem_data <= 16'h0000;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) mem_data <= 16'h0000;
else if (mem_data_wr) mem_data <= dbg_din;
else if (dbg_reg_rd) mem_data <= dbg_reg_din;
else if (dbg_mem_rd_dly) mem_data <= dbg_mem_din_bw;
389,8 → 397,8
(dbg_mem_acc & ~mem_bw) ? 16'h0002 :
(dbg_mem_acc | dbg_reg_acc) ? 16'h0001 : 16'h0000;
always @ (posedge mclk or posedge por)
if (por) mem_addr <= 16'h0000;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) mem_addr <= 16'h0000;
else if (mem_addr_wr) mem_addr <= dbg_din;
else mem_addr <= mem_addr + mem_addr_inc;
402,8 → 410,8
wire [15:0] mem_cnt_dec = (mem_cnt==16'h0000) ? 16'h0000 :
(dbg_mem_acc | dbg_reg_acc) ? 16'hffff : 16'h0000;
always @ (posedge mclk or posedge por)
if (por) mem_cnt <= 16'h0000;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) mem_cnt <= 16'h0000;
else if (mem_cnt_wr) mem_cnt <= dbg_din;
else mem_cnt <= mem_cnt + mem_cnt_dec;
 
435,7 → 443,9
// INPUTs
.brk_reg_rd (brk0_reg_rd), // Hardware break/watch-point register read select
.brk_reg_wr (brk0_reg_wr), // Hardware break/watch-point register write select
.dbg_clk (dbg_clk), // Debug unit clock
.dbg_din (dbg_din), // Debug register data input
.dbg_rst (dbg_rst), // Debug unit reset
.eu_mab (eu_mab), // Execution-Unit Memory address bus
.eu_mb_en (eu_mb_en), // Execution-Unit Memory bus enable
.eu_mb_wr (eu_mb_wr), // Execution-Unit Memory bus write transfer
443,9 → 453,7
.eu_mdb_out (eu_mdb_out), // Memory data bus output
.exec_done (exec_done), // Execution completed
.fe_mb_en (fe_mb_en), // Frontend Memory bus enable
.mclk (mclk), // Main system clock
.pc (pc), // Program counter
.por (por) // Power on reset
.pc (pc) // Program counter
);
 
`else
477,7 → 485,9
// INPUTs
.brk_reg_rd (brk1_reg_rd), // Hardware break/watch-point register read select
.brk_reg_wr (brk1_reg_wr), // Hardware break/watch-point register write select
.dbg_clk (dbg_clk), // Debug unit clock
.dbg_din (dbg_din), // Debug register data input
.dbg_rst (dbg_rst), // Debug unit reset
.eu_mab (eu_mab), // Execution-Unit Memory address bus
.eu_mb_en (eu_mb_en), // Execution-Unit Memory bus enable
.eu_mb_wr (eu_mb_wr), // Execution-Unit Memory bus write transfer
485,9 → 495,7
.eu_mdb_out (eu_mdb_out), // Memory data bus output
.exec_done (exec_done), // Execution completed
.fe_mb_en (fe_mb_en), // Frontend Memory bus enable
.mclk (mclk), // Main system clock
.pc (pc), // Program counter
.por (por) // Power on reset
.pc (pc) // Program counter
);
 
`else
519,7 → 527,9
// INPUTs
.brk_reg_rd (brk2_reg_rd), // Hardware break/watch-point register read select
.brk_reg_wr (brk2_reg_wr), // Hardware break/watch-point register write select
.dbg_clk (dbg_clk), // Debug unit clock
.dbg_din (dbg_din), // Debug register data input
.dbg_rst (dbg_rst), // Debug unit reset
.eu_mab (eu_mab), // Execution-Unit Memory address bus
.eu_mb_en (eu_mb_en), // Execution-Unit Memory bus enable
.eu_mb_wr (eu_mb_wr), // Execution-Unit Memory bus write transfer
527,9 → 537,7
.eu_mdb_out (eu_mdb_out), // Memory data bus output
.exec_done (exec_done), // Execution completed
.fe_mb_en (fe_mb_en), // Frontend Memory bus enable
.mclk (mclk), // Main system clock
.pc (pc), // Program counter
.por (por) // Power on reset
.pc (pc) // Program counter
);
 
`else
561,7 → 569,9
// INPUTs
.brk_reg_rd (brk3_reg_rd), // Hardware break/watch-point register read select
.brk_reg_wr (brk3_reg_wr), // Hardware break/watch-point register write select
.dbg_clk (dbg_clk), // Debug unit clock
.dbg_din (dbg_din), // Debug register data input
.dbg_rst (dbg_rst), // Debug unit reset
.eu_mab (eu_mab), // Execution-Unit Memory address bus
.eu_mb_en (eu_mb_en), // Execution-Unit Memory bus enable
.eu_mb_wr (eu_mb_wr), // Execution-Unit Memory bus write transfer
569,9 → 579,7
.eu_mdb_out (eu_mdb_out), // Memory data bus output
.exec_done (exec_done), // Execution completed
.fe_mb_en (fe_mb_en), // Frontend Memory bus enable
.mclk (mclk), // Main system clock
.pc (pc), // Program counter
.por (por) // Power on reset
.pc (pc) // Program counter
);
 
`else
608,8 → 616,8
brk3_dout;
 
// Tell UART/JTAG interface that the data is ready to be read
always @ (posedge mclk or posedge por)
if (por) dbg_rd_rdy <= 1'b0;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) dbg_rd_rdy <= 1'b0;
else if (mem_burst | mem_burst_rd) dbg_rd_rdy <= (dbg_reg_rd | dbg_mem_rd_dly);
else dbg_rd_rdy <= dbg_rd;
 
620,19 → 628,19
 
// Reset CPU
//--------------------------
wire dbg_reset = cpu_ctl[`CPU_RST];
wire dbg_cpu_reset = cpu_ctl[`CPU_RST];
 
// Break after reset
//--------------------------
wire halt_rst = cpu_ctl[`RST_BRK_EN] & puc_s;
wire halt_rst = cpu_ctl[`RST_BRK_EN] & dbg_en_s & puc_s;
 
// Freeze peripherals
//--------------------------
wire dbg_freeze = dbg_halt_st & cpu_ctl[`FRZ_BRK_EN];
wire dbg_freeze = dbg_halt_st & (cpu_ctl[`FRZ_BRK_EN] | ~cpu_en_s);
 
 
// Software break
//--------------------------
assign dbg_swbrk = (fe_mdb_in==`DBG_SWBRK_OP) & decode_noirq & cpu_ctl[`SW_BRK_EN];
641,8 → 649,8
// Single step
//--------------------------
reg [1:0] inc_step;
always @(posedge mclk or posedge por)
if (por) inc_step <= 2'b00;
always @(posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) inc_step <= 2'b00;
else if (istep) inc_step <= 2'b11;
else inc_step <= {inc_step[0], 1'b0};
 
658,8 → 666,8
wire halt_flag_set = halt_cpu | halt_rst | dbg_swbrk | mem_halt_cpu |
brk0_halt | brk1_halt | brk2_halt | brk3_halt;
 
always @(posedge mclk or posedge por)
if (por) halt_flag <= 1'b0;
always @(posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) halt_flag <= 1'b0;
else if (halt_flag_clr) halt_flag <= 1'b0;
else if (halt_flag_set) halt_flag <= 1'b1;
 
677,8 → 685,8
wire mem_burst_end = ((dbg_wr | dbg_rd_rdy) & ~|mem_cnt);
 
// Detect when burst is on going
always @(posedge mclk or posedge por)
if (por) mem_burst <= 1'b0;
always @(posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) mem_burst <= 1'b0;
else if (mem_burst_start) mem_burst <= 1'b1;
else if (mem_burst_end) mem_burst <= 1'b0;
 
688,9 → 696,9
 
// Trigger CPU Register or memory access during a burst
reg mem_startb;
always @(posedge mclk or posedge por)
if (por) mem_startb <= 1'b0;
else mem_startb <= (mem_burst & (dbg_wr | dbg_rd)) | mem_burst_rd;
always @(posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) mem_startb <= 1'b0;
else mem_startb <= (mem_burst & (dbg_wr | dbg_rd)) | mem_burst_rd;
 
// Combine single and burst memory start of sequence
wire mem_seq_start = ((mem_start & ~|mem_cnt) | mem_startb);
719,9 → 727,9
endcase
 
// State machine
always @(posedge mclk or posedge por)
if (por) mem_state <= M_IDLE;
else mem_state <= mem_state_nxt;
always @(posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) mem_state <= M_IDLE;
else mem_state <= mem_state_nxt;
 
// Utility signals
assign mem_halt_cpu = (mem_state==M_IDLE) & (mem_state_nxt==M_SET_BRK);
748,9 → 756,9
 
 
// It takes one additional cycle to read from Memory as from registers
always @(posedge mclk or posedge por)
if (por) dbg_mem_rd_dly <= 1'b0;
else dbg_mem_rd_dly <= dbg_mem_rd;
always @(posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) dbg_mem_rd_dly <= 1'b0;
else dbg_mem_rd_dly <= dbg_mem_rd;
 
//=============================================================================
767,16 → 775,16
.dbg_wr (dbg_wr), // Debug register data write
// INPUTs
.dbg_clk (dbg_clk), // Debug unit clock
.dbg_dout (dbg_dout), // Debug register data output
.dbg_rd_rdy (dbg_rd_rdy), // Debug register data is ready for read
.dbg_rst (dbg_rst), // Debug unit reset
.dbg_uart_rxd (dbg_uart_rxd), // Debug interface: UART RXD
.mclk (mclk), // Main system clock
.mem_burst (mem_burst), // Burst on going
.mem_burst_end(mem_burst_end), // End TX/RX burst
.mem_burst_rd (mem_burst_rd), // Start TX burst
.mem_burst_wr (mem_burst_wr), // Start RX burst
.mem_bw (mem_bw), // Burst byte width
.por (por) // Power on reset
.mem_bw (mem_bw) // Burst byte width
);
 
`else
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_clock_module.v
35,9 → 35,9
// - Olivier Girard, olgirard@gmail.com
//
//----------------------------------------------------------------------------
// $Rev: 103 $
// $Rev: 106 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
// $LastChangedDate: 2011-03-25 23:01:03 +0100 (Fri, 25 Mar 2011) $
//----------------------------------------------------------------------------
`ifdef OMSP_NO_INCLUDE
`else
48,6 → 48,10
 
// OUTPUTs
aclk_en, // ACLK enable
cpu_en_s, // Enable CPU code execution (synchronous)
dbg_clk, // Debug unit clock
dbg_en_s, // Debug interface enable (synchronous)
dbg_rst, // Debug unit reset
mclk, // Main system clock
per_dout, // Peripheral data output
por, // Power-on reset
55,7 → 59,9
smclk_en, // SMCLK enable
// INPUTs
dbg_reset, // Reset CPU from debug interface
cpu_en, // Enable CPU code execution (asynchronous)
dbg_cpu_reset, // Reset CPU from debug interface
dbg_en, // Debug interface enable (asynchronous)
dco_clk, // Fast oscillator (fast clock)
lfxt_clk, // Low frequency oscillator (typ 32kHz)
oscoff, // Turns off LFXT1 clock input
62,8 → 68,8
per_addr, // Peripheral address
per_din, // Peripheral data input
per_en, // Peripheral enable (high active)
per_wen, // Peripheral write enable (high active)
reset_n, // Reset Pin (low active)
per_we, // Peripheral write enable (high active)
reset_n, // Reset Pin (low active, asynchronous)
scg1, // System clock generator 1. Turns off the SMCLK
wdt_reset // Watchdog-timer reset
);
71,6 → 77,10
// OUTPUTs
//=========
output aclk_en; // ACLK enable
output cpu_en_s; // Enable CPU code execution (synchronous)
output dbg_clk; // Debug unit clock
output dbg_en_s; // Debug unit enable (synchronous)
output dbg_rst; // Debug unit reset
output mclk; // Main system clock
output [15:0] per_dout; // Peripheral data output
output por; // Power-on reset
79,7 → 89,9
 
// INPUTs
//=========
input dbg_reset; // Reset CPU from debug interface
input cpu_en; // Enable CPU code execution (asynchronous)
input dbg_cpu_reset;// Reset CPU from debug interface
input dbg_en; // Debug interface enable (asynchronous)
input dco_clk; // Fast oscillator (fast clock)
input lfxt_clk; // Low frequency oscillator (typ 32kHz)
input oscoff; // Turns off LFXT1 clock input
86,8 → 98,8
input [7:0] per_addr; // Peripheral address
input [15:0] per_din; // Peripheral data input
input per_en; // Peripheral enable (high active)
input [1:0] per_wen; // Peripheral write enable (high active)
input reset_n; // Reset Pin (low active)
input [1:0] per_we; // Peripheral write enable (high active)
input reset_n; // Reset Pin (low active, asynchronous)
input scg1; // System clock generator 1. Turns off the SMCLK
input wdt_reset; // Watchdog-timer reset
 
119,9 → 131,9
endcase
 
// Read/Write probes
wire reg_lo_write = per_wen[0] & per_en;
wire reg_hi_write = per_wen[1] & per_en;
wire reg_read = ~|per_wen & per_en;
wire reg_lo_write = per_we[0] & per_en;
wire reg_hi_write = per_we[1] & per_en;
wire reg_read = ~|per_we & per_en;
 
// Read/Write vectors
wire [255:0] reg_hi_wr = reg_dec & {256{reg_hi_write}};
171,12 → 183,22
// 5) CLOCK GENERATION
//=============================================================================
 
// Synchronize CPU_EN signal
//---------------------------------------
reg [1:0] cpu_en_sync;
always @ (posedge mclk or posedge por)
if (por) cpu_en_sync <= 2'b00;
else cpu_en_sync <= {cpu_en_sync[0], cpu_en};
 
assign cpu_en_s = cpu_en_sync[1];
 
// Synchronize LFXT_CLK & edge detection
//---------------------------------------
reg [2:0] lfxt_clk_s;
always @ (posedge mclk or posedge puc)
if (puc) lfxt_clk_s <= 3'b000;
always @ (posedge mclk or posedge por)
if (por) lfxt_clk_s <= 3'b000;
else lfxt_clk_s <= {lfxt_clk_s[1:0], lfxt_clk};
 
wire lfxt_clk_en = (lfxt_clk_s[1] & ~lfxt_clk_s[2]) & ~(oscoff & ~bcsctl2[`SELS]);
202,7 → 224,7
 
always @ (posedge mclk or posedge puc)
if (puc) aclk_en <= 1'b0;
else aclk_en <= aclk_en_nxt;
else aclk_en <= aclk_en_nxt & cpu_en_s;
 
always @ (posedge mclk or posedge puc)
if (puc) aclk_div <= 3'h0;
224,7 → 246,7
always @ (posedge mclk or posedge puc)
if (puc) smclk_en <= 1'b0;
else smclk_en <= smclk_en_nxt;
else smclk_en <= smclk_en_nxt & cpu_en_s;
 
always @ (posedge mclk or posedge puc)
if (puc) smclk_div <= 3'h0;
231,29 → 253,51
else if ((bcsctl2[`DIVSx]!=2'b00) & smclk_in) smclk_div <= smclk_div+3'h1;
 
 
// Generate DBG_CLK
//----------------------------
 
assign dbg_clk = mclk;
 
 
//=============================================================================
// 6) RESET GENERATION
//=============================================================================
 
// Generate synchronized POR
wire por_reset = !reset_n;
wire por_reset_a = !reset_n;
 
reg [1:0] por_s;
always @(posedge mclk_n or posedge por_reset)
if (por_reset) por_s <= 2'b11;
else por_s <= {por_s[0], 1'b0};
always @(posedge mclk or posedge por_reset_a)
if (por_reset_a) por_s <= 2'b11;
else por_s <= {por_s[0], 1'b0};
wire por = por_s[1];
 
 
// Generate main system reset
wire puc_reset = por_reset | wdt_reset | dbg_reset;
wire puc_reset = por | wdt_reset | dbg_cpu_reset;
 
reg [1:0] puc_s;
always @(posedge mclk_n or posedge puc_reset)
always @(posedge mclk or posedge puc_reset)
if (puc_reset) puc_s <= 2'b11;
else puc_s <= {puc_s[0], 1'b0};
wire puc = puc_s[1];
 
 
// Generate debug unit reset
`ifdef DBG_EN
reg [1:0] dbg_rst_s;
always @(posedge mclk or posedge por)
if (por) dbg_rst_s <= 2'b11;
else dbg_rst_s <= {dbg_rst_s[0], ~dbg_en};
 
`else
wire [1:0] dbg_rst_s = 2'b11;
`endif
 
wire dbg_en_s = ~dbg_rst_s[1];
wire dbg_rst = dbg_rst_s[1];
 
 
endmodule // omsp_clock_module
 
`ifdef OMSP_NO_INCLUDE
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_watchdog.v
31,9 → 31,9
// - Olivier Girard, olgirard@gmail.com
//
//----------------------------------------------------------------------------
// $Rev: 103 $
// $Rev: 106 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
// $LastChangedDate: 2011-03-25 23:01:03 +0100 (Fri, 25 Mar 2011) $
//----------------------------------------------------------------------------
`ifdef OMSP_NO_INCLUDE
`else
58,7 → 58,7
per_addr, // Peripheral address
per_din, // Peripheral data input
per_en, // Peripheral enable (high active)
per_wen, // Peripheral write enable (high active)
per_we, // Peripheral write enable (high active)
puc, // Main system reset
smclk_en, // SMCLK enable
wdtie // Watchdog timer interrupt enable
82,7 → 82,7
input [7:0] per_addr; // Peripheral address
input [15:0] per_din; // Peripheral data input
input per_en; // Peripheral enable (high active)
input [1:0] per_wen; // Peripheral write enable (high active)
input [1:0] per_we; // Peripheral write enable (high active)
input puc; // Main system reset
input smclk_en; // SMCLK enable
input wdtie; // Watchdog timer interrupt enable
113,8 → 113,8
endcase
 
// Read/Write probes
wire reg_write = |per_wen & per_en;
wire reg_read = ~|per_wen & per_en;
wire reg_write = |per_we & per_en;
wire reg_read = ~|per_we & per_en;
 
// Read/Write vectors
wire [511:0] reg_wr = reg_dec & {512{reg_write}};
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_mem_backbone.v
31,9 → 31,9
// - Olivier Girard, olgirard@gmail.com
//
//----------------------------------------------------------------------------
// $Rev: 103 $
// $Rev: 106 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
// $LastChangedDate: 2011-03-25 23:01:03 +0100 (Fri, 25 Mar 2011) $
//----------------------------------------------------------------------------
`ifdef OMSP_NO_INCLUDE
`else
53,7 → 53,7
fe_pmem_wait, // Frontend wait for Instruction fetch
per_addr, // Peripheral address
per_din, // Peripheral data input
per_wen, // Peripheral write enable (high active)
per_we, // Peripheral write enable (high active)
per_en, // Peripheral enable (high active)
pmem_addr, // Program Memory address
pmem_cen, // Program Memory chip enable (low active)
91,7 → 91,7
output fe_pmem_wait; // Frontend wait for Instruction fetch
output [7:0] per_addr; // Peripheral address
output [15:0] per_din; // Peripheral data input
output [1:0] per_wen; // Peripheral write enable (high active)
output [1:0] per_we; // Peripheral write enable (high active)
output per_en; // Peripheral enable (high active)
output [`PMEM_MSB:0] pmem_addr; // Program Memory address
output pmem_cen; // Program Memory chip enable (low active)
177,7 → 177,7
 
wire [7:0] per_addr = dbg_mem_en ? dbg_mem_addr[8:1] : eu_mab[7:0];
wire [15:0] per_din = dbg_mem_en ? dbg_mem_dout : eu_mdb_out;
wire [1:0] per_wen = dbg_mem_en ? dbg_mem_wr : eu_mb_wr;
wire [1:0] per_we = dbg_mem_en ? dbg_mem_wr : eu_mb_wr;
wire per_en = dbg_mem_en ? dbg_per_en : eu_per_en;
 
reg [15:0] per_dout_val;
231,11 → 231,16
//---------------------------------
 
// Select between peripherals, RAM and ROM
reg [1:0] dbg_mem_din_sel;
`ifdef DBG_EN
reg [1:0] dbg_mem_din_sel;
always @(posedge mclk or posedge puc)
if (puc) dbg_mem_din_sel <= 2'b00;
else dbg_mem_din_sel <= {~dbg_pmem_cen, dbg_per_en};
 
`else
wire [1:0] dbg_mem_din_sel = 2'b00;
`endif
// Mux
assign dbg_mem_din = dbg_mem_din_sel[1] ? pmem_dout :
dbg_mem_din_sel[0] ? per_dout_val : dmem_dout;
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430_defines.v
114,6 → 114,15
//`define DBG_HWBRK_3
 
 
// Defines the debugger CPU_CTL.RST_BRK_EN reset value (CPU break on PUC reset)
//
// When defined, this concretely bring the CPU to break after a PUC
// occurrence by default. This is typically usefull when the program
// memory can only be initialized through the serial debug interface.
//
`define DBG_RST_BRK_EN
 
 
//==========================================================================//
//==========================================================================//
//==========================================================================//
366,28 → 375,7
`define SELS 3
`define DIVSx 2:1
 
// Timer A: TACTL Control Register
`define TASSELx 9:8
`define TAIDx 7:6
`define TAMCx 5:4
`define TACLR 2
`define TAIE 1
`define TAIFG 0
 
// Timer A: TACCTLx Capture/Compare Control Register
`define TACMx 15:14
`define TACCISx 13:12
`define TASCS 11
`define TASCCI 10
`define TACAP 8
`define TAOUTMODx 7:5
`define TACCIE 4
`define TACCI 3
`define TAOUT 2
`define TACOV 1
`define TACCIFG 0
 
 
//
// DEBUG INTERFACE EXTRA CONFIGURATION
//======================================
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430.v
31,9 → 31,9
// - Olivier Girard, olgirard@gmail.com
//
//----------------------------------------------------------------------------
// $Rev: 103 $
// $Rev: 106 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
// $LastChangedDate: 2011-03-25 23:01:03 +0100 (Fri, 25 Mar 2011) $
//----------------------------------------------------------------------------
`ifdef OMSP_NO_INCLUDE
`else
54,7 → 54,7
mclk, // Main system clock
per_addr, // Peripheral address
per_din, // Peripheral data input
per_wen, // Peripheral write enable (high active)
per_we, // Peripheral write enable (high active)
per_en, // Peripheral enable (high active)
pmem_addr, // Program Memory address
pmem_cen, // Program Memory chip enable (low active)
64,7 → 64,9
smclk_en, // SMCLK enable
 
// INPUTs
dbg_uart_rxd, // Debug interface: UART RXD
cpu_en, // Enable CPU code execution (asynchronous)
dbg_en, // Debug interface enable (asynchronous)
dbg_uart_rxd, // Debug interface: UART RXD (asynchronous)
dco_clk, // Fast oscillator (fast clock)
dmem_dout, // Data Memory data output
irq, // Maskable interrupts
72,7 → 74,7
nmi, // Non-maskable interrupt (asynchronous)
per_dout, // Peripheral data output
pmem_dout, // Program Memory data output
reset_n // Reset Pin (low active)
reset_n // Reset Pin (low active, asynchronous)
);
 
// OUTPUTs
88,7 → 90,7
output mclk; // Main system clock
output [7:0] per_addr; // Peripheral address
output [15:0] per_din; // Peripheral data input
output [1:0] per_wen; // Peripheral write enable (high active)
output [1:0] per_we; // Peripheral write enable (high active)
output per_en; // Peripheral enable (high active)
output [`PMEM_MSB:0] pmem_addr; // Program Memory address
output pmem_cen; // Program Memory chip enable (low active)
100,7 → 102,9
 
// INPUTs
//=========
input dbg_uart_rxd; // Debug interface: UART RXD
input cpu_en; // Enable CPU code execution (asynchronous)
input dbg_en; // Debug interface enable (asynchronous)
input dbg_uart_rxd; // Debug interface: UART RXD (asynchronous)
input dco_clk; // Fast oscillator (fast clock)
input [15:0] dmem_dout; // Data Memory data output
input [13:0] irq; // Maskable interrupts
108,7 → 112,7
input nmi; // Non-maskable interrupt (asynchronous)
input [15:0] per_dout; // Peripheral data output
input [15:0] pmem_dout; // Program Memory data output
input reset_n; // Reset Pin (active low)
input reset_n; // Reset Pin (active low, asynchronous)
 
 
 
144,7 → 148,7
wire dbg_halt_cmd;
wire dbg_mem_en;
wire dbg_reg_wr;
wire dbg_reset;
wire dbg_cpu_reset;
wire [15:0] dbg_mem_addr;
wire [15:0] dbg_mem_dout;
wire [15:0] dbg_mem_din;
166,6 → 170,10
 
// OUTPUTs
.aclk_en (aclk_en), // ACLK enablex
.cpu_en_s (cpu_en_s), // Enable CPU code execution (synchronous)
.dbg_clk (dbg_clk), // Debug unit clock
.dbg_en_s (dbg_en_s), // Debug interface enable (synchronous)
.dbg_rst (dbg_rst), // Debug unit reset
.mclk (mclk), // Main system clock
.per_dout (per_dout_clk), // Peripheral data output
.por (por), // Power-on reset
173,7 → 181,9
.smclk_en (smclk_en), // SMCLK enable
// INPUTs
.dbg_reset (dbg_reset), // Reset CPU from debug interface
.cpu_en (cpu_en), // Enable CPU code execution (asynchronous)
.dbg_cpu_reset(dbg_cpu_reset), // Reset CPU from debug interface
.dbg_en (dbg_en), // Debug interface enable (asynchronous)
.dco_clk (dco_clk), // Fast oscillator (fast clock)
.lfxt_clk (lfxt_clk), // Low frequency oscillator (typ 32kHz)
.oscoff (oscoff), // Turns off LFXT1 clock input
180,8 → 190,8
.per_addr (per_addr), // Peripheral address
.per_din (per_din), // Peripheral data input
.per_en (per_en), // Peripheral enable (high active)
.per_wen (per_wen), // Peripheral write enable (high active)
.reset_n (reset_n), // Reset Pin (low active)
.per_we (per_we), // Peripheral write enable (high active)
.reset_n (reset_n), // Reset Pin (low active, asynchronous)
.scg1 (scg1), // System clock generator 1. Turns off the SMCLK
.wdt_reset (wdt_reset) // Watchdog-timer reset
);
219,6 → 229,7
.pc_nxt (pc_nxt), // Next PC value (for CALL & IRQ)
// INPUTs
.cpu_en_s (cpu_en_s), // Enable CPU code execution (synchronous)
.cpuoff (cpuoff), // Turns off the CPU
.dbg_halt_cmd (dbg_halt_cmd), // Halt CPU command
.dbg_reg_sel (dbg_mem_addr[3:0]), // Debug selected register for rd/wr access
298,7 → 309,7
.fe_pmem_wait (fe_pmem_wait), // Frontend wait for Instruction fetch
.per_addr (per_addr), // Peripheral address
.per_din (per_din), // Peripheral data input
.per_wen (per_wen), // Peripheral write enable (high active)
.per_we (per_we), // Peripheral write enable (high active)
.per_en (per_en), // Peripheral enable (high active)
.pmem_addr (pmem_addr), // Program Memory address
.pmem_cen (pmem_cen), // Program Memory chip enable (low active)
344,7 → 355,7
.per_addr (per_addr), // Peripheral address
.per_din (per_din), // Peripheral data input
.per_en (per_en), // Peripheral enable (high active)
.per_wen (per_wen), // Peripheral write enable (high active)
.per_we (per_we), // Peripheral write enable (high active)
.por (por), // Power-on reset
.puc (puc), // Main system reset
.wdtifg_clr (irq_acc[10]), // Clear Watchdog-timer interrupt flag
376,7 → 387,7
.per_addr (per_addr), // Peripheral address
.per_din (per_din), // Peripheral data input
.per_en (per_en), // Peripheral enable (high active)
.per_wen (per_wen), // Peripheral write enable (high active)
.per_we (per_we), // Peripheral write enable (high active)
.puc (puc), // Main system reset
.smclk_en (smclk_en), // SMCLK enable
.wdtie (wdtie) // Watchdog-timer interrupt enable
397,7 → 408,7
.per_addr (per_addr), // Peripheral address
.per_din (per_din), // Peripheral data input
.per_en (per_en), // Peripheral enable (high active)
.per_wen (per_wen), // Peripheral write enable (high active)
.per_we (per_we), // Peripheral write enable (high active)
.puc (puc) // Main system reset
);
`else
430,14 → 441,18
.dbg_mem_en (dbg_mem_en), // Debug unit memory enable
.dbg_mem_wr (dbg_mem_wr), // Debug unit memory write
.dbg_reg_wr (dbg_reg_wr), // Debug unit CPU register write
.dbg_reset (dbg_reset), // Reset CPU from debug interface
.dbg_cpu_reset(dbg_cpu_reset), // Reset CPU from debug interface
.dbg_uart_txd (dbg_uart_txd), // Debug interface: UART TXD
// INPUTs
.cpu_en_s (cpu_en_s), // Enable CPU code execution (synchronous)
.dbg_clk (dbg_clk), // Debug unit clock
.dbg_en_s (dbg_en_s), // Debug interface enable (synchronous)
.dbg_halt_st (dbg_halt_st), // Halt/Run status from CPU
.dbg_mem_din (dbg_mem_din), // Debug unit Memory data input
.dbg_reg_din (dbg_reg_din), // Debug unit CPU register data input
.dbg_uart_rxd (dbg_uart_rxd), // Debug interface: UART RXD
.dbg_rst (dbg_rst), // Debug unit reset
.dbg_uart_rxd (dbg_uart_rxd), // Debug interface: UART RXD (asynchronous)
.decode_noirq (decode_noirq), // Frontend decode instruction
.eu_mab (eu_mab), // Execution-Unit Memory address bus
.eu_mb_en (eu_mb_en), // Execution-Unit Memory bus enable
447,22 → 462,20
.exec_done (exec_done), // Execution completed
.fe_mb_en (fe_mb_en), // Frontend Memory bus enable
.fe_mdb_in (fe_mdb_in), // Frontend Memory data bus input
.mclk (mclk), // Main system clock
.pc (pc), // Program counter
.por (por), // Power on reset
.puc (puc) // Main system reset
);
 
`else
assign dbg_freeze = 1'b0;
assign dbg_halt_cmd = 1'b0;
assign dbg_mem_addr = 16'h0000;
assign dbg_mem_dout = 16'h0000;
assign dbg_mem_en = 1'b0;
assign dbg_mem_wr = 2'b00;
assign dbg_reg_wr = 1'b0;
assign dbg_reset = 1'b0;
assign dbg_uart_txd = 1'b0;
assign dbg_freeze = ~cpu_en_s;
assign dbg_halt_cmd = 1'b0;
assign dbg_mem_addr = 16'h0000;
assign dbg_mem_dout = 16'h0000;
assign dbg_mem_en = 1'b0;
assign dbg_mem_wr = 2'b00;
assign dbg_reg_wr = 1'b0;
assign dbg_cpu_reset = 1'b0;
assign dbg_uart_txd = 1'b0;
`endif
 
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430_undefines.v
86,7 → 86,12
`undef DBG_HWBRK_3
`endif
 
// Let the CPU break after a PUC occurrence by default
`ifdef DBG_RST_BRK_EN
`undef DBG_RST_BRK_EN
`endif
 
 
//==========================================================================//
//==========================================================================//
//==========================================================================//
499,61 → 504,7
`undef DIVSx
`endif
 
// Timer A: TACTL Control Register
`ifdef TASSELx
`undef TASSELx
`endif
`ifdef TAIDx
`undef TAIDx
`endif
`ifdef TAMCx
`undef TAMCx
`endif
`ifdef TACLR
`undef TACLR
`endif
`ifdef TAIE
`undef TAIE
`endif
`ifdef TAIFG
`undef TAIFG
`endif
 
// Timer A: TACCTLx Capture/Compare Control Register
`ifdef TACMx
`undef TACMx
`endif
`ifdef TACCISx
`undef TACCISx
`endif
`ifdef TASCS
`undef TASCS
`endif
`ifdef TASCCI
`undef TASCCI
`endif
`ifdef TACAP
`undef TACAP
`endif
`ifdef TAOUTMODx
`undef TAOUTMODx
`endif
`ifdef TACCIE
`undef TACCIE
`endif
`ifdef TACCI
`undef TACCI
`endif
`ifdef TAOUT
`undef TAOUT
`endif
`ifdef TACOV
`undef TACOV
`endif
`ifdef TACCIFG
`undef TACCIFG
`endif
 
//
// DEBUG INTERFACE EXTRA CONFIGURATION
//======================================
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openMSP430_fpga.v
97,7 → 97,7
wire [7:0] per_addr;
wire [15:0] per_din;
wire per_en;
wire [1:0] per_wen;
wire [1:0] per_we;
wire [15:0] per_dout;
 
wire [13:0] irq_acc;
315,7 → 315,7
.mclk (mclk), // Main system clock
.per_addr (per_addr), // Peripheral address
.per_din (per_din), // Peripheral data input
.per_wen (per_wen), // Peripheral write enable (high active)
.per_we (per_we), // Peripheral write enable (high active)
.per_en (per_en), // Peripheral enable (high active)
.pmem_addr (pmem_addr), // Program Memory address
.pmem_cen (pmem_cen), // Program Memory chip enable (low active)
325,6 → 325,8
.smclk_en (smclk_en), // SMCLK enable
 
// INPUTs
.cpu_en (1'b1), // Enable CPU code execution (asynchronous)
.dbg_en (1'b1), // Debug interface enable (asynchronous)
.dbg_uart_rxd (uart_rx), // Debug interface: UART RXD
.dco_clk (dco_clk), // Fast oscillator (fast clock)
.dmem_dout (dmem_dout), // Data Memory data output
360,7 → 362,7
.per_addr (per_addr), // Peripheral address
.per_din (per_din), // Peripheral data input
.per_en (per_en), // Peripheral enable (high active)
.per_wen (per_wen), // Peripheral write enable (high active)
.per_we (per_we), // Peripheral write enable (high active)
.puc (puc) // Main system reset
);
 
379,7 → 381,7
.per_addr (per_addr), // Peripheral address
.per_din (per_din), // Peripheral data input
.per_en (per_en), // Peripheral enable (high active)
.per_wen (per_wen), // Peripheral write enable (high active)
.per_we (per_we), // Peripheral write enable (high active)
.puc (puc) // Main system reset
);
 
428,7 → 430,7
.per_addr (per_addr), // Peripheral address
.per_din (per_din), // Peripheral data input
.per_en (per_en), // Peripheral enable (high active)
.per_wen (per_wen), // Peripheral write enable (high active)
.per_we (per_we), // Peripheral write enable (high active)
.puc (puc) // Main system reset
);
 
458,7 → 460,7
.per_addr (per_addr), // Peripheral address
.per_din (per_din), // Peripheral data input
.per_en (per_en), // Peripheral enable (high active)
.per_wen (per_wen), // Peripheral write enable (high active)
.per_we (per_we), // Peripheral write enable (high active)
.puc (puc), // Main system reset
.smclk_en (smclk_en), // SMCLK enable (from CPU)
.ta_cci0a (1'b0), // Timer A capture 0 input A
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim/src/submit.f
68,6 → 68,7
//=============================================================================
 
+incdir+../../../rtl/verilog/openmsp430/
+incdir+../../../rtl/verilog/openmsp430/periph
../../../rtl/verilog/openmsp430/openMSP430.v
../../../rtl/verilog/openmsp430/omsp_frontend.v
../../../rtl/verilog/openmsp430/omsp_execution_unit.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim/src/spacewar.v
12,10 → 12,14
repeat(5) @(posedge oscclk);
stimulus_done = 0;
 
repeat(50) @(posedge mclk);
 
// Send uart synchronization frame
dbg_uart_tx(DBG_SYNC);
 
// Let the CPU run
dbg_uart_wr(CPU_CTL, 16'h0002);
 
 
stimulus_done = 1;
end
 
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/synthesis/actel/prepare_implementation.tcl
55,9 → 55,11
set designTop "openMSP430_fpga"
 
# RTL include files
set rtlIncludeFiles "../../../rtl/verilog/openmsp430/timescale.v \
../../../rtl/verilog/openmsp430/openMSP430_defines.v \
../../../rtl/verilog/openmsp430/openMSP430_undefines.v"
set rtlIncludeFiles "../../../rtl/verilog/openmsp430/timescale.v \
../../../rtl/verilog/openmsp430/openMSP430_defines.v \
../../../rtl/verilog/openmsp430/openMSP430_undefines.v \
../../../rtl/verilog/openmsp430/periph/omsp_timerA_defines.v \
../../../rtl/verilog/openmsp430/periph/omsp_timerA_undefines.v"
 
###############################################################################
# CLEANUP #

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