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URL https://opencores.org/ocsvn/or1k/or1k/trunk

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Rev 1062 → Rev 1063

/trunk/or1200/rtl/verilog/or1200_spram_1024x8.v
62,6 → 62,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.8 2001/11/02 18:57:14 lampret
// Modified virtual silicon instantiations.
//
88,6 → 91,10
`include "or1200_defines.v"
 
module or1200_spram_1024x8(
`ifdef OR1200_BIST
// RAM BIST
scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
`endif
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, do
);
98,7 → 105,18
parameter aw = 10;
parameter dw = 8;
 
`ifdef OR1200_BIST
//
// RAM BIST
//
input scanb_rst,
scanb_si,
scanb_en,
scanb_clk;
output scanb_so;
`endif
 
//
// Generic synchronous single-port RAM interface
//
input clk; // Clock
114,6 → 132,12
// Internal wires and registers
//
 
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign scanb_so = scanb_si;
`endif
`endif
 
`ifdef OR1200_ARTISAN_SSP
 
188,8 → 212,20
`ifdef UNUSED
vs_hdsp_1024x8 #(1<<aw, aw-1, dw-1) vs_ssp(
`else
`ifdef OR1200_BIST
vs_hdsp_1024x8_bist vs_ssp(
`else
vs_hdsp_1024x8 vs_ssp(
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_si),
.scanb_so(scanb_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
`endif
.CK(clk),
.ADR(addr),
.DI(di),
/trunk/or1200/rtl/verilog/or1200_ic_top.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.6 2002/03/29 15:16:55 lampret
// Some of the warnings fixed.
//
// Revision 1.5 2002/02/11 04:33:17 lampret
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
//
104,6 → 107,11
icpu_sel_i, icpu_tag_i,
icpu_dat_o, icpu_ack_o, icimmu_rty_o, icimmu_err_o, icimmu_tag_o,
 
`ifdef OR1200_BIST
// RAM BIST
scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
`endif
 
// SPRs
spr_cs, spr_write, spr_dat_i
);
149,7 → 157,18
output icimmu_err_o;
output [3:0] icimmu_tag_o;
 
`ifdef OR1200_BIST
//
// RAM BIST
//
input scanb_rst,
scanb_si,
scanb_en,
scanb_clk;
output scanb_so;
`endif
 
//
// SPR access
//
input spr_cs;
178,6 → 197,16
wire icfsm_first_miss_err;
wire icfsm_burst;
wire icfsm_tag_we;
`ifdef OR1200_BIST
//
// RAM BIST
//
wire scanb_ram_so;
wire scanb_tag_so;
wire scanb_ram_si = scanb_si;
wire scanb_tag_si = scanb_ram_so;
assign scanb_so = scanb_tag_so;
`endif
 
//
// Simple assignments
266,6 → 295,14
or1200_ic_ram or1200_ic_ram(
.clk(clk),
.rst(rst),
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_ram_si),
.scanb_so(scanb_ram_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
`endif
.addr(ic_addr[`OR1200_ICINDXH:2]),
.en(ic_en),
.we(icram_we),
279,6 → 316,14
or1200_ic_tag or1200_ic_tag(
.clk(clk),
.rst(rst),
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_tag_si),
.scanb_so(scanb_tag_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
`endif
.addr(ictag_addr),
.en(ictag_en),
.we(ictag_we),
/trunk/or1200/rtl/verilog/or1200_defines.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.27 2002/09/16 03:13:23 lampret
// Removed obsolete comment.
//
// Revision 1.26 2002/09/08 05:52:16 lampret
// Added optional l.div/l.divu insns. By default they are disabled.
//
303,6 → 306,16
//
 
//
// Enable RAM BIST
//
// At the moment this only works for Virtual Silicon
// single port RAMs. For other RAMs it has not effect.
// Special wrapper for VS RAMs needs to be provided
// with scan flops to facilitate bist scan.
//
//`define OR1200_BIST
 
//
// Register OR1200 WISHBONE outputs
// (must be defined/enabled)
//
/trunk/or1200/rtl/verilog/or1200_dc_tag.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.8 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
70,6 → 73,11
// Clock and reset
clk, rst,
 
`ifdef OR1200_BIST
// RAM BIST
scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
`endif
 
// Internal i/f
addr, en, we, datain, tag_v, tag
);
89,6 → 97,17
output tag_v;
output [dw-2:0] tag;
 
`ifdef OR1200_BIST
//
// RAM BIST
//
input scanb_rst,
scanb_si,
scanb_en,
scanb_clk;
output scanb_so;
`endif
 
`ifdef OR1200_NO_DC
 
//
96,6 → 115,9
//
assign tag = {dw-1{1'b0}};
assign tag_v = 1'b0;
`ifdef OR1200_BIST
assign scanb_so = scanb_si;
`endif
 
`else
 
108,6 → 130,14
`ifdef OR1200_DC_1W_8KB
or1200_spram_512x20 dc_tag0(
`endif
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_si),
.scanb_so(scanb_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
`endif
.clk(clk),
.rst(rst),
.ce(en),
/trunk/or1200/rtl/verilog/or1200_dc_ram.v
1,3 → 1,4
 
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's DC RAMs ////
44,6 → 45,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.8 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
70,6 → 74,11
// Reset and clock
clk, rst,
 
`ifdef OR1200_BIST
// RAM BIST
scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
`endif
 
// Internal i/f
addr, en, we, datain, dataout
);
88,17 → 97,45
input [dw-1:0] datain;
output [dw-1:0] dataout;
 
`ifdef OR1200_BIST
//
// RAM BIST
//
input scanb_rst,
scanb_si,
scanb_en,
scanb_clk;
output scanb_so;
`endif
 
`ifdef OR1200_NO_DC
 
//
// Data cache not implemented
//
 
assign dataout = {dw{1'b0}};
`ifdef OR1200_BIST
assign scanb_so = scanb_si;
`endif
 
`else
 
`ifdef OR1200_BIST
//
// RAM BIST
//
wire scanb_ram0_so;
wire scanb_ram1_so;
wire scanb_ram2_so;
wire scanb_ram3_so;
wire scanb_ram0_si = scanb_si;
wire scanb_ram1_si = scanb_ram0_so;
wire scanb_ram2_si = scanb_ram1_so;
wire scanb_ram3_si = scanb_ram2_so;
assign scanb_so = scanb_ram3_so;
`endif
 
//
// Instantiation of RAM block 0
//
`ifdef OR1200_DC_1W_4KB
107,6 → 144,14
`ifdef OR1200_DC_1W_8KB
or1200_spram_2048x8 dc_ram0(
`endif
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_ram0_si),
.scanb_so(scanb_ram0_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
`endif
.clk(clk),
.rst(rst),
.ce(en),
126,6 → 171,14
`ifdef OR1200_DC_1W_8KB
or1200_spram_2048x8 dc_ram1(
`endif
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_ram1_si),
.scanb_so(scanb_ram1_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
`endif
.clk(clk),
.rst(rst),
.ce(en),
145,6 → 198,14
`ifdef OR1200_DC_1W_8KB
or1200_spram_2048x8 dc_ram2(
`endif
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_ram2_si),
.scanb_so(scanb_ram2_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
`endif
.clk(clk),
.rst(rst),
.ce(en),
164,6 → 225,14
`ifdef OR1200_DC_1W_8KB
or1200_spram_2048x8 dc_ram3(
`endif
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_ram3_si),
.scanb_so(scanb_ram3_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
`endif
.clk(clk),
.rst(rst),
.ce(en),
/trunk/or1200/rtl/verilog/or1200_spram_1024x32.v
62,6 → 62,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.8 2001/11/02 18:57:14 lampret
// Modified virtual silicon instantiations.
//
88,6 → 91,10
`include "or1200_defines.v"
 
module or1200_spram_1024x32(
`ifdef OR1200_BIST
// RAM BIST
scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
`endif
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, do
);
98,7 → 105,18
parameter aw = 10;
parameter dw = 32;
 
`ifdef OR1200_BIST
//
// RAM BIST
//
input scanb_rst,
scanb_si,
scanb_en,
scanb_clk;
output scanb_so;
`endif
 
//
// Generic synchronous single-port RAM interface
//
input clk; // Clock
114,6 → 132,12
// Internal wires and registers
//
 
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign scanb_so = scanb_si;
`endif
`endif
 
`ifdef OR1200_ARTISAN_SSP
 
188,8 → 212,20
`ifdef UNUSED
vs_hdsp_1024x32 #(1<<aw, aw-1, dw-1) vs_ssp(
`else
`ifdef OR1200_BIST
vs_hdsp_1024x32_bist vs_ssp(
`else
vs_hdsp_1024x32 vs_ssp(
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_si),
.scanb_so(scanb_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
`endif
.CK(clk),
.ADR(addr),
.DI(di),
/trunk/or1200/rtl/verilog/or1200_spram_64x22.v
62,6 → 62,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.7 2001/11/02 18:57:14 lampret
// Modified virtual silicon instantiations.
//
88,6 → 91,10
`include "or1200_defines.v"
 
module or1200_spram_64x22(
`ifdef OR1200_BIST
// RAM BIST
scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
`endif
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, do
);
98,7 → 105,18
parameter aw = 6;
parameter dw = 22;
 
`ifdef OR1200_BIST
//
// RAM BIST
//
input scanb_rst,
scanb_si,
scanb_en,
scanb_clk;
output scanb_so;
`endif
 
//
// Generic synchronous single-port RAM interface
//
input clk; // Clock
115,6 → 133,13
//
wire [9:0] unconnected;
 
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign scanb_so = scanb_si;
`endif
`endif
 
`ifdef OR1200_ARTISAN_SSP
 
//
188,8 → 213,20
`ifdef UNUSED
vs_hdsp_64x22 #(1<<aw, aw-1, dw-1) vs_ssp(
`else
`ifdef OR1200_BIST
vs_hdsp_64x22_bist vs_ssp(
`else
vs_hdsp_64x22 vs_ssp(
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_si),
.scanb_so(scanb_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
`endif
.CK(clk),
.ADR(addr),
.DI(di),
/trunk/or1200/rtl/verilog/or1200_immu_top.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.10 2002/09/16 03:08:56 lampret
// Disabled cache inhibit atttribute.
//
// Revision 1.9 2002/08/18 19:54:17 lampret
// Added store buffer.
//
111,6 → 114,11
// SPR access
spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
 
`ifdef OR1200_BIST
// RAM BIST
scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
`endif
 
// IC i/f
icimmu_rty_i, icimmu_err_i, icimmu_tag_i, icimmu_adr_o, icimmu_cycstb_o, icimmu_ci_o
);
150,7 → 158,18
input [31:0] spr_dat_i;
output [31:0] spr_dat_o;
 
`ifdef OR1200_BIST
//
// RAM BIST
//
input scanb_rst,
scanb_si,
scanb_en,
scanb_clk;
output scanb_so;
`endif
 
//
// IC I/F
//
input icimmu_rty_i;
221,7 → 240,9
assign icpu_rty_o = icimmu_rty_i;
assign icpu_err_o = icimmu_err_i;
assign icimmu_ci_o = `OR1200_IMMU_CI;
 
`ifdef OR1200_BIST
assign scanb_so = scanb_si;
`endif
`else
 
//
367,6 → 388,15
.sxe(itlb_sxe),
.ci(itlb_ci),
 
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_si),
.scanb_so(scanb_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
`endif
 
// SPR access
.spr_cs(itlb_spr_access),
.spr_write(spr_write),
/trunk/or1200/rtl/verilog/or1200_spram_64x24.v
62,6 → 62,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.8 2001/11/02 18:57:14 lampret
// Modified virtual silicon instantiations.
//
91,6 → 94,10
`include "or1200_defines.v"
 
module or1200_spram_64x24(
`ifdef OR1200_BIST
// RAM BIST
scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
`endif
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, do
);
101,7 → 108,18
parameter aw = 6;
parameter dw = 24;
 
`ifdef OR1200_BIST
//
// RAM BIST
//
input scanb_rst,
scanb_si,
scanb_en,
scanb_clk;
output scanb_so;
`endif
 
//
// Generic synchronous single-port RAM interface
//
input clk; // Clock
118,6 → 136,13
//
wire [7:0] unconnected;
 
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign scanb_so = scanb_si;
`endif
`endif
 
`ifdef OR1200_ARTISAN_SSP
 
//
191,8 → 216,20
`ifdef UNUSED
vs_hdsp_64x24 #(1<<aw, aw-1, dw-1) vs_ssp(
`else
`ifdef OR1200_BIST
vs_hdsp_64x24_bist vs_ssp(
`else
vs_hdsp_64x24 vs_ssp(
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_si),
.scanb_so(scanb_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
`endif
.CK(clk),
.ADR(addr),
.DI(di),
/trunk/or1200/rtl/verilog/or1200_spram_2048x32.v
62,6 → 62,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.8 2001/11/02 18:57:14 lampret
// Modified virtual silicon instantiations.
//
88,6 → 91,10
`include "or1200_defines.v"
 
module or1200_spram_2048x32(
`ifdef OR1200_BIST
// RAM BIST
scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
`endif
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, do
);
98,7 → 105,18
parameter aw = 11;
parameter dw = 32;
 
`ifdef OR1200_BIST
//
// RAM BIST
//
input scanb_rst,
scanb_si,
scanb_en,
scanb_clk;
output scanb_so;
`endif
 
//
// Generic synchronous single-port RAM interface
//
input clk; // Clock
114,6 → 132,12
// Internal wires and registers
//
 
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign scanb_so = scanb_si;
`endif
`endif
 
`ifdef OR1200_ARTISAN_SSP
 
188,8 → 212,20
`ifdef UNUSED
vs_hdsp_2048x32 #(1<<aw, aw-1, dw-1) vs_ssp(
`else
`ifdef OR1200_BIST
vs_hdsp_2048x32_bist vs_ssp(
`else
vs_hdsp_2048x32 vs_ssp(
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_si),
.scanb_so(scanb_so),
.scanb_en(scanb_en),
.canb_clk(scanb_clk),
`endif
.CK(clk),
.ADR(addr),
.DI(di),
/trunk/or1200/rtl/verilog/or1200_immu_tlb.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4 2002/08/14 06:23:50 lampret
// Disabled ITLB translation when 1) doing access to ITLB SPRs or 2) crossing page. This modification was tested only with parts of IMMU test - remaining test cases needs to be run.
//
// Revision 1.3 2002/02/11 04:33:17 lampret
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
//
80,6 → 83,11
// I/F for translation
tlb_en, vaddr, hit, ppn, uxe, sxe, ci,
 
`ifdef OR1200_BIST
// RAM BIST
scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
`endif
 
// SPR access
spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o
);
108,7 → 116,18
output sxe;
output ci;
 
`ifdef OR1200_BIST
//
// RAM BIST
//
input scanb_rst,
scanb_si,
scanb_en,
scanb_clk;
output scanb_so;
`endif
 
//
// SPR access
//
input spr_cs;
214,6 → 233,14
or1200_spram_64x14 itlb_mr_ram(
.clk(clk),
.rst(rst),
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_si),
.scanb_so(scanb_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
`endif
.ce(tlb_mr_en),
.we(tlb_mr_we),
.oe(1'b1),
228,6 → 255,14
or1200_spram_64x22 itlb_tr_ram(
.clk(clk),
.rst(rst),
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_si),
.scanb_so(scanb_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
`endif
.ce(tlb_tr_en),
.we(tlb_tr_we),
.oe(1'b1),
/trunk/or1200/rtl/verilog/or1200_dc_top.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.5 2002/08/18 19:54:47 lampret
// Added store buffer.
//
// Revision 1.4 2002/02/11 04:33:17 lampret
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
//
101,6 → 104,11
dcpu_we_i, dcpu_sel_i, dcpu_tag_i, dcpu_dat_i,
dcpu_dat_o, dcpu_ack_o, dcpu_rty_o, dcdmmu_err_o, dcdmmu_tag_o,
 
`ifdef OR1200_BIST
// RAM BIST
scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
`endif
 
// SPRs
spr_cs, spr_write, spr_dat_i
);
148,7 → 156,18
output dcdmmu_err_o;
output [3:0] dcdmmu_tag_o;
 
`ifdef OR1200_BIST
//
// RAM BIST
//
input scanb_rst,
scanb_si,
scanb_en,
scanb_clk;
output scanb_so;
`endif
 
//
// SPR access
//
input spr_cs;
178,6 → 197,16
wire dcfsm_first_miss_err;
wire dcfsm_burst;
wire dcfsm_tag_we;
`ifdef OR1200_BIST
//
// RAM BIST
//
wire scanb_ram_so;
wire scanb_tag_so;
wire scanb_ram_si = scanb_si;
wire scanb_tag_si = scanb_ram_so;
assign scanb_so = scanb_tag_so;
`endif
 
//
// Simple assignments
270,6 → 299,14
or1200_dc_ram or1200_dc_ram(
.clk(clk),
.rst(rst),
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_ram_si),
.scanb_so(scanb_ram_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
`endif
.addr(dc_addr[`OR1200_DCINDXH:2]),
.en(dc_en),
.we(dcram_we),
283,6 → 320,14
or1200_dc_tag or1200_dc_tag(
.clk(clk),
.rst(rst),
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_tag_si),
.scanb_so(scanb_tag_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
`endif
.addr(dctag_addr),
.en(dctag_en),
.we(dctag_we),
/trunk/or1200/rtl/verilog/or1200_spram_256x21.v
62,6 → 62,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.10 2001/11/27 21:24:04 lampret
// Changed instantiation name of VS RAMs.
//
94,6 → 97,10
`include "or1200_defines.v"
 
module or1200_spram_256x21(
`ifdef OR1200_BIST
// RAM BIST
scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
`endif
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, do
);
104,7 → 111,18
parameter aw = 8;
parameter dw = 21;
 
`ifdef OR1200_BIST
//
// RAM BIST
//
input scanb_rst,
scanb_si,
scanb_en,
scanb_clk;
output scanb_so;
`endif
 
//
// Generic synchronous single-port RAM interface
//
input clk; // Clock
121,6 → 139,13
//
wire [10:0] unconnected;
 
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign scanb_so = scanb_si;
`endif
`endif
 
`ifdef OR1200_ARTISAN_SSP
 
//
194,8 → 219,20
`ifdef UNUSED
vs_hdsp_256x21 #(1<<aw, aw-1, dw-1) vs_ssp(
`else
`ifdef OR1200_BIST
vs_hdsp_256x21_bist vs_ssp(
`else
vs_hdsp_256x21 vs_ssp(
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_si),
.scanb_so(scanb_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
`endif
.CK(clk),
.ADR(addr),
.DI(di),
/trunk/or1200/rtl/verilog/or1200_spram_2048x8.v
62,6 → 62,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.8 2001/11/02 18:57:14 lampret
// Modified virtual silicon instantiations.
//
88,6 → 91,10
`include "or1200_defines.v"
 
module or1200_spram_2048x8(
`ifdef OR1200_BIST
// RAM BIST
scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
`endif
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, do
);
98,7 → 105,18
parameter aw = 11;
parameter dw = 8;
 
`ifdef OR1200_BIST
//
// RAM BIST
//
input scanb_rst,
scanb_si,
scanb_en,
scanb_clk;
output scanb_so;
`endif
 
//
// Generic synchronous single-port RAM interface
//
input clk; // Clock
114,6 → 132,12
// Internal wires and registers
//
 
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign scanb_so = scanb_si;
`endif
`endif
 
`ifdef OR1200_ARTISAN_SSP
 
188,8 → 212,20
`ifdef UNUSED
vs_hdsp_2048x8 #(1<<aw, aw-1, dw-1) vs_ssp(
`else
`ifdef OR1200_BIST
vs_hdsp_2048x8_bist vs_ssp(
`else
vs_hdsp_2048x8 vs_ssp(
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_si),
.scanb_so(scanb_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
`endif
.CK(clk),
.ADR(addr),
.DI(di),
/trunk/or1200/rtl/verilog/or1200_dmmu_top.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.6 2002/03/29 15:16:55 lampret
// Some of the warnings fixed.
//
// Revision 1.5 2002/02/14 15:34:02 simons
// Lapsus fixed.
//
99,6 → 102,11
// SPR access
spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
 
`ifdef OR1200_BIST
// RAM BIST
scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
`endif
 
// DC i/f
dcdmmu_err_i, dcdmmu_tag_i, dcdmmu_adr_o, dcdmmu_cycstb_o, dcdmmu_ci_o
);
137,7 → 145,18
input [31:0] spr_dat_i;
output [31:0] spr_dat_o;
 
`ifdef OR1200_BIST
//
// RAM BIST
//
input scanb_rst,
scanb_si,
scanb_en,
scanb_clk;
output scanb_so;
`endif
 
//
// DC I/F
//
input dcdmmu_err_i;
191,6 → 210,9
assign dcdmmu_cycstb_o = dcpu_cycstb_i;
assign dcpu_err_o = dcdmmu_err_i;
assign dcdmmu_ci_o = `OR1200_DMMU_CI;
`ifdef OR1200_BIST
assign scanb_so = scanb_si;
`endif
 
`else
 
300,6 → 322,15
.sre(dtlb_sre),
.ci(dtlb_ci),
 
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_si),
.scanb_so(scanb_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
`endif
 
// SPR access
.spr_cs(dtlb_spr_access),
.spr_write(spr_write),
/trunk/or1200/rtl/verilog/or1200_ic_tag.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.8 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
70,6 → 73,11
// Clock and reset
clk, rst,
 
`ifdef OR1200_BIST
// RAM BIST
scanb_rst, scanb_si, scanb_so, scanb_eni, scanb_clk,
`endif
 
// Internal i/f
addr, en, we, datain, tag_v, tag
);
87,7 → 95,18
input clk;
input rst;
 
`ifdef OR1200_BIST
//
// RAM BIST
//
input scanb_rst,
scanb_si,
scanb_en,
scanb_clk;
output scanb_so;
`endif
 
//
// Internal i/f
//
input [aw-1:0] addr;
104,6 → 123,10
//
assign tag = {dw-1{1'b0}};
assign tag_v = 1'b0;
`ifdef OR1200_BIST
assign scanb_so = scanb_si;
`endif
 
`else
 
//
115,6 → 138,14
`ifdef OR1200_IC_1W_8KB
or1200_spram_512x20 ic_tag0(
`endif
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_si),
.scanb_so(scanb_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
`endif
.clk(clk),
.rst(rst),
.ce(en),
/trunk/or1200/rtl/verilog/or1200_spram_64x14.v
62,6 → 62,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.7 2001/11/02 18:57:14 lampret
// Modified virtual silicon instantiations.
//
88,6 → 91,10
`include "or1200_defines.v"
 
module or1200_spram_64x14(
`ifdef OR1200_BIST
// RAM BIST
scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
`endif
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, do
);
98,7 → 105,18
parameter aw = 6;
parameter dw = 14;
 
`ifdef OR1200_BIST
//
// RAM BIST
//
input scanb_rst,
scanb_si,
scanb_en,
scanb_clk;
output scanb_so;
`endif
 
//
// Generic synchronous single-port RAM interface
//
input clk; // Clock
115,6 → 133,13
//
wire [1:0] unconnected;
 
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign scanb_so = scanb_si;
`endif
`endif
 
`ifdef OR1200_ARTISAN_SSP
 
//
188,8 → 213,20
`ifdef UNUSED
vs_hdsp_64x14 #(1<<aw, aw-1, dw-1) vs_ssp(
`else
`ifdef OR1200_BIST
vs_hdsp_64x14_bist vs_ssp(
`else
vs_hdsp_64x14 vs_ssp(
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_si),
.scanb_so(scanb_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
`endif
.CK(clk),
.ADR(addr),
.DI(di),
/trunk/or1200/rtl/verilog/or1200_ic_ram.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.9 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
73,6 → 76,11
// Clock and reset
clk, rst,
 
`ifdef OR1200_BIST
// RAM BIST
scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
`endif
 
// Internal i/f
addr, en, we, datain, dataout
);
91,6 → 99,17
input [dw-1:0] datain;
output [dw-1:0] dataout;
 
`ifdef OR1200_BIST
//
// RAM BIST
//
input scanb_rst,
scanb_si,
scanb_en,
scanb_clk;
output scanb_so;
`endif
 
`ifdef OR1200_NO_IC
 
//
97,6 → 116,9
// Insn cache not implemented
//
assign dataout = {dw{1'b0}};
`ifdef OR1200_BIST
assign scanb_so = scanb_si;
`endif
 
`else
 
109,6 → 131,14
`ifdef OR1200_IC_1W_8KB
or1200_spram_2048x32 ic_ram0(
`endif
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_si),
.scanb_so(scanb_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
`endif
.clk(clk),
.rst(rst),
.ce(en),
/trunk/or1200/rtl/verilog/or1200_top.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.8 2002/08/18 19:54:22 lampret
// Added store buffer.
//
// Revision 1.7 2002/07/14 22:17:17 lampret
// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
//
118,6 → 121,10
dbg_stall_i, dbg_dat_i, dbg_adr_i, dbg_op_i, dbg_ewt_i,
dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o, dbg_dat_o,
`ifdef OR1200_BIST
// RAM BIST
scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
`endif
// Power Management
pm_cpustall_i,
pm_clksd_o, pm_dc_gate_o, pm_ic_gate_o, pm_dmmu_gate_o,
189,7 → 196,18
output dbg_bp_o; // Breakpoint Output
output [dw-1:0] dbg_dat_o; // External Data Output
 
`ifdef OR1200_BIST
//
// RAM BIST
//
input scanb_rst,
scanb_si,
scanb_en,
scanb_clk;
output scanb_so;
`endif
 
//
// Power Management
//
input pm_cpustall_i;
357,7 → 375,22
wire [31:0] spr_dat_npc;
wire [31:0] rf_dataw;
 
`ifdef OR1200_BIST
//
// RAM BIST
//
wire scanb_immu_so;
wire scanb_ic_so;
wire scanb_dmmu_so;
wire scanb_dc_so;
wire scanb_immu_si = scanb_si;
wire scanb_ic_si = scanb_immu_so;
wire scanb_dmmu_si = scanb_ic_so;
wire scanb_dc_si = scanb_dmmu_so;
assign scanb_so = scanb_dc_so;
`endif
 
 
//
// Instantiation of Instruction WISHBONE BIU
//
440,6 → 473,15
.clk(clk_i),
.rst(rst_i),
 
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_immu_si),
.scanb_so(scanb_immu_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
`endif
 
// CPU i/f
.ic_en(ic_en),
.immu_en(immu_en),
474,6 → 516,15
.clk(clk_i),
.rst(rst_i),
 
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_ic_si),
.scanb_so(scanb_ic_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
`endif
 
// IC and CPU/IMMU
.ic_en(ic_en),
.icimmu_adr_i(icimmu_adr_immu),
587,6 → 638,15
.clk(clk_i),
.rst(rst_i),
 
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_dmmu_si),
.scanb_so(scanb_dmmu_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
`endif
 
// CPU i/f
.dc_en(dc_en),
.dmmu_en(dmmu_en),
619,6 → 679,15
.clk(clk_i),
.rst(rst_i),
 
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_dc_si),
.scanb_so(scanb_dc_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
`endif
 
// DC and CPU/DMMU
.dc_en(dc_en),
.dcdmmu_adr_i(dcdmmu_adr_dmmu),
/trunk/or1200/rtl/verilog/or1200_dmmu_tlb.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3 2002/02/11 04:33:17 lampret
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
//
// Revision 1.2 2002/01/28 01:16:00 lampret
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
//
77,6 → 80,11
// I/F for translation
tlb_en, vaddr, hit, ppn, uwe, ure, swe, sre, ci,
 
`ifdef OR1200_BIST
// RAM BIST
scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
`endif
 
// SPR access
spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o
);
107,7 → 115,18
output sre;
output ci;
 
`ifdef OR1200_BIST
//
// RAM BIST
//
input scanb_rst,
scanb_si,
scanb_en,
scanb_clk;
output scanb_so;
`endif
 
//
// SPR access
//
input spr_cs;
130,6 → 149,16
wire tlb_tr_we;
wire [`OR1200_DTLBTRW-1:0] tlb_tr_ram_in;
wire [`OR1200_DTLBTRW-1:0] tlb_tr_ram_out;
`ifdef OR1200_BIST
//
// RAM BIST
//
wire scanb_mr_so;
wire scanb_tr_so;
wire scanb_mr_si = scanb_si;
wire scanb_tr_si = scanb_mr_so;
assign scanb_so = scanb_tr_so;
`endif
 
//
// Implemented bits inside match and translate registers
215,6 → 244,14
or1200_spram_64x14 dtlb_mr_ram(
.clk(clk),
.rst(rst),
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_mr_si),
.scanb_so(scanb_mr_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
`endif
.ce(tlb_mr_en),
.we(tlb_mr_we),
.oe(1'b1),
229,6 → 266,14
or1200_spram_64x24 dtlb_tr_ram(
.clk(clk),
.rst(rst),
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_tr_si),
.scanb_so(scanb_tr_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
`endif
.ce(tlb_tr_en),
.we(tlb_tr_we),
.oe(1'b1),
/trunk/or1200/rtl/verilog/or1200_spram_512x20.v
62,6 → 62,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.10 2001/11/27 21:24:04 lampret
// Changed instantiation name of VS RAMs.
//
94,6 → 97,10
`include "or1200_defines.v"
 
module or1200_spram_512x20(
`ifdef OR1200_BIST
// RAM BIST
scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
`endif
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, do
);
104,7 → 111,18
parameter aw = 9;
parameter dw = 20;
 
`ifdef OR1200_BIST
//
// RAM BIST
//
input scanb_rst,
scanb_si,
scanb_en,
scanb_clk;
output scanb_so;
`endif
 
//
// Generic synchronous single-port RAM interface
//
input clk; // Clock
121,6 → 139,13
//
wire [3:0] unconnected;
 
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign scanb_so = scanb_si;
`endif
`endif
 
`ifdef OR1200_ARTISAN_SSP
 
//
194,8 → 219,20
`ifdef UNUSED
vs_hdsp_512x20 #(1<<aw, aw-1, dw-1) vs_ssp(
`else
`ifdef OR1200_BIST
vs_hdsp_512x20_bist vs_ssp(
`else
vs_hdsp_512x20 vs_ssp(
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_si),
.scanb_so(scanb_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
`endif
.CK(clk),
.ADR(addr),
.DI(di),

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