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https://opencores.org/ocsvn/or1k/or1k/trunk
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- This comparison shows the changes necessary to convert path
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- from Rev 1076 to Rev 1077
- ↔ Reverse comparison
Rev 1076 → Rev 1077
/trunk/or1200/rtl/verilog/or1200_defines.v
44,6 → 44,15
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.5 2002/10/28 11:09:52 igorm |
// OR1200_ASIC is automatically switched on if the fpga define is turned on in the marvin_top_defines.c |
// |
// Revision 1.4 2002/10/24 17:38:16 igorm |
// Define OR1200_BIST switched on. |
// |
// Revision 1.28 2002/10/17 20:04:40 lampret |
// Added BIST scan. Special VS RAMs need to be used to implement BIST. |
// |
// Revision 1.27 2002/09/16 03:13:23 lampret |
// Removed obsolete comment. |
// |
184,6 → 193,8
// |
// |
|
`include "marvin_top_defines.v" |
|
// |
// Dump VCD |
// |
194,7 → 205,11
// |
//`define OR1200_VERBOSE |
|
//`define OR1200_ASIC |
|
`ifdef fpga |
`else |
`define OR1200_ASIC |
`endif |
//////////////////////////////////////////////////////// |
// |
// Typical configuration for an ASIC |
208,7 → 223,7
//`define OR1200_ARTISAN_SDP |
//`define OR1200_ARTISAN_STP |
`define OR1200_VIRTUALSILICON_SSP |
`define OR1200_VIRTUALSILICON_STP_T1 |
//`define OR1200_VIRTUALSILICON_STP_T1 |
//`define OR1200_VIRTUALSILICON_STP_T2 |
|
// |
313,7 → 328,7
// Special wrapper for VS RAMs needs to be provided |
// with scan flops to facilitate bist scan. |
// |
//`define OR1200_BIST |
`define OR1200_BIST |
|
// |
// Register OR1200 WISHBONE outputs |
/trunk/or1200/rtl/verilog/or1200_spram_2048x32.v
62,6 → 62,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.2 2002/10/17 20:04:40 lampret |
// Added BIST scan. Special VS RAMs need to be used to implement BIST. |
// |
// Revision 1.1 2002/01/03 08:16:15 lampret |
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. |
// |
224,7 → 227,7
.scanb_si(scanb_si), |
.scanb_so(scanb_so), |
.scanb_en(scanb_en), |
.canb_clk(scanb_clk), |
.scanb_clk(scanb_clk), |
`endif |
.CK(clk), |
.ADR(addr), |