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https://opencores.org/ocsvn/or1k/or1k/trunk
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- This comparison shows the changes necessary to convert path
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- from Rev 1078 to Rev 1079
- ↔ Reverse comparison
Rev 1078 → Rev 1079
/trunk/or1200/rtl/verilog/or1200_immu_tlb.v
44,6 → 44,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.5 2002/10/17 20:04:40 lampret |
// Added BIST scan. Special VS RAMs need to be used to implement BIST. |
// |
// Revision 1.4 2002/08/14 06:23:50 lampret |
// Disabled ITLB translation when 1) doing access to ITLB SPRs or 2) crossing page. This modification was tested only with parts of IMMU test - remaining test cases needs to be run. |
// |
151,6 → 154,14
wire [`OR1200_ITLBTRW-1:0] tlb_tr_ram_in; |
wire [`OR1200_ITLBTRW-1:0] tlb_tr_ram_out; |
|
// BIST |
`ifdef OR1200_BIST |
wire itlb_mr_ram_si; |
wire itlb_mr_ram_so; |
wire itlb_tr_ram_si; |
wire itlb_tr_ram_so; |
`endif |
|
// |
// Implemented bits inside match and translate registers |
// |
227,6 → 238,14
// |
assign tlb_index = spr_cs ? spr_addr[`OR1200_ITLB_INDXW-1:0] : vaddr[`OR1200_ITLB_INDX]; |
|
|
`ifdef OR1200_BIST |
assign itlb_mr_ram_si = scanb_si; |
assign itlb_tr_ram_si = itlb_mr_ram_so; |
assign scanb_so = itlb_tr_ram_so; |
`endif |
|
|
// |
// Instantiation of ITLB Match Registers |
// |
236,8 → 255,8
`ifdef OR1200_BIST |
// RAM BIST |
.scanb_rst(scanb_rst), |
.scanb_si(scanb_si), |
.scanb_so(scanb_so), |
.scanb_si(itlb_mr_ram_si), |
.scanb_so(itlb_mr_ram_so), |
.scanb_en(scanb_en), |
.scanb_clk(scanb_clk), |
`endif |
258,8 → 277,8
`ifdef OR1200_BIST |
// RAM BIST |
.scanb_rst(scanb_rst), |
.scanb_si(scanb_si), |
.scanb_so(scanb_so), |
.scanb_si(itlb_tr_ram_si), |
.scanb_so(itlb_tr_ram_so), |
.scanb_en(scanb_en), |
.scanb_clk(scanb_clk), |
`endif |