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/versatile_mem_ctrl/tags/Rev2/doc/versatile_mem_ctrl.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/versatile_mem_ctrl/tags/Rev2/doc/versatile_mem_ctrl.pdf
versatile_mem_ctrl/tags/Rev2/doc/versatile_mem_ctrl.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: versatile_mem_ctrl/tags/Rev2/doc/src/tRCD.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: versatile_mem_ctrl/tags/Rev2/doc/src/tRCD.png =================================================================== --- versatile_mem_ctrl/tags/Rev2/doc/src/tRCD.png (nonexistent) +++ versatile_mem_ctrl/tags/Rev2/doc/src/tRCD.png (revision 109)
versatile_mem_ctrl/tags/Rev2/doc/src/tRCD.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: versatile_mem_ctrl/tags/Rev2/doc/src/versatile_mem_ctrl.texi =================================================================== --- versatile_mem_ctrl/tags/Rev2/doc/src/versatile_mem_ctrl.texi (nonexistent) +++ versatile_mem_ctrl/tags/Rev2/doc/src/versatile_mem_ctrl.texi (revision 109) @@ -0,0 +1,323 @@ +\input texinfo +@c -*-texinfo-*- +@c %**start of header +@setfilename versatile_mem_ctrl +@include version.texi +@settitle Versatile memory controller @value{VERSION} + +@c %**end of header + +@set DESIGN Versatile memory controller +@copying +This file documents the @value{DESIGN}. + +Copyright @copyright{} 2011 ORSoC + +@quotation +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License, Version 1.2 or +any later version published by the Free Software Foundation; with no +Invariant Sections, with no Front-Cover Texts, and with no Back-Cover +Texts. A copy of the license is included in the section entitled ``GNU +Free Documentation License''. +@end quotation +@end copying + +@afourpaper + +@titlepage +@title @value{DESIGN} User Guide +@c @subtitle subtitle-if-any +@c @subtitle second-subtitle +@author Michael Unneback +@author ORSoC + +@c The following two commands +@c start the copyright page. +@page +@vskip 0pt plus 1filll +@insertcopying + +Published by ORSoC +@end titlepage + +@c So the toc is printed at the start. +@contents + +@ifnottex +@node Top +@top Scope of this Document + +This document is the user guide for @value{DESIGN}. + +@end ifnottex + +@node Document Introduction +@chapter Introduction + +@cindex Introduction to this @value{DESIGN} + +This design implements a versatile memory controller. If used in combination with the versitale library, available from OpenCores, +different types of system can easily be designed, including use cases where the system bus is in one clock domain and the memory + controller in an other. + +@section Dependencies to other IP cores + +This design uses the following IP coreas available from OpenCores project verstile library. +@itemize @bullet +@item vl_cnt_shreg_ce_clear +@item vl_dff_ce_clear +@item vl_cnt_lfsr_zq +@item vl_dff +@item vl_o_dff +@item vl_io_dff_oe +@end itemize + +@node Block diagram +@chapter Block Diagram +@cindex Block diagram + +@section Synchronous design +@image{block-sdram} +Synchronous design where wishbone clock domain is equal to SDRAM and SDRAM controller clock domain. + +@section Asynchronous design +@image{block-sdram-wbwb} +Asynchronous design where wishbone and SDRAM clock domain are independant. A wishbone rev B3 compatilble bridge +is available in project versatile_library from OpenCores, http://www.opencores.org. + +@section Asynchronous design with multiple wishbone interfaces +@image{block-sdram-wbwb-arbiter} +Asynchronous design where wishbone and SDRAM clock domain are independant. Multiple wishbone port with use of a wishbone arbiter. + +@node SDR SDRAM controller +@chapter SDR SDRAM controller + +@section Module defines +@multitable @columnfractions .2 .8 +@headitem Name @tab Description +@item NO_BURST @tab Define if burst cycles not used +@item WRAP4 @tab Define to support 4 word wrap burst +@item WRAP8 @tab Define to support 8 word wrap burst +@item WRAP16 @tab Define to support 16 word wrap burst +@end multitable + +@section Module parameters + +@multitable @columnfractions .2 .1 .7 +@headitem Name @tab Default value @tab Description +@item ba_size @tab 2 @tab Bank adress vector size +@item row_size @tab 13 @tab Row adress vector size +@item col_size @tab 9 @tab Column adress vector size +@item cl @tab 2 @tab CAS latency +@end multitable + +Parameters ba_size, col_size and row_size should be set depending on memory configuration. The following +table holds figures for some SDRAM memories. + +@multitable @columnfractions .15 .25 .1 .1 .1 .3 +@headitem Manufacturer @tab Partnumber @tab ba_size @tab row_size @tab col_size @tab Memory size +@item Micron @tab MT48LC4M16 @tab 2 @tab 12 @tab 8 @tab 8Mbyte +@item Micron @tab MT48LC8M16 @tab 2 @tab 12 @tab 9 @tab 16Mbyte +@item Micron @tab MT48LC16M16 @tab 2 @tab 13 @tab 9 @tab 32Mbyte +@item Micron @tab MT48LC32M16 @tab 2 @tab 13 @tab 10 @tab 64Mbyte +@end multitable + +Parameter cl should be set to either 2 or 3 depending on SDRAM clock. + +@section Module IO signals +@subsection Wishbone signals +@multitable @columnfractions .2 .1 .1 .6 +@headitem Name @tab Dir @tab Width @tab Description +@item dat_i @tab I @tab 32 @tab Input data vector +@item adr_i @tab I @tab @tab Adress vector +@item sel_i @tab I @tab 4 @tab Byte select signals +@item bte_i @tab I @tab 2 @tab Bus tag identifier +@item we_i @tab I @tab 1 @tab Write enable +@item cyc_i @tab I @tab 1 @tab Active cycle indicator +@item stb_i @tab I @tab 1 @tab Strobe +@item dat_o @tab O @tab 32 @tab Output data vector +@item ack_o @tab O @tab 1 @tab Acknowledge signal +@end multitable + +Wishbone signal bte_i is optional and is only used for designs supporting burst transfer. +@subsection SDRAM signals +@multitable @columnfractions .2 .1 .1 .6 +@headitem Name @tab Dir @tab Width @tab Description +@item ba @tab O @tab ba_size @tab Bank adress vector +@item a @tab O @tab 13 @tab Adress vector +@item cmd @tab O @tab 3 @tab SDRAM command, {ras_n, cas_n, we_n} +@item cke @tab O @tab 1 @tab Clock enable +@item cs_n @tab O @tab 1 @tab Chip select, active low +@item dqm @tab O @tab 2 @tab Data mask +@item dq_i @tab I @tab 16 @tab Data input vector +@item dq_o @tab O @tab 16 @tab Data output vector +@item dq_oe @tab O @tab 1 @tab Data output enable +@end multitable + +@subsection System signals +@multitable @columnfractions .2 .1 .1 .6 +@headitem Name @tab Dir @tab Width @tab Description +@item clk @tab I @tab 1 @tab SDRAM system clock +@item rst @tab I @tab 1 @tab Asynchronous reset, active hig +@end multitable + +@node SDR SDRAM 16 bit data bus controller +@chapter SDR SDRAM 16 bit data bus controller +@cindex SDR SDRAM 16 bit data bus controller + +@section State machine implementation + +Design is based on a state machine as described below. + +@image{sdr_sdram_16,14cm,16cm,,.png} + +A counter is incremented on each cycle the state machine reside in any given state. +When changing state a counter clear is issued. The counter state vector is used for +two things +@itemize +@item controlling outputs, ie defining cmd and other control signals +@item to make sure timing reqiurements are fulfilled, ie define time from precharge to activate +@end itemize + +@subsection State - init + +The init state is responsible to make sure that a proper start-up and initialization of the SDRAM is +performed. The following sequence should be applied: +@enumerate +@item assert CKE low +@item provide stable clock +@item bring CKE high +@item perform PRECHARGE ALL command and wait for tRP +@item issue AUTO RERFESH and wait for tRFC +@item issue AUTO RERFESH and wait for tRFC +@item LOAD MODE REGISTER and wait for tMR +@end enumerate +After this state machine advances to idle state + +@subsection State - idle + +In state idle implementation awaits two different condition, appearing in order of priority +@enumerate +@item refresh request => next state is rfr +@item cyc_i & stb_i => next state is adr +@end enumerate + + +@subsection State - adr + +Depending on status of open bank and open rows choice is taken whether to precharge and activate, activate or go +directly to read write state. Reason for this as a separate state is to be able to have comparison result as a +registered signal to achive an higher clock frequency. + +@subsection State - pch + +Open row in current bank is deactivated. State machine waits in pch state to fulfill tRP. + +@subsection State - act + +Row in current bank is activated. State machine waits in act state to fulfill tRCD. + +@subsection State - rw + +A two word read or write burst is started. If wishbone cycle is of type burst column will get incremented +with possible wrap around and a new burst started for each 32 bit word. + +@section Timing + +The follwoing timing requirements must be fulfilled: + +@itemize +@item tMR - Load Mode Register period +@item tRCD - Active to read/write delay +@item tRP - Precharge command period +@item tRFC - Auto refresh period +@item tREF - refresh period +@end itemize + +In the SDRAM datasheet the above timing figures will be given in ns and should be +converted to number of clock cycles. All of the above timing figures, except tREF, are implemented as parameters +in the design and should be set depending on SDRAM figures and actual clock period. All +parameters have default values of 2 clock cycles. + +@subsection Bank/Row activation - tRCD + +@image{tRCD,15cm,5cm,,.png} + +Minimum time between activation of and read or write command. +@subsection Auto refresh mode + +@image{aref,15cm,15cm,,.png} + +Minumum time between precharge and auto refresh and active command. + +@subsection Refresh period - tREF + +The auto refresh period, tREF must be met. During auto refresh an internal address counter +is used and adress signals are treated as don't care. During the refresh period each row must +be refreshed. @* +For example consider a SDRAM with tREF = 64 ms and row size of 8K. An auto refresh command +should be issued once every 64 ms / 8192 = 7.813 us.@* +The refresh interval counter is implemented as an LFSR style counter for minimal area and maximum +performance. To accurately set the wrap value for this counter use the application VersatileCounter found +in the versatile library project at opencores. This program gives the wrap value for a given vector length. +Assuming an SDRAM clock frequency of 133 MHz which equals a period time of 7.5 ns we should issue an auto +refresh every 7.813 us / 7.5 ns = 1041 cycle. We need a state vector of 11 bits in the counter.@* +To get the wrap value we use the application@* +@command{./VersatileCounter.php 11 1041@*11111110101} + +@node Example: Timing setup +@chapter Example: Timing setup + +@section Requirements + +SDRAM device to use: +@itemize +@item Micron MT48LC32M16-7E +@end itemize + +@multitable @columnfractions .4 .2 .1 .1 .1 .1 +@headitem Parameter @tab Symbol @tab Min @tab Max @tab Unit +@item Auto refresh period @tab tRFC @tab 66 @tab - @tab ns +@item Precharge command period @tab tRP @tab 15 @tab - @tab ns +@item Active to read or write delay @tab tRCD @tab 15 @tab - @tab ns +@item Load mode register command to active or refresh @tab tMRD @tab 2 @tab - @tab tCK +@item Refresh periods (8192 rows) @tab tREF @tab 66 @tab -@tab ms +@end multitable + +Intended operating frequency is 75 MHz, tCK = 13.333 ns + +@section Parameter settings + +@multitable @columnfractions .2 .8 +@headitem Symbol @tab Value +@item tRFC @tab 5 +@item tRP @tab 2 +@item tRCD @tab 2 +@item tMRD @tab 2 +@end multitable +@* +Refresh rate is 66 ms / 8192 = 8.057 us@* +Number of clock cycles between refresh request 8.057 us / 13.333 ns = 604@* +@* +To get the wrap value we use the application from Versatile Library@* +@command{./VersatileCounter.php 10 604@*0101001110} + + +@c **************************************************************************** +@c End bits +@c **************************************************************************** + +@node GNU Free Documentation License +@chapter GNU Free Documentation License +@cindex license for @value{DESIGN} + +@include fdl.texi + +@node Index + +@unnumbered Index + +@printindex cp + +@bye Index: versatile_mem_ctrl/tags/Rev2/doc/src/aref.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: versatile_mem_ctrl/tags/Rev2/doc/src/aref.png =================================================================== --- versatile_mem_ctrl/tags/Rev2/doc/src/aref.png (nonexistent) +++ versatile_mem_ctrl/tags/Rev2/doc/src/aref.png (revision 109)
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versatile_mem_ctrl/tags/Rev2/doc/src/sdr_sdram_16.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: versatile_mem_ctrl/tags/Rev2/doc/src/sdr_sdram_16.fsm =================================================================== --- versatile_mem_ctrl/tags/Rev2/doc/src/sdr_sdram_16.fsm (nonexistent) +++ versatile_mem_ctrl/tags/Rev2/doc/src/sdr_sdram_16.fsm (revision 109) @@ -0,0 +1,75 @@ + + + + + s_out7,s_out6,s_out5,s_out4,s_out3,s_out2,s_out1,s_out0 + i_7,i_6,i_5,i_4,i_3,i_2,i_1,i_0 + o_7,o_6,o_5,o_4,o_3,o_2,o_1,o_0 + + init + idle + rfr + adr + rw + pch + act + + 0 + 1 + init_done + + + + 1 + 2 + refresh_req + + + + 1 + 3 + cyc&stb + + + + 2 + 1 + tRFC + + + + 3 + 6 + current_bank_closed + + + + 3 + 4 + current_row_open + + + + 3 + + + + + 5 + 6 + tRP + + + + 6 + 4 + tRCD + + + + 1 + end_of_cycle + + + + Index: versatile_mem_ctrl/tags/Rev2/doc/src/Makefile =================================================================== --- versatile_mem_ctrl/tags/Rev2/doc/src/Makefile (nonexistent) +++ versatile_mem_ctrl/tags/Rev2/doc/src/Makefile (revision 109) @@ -0,0 +1,9 @@ +MDIO-timing: + drawtiming --output MDIO_rd.png MDIO_rd.dt + drawtiming --output MDIO_wr.png MDIO_wr.dt + +texinfo: + texi2pdf versatile_mem_ctrl.texi + mv versatile_mem_ctrl.pdf ../ + +all: texinfo Index: versatile_mem_ctrl/tags/Rev2/doc/src/block-sdram-wbwb.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: versatile_mem_ctrl/tags/Rev2/doc/src/block-sdram-wbwb.png =================================================================== --- versatile_mem_ctrl/tags/Rev2/doc/src/block-sdram-wbwb.png (nonexistent) +++ versatile_mem_ctrl/tags/Rev2/doc/src/block-sdram-wbwb.png (revision 109)
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versatile_mem_ctrl/tags/Rev2/doc/src/block-sdram-wbwb-arbiter.odg Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: versatile_mem_ctrl/tags/Rev2/doc/src/fdl.texi =================================================================== --- versatile_mem_ctrl/tags/Rev2/doc/src/fdl.texi (nonexistent) +++ versatile_mem_ctrl/tags/Rev2/doc/src/fdl.texi (revision 109) @@ -0,0 +1,451 @@ +@c The GNU Free Documentation License. +@center Version 1.2, November 2002 + +@c This file is intended to be included within another document, +@c hence no sectioning command or @node. + +@display +Copyright @copyright{} 2000,2001,2002 Free Software Foundation, Inc. +51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA + +Everyone is permitted to copy and distribute verbatim copies +of this license document, but changing it is not allowed. +@end display + +@enumerate 0 +@item +PREAMBLE + +The purpose of this License is to make a manual, textbook, or other +functional and useful document @dfn{free} in the sense of freedom: to +assure everyone the effective freedom to copy and redistribute it, +with or without modifying it, either commercially or noncommercially. +Secondarily, this License preserves for the author and publisher a way +to get credit for their work, while not being considered responsible +for modifications made by others. + +This License is a kind of ``copyleft'', which means that derivative +works of the document must themselves be free in the same sense. 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A copy of the license is included in the section entitled ``GNU + Free Documentation License''. +@end group +@end smallexample + +If you have Invariant Sections, Front-Cover Texts and Back-Cover Texts, +replace the ``with@dots{}Texts.'' line with this: + +@smallexample +@group + with the Invariant Sections being @var{list their titles}, with + the Front-Cover Texts being @var{list}, and with the Back-Cover Texts + being @var{list}. +@end group +@end smallexample + +If you have Invariant Sections without Cover Texts, or some other +combination of the three, merge those two alternatives to suit the +situation. + +If your document contains nontrivial examples of program code, we +recommend releasing these examples in parallel under your choice of +free software license, such as the GNU General Public License, +to permit their use in free software. + +@c Local Variables: +@c ispell-local-pdict: "ispell-dict" +@c End: + Index: versatile_mem_ctrl/tags/Rev2/doc/src/version.texi =================================================================== --- versatile_mem_ctrl/tags/Rev2/doc/src/version.texi (nonexistent) +++ versatile_mem_ctrl/tags/Rev2/doc/src/version.texi (revision 109) @@ -0,0 +1,4 @@ +@set UPDATED 27 December 2010 +@set UPDATED-MONTH December 2010 +@set EDITION 1 +@set VERSION 1.0 Index: versatile_mem_ctrl/tags/Rev2/doc/src/sdr_16.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: versatile_mem_ctrl/tags/Rev2/doc/src/sdr_16.png =================================================================== --- versatile_mem_ctrl/tags/Rev2/doc/src/sdr_16.png (nonexistent) +++ versatile_mem_ctrl/tags/Rev2/doc/src/sdr_16.png (revision 109)
versatile_mem_ctrl/tags/Rev2/doc/src/sdr_16.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: versatile_mem_ctrl/tags/Rev2/doc/src/versatile_mem_ctrl.odt =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: versatile_mem_ctrl/tags/Rev2/doc/src/versatile_mem_ctrl.odt =================================================================== --- versatile_mem_ctrl/tags/Rev2/doc/src/versatile_mem_ctrl.odt (nonexistent) +++ versatile_mem_ctrl/tags/Rev2/doc/src/versatile_mem_ctrl.odt (revision 109)
versatile_mem_ctrl/tags/Rev2/doc/src/versatile_mem_ctrl.odt Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: versatile_mem_ctrl/tags/Rev2/doc/src/sdr_16.fzm =================================================================== --- versatile_mem_ctrl/tags/Rev2/doc/src/sdr_16.fzm (nonexistent) +++ versatile_mem_ctrl/tags/Rev2/doc/src/sdr_16.fzm (revision 109) @@ -0,0 +1,2981 @@ +## File last modified by Fizzim: 3:05:51 PM on 4/9/10 + + 9.10.05 + + + + + + ABS + + + fsm_sdr_16 + + GLOBAL_VAR + + + + 0 + + GLOBAL_VAR + + + + + + GLOBAL_VAR + + + + + + GLOBAL_VAR + + + + -16777216 + + GLOBAL_VAR + + + + 0 + + + 0 + + + -1 + + + + + ABS + + + sdram_clk + + GLOBAL_VAR + + + + 0 + + GLOBAL_VAR + + + + posedge + + GLOBAL_VAR + + + + + + GLOBAL_VAR + + + + -16777216 + + GLOBAL_VAR + + + + 0 + + + 0 + + + -1 + + + + + + + + + + + ABS + + + def_name + + GLOBAL_VAR + + + + 1 + + GLOBAL_VAR + + + + def_type + + GLOBAL_VAR + + + + + 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versatile_mem_ctrl/tags/Rev2/doc/src/block.dia =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: versatile_mem_ctrl/tags/Rev2/doc/src/block.dia =================================================================== --- versatile_mem_ctrl/tags/Rev2/doc/src/block.dia (nonexistent) +++ versatile_mem_ctrl/tags/Rev2/doc/src/block.dia (revision 109)
versatile_mem_ctrl/tags/Rev2/doc/src/block.dia Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: versatile_mem_ctrl/tags/Rev2/rtl/verilog/sdr_sdram_16_ctrl.v =================================================================== --- versatile_mem_ctrl/tags/Rev2/rtl/verilog/sdr_sdram_16_ctrl.v (nonexistent) +++ versatile_mem_ctrl/tags/Rev2/rtl/verilog/sdr_sdram_16_ctrl.v (revision 109) @@ -0,0 +1,347 @@ +`timescale 1ns/1ns +module sdr_sdram_16_ctrl ( + // wisbone i/f +`ifdef NO_BURST + dat_i, adr_i, sel_i, we_i, cyc_i, stb_i, dat_o, ack_o, +`else + dat_i, adr_i, sel_i, bte_i, we_i, cyc_i, stb_i, dat_o, ack_o, +`endif + // SDR SDRAM + ba, a, cmd, cke, cs_n, dqm, dq_i, dq_o, dq_oe, + // system + clk, rst); + + // memory geometry parameters + parameter ba_size = 2; + parameter row_size = 13; + parameter col_size = 9; + parameter cl = 2; + // memory timing parameters + parameter tRFC = 9; + parameter tRP = 2; + parameter tRCD = 2; + parameter tMRD = 2; + + // LMR + // [12:10] reserved + // [9] WB, write burst; 0 - programmed burst length, 1 - single location + // [8:7] OP Mode, 2'b00 + // [6:4] CAS Latency; 3'b010 - 2, 3'b011 - 3 + // [3] BT, Burst Type; 1'b0 - sequential, 1'b1 - interleaved + // [2:0] Burst length; 3'b000 - 1, 3'b001 - 2, 3'b010 - 4, 3'b011 - 8, 3'b111 - full page + parameter init_wb = 1'b0; + parameter init_cl = (cl==2) ? 3'b010 : 3'b011; + parameter init_bt = 1'b0; + parameter init_bl = 3'b001; + + input [31:0] dat_i; + input [ba_size+col_size+row_size:1] adr_i; + input [3:0] sel_i; +`ifndef NO_BURST + input [1:0] bte_i; +`endif + input we_i, cyc_i, stb_i; + output [31:0] dat_o; + output ack_o; + + output [ba_size-1:0] ba; + output reg [12:0] a; + output reg [2:0] cmd; // {ras,cas,we} + output cke, cs_n; + output reg [1:0] dqm; + output [15:0] dq_o; + output reg dq_oe; + input [15:0] dq_i; + + input clk, rst; + + wire [ba_size-1:0] bank; + wire [row_size-1:0] row; + wire [col_size-1:0] col; + wire [12:0] col_a10_fix; +`ifdef BEAT16 + parameter col_reg_width = 5; + reg [4:0] col_reg; +`else +`ifdef BEAT8 + parameter col_reg_width = 4; + reg [3:0] col_reg; +`else +`ifdef BEAT4 + parameter col_reg_width = 3; + reg [2:0] col_reg; +`endif +`endif +`endif + wire [0:31] shreg; + wire count0; + wire stall; // active if write burst need data + wire ref_cnt_zero; + reg refresh_req; + + wire ack_rd, rd_ack_emptyflag; + wire ack_wr; + + // to keep track of open rows per bank + reg [row_size-1:0] open_row[0:3]; + reg [0:3] open_ba; + reg current_bank_closed, current_row_open; + +`ifndef RFR_WRAP_VALUE + parameter rfr_length = 10; + parameter rfr_wrap_value = 1010; +`else + parameter rfr_length = `RFR_LENGTH; + parameter rfr_wrap_value = `RFR_WRAP_VALUE; +`endif + + // cti + parameter [2:0] classic = 3'b000, + endofburst = 3'b111; + + // bte + parameter [1:0] linear = 2'b00, + beat4 = 2'b01, + beat8 = 2'b10, + beat16 = 2'b11; + + parameter [2:0] cmd_nop = 3'b111, + cmd_act = 3'b011, + cmd_rd = 3'b101, + cmd_wr = 3'b100, + cmd_pch = 3'b010, + cmd_rfr = 3'b001, + cmd_lmr = 3'b000; + +// ctrl FSM +`define FSM_INIT 3'b000 +`define FSM_IDLE 3'b001 +`define FSM_RFR 3'b010 +`define FSM_ADR 3'b011 +`define FSM_PCH 3'b100 +`define FSM_ACT 3'b101 +`define FSM_RW 3'b111 + + assign cke = 1'b1; + assign cs_n = 1'b0; + + reg [2:0] state, next; + + function [12:0] a10_fix; + input [col_size-1:0] a; + integer i; + begin + for (i=0;i<13;i=i+1) begin + if (i<10) + if (i sdr_sdram_16_ctrl_actel.v + +export: + svn export http://opencores.org/ocsvn/versatile_library/versatile_library/trunk/rtl/verilog/versatile_library.v + +# the single all rule +all: sdr_sdram_16_ctrl_actel.v + +clean: + rm -rf $(VERSATILE_FIFO_PROJECT_FILES) $(VERSATILE_COUNTER_PROJECT_FILES) + rm -rf fifo_fill.v sdr_16.v ddr_16.v + rm -f versatile_fifo_dual_port_ram_dc_dw.v ddr_16_generated.v + rm -rf *_counter.v + rm -rf *.csv + rm -rf *~ + rm -rf sdr_sdram_16_ctrl_actel.v Index: versatile_mem_ctrl/tags/Rev2/rtl/verilog/copyright.v =================================================================== --- versatile_mem_ctrl/tags/Rev2/rtl/verilog/copyright.v (nonexistent) +++ versatile_mem_ctrl/tags/Rev2/rtl/verilog/copyright.v (revision 109) @@ -0,0 +1,41 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Versatile memory controller //// +//// //// +//// Description //// +//// A modular wishbone compatible memory controller with support//// +//// for various types of memory configurations //// +//// //// +//// To Do: //// +//// - add support for additional SDRAM variants //// +//// //// +//// Author(s): //// +//// - Michael Unneback, unneback@opencores.org //// +//// ORSoC AB //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2009 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// Index: versatile_mem_ctrl/tags/Rev2/bench/tb.v =================================================================== --- versatile_mem_ctrl/tags/Rev2/bench/tb.v (nonexistent) +++ versatile_mem_ctrl/tags/Rev2/bench/tb.v (revision 109) @@ -0,0 +1,222 @@ +//`include "tb_defines.v" +`timescale 1ns/1ns +module versatile_mem_ctrl_tb + ( + output OK + ); + +`ifdef NR_OF_WBM + parameter nr_of_wbm = `NR_OF_WBM; +`else + parameter nr_of_wbm = 1; +`endif + +`ifdef SDRAM_CLK_PERIOD + parameter sdram_clk_period = `SDRAM_CLK_PERIOD; +`else + parameter sdram_clk_period = 8; +`endif + +`ifdef WB_CLK_PERIODS + parameter [1:nr_of_wbm] wb_clk_periods = {`WB_CLK_PERIODS}; +`else + parameter [1:nr_of_wbm] wb_clk_periods = (20); +`endif + parameter wb_clk_period = 20; + + wire [31:0] wbm_a_dat_o; + wire [3:0] wbm_a_sel_o; + wire [31:0] wbm_a_adr_o; + wire [2:0] wbm_a_cti_o; + wire [1:0] wbm_a_bte_o; + wire wbm_a_we_o ; + wire wbm_a_cyc_o; + wire wbm_a_stb_o; + wire [31:0] wbm_a_dat_i; + wire wbm_a_ack_i; + reg wbm_a_clk ; + reg wbm_a_rst ; + + wire [31:0] wbm_b_dat_o; + wire [3:0] wbm_b_sel_o; + wire [31:2] wbm_b_adr_o; + wire [2:0] wbm_b_cti_o; + wire [1:0] wbm_b_bte_o; + wire wbm_b_we_o ; + wire wbm_b_cyc_o; + wire wbm_b_stb_o; + wire [31:0] wbm_b_dat_i; + wire wbm_b_ack_i; + + wire [31:0] wb_sdram_dat_i; + wire [3:0] wb_sdram_sel_i; + wire [31:2] wb_sdram_adr_i; + wire [2:0] wb_sdram_cti_i; + wire [1:0] wb_sdram_bte_i; + wire wb_sdram_we_i; + wire wb_sdram_cyc_i; + wire wb_sdram_stb_i; + wire [31:0] wb_sdram_dat_o; + wire wb_sdram_ack_o; + reg wb_sdram_clk; + reg wb_sdram_rst; + + wire wbm_OK; + + genvar i; + +`define DUT sdr_sdram_16_ctrl +`define SDR 16 +`ifdef SDR + wire [1:0] ba, ba_pad; + wire [12:0] a, a_pad; + wire [`SDR-1:0] dq_i, dq_o, dq_pad; + wire dq_oe; + wire [1:0] dqm, dqm_pad; + wire cke, cke_pad, cs_n, cs_n_pad, ras, ras_pad, cas, cas_pad, we, we_pad; + + vl_o_dff # ( .width(20), .reset_value({2'b00, 13'h0,3'b111,2'b11})) o0( + .d_i({ba,a,ras,cas,we,dqm}), + .o_pad({ba_pad,a_pad,ras_pad, cas_pad, we_pad, dqm_pad}), + .clk(wb_sdram_clk), + .rst(wb_sdram_rst)); + /* + assign #1 {ba_pad,a_pad} = {ba,a}; + assign #1 {ras_pad, cas_pad, we_pad} = {ras,cas,we}; + assign #1 dqm_pad = dqm;*/ + assign #1 cke_pad = cke; + assign cs_n_pad = cs_n; + vl_io_dff_oe # ( .width(16)) io0 ( + .d_i(dq_i), + .d_o(dq_o), + .oe(dq_oe), + .io_pad(dq_pad), + .clk(wb_sdram_clk), + .rst(wb_sdram_rst)); + + mt48lc16m16a2 mem( + .Dq(dq_pad), + .Addr(a_pad), + .Ba(ba_pad), + .Clk(wb_sdram_clk), + .Cke(cke_pad), + .Cs_n(cs_n_pad), + .Ras_n(ras_pad), + .Cas_n(cas_pad), + .We_n(we_pad), + .Dqm(dqm_pad)); + + `DUT + # (.tRFC(9), .cl(3)) + DUT( + // wisbone i/f + .dat_i(wbm_b_dat_o), + .adr_i({wbm_b_adr_o[24:2],1'b0}), + .sel_i(wbm_b_sel_o), +`ifndef NO_BURST + .bte_i(wbm_b_bte_o), +`endif + .we_i (wbm_b_we_o), + .cyc_i(wbm_b_cyc_o), + .stb_i(wbm_b_stb_o), + .dat_o(wbm_b_dat_i), + .ack_o(wbm_b_ack_i), + // SDR SDRAM + .ba(ba), + .a(a), + .cmd({ras, cas, we}), + .cke(cke), + .cs_n(cs_n), + .dqm(dqm), + .dq_i(dq_i), + .dq_o(dq_o), + .dq_oe(dq_oe), + // system + .clk(wb_sdram_clk), .rst(wb_sdram_rst)); + +`endif + +// wishbone master + + wbm wbmi( + .adr_o(wbm_a_adr_o), + .bte_o(wbm_a_bte_o), + .cti_o(wbm_a_cti_o), + .dat_o(wbm_a_dat_o), + .sel_o(wbm_a_sel_o), + .we_o (wbm_a_we_o), + .cyc_o(wbm_a_cyc_o), + .stb_o(wbm_a_stb_o), + .dat_i(wbm_a_dat_i), + .ack_i(wbm_a_ack_i), + .clk(wbm_a_clk), + .reset(wbm_a_rst), + .OK(wbm_OK) +); + + vl_wb3wb3_bridge wbwb_bridgei ( + // wishbone slave side + .wbs_dat_i(wbm_a_dat_o), + .wbs_adr_i(wbm_a_adr_o[31:2]), + .wbs_sel_i(wbm_a_sel_o), + .wbs_bte_i(wbm_a_bte_o), + .wbs_cti_i(wbm_a_cti_o), + .wbs_we_i (wbm_a_we_o), + .wbs_cyc_i(wbm_a_cyc_o), + .wbs_stb_i(wbm_a_stb_o), + .wbs_dat_o(wbm_a_dat_i), + .wbs_ack_o(wbm_a_ack_i), + .wbs_clk(wbm_a_clk), + .wbs_rst(wbm_a_rst), + // wishbone master side + .wbm_dat_o(wbm_b_dat_o), + .wbm_adr_o(wbm_b_adr_o), + .wbm_sel_o(wbm_b_sel_o), + .wbm_bte_o(wbm_b_bte_o), + .wbm_cti_o(wbm_b_cti_o), + .wbm_we_o (wbm_b_we_o), + .wbm_cyc_o(wbm_b_cyc_o), + .wbm_stb_o(wbm_b_stb_o), + .wbm_dat_i(wbm_b_dat_i), + .wbm_ack_i(wbm_b_ack_i), + .wbm_clk(wb_sdram_clk), + .wbm_rst(wb_sdram_rst)); + + + + assign OK = wbm_OK; + + + // Wishbone reset + initial + begin + #0 wbm_a_rst = 1'b1; + #200 wbm_a_rst = 1'b0; + end + + // Wishbone clock + initial + begin + #0 wbm_a_clk = 1'b0; + forever + #(wb_clk_period/2) wbm_a_clk = !wbm_a_clk; + end + + + + // SDRAM reset + initial + begin + #0 wb_sdram_rst = 1'b1; + #200 wb_sdram_rst = 1'b0; + end + + // SDRAM clock + initial + begin + #0 wb_sdram_clk = 1'b0; + forever + #(sdram_clk_period/2) wb_sdram_clk = !wb_sdram_clk; + end + +endmodule // versatile_mem_ctrl_tb
versatile_mem_ctrl/tags/Rev2/bench/tb.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: versatile_mem_ctrl/tags/Rev2/bench/wbm.v =================================================================== --- versatile_mem_ctrl/tags/Rev2/bench/wbm.v (nonexistent) +++ versatile_mem_ctrl/tags/Rev2/bench/wbm.v (revision 109) @@ -0,0 +1,144 @@ +`timescale 1ns/1ns +module wbm ( + output [31:0] adr_o, + output [1:0] bte_o, + output [2:0] cti_o, + output [31:0] dat_o, + output [3:0] sel_o, + output we_o, + output cyc_o, + output stb_o, + input wire [31:0] dat_i, + input wire ack_i, + input wire clk, + input wire reset, + output reg OK +); + + parameter [1:0] linear = 2'b00, + beat4 = 2'b01, + beat8 = 2'b10, + beat16 = 2'b11; + + parameter [2:0] classic = 3'b000, + inc = 3'b010, + eob = 3'b111; + + parameter instructions = 32; + + // {adr_o,bte_o,cti_o,dat_o,sel_o,we_o,cyc_o,stb_o} + parameter [32+2+3+32+4+1+1+1:1] inst_rom [0:instructions-1]= { + {32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0}, + + {32'h100,linear,classic,32'h12345678,4'b1111,1'b1,1'b1,1'b1}, // write 0x12345678 @ 0x100 + {32'h100,linear,classic,32'h0,4'b1111,1'b0,1'b1,1'b1}, // read @ 0x100 + + {32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0}, + + {32'hA000,beat4,inc,32'h00010002,4'b1111,1'b1,1'b1,1'b1}, // write burst + {32'hA004,beat4,inc,32'h00030004,4'b1111,1'b1,1'b1,1'b1}, + {32'hA008,beat4,inc,32'h00050006,4'b1111,1'b1,1'b1,1'b1}, + {32'hA00C,beat4,eob,32'h00070008,4'b1111,1'b1,1'b1,1'b1}, + + {32'hA008,linear,classic,32'hA1FFFFFF,4'b1000,1'b1,1'b1,1'b1},// write byte + + {32'hA000,beat4,inc,32'h0,4'b1111,1'b0,1'b1,1'b1}, // read burst + {32'hA004,beat4,inc,32'h0,4'b1111,1'b0,1'b1,1'b1}, + {32'hA008,beat4,inc,32'h0,4'b1111,1'b0,1'b1,1'b1}, + {32'hA00C,beat4,eob,32'h0,4'b1111,1'b0,1'b1,1'b1}, + + {32'h1000,linear,inc,32'hdeaddead,4'b1111,1'b1,1'b1,1'b1}, // write + {32'h1004,linear,eob,32'h55555555,4'b1111,1'b1,1'b1,1'b1}, // + + {32'h1000,linear,inc,32'h0,4'b1111,1'b0,1'b1,1'b1}, // read + {32'h1004,linear,eob,32'h0,4'b1111,1'b0,1'b1,1'b1}, // read + + {32'hA008,beat4,inc,32'h0,4'b1111,1'b0,1'b1,1'b1}, // read burst + {32'hA00C,beat4,inc,32'h0,4'b1111,1'b0,1'b1,1'b1}, + {32'hA000,beat4,inc,32'h0,4'b1111,1'b0,1'b1,1'b1}, + {32'hA004,beat4,eob,32'h0,4'b1111,1'b0,1'b1,1'b1}, + + {32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0}, + {32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0}, + {32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0}, + {32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0}, + {32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0}, + {32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0}, + {32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0}, + {32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0}, + {32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0}, + {32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0}}; + + parameter [31:0] dat [0:instructions-1] = { + 32'h0, + 32'h0, + 32'h0, + 32'h12345678, + 32'h0, + 32'h0, + 32'h0, + 32'h0, + 32'h0, + 32'h0, + 32'h00010002, + 32'h00030004, + 32'ha1050006, + 32'h00070008, + 32'h0, + 32'h0, + 32'hdeaddead, + 32'h55555555, + 32'ha1050006, + 32'h00070008, + 32'h00010002, + 32'h00030004, + 32'h0, + 32'h0, + 32'h0, + 32'h0, + 32'h0, + 32'h0, + 32'h0, + 32'h0, + 32'h0, + 32'h0, + 32'h0}; + +// parameter idle = 1'b0; +// parameter active = 1'b1; +// +// reg state; + + integer i; + + assign {adr_o,bte_o,cti_o,dat_o,sel_o,we_o,cyc_o,stb_o} = inst_rom[i]; + + always @ (posedge clk or posedge reset) + if (reset) + i = 0; + else + if ((!stb_o | ack_i) & i < instructions - 1) + i = i + 1; + + always @ (posedge clk or posedge reset) + if (reset) + OK <= 1'b1; + else + if (ack_i & !we_o & (dat_i != dat[i])) begin + OK <= 1'b0; + $display ("wrong read value %h @ %h at %t", dat_i, adr_o, $time); + end else if (ack_i & !we_o & (dat_i == dat[i])) + $display ("read value %h @ %h at %t", dat_i, adr_o, $time); + else if (ack_i) + $display ("write value %h %b @ %h at %t", dat_o, sel_o, adr_o, $time); + +// always @ (posedge clk or posedge reset) +// if (reset) +// state <= idle; +// else +// if (state==idle & cyc_o) +// state <= active; +// else if ((cti_o==3'b000 | cti_o==3'b111) & cyc_o & stb_o & ack_i) +// state <= idle; + +endmodule Index: versatile_mem_ctrl/tags/Rev2/bench/mt48lc16m16a2.v =================================================================== --- versatile_mem_ctrl/tags/Rev2/bench/mt48lc16m16a2.v (nonexistent) +++ versatile_mem_ctrl/tags/Rev2/bench/mt48lc16m16a2.v (revision 109) @@ -0,0 +1,1072 @@ +/************************************************************************** +* +* File Name: MT48LC16M16A2.V +* Version: 2.1 +* Date: June 6th, 2002 +* Model: BUS Functional +* Simulator: Model Technology +* +* Dependencies: None +* +* Email: modelsupport@micron.com +* Company: Micron Technology, Inc. +* Model: MT48LC16M16A2 (4Meg x 16 x 4 Banks) +* +* Description: Micron 256Mb SDRAM Verilog model +* +* Limitation: - Doesn't check for 8192 cycle refresh +* +* Note: - Set simulator resolution to "ps" accuracy +* - Set Debug = 0 to disable $display messages +* +* Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY +* WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY +* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR +* A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT. +* +* Copyright © 2001 Micron Semiconductor Products, Inc. +* All rights researved +* +* Rev Author Date Changes +* --- -------------------------- --------------------------------------- +* 2.1 SH 06/06/2002 - Typo in bank multiplex +* Micron Technology Inc. +* +* 2.0 SH 04/30/2002 - Second release +* Micron Technology Inc. +* +**************************************************************************/ + +`timescale 1ns / 1ps + +module mt48lc16m16a2 (Dq, Addr, Ba, Clk, Cke, Cs_n, Ras_n, Cas_n, We_n, Dqm); + + parameter addr_bits = 13; + parameter data_bits = 16; + parameter col_bits = 9; + parameter mem_sizes = 4194303; + + inout [data_bits - 1 : 0] Dq; + input [addr_bits - 1 : 0] Addr; + input [1 : 0] Ba; + input Clk; + input Cke; + input Cs_n; + input Ras_n; + input Cas_n; + input We_n; + input [1 : 0] Dqm; + + reg [data_bits - 1 : 0] Bank0 [0 : mem_sizes]; + reg [data_bits - 1 : 0] Bank1 [0 : mem_sizes]; + reg [data_bits - 1 : 0] Bank2 [0 : mem_sizes]; + reg [data_bits - 1 : 0] Bank3 [0 : mem_sizes]; + + reg [1 : 0] Bank_addr [0 : 3]; // Bank Address Pipeline + reg [col_bits - 1 : 0] Col_addr [0 : 3]; // Column Address Pipeline + reg [3 : 0] Command [0 : 3]; // Command Operation Pipeline + reg [1 : 0] Dqm_reg0, Dqm_reg1; // DQM Operation Pipeline + reg [addr_bits - 1 : 0] B0_row_addr, B1_row_addr, B2_row_addr, B3_row_addr; + + reg [addr_bits - 1 : 0] Mode_reg; + reg [data_bits - 1 : 0] Dq_reg, Dq_dqm; + reg [col_bits - 1 : 0] Col_temp, Burst_counter; + + reg Act_b0, Act_b1, Act_b2, Act_b3; // Bank Activate + reg Pc_b0, Pc_b1, Pc_b2, Pc_b3; // Bank Precharge + + reg [1 : 0] Bank_precharge [0 : 3]; // Precharge Command + reg A10_precharge [0 : 3]; // Addr[10] = 1 (All banks) + reg Auto_precharge [0 : 3]; // RW Auto Precharge (Bank) + reg Read_precharge [0 : 3]; // R Auto Precharge + reg Write_precharge [0 : 3]; // W Auto Precharge + reg RW_interrupt_read [0 : 3]; // RW Interrupt Read with Auto Precharge + reg RW_interrupt_write [0 : 3]; // RW Interrupt Write with Auto Precharge + reg [1 : 0] RW_interrupt_bank; // RW Interrupt Bank + integer RW_interrupt_counter [0 : 3]; // RW Interrupt Counter + integer Count_precharge [0 : 3]; // RW Auto Precharge Counter + + reg Data_in_enable; + reg Data_out_enable; + + reg [1 : 0] Bank, Prev_bank; + reg [addr_bits - 1 : 0] Row; + reg [col_bits - 1 : 0] Col, Col_brst; + + // Internal system clock + reg CkeZ, Sys_clk; + + // Commands Decode + wire Active_enable = ~Cs_n & ~Ras_n & Cas_n & We_n; + wire Aref_enable = ~Cs_n & ~Ras_n & ~Cas_n & We_n; + wire Burst_term = ~Cs_n & Ras_n & Cas_n & ~We_n; + wire Mode_reg_enable = ~Cs_n & ~Ras_n & ~Cas_n & ~We_n; + wire Prech_enable = ~Cs_n & ~Ras_n & Cas_n & ~We_n; + wire Read_enable = ~Cs_n & Ras_n & ~Cas_n & We_n; + wire Write_enable = ~Cs_n & Ras_n & ~Cas_n & ~We_n; + + // Burst Length Decode + wire Burst_length_1 = ~Mode_reg[2] & ~Mode_reg[1] & ~Mode_reg[0]; + wire Burst_length_2 = ~Mode_reg[2] & ~Mode_reg[1] & Mode_reg[0]; + wire Burst_length_4 = ~Mode_reg[2] & Mode_reg[1] & ~Mode_reg[0]; + wire Burst_length_8 = ~Mode_reg[2] & Mode_reg[1] & Mode_reg[0]; + wire Burst_length_f = Mode_reg[2] & Mode_reg[1] & Mode_reg[0]; + + // CAS Latency Decode + wire Cas_latency_2 = ~Mode_reg[6] & Mode_reg[5] & ~Mode_reg[4]; + wire Cas_latency_3 = ~Mode_reg[6] & Mode_reg[5] & Mode_reg[4]; + + // Write Burst Mode + wire Write_burst_mode = Mode_reg[9]; + + wire Debug = 1'b0; // Debug messages : 1 = On + wire Dq_chk = Sys_clk & Data_in_enable; // Check setup/hold time for DQ + + assign Dq = Dq_reg; // DQ buffer + + // Commands Operation + `define ACT 0 + `define NOP 1 + `define READ 2 + `define WRITE 3 + `define PRECH 4 + `define A_REF 5 + `define BST 6 + `define LMR 7 + + // Timing Parameters for -7E PC133 CL2 + parameter tAC = 5.4; + parameter tHZ = 5.4; + parameter tOH = 3.0; + parameter tMRD = 2.0; // 2 Clk Cycles + parameter tRAS = 37.0; + parameter tRC = 60.0; + parameter tRCD = 15.0; + parameter tRFC = 66.0; + parameter tRP = 15.0; + parameter tRRD = 14.0; + parameter tWRa = 7.0; // A2 Version - Auto precharge mode (1 Clk + 7 ns) + parameter tWRm = 14.0; // A2 Version - Manual precharge mode (14 ns) + + // Timing Check variable + time MRD_chk; + time WR_chkm [0 : 3]; + time RFC_chk, RRD_chk; + time RC_chk0, RC_chk1, RC_chk2, RC_chk3; + time RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3; + time RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3; + time RP_chk0, RP_chk1, RP_chk2, RP_chk3; + + initial begin + Dq_reg = {data_bits{1'bz}}; + Data_in_enable = 0; Data_out_enable = 0; + Act_b0 = 1; Act_b1 = 1; Act_b2 = 1; Act_b3 = 1; + Pc_b0 = 0; Pc_b1 = 0; Pc_b2 = 0; Pc_b3 = 0; + WR_chkm[0] = 0; WR_chkm[1] = 0; WR_chkm[2] = 0; WR_chkm[3] = 0; + RW_interrupt_read[0] = 0; RW_interrupt_read[1] = 0; RW_interrupt_read[2] = 0; RW_interrupt_read[3] = 0; + RW_interrupt_write[0] = 0; RW_interrupt_write[1] = 0; RW_interrupt_write[2] = 0; RW_interrupt_write[3] = 0; + MRD_chk = 0; RFC_chk = 0; RRD_chk = 0; + RAS_chk0 = 0; RAS_chk1 = 0; RAS_chk2 = 0; RAS_chk3 = 0; + RCD_chk0 = 0; RCD_chk1 = 0; RCD_chk2 = 0; RCD_chk3 = 0; + RC_chk0 = 0; RC_chk1 = 0; RC_chk2 = 0; RC_chk3 = 0; + RP_chk0 = 0; RP_chk1 = 0; RP_chk2 = 0; RP_chk3 = 0; + $timeformat (-9, 1, " ns", 12); + end + + // System clock generator + always begin + @ (posedge Clk) begin + Sys_clk = CkeZ; + CkeZ = Cke; + end + @ (negedge Clk) begin + Sys_clk = 1'b0; + end + end + + always @ (posedge Sys_clk) begin + // Internal Commamd Pipelined + Command[0] = Command[1]; + Command[1] = Command[2]; + Command[2] = Command[3]; + Command[3] = `NOP; + + Col_addr[0] = Col_addr[1]; + Col_addr[1] = Col_addr[2]; + Col_addr[2] = Col_addr[3]; + Col_addr[3] = {col_bits{1'b0}}; + + Bank_addr[0] = Bank_addr[1]; + Bank_addr[1] = Bank_addr[2]; + Bank_addr[2] = Bank_addr[3]; + Bank_addr[3] = 2'b0; + + Bank_precharge[0] = Bank_precharge[1]; + Bank_precharge[1] = Bank_precharge[2]; + Bank_precharge[2] = Bank_precharge[3]; + Bank_precharge[3] = 2'b0; + + A10_precharge[0] = A10_precharge[1]; + A10_precharge[1] = A10_precharge[2]; + A10_precharge[2] = A10_precharge[3]; + A10_precharge[3] = 1'b0; + + // Dqm pipeline for Read + Dqm_reg0 = Dqm_reg1; + Dqm_reg1 = Dqm; + + // Read or Write with Auto Precharge Counter + if (Auto_precharge[0] === 1'b1) begin + Count_precharge[0] = Count_precharge[0] + 1; + end + if (Auto_precharge[1] === 1'b1) begin + Count_precharge[1] = Count_precharge[1] + 1; + end + if (Auto_precharge[2] === 1'b1) begin + Count_precharge[2] = Count_precharge[2] + 1; + end + if (Auto_precharge[3] === 1'b1) begin + Count_precharge[3] = Count_precharge[3] + 1; + end + + // Read or Write Interrupt Counter + if (RW_interrupt_write[0] === 1'b1) begin + RW_interrupt_counter[0] = RW_interrupt_counter[0] + 1; + end + if (RW_interrupt_write[1] === 1'b1) begin + RW_interrupt_counter[1] = RW_interrupt_counter[1] + 1; + end + if (RW_interrupt_write[2] === 1'b1) begin + RW_interrupt_counter[2] = RW_interrupt_counter[2] + 1; + end + if (RW_interrupt_write[3] === 1'b1) begin + RW_interrupt_counter[3] = RW_interrupt_counter[3] + 1; + end + + // tMRD Counter + MRD_chk = MRD_chk + 1; + + // Auto Refresh + if (Aref_enable === 1'b1) begin + if (Debug) begin + $display ("%m : at time %t AREF : Auto Refresh", $time); + end + + // Auto Refresh to Auto Refresh + if ($time - RFC_chk < tRFC) begin + $display ("%m : at time %t ERROR: tRFC violation during Auto Refresh", $time); + end + + // Precharge to Auto Refresh + if (($time - RP_chk0 < tRP) || ($time - RP_chk1 < tRP) || + ($time - RP_chk2 < tRP) || ($time - RP_chk3 < tRP)) begin + $display ("%m : at time %t ERROR: tRP violation during Auto Refresh", $time); + end + + // Precharge to Refresh + if (Pc_b0 === 1'b0 || Pc_b1 === 1'b0 || Pc_b2 === 1'b0 || Pc_b3 === 1'b0) begin + $display ("%m : at time %t ERROR: All banks must be Precharge before Auto Refresh", $time); + end + + // Load Mode Register to Auto Refresh + if (MRD_chk < tMRD) begin + $display ("%m : at time %t ERROR: tMRD violation during Auto Refresh", $time); + end + + // Record Current tRFC time + RFC_chk = $time; + end + + // Load Mode Register + if (Mode_reg_enable === 1'b1) begin + // Register Mode + Mode_reg = Addr; + + // Decode CAS Latency, Burst Length, Burst Type, and Write Burst Mode + if (Debug) begin + $display ("%m : at time %t LMR : Load Mode Register", $time); + // CAS Latency + case (Addr[6 : 4]) + 3'b010 : $display ("%m : CAS Latency = 2"); + 3'b011 : $display ("%m : CAS Latency = 3"); + default : $display ("%m : CAS Latency = Reserved"); + endcase + + // Burst Length + case (Addr[2 : 0]) + 3'b000 : $display ("%m : Burst Length = 1"); + 3'b001 : $display ("%m : Burst Length = 2"); + 3'b010 : $display ("%m : Burst Length = 4"); + 3'b011 : $display ("%m : Burst Length = 8"); + 3'b111 : $display ("%m : Burst Length = Full"); + default : $display ("%m : Burst Length = Reserved"); + endcase + + // Burst Type + if (Addr[3] === 1'b0) begin + $display ("%m : Burst Type = Sequential"); + end else if (Addr[3] === 1'b1) begin + $display ("%m : Burst Type = Interleaved"); + end else begin + $display ("%m : Burst Type = Reserved"); + end + + // Write Burst Mode + if (Addr[9] === 1'b0) begin + $display ("%m : Write Burst Mode = Programmed Burst Length"); + end else if (Addr[9] === 1'b1) begin + $display ("%m : Write Burst Mode = Single Location Access"); + end else begin + $display ("%m : Write Burst Mode = Reserved"); + end + end + + // Precharge to Load Mode Register + if (Pc_b0 === 1'b0 && Pc_b1 === 1'b0 && Pc_b2 === 1'b0 && Pc_b3 === 1'b0) begin + $display ("%m : at time %t ERROR: all banks must be Precharge before Load Mode Register", $time); + end + + // Precharge to Load Mode Register + if (($time - RP_chk0 < tRP) || ($time - RP_chk1 < tRP) || + ($time - RP_chk2 < tRP) || ($time - RP_chk3 < tRP)) begin + $display ("%m : at time %t ERROR: tRP violation during Load Mode Register", $time); + end + + // Auto Refresh to Load Mode Register + if ($time - RFC_chk < tRFC) begin + $display ("%m : at time %t ERROR: tRFC violation during Load Mode Register", $time); + end + + // Load Mode Register to Load Mode Register + if (MRD_chk < tMRD) begin + $display ("%m : at time %t ERROR: tMRD violation during Load Mode Register", $time); + end + + // Reset MRD Counter + MRD_chk = 0; + end + + // Active Block (Latch Bank Address and Row Address) + if (Active_enable === 1'b1) begin + // Activate an open bank can corrupt data + if ((Ba === 2'b00 && Act_b0 === 1'b1) || (Ba === 2'b01 && Act_b1 === 1'b1) || + (Ba === 2'b10 && Act_b2 === 1'b1) || (Ba === 2'b11 && Act_b3 === 1'b1)) begin + $display ("%m : at time %t ERROR: Bank already activated -- data can be corrupted", $time); + end + + // Activate Bank 0 + if (Ba === 2'b00 && Pc_b0 === 1'b1) begin + // Debug Message + if (Debug) begin + $display ("%m : at time %t ACT : Bank = 0 Row = %h", $time, Addr); + end + + // ACTIVE to ACTIVE command period + if ($time - RC_chk0 < tRC) begin + $display ("%m : at time %t ERROR: tRC violation during Activate bank 0", $time); + end + + // Precharge to Activate Bank 0 + if ($time - RP_chk0 < tRP) begin + $display ("%m : at time %t ERROR: tRP violation during Activate bank 0", $time); + end + + // Record variables + Act_b0 = 1'b1; + Pc_b0 = 1'b0; + B0_row_addr = Addr [addr_bits - 1 : 0]; + RAS_chk0 = $time; + RC_chk0 = $time; + RCD_chk0 = $time; + end + + if (Ba == 2'b01 && Pc_b1 == 1'b1) begin + // Debug Message + if (Debug) begin + $display ("%m : at time %t ACT : Bank = 1 Row = %h", $time, Addr); + end + + // ACTIVE to ACTIVE command period + if ($time - RC_chk1 < tRC) begin + $display ("%m : at time %t ERROR: tRC violation during Activate bank 1", $time); + end + + // Precharge to Activate Bank 1 + if ($time - RP_chk1 < tRP) begin + $display ("%m : at time %t ERROR: tRP violation during Activate bank 1", $time); + end + + // Record variables + Act_b1 = 1'b1; + Pc_b1 = 1'b0; + B1_row_addr = Addr [addr_bits - 1 : 0]; + RAS_chk1 = $time; + RC_chk1 = $time; + RCD_chk1 = $time; + end + + if (Ba == 2'b10 && Pc_b2 == 1'b1) begin + // Debug Message + if (Debug) begin + $display ("%m : at time %t ACT : Bank = 2 Row = %h", $time, Addr); + end + + // ACTIVE to ACTIVE command period + if ($time - RC_chk2 < tRC) begin + $display ("%m : at time %t ERROR: tRC violation during Activate bank 2", $time); + end + + // Precharge to Activate Bank 2 + if ($time - RP_chk2 < tRP) begin + $display ("%m : at time %t ERROR: tRP violation during Activate bank 2", $time); + end + + // Record variables + Act_b2 = 1'b1; + Pc_b2 = 1'b0; + B2_row_addr = Addr [addr_bits - 1 : 0]; + RAS_chk2 = $time; + RC_chk2 = $time; + RCD_chk2 = $time; + end + + if (Ba == 2'b11 && Pc_b3 == 1'b1) begin + // Debug Message + if (Debug) begin + $display ("%m : at time %t ACT : Bank = 3 Row = %h", $time, Addr); + end + + // ACTIVE to ACTIVE command period + if ($time - RC_chk3 < tRC) begin + $display ("%m : at time %t ERROR: tRC violation during Activate bank 3", $time); + end + + // Precharge to Activate Bank 3 + if ($time - RP_chk3 < tRP) begin + $display ("%m : at time %t ERROR: tRP violation during Activate bank 3", $time); + end + + // Record variables + Act_b3 = 1'b1; + Pc_b3 = 1'b0; + B3_row_addr = Addr [addr_bits - 1 : 0]; + RAS_chk3 = $time; + RC_chk3 = $time; + RCD_chk3 = $time; + end + + // Active Bank A to Active Bank B + if ((Prev_bank != Ba) && ($time - RRD_chk < tRRD)) begin + $display ("%m : at time %t ERROR: tRRD violation during Activate bank = %h", $time, Ba); + end + + // Auto Refresh to Activate + if ($time - RFC_chk < tRFC) begin + $display ("%m : at time %t ERROR: tRFC violation during Activate bank = %h", $time, Ba); + end + + // Load Mode Register to Active + if (MRD_chk < tMRD ) begin + $display ("%m : at time %t ERROR: tMRD violation during Activate bank = %h", $time, Ba); + end + + // Record variables for checking violation + RRD_chk = $time; + Prev_bank = Ba; + end + + // Precharge Block + if (Prech_enable == 1'b1) begin + // Load Mode Register to Precharge + if ($time - MRD_chk < tMRD) begin + $display ("%m : at time %t ERROR: tMRD violaiton during Precharge", $time); + end + + // Precharge Bank 0 + if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b00)) && Act_b0 === 1'b1) begin + Act_b0 = 1'b0; + Pc_b0 = 1'b1; + RP_chk0 = $time; + + // Activate to Precharge + if ($time - RAS_chk0 < tRAS) begin + $display ("%m : at time %t ERROR: tRAS violation during Precharge", $time); + end + + // tWR violation check for write + if ($time - WR_chkm[0] < tWRm) begin + $display ("%m : at time %t ERROR: tWR violation during Precharge", $time); + end + end + + // Precharge Bank 1 + if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b01)) && Act_b1 === 1'b1) begin + Act_b1 = 1'b0; + Pc_b1 = 1'b1; + RP_chk1 = $time; + + // Activate to Precharge + if ($time - RAS_chk1 < tRAS) begin + $display ("%m : at time %t ERROR: tRAS violation during Precharge", $time); + end + + // tWR violation check for write + if ($time - WR_chkm[1] < tWRm) begin + $display ("%m : at time %t ERROR: tWR violation during Precharge", $time); + end + end + + // Precharge Bank 2 + if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b10)) && Act_b2 === 1'b1) begin + Act_b2 = 1'b0; + Pc_b2 = 1'b1; + RP_chk2 = $time; + + // Activate to Precharge + if ($time - RAS_chk2 < tRAS) begin + $display ("%m : at time %t ERROR: tRAS violation during Precharge", $time); + end + + // tWR violation check for write + if ($time - WR_chkm[2] < tWRm) begin + $display ("%m : at time %t ERROR: tWR violation during Precharge", $time); + end + end + + // Precharge Bank 3 + if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b11)) && Act_b3 === 1'b1) begin + Act_b3 = 1'b0; + Pc_b3 = 1'b1; + RP_chk3 = $time; + + // Activate to Precharge + if ($time - RAS_chk3 < tRAS) begin + $display ("%m : at time %t ERROR: tRAS violation during Precharge", $time); + end + + // tWR violation check for write + if ($time - WR_chkm[3] < tWRm) begin + $display ("%m : at time %t ERROR: tWR violation during Precharge", $time); + end + end + + // Terminate a Write Immediately (if same bank or all banks) + if (Data_in_enable === 1'b1 && (Bank === Ba || Addr[10] === 1'b1)) begin + Data_in_enable = 1'b0; + end + + // Precharge Command Pipeline for Read + if (Cas_latency_3 === 1'b1) begin + Command[2] = `PRECH; + Bank_precharge[2] = Ba; + A10_precharge[2] = Addr[10]; + end else if (Cas_latency_2 === 1'b1) begin + Command[1] = `PRECH; + Bank_precharge[1] = Ba; + A10_precharge[1] = Addr[10]; + end + end + + // Burst terminate + if (Burst_term === 1'b1) begin + // Terminate a Write Immediately + if (Data_in_enable == 1'b1) begin + Data_in_enable = 1'b0; + end + + // Terminate a Read Depend on CAS Latency + if (Cas_latency_3 === 1'b1) begin + Command[2] = `BST; + end else if (Cas_latency_2 == 1'b1) begin + Command[1] = `BST; + end + + // Display debug message + if (Debug) begin + $display ("%m : at time %t BST : Burst Terminate",$time); + end + end + + // Read, Write, Column Latch + if (Read_enable === 1'b1) begin + // Check to see if bank is open (ACT) + if ((Ba == 2'b00 && Pc_b0 == 1'b1) || (Ba == 2'b01 && Pc_b1 == 1'b1) || + (Ba == 2'b10 && Pc_b2 == 1'b1) || (Ba == 2'b11 && Pc_b3 == 1'b1)) begin + $display("%m : at time %t ERROR: Bank is not Activated for Read", $time); + end + + // Activate to Read or Write + if ((Ba == 2'b00) && ($time - RCD_chk0 < tRCD) || + (Ba == 2'b01) && ($time - RCD_chk1 < tRCD) || + (Ba == 2'b10) && ($time - RCD_chk2 < tRCD) || + (Ba == 2'b11) && ($time - RCD_chk3 < tRCD)) begin + $display("%m : at time %t ERROR: tRCD violation during Read", $time); + end + + // CAS Latency pipeline + if (Cas_latency_3 == 1'b1) begin + Command[2] = `READ; + Col_addr[2] = Addr; + Bank_addr[2] = Ba; + end else if (Cas_latency_2 == 1'b1) begin + Command[1] = `READ; + Col_addr[1] = Addr; + Bank_addr[1] = Ba; + end + + // Read interrupt Write (terminate Write immediately) + if (Data_in_enable == 1'b1) begin + Data_in_enable = 1'b0; + + // Interrupting a Write with Autoprecharge + if (Auto_precharge[RW_interrupt_bank] == 1'b1 && Write_precharge[RW_interrupt_bank] == 1'b1) begin + RW_interrupt_write[RW_interrupt_bank] = 1'b1; + RW_interrupt_counter[RW_interrupt_bank] = 0; + + // Display debug message + if (Debug) begin + $display ("%m : at time %t NOTE : Read interrupt Write with Autoprecharge", $time); + end + end + end + + // Write with Auto Precharge + if (Addr[10] == 1'b1) begin + Auto_precharge[Ba] = 1'b1; + Count_precharge[Ba] = 0; + RW_interrupt_bank = Ba; + Read_precharge[Ba] = 1'b1; + end + end + + // Write Command + if (Write_enable == 1'b1) begin + // Activate to Write + if ((Ba == 2'b00 && Pc_b0 == 1'b1) || (Ba == 2'b01 && Pc_b1 == 1'b1) || + (Ba == 2'b10 && Pc_b2 == 1'b1) || (Ba == 2'b11 && Pc_b3 == 1'b1)) begin + $display("%m : at time %t ERROR: Bank is not Activated for Write", $time); + end + + // Activate to Read or Write + if ((Ba == 2'b00) && ($time - RCD_chk0 < tRCD) || + (Ba == 2'b01) && ($time - RCD_chk1 < tRCD) || + (Ba == 2'b10) && ($time - RCD_chk2 < tRCD) || + (Ba == 2'b11) && ($time - RCD_chk3 < tRCD)) begin + $display("%m : at time %t ERROR: tRCD violation during Read", $time); + end + + // Latch Write command, Bank, and Column + Command[0] = `WRITE; + Col_addr[0] = Addr; + Bank_addr[0] = Ba; + + // Write interrupt Write (terminate Write immediately) + if (Data_in_enable == 1'b1) begin + Data_in_enable = 1'b0; + + // Interrupting a Write with Autoprecharge + if (Auto_precharge[RW_interrupt_bank] == 1'b1 && Write_precharge[RW_interrupt_bank] == 1'b1) begin + RW_interrupt_write[RW_interrupt_bank] = 1'b1; + + // Display debug message + if (Debug) begin + $display ("%m : at time %t NOTE : Read Bank %h interrupt Write Bank %h with Autoprecharge", $time, Ba, RW_interrupt_bank); + end + end + end + + // Write interrupt Read (terminate Read immediately) + if (Data_out_enable == 1'b1) begin + Data_out_enable = 1'b0; + + // Interrupting a Read with Autoprecharge + if (Auto_precharge[RW_interrupt_bank] == 1'b1 && Read_precharge[RW_interrupt_bank] == 1'b1) begin + RW_interrupt_read[RW_interrupt_bank] = 1'b1; + + // Display debug message + if (Debug) begin + $display ("%m : at time %t NOTE : Write Bank %h interrupt Read Bank %h with Autoprecharge", $time, Ba, RW_interrupt_bank); + end + end + end + + // Write with Auto Precharge + if (Addr[10] == 1'b1) begin + Auto_precharge[Ba] = 1'b1; + Count_precharge[Ba] = 0; + RW_interrupt_bank = Ba; + Write_precharge[Ba] = 1'b1; + end + end + + /* + Write with Auto Precharge Calculation + The device start internal precharge when: + 1. Meet minimum tRAS requirement + and 2. tWR cycle(s) after last valid data + or 3. Interrupt by a Read or Write (with or without Auto Precharge) + + Note: Model is starting the internal precharge 1 cycle after they meet all the + requirement but tRP will be compensate for the time after the 1 cycle. + */ + if ((Auto_precharge[0] == 1'b1) && (Write_precharge[0] == 1'b1)) begin + if ((($time - RAS_chk0 >= tRAS) && // Case 1 + (((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [0] >= 1) || // Case 2 + (Burst_length_2 == 1'b1 && Count_precharge [0] >= 2) || + (Burst_length_4 == 1'b1 && Count_precharge [0] >= 4) || + (Burst_length_8 == 1'b1 && Count_precharge [0] >= 8))) || + (RW_interrupt_write[0] == 1'b1 && RW_interrupt_counter[0] >= 1)) begin // Case 3 + Auto_precharge[0] = 1'b0; + Write_precharge[0] = 1'b0; + RW_interrupt_write[0] = 1'b0; + Pc_b0 = 1'b1; + Act_b0 = 1'b0; + RP_chk0 = $time + tWRa; + if (Debug) begin + $display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 0", $time); + end + end + end + if ((Auto_precharge[1] == 1'b1) && (Write_precharge[1] == 1'b1)) begin + if ((($time - RAS_chk1 >= tRAS) && // Case 1 + (((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [1] >= 1) || // Case 2 + (Burst_length_2 == 1'b1 && Count_precharge [1] >= 2) || + (Burst_length_4 == 1'b1 && Count_precharge [1] >= 4) || + (Burst_length_8 == 1'b1 && Count_precharge [1] >= 8))) || + (RW_interrupt_write[1] == 1'b1 && RW_interrupt_counter[1] >= 1)) begin // Case 3 + Auto_precharge[1] = 1'b0; + Write_precharge[1] = 1'b0; + RW_interrupt_write[1] = 1'b0; + Pc_b1 = 1'b1; + Act_b1 = 1'b0; + RP_chk1 = $time + tWRa; + if (Debug) begin + $display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 1", $time); + end + end + end + if ((Auto_precharge[2] == 1'b1) && (Write_precharge[2] == 1'b1)) begin + if ((($time - RAS_chk2 >= tRAS) && // Case 1 + (((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [2] >= 1) || // Case 2 + (Burst_length_2 == 1'b1 && Count_precharge [2] >= 2) || + (Burst_length_4 == 1'b1 && Count_precharge [2] >= 4) || + (Burst_length_8 == 1'b1 && Count_precharge [2] >= 8))) || + (RW_interrupt_write[2] == 1'b1 && RW_interrupt_counter[2] >= 1)) begin // Case 3 + Auto_precharge[2] = 1'b0; + Write_precharge[2] = 1'b0; + RW_interrupt_write[2] = 1'b0; + Pc_b2 = 1'b1; + Act_b2 = 1'b0; + RP_chk2 = $time + tWRa; + if (Debug) begin + $display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 2", $time); + end + end + end + if ((Auto_precharge[3] == 1'b1) && (Write_precharge[3] == 1'b1)) begin + if ((($time - RAS_chk3 >= tRAS) && // Case 1 + (((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [3] >= 1) || // Case 2 + (Burst_length_2 == 1'b1 && Count_precharge [3] >= 2) || + (Burst_length_4 == 1'b1 && Count_precharge [3] >= 4) || + (Burst_length_8 == 1'b1 && Count_precharge [3] >= 8))) || + (RW_interrupt_write[3] == 1'b1 && RW_interrupt_counter[3] >= 1)) begin // Case 3 + Auto_precharge[3] = 1'b0; + Write_precharge[3] = 1'b0; + RW_interrupt_write[3] = 1'b0; + Pc_b3 = 1'b1; + Act_b3 = 1'b0; + RP_chk3 = $time + tWRa; + if (Debug) begin + $display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 3", $time); + end + end + end + + // Read with Auto Precharge Calculation + // The device start internal precharge: + // 1. Meet minimum tRAS requirement + // and 2. CAS Latency - 1 cycles before last burst + // or 3. Interrupt by a Read or Write (with or without AutoPrecharge) + if ((Auto_precharge[0] == 1'b1) && (Read_precharge[0] == 1'b1)) begin + if ((($time - RAS_chk0 >= tRAS) && // Case 1 + ((Burst_length_1 == 1'b1 && Count_precharge[0] >= 1) || // Case 2 + (Burst_length_2 == 1'b1 && Count_precharge[0] >= 2) || + (Burst_length_4 == 1'b1 && Count_precharge[0] >= 4) || + (Burst_length_8 == 1'b1 && Count_precharge[0] >= 8))) || + (RW_interrupt_read[0] == 1'b1)) begin // Case 3 + Pc_b0 = 1'b1; + Act_b0 = 1'b0; + RP_chk0 = $time; + Auto_precharge[0] = 1'b0; + Read_precharge[0] = 1'b0; + RW_interrupt_read[0] = 1'b0; + if (Debug) begin + $display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 0", $time); + end + end + end + if ((Auto_precharge[1] == 1'b1) && (Read_precharge[1] == 1'b1)) begin + if ((($time - RAS_chk1 >= tRAS) && + ((Burst_length_1 == 1'b1 && Count_precharge[1] >= 1) || + (Burst_length_2 == 1'b1 && Count_precharge[1] >= 2) || + (Burst_length_4 == 1'b1 && Count_precharge[1] >= 4) || + (Burst_length_8 == 1'b1 && Count_precharge[1] >= 8))) || + (RW_interrupt_read[1] == 1'b1)) begin + Pc_b1 = 1'b1; + Act_b1 = 1'b0; + RP_chk1 = $time; + Auto_precharge[1] = 1'b0; + Read_precharge[1] = 1'b0; + RW_interrupt_read[1] = 1'b0; + if (Debug) begin + $display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 1", $time); + end + end + end + if ((Auto_precharge[2] == 1'b1) && (Read_precharge[2] == 1'b1)) begin + if ((($time - RAS_chk2 >= tRAS) && + ((Burst_length_1 == 1'b1 && Count_precharge[2] >= 1) || + (Burst_length_2 == 1'b1 && Count_precharge[2] >= 2) || + (Burst_length_4 == 1'b1 && Count_precharge[2] >= 4) || + (Burst_length_8 == 1'b1 && Count_precharge[2] >= 8))) || + (RW_interrupt_read[2] == 1'b1)) begin + Pc_b2 = 1'b1; + Act_b2 = 1'b0; + RP_chk2 = $time; + Auto_precharge[2] = 1'b0; + Read_precharge[2] = 1'b0; + RW_interrupt_read[2] = 1'b0; + if (Debug) begin + $display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 2", $time); + end + end + end + if ((Auto_precharge[3] == 1'b1) && (Read_precharge[3] == 1'b1)) begin + if ((($time - RAS_chk3 >= tRAS) && + ((Burst_length_1 == 1'b1 && Count_precharge[3] >= 1) || + (Burst_length_2 == 1'b1 && Count_precharge[3] >= 2) || + (Burst_length_4 == 1'b1 && Count_precharge[3] >= 4) || + (Burst_length_8 == 1'b1 && Count_precharge[3] >= 8))) || + (RW_interrupt_read[3] == 1'b1)) begin + Pc_b3 = 1'b1; + Act_b3 = 1'b0; + RP_chk3 = $time; + Auto_precharge[3] = 1'b0; + Read_precharge[3] = 1'b0; + RW_interrupt_read[3] = 1'b0; + if (Debug) begin + $display("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 3", $time); + end + end + end + + // Internal Precharge or Bst + if (Command[0] == `PRECH) begin // Precharge terminate a read with same bank or all banks + if (Bank_precharge[0] == Bank || A10_precharge[0] == 1'b1) begin + if (Data_out_enable == 1'b1) begin + Data_out_enable = 1'b0; + end + end + end else if (Command[0] == `BST) begin // BST terminate a read to current bank + if (Data_out_enable == 1'b1) begin + Data_out_enable = 1'b0; + end + end + + if (Data_out_enable == 1'b0) begin + Dq_reg <= #tOH {data_bits{1'bz}}; + end + + // Detect Read or Write command + if (Command[0] == `READ) begin + Bank = Bank_addr[0]; + Col = Col_addr[0]; + Col_brst = Col_addr[0]; + case (Bank_addr[0]) + 2'b00 : Row = B0_row_addr; + 2'b01 : Row = B1_row_addr; + 2'b10 : Row = B2_row_addr; + 2'b11 : Row = B3_row_addr; + endcase + Burst_counter = 0; + Data_in_enable = 1'b0; + Data_out_enable = 1'b1; + end else if (Command[0] == `WRITE) begin + Bank = Bank_addr[0]; + Col = Col_addr[0]; + Col_brst = Col_addr[0]; + case (Bank_addr[0]) + 2'b00 : Row = B0_row_addr; + 2'b01 : Row = B1_row_addr; + 2'b10 : Row = B2_row_addr; + 2'b11 : Row = B3_row_addr; + endcase + Burst_counter = 0; + Data_in_enable = 1'b1; + Data_out_enable = 1'b0; + end + + // DQ buffer (Driver/Receiver) + if (Data_in_enable == 1'b1) begin // Writing Data to Memory + // Array buffer + case (Bank) + 2'b00 : Dq_dqm = Bank0 [{Row, Col}]; + 2'b01 : Dq_dqm = Bank1 [{Row, Col}]; + 2'b10 : Dq_dqm = Bank2 [{Row, Col}]; + 2'b11 : Dq_dqm = Bank3 [{Row, Col}]; + endcase + + // Dqm operation + if (Dqm[0] == 1'b0) begin + Dq_dqm [ 7 : 0] = Dq [ 7 : 0]; + end + if (Dqm[1] == 1'b0) begin + Dq_dqm [15 : 8] = Dq [15 : 8]; + end + + // Write to memory + case (Bank) + 2'b00 : Bank0 [{Row, Col}] = Dq_dqm; + 2'b01 : Bank1 [{Row, Col}] = Dq_dqm; + 2'b10 : Bank2 [{Row, Col}] = Dq_dqm; + 2'b11 : Bank3 [{Row, Col}] = Dq_dqm; + endcase + + // Display debug message + if (Dqm !== 2'b11) begin + // Record tWR for manual precharge + WR_chkm [Bank] = $time; + + if (Debug) begin + $display("%m : at time %t WRITE: Bank = %h Row = %h, Col = %h, Data = %h", $time, Bank, Row, Col, Dq_dqm); + end + end else begin + if (Debug) begin + $display("%m : at time %t WRITE: Bank = %h Row = %h, Col = %h, Data = Hi-Z due to DQM", $time, Bank, Row, Col); + end + end + + // Advance burst counter subroutine + #tHZ Burst_decode; + + end else if (Data_out_enable == 1'b1) begin // Reading Data from Memory + // Array buffer + case (Bank) + 2'b00 : Dq_dqm = Bank0[{Row, Col}]; + 2'b01 : Dq_dqm = Bank1[{Row, Col}]; + 2'b10 : Dq_dqm = Bank2[{Row, Col}]; + 2'b11 : Dq_dqm = Bank3[{Row, Col}]; + endcase + + // Dqm operation + if (Dqm_reg0 [0] == 1'b1) begin + Dq_dqm [ 7 : 0] = 8'bz; + end + if (Dqm_reg0 [1] == 1'b1) begin + Dq_dqm [15 : 8] = 8'bz; + end + + // Display debug message + if (Dqm_reg0 !== 2'b11) begin + Dq_reg = #tAC Dq_dqm; + if (Debug) begin + $display("%m : at time %t READ : Bank = %h Row = %h, Col = %h, Data = %h", $time, Bank, Row, Col, Dq_reg); + end + end else begin + Dq_reg = #tHZ {data_bits{1'bz}}; + if (Debug) begin + $display("%m : at time %t READ : Bank = %h Row = %h, Col = %h, Data = Hi-Z due to DQM", $time, Bank, Row, Col); + end + end + + // Advance burst counter subroutine + Burst_decode; + end + end + + // Burst counter decode + task Burst_decode; + begin + // Advance Burst Counter + Burst_counter = Burst_counter + 1; + + // Burst Type + if (Mode_reg[3] == 1'b0) begin // Sequential Burst + Col_temp = Col + 1; + end else if (Mode_reg[3] == 1'b1) begin // Interleaved Burst + Col_temp[2] = Burst_counter[2] ^ Col_brst[2]; + Col_temp[1] = Burst_counter[1] ^ Col_brst[1]; + Col_temp[0] = Burst_counter[0] ^ Col_brst[0]; + end + + // Burst Length + if (Burst_length_2) begin // Burst Length = 2 + Col [0] = Col_temp [0]; + end else if (Burst_length_4) begin // Burst Length = 4 + Col [1 : 0] = Col_temp [1 : 0]; + end else if (Burst_length_8) begin // Burst Length = 8 + Col [2 : 0] = Col_temp [2 : 0]; + end else begin // Burst Length = FULL + Col = Col_temp; + end + + // Burst Read Single Write + if (Write_burst_mode == 1'b1) begin + Data_in_enable = 1'b0; + end + + // Data Counter + if (Burst_length_1 == 1'b1) begin + if (Burst_counter >= 1) begin + Data_in_enable = 1'b0; + Data_out_enable = 1'b0; + end + end else if (Burst_length_2 == 1'b1) begin + if (Burst_counter >= 2) begin + Data_in_enable = 1'b0; + Data_out_enable = 1'b0; + end + end else if (Burst_length_4 == 1'b1) begin + if (Burst_counter >= 4) begin + Data_in_enable = 1'b0; + Data_out_enable = 1'b0; + end + end else if (Burst_length_8 == 1'b1) begin + if (Burst_counter >= 8) begin + Data_in_enable = 1'b0; + Data_out_enable = 1'b0; + end + end + end + endtask + + // Timing Parameters for -7E (133 MHz @ CL2) + specify + specparam + tAH = 0.8, // Addr, Ba Hold Time + tAS = 1.5, // Addr, Ba Setup Time + tCH = 2.5, // Clock High-Level Width + tCL = 2.5, // Clock Low-Level Width + tCK = 7.0, // Clock Cycle Time + tDH = 0.8, // Data-in Hold Time + tDS = 1.5, // Data-in Setup Time + tCKH = 0.8, // CKE Hold Time + tCKS = 1.5, // CKE Setup Time + tCMH = 0.8, // CS#, RAS#, CAS#, WE#, DQM# Hold Time + tCMS = 1.5; // CS#, RAS#, CAS#, WE#, DQM# Setup Time + $width (posedge Clk, tCH); + $width (negedge Clk, tCL); + $period (negedge Clk, tCK); + $period (posedge Clk, tCK); + $setuphold(posedge Clk, Cke, tCKS, tCKH); + $setuphold(posedge Clk, Cs_n, tCMS, tCMH); + $setuphold(posedge Clk, Cas_n, tCMS, tCMH); + $setuphold(posedge Clk, Ras_n, tCMS, tCMH); + $setuphold(posedge Clk, We_n, tCMS, tCMH); + $setuphold(posedge Clk, Addr, tAS, tAH); + $setuphold(posedge Clk, Ba, tAS, tAH); + $setuphold(posedge Clk, Dqm, tCMS, tCMH); + $setuphold(posedge Dq_chk, Dq, tDS, tDH); + endspecify + +endmodule
versatile_mem_ctrl/tags/Rev2/bench/mt48lc16m16a2.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: versatile_mem_ctrl/tags/Rev2/bench/tb_defines.v =================================================================== --- versatile_mem_ctrl/tags/Rev2/bench/tb_defines.v (nonexistent) +++ versatile_mem_ctrl/tags/Rev2/bench/tb_defines.v (revision 109) @@ -0,0 +1,6 @@ +// clock periods +`define WB0_CLK_PERIOD 20 +`define SDRAM_CLK_PERIOD 6 + +`define SDR_16 +`define DDR_16 Index: versatile_mem_ctrl/tags/Rev2/bench/ddr/ddr2.v =================================================================== --- versatile_mem_ctrl/tags/Rev2/bench/ddr/ddr2.v (nonexistent) +++ versatile_mem_ctrl/tags/Rev2/bench/ddr/ddr2.v (revision 109) @@ -0,0 +1,2025 @@ +/**************************************************************************************** +* +* File Name: ddr2.v +* Version: 5.80 +* Model: BUS Functional +* +* Dependencies: ddr2_parameters.vh +* +* Description: Micron SDRAM DDR2 (Double Data Rate 2) +* +* Limitation: - doesn't check for average refresh timings +* - positive ck and ck_n edges are used to form internal clock +* - positive dqs and dqs_n edges are used to latch data +* - test mode is not modeled +* +* Note: - Set simulator resolution to "ps" accuracy +* - Set Debug = 0 to disable $display messages +* +* Disclaimer This software code and all associated documentation, comments or other +* of Warranty: information (collectively "Software") is provided "AS IS" without +* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY +* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES +* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT +* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE +* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE. +* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR +* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS, +* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE +* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI, +* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT, +* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING, +* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, +* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE +* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH +* DAMAGES. Because some jurisdictions prohibit the exclusion or +* limitation of liability for consequential or incidental damages, the +* above limitation may not apply to you. +* +* Copyright 2003 Micron Technology, Inc. All rights reserved. +* +* Rev Author Date Changes +* --------------------------------------------------------------------------------------- +* 1.00 JMK 07/29/03 Initial Release +* 1.10 JMK 08/09/03 Timing Parameter updates to tIS, tIH, tDS, tDH +* 2.20 JMK 08/07/03 General cleanup +* 2.30 JMK 11/26/03 Added CL_MIN, CL_MAX, wl_min and wl_max parameters. +* Added AL_MIN and AL_MAX parameters. +* Removed support for OCD. +* 2.40 JMK 01/15/04 Removed verilog 2001 constructs. +* 2.50 JMK 01/29/04 Removed tRP checks during Precharge command. +* 2.60 JMK 04/20/04 Fixed tWTR check. +* 2.70 JMK 04/30/04 Added tRFC maximum check. +* Combined Self Refresh and Power Down always blocks. +* Added Reset Function (CKE LOW Anytime). +* 2.80 JMK 08/19/04 Precharge is treated as NOP when bank is not active. +* Added checks for tRAS, tWR, tRTP to any bank during Pre-All. +* tRFC maximum violation will only display one time. +* 2.90 JMK 11/05/04 Fixed DQS checking during write. +* Fixed false tRFC max assertion during power up and self ref. +* Added warning for 200us CKE low time during initialization. +* Added -3, -3E, and -37V speed grades to ddr2_parameters.v +* 3.00 JMK 04/22/05 Removed ODT off requirement during power down. +* Added tAOND, tAOFD, tANPD, tAXPD, tAONPD, and tAOFPD parameters. +* Added ODT status messages. +* Updated the initialization sequence. +* Disable ODT and CLK pins during self refresh. +* Disable cmd and addr pins during power down and self refresh. +* 3.10 JMK 06/07/05 Disable trpa checking if the part does not have 8 banks. +* Changed tAXPD message from error to a warning. +* Added tDSS checking. +* Removed tDQSL checking during tWPRE and tWPST. +* Fixed a burst order error during writes. +* Renamed parameters file with .vh extension. +* 3.20 JMK 07/18/05 Removed 14 tCK requirement from LMR to READ. +* 3.30 JMK 08/03/05 Added check for interrupting a burst with auto precharge. +* 4.00 JMK 11/21/05 Parameter names all UPPERCASE, signal names all lowercase. +* Clock jitter can be tolerated within specification range. +* Clock frequency is sampled from the CK pin. +* Scaleable up to 64 DQ and 16 DQS bits. +* Read data can be randomly skewed using RANDOM_OUT_DELAY. +* Parameterized read and write DQS, and read DQ. +* Initialization can be bypassed using initialize task. +* 4.10 JMK 11/30/05 Fixed compile errors when `MAX_MEM was defined. +* 4.20 JMK 12/09/05 Fixed memory addressing error when `MAX_MEM was defined. +* 4.30 JMK 02/15/06 Added dummy write to initialization sequence. +* Removed tWPST maximum checking. +* Rising dqs_n edge latches data when enabled in EMR. +* Fixed a sign error in the tJIT(cc) calculation. +* 4.40 JMK 02/16/06 Fixed dummy write when`MAX_MEM was defined. +* 4.50 JMK 02/27/06 Fixed extra tDQSS assertions. +* Fixed tRCD and tWTR checking. +* Errors entering Power Down or Self Refresh will cause reset. +* Ignore dqs_n when disabled in EMR. +* 5.00 JMK 04/24/06 Test stimulus now included from external file (subtest.vh) +* Fixed tRFC max assertion during self refresh. +* Fixed tANPD checking during Power Down. +* Removed dummy write from initialization sequence. +* 5.01 JMK 04/28/06 Fixed Auto Precharge to Load Mode, Refresh and Self Refresh. +* Removed Auto Precharge error message during Power Down Enter. +* 5.10 JMK 07/26/06 Created internal clock using ck and ck_n. +* RDQS can only be enabled in EMR for x8 configurations. +* CAS latency is checked vs frequency when DLL locks. +* tMOD changed from tCK units to ns units. +* Added 50 Ohm setting for Rtt in EMR. +* Improved checking of DQS during writes. +* 5.20 JMK 10/02/06 Fixed DQS checking for interrupting write to write and x16. +* 5.30 JMK 05/25/07 Fixed checking for 0-Z transition on write postamble. +* 5.50 JMK 05/30/08 Renamed ddr2_dimm.v to ddr2_module.v and added SODIMM support. +* Added a register delay to ddr2_module.v when RDIMM is defined. +* Added multi-chip package model support in ddr2_mcp.v +* Added High Temp Self Refresh rate setting in EMRS2[7] +* 5.70 JMK 04/23/09 Updated tRPA definition +* Increased internal width to 72 bit DQ bus +* 5.80 SPH 08/12/09 Fixed tRAS maximum violation (only check if bank still open) +****************************************************************************************/ + +// DO NOT CHANGE THE TIMESCALE +// MAKE SURE YOUR SIMULATOR USES "PS" RESOLUTION +`timescale 1ps / 1ps + +module ddr2 ( + ck, + ck_n, + cke, + cs_n, + ras_n, + cas_n, + we_n, + dm_rdqs, + ba, + addr, + dq, + dqs, + dqs_n, + rdqs_n, + odt +); + + `include "ddr2_parameters.vh" + + // text macros + `define DQ_PER_DQS DQ_BITS/DQS_BITS + `define BANKS (1<= 2. \nBL_MAX = %d", BL_MAX); + if ((1< BL_MAX) + $display("%m ERROR: 2^BO_BITS cannot be greater than BL_MAX parameter."); + $timeformat (-12, 1, " ps", 1); + reset_task; + seed = RANDOM_SEED; + ck_cntr = 0; + end + + // calculate the absolute value of a real number + function real abs_value; + input arg; + real arg; + begin + if (arg < 0.0) + abs_value = -1.0 * arg; + else + abs_value = arg; + end + endfunction + +`ifdef MAX_MEM +`else + function get_index; + input [`MAX_BITS-1:0] addr; + begin : index + get_index = 0; + for (memory_index=0; memory_index TRAS_MAX) && (active_bank[bank] === 1'b1)) $display ("%m: at time %t ERROR: tRAS maximum violation during %s to bank %d", $time, cmd_string[cmd], bank); + if ($time - tm_bank_activate[bank] < TRAS_MIN) $display ("%m: at time %t ERROR: tRAS minimum violation during %s to bank %d", $time, cmd_string[cmd], bank);end + {1'b0, ACTIVATE , ACTIVATE } : begin if ($time - tm_activate < TRRD) $display ("%m: at time %t ERROR: tRRD violation during %s to bank %d", $time, cmd_string[cmd], bank); end + {1'b1, ACTIVATE , ACTIVATE } : begin if ($time - tm_bank_activate[bank] < TRC) $display ("%m: at time %t ERROR: tRC violation during %s to bank %d", $time, cmd_string[cmd], bank); end + {1'b1, ACTIVATE , 4'b010x } : ; // tRCD is checked outside this task + {1'b1, ACTIVATE , PWR_DOWN } : ; // 1 tCK + {1'b1, WRITE , PRECHARGE} : begin if ((ck_cntr - ck_bank_write[bank] <= write_latency + burst_length/2) || ($time - tm_bank_write_end[bank] < TWR)) $display ("%m: at time %t ERROR: tWR violation during %s to bank %d", $time, cmd_string[cmd], bank); end + {1'b0, WRITE , WRITE } : begin if (ck_cntr - ck_write < TCCD) $display ("%m: at time %t ERROR: tCCD violation during %s to bank %d", $time, cmd_string[cmd], bank); end + {1'b0, WRITE , READ } : begin if ((ck_load_mode < ck_write) && (ck_cntr - ck_write < write_latency + burst_length/2 + 2 - additive_latency)) $display ("%m: at time %t ERROR: tWTR violation during %s to bank %d", $time, cmd_string[cmd], bank); end + {1'b0, WRITE , PWR_DOWN } : begin if ((ck_load_mode < ck_write) && ( + |write_precharge_bank + || (ck_cntr - ck_write_ap < 1) + || (ck_cntr - ck_write < write_latency + burst_length/2 + 2) + || ($time - tm_write_end < TWTR))) begin $display ("%m: at time %t INFO: Write to Reset condition", $time); init_done = 0; end end + {1'b1, READ , PRECHARGE} : begin if ((ck_cntr - ck_bank_read[bank] < additive_latency + burst_length/2) || ($time - tm_bank_read_end[bank] < TRTP)) $display ("%m: at time %t ERROR: tRTP violation during %s to bank %d", $time, cmd_string[cmd], bank); end + {1'b0, READ , WRITE } : begin if ((ck_load_mode < ck_read) && (ck_cntr - ck_read < read_latency + burst_length/2 + 1 - write_latency)) $display ("%m: at time %t ERROR: tRTW violation during %s to bank %d", $time, cmd_string[cmd], bank); end + {1'b0, READ , READ } : begin if (ck_cntr - ck_read < TCCD) $display ("%m: at time %t ERROR: tCCD violation during %s to bank %d", $time, cmd_string[cmd], bank); end + {1'b0, READ , PWR_DOWN } : begin if ((ck_load_mode < ck_read) && (ck_cntr - ck_read < read_latency + burst_length/2 + 1)) begin $display ("%m: at time %t INFO: Read to Reset condition", $time); init_done = 0; end end + {1'b0, PWR_DOWN , 4'b00xx } : begin if (ck_cntr - ck_power_down < TXP) $display ("%m: at time %t ERROR: tXP violation during %s", $time, cmd_string[cmd]); end + {1'b0, PWR_DOWN , WRITE } : begin if (ck_cntr - ck_power_down < TXP) $display ("%m: at time %t ERROR: tXP violation during %s", $time, cmd_string[cmd]); end + {1'b0, PWR_DOWN , READ } : begin if (ck_cntr - ck_slow_exit_pd < TXARDS - additive_latency) $display ("%m: at time %t ERROR: tXARDS violation during %s", $time, cmd_string[cmd]); + else if (ck_cntr - ck_power_down < TXARD) $display ("%m: at time %t ERROR: tXARD violation during %s", $time, cmd_string[cmd]); end + {1'b0, SELF_REF , 4'b00xx } : begin if ($time - tm_self_refresh < TXSNR) $display ("%m: at time %t ERROR: tXSNR violation during %s", $time, cmd_string[cmd]); end + {1'b0, SELF_REF , WRITE } : begin if ($time - tm_self_refresh < TXSNR) $display ("%m: at time %t ERROR: tXSNR violation during %s", $time, cmd_string[cmd]); end + {1'b0, SELF_REF , READ } : begin if (ck_cntr - ck_self_refresh < TXSRD) $display ("%m: at time %t ERROR: tXSRD violation during %s", $time, cmd_string[cmd]); end + {1'b0, 4'b100x , 4'b100x } : begin if (ck_cntr - ck_cke < TCKE) begin $display ("%m: at time %t ERROR: tCKE violation on CKE", $time); init_done = 0; end end + endcase + end + endtask + + task cmd_task; + input cke; + input [2:0] cmd; + input [BA_BITS-1:0] bank; + input [ADDR_BITS-1:0] addr; + reg [`BANKS:0] i; + integer j; + reg [`BANKS:0] tfaw_cntr; + reg [COL_BITS-1:0] col; + begin + + // tRFC max check + if (!er_trfc_max && !in_self_refresh) begin + if ($time - tm_refresh > TRFC_MAX) begin + $display ("%m: at time %t ERROR: tRFC maximum violation during %s", $time, cmd_string[cmd]); + er_trfc_max = 1; + end + end + if (cke) begin + if ((cmd < NOP) && ((cmd != PRECHARGE) || !addr[AP])) begin + for (j=0; j= BL_MIN) && (burst_length <= BL_MAX)) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Length = %d", $time, cmd_string[cmd], bank, burst_length); + end else begin + $display ("%m: at time %t ERROR: %s %d Illegal Burst Length = %d", $time, cmd_string[cmd], bank, burst_length); + end + // Burst Order + burst_order = addr[3]; + if (!burst_order) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Order = Sequential", $time, cmd_string[cmd], bank); + end else if (burst_order) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Order = Interleaved", $time, cmd_string[cmd], bank); + end else begin + $display ("%m: at time %t ERROR: %s %d Illegal Burst Order = %d", $time, cmd_string[cmd], bank, burst_order); + end + // CAS Latency + cas_latency = addr[6:4]; + read_latency = cas_latency + additive_latency; + write_latency = read_latency - 1; + if ((cas_latency >= CL_MIN) && (cas_latency <= CL_MAX)) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d CAS Latency = %d", $time, cmd_string[cmd], bank, cas_latency); + end else begin + $display ("%m: at time %t ERROR: %s %d Illegal CAS Latency = %d", $time, cmd_string[cmd], bank, cas_latency); + end + // Test Mode + if (!addr[7]) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d Test Mode = Normal", $time, cmd_string[cmd], bank); + end else begin + $display ("%m: at time %t ERROR: %s %d Illegal Test Mode = %d", $time, cmd_string[cmd], bank, addr[7]); + end + // DLL Reset + dll_reset = addr[8]; + if (!dll_reset) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Reset = Normal", $time, cmd_string[cmd], bank); + end else if (dll_reset) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Reset = Reset DLL", $time, cmd_string[cmd], bank); + dll_locked = 0; + ck_dll_reset <= ck_cntr; + end else begin + $display ("%m: at time %t ERROR: %s %d Illegal DLL Reset = %d", $time, cmd_string[cmd], bank, dll_reset); + end + // Write Recovery + write_recovery = addr[11:9] + 1; + if ((write_recovery >= WR_MIN) && (write_recovery <= WR_MAX)) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d Write Recovery = %d", $time, cmd_string[cmd], bank, write_recovery); + end else begin + $display ("%m: at time %t ERROR: %s %d Illegal Write Recovery = %d", $time, cmd_string[cmd], bank, write_recovery); + end + // Power Down Mode + low_power = addr[12]; + if (!low_power) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d Power Down Mode = Fast Exit", $time, cmd_string[cmd], bank); + end else if (low_power) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d Power Down Mode = Slow Exit", $time, cmd_string[cmd], bank); + end else begin + $display ("%m: at time %t ERROR: %s %d Illegal Power Down Mode = %d", $time, cmd_string[cmd], bank, low_power); + end + end + 1 : begin + // DLL Enable + dll_en = !addr[0]; + if (!dll_en) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Enable = Disabled", $time, cmd_string[cmd], bank); + end else if (dll_en) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Enable = Enabled", $time, cmd_string[cmd], bank); + end else begin + $display ("%m: at time %t ERROR: %s %d Illegal DLL Enable = %d", $time, cmd_string[cmd], bank, dll_en); + end + // Output Drive Strength + if (!addr[1]) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Drive Strength = Full", $time, cmd_string[cmd], bank); + end else if (addr[1]) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Drive Strength = Reduced", $time, cmd_string[cmd], bank); + end else begin + $display ("%m: at time %t ERROR: %s %d Illegal Output Drive Strength = %d", $time, cmd_string[cmd], bank, addr[1]); + end + // ODT Rtt + odt_rtt = {addr[6], addr[2]}; + if (odt_rtt == 2'b00) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d ODT Rtt = Disabled", $time, cmd_string[cmd], bank); + odt_en = 0; + end else if (odt_rtt == 2'b01) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d ODT Rtt = 75 Ohm", $time, cmd_string[cmd], bank); + odt_en = 1; + tm_odt_en <= $time; + end else if (odt_rtt == 2'b10) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d ODT Rtt = 150 Ohm", $time, cmd_string[cmd], bank); + odt_en = 1; + tm_odt_en <= $time; + end else if (odt_rtt == 2'b11) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d ODT Rtt = 50 Ohm", $time, cmd_string[cmd], bank); + odt_en = 1; + tm_odt_en <= $time; + end else begin + $display ("%m: at time %t ERROR: %s %d Illegal ODT Rtt = %d", $time, cmd_string[cmd], bank, odt_rtt); + odt_en = 0; + end + // Additive Latency + additive_latency = addr[5:3]; + read_latency = cas_latency + additive_latency; + write_latency = read_latency - 1; + if ((additive_latency >= AL_MIN) && (additive_latency <= AL_MAX)) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d Additive Latency = %d", $time, cmd_string[cmd], bank, additive_latency); + end else begin + $display ("%m: at time %t ERROR: %s %d Illegal Additive Latency = %d", $time, cmd_string[cmd], bank, additive_latency); + end + // OCD Program + ocd = addr[9:7]; + if (ocd == 3'b000) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d OCD Program = OCD Exit", $time, cmd_string[cmd], bank); + end else if (ocd == 3'b111) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d OCD Program = OCD Default", $time, cmd_string[cmd], bank); + end else begin + $display ("%m: at time %t ERROR: %s %d Illegal OCD Program = %b", $time, cmd_string[cmd], bank, ocd); + end + + // DQS_N Enable + dqs_n_en = !addr[10]; + if (!dqs_n_en) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d DQS_N Enable = Disabled", $time, cmd_string[cmd], bank); + end else if (dqs_n_en) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d DQS_N Enable = Enabled", $time, cmd_string[cmd], bank); + end else begin + $display ("%m: at time %t ERROR: %s %d Illegal DQS_N Enable = %d", $time, cmd_string[cmd], bank, dqs_n_en); + end + // RDQS Enable + rdqs_en = addr[11]; + if (!rdqs_en) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d RDQS Enable = Disabled", $time, cmd_string[cmd], bank); + end else if (rdqs_en) begin +`ifdef x8 + if (DEBUG) $display ("%m: at time %t INFO: %s %d RDQS Enable = Enabled", $time, cmd_string[cmd], bank); +`else + $display ("%m: at time %t WARNING: %s %d Illegal RDQS Enable. RDQS only exists on a x8 part", $time, cmd_string[cmd], bank); + rdqs_en = 0; +`endif + end else begin + $display ("%m: at time %t ERROR: %s %d Illegal RDQS Enable = %d", $time, cmd_string[cmd], bank, rdqs_en); + end + // Output Enable + out_en = !addr[12]; + if (!out_en) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Enable = Disabled", $time, cmd_string[cmd], bank); + end else if (out_en) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Enable = Enabled", $time, cmd_string[cmd], bank); + end else begin + $display ("%m: at time %t ERROR: %s %d Illegal Output Enable = %d", $time, cmd_string[cmd], bank, out_en); + end + end + 2 : begin + // High Temperature Self Refresh rate + if (!addr[7]) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d High Temperature Self Refresh rate = Disabled", $time, cmd_string[cmd], bank); + end else if (addr[1]) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d High Temperature Self Refresh rate = Enabled", $time, cmd_string[cmd], bank); + end else begin + $display ("%m: at time %t ERROR: %s %d Illegal High Temperature Self Refresh rate = %d", $time, cmd_string[cmd], bank, addr[7]); + end + if ((addr & ~(1<<7)) !== 0) begin + $display ("%m: at time %t ERROR: %s %d Illegal value. Reserved bits must be programmed to zero", $time, cmd_string[cmd], bank); + end + end + 3 : begin + if (addr !== 0) begin + $display ("%m: at time %t ERROR: %s %d Illegal value. Reserved bits must be programmed to zero", $time, cmd_string[cmd], bank); + end + end + endcase + init_mode_reg[bank] = 1; + ck_load_mode <= ck_cntr; + end + end + REFRESH : begin + if (|active_bank) begin + $display ("%m: at time %t ERROR: %s Failure. All banks must be Precharged.", $time, cmd_string[cmd]); + if (STOP_ON_ERROR) $stop(0); + end else begin + if (DEBUG) $display ("%m: at time %t INFO: %s", $time, cmd_string[cmd]); + er_trfc_max = 0; + ref_cntr = ref_cntr + 1; + tm_refresh <= $time; + end + end + PRECHARGE : begin + if (addr[AP]) begin + // tRPA timing applies when the PRECHARGE (ALL) command is issued, regardless of + // the number of banks already open or closed. + for (i=0; i<`BANKS; i=i+1) begin + for (j=0; j 3) begin + $display ("%m: at time %t ERROR: tFAW violation during %s to bank %d", $time, cmd_string[cmd], bank); + end + end + + if (!init_done) begin + $display ("%m: at time %t ERROR: %s Failure. Initialization sequence is not complete.", $time, cmd_string[cmd]); + if (STOP_ON_ERROR) $stop(0); + end else if (active_bank[bank]) begin + $display ("%m: at time %t ERROR: %s Failure. Bank %d must be Precharged.", $time, cmd_string[cmd], bank); + if (STOP_ON_ERROR) $stop(0); + end else begin + if (addr >= 1<>1) & -1*(1<= 1<>1) & -1*(1<= 1< $time) +// $display("%m: at time %t WARNING: NOP or DESELECT is required for 200 us before CKE is brought high", $time); + init_step = init_step + 1; + end + 1 : if (dll_en) init_step = init_step + 1; + 2 : begin + if (&init_mode_reg && dll_reset) begin + active_bank = {`BANKS{1'b1}}; // require Precharge All or bank Precharges + ref_cntr = 0; // require refresh + init_step = init_step + 1; + end + end + 3 : if (ref_cntr == 2) begin + init_step = init_step + 1; + end + 4 : if (!dll_reset) init_step = init_step + 1; + 5 : if (ocd == 3'b111) init_step = init_step + 1; + 6 : begin + if (ocd == 3'b000) begin + if (DEBUG) $display ("%m: at time %t INFO: Initialization Sequence is complete", $time); + init_done = 1; + end + end + endcase + end + end else if (prev_cke) begin + if ((!init_done) && (init_step > 1)) begin + $display ("%m: at time %t ERROR: CKE must remain active until the initialization sequence is complete.", $time); + if (STOP_ON_ERROR) $stop(0); + end + case (cmd) + REFRESH : begin + for (j=0; j TDQSS*tck_avg)) + $display ("%m: at time %t ERROR: tDQSS violation on %s bit %d", $time, dqs_string[i/18], i%18); + end + if (check_write_dqs_low[i]) + $display ("%m: at time %t ERROR: %s bit %d latching edge required during the preceding clock period", $time, dqs_string[i/18], i%18); + end + check_write_preamble <= 0; + check_write_postamble <= 0; + check_write_dqs_low <= 0; + end + + if (wr_pipeline[0] || rd_pipeline[0]) begin + bank = ba_pipeline[0]; + row = row_pipeline[0]; + col = col_pipeline[0]; + burst_cntr = 0; + memory_read(bank, row, col, memory_data); + end + + // burst counter + if (burst_cntr < burst_length) begin + burst_position = col ^ burst_cntr; + if (!burst_order) begin + burst_position[BO_BITS-1:0] = col + burst_cntr; + end + burst_cntr = burst_cntr + 1; + end + + // write dqs counter + if (wr_pipeline[WDQS_PRE + 1]) begin + wdqs_cntr = WDQS_PRE + burst_length + WDQS_PST - 1; + end + // write dqs + if ((wdqs_cntr == burst_length + WDQS_PST) && (wdq_cntr == 0)) begin //write preamble + check_write_preamble <= ({DQS_BITS{dqs_n_en}}<<18) | {DQS_BITS{1'b1}}; + end + if (wdqs_cntr > 1) begin // write data + if ((wdqs_cntr - WDQS_PST)%2) begin + check_write_dqs_high <= ({DQS_BITS{dqs_n_en}}<<18) | {DQS_BITS{1'b1}}; + end else begin + check_write_dqs_low <= ({DQS_BITS{dqs_n_en}}<<18) | {DQS_BITS{1'b1}}; + end + end + if (wdqs_cntr == WDQS_PST) begin // write postamble + check_write_postamble <= ({DQS_BITS{dqs_n_en}}<<18) | {DQS_BITS{1'b1}}; + end + if (wdqs_cntr > 0) begin + wdqs_cntr = wdqs_cntr - 1; + end + + // write dq + if (dq_in_valid) begin // write data + bit_mask = 0; + if (diff_ck) begin + for (i=0; i>(burst_position*DQ_BITS); + if (DEBUG) $display ("%m: at time %t INFO: WRITE @ DQS= bank = %h row = %h col = %h data = %h",$time, bank, row, (-1*BL_MAX & col) + burst_position, dq_temp); + if (burst_cntr%BL_MIN == 0) begin + memory_write(bank, row, col, memory_data); + end + end + if (wr_pipeline[1]) begin + wdq_cntr = burst_length; + end + if (wdq_cntr > 0) begin + wdq_cntr = wdq_cntr - 1; + dq_in_valid = 1'b1; + end else begin + dq_in_valid = 1'b0; + dqs_in_valid <= 1'b0; + for (i=0; i<36; i=i+1) begin + wdqs_pos_cntr[i] <= 0; + end + end + if (wr_pipeline[0]) begin + b2b_write <= 1'b0; + end + if (wr_pipeline[2]) begin + if (dqs_in_valid) begin + b2b_write <= 1'b1; + end + dqs_in_valid <= 1'b1; + end + // read dqs enable counter + if (rd_pipeline[RDQSEN_PRE]) begin + rdqsen_cntr = RDQSEN_PRE + burst_length + RDQSEN_PST - 1; + end + if (rdqsen_cntr > 0) begin + rdqsen_cntr = rdqsen_cntr - 1; + dqs_out_en = 1'b1; + end else begin + dqs_out_en = 1'b0; + end + + // read dqs counter + if (rd_pipeline[RDQS_PRE]) begin + rdqs_cntr = RDQS_PRE + burst_length + RDQS_PST - 1; + end + // read dqs + if ((rdqs_cntr >= burst_length + RDQS_PST) && (rdq_cntr == 0)) begin //read preamble + dqs_out = 1'b0; + end else if (rdqs_cntr > RDQS_PST) begin // read data + dqs_out = rdqs_cntr - RDQS_PST; + end else if (rdqs_cntr > 0) begin // read postamble + dqs_out = 1'b0; + end else begin + dqs_out = 1'b1; + end + if (rdqs_cntr > 0) begin + rdqs_cntr = rdqs_cntr - 1; + end + + // read dq enable counter + if (rd_pipeline[RDQEN_PRE]) begin + rdqen_cntr = RDQEN_PRE + burst_length + RDQEN_PST; + end + if (rdqen_cntr > 0) begin + rdqen_cntr = rdqen_cntr - 1; + dq_out_en = 1'b1; + end else begin + dq_out_en = 1'b0; + end + // read dq + if (rd_pipeline[0]) begin + rdq_cntr = burst_length; + end + if (rdq_cntr > 0) begin // read data + dq_temp = memory_data>>(burst_position*DQ_BITS); + dq_out = dq_temp; + if (DEBUG) $display ("%m: at time %t INFO: READ @ DQS= bank = %h row = %h col = %h data = %h",$time, bank, row, (-1*BL_MAX & col) + burst_position, dq_temp); + rdq_cntr = rdq_cntr - 1; + end else begin + dq_out = {DQ_BITS{1'b1}}; + end + + // delay signals prior to output + if (RANDOM_OUT_DELAY && (dqs_out_en || |dqs_out_en_dly || dq_out_en || |dq_out_en_dly)) begin + for (i=0; i dqsck[i] + TQHS + TDQSQ) begin + dqsck_max = dqsck[i] + TQHS + TDQSQ; + end + dqsck_min = -1*TDQSCK; + if (dqsck_min < dqsck[i] - TQHS - TDQSQ) begin + dqsck_min = dqsck[i] - TQHS - TDQSQ; + end + + // DQSQ requirements + // 1.) less than tAC - DQSCK + // 2.) less than tDQSQ + // 3.) greater than -tAC + // 4.) greater than tQH from previous DQS edge + dqsq_min = -1*TAC; + if (dqsq_min < dqsck[i] - TQHS) begin + dqsq_min = dqsck[i] - TQHS; + end + if (dqsck_min == dqsck_max) begin + dqsck[i] = dqsck_min; + end else begin + dqsck[i] = $dist_uniform(seed, dqsck_min, dqsck_max); + end + dqsq_max = TAC; + if (dqsq_max > TDQSQ + dqsck[i]) begin + dqsq_max = TDQSQ + dqsck[i]; + end + + dqs_out_en_dly[i] <= #(tck_avg/2.0 + ($random % TAC)) dqs_out_en; + dqs_out_dly[i] <= #(tck_avg/2.0 + dqsck[i]) dqs_out; + for (j=0; j<`DQ_PER_DQS; j=j+1) begin + if (dq_out_en) begin // tLZ2 + dq_out_en_dly[i*`DQ_PER_DQS + j] <= #(tck_avg/2.0 + $dist_uniform(seed, -2*TAC, dqsq_max)) dq_out_en; + end else begin // tHZ + dq_out_en_dly[i*`DQ_PER_DQS + j] <= #(tck_avg/2.0 + ($random % TAC)) dq_out_en; + end + if (dqsq_min == dqsq_max) begin + dq_out_dly [i*`DQ_PER_DQS + j] <= #(tck_avg/2.0 + dqsq_min) dq_out[i*`DQ_PER_DQS + j]; + end else begin + dq_out_dly [i*`DQ_PER_DQS + j] <= #(tck_avg/2.0 + $dist_uniform(seed, dqsq_min, dqsq_max)) dq_out[i*`DQ_PER_DQS + j]; + end + end + end + end else begin + out_delay = tck_avg/2.0; + dqs_out_en_dly <= #(out_delay) {DQS_BITS{dqs_out_en}}; + dqs_out_dly <= #(out_delay) {DQS_BITS{dqs_out }}; + dq_out_en_dly <= #(out_delay) {DQ_BITS {dq_out_en }}; + dq_out_dly <= #(out_delay) {DQ_BITS {dq_out }}; + end + end + endtask + + always @(diff_ck) begin : main + integer i; + + if (!in_self_refresh && (diff_ck !== 1'b0) && (diff_ck !== 1'b1)) + $display ("%m: at time %t ERROR: CK and CK_N are not allowed to go to an unknown state.", $time); + data_task; + if (diff_ck) begin + // check setup of command signals + if ($time > TIS) begin + if ($time - tm_cke < TIS) + $display ("%m: at time %t ERROR: tIS violation on CKE by %t", $time, tm_cke + TIS - $time); + if (cke_in) begin + for (i=0; i<22; i=i+1) begin + if ($time - tm_cmd_addr[i] < TIS) + $display ("%m: at time %t ERROR: tIS violation on %s by %t", $time, cmd_addr_string[i], tm_cmd_addr[i] + TIS - $time); + end + end + end + + // update current state + if (!dll_locked && !in_self_refresh && (ck_cntr - ck_dll_reset == TDLLK)) begin + // check CL value against the clock frequency + if (cas_latency*tck_avg < CL_TIME) + $display ("%m: at time %t ERROR: CAS Latency = %d is illegal @tCK(avg) = %f", $time, cas_latency, tck_avg); + // check WR value against the clock frequency + if (write_recovery*tck_avg < TWR) + $display ("%m: at time %t ERROR: Write Recovery = %d is illegal @tCK(avg) = %f", $time, write_recovery, tck_avg); + dll_locked = 1; + end + if (|auto_precharge_bank) begin + for (i=0; i<`BANKS; i=i+1) begin + // Write with Auto Precharge Calculation + // 1. Meet minimum tRAS requirement + // 2. Write Latency PLUS BL/2 cycles PLUS WR after Write command + if (write_precharge_bank[i] + && ($time - tm_bank_activate[i] >= TRAS_MIN) + && (ck_cntr - ck_bank_write[i] >= write_latency + burst_length/2 + write_recovery)) begin + + if (DEBUG) $display ("%m: at time %t INFO: Auto Precharge bank %d", $time, i); + write_precharge_bank[i] = 0; + active_bank[i] = 0; + auto_precharge_bank[i] = 0; + ck_write_ap = ck_cntr; + tm_bank_precharge[i] = $time; + tm_precharge = $time; + end + // Read with Auto Precharge Calculation + // 1. Meet minimum tRAS requirement + // 2. Additive Latency plus BL/2 cycles after Read command + // 3. tRTP after the last 4-bit prefetch + if (read_precharge_bank[i] + && ($time - tm_bank_activate[i] >= TRAS_MIN) + && (ck_cntr - ck_bank_read[i] >= additive_latency + burst_length/2)) begin + + read_precharge_bank[i] = 0; + // In case the internal precharge is pushed out by tRTP, tRP starts at the point where + // the internal precharge happens (not at the next rising clock edge after this event). + if ($time - tm_bank_read_end[i] < TRTP) begin + if (DEBUG) $display ("%m: at time %t INFO: Auto Precharge bank %d", tm_bank_read_end[i] + TRTP, i); + active_bank[i] <= #(tm_bank_read_end[i] + TRTP - $time) 0; + auto_precharge_bank[i] <= #(tm_bank_read_end[i] + TRTP - $time) 0; + tm_bank_precharge[i] <= #(tm_bank_read_end[i] + TRTP - $time) tm_bank_read_end[i] + TRTP; + tm_precharge <= #(tm_bank_read_end[i] + TRTP - $time) tm_bank_read_end[i] + TRTP; + end else begin + if (DEBUG) $display ("%m: at time %t INFO: Auto Precharge bank %d", $time, i); + active_bank[i] = 0; + auto_precharge_bank[i] = 0; + tm_bank_precharge[i] = $time; + tm_precharge = $time; + end + end + end + end + + // respond to incoming command + if (cke_in ^ prev_cke) begin + ck_cke <= ck_cntr; + end + + cmd_task(cke_in, cmd_n_in, ba_in, addr_in); + if ((cmd_n_in == WRITE) || (cmd_n_in == READ)) begin + al_pipeline[2*additive_latency] = 1'b1; + end + if (al_pipeline[0]) begin + // check tRCD after additive latency + if ($time - tm_bank_activate[ba_pipeline[2*cas_latency - 1]] < TRCD) begin + if (rd_pipeline[2*cas_latency - 1]) begin + $display ("%m: at time %t ERROR: tRCD violation during %s", $time, cmd_string[READ]); + end else begin + $display ("%m: at time %t ERROR: tRCD violation during %s", $time, cmd_string[WRITE]); + end + end + // check tWTR after additive latency + if (rd_pipeline[2*cas_latency - 1]) begin + if ($time - tm_write_end < TWTR) + $display ("%m: at time %t ERROR: tWTR violation during %s", $time, cmd_string[READ]); + end + end + if (rd_pipeline[2*(cas_latency - burst_length/2 + 2) - 1]) begin + tm_bank_read_end[ba_pipeline[2*(cas_latency - burst_length/2 + 2) - 1]] <= $time; + end + for (i=0; i<`BANKS; i=i+1) begin + if ((ck_cntr - ck_bank_write[i] > write_latency) && (ck_cntr - ck_bank_write[i] <= write_latency + burst_length/2)) begin + tm_bank_write_end[i] <= $time; + tm_write_end <= $time; + end + end + + // clk pin is disabled during self refresh + if (!in_self_refresh) begin + tjit_cc_time = $time - tm_ck_pos - tck_i; + tck_i = $time - tm_ck_pos; + tck_avg = tck_avg - tck_sample[ck_cntr%TDLLK]/$itor(TDLLK); + tck_avg = tck_avg + tck_i/$itor(TDLLK); + tck_sample[ck_cntr%TDLLK] = tck_i; + tjit_per_rtime = tck_i - tck_avg; + + if (dll_locked) begin + // check accumulated error + terr_nper_rtime = 0; + for (i=0; i<50; i=i+1) begin + terr_nper_rtime = terr_nper_rtime + tck_sample[i] - tck_avg; + terr_nper_rtime = abs_value(terr_nper_rtime); + case (i) + 0 :; + 1 : if (terr_nper_rtime - TERR_2PER >= 1.0) $display ("%m: at time %t ERROR: tERR(2per) violation by %f ps.", $time, terr_nper_rtime - TERR_2PER); + 2 : if (terr_nper_rtime - TERR_3PER >= 1.0) $display ("%m: at time %t ERROR: tERR(3per) violation by %f ps.", $time, terr_nper_rtime - TERR_3PER); + 3 : if (terr_nper_rtime - TERR_4PER >= 1.0) $display ("%m: at time %t ERROR: tERR(4per) violation by %f ps.", $time, terr_nper_rtime - TERR_4PER); + 4 : if (terr_nper_rtime - TERR_5PER >= 1.0) $display ("%m: at time %t ERROR: tERR(5per) violation by %f ps.", $time, terr_nper_rtime - TERR_5PER); + 5,6,7,8,9 : if (terr_nper_rtime - TERR_N1PER >= 1.0) $display ("%m: at time %t ERROR: tERR(n1per) violation by %f ps.", $time, terr_nper_rtime - TERR_N1PER); + default : if (terr_nper_rtime - TERR_N2PER >= 1.0) $display ("%m: at time %t ERROR: tERR(n2per) violation by %f ps.", $time, terr_nper_rtime - TERR_N2PER); + endcase + end + + // check tCK min/max/jitter + if (abs_value(tjit_per_rtime) - TJIT_PER >= 1.0) + $display ("%m: at time %t ERROR: tJIT(per) violation by %f ps.", $time, abs_value(tjit_per_rtime) - TJIT_PER); + if (abs_value(tjit_cc_time) - TJIT_CC >= 1.0) + $display ("%m: at time %t ERROR: tJIT(cc) violation by %f ps.", $time, abs_value(tjit_cc_time) - TJIT_CC); + if (TCK_MIN - tck_avg >= 1.0) + $display ("%m: at time %t ERROR: tCK(avg) minimum violation by %f ps.", $time, TCK_MIN - tck_avg); + if (tck_avg - TCK_MAX >= 1.0) + $display ("%m: at time %t ERROR: tCK(avg) maximum violation by %f ps.", $time, tck_avg - TCK_MAX); + if (tm_ck_pos + TCK_MIN - TJIT_PER > $time) + $display ("%m: at time %t ERROR: tCK(abs) minimum violation by %t", $time, tm_ck_pos + TCK_MIN - TJIT_PER - $time); + if (tm_ck_pos + TCK_MAX + TJIT_PER < $time) + $display ("%m: at time %t ERROR: tCK(abs) maximum violation by %t", $time, $time - tm_ck_pos - TCK_MAX - TJIT_PER); + + // check tCL + if (tm_ck_neg + TCL_MIN*tck_avg - TJIT_DUTY > $time) + $display ("%m: at time %t ERROR: tCL(abs) minimum violation on CLK by %t", $time, tm_ck_neg + TCL_MIN*tck_avg - TJIT_DUTY - $time); + if (tm_ck_neg + TCL_MAX*tck_avg + TJIT_DUTY < $time) + $display ("%m: at time %t ERROR: tCL(abs) maximum violation on CLK by %t", $time, $time - tm_ck_neg - TCL_MAX*tck_avg - TJIT_DUTY); + if (tcl_avg < TCL_MIN*tck_avg) + $display ("%m: at time %t ERROR: tCL(avg) minimum violation on CLK by %t", $time, TCL_MIN*tck_avg - tcl_avg); + if (tcl_avg > TCL_MAX*tck_avg) + $display ("%m: at time %t ERROR: tCL(avg) maximum violation on CLK by %t", $time, tcl_avg - TCL_MAX*tck_avg); + end + + // calculate the tch avg jitter + tch_avg = tch_avg - tch_sample[ck_cntr%TDLLK]/$itor(TDLLK); + tch_avg = tch_avg + tch_i/$itor(TDLLK); + tch_sample[ck_cntr%TDLLK] = tch_i; + + // update timers/counters + tcl_i <= $time - tm_ck_neg; + end + + prev_odt <= odt_in; + // update timers/counters + ck_cntr <= ck_cntr + 1; + tm_ck_pos <= $time; + end else begin + // clk pin is disabled during self refresh + if (!in_self_refresh) begin + if (dll_locked) begin + if (tm_ck_pos + TCH_MIN*tck_avg - TJIT_DUTY > $time) + $display ("%m: at time %t ERROR: tCH(abs) minimum violation on CLK by %t", $time, tm_ck_pos + TCH_MIN*tck_avg - TJIT_DUTY + $time); + if (tm_ck_pos + TCH_MAX*tck_avg + TJIT_DUTY < $time) + $display ("%m: at time %t ERROR: tCH(abs) maximum violation on CLK by %t", $time, $time - tm_ck_pos - TCH_MAX*tck_avg - TJIT_DUTY); + if (tch_avg < TCH_MIN*tck_avg) + $display ("%m: at time %t ERROR: tCH(avg) minimum violation on CLK by %t", $time, TCH_MIN*tck_avg - tch_avg); + if (tch_avg > TCH_MAX*tck_avg) + $display ("%m: at time %t ERROR: tCH(avg) maximum violation on CLK by %t", $time, tch_avg - TCH_MAX*tck_avg); + end + + // calculate the tcl avg jitter + tcl_avg = tcl_avg - tcl_sample[ck_cntr%TDLLK]/$itor(TDLLK); + tcl_avg = tcl_avg + tcl_i/$itor(TDLLK); + tcl_sample[ck_cntr%TDLLK] = tcl_i; + + // update timers/counters + tch_i <= $time - tm_ck_pos; + end + tm_ck_neg <= $time; + end + + // on die termination + if (odt_en) begin + // clk pin is disabled during self refresh + if (!in_self_refresh && diff_ck) begin + if ($time - tm_odt < TIS) begin + $display ("%m: at time %t ERROR: tIS violation on ODT by %t", $time, tm_odt + TIS - $time); + end + if (prev_odt ^ odt_in) begin + if (!dll_locked) + $display ("%m: at time %t WARNING: tDLLK violation during ODT transition.", $time); + if (odt_in && ($time - tm_odt_en < TMOD)) + $display ("%m: at time %t ERROR: tMOD violation during ODT transition", $time); + if ($time - tm_self_refresh < TXSNR) + $display ("%m: at time %t ERROR: tXSNR violation during ODT transition", $time); + if (in_self_refresh) + $display ("%m: at time %t ERROR: Illegal ODT transition during Self Refresh.", $time); + + // async ODT mode applies: + // 1.) during active power down with slow exit + // 2.) during precharge power down + // 3.) if tANPD has not been satisfied + // 4.) until tAXPD has been satisfied + if ((in_power_down && (low_power || (active_bank == 0))) || (ck_cntr - ck_slow_exit_pd < TAXPD)) begin + if (ck_cntr - ck_slow_exit_pd < TAXPD) + $display ("%m: at time %t WARNING: tAXPD violation during ODT transition. Synchronous or asynchronous change in termination resistance is possible.", $time); + if (odt_in) begin + if (DEBUG) $display ("%m: at time %t INFO: Async On Die Termination = %d", $time + TAONPD, 1'b1); + odt_state <= #(TAONPD) 1'b1; + end else begin + if (DEBUG) $display ("%m: at time %t INFO: Async On Die Termination = %d", $time + TAOFPD, 1'b0); + odt_state <= #(TAOFPD) 1'b0; + end + // sync ODT mode applies: + // 1.) during normal operation + // 2.) during active power down with fast exit + end else begin + if (odt_in) begin + i = TAOND*2; + odt_pipeline[i] = 1'b1; + end else begin + i = TAOFD*2; + odt_pipeline[i] = 1'b1; + end + end + ck_odt <= ck_cntr; + end + end + if (odt_pipeline[0]) begin + odt_state = ~odt_state; + if (DEBUG) $display ("%m: at time %t INFO: Sync On Die Termination = %d", $time, odt_state); + end + end + + // shift pipelines + if (|wr_pipeline || |rd_pipeline || |al_pipeline) begin + al_pipeline = al_pipeline>>1; + wr_pipeline = wr_pipeline>>1; + rd_pipeline = rd_pipeline>>1; + for (i=0; i<`MAX_PIPE; i=i+1) begin + ba_pipeline[i] = ba_pipeline[i+1]; + row_pipeline[i] = row_pipeline[i+1]; + col_pipeline[i] = col_pipeline[i+1]; + end + end + if (|odt_pipeline) begin + odt_pipeline = odt_pipeline>>1; + end + end + + // receiver(s) + task dqs_even_receiver; + input [4:0] i; + reg [71:0] bit_mask; + begin + bit_mask = {`DQ_PER_DQS{1'b1}}<<(i*`DQ_PER_DQS); + if (dqs_even[i]) begin + if (rdqs_en) begin // rdqs disables dm + dm_in_pos[i] = 1'b0; + end else begin + dm_in_pos[i] = dm_in[i]; + end + dq_in_pos = (dq_in & bit_mask) | (dq_in_pos & ~bit_mask); + end + end + endtask + + always @(posedge dqs_even[ 0]) dqs_even_receiver( 0); + always @(posedge dqs_even[ 1]) dqs_even_receiver( 1); + always @(posedge dqs_even[ 2]) dqs_even_receiver( 2); + always @(posedge dqs_even[ 3]) dqs_even_receiver( 3); + always @(posedge dqs_even[ 4]) dqs_even_receiver( 4); + always @(posedge dqs_even[ 5]) dqs_even_receiver( 5); + always @(posedge dqs_even[ 6]) dqs_even_receiver( 6); + always @(posedge dqs_even[ 7]) dqs_even_receiver( 7); + always @(posedge dqs_even[ 8]) dqs_even_receiver( 8); + always @(posedge dqs_even[ 9]) dqs_even_receiver( 9); + always @(posedge dqs_even[10]) dqs_even_receiver(10); + always @(posedge dqs_even[11]) dqs_even_receiver(11); + always @(posedge dqs_even[12]) dqs_even_receiver(12); + always @(posedge dqs_even[13]) dqs_even_receiver(13); + always @(posedge dqs_even[14]) dqs_even_receiver(14); + always @(posedge dqs_even[15]) dqs_even_receiver(15); + always @(posedge dqs_even[16]) dqs_even_receiver(16); + always @(posedge dqs_even[17]) dqs_even_receiver(17); + + task dqs_odd_receiver; + input [4:0] i; + reg [71:0] bit_mask; + begin + bit_mask = {`DQ_PER_DQS{1'b1}}<<(i*`DQ_PER_DQS); + if (dqs_odd[i]) begin + if (rdqs_en) begin // rdqs disables dm + dm_in_neg[i] = 1'b0; + end else begin + dm_in_neg[i] = dm_in[i]; + end + dq_in_neg = (dq_in & bit_mask) | (dq_in_neg & ~bit_mask); + end + end + endtask + + always @(posedge dqs_odd[ 0]) dqs_odd_receiver( 0); + always @(posedge dqs_odd[ 1]) dqs_odd_receiver( 1); + always @(posedge dqs_odd[ 2]) dqs_odd_receiver( 2); + always @(posedge dqs_odd[ 3]) dqs_odd_receiver( 3); + always @(posedge dqs_odd[ 4]) dqs_odd_receiver( 4); + always @(posedge dqs_odd[ 5]) dqs_odd_receiver( 5); + always @(posedge dqs_odd[ 6]) dqs_odd_receiver( 6); + always @(posedge dqs_odd[ 7]) dqs_odd_receiver( 7); + always @(posedge dqs_odd[ 8]) dqs_odd_receiver( 8); + always @(posedge dqs_odd[ 9]) dqs_odd_receiver( 9); + always @(posedge dqs_odd[10]) dqs_odd_receiver(10); + always @(posedge dqs_odd[11]) dqs_odd_receiver(11); + always @(posedge dqs_odd[12]) dqs_odd_receiver(12); + always @(posedge dqs_odd[13]) dqs_odd_receiver(13); + always @(posedge dqs_odd[14]) dqs_odd_receiver(14); + always @(posedge dqs_odd[15]) dqs_odd_receiver(15); + always @(posedge dqs_odd[16]) dqs_odd_receiver(16); + always @(posedge dqs_odd[17]) dqs_odd_receiver(17); + + // Processes to check hold and pulse width of control signals + always @(cke_in) begin + if ($time > TIH) begin + if ($time - tm_ck_pos < TIH) + $display ("%m: at time %t ERROR: tIH violation on CKE by %t", $time, tm_ck_pos + TIH - $time); + end + if (dll_locked && ($time - tm_cke < $rtoi(TIPW*tck_avg))) + $display ("%m: at time %t ERROR: tIPW violation on CKE by %t", $time, tm_cke + TIPW*tck_avg - $time); + tm_cke = $time; + end + always @(odt_in) begin + if (odt_en && !in_self_refresh) begin + if ($time - tm_ck_pos < TIH) + $display ("%m: at time %t ERROR: tIH violation on ODT by %t", $time, tm_ck_pos + TIH - $time); + if (dll_locked && ($time - tm_odt < $rtoi(TIPW*tck_avg))) + $display ("%m: at time %t ERROR: tIPW violation on ODT by %t", $time, tm_odt + TIPW*tck_avg - $time); + end + tm_odt = $time; + end + + task cmd_addr_timing_check; + input i; + reg [4:0] i; + begin + if (prev_cke) begin + if ($time - tm_ck_pos < TIH) + $display ("%m: at time %t ERROR: tIH violation on %s by %t", $time, cmd_addr_string[i], tm_ck_pos + TIH - $time); + if (dll_locked && ($time - tm_cmd_addr[i] < $rtoi(TIPW*tck_avg))) + $display ("%m: at time %t ERROR: tIPW violation on %s by %t", $time, cmd_addr_string[i], tm_cmd_addr[i] + TIPW*tck_avg - $time); + end + tm_cmd_addr[i] = $time; + end + endtask + + always @(cs_n_in ) cmd_addr_timing_check( 0); + always @(ras_n_in ) cmd_addr_timing_check( 1); + always @(cas_n_in ) cmd_addr_timing_check( 2); + always @(we_n_in ) cmd_addr_timing_check( 3); + always @(ba_in [ 0]) cmd_addr_timing_check( 4); + always @(ba_in [ 1]) cmd_addr_timing_check( 5); + always @(ba_in [ 2]) cmd_addr_timing_check( 6); + always @(addr_in[ 0]) cmd_addr_timing_check( 7); + always @(addr_in[ 1]) cmd_addr_timing_check( 8); + always @(addr_in[ 2]) cmd_addr_timing_check( 9); + always @(addr_in[ 3]) cmd_addr_timing_check(10); + always @(addr_in[ 4]) cmd_addr_timing_check(11); + always @(addr_in[ 5]) cmd_addr_timing_check(12); + always @(addr_in[ 6]) cmd_addr_timing_check(13); + always @(addr_in[ 7]) cmd_addr_timing_check(14); + always @(addr_in[ 8]) cmd_addr_timing_check(15); + always @(addr_in[ 9]) cmd_addr_timing_check(16); + always @(addr_in[10]) cmd_addr_timing_check(17); + always @(addr_in[11]) cmd_addr_timing_check(18); + always @(addr_in[12]) cmd_addr_timing_check(19); + always @(addr_in[13]) cmd_addr_timing_check(20); + always @(addr_in[14]) cmd_addr_timing_check(21); + always @(addr_in[15]) cmd_addr_timing_check(22); + + // Processes to check setup and hold of data signals + task dm_timing_check; + input i; + reg [4:0] i; + begin + if (dqs_in_valid) begin + if ($time - tm_dqs[i] < TDH) + $display ("%m: at time %t ERROR: tDH violation on DM bit %d by %t", $time, i, tm_dqs[i] + TDH - $time); + if (check_dm_tdipw[i]) begin + if (dll_locked && ($time - tm_dm[i] < $rtoi(TDIPW*tck_avg))) + $display ("%m: at time %t ERROR: tDIPW violation on DM bit %d by %t", $time, i, tm_dm[i] + TDIPW*tck_avg - $time); + end + end + check_dm_tdipw[i] <= 1'b0; + tm_dm[i] = $time; + end + endtask + + always @(dm_in[ 0]) dm_timing_check( 0); + always @(dm_in[ 1]) dm_timing_check( 1); + always @(dm_in[ 2]) dm_timing_check( 2); + always @(dm_in[ 3]) dm_timing_check( 3); + always @(dm_in[ 4]) dm_timing_check( 4); + always @(dm_in[ 5]) dm_timing_check( 5); + always @(dm_in[ 6]) dm_timing_check( 6); + always @(dm_in[ 7]) dm_timing_check( 7); + always @(dm_in[ 8]) dm_timing_check( 8); + always @(dm_in[ 9]) dm_timing_check( 9); + always @(dm_in[10]) dm_timing_check(10); + always @(dm_in[11]) dm_timing_check(11); + always @(dm_in[12]) dm_timing_check(12); + always @(dm_in[13]) dm_timing_check(13); + always @(dm_in[14]) dm_timing_check(14); + always @(dm_in[15]) dm_timing_check(15); + always @(dm_in[16]) dm_timing_check(16); + always @(dm_in[17]) dm_timing_check(17); + + task dq_timing_check; + input i; + reg [6:0] i; + begin + if (dqs_in_valid) begin + if ($time - tm_dqs[i/`DQ_PER_DQS] < TDH) + $display ("%m: at time %t ERROR: tDH violation on DQ bit %d by %t", $time, i, tm_dqs[i/`DQ_PER_DQS] + TDH - $time); + if (check_dq_tdipw[i]) begin + if (dll_locked && ($time - tm_dq[i] < $rtoi(TDIPW*tck_avg))) + $display ("%m: at time %t ERROR: tDIPW violation on DQ bit %d by %t", $time, i, tm_dq[i] + TDIPW*tck_avg - $time); + end + end + check_dq_tdipw[i] <= 1'b0; + tm_dq[i] = $time; + end + endtask + + always @(dq_in[ 0]) dq_timing_check( 0); + always @(dq_in[ 1]) dq_timing_check( 1); + always @(dq_in[ 2]) dq_timing_check( 2); + always @(dq_in[ 3]) dq_timing_check( 3); + always @(dq_in[ 4]) dq_timing_check( 4); + always @(dq_in[ 5]) dq_timing_check( 5); + always @(dq_in[ 6]) dq_timing_check( 6); + always @(dq_in[ 7]) dq_timing_check( 7); + always @(dq_in[ 8]) dq_timing_check( 8); + always @(dq_in[ 9]) dq_timing_check( 9); + always @(dq_in[10]) dq_timing_check(10); + always @(dq_in[11]) dq_timing_check(11); + always @(dq_in[12]) dq_timing_check(12); + always @(dq_in[13]) dq_timing_check(13); + always @(dq_in[14]) dq_timing_check(14); + always @(dq_in[15]) dq_timing_check(15); + always @(dq_in[16]) dq_timing_check(16); + always @(dq_in[17]) dq_timing_check(17); + always @(dq_in[18]) dq_timing_check(18); + always @(dq_in[19]) dq_timing_check(19); + always @(dq_in[20]) dq_timing_check(20); + always @(dq_in[21]) dq_timing_check(21); + always @(dq_in[22]) dq_timing_check(22); + always @(dq_in[23]) dq_timing_check(23); + always @(dq_in[24]) dq_timing_check(24); + always @(dq_in[25]) dq_timing_check(25); + always @(dq_in[26]) dq_timing_check(26); + always @(dq_in[27]) dq_timing_check(27); + always @(dq_in[28]) dq_timing_check(28); + always @(dq_in[29]) dq_timing_check(29); + always @(dq_in[30]) dq_timing_check(30); + always @(dq_in[31]) dq_timing_check(31); + always @(dq_in[32]) dq_timing_check(32); + always @(dq_in[33]) dq_timing_check(33); + always @(dq_in[34]) dq_timing_check(34); + always @(dq_in[35]) dq_timing_check(35); + always @(dq_in[36]) dq_timing_check(36); + always @(dq_in[37]) dq_timing_check(37); + always @(dq_in[38]) dq_timing_check(38); + always @(dq_in[39]) dq_timing_check(39); + always @(dq_in[40]) dq_timing_check(40); + always @(dq_in[41]) dq_timing_check(41); + always @(dq_in[42]) dq_timing_check(42); + always @(dq_in[43]) dq_timing_check(43); + always @(dq_in[44]) dq_timing_check(44); + always @(dq_in[45]) dq_timing_check(45); + always @(dq_in[46]) dq_timing_check(46); + always @(dq_in[47]) dq_timing_check(47); + always @(dq_in[48]) dq_timing_check(48); + always @(dq_in[49]) dq_timing_check(49); + always @(dq_in[50]) dq_timing_check(50); + always @(dq_in[51]) dq_timing_check(51); + always @(dq_in[52]) dq_timing_check(52); + always @(dq_in[53]) dq_timing_check(53); + always @(dq_in[54]) dq_timing_check(54); + always @(dq_in[55]) dq_timing_check(55); + always @(dq_in[56]) dq_timing_check(56); + always @(dq_in[57]) dq_timing_check(57); + always @(dq_in[58]) dq_timing_check(58); + always @(dq_in[59]) dq_timing_check(59); + always @(dq_in[60]) dq_timing_check(60); + always @(dq_in[61]) dq_timing_check(61); + always @(dq_in[62]) dq_timing_check(62); + always @(dq_in[63]) dq_timing_check(63); + always @(dq_in[64]) dq_timing_check(64); + always @(dq_in[65]) dq_timing_check(65); + always @(dq_in[66]) dq_timing_check(66); + always @(dq_in[67]) dq_timing_check(67); + always @(dq_in[68]) dq_timing_check(68); + always @(dq_in[69]) dq_timing_check(69); + always @(dq_in[70]) dq_timing_check(70); + always @(dq_in[71]) dq_timing_check(71); + + task dqs_pos_timing_check; + input i; + reg [5:0] i; + reg [3:0] j; + begin + if (dqs_in_valid && ((wdqs_pos_cntr[i] < burst_length/2) || b2b_write) && (dqs_n_en || i<18)) begin + if (dqs_in[i] ^ prev_dqs_in[i]) begin + if (dll_locked) begin + if (check_write_preamble[i]) begin + if ($time - tm_dqs_neg[i] < $rtoi(TWPRE*tck_avg)) + $display ("%m: at time %t ERROR: tWPRE violation on &s bit %d", $time, dqs_string[i/18], i%18); + end else if (check_write_postamble[i]) begin + if ($time - tm_dqs_neg[i] < $rtoi(TWPST*tck_avg)) + $display ("%m: at time %t ERROR: tWPST violation on %s bit %d", $time, dqs_string[i/18], i%18); + end else begin + if ($time - tm_dqs_neg[i] < $rtoi(TDQSL*tck_avg)) + $display ("%m: at time %t ERROR: tDQSL violation on %s bit %d", $time, dqs_string[i/18], i%18); + end + end + if ($time - tm_dm[i%18] < TDS) + $display ("%m: at time %t ERROR: tDS violation on DM bit %d by %t", $time, i, tm_dm[i%18] + TDS - $time); + if (!dq_out_en) begin + for (j=0; j<`DQ_PER_DQS; j=j+1) begin + if ($time - tm_dq[i*`DQ_PER_DQS+j] < TDS) + $display ("%m: at time %t ERROR: tDS violation on DQ bit %d by %t", $time, i*`DQ_PER_DQS+j, tm_dq[i*`DQ_PER_DQS+j] + TDS - $time); + check_dq_tdipw[i*`DQ_PER_DQS+j] <= 1'b1; + end + end + if ((wdqs_pos_cntr[i] < burst_length/2) && !b2b_write) begin + wdqs_pos_cntr[i] <= wdqs_pos_cntr[i] + 1; + end else begin + wdqs_pos_cntr[i] <= 1; + end + check_dm_tdipw[i%18] <= 1'b1; + check_write_preamble[i] <= 1'b0; + check_write_postamble[i] <= 1'b0; + check_write_dqs_low[i] <= 1'b0; + tm_dqs[i%18] <= $time; + end else begin + $display ("%m: at time %t ERROR: Invalid latching edge on %s bit %d", $time, dqs_string[i/18], i%18); + end + end + tm_dqss_pos[i] <= $time; + tm_dqs_pos[i] = $time; + prev_dqs_in[i] <= dqs_in[i]; + end + endtask + + always @(posedge dqs_in[ 0]) dqs_pos_timing_check( 0); + always @(posedge dqs_in[ 1]) dqs_pos_timing_check( 1); + always @(posedge dqs_in[ 2]) dqs_pos_timing_check( 2); + always @(posedge dqs_in[ 3]) dqs_pos_timing_check( 3); + always @(posedge dqs_in[ 4]) dqs_pos_timing_check( 4); + always @(posedge dqs_in[ 5]) dqs_pos_timing_check( 5); + always @(posedge dqs_in[ 6]) dqs_pos_timing_check( 6); + always @(posedge dqs_in[ 7]) dqs_pos_timing_check( 7); + always @(posedge dqs_in[ 8]) dqs_pos_timing_check( 8); + always @(posedge dqs_in[ 9]) dqs_pos_timing_check( 9); + always @(posedge dqs_in[10]) dqs_pos_timing_check(10); + always @(posedge dqs_in[11]) dqs_pos_timing_check(11); + always @(posedge dqs_in[12]) dqs_pos_timing_check(12); + always @(posedge dqs_in[13]) dqs_pos_timing_check(13); + always @(posedge dqs_in[14]) dqs_pos_timing_check(14); + always @(posedge dqs_in[15]) dqs_pos_timing_check(15); + always @(posedge dqs_in[16]) dqs_pos_timing_check(16); + always @(posedge dqs_in[17]) dqs_pos_timing_check(17); + always @(negedge dqs_in[18]) dqs_pos_timing_check(18); + always @(negedge dqs_in[19]) dqs_pos_timing_check(19); + always @(negedge dqs_in[20]) dqs_pos_timing_check(20); + always @(negedge dqs_in[21]) dqs_pos_timing_check(21); + always @(negedge dqs_in[22]) dqs_pos_timing_check(22); + always @(negedge dqs_in[23]) dqs_pos_timing_check(23); + always @(negedge dqs_in[24]) dqs_pos_timing_check(24); + always @(negedge dqs_in[25]) dqs_pos_timing_check(25); + always @(negedge dqs_in[26]) dqs_pos_timing_check(26); + always @(negedge dqs_in[27]) dqs_pos_timing_check(27); + always @(negedge dqs_in[28]) dqs_pos_timing_check(28); + always @(negedge dqs_in[29]) dqs_pos_timing_check(29); + always @(negedge dqs_in[30]) dqs_pos_timing_check(30); + always @(negedge dqs_in[31]) dqs_pos_timing_check(31); + always @(negedge dqs_in[32]) dqs_neg_timing_check(32); + always @(negedge dqs_in[33]) dqs_neg_timing_check(33); + always @(negedge dqs_in[34]) dqs_neg_timing_check(34); + always @(negedge dqs_in[35]) dqs_neg_timing_check(35); + + task dqs_neg_timing_check; + input i; + reg [5:0] i; + reg [3:0] j; + begin + if (dqs_in_valid && (wdqs_pos_cntr[i] > 0) && check_write_dqs_high[i] && (dqs_n_en || i < 18)) begin + if (dqs_in[i] ^ prev_dqs_in[i]) begin + if (dll_locked) begin + if ($time - tm_dqs_pos[i] < $rtoi(TDQSH*tck_avg)) + $display ("%m: at time %t ERROR: tDQSH violation on %s bit %d", $time, dqs_string[i/18], i%18); + if ($time - tm_ck_pos < $rtoi(TDSH*tck_avg)) + $display ("%m: at time %t ERROR: tDSH violation on %s bit %d", $time, dqs_string[i/18], i%18); + end + if ($time - tm_dm[i%18] < TDS) + $display ("%m: at time %t ERROR: tDS violation on DM bit %d by %t", $time, i, tm_dm[i%18] + TDS - $time); + if (!dq_out_en) begin + for (j=0; j<`DQ_PER_DQS; j=j+1) begin + if ($time - tm_dq[i*`DQ_PER_DQS+j] < TDS) + $display ("%m: at time %t ERROR: tDS violation on DQ bit %d by %t", $time, i*`DQ_PER_DQS+j, tm_dq[i*`DQ_PER_DQS+j] + TDS - $time); + check_dq_tdipw[i*`DQ_PER_DQS+j] <= 1'b1; + end + end + check_dm_tdipw[i%18] <= 1'b1; + check_write_dqs_high[i] <= 1'b0; + tm_dqs[i%18] <= $time; + end else begin + $display ("%m: at time %t ERROR: Invalid latching edge on %s bit %d", $time, dqs_string[i/18], i%18); + end + end + tm_dqs_neg[i] = $time; + prev_dqs_in[i] <= dqs_in[i]; + end + endtask + + always @(negedge dqs_in[ 0]) dqs_neg_timing_check( 0); + always @(negedge dqs_in[ 1]) dqs_neg_timing_check( 1); + always @(negedge dqs_in[ 2]) dqs_neg_timing_check( 2); + always @(negedge dqs_in[ 3]) dqs_neg_timing_check( 3); + always @(negedge dqs_in[ 4]) dqs_neg_timing_check( 4); + always @(negedge dqs_in[ 5]) dqs_neg_timing_check( 5); + always @(negedge dqs_in[ 6]) dqs_neg_timing_check( 6); + always @(negedge dqs_in[ 7]) dqs_neg_timing_check( 7); + always @(negedge dqs_in[ 8]) dqs_neg_timing_check( 8); + always @(negedge dqs_in[ 9]) dqs_neg_timing_check( 9); + always @(negedge dqs_in[10]) dqs_neg_timing_check(10); + always @(negedge dqs_in[11]) dqs_neg_timing_check(11); + always @(negedge dqs_in[12]) dqs_neg_timing_check(12); + always @(negedge dqs_in[13]) dqs_neg_timing_check(13); + always @(negedge dqs_in[14]) dqs_neg_timing_check(14); + always @(negedge dqs_in[15]) dqs_neg_timing_check(15); + always @(negedge dqs_in[16]) dqs_neg_timing_check(16); + always @(negedge dqs_in[17]) dqs_neg_timing_check(17); + always @(posedge dqs_in[18]) dqs_neg_timing_check(18); + always @(posedge dqs_in[19]) dqs_neg_timing_check(19); + always @(posedge dqs_in[20]) dqs_neg_timing_check(20); + always @(posedge dqs_in[21]) dqs_neg_timing_check(21); + always @(posedge dqs_in[22]) dqs_neg_timing_check(22); + always @(posedge dqs_in[23]) dqs_neg_timing_check(23); + always @(posedge dqs_in[24]) dqs_neg_timing_check(24); + always @(posedge dqs_in[25]) dqs_neg_timing_check(25); + always @(posedge dqs_in[26]) dqs_neg_timing_check(26); + always @(posedge dqs_in[27]) dqs_neg_timing_check(27); + always @(posedge dqs_in[28]) dqs_neg_timing_check(28); + always @(posedge dqs_in[29]) dqs_neg_timing_check(29); + always @(posedge dqs_in[30]) dqs_neg_timing_check(30); + always @(posedge dqs_in[31]) dqs_neg_timing_check(31); + always @(posedge dqs_in[32]) dqs_neg_timing_check(32); + always @(posedge dqs_in[33]) dqs_neg_timing_check(33); + always @(posedge dqs_in[34]) dqs_neg_timing_check(34); + always @(posedge dqs_in[35]) dqs_neg_timing_check(35); + +endmodule Index: versatile_mem_ctrl/tags/Rev2/bench/ddr/ddr2_module.v =================================================================== --- versatile_mem_ctrl/tags/Rev2/bench/ddr/ddr2_module.v (nonexistent) +++ versatile_mem_ctrl/tags/Rev2/bench/ddr/ddr2_module.v (revision 109) @@ -0,0 +1,367 @@ +/**************************************************************************************** +* +* File Name: ddr2_module.v +* +* Dependencies: ddr2.v, ddr2.v, ddr2_parameters.vh +* +* Description: Micron SDRAM DDR2 (Double Data Rate 2) module model +* +* Limitation: - SPD (Serial Presence-Detect) is not modeled +* +* Disclaimer This software code and all associated documentation, comments or other +* of Warranty: information (collectively "Software") is provided "AS IS" without +* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY +* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES +* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT +* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE +* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE. +* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR +* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS, +* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE +* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI, +* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT, +* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING, +* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, +* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE +* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH +* DAMAGES. Because some jurisdictions prohibit the exclusion or +* limitation of liability for consequential or incidental damages, the +* above limitation may not apply to you. +* +* Copyright 2003 Micron Technology, Inc. All rights reserved. +* +****************************************************************************************/ + `timescale 1ps / 1ps + +module ddr2_module ( +`ifdef SODIMM +`else + reset_n, + cb , +`endif + ck , + ck_n , + cke , + s_n , + ras_n , + cas_n , + we_n , + ba , + addr , + odt , + dqs , + dqs_n , + dq , + scl , + sa , + sda +); + +`include "ddr2_parameters.vh" + + input [1:0] cke ; + input ras_n ; + input cas_n ; + input we_n ; + input [2:0] ba ; + input [15:0] addr ; + input [1:0] odt ; + inout [17:0] dqs ; + inout [17:0] dqs_n ; + inout [63:0] dq ; + input scl ; // no connect + inout sda ; // no connect + +`ifdef QUAD_RANK + initial if (DEBUG) $display("%m: Quad Rank"); +`else `ifdef DUAL_RANK + initial if (DEBUG) $display("%m: Dual Rank"); +`else + initial if (DEBUG) $display("%m: Single Rank"); +`endif `endif + +`ifdef ECC + initial if (DEBUG) $display("%m: ECC"); + `ifdef SODIMM + initial begin + $display("%m ERROR: ECC is not available on SODIMM configurations"); + if (STOP_ON_ERROR) $stop(0); + end + `endif +`else + initial if (DEBUG) $display("%m: non ECC"); +`endif + +`ifdef RDIMM + initial if (DEBUG) $display("%m: RDIMM"); + input reset_n; + input ck ; + input ck_n ; + input [3:0] s_n ; + inout [7:0] cb ; + input [2:0] sa ; // no connect + + wire [5:0] rck = {6{ck}}; + wire [5:0] rck_n = {6{ck_n}}; + reg [3:0] rs_n ; + reg rras_n ; + reg rcas_n ; + reg rwe_n ; + reg [2:0] rba ; + reg [15:0] raddr ; + reg [3:0] rcke ; + reg [3:0] rodt ; + + always @(negedge reset_n or posedge ck) begin + if (!reset_n) begin + rs_n <= #(500) 0; + rras_n <= #(500) 0; + rcas_n <= #(500) 0; + rwe_n <= #(500) 0; + rba <= #(500) 0; + raddr <= #(500) 0; + rcke <= #(500) 0; + rodt <= #(500) 0; + end else begin + rs_n <= #(500) s_n ; + rras_n <= #(500) ras_n; + rcas_n <= #(500) cas_n; + rwe_n <= #(500) we_n ; + rba <= #(500) ba ; + raddr <= #(500) addr ; + `ifdef QUAD_RANK + rcke <= #(500) {{2{cke[1]}}, {2{cke[0]}}}; + rodt <= #(500) {{2{odt[1]}}, {2{odt[0]}}}; + `else + rcke <= #(500) {2'b00, cke}; + rodt <= #(500) {2'b00, odt}; + `endif + + end + end +`else + `ifdef SODIMM + initial if (DEBUG) $display("%m: SODIMM"); + input [1:0] ck ; + input [1:0] ck_n ; + input [1:0] s_n ; + input [1:0] sa ; // no connect + + wire [7:0] cb; + wire [5:0] rck = {{3{ck[1]}}, {3{ck[0]}}}; + wire [5:0] rck_n = {{3{ck_n[1]}}, {3{ck_n[0]}}}; + `else + initial if (DEBUG) $display("%m: UDIMM"); + input reset_n; + input [2:0] ck ; + input [2:0] ck_n ; + input [1:0] s_n ; + inout [7:0] cb ; + input [2:0] sa ; // no connect + + wire [5:0] rck = {2{ck}}; + wire [5:0] rck_n = {2{ck_n}}; + `endif + + wire [2:0] rba = ba ; + wire [15:0] raddr = addr ; + wire rras_n = ras_n; + wire rcas_n = cas_n; + wire rwe_n = we_n ; + `ifdef QUAD_RANK + wire [3:0] rs_n = {{2{s_n[1]}}, {2{s_n[0]}}}; + wire [3:0] rcke = {{2{cke[1]}}, {2{cke[0]}}}; + wire [3:0] rodt = {{2{odt[1]}}, {2{odt[0]}}}; + `else + wire [3:0] rs_n = {2'b00, s_n}; + wire [3:0] rcke = {2'b00, cke}; + wire [3:0] rodt = {2'b00, odt}; + `endif +`endif + wire [15:0] rcb = {8'b0, cb}; + wire zero = 1'b0; + wire one = 1'b1; + + //ddr2 (ck , ck_n , cke , cs_n , ras_n , cas_n , we_n , dm_rdqs , ba , addr , dq , dqs , dqs_n , rdqs_n , odt ); +`ifdef x4 + initial if (DEBUG) $display("%m: Component Width = x4"); + ddr2 U1R0 (rck[1], rck_n[1], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [ 3: 0], dqs[ 0] , dqs_n[ 0], , rodt[0]); + ddr2 U2R0 (rck[1], rck_n[1], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [11: 8], dqs[ 1] , dqs_n[ 1], , rodt[0]); + ddr2 U3R0 (rck[1], rck_n[1], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [19:16], dqs[ 2] , dqs_n[ 2], , rodt[0]); + ddr2 U4R0 (rck[0], rck_n[0], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [27:24], dqs[ 3] , dqs_n[ 3], , rodt[0]); + ddr2 U6R0 (rck[0], rck_n[0], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [35:32], dqs[ 4] , dqs_n[ 4], , rodt[0]); + ddr2 U7R0 (rck[2], rck_n[2], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [43:40], dqs[ 5] , dqs_n[ 5], , rodt[0]); + ddr2 U8R0 (rck[2], rck_n[2], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [51:48], dqs[ 6] , dqs_n[ 6], , rodt[0]); + ddr2 U9R0 (rck[2], rck_n[2], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [59:56], dqs[ 7] , dqs_n[ 7], , rodt[0]); + `ifdef ECC + ddr2 U5R0 (rck[0], rck_n[0], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], rcb[ 3: 0], dqs[ 8] , dqs_n[ 8], , rodt[0]); + `endif + ddr2 U18R0 (rck[1], rck_n[1], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [ 7: 4], dqs[ 9] , dqs_n[ 9], , rodt[0]); + ddr2 U17R0 (rck[1], rck_n[1], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [15:12], dqs[ 10] , dqs_n[ 10], , rodt[0]); + ddr2 U16R0 (rck[1], rck_n[1], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [23:20], dqs[ 11] , dqs_n[ 11], , rodt[0]); + ddr2 U15R0 (rck[0], rck_n[0], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [31:28], dqs[ 12] , dqs_n[ 12], , rodt[0]); + ddr2 U13R0 (rck[0], rck_n[0], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [39:36], dqs[ 13] , dqs_n[ 13], , rodt[0]); + ddr2 U12R0 (rck[2], rck_n[2], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [47:44], dqs[ 14] , dqs_n[ 14], , rodt[0]); + ddr2 U11R0 (rck[2], rck_n[2], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [55:52], dqs[ 15] , dqs_n[ 15], , rodt[0]); + ddr2 U10R0 (rck[2], rck_n[2], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [63:60], dqs[ 16] , dqs_n[ 16], , rodt[0]); + `ifdef ECC + ddr2 U14R0 (rck[0], rck_n[0], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], rcb[ 7: 4], dqs[ 17] , dqs_n[ 17], , rodt[0]); + `endif + `ifdef DUAL_RANK + ddr2 U1R1 (rck[4], rck_n[4], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [ 3: 0], dqs[ 0] , dqs_n[ 0], , rodt[1]); + ddr2 U2R1 (rck[4], rck_n[4], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [11: 8], dqs[ 1] , dqs_n[ 1], , rodt[1]); + ddr2 U3R1 (rck[4], rck_n[4], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [19:16], dqs[ 2] , dqs_n[ 2], , rodt[1]); + ddr2 U4R1 (rck[3], rck_n[3], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [27:24], dqs[ 3] , dqs_n[ 3], , rodt[1]); + ddr2 U6R1 (rck[3], rck_n[3], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [35:32], dqs[ 4] , dqs_n[ 4], , rodt[1]); + ddr2 U7R1 (rck[5], rck_n[5], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [43:40], dqs[ 5] , dqs_n[ 5], , rodt[1]); + ddr2 U8R1 (rck[5], rck_n[5], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [51:48], dqs[ 6] , dqs_n[ 6], , rodt[1]); + ddr2 U9R1 (rck[5], rck_n[5], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [59:56], dqs[ 7] , dqs_n[ 7], , rodt[1]); + `ifdef ECC + ddr2 U5R1 (rck[3], rck_n[3], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], rcb[ 3: 0], dqs[ 8] , dqs_n[ 8], , rodt[1]); + `endif + ddr2 U18R1 (rck[4], rck_n[4], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [ 7: 4], dqs[ 9] , dqs_n[ 9], , rodt[1]); + ddr2 U17R1 (rck[4], rck_n[4], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [15:12], dqs[ 10] , dqs_n[ 10], , rodt[1]); + ddr2 U16R1 (rck[4], rck_n[4], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [23:20], dqs[ 11] , dqs_n[ 11], , rodt[1]); + ddr2 U15R1 (rck[3], rck_n[3], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [31:28], dqs[ 12] , dqs_n[ 12], , rodt[1]); + ddr2 U13R1 (rck[3], rck_n[3], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [39:36], dqs[ 13] , dqs_n[ 13], , rodt[1]); + ddr2 U12R1 (rck[5], rck_n[5], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [47:44], dqs[ 14] , dqs_n[ 14], , rodt[1]); + ddr2 U11R1 (rck[5], rck_n[5], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [55:52], dqs[ 15] , dqs_n[ 15], , rodt[1]); + ddr2 U10R1 (rck[5], rck_n[5], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [63:60], dqs[ 16] , dqs_n[ 16], , rodt[1]); + `ifdef ECC + ddr2 U14R1 (rck[3], rck_n[3], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], rcb[ 7: 4], dqs[ 17] , dqs_n[ 17], , rodt[1]); + `endif + `endif + `ifdef QUAD_RANK + ddr2 U1R2 (rck[1], rck_n[1], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [ 3: 0], dqs[ 0] , dqs_n[ 0], , rodt[2]); + ddr2 U2R2 (rck[1], rck_n[1], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [11: 8], dqs[ 1] , dqs_n[ 1], , rodt[2]); + ddr2 U3R2 (rck[1], rck_n[1], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [19:16], dqs[ 2] , dqs_n[ 2], , rodt[2]); + ddr2 U4R2 (rck[0], rck_n[0], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [27:24], dqs[ 3] , dqs_n[ 3], , rodt[2]); + ddr2 U6R2 (rck[0], rck_n[0], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [35:32], dqs[ 4] , dqs_n[ 4], , rodt[2]); + ddr2 U7R2 (rck[2], rck_n[2], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [43:40], dqs[ 5] , dqs_n[ 5], , rodt[2]); + ddr2 U8R2 (rck[2], rck_n[2], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [51:48], dqs[ 6] , dqs_n[ 6], , rodt[2]); + ddr2 U9R2 (rck[2], rck_n[2], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [59:56], dqs[ 7] , dqs_n[ 7], , rodt[2]); + `ifdef ECC + ddr2 U5R2 (rck[0], rck_n[0], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], rcb[ 3: 0], dqs[ 8] , dqs_n[ 8], , rodt[2]); + `endif + ddr2 U18R2 (rck[1], rck_n[1], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [ 7: 4], dqs[ 9] , dqs_n[ 9], , rodt[2]); + ddr2 U17R2 (rck[1], rck_n[1], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [15:12], dqs[ 10] , dqs_n[ 10], , rodt[2]); + ddr2 U16R2 (rck[1], rck_n[1], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [23:20], dqs[ 11] , dqs_n[ 11], , rodt[2]); + ddr2 U15R2 (rck[0], rck_n[0], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [31:28], dqs[ 12] , dqs_n[ 12], , rodt[2]); + ddr2 U13R2 (rck[0], rck_n[0], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [39:36], dqs[ 13] , dqs_n[ 13], , rodt[2]); + ddr2 U12R2 (rck[2], rck_n[2], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [47:44], dqs[ 14] , dqs_n[ 14], , rodt[2]); + ddr2 U11R2 (rck[2], rck_n[2], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [55:52], dqs[ 15] , dqs_n[ 15], , rodt[2]); + ddr2 U10R2 (rck[2], rck_n[2], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [63:60], dqs[ 16] , dqs_n[ 16], , rodt[2]); + `ifdef ECC + ddr2 U14R2 (rck[0], rck_n[0], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], rcb[ 7: 4], dqs[ 17] , dqs_n[ 17], , rodt[2]); + `endif + ddr2 U1R3 (rck[4], rck_n[4], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [ 3: 0], dqs[ 0] , dqs_n[ 0], , rodt[3]); + ddr2 U2R3 (rck[4], rck_n[4], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [11: 8], dqs[ 1] , dqs_n[ 1], , rodt[3]); + ddr2 U3R3 (rck[4], rck_n[4], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [19:16], dqs[ 2] , dqs_n[ 2], , rodt[3]); + ddr2 U4R3 (rck[3], rck_n[3], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [27:24], dqs[ 3] , dqs_n[ 3], , rodt[3]); + ddr2 U6R3 (rck[3], rck_n[3], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [35:32], dqs[ 4] , dqs_n[ 4], , rodt[3]); + ddr2 U7R3 (rck[5], rck_n[5], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [43:40], dqs[ 5] , dqs_n[ 5], , rodt[3]); + ddr2 U8R3 (rck[5], rck_n[5], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [51:48], dqs[ 6] , dqs_n[ 6], , rodt[3]); + ddr2 U9R3 (rck[5], rck_n[5], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [59:56], dqs[ 7] , dqs_n[ 7], , rodt[3]); + `ifdef ECC + ddr2 U5R3 (rck[3], rck_n[3], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], rcb[ 3: 0], dqs[ 8] , dqs_n[ 8], , rodt[3]); + `endif + ddr2 U18R3 (rck[4], rck_n[4], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [ 7: 4], dqs[ 9] , dqs_n[ 9], , rodt[3]); + ddr2 U17R3 (rck[4], rck_n[4], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [15:12], dqs[ 10] , dqs_n[ 10], , rodt[3]); + ddr2 U16R3 (rck[4], rck_n[4], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [23:20], dqs[ 11] , dqs_n[ 11], , rodt[3]); + ddr2 U15R3 (rck[3], rck_n[3], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [31:28], dqs[ 12] , dqs_n[ 12], , rodt[3]); + ddr2 U13R3 (rck[3], rck_n[3], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [39:36], dqs[ 13] , dqs_n[ 13], , rodt[3]); + ddr2 U12R3 (rck[5], rck_n[5], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [47:44], dqs[ 14] , dqs_n[ 14], , rodt[3]); + ddr2 U11R3 (rck[5], rck_n[5], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [55:52], dqs[ 15] , dqs_n[ 15], , rodt[3]); + ddr2 U10R3 (rck[5], rck_n[5], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [63:60], dqs[ 16] , dqs_n[ 16], , rodt[3]); + `ifdef ECC + ddr2 U14R3 (rck[3], rck_n[3], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], rcb[ 7: 4], dqs[ 17] , dqs_n[ 17], , rodt[3]); + `endif + `endif +`else `ifdef x8 + initial if (DEBUG) $display("%m: Component Width = x8"); + ddr2 U1R0 (rck[1], rck_n[1], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, dqs[ 9] , rba, raddr[ADDR_BITS-1:0], dq [ 7: 0], dqs[ 0] , dqs_n[ 0], dqs_n[ 9], rodt[0]); + ddr2 U2R0 (rck[1], rck_n[1], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, dqs[10] , rba, raddr[ADDR_BITS-1:0], dq [15: 8], dqs[ 1] , dqs_n[ 1], dqs_n[10], rodt[0]); + ddr2 U3R0 (rck[1], rck_n[1], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, dqs[11] , rba, raddr[ADDR_BITS-1:0], dq [23:16], dqs[ 2] , dqs_n[ 2], dqs_n[11], rodt[0]); + ddr2 U4R0 (rck[0], rck_n[0], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, dqs[12] , rba, raddr[ADDR_BITS-1:0], dq [31:24], dqs[ 3] , dqs_n[ 3], dqs_n[12], rodt[0]); + ddr2 U6R0 (rck[0], rck_n[0], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, dqs[13] , rba, raddr[ADDR_BITS-1:0], dq [39:32], dqs[ 4] , dqs_n[ 4], dqs_n[13], rodt[0]); + ddr2 U7R0 (rck[2], rck_n[2], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, dqs[14] , rba, raddr[ADDR_BITS-1:0], dq [47:40], dqs[ 5] , dqs_n[ 5], dqs_n[14], rodt[0]); + ddr2 U8R0 (rck[2], rck_n[2], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, dqs[15] , rba, raddr[ADDR_BITS-1:0], dq [55:48], dqs[ 6] , dqs_n[ 6], dqs_n[15], rodt[0]); + ddr2 U9R0 (rck[2], rck_n[2], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, dqs[16] , rba, raddr[ADDR_BITS-1:0], dq [63:56], dqs[ 7] , dqs_n[ 7], dqs_n[16], rodt[0]); + `ifdef ECC + ddr2 U5R0 (rck[0], rck_n[0], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, dqs[17] , rba, raddr[ADDR_BITS-1:0], rcb[ 7: 0], dqs[ 8] , dqs_n[ 8], dqs_n[17], rodt[0]); + `endif + `ifdef DUAL_RANK + ddr2 U1R1 (rck[4], rck_n[4], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, dqs[ 9] , rba, raddr[ADDR_BITS-1:0], dq [ 7: 0], dqs[ 0] , dqs_n[ 0], dqs_n[ 9], rodt[1]); + ddr2 U2R1 (rck[4], rck_n[4], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, dqs[10] , rba, raddr[ADDR_BITS-1:0], dq [15: 8], dqs[ 1] , dqs_n[ 1], dqs_n[10], rodt[1]); + ddr2 U3R1 (rck[4], rck_n[4], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, dqs[11] , rba, raddr[ADDR_BITS-1:0], dq [23:16], dqs[ 2] , dqs_n[ 2], dqs_n[11], rodt[1]); + ddr2 U4R1 (rck[3], rck_n[3], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, dqs[12] , rba, raddr[ADDR_BITS-1:0], dq [31:24], dqs[ 3] , dqs_n[ 3], dqs_n[12], rodt[1]); + ddr2 U6R1 (rck[3], rck_n[3], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, dqs[13] , rba, raddr[ADDR_BITS-1:0], dq [39:32], dqs[ 4] , dqs_n[ 4], dqs_n[13], rodt[1]); + ddr2 U7R1 (rck[5], rck_n[5], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, dqs[14] , rba, raddr[ADDR_BITS-1:0], dq [47:40], dqs[ 5] , dqs_n[ 5], dqs_n[14], rodt[1]); + ddr2 U8R1 (rck[5], rck_n[5], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, dqs[15] , rba, raddr[ADDR_BITS-1:0], dq [55:48], dqs[ 6] , dqs_n[ 6], dqs_n[15], rodt[1]); + ddr2 U9R1 (rck[5], rck_n[5], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, dqs[16] , rba, raddr[ADDR_BITS-1:0], dq [63:56], dqs[ 7] , dqs_n[ 7], dqs_n[16], rodt[1]); + `ifdef ECC + ddr2 U5R1 (rck[3], rck_n[3], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, dqs[17] , rba, raddr[ADDR_BITS-1:0], rcb[ 7: 0], dqs[ 8] , dqs_n[ 8], dqs_n[17], rodt[1]); + `endif + `endif + `ifdef QUAD_RANK + ddr2 U1R2 (rck[1], rck_n[1], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, dqs[ 9] , rba, raddr[ADDR_BITS-1:0], dq [ 7: 0], dqs[ 0] , dqs_n[ 0], dqs_n[ 9], rodt[2]); + ddr2 U2R2 (rck[1], rck_n[1], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, dqs[10] , rba, raddr[ADDR_BITS-1:0], dq [15: 8], dqs[ 1] , dqs_n[ 1], dqs_n[10], rodt[2]); + ddr2 U3R2 (rck[1], rck_n[1], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, dqs[11] , rba, raddr[ADDR_BITS-1:0], dq [23:16], dqs[ 2] , dqs_n[ 2], dqs_n[11], rodt[2]); + ddr2 U4R2 (rck[0], rck_n[0], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, dqs[12] , rba, raddr[ADDR_BITS-1:0], dq [31:24], dqs[ 3] , dqs_n[ 3], dqs_n[12], rodt[2]); + ddr2 U6R2 (rck[0], rck_n[0], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, dqs[13] , rba, raddr[ADDR_BITS-1:0], dq [39:32], dqs[ 4] , dqs_n[ 4], dqs_n[13], rodt[2]); + ddr2 U7R2 (rck[2], rck_n[2], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, dqs[14] , rba, raddr[ADDR_BITS-1:0], dq [47:40], dqs[ 5] , dqs_n[ 5], dqs_n[14], rodt[2]); + ddr2 U8R2 (rck[2], rck_n[2], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, dqs[15] , rba, raddr[ADDR_BITS-1:0], dq [55:48], dqs[ 6] , dqs_n[ 6], dqs_n[15], rodt[2]); + ddr2 U9R2 (rck[2], rck_n[2], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, dqs[16] , rba, raddr[ADDR_BITS-1:0], dq [63:56], dqs[ 7] , dqs_n[ 7], dqs_n[16], rodt[2]); + `ifdef ECC + ddr2 U5R2 (rck[0], rck_n[0], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, dqs[17] , rba, raddr[ADDR_BITS-1:0], rcb[ 7: 0], dqs[ 8] , dqs_n[ 8], dqs_n[17], rodt[2]); + `endif + ddr2 U1R3 (rck[4], rck_n[4], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, dqs[ 9] , rba, raddr[ADDR_BITS-1:0], dq [ 7: 0], dqs[ 0] , dqs_n[ 0], dqs_n[ 9], rodt[3]); + ddr2 U2R3 (rck[4], rck_n[4], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, dqs[10] , rba, raddr[ADDR_BITS-1:0], dq [15: 8], dqs[ 1] , dqs_n[ 1], dqs_n[10], rodt[3]); + ddr2 U3R3 (rck[4], rck_n[4], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, dqs[11] , rba, raddr[ADDR_BITS-1:0], dq [23:16], dqs[ 2] , dqs_n[ 2], dqs_n[11], rodt[3]); + ddr2 U4R3 (rck[3], rck_n[3], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, dqs[12] , rba, raddr[ADDR_BITS-1:0], dq [31:24], dqs[ 3] , dqs_n[ 3], dqs_n[12], rodt[3]); + ddr2 U6R3 (rck[3], rck_n[3], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, dqs[13] , rba, raddr[ADDR_BITS-1:0], dq [39:32], dqs[ 4] , dqs_n[ 4], dqs_n[13], rodt[3]); + ddr2 U7R3 (rck[5], rck_n[5], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, dqs[14] , rba, raddr[ADDR_BITS-1:0], dq [47:40], dqs[ 5] , dqs_n[ 5], dqs_n[14], rodt[3]); + ddr2 U8R3 (rck[5], rck_n[5], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, dqs[15] , rba, raddr[ADDR_BITS-1:0], dq [55:48], dqs[ 6] , dqs_n[ 6], dqs_n[15], rodt[3]); + ddr2 U9R3 (rck[5], rck_n[5], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, dqs[16] , rba, raddr[ADDR_BITS-1:0], dq [63:56], dqs[ 7] , dqs_n[ 7], dqs_n[16], rodt[3]); + `ifdef ECC + ddr2 U5R3 (rck[3], rck_n[3], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, dqs[17] , rba, raddr[ADDR_BITS-1:0], rcb[ 7: 0], dqs[ 8] , dqs_n[ 8], dqs_n[17], rodt[3]); + `endif + `endif +`else `ifdef x16 + initial if (DEBUG) $display("%m: Component Width = x16"); + ddr2 U1R0 (rck[1], rck_n[1], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, dqs[10: 9] , rba, raddr[ADDR_BITS-1:0], dq [15: 0], dqs[1:0] , dqs_n[1:0], , rodt[0]); + ddr2 U2R0 (rck[1], rck_n[1], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, dqs[12:11] , rba, raddr[ADDR_BITS-1:0], dq [31:16], dqs[3:2] , dqs_n[3:2], , rodt[0]); + ddr2 U4R0 (rck[2], rck_n[2], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, dqs[14:13] , rba, raddr[ADDR_BITS-1:0], dq [47:32], dqs[5:4] , dqs_n[5:4], , rodt[0]); + ddr2 U5R0 (rck[2], rck_n[2], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, dqs[16:15] , rba, raddr[ADDR_BITS-1:0], dq [63:48], dqs[7:6] , dqs_n[7:6], , rodt[0]); + `ifdef ECC + ddr2 U3R0 (rck[0], rck_n[0], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, {one, dqs[17]}, rba, raddr[ADDR_BITS-1:0], rcb[15: 0], {zero, dqs[8]}, {one, dqs_n[8]}, , rodt[0]); + `endif + `ifdef DUAL_RANK + ddr2 U1R1 (rck[4], rck_n[4], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, dqs[10: 9] , rba, raddr[ADDR_BITS-1:0], dq [15: 0], dqs[1:0] , dqs_n[1:0], , rodt[1]); + ddr2 U2R1 (rck[4], rck_n[4], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, dqs[12:11] , rba, raddr[ADDR_BITS-1:0], dq [31:16], dqs[3:2] , dqs_n[3:2], , rodt[1]); + ddr2 U4R1 (rck[5], rck_n[5], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, dqs[14:13] , rba, raddr[ADDR_BITS-1:0], dq [47:32], dqs[5:4] , dqs_n[5:4], , rodt[1]); + ddr2 U5R1 (rck[5], rck_n[5], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, dqs[16:15] , rba, raddr[ADDR_BITS-1:0], dq [63:48], dqs[7:6] , dqs_n[7:6], , rodt[1]); + `ifdef ECC + ddr2 U3R1 (rck[3], rck_n[3], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, {one, dqs[17]}, rba, raddr[ADDR_BITS-1:0], rcb[15: 0], {zero, dqs[8]}, {one, dqs_n[8]}, , rodt[1]); + `endif + `endif + `ifdef QUAD_RANK + ddr2 U1R2 (rck[1], rck_n[1], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, dqs[10: 9] , rba, raddr[ADDR_BITS-1:0], dq [15: 0], dqs[1:0] , dqs_n[1:0], , rodt[2]); + ddr2 U2R2 (rck[1], rck_n[1], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, dqs[12:11] , rba, raddr[ADDR_BITS-1:0], dq [31:16], dqs[3:2] , dqs_n[3:2], , rodt[2]); + ddr2 U4R2 (rck[2], rck_n[2], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, dqs[14:13] , rba, raddr[ADDR_BITS-1:0], dq [47:32], dqs[5:4] , dqs_n[5:4], , rodt[2]); + ddr2 U5R2 (rck[2], rck_n[2], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, dqs[16:15] , rba, raddr[ADDR_BITS-1:0], dq [63:48], dqs[7:6] , dqs_n[7:6], , rodt[2]); + `ifdef ECC + ddr2 U3R2 (rck[0], rck_n[0], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, {one, dqs[17]}, rba, raddr[ADDR_BITS-1:0], rcb[15: 0], {zero, dqs[8]}, {one, dqs_n[8]}, , rodt[2]); + `endif + ddr2 U1R3 (rck[4], rck_n[4], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, dqs[10: 9] , rba, raddr[ADDR_BITS-1:0], dq [15: 0], dqs[1:0] , dqs_n[1:0], , rodt[3]); + ddr2 U2R3 (rck[4], rck_n[4], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, dqs[12:11] , rba, raddr[ADDR_BITS-1:0], dq [31:16], dqs[3:2] , dqs_n[3:2], , rodt[3]); + ddr2 U4R3 (rck[5], rck_n[5], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, dqs[14:13] , rba, raddr[ADDR_BITS-1:0], dq [47:32], dqs[5:4] , dqs_n[5:4], , rodt[3]); + ddr2 U5R3 (rck[5], rck_n[5], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, dqs[16:15] , rba, raddr[ADDR_BITS-1:0], dq [63:48], dqs[7:6] , dqs_n[7:6], , rodt[3]); + `ifdef ECC + ddr2 U3R3 (rck[3], rck_n[3], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, {one, dqs[17]}, rba, raddr[ADDR_BITS-1:0], rcb[15: 0], {zero, dqs[8]}, {one, dqs_n[8]}, , rodt[3]); + `endif + `endif +`endif `endif `endif + +endmodule Index: versatile_mem_ctrl/tags/Rev2/bench/ddr/subtest.vh =================================================================== --- versatile_mem_ctrl/tags/Rev2/bench/ddr/subtest.vh (nonexistent) +++ versatile_mem_ctrl/tags/Rev2/bench/ddr/subtest.vh (revision 109) @@ -0,0 +1,225 @@ +/**************************************************************************************** +* +* File Name: subtest.vh +* +* Description: Micron SDRAM DDR2 (Double Data Rate 2) +* This file is included by tb.v +* +* Disclaimer This software code and all associated documentation, comments or other +* of Warranty: information (collectively "Software") is provided "AS IS" without +* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY +* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES +* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT +* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE +* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE. +* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR +* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS, +* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE +* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI, +* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT, +* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING, +* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, +* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE +* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH +* DAMAGES. Because some jurisdictions prohibit the exclusion or +* limitation of liability for consequential or incidental damages, the +* above limitation may not apply to you. +* +* Copyright 2003 Micron Technology, Inc. All rights reserved. +* +****************************************************************************************/ + + initial begin : test + cke <= 1'b0; + cs_n <= 1'b1; + ras_n <= 1'b1; + cas_n <= 1'b1; + we_n <= 1'b1; + ba <= {BA_BITS{1'bz}}; + a <= {ADDR_BITS{1'bz}}; + odt <= 1'b0; + dq_en <= 1'b0; + dqs_en <= 1'b0; + + cke <= 1'b1; + + // POWERUP SECTION + power_up; + + // INITIALIZE SECTION + precharge (0, 1); // Precharge all banks + nop (trp); + + load_mode (2, 0); // Extended Mode Register (2) + nop (tmrd-1); + + load_mode (3, 0); // Extended Mode Register (3) + nop (tmrd-1); + + load_mode (1, 13'b0_0_0_000_0_000_1_0_0); // Extended Mode Register with DLL Enable + nop (tmrd-1); + + load_mode (0, 13'b0_000_1_0_000_0_011 | (twr-1)<<9 | taa<<4); // Mode Register without DLL Reset (bl=8) + nop (tmrd-1); + + precharge (0, 1); // Precharge all banks + nop (trp); + + refresh; + nop (trfc-1); + + refresh; + nop (trfc-1); + + load_mode (0, 13'b0_000_0_0_000_0_011 | (twr-1)<<9 | taa<<4); // Mode Register without DLL Reset (bl=8) + nop (tmrd-1); + + load_mode (1, 13'b0_0_0_111_0_000_1_0_0); // Extended Mode Register with OCD Default + nop (tmrd-1); + + load_mode (1, 13'b0_0_0_000_0_000_1_0_0); // Extended Mode Register with OCD Exit + nop (tmrd-1); + + // DLL RESET ENABLE - you will need 200 TCK before any read command. + nop (200); + + // WRITE SECTION + activate (0, 0); // Activate Bank 0, Row 0 + nop (trcd-1); + write (0, 4, 0, 0, 'h3210); // Write Bank 0, Col 0 + nop (tccd-1); + write (0, 0, 1, 0, 'h0123); // Write Bank 0, Col 0 + + activate (1, 0); // Activate Bank 1, Row 0 + nop (trcd-1); + write (1, 0, 1, 0, 'h4567); // Write Bank 1, Col 0 + + activate (2, 0); // Activate Bank 2, Row 0 + nop (trcd-1); + write (2, 0, 1, 0, 'h89AB); // Write Bank 2, Col 0 + + activate (3, 0); // Activate Bank 3, Row 0 + nop (trcd-1); + write (3, 0, 1, 0, 'hCDEF); // Write Bank 3, Col 0 + + nop (cl - 1 + bl/2 + twtr-1); + + nop (tras); + + // READ SECTION + activate (0, 0); // Activate Bank 0, Row 0 + nop (trrd-1); + activate (1, 0); // Activate Bank 1, Row 0 + nop (trrd-1); + activate (2, 0); // Activate Bank 2, Row 0 + nop (trrd-1); + activate (3, 0); // Activate Bank 3, Row 0 + read (0, 0, 1); // Read Bank 0, Col 0 + nop (bl/2); + read (1, 1, 1); // Read Bank 1, Col 1 + nop (bl/2); + read (2, 2, 1); // Read Bank 2, Col 2 + nop (bl/2); + read (3, 3, 1); // Read Bank 3, Col 3 + nop (rl + bl/2); + + activate (0, 0); // Activate Bank 0, Row 0 + nop (trrd-1); + activate (1, 0); // Activate Bank 1, Row 0 + nop (trcd-1); + $display ("%m at time %t: Figure 22: Consecutive READ Bursts", $time); + read (0, 0, 0); // Read Bank 0, Col 0 + nop (bl/2-1); + read (0, 4, 0); // Read Bank 0, Col 4 + nop (rl + bl/2); + + $display ("%m at time %t: Figure 23: Nonconsecutive READ Bursts", $time); + read (0, 0, 0); // Read Bank 0, Col 0 + nop (bl/2); + read (0, 4, 0); // Read Bank 0, Col 4 + nop (rl + bl/2); + + $display ("%m at time %t: Figure 24: READ Interrupted by READ", $time); + read (0, 0, 0); // Read Bank 0, Col 0 + nop (tccd-1); + read (1, 0, 0); // Read Bank 0, Col 0 + nop (rl + bl/2); + + $display ("%m at time %t: Figure 25 & 26: READ to PRECHARGE", $time); + read (0, 0, 0); // Read Bank 0, Col 0 + nop (al + bl/2 + trtp - 2); + precharge (0, 0); // Precharge Bank 0 + nop (trp-1); + + activate (0, 0); // Activate Bank 0, Row 0 + nop (trcd-1); + $display ("%m at time %t: Figure 27: READ to WRITE", $time); + read (0, 0, 0); // Read Bank 0, Col 0 + nop (rl + bl/2 - wl); + write (0, 0, 1, 0, 'h0123); // Write Bank 0, Col 0 + nop (wl + bl/2 + twr + trp-1); + + activate (0, 0); // Activate Bank 0, Row 0 + nop (trcd-1); + $display ("%m at time %t: Figure 36: Nonconsecutive WRITE to WRITE", $time); + write (0, 0, 0, 0, 'h0123); // Write Bank 0, Col 0 + nop (bl/2); + write (0, 4, 0, 0, 'h0123); // Write Bank 0, Col 0 + nop (wl + bl/2); + + $display ("%m at time %t: Figure 37: Random WRITE Cycles", $time); + write (0, 0, 0, 0, 'h0123); // Write Bank 0, Col 0 + nop (bl/2-1); + write (0, 4, 0, 0, 'h0123); // Write Bank 0, Col 0 + nop (wl + bl/2); + + $display ("%m at time %t: Figure 37: Figure 38: WRITE Interrupted by WRITE", $time); + write (0, 0, 0, 0, 'h0123); // Write Bank 0, Col 0 + nop (tccd-1); + write (1, 4, 0, 0, 'h0123); // Write Bank 0, Col 0 + nop (wl + bl/2); + + $display ("%m at time %t: Figure 39: WRITE to READ", $time); + write (0, 0, 0, 0, 'h0123); // Write Bank 0, Col 0 + nop (wl + bl/2 + twtr-1); + read_verify (0, 0, 0, 0, 'h0123); // Read Bank 0, Col 0 + nop (rl + bl/2); + + $display ("%m at time %t: Figure 40: WRITE to PRECHARGE", $time); + write (0, 0, 0, 0, 'h0123); // Write Bank 0, Col 0 + nop (wl + bl/2 + twr-1); + precharge (0, 1); // Precharge all banks + nop (trp-1); + + // odt Section + $display ("%m at time %t: Figure 60: odt Timing for Active or Fast-Exit Power-Down Mode", $time); + odt = 1'b1; + nop (1); + odt = 1'b0; + nop (tanpd); + + $display ("%m at time %t: Figure 61: odt timing for Slow-Exit or Precharge Power-Down Modes", $time); + cke = 1'b0; + @(negedge ck); + odt = 1'b1; + @(negedge ck); + odt = 1'b0; + repeat(tanpd)@(negedge ck); + nop (taxpd); + + $display ("%m at time %t: Figure 62 & 63: odt Transition Timings when Entering Power-Down Mode", $time); + odt = 1'b1; + nop (tanpd); + power_down (tcke); + + // Self Refresh Section + nop (taxpd); + odt = 1'b0; + nop (3); // taofd + self_refresh (tcke); + nop (tdllk); + nop (tcke); + + test_done; + end Index: versatile_mem_ctrl/tags/Rev2/bench/ddr/tb.do =================================================================== --- versatile_mem_ctrl/tags/Rev2/bench/ddr/tb.do (nonexistent) +++ versatile_mem_ctrl/tags/Rev2/bench/ddr/tb.do (revision 109) @@ -0,0 +1,31 @@ +######################################################################################### +# +# Disclaimer This software code and all associated documentation, comments or other +# of Warranty: information (collectively "Software") is provided "AS IS" without +# warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY +# DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +# TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES +# OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT +# WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE +# OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE. +# FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR +# THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS, +# ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE +# OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI, +# ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT, +# INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING, +# WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, +# OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE +# THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH +# DAMAGES. Because some jurisdictions prohibit the exclusion or +# limitation of liability for consequential or incidental damages, the +# above limitation may not apply to you. +# +# Copyright 2003 Micron Technology, Inc. All rights reserved. +# +######################################################################################### + +vlog -novopt ddr2.v tb.v +vsim -novopt tb +add wave -p sdramddr2/* +run -all Index: versatile_mem_ctrl/tags/Rev2/bench/ddr/tb.v =================================================================== --- versatile_mem_ctrl/tags/Rev2/bench/ddr/tb.v (nonexistent) +++ versatile_mem_ctrl/tags/Rev2/bench/ddr/tb.v (revision 109) @@ -0,0 +1,468 @@ +/**************************************************************************************** +* +* File Name: tb.v +* +* Dependencies: ddr2.v, ddr2_parameters.vh +* +* Description: Micron SDRAM DDR2 (Double Data Rate 2) test bench +* +* Note: -Set simulator resolution to "ps" accuracy +* -Set Debug = 0 to disable $display messages +* +* Disclaimer This software code and all associated documentation, comments or other +* of Warranty: information (collectively "Software") is provided "AS IS" without +* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY +* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES +* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT +* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE +* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE. +* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR +* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS, +* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE +* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI, +* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT, +* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING, +* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, +* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE +* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH +* DAMAGES. Because some jurisdictions prohibit the exclusion or +* limitation of liability for consequential or incidental damages, the +* above limitation may not apply to you. +* +* Copyright 2003 Micron Technology, Inc. All rights reserved. +* +****************************************************************************************/ + +// DO NOT CHANGE THE TIMESCALE + +`timescale 1ps / 1ps + +module tb; + +`include "ddr2_parameters.vh" + + // ports + reg ck; + wire ck_n = ~ck; + reg cke; + reg cs_n; + reg ras_n; + reg cas_n; + reg we_n; + reg [BA_BITS-1:0] ba; + reg [ADDR_BITS-1:0] a; + wire [DM_BITS-1:0] dm; + wire [DQ_BITS-1:0] dq; + wire [DQS_BITS-1:0] dqs; + wire [DQS_BITS-1:0] dqs_n; + wire [DQS_BITS-1:0] rdqs_n; + reg odt; + + // mode registers + reg [ADDR_BITS-1:0] mode_reg0; //Mode Register + reg [ADDR_BITS-1:0] mode_reg1; //Extended Mode Register + wire [2:0] cl = mode_reg0[6:4]; //CAS Latency + wire bo = mode_reg0[3]; //Burst Order + wire [7:0] bl = (1< $rtoi(number)) + ceil = $rtoi(number) + 1; + else + ceil = number; + endfunction + + function integer max; + input arg1; + input arg2; + integer arg1; + integer arg2; + if (arg1 > arg2) + max = arg1; + else + max = arg2; + endfunction + + task power_up; + begin + cke <= 1'b0; + odt <= 1'b0; + repeat(10) @(negedge ck); + cke <= 1'b1; + nop (400000/tck+1); + end + endtask + + task load_mode; + input [BA_BITS-1:0] bank; + input [ADDR_BITS-1:0] addr; + begin + case (bank) + 0: mode_reg0 = addr; + 1: mode_reg1 = addr; + endcase + cke <= 1'b1; + cs_n <= 1'b0; + ras_n <= 1'b0; + cas_n <= 1'b0; + we_n <= 1'b0; + ba <= bank; + a <= addr; + @(negedge ck); + end + endtask + + task refresh; + begin + cke <= 1'b1; + cs_n <= 1'b0; + ras_n <= 1'b0; + cas_n <= 1'b0; + we_n <= 1'b1; + @(negedge ck); + end + endtask + + task precharge; + input [BA_BITS-1:0] bank; + input ap; //precharge all + begin + cke <= 1'b1; + cs_n <= 1'b0; + ras_n <= 1'b0; + cas_n <= 1'b1; + we_n <= 1'b0; + ba <= bank; + a <= (ap<<10); + @(negedge ck); + end + endtask + + task activate; + input [BA_BITS-1:0] bank; + input [ROW_BITS-1:0] row; + begin + cke <= 1'b1; + cs_n <= 1'b0; + ras_n <= 1'b0; + cas_n <= 1'b1; + we_n <= 1'b1; + ba <= bank; + a <= row; + @(negedge ck); + end + endtask + + //write task supports burst lengths <= 8 + task write; + input [BA_BITS-1:0] bank; + input [COL_BITS-1:0] col; + input ap; //Auto Precharge + input [8*DM_BITS-1:0] dm; + input [8*DQ_BITS-1:0] dq; + reg [ADDR_BITS-1:0] atemp [1:0]; + integer i; + begin + cke <= 1'b1; + cs_n <= 1'b0; + ras_n <= 1'b1; + cas_n <= 1'b0; + we_n <= 1'b0; + ba <= bank; + atemp[0] = col & 10'h3ff; //addr[ 9: 0] = COL[ 9: 0] + atemp[1] = (col>>10)<<11; //addr[ N:11] = COL[ N:10] + a <= atemp[0] | atemp[1] | (ap<<10); + for (i=0; i<=bl; i=i+1) begin + + dqs_en <= #(wl*tck + i*tck/2) 1'b1; + if (i%2 == 0) begin + dqs_out <= #(wl*tck + i*tck/2) {DQS_BITS{1'b0}}; + end else begin + dqs_out <= #(wl*tck + i*tck/2) {DQS_BITS{1'b1}}; + end + + dq_en <= #(wl*tck + i*tck/2 + tck/4) 1'b1; + dm_out <= #(wl*tck + i*tck/2 + tck/4) dm>>i*DM_BITS; + dq_out <= #(wl*tck + i*tck/2 + tck/4) dq>>i*DQ_BITS; + end + dqs_en <= #(wl*tck + bl*tck/2 + tck/2) 1'b0; + dq_en <= #(wl*tck + bl*tck/2 + tck/4) 1'b0; + @(negedge ck); + end + endtask + + // read without data verification + task read; + input [BA_BITS-1:0] bank; + input [COL_BITS-1:0] col; + input ap; //Auto Precharge + reg [ADDR_BITS-1:0] atemp [1:0]; + begin + cke <= 1'b1; + cs_n <= 1'b0; + ras_n <= 1'b1; + cas_n <= 1'b0; + we_n <= 1'b1; + ba <= bank; + atemp[0] = col & 10'h3ff; //addr[ 9: 0] = COL[ 9: 0] + atemp[1] = (col>>10)<<11; //addr[ N:11] = COL[ N:10] + a <= atemp[0] | atemp[1] | (ap<<10); + @(negedge ck); + end + endtask + + task nop; + input [31:0] count; + begin + cke <= 1'b1; + cs_n <= 1'b0; + ras_n <= 1'b1; + cas_n <= 1'b1; + we_n <= 1'b1; + repeat(count) @(negedge ck); + end + endtask + + task deselect; + input [31:0] count; + begin + cke <= 1'b1; + cs_n <= 1'b1; + ras_n <= 1'b1; + cas_n <= 1'b1; + we_n <= 1'b1; + repeat(count) @(negedge ck); + end + endtask + + task power_down; + input [31:0] count; + begin + cke <= 1'b0; + cs_n <= 1'b1; + ras_n <= 1'b1; + cas_n <= 1'b1; + we_n <= 1'b1; + repeat(count) @(negedge ck); + end + endtask + + task self_refresh; + input [31:0] count; + begin + cke <= 1'b0; + cs_n <= 1'b0; + ras_n <= 1'b0; + cas_n <= 1'b0; + we_n <= 1'b1; + cs_n <= #(tck) 1'b1; + ras_n <= #(tck) 1'b1; + cas_n <= #(tck) 1'b1; + we_n <= #(tck) 1'b1; + repeat(count) @(negedge ck); + end + endtask + + // read with data verification + task read_verify; + input [BA_BITS-1:0] bank; + input [COL_BITS-1:0] col; + input ap; //Auto Precharge + input [8*DM_BITS-1:0] dm; //Expected Data Mask + input [8*DQ_BITS-1:0] dq; //Expected Data + integer i; + begin + read (bank, col, ap); + for (i=0; i> (i*DM_BITS); + dq_fifo[2*rl + i] = dq >> (i*DQ_BITS); + end + end + endtask + + // receiver(s) for data_verify process + dqrx dqrx[DQS_BITS-1:0] (dqs, dq, q0, q1, q2, q3); + + // perform data verification as a result of read_verify task call + always @(ck) begin:data_verify + integer i; + integer j; + reg [DQ_BITS-1:0] bit_mask; + reg [DM_BITS-1:0] dm_temp; + reg [DQ_BITS-1:0] dq_temp; + + for (i = !ck; (i < 2/(2.0 - !ck)); i=i+1) begin + if (dm_fifo[i] === {DM_BITS{1'bx}}) begin + burst_cntr = 0; + end else begin + + dm_temp = dm_fifo[i]; + for (j=0; j +add wave -noupdate -group {WISHBONE IF} -expand -group wb0 -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wb_dat_i_0 +add wave -noupdate -group {WISHBONE IF} -expand -group wb0 -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wb_adr_i_0 +add wave -noupdate -group {WISHBONE IF} -expand -group wb0 -format Literal /versatile_mem_ctrl_tb/dut/wb_stb_i_0 +add wave -noupdate -group {WISHBONE IF} -expand -group wb0 -format Literal /versatile_mem_ctrl_tb/dut/wb_cyc_i_0 +add wave -noupdate -group {WISHBONE IF} -expand -group wb0 -format Literal -expand /versatile_mem_ctrl_tb/dut/wb_ack_o_0 +add wave -noupdate -group {WISHBONE IF} -expand -group wb0 -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wb_dat_o_0 +add wave -noupdate -group {WISHBONE IF} -expand -group wb0 -divider +add wave -noupdate -group {WISHBONE IF} -expand -group wb1 -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wb_dat_i_1 +add wave -noupdate -group {WISHBONE IF} -expand -group wb1 -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wb_adr_i_1 +add wave -noupdate -group {WISHBONE IF} -expand -group wb1 -format Literal /versatile_mem_ctrl_tb/dut/wb_stb_i_1 +add wave -noupdate -group {WISHBONE IF} -expand -group wb1 -format Literal /versatile_mem_ctrl_tb/dut/wb_cyc_i_1 +add wave -noupdate -group {WISHBONE IF} -expand -group wb1 -format Literal -expand /versatile_mem_ctrl_tb/dut/wb_ack_o_1 +add wave -noupdate -group {WISHBONE IF} -expand -group wb1 -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wb_dat_o_1 +add wave -noupdate -group {WISHBONE IF} -expand -group wb1 -divider +add wave -noupdate -group {WISHBONE IF} -group wb2 -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wb_dat_i_2 +add wave -noupdate -group {WISHBONE IF} -group wb2 -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wb_adr_i_2 +add wave -noupdate -group {WISHBONE IF} -group wb2 -format Literal /versatile_mem_ctrl_tb/dut/wb_stb_i_2 +add wave -noupdate -group {WISHBONE IF} -group wb2 -format Literal /versatile_mem_ctrl_tb/dut/wb_cyc_i_2 +add wave -noupdate -group {WISHBONE IF} -group wb2 -format Literal /versatile_mem_ctrl_tb/dut/wb_ack_o_2 +add wave -noupdate -group {WISHBONE IF} -group wb2 -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wb_dat_o_2 +add wave -noupdate -group {WISHBONE IF} -group wb2 -divider +add wave -noupdate -group {WISHBONE IF} -group wb3 -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wb_dat_i_3 +add wave -noupdate -group {WISHBONE IF} -group wb3 -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wb_adr_i_3 +add wave -noupdate -group {WISHBONE IF} -group wb3 -format Literal /versatile_mem_ctrl_tb/dut/wb_stb_i_3 +add wave -noupdate -group {WISHBONE IF} -group wb3 -format Literal /versatile_mem_ctrl_tb/dut/wb_cyc_i_3 +add wave -noupdate -group {WISHBONE IF} -group wb3 -format Literal /versatile_mem_ctrl_tb/dut/wb_ack_o_3 +add wave -noupdate -group {WISHBONE IF} -group wb3 -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wb_dat_o_3 +add wave -noupdate -group {WISHBONE IF} -group wb3 -divider +add wave -noupdate -group {WISHBONE IF} -group Testbench -format Literal -radix ascii /versatile_mem_ctrl_tb/wb0i/statename +add wave -noupdate -group {WISHBONE IF} -group Testbench -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/wb0_dat_i +add wave -noupdate -group {WISHBONE IF} -group Testbench -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/wb0_adr_i +add wave -noupdate -group {WISHBONE IF} -group Testbench -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/wb0_dat_o +add wave -noupdate -group {WISHBONE IF} -group Testbench -format Logic /versatile_mem_ctrl_tb/wb0_ack_o +add wave -noupdate -group {WISHBONE IF} -group Testbench -divider +add wave -noupdate -group {WISHBONE IF} -group Testbench -format Literal -radix ascii /versatile_mem_ctrl_tb/wb1i/statename +add wave -noupdate -group {WISHBONE IF} -group Testbench -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/wb1_dat_i +add wave -noupdate -group {WISHBONE IF} -group Testbench -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/wb1_adr_i +add wave -noupdate -group {WISHBONE IF} -group Testbench -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/wb1_dat_o +add wave -noupdate -group {WISHBONE IF} -group Testbench -format Logic /versatile_mem_ctrl_tb/wb1_ack_o +add wave -noupdate -group {WISHBONE IF} -group Testbench -divider +add wave -noupdate -group {WISHBONE IF} -group Testbench -format Literal -radix ascii /versatile_mem_ctrl_tb/wb4i/statename +add wave -noupdate -group {WISHBONE IF} -group Testbench -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/wb4_dat_i +add wave -noupdate -group {WISHBONE IF} -group Testbench -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/wb4_adr_i +add wave -noupdate -group {WISHBONE IF} -group Testbench -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/wb4_dat_o +add wave -noupdate -group {WISHBONE IF} -group Testbench -format Logic /versatile_mem_ctrl_tb/wb4_ack_o +add wave -noupdate -group {WISHBONE IF} -group Testbench -divider +add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 0} -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[31]} +add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 0} -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[30]} +add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 0} -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[29]} +add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 0} -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[28]} +add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 0} -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[27]} +add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 0} -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[26]} +add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 0} -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[25]} +add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 0} -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[24]} +add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 0} -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[23]} +add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 0} -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[22]} +add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 0} -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[21]} +add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 0} -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[20]} +add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 0} -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[19]} +add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 0} -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[18]} +add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 0} -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[17]} +add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 0} -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[16]} +add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[15]} +add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[14]} +add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[13]} +add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[12]} +add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[11]} +add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[10]} +add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[9]} +add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[8]} +add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[7]} +add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[6]} +add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[5]} +add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[4]} +add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[3]} +add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[2]} +add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[1]} +add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[0]} +add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 1} -group FIFO_1_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[31]} +add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 1} -group FIFO_1_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[30]} +add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 1} -group FIFO_1_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[29]} +add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 1} -group FIFO_1_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[28]} +add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 1} -group FIFO_1_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[27]} +add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 1} -group FIFO_1_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[26]} +add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 1} -group FIFO_1_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[25]} +add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 1} -group FIFO_1_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[24]} +add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 1} -group FIFO_1_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[23]} +add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 1} -group FIFO_1_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[22]} +add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 1} -group FIFO_1_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[21]} +add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 1} -group FIFO_1_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[20]} +add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 1} -group FIFO_1_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[19]} +add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 1} -group FIFO_1_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[18]} +add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 1} -group FIFO_1_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[17]} +add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 1} -group FIFO_1_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[16]} +add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 1} -expand -group FIFO_1_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[15]} +add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 1} -expand -group FIFO_1_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[14]} +add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 1} -expand -group FIFO_1_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[13]} +add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 1} -expand -group FIFO_1_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[12]} +add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 1} -expand -group FIFO_1_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[11]} +add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 1} -expand -group FIFO_1_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[10]} +add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 1} -expand -group FIFO_1_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[9]} +add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 1} -expand -group FIFO_1_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[8]} +add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 1} -expand -group FIFO_1_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[7]} +add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 1} -expand -group FIFO_1_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[6]} +add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 1} -expand -group FIFO_1_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[5]} +add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 1} -expand -group FIFO_1_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[4]} +add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 1} -expand -group FIFO_1_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[3]} +add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 1} -expand -group FIFO_1_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[2]} +add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 1} -expand -group FIFO_1_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[1]} +add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 1} -expand -group FIFO_1_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[0]} +add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/rst +add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/clk +add wave -noupdate -group {MAIN STATE MACHINE} -divider State +add wave -noupdate -group {MAIN STATE MACHINE} -format Literal -radix ascii /versatile_mem_ctrl_tb/dut/ddr_16_0/statename +add wave -noupdate -group {MAIN STATE MACHINE} -divider Input +add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/bl_ack +add wave -noupdate -group {MAIN STATE MACHINE} -format Literal /versatile_mem_ctrl_tb/dut/ddr_16_0/burst_adr +add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/fifo_empty +add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/fifo_re_d +add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/next_row_open +add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/ref_delay_ack +add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/ref_req +add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/stall +add wave -noupdate -group {MAIN STATE MACHINE} -format Logic -radix hexadecimal {/versatile_mem_ctrl_tb/dut/ddr_16_0/tx_fifo_dat_o[5]} +add wave -noupdate -group {MAIN STATE MACHINE} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/ddr_16_0/tx_fifo_dat_o +add wave -noupdate -group {MAIN STATE MACHINE} -divider Output +add wave -noupdate -group {MAIN STATE MACHINE} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/ddr_16_0/a +add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/adr_init +add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/bl_en +add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/close_cur_row +add wave -noupdate -group {MAIN STATE MACHINE} -format Literal /versatile_mem_ctrl_tb/dut/ddr_16_0/cmd +add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/cs_n +add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/fifo_re +add wave -noupdate -group {MAIN STATE MACHINE} -format Literal /versatile_mem_ctrl_tb/dut/ddr_16_0/open_ba +add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/open_cur_row +add wave -noupdate -group {MAIN STATE MACHINE} -format Literal /versatile_mem_ctrl_tb/dut/ddr_16_0/open_row +add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/read +add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/ref_ack +add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/ref_delay +add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/state_idle +add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/write +add wave -noupdate -group {MAIN STATE MACHINE} -divider {Other usefull signals (Non-FSM)} +add wave -noupdate -group {MAIN STATE MACHINE} -format Literal /versatile_mem_ctrl_tb/dut/fifo_sel_domain_reg +add wave -noupdate -group {MAIN STATE MACHINE} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/fifo_dat_o +add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/state_idle +add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/tx_fifo_re_i +add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/tx_fifo_re +add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/burst_mask +add wave -noupdate -group {BURST ADDRESS} -divider State +add wave -noupdate -group {BURST ADDRESS} -format Literal -radix ascii /versatile_mem_ctrl_tb/dut/ddr_16_0/statename +add wave -noupdate -group {BURST ADDRESS} -divider {Burst Address} +add wave -noupdate -group {BURST ADDRESS} -format Logic /versatile_mem_ctrl_tb/dut/inc_adr0/rst +add wave -noupdate -group {BURST ADDRESS} -format Logic /versatile_mem_ctrl_tb/dut/inc_adr0/clk +add wave -noupdate -group {BURST ADDRESS} -divider Input +add wave -noupdate -group {BURST ADDRESS} -format Literal -radix unsigned /versatile_mem_ctrl_tb/dut/inc_adr0/adr_i +add wave -noupdate -group {BURST ADDRESS} -format Literal /versatile_mem_ctrl_tb/dut/inc_adr0/cti_i +add wave -noupdate -group {BURST ADDRESS} -format Literal /versatile_mem_ctrl_tb/dut/inc_adr0/bte_i +add wave -noupdate -group {BURST ADDRESS} -format Logic /versatile_mem_ctrl_tb/dut/inc_adr0/init +add wave -noupdate -group {BURST ADDRESS} -format Logic /versatile_mem_ctrl_tb/dut/inc_adr0/inc +add wave -noupdate -group {BURST ADDRESS} -divider Internal +add wave -noupdate -group {BURST ADDRESS} -format Logic /versatile_mem_ctrl_tb/dut/inc_adr0/init_i +add wave -noupdate -group {BURST ADDRESS} -format Literal /versatile_mem_ctrl_tb/dut/inc_adr0/bte +add wave -noupdate -group {BURST ADDRESS} -format Literal /versatile_mem_ctrl_tb/dut/inc_adr0/cnt +add wave -noupdate -group {BURST ADDRESS} -divider Output +add wave -noupdate -group {BURST ADDRESS} -format Literal /versatile_mem_ctrl_tb/dut/inc_adr0/adr_o +add wave -noupdate -group {BURST ADDRESS} -format Logic /versatile_mem_ctrl_tb/dut/inc_adr0/done +add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -divider {Micron DDR2 SDRAM} +add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Literal -radix ascii /versatile_mem_ctrl_tb/dut/ddr_16_0/statename +add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Logic /versatile_mem_ctrl_tb/ddr2_sdram/ck +add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Logic /versatile_mem_ctrl_tb/ddr2_sdram/ck_n +add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Logic /versatile_mem_ctrl_tb/ddr2_sdram/cke +add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Logic /versatile_mem_ctrl_tb/ddr2_sdram/cs_n +add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Logic /versatile_mem_ctrl_tb/ddr2_sdram/ras_n +add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Logic /versatile_mem_ctrl_tb/ddr2_sdram/cas_n +add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Logic /versatile_mem_ctrl_tb/ddr2_sdram/we_n +add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Literal /versatile_mem_ctrl_tb/ddr2_sdram/ba +add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/ddr2_sdram/addr +add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Logic /versatile_mem_ctrl_tb/ddr2_sdram/odt +add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Literal /versatile_mem_ctrl_tb/ddr2_sdram/dm_rdqs +add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/ddr2_sdram/dq +add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Literal /versatile_mem_ctrl_tb/ddr2_sdram/dqs +add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Literal /versatile_mem_ctrl_tb/ddr2_sdram/dqs_n +add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Literal /versatile_mem_ctrl_tb/ddr2_sdram/rdqs_n +add wave -noupdate -group {RX FIFO (Ingress FIFO)} -divider {Rx FIFO 0} +add wave -noupdate -group {RX FIFO (Ingress FIFO)} -group {Fifo Control} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/d +add wave -noupdate -group {RX FIFO (Ingress FIFO)} -group {Fifo Control} -format Logic /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/write +add wave -noupdate -group {RX FIFO (Ingress FIFO)} -group {Fifo Control} -format Literal /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/write_enable +add wave -noupdate -group {RX FIFO (Ingress FIFO)} -group {Fifo Control} -format Logic /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/clk1 +add wave -noupdate -group {RX FIFO (Ingress FIFO)} -group {Fifo Control} -format Logic /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/rst1 +add wave -noupdate -group {RX FIFO (Ingress FIFO)} -group {Fifo Control} -format Logic /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/read +add wave -noupdate -group {RX FIFO (Ingress FIFO)} -group {Fifo Control} -format Literal /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/read_enable +add wave -noupdate -group {RX FIFO (Ingress FIFO)} -group {Fifo Control} -format Logic /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/clk2 +add wave -noupdate -group {RX FIFO (Ingress FIFO)} -group {Fifo Control} -format Logic /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/rst2 +add wave -noupdate -group {RX FIFO (Ingress FIFO)} -group {Fifo Control} -format Literal /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/fifo_full +add wave -noupdate -group {RX FIFO (Ingress FIFO)} -group {Fifo Control} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/q +add wave -noupdate -group {RX FIFO (Ingress FIFO)} -group {Fifo Control} -format Literal /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/fifo_empty +add wave -noupdate -group {RX FIFO (Ingress FIFO)} -expand -group {Fifo 0 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[31]} +add wave -noupdate -group {RX FIFO (Ingress FIFO)} -expand -group {Fifo 0 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[30]} +add wave -noupdate -group {RX FIFO (Ingress FIFO)} -expand -group {Fifo 0 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[29]} +add wave -noupdate -group {RX FIFO (Ingress FIFO)} -expand -group {Fifo 0 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[28]} +add wave -noupdate -group {RX FIFO (Ingress FIFO)} -expand -group {Fifo 0 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[27]} +add wave -noupdate -group {RX FIFO (Ingress FIFO)} -expand -group {Fifo 0 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[26]} +add wave -noupdate -group {RX FIFO (Ingress FIFO)} -expand -group {Fifo 0 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[25]} +add wave -noupdate -group {RX FIFO (Ingress FIFO)} -expand -group {Fifo 0 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[24]} +add wave -noupdate -group {RX FIFO (Ingress FIFO)} -expand -group {Fifo 0 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[23]} +add wave -noupdate -group {RX FIFO (Ingress FIFO)} -expand -group {Fifo 0 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[22]} +add wave -noupdate -group {RX FIFO (Ingress FIFO)} -expand -group {Fifo 0 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[21]} +add wave -noupdate -group {RX FIFO (Ingress FIFO)} -expand -group {Fifo 0 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[20]} +add wave -noupdate -group {RX FIFO (Ingress FIFO)} -expand -group {Fifo 0 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[19]} +add wave -noupdate -group {RX FIFO (Ingress FIFO)} -expand -group {Fifo 0 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[18]} +add wave -noupdate -group {RX FIFO (Ingress FIFO)} -expand -group {Fifo 0 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[17]} +add wave -noupdate -group {RX FIFO (Ingress FIFO)} -expand -group {Fifo 0 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[16]} +add wave -noupdate -group {RX FIFO (Ingress FIFO)} -expand -group {Fifo 0 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[15]} +add wave -noupdate -group {RX FIFO (Ingress FIFO)} -expand -group {Fifo 0 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[14]} +add wave -noupdate -group {RX FIFO (Ingress FIFO)} -expand -group {Fifo 0 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[13]} +add wave -noupdate -group {RX FIFO (Ingress FIFO)} -expand -group {Fifo 0 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[12]} +add wave -noupdate -group {RX FIFO (Ingress FIFO)} -expand -group {Fifo 0 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[11]} +add wave -noupdate -group {RX FIFO (Ingress FIFO)} -expand -group {Fifo 0 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[10]} +add wave -noupdate -group {RX FIFO (Ingress FIFO)} -expand -group {Fifo 0 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[9]} +add wave -noupdate -group {RX FIFO (Ingress FIFO)} -expand -group {Fifo 0 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[8]} +add wave -noupdate -group {RX FIFO (Ingress FIFO)} -expand -group {Fifo 0 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[7]} +add wave -noupdate -group {RX FIFO (Ingress FIFO)} -expand -group {Fifo 0 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[6]} +add wave -noupdate -group {RX FIFO (Ingress FIFO)} -expand -group {Fifo 0 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[5]} +add wave -noupdate -group {RX FIFO (Ingress FIFO)} -expand -group {Fifo 0 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[4]} +add wave -noupdate -group {RX FIFO (Ingress FIFO)} -expand -group {Fifo 0 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[3]} +add wave -noupdate -group {RX FIFO (Ingress FIFO)} -expand -group {Fifo 0 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[2]} +add wave -noupdate -group {RX FIFO (Ingress FIFO)} -expand -group {Fifo 0 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[1]} +add wave -noupdate -group {RX FIFO (Ingress FIFO)} -expand -group {Fifo 0 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[0]} +add wave -noupdate -group {RX FIFO (Ingress FIFO)} -divider {Rx FIFO 1} +add wave -noupdate -group {BURST LENGTH} -format Logic /versatile_mem_ctrl_tb/dut/burst_length_counter0/rst +add wave -noupdate -group {BURST LENGTH} -format Logic /versatile_mem_ctrl_tb/dut/burst_length_counter0/clk +add wave -noupdate -group {BURST LENGTH} -format Logic /versatile_mem_ctrl_tb/dut/burst_length_counter0/cke +add wave -noupdate -group {BURST LENGTH} -format Literal /versatile_mem_ctrl_tb/dut/burst_length_counter0/length +add wave -noupdate -group {BURST LENGTH} -format Literal /versatile_mem_ctrl_tb/dut/burst_length_counter0/clear_value +add wave -noupdate -group {BURST LENGTH} -format Literal /versatile_mem_ctrl_tb/dut/burst_length_counter0/set_value +add wave -noupdate -group {BURST LENGTH} -format Literal /versatile_mem_ctrl_tb/dut/burst_length_counter0/wrap_value +add wave -noupdate -group {BURST LENGTH} -format Literal -radix unsigned /versatile_mem_ctrl_tb/dut/burst_length_counter0/qi +add wave -noupdate -group {BURST LENGTH} -format Literal -radix unsigned /versatile_mem_ctrl_tb/dut/burst_length_counter0/q_next +add wave -noupdate -group {BURST LENGTH} -format Logic /versatile_mem_ctrl_tb/dut/burst_length_counter0/zq +add wave -noupdate -group {DDR2 IF} -divider FSM +add wave -noupdate -group {DDR2 IF} -format Literal -radix ascii /versatile_mem_ctrl_tb/dut/ddr_16_0/statename +add wave -noupdate -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/sdram_clk_270 +add wave -noupdate -group {DDR2 IF} -divider {Controller side} +add wave -noupdate -group {DDR2 IF} -divider {Clock & reset} +add wave -noupdate -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/sdram_rst +add wave -noupdate -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/sdram_clk +add wave -noupdate -group {DDR2 IF} -divider {Tx Data} +add wave -noupdate -group {DDR2 IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/versatile_mem_ctrl_ddr_0/tx_dat_i +add wave -noupdate -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/versatile_mem_ctrl_ddr_0/dq_en +add wave -noupdate -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/versatile_mem_ctrl_ddr_0/dqm_en +add wave -noupdate -group {DDR2 IF} -divider {Rx Data} +add wave -noupdate -group {DDR2 IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/versatile_mem_ctrl_ddr_0/rx_dat_o +add wave -noupdate -group {DDR2 IF} -divider {SDRAM side} +add wave -noupdate -group {DDR2 IF} -divider Address +add wave -noupdate -group {DDR2 IF} -format Literal /versatile_mem_ctrl_tb/dut/ba_pad_o +add wave -noupdate -group {DDR2 IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/addr_pad_o +add wave -noupdate -group {DDR2 IF} -divider {Data & mask} +add wave -noupdate -group {DDR2 IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/dq_pad_io +add wave -noupdate -group {DDR2 IF} -format Literal /versatile_mem_ctrl_tb/dut/dm_rdqs_pad_io +add wave -noupdate -group {DDR2 IF} -divider {Clock & strobe} +add wave -noupdate -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/cke_pad_o +add wave -noupdate -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/ck_pad_o +add wave -noupdate -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/ck_n_pad_o +add wave -noupdate -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/ck_fb_pad_o +add wave -noupdate -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/ck_fb_pad_i +add wave -noupdate -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/dqs_oe +add wave -noupdate -group {DDR2 IF} -format Literal /versatile_mem_ctrl_tb/dut/dqs_pad_io +add wave -noupdate -group {DDR2 IF} -format Literal /versatile_mem_ctrl_tb/dut/dqs_n_pad_io +add wave -noupdate -group {DDR2 IF} -format Literal /versatile_mem_ctrl_tb/dut/rdqs_n_pad_i +add wave -noupdate -group {DDR2 IF} -divider Command +add wave -noupdate -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/cs_n_pad_o +add wave -noupdate -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/ras_pad_o +add wave -noupdate -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/cas_pad_o +add wave -noupdate -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/we_pad_o +add wave -noupdate -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/odt_pad_o +add wave -noupdate -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/versatile_mem_ctrl_ddr_0/dq_en +add wave -noupdate -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/versatile_mem_ctrl_ddr_0/dqm_en +add wave -noupdate -group {DDR2 IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/versatile_mem_ctrl_ddr_0/tx_dat_i +add wave -noupdate -group {OPEN BANKS & ROWS} -divider State +add wave -noupdate -group {OPEN BANKS & ROWS} -format Literal -radix ascii /versatile_mem_ctrl_tb/dut/ddr_16_0/statename +add wave -noupdate -group {OPEN BANKS & ROWS} -divider {Open bank & row} +add wave -noupdate -group {OPEN BANKS & ROWS} -format Literal /versatile_mem_ctrl_tb/dut/open_bank_i +add wave -noupdate -group {OPEN BANKS & ROWS} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/open_row_i +add wave -noupdate -group {OPEN BANKS & ROWS} -format Logic /versatile_mem_ctrl_tb/dut/open_cur_row +add wave -noupdate -group {OPEN BANKS & ROWS} -format Logic /versatile_mem_ctrl_tb/dut/close_cur_row +add wave -noupdate -group {OPEN BANKS & ROWS} -format Literal /versatile_mem_ctrl_tb/dut/open_row +add wave -noupdate -group {OPEN BANKS & ROWS} -format Literal /versatile_mem_ctrl_tb/dut/next_row +add wave -noupdate -group {OPEN BANKS & ROWS} -format Literal /versatile_mem_ctrl_tb/dut/next_row +add wave -noupdate -group {OPEN BANKS & ROWS} -format Literal /versatile_mem_ctrl_tb/dut/next_bank +add wave -noupdate -group {OPEN BANKS & ROWS} -format Logic /versatile_mem_ctrl_tb/dut/next_row_open +add wave -noupdate -group {FIFO Pointers & Flags} -divider FIFO_0_1 +add wave -noupdate -group {FIFO Pointers & Flags} -divider FIFO_0_0 +add wave -noupdate -group {FIFO Pointers & Flags} -format Literal -radix unsigned {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/fifo_adr[0]/egresscmp/wptr_bin} +add wave -noupdate -group {FIFO Pointers & Flags} -format Literal -radix unsigned {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/fifo_adr[0]/egresscmp/rptr_bin} +add wave -noupdate -group {FIFO Pointers & Flags} -format Literal -radix unsigned {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/fifo_adr[0]/egresscmp/ptr_diff} +add wave -noupdate -group {FIFO Pointers & Flags} -format Logic {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/fifo_adr[0]/egresscmp/fifo_empty} +add wave -noupdate -group {FIFO Pointers & Flags} -format Logic {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/fifo_adr[0]/egresscmp/fifo_full} +add wave -noupdate -group {FIFO Pointers & Flags} -format Logic {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/fifo_adr[0]/egresscmp/fifo_flag} +add wave -noupdate -group {FIFO Pointers & Flags} -divider FIFO_1_1 +add wave -noupdate -group {FIFO Pointers & Flags} -divider FIFO_1_0 +add wave -noupdate -group {FIFO Pointers & Flags} -format Literal -radix unsigned {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/fifo_adr[0]/egresscmp/wptr_bin} +add wave -noupdate -group {FIFO Pointers & Flags} -format Literal -radix unsigned {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/fifo_adr[0]/egresscmp/rptr_bin} +add wave -noupdate -group {FIFO Pointers & Flags} -format Literal -radix unsigned {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/fifo_adr[0]/egresscmp/ptr_diff} +add wave -noupdate -group {FIFO Pointers & Flags} -format Logic {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/fifo_adr[0]/egresscmp/fifo_empty} +add wave -noupdate -group {FIFO Pointers & Flags} -format Logic {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/fifo_adr[0]/egresscmp/fifo_full} +add wave -noupdate -group {FIFO Pointers & Flags} -format Logic {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/fifo_adr[0]/egresscmp/fifo_flag} +add wave -noupdate -group {FIFO Pointers & Flags} -divider {FIFO Flags on top-level} +add wave -noupdate -group {FIFO Pointers & Flags} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/fifo_empty +add wave -noupdate -group {FIFO Pointers & Flags} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/fifo_flag +add wave -noupdate -group {FIFO Pointers & Flags} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/versatile_mem_ctrl_ddr_0/dq_rx +add wave -noupdate -divider tmp +add wave -noupdate -format Logic /versatile_mem_ctrl_tb/dut/ck_pad_o +add wave -noupdate -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/dq_pad_io +add wave -noupdate -format Logic /versatile_mem_ctrl_tb/dut/sdram_clk_270 +add wave -noupdate -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/versatile_mem_ctrl_ddr_0/dq_rx +add wave -noupdate -format Logic /versatile_mem_ctrl_tb/dut/sdram_clk_180 +add wave -noupdate -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/versatile_mem_ctrl_ddr_0/dq_rx_reg +add wave -noupdate -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/fifo_dat_i +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {222981669 ps} 0} +configure wave -namecolwidth 441 +configure wave -valuecolwidth 151 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {0 ps} {346500 ns} Index: versatile_mem_ctrl/tags/Rev2/sim/rtl_sim/bin/sim_altera.tcl =================================================================== --- versatile_mem_ctrl/tags/Rev2/sim/rtl_sim/bin/sim_altera.tcl (nonexistent) +++ versatile_mem_ctrl/tags/Rev2/sim/rtl_sim/bin/sim_altera.tcl (revision 109) @@ -0,0 +1,67 @@ +# Usage: +# cd /versatile_mem_ctrl/trunk/sim/rtl_sim/run/ +# vsim -gui -do ../bin/sim_altera.tcl + +set DESIGN_NAME "versatile_memory_controller" +set WAVE_FILE ../bin/wave_ddr.do +set FORCE_LIBRARY_RECOMPILE 0 + +# Quit simulation if you are running one +quit -sim + +# Create and open project +if {[file exists ${DESIGN_NAME}_sim_altera.mpf]} { +project open ${DESIGN_NAME}_sim_altera +} else { +project new . ${DESIGN_NAME}_sim_altera +} + +# Compile Altera libraries +if {![file exists altera_primitives] || $FORCE_LIBRARY_RECOMPILE} { +vlib altera_primitives +vmap altera_primitives altera_primitives +#vlog -work altera_primitives /opt/altera9.1/quartus/eda/sim_lib/altera_primitives.v +vcom -work altera_primitives /opt/altera9.1/quartus/eda/sim_lib/altera_primitives_components.vhd +vcom -work altera_primitives /opt/altera9.1/quartus/eda/sim_lib/altera_primitives.vhd +} +if {![file exists altera_mf] || $FORCE_LIBRARY_RECOMPILE} { +vlib altera_mf +vmap altera_mf altera_mf +#vlog -work altera_mf /opt/altera9.1/quartus/eda/sim_lib/altera_mf.v +vcom -work altera_mf /opt/altera9.1/quartus/eda/sim_lib/altera_mf_components.vhd +vcom -work altera_mf /opt/altera9.1/quartus/eda/sim_lib/altera_mf.vhd +} +if {![file exists lpm] || $FORCE_LIBRARY_RECOMPILE} { +vlib lpm +vmap lpm lpm +vlog -work lpm /opt/altera9.1/quartus/eda/sim_lib/220model.v +} + +# Compile project source code +vlog ../../../rtl/verilog/versatile_mem_ctrl_ip.v +incdir+../../../rtl/verilog/ + +# Compile test bench source code +vlog ../../../bench/ddr/ddr2.v +incdir+../../../bench/ddr/ +vlog ../../../bench/wb0_ddr.v ../../../bench/wb1_ddr.v ../../../bench/wb4_ddr.v +define+x16 ../../../bench/tb_top.v +incdir+../../../bench/ + +# Quit without asking +set PrefMain(forceQuit) 1 + +# Invoke the simulator +# -gui Open the GUI without loading a design +# -novopt Force incremental mode (pre-6.0 behavior) +# -L Search library for design units instantiated from Verilog and for VHDL default component binding +vsim -gui -novopt -L altera_mf -L lpm work.versatile_mem_ctrl_tb + +# Open waveform viewer +view wave -title "${DESIGN_NAME}" + +# Open signal viewer +view signals + +# Run the .do file to load signals to the waveform viewer +do $WAVE_FILE + +# Run the simulation +run 330 us + Index: versatile_mem_ctrl/tags/Rev2/sim/rtl_sim/bin/sim_xilinx.tcl =================================================================== --- versatile_mem_ctrl/tags/Rev2/sim/rtl_sim/bin/sim_xilinx.tcl (nonexistent) +++ versatile_mem_ctrl/tags/Rev2/sim/rtl_sim/bin/sim_xilinx.tcl (revision 109) @@ -0,0 +1,66 @@ +# Usage: +# cd /versatile_mem_ctrl/trunk/sim/rtl_sim/run/ +# vsim -gui -do ../bin/sim_xilinx.tcl + +set DESIGN_NAME "versatile_memory_controller" +set WAVE_FILE wave_ddr.do +set FORCE_LIBRARY_RECOMPILE 0 + +# Quit simulation if you are running one +quit -sim + +# Create and open project +if {[file exists ${DESIGN_NAME}_sim_xilinx.mpf]} { +project open ${DESIGN_NAME}_sim_xilinx +} else { +project new . ${DESIGN_NAME}_sim_xilinx +} + +# Compile Xilinx libraries +if {![file exists unisims_ver] || $FORCE_LIBRARY_RECOMPILE} { +vlib unisims_ver +vmap unisims_ver unisims_ver +vlog -work unisims_ver /opt/Xilinx/11.1/ISE/verilog/src/unisims/*.v +} +if {![file exists simprims_ver] || $FORCE_LIBRARY_RECOMPILE} { +vlib simprims_ver +vmap simprims_ver simprims_ver +vlog -work simprims_ver /opt/Xilinx/11.1/ISE/verilog/src/simprims/*.v +} +if {![file exists xilinxcorelib_ver] || $FORCE_LIBRARY_RECOMPILE} { +vlib xilinxcorelib_ver +vmap xilinxcorelib_ver xilinxcorelib_ver +vlog -work xilinxcorelib_ver /opt/Xilinx/11.1/ISE/verilog/src/XilinxCoreLib/*.v +} + +# Compile the glbl.v module +vlog /opt/Xilinx/11.1/ISE/verilog/src/glbl.v + +# Compile project source code +vlog ../../../rtl/verilog/versatile_mem_ctrl_ip.v +incdir+../../../rtl/verilog/ + +# Compile test bench source code +vlog ../../../bench/ddr/ddr2.v +incdir+../../../bench/ddr/ +vlog ../../../bench/wb0_ddr.v ../../../bench/wb1_ddr.v ../../../bench/wb4_ddr.v +define+x16 ../../../bench/tb_top.v +incdir+../../../bench/ + +# Quit without asking +set PrefMain(forceQuit) 1 + +# Invoke the simulator +# -gui Open the GUI without loading a design +# -novopt Force incremental mode (pre-6.0 behavior) +# -L Search library for design units instantiated from Verilog and for VHDL default component binding +vsim -gui -novopt -L unisims_ver -L xilinxcorelib_ver work.versatile_mem_ctrl_tb work.glbl + +# Open waveform viewer +view wave -title "${DESIGN_NAME}" + +# Open signal viewer +view signals + +# Run the .do file to load signals to the waveform viewer +do $WAVE_FILE + +# Run the simulation +run 330 us + Index: versatile_mem_ctrl/tags/Rev2/syn/altera/bin/versatile_memory_controller.sdc =================================================================== --- versatile_mem_ctrl/tags/Rev2/syn/altera/bin/versatile_memory_controller.sdc (nonexistent) +++ versatile_mem_ctrl/tags/Rev2/syn/altera/bin/versatile_memory_controller.sdc (revision 109) @@ -0,0 +1,248 @@ +#************************************************************** +# Timimg Information for DDR2 SDRAM +#************************************************************** +# Timing specifications from Micron Data Sheet (DDR2 SDRAM MT47H32M16-5E) + +# Clock cycle time: min=5.00ns, max=8.00ns +set tCK 8.000 + +# Data Strobe Out +# DQS output access time from CK/CK# +set tDQSCKmin -0.500 +set tDQSCKmax 0.500 + +# Data Strobe In +# DQS rising edge to CK rising edge +set tDQSSmin [expr -0.25 * $tCK] +set tDQSSmax [expr 0.25 * $tCK] +# DQS falling to CK rising: setup time +set tDSSmin [expr 0.2 * $tCK] +# DQS falling from CK rising: hold time +set tDSHmin [expr 0.2 * $tCK] + +# Data Out +# DQ output access time from CK/CK# +set tACmin -0.600 +set tACmax 0.600 + +# Data In +# DQ and DM input setup time to DQS +set tDSb 0.150 +# DQ and DM input hold time to DQS +set tDHb 0.275 +# DQ and DM input setup time to DQS +set tDSa 0.400 +# DQ and DM input hold time to DQS +set tDHa 0.400 + +# Command and Address +# Input setup time +set tISb 0.350 +set tISa 0.600 +# Input hold time +set tIHb 0.470 +set tIHa 0.600 + + +#************************************************************** +# Timimg Information +#************************************************************** + +# Trace delay for data +set tTDDmin 0.100 +set tTDDmax 0.200 + +# Trace delay for clock +set tTDCmin 0.100 +set tTDCmax 0.200 + + +#************************************************************** +# Create Clock +#************************************************************** + +# Clock frequency +set wb_clk_period 20.000 +set sdram_clk_period $tCK + +# Clocks +create_clock -name {wb_clk[*]} -period $wb_clk_period [get_ports {wb_clk[*]}] +create_clock -name {sdram_clk} -period $sdram_clk_period [get_ports {sdram_clk}] + +# Virtual clocks +#create_clock -name {v_wb_clk_in} -period $wb_clk_period +#create_clock -name {v_wb_clk_out} -period $wb_clk_period +#create_clock -name {v_sdram_clk_in} -period $sdram_clk_period +#create_clock -name {v_sdram_clk_out} -period $sdram_clk_period + + +#************************************************************** +# Create Generated Clock +#************************************************************** + +create_generated_clock -name sdram_clk_0 -phase 0 -source [get_ports {sdram_clk}] [get_pins {dcm_pll_0|altpll_internal|auto_generated|pll1|clk[0]}] +create_generated_clock -name sdram_clk_180 -phase 180 -source [get_ports {sdram_clk}] [get_pins {dcm_pll_0|altpll_internal|auto_generated|pll1|clk[2]}] +create_generated_clock -name sdram_clk_270 -phase 270 -source [get_ports {sdram_clk}] [get_pins {dcm_pll_0|altpll_internal|auto_generated|pll1|clk[3]}] +create_generated_clock -name ck_pad_o -phase 0 -source [get_pins {versatile_mem_ctrl_ddr_0|ddr_ff_out_ck|altddio_out_inst|auto_generated|ddio_outa[0]|clkhi}] [get_ports {ck_pad_o}] + +#************************************************************** +# Set Clock Latency +#************************************************************** + + + +#************************************************************** +# Set Clock Uncertainty +#************************************************************** + +derive_clock_uncertainty + + +#************************************************************** +# Set Input Delay +#************************************************************** +# Double Data Rate requires constraints for both rising and falling clock edge +# Input max delay value = max trace delay for data + tCO of external device – min trace delay for clock +# Input min delay value = min trace delay for data + tCOmin of external device – max trace delay for clock +# Assume (for now): max trace delay for data = min trace delay for clock +# min trace delay for data = max trace delay for clock +# Data +set_input_delay -clock {ck_pad_o} -max $tACmax [get_ports {dq_pad_io[*]}] -add_delay +set_input_delay -clock {ck_pad_o} -max $tACmax -clock_fall [get_ports {dq_pad_io[*]}] -add_delay +set_input_delay -clock {ck_pad_o} -min $tACmin [get_ports {dq_pad_io[*]}] -add_delay +set_input_delay -clock {ck_pad_o} -min $tACmin -clock_fall [get_ports {dq_pad_io[*]}] -add_delay +# Data Strobe +set_input_delay -clock {ck_pad_o} -max $tDQSCKmax [get_ports {dqs_pad_io[*]}] -add_delay +set_input_delay -clock {ck_pad_o} -max $tDQSCKmax -clock_fall [get_ports {dqs_pad_io[*]}] -add_delay +set_input_delay -clock {ck_pad_o} -min $tDQSCKmin [get_ports {dqs_pad_io[*]}] -add_delay +set_input_delay -clock {ck_pad_o} -min $tDQSCKmin -clock_fall [get_ports {dqs_pad_io[*]}] -add_delay +# Data Strobe +set_input_delay -clock {ck_pad_o} -max $tDQSCKmax [get_ports {dqs_n_pad_io[*]}] -add_delay +set_input_delay -clock {ck_pad_o} -max $tDQSCKmax -clock_fall [get_ports {dqs_n_pad_io[*]}] -add_delay +set_input_delay -clock {ck_pad_o} -min $tDQSCKmin [get_ports {dqs_n_pad_io[*]}] -add_delay +set_input_delay -clock {ck_pad_o} -min $tDQSCKmin -clock_fall [get_ports {dqs_n_pad_io[*]}] -add_delay +# Data Mask +set_input_delay -clock {ck_pad_o} -max $tDQSCKmax [get_ports {dm_rdqs_pad_io[*]}] -add_delay +set_input_delay -clock {ck_pad_o} -max $tDQSCKmax -clock_fall [get_ports {dm_rdqs_pad_io[*]}] -add_delay +set_input_delay -clock {ck_pad_o} -min $tDQSCKmin [get_ports {dm_rdqs_pad_io[*]}] -add_delay +set_input_delay -clock {ck_pad_o} -min $tDQSCKmin -clock_fall [get_ports {dm_rdqs_pad_io[*]}] -add_delay + +# Single Data Rate requires constraints for rising clock edge only + + +#************************************************************** +# Set Output Delay +#************************************************************** +# Double Data Rate requires constraints for both rising and falling clock edge +# Output max delay = max trace delay for data + tSU of external register – min trace delay for clock +# Output min delay = min trace delay for data – tH of external register – max trace delay for clock +# Assume (for now): max trace delay for data = min trace delay for clock +# min trace delay for data = max trace delay for clock +# Data +set_output_delay -clock {ck_pad_o} -max $tISa [get_ports {dq_pad_io[*]}] -add_delay +set_output_delay -clock {ck_pad_o} -max $tISa -clock_fall [get_ports {dq_pad_io[*]}] -add_delay +set_output_delay -clock {ck_pad_o} -min -$tIHa [get_ports {dq_pad_io[*]}] -add_delay +set_output_delay -clock {ck_pad_o} -min -$tIHa -clock_fall [get_ports {dq_pad_io[*]}] -add_delay +# Data Strobe +set_output_delay -clock {ck_pad_o} -max $tISa [get_ports {dqs_pad_io[*]}] -add_delay +set_output_delay -clock {ck_pad_o} -max $tISa -clock_fall [get_ports {dqs_pad_io[*]}] -add_delay +set_output_delay -clock {ck_pad_o} -min -$tIHa [get_ports {dqs_pad_io[*]}] -add_delay +set_output_delay -clock {ck_pad_o} -min -$tIHa -clock_fall [get_ports {dqs_pad_io[*]}] -add_delay +# Data Strobe +set_output_delay -clock {ck_pad_o} -max $tISa [get_ports {dqs_n_pad_io[*]}] -add_delay +set_output_delay -clock {ck_pad_o} -max $tISa -clock_fall [get_ports {dqs_n_pad_io[*]}] -add_delay +set_output_delay -clock {ck_pad_o} -min -$tIHa [get_ports {dqs_n_pad_io[*]}] -add_delay +set_output_delay -clock {ck_pad_o} -min -$tIHa -clock_fall [get_ports {dqs_n_pad_io[*]}] -add_delay +# Data Mask +set_output_delay -clock {ck_pad_o} -max $tISa [get_ports {dm_rdqs_pad_io[*]}] -add_delay +set_output_delay -clock {ck_pad_o} -max $tISa -clock_fall [get_ports {dm_rdqs_pad_io[*]}] -add_delay +set_output_delay -clock {ck_pad_o} -min -$tIHa [get_ports {dm_rdqs_pad_io[*]}] -add_delay +set_output_delay -clock {ck_pad_o} -min -$tIHa -clock_fall [get_ports {dm_rdqs_pad_io[*]}] -add_delay + +# Single Data Rate requires constraints for rising clock edge only +# Chip Select +set_output_delay -clock {ck_pad_o} -max $tISa [get_ports {cs_n_pad_o}] -add_delay +set_output_delay -clock {ck_pad_o} -min -$tIHa [get_ports {cs_n_pad_o}] -add_delay +# Row Address Strobe +set_output_delay -clock {ck_pad_o} -max $tISa [get_ports {ras_pad_o}] -add_delay +set_output_delay -clock {ck_pad_o} -min -$tIHa [get_ports {ras_pad_o}] -add_delay +# Column Address Strobe +set_output_delay -clock {ck_pad_o} -max $tISa [get_ports {cas_pad_o}] -add_delay +set_output_delay -clock {ck_pad_o} -min -$tIHa [get_ports {cas_pad_o}] -add_delay +# Write Enable +set_output_delay -clock {ck_pad_o} -max $tISa [get_ports {we_pad_o}] -add_delay +set_output_delay -clock {ck_pad_o} -min -$tIHa [get_ports {we_pad_o}] -add_delay +# Bank Address +set_output_delay -clock {ck_pad_o} -max $tISa [get_ports {ba_pad_o[*]}] -add_delay +set_output_delay -clock {ck_pad_o} -min -$tIHa [get_ports {ba_pad_o[*]}] -add_delay +# Address +set_output_delay -clock {ck_pad_o} -max $tISa [get_ports {addr_pad_o[*]}] -add_delay +set_output_delay -clock {ck_pad_o} -min -$tIHa [get_ports {addr_pad_o[*]}] -add_delay +# Clock Enable +set_output_delay -clock {ck_pad_o} -max $tISa [get_ports {cke_pad_o}] -add_delay +set_output_delay -clock {ck_pad_o} -min -$tIHa [get_ports {cke_pad_o}] -add_delay + + +#************************************************************** +# Set Clock Groups +#************************************************************** + + + +#************************************************************** +# Set False Path +#************************************************************** + +# Reset +set_false_path -from [get_ports {wb_rst[*]}] + +# Input Timing Exceptions +# False path exceptions for opposite-edge transfer +# Data +set_false_path -setup -fall_from [get_clocks ck_pad_o] -fall_to [get_clocks sdram_clk_270] +set_false_path -setup -rise_from [get_clocks ck_pad_o] -rise_to [get_clocks sdram_clk_270] +set_false_path -hold -rise_from [get_clocks ck_pad_o] -rise_to [get_clocks sdram_clk_270] +set_false_path -hold -fall_from [get_clocks ck_pad_o] -fall_to [get_clocks sdram_clk_270] +# Data Strobe +#set_false_path -setup -fall_from [get_clocks ck_pad_o] -fall_to [get_clocks sdram_clk_0] +#set_false_path -setup -rise_from [get_clocks ck_pad_o] -rise_to [get_clocks sdram_clk_0] +#set_false_path -hold -rise_from [get_clocks ck_pad_o] -rise_to [get_clocks sdram_clk_0] +#set_false_path -hold -fall_from [get_clocks ck_pad_o] -fall_to [get_clocks sdram_clk_0] + +# Output Timing Exceptions +# False path exceptions for opposite-edge transfer +# Data +set_false_path -setup -rise_from [get_clocks sdram_clk_270] -fall_to [get_clocks ck_pad_o] +set_false_path -setup -fall_from [get_clocks sdram_clk_270] -rise_to [get_clocks ck_pad_o] +set_false_path -hold -rise_from [get_clocks sdram_clk_270] -rise_to [get_clocks ck_pad_o] +set_false_path -hold -fall_from [get_clocks sdram_clk_270] -fall_to [get_clocks ck_pad_o] +# Data Strobe +set_false_path -setup -rise_from [get_clocks sdram_clk_0] -fall_to [get_clocks ck_pad_o] +set_false_path -setup -fall_from [get_clocks sdram_clk_0] -rise_to [get_clocks ck_pad_o] +set_false_path -hold -rise_from [get_clocks sdram_clk_0] -rise_to [get_clocks ck_pad_o] +set_false_path -hold -fall_from [get_clocks sdram_clk_0] -fall_to [get_clocks ck_pad_o] + + +#************************************************************** +# Set Multicycle Path +#************************************************************** + + + +#************************************************************** +# Set Maximum Delay +#************************************************************** + + + +#************************************************************** +# Set Minimum Delay +#************************************************************** + + + +#************************************************************** +# Set Input Transition +#************************************************************** + + Index: versatile_mem_ctrl/tags/Rev2/syn/altera/bin/versatile_memory_controller.tcl =================================================================== --- versatile_mem_ctrl/tags/Rev2/syn/altera/bin/versatile_memory_controller.tcl (nonexistent) +++ versatile_mem_ctrl/tags/Rev2/syn/altera/bin/versatile_memory_controller.tcl (revision 109) @@ -0,0 +1,67 @@ +# Usage: +# cd /versatile_mem_ctrl/trunk/syn/altera/run/ +# quartus_sh -t ../bin/versatile_memory_controller.tcl + +# Load Quartus II Tcl Project package +package require ::quartus::project + +# Add the next line to get the execute_flow command +package require ::quartus::flow + +set need_to_close_project 0 +set make_assignments 1 + +# Check that the right project is open +if {[is_project_open]} { + if {[string compare $quartus(project) "versatile_memory_controller"]} { + puts "Project versatile_memory_controller is not open" + set make_assignments 0 + } +} else { + # Only open if not already open + if {[project_exists versatile_memory_controller]} { + project_open -revision versatile_mem_ctrl_top versatile_memory_controller + } else { + project_new -revision versatile_mem_ctrl_top versatile_memory_controller + } + set need_to_close_project 1 +} + +# Make assignments +if {$make_assignments} { + set_global_assignment -name FAMILY "Stratix III" + set_global_assignment -name DEVICE AUTO + set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.0 SP2" + set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:18:52 DECEMBER 14, 2009" + set_global_assignment -name LAST_QUARTUS_VERSION "9.0 SP2" + set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga + set_global_assignment -name SEARCH_PATH core_prbs/rtl/ + set_global_assignment -name SEARCH_PATH core_prbs/ + set_global_assignment -name SEARCH_PATH NPU1C_XCVR_reconfig/ + set_global_assignment -name SEARCH_PATH Bacchus_PTP_ALTLVDS_DYN_LINERATE_MULTICHANNEL/ + set_global_assignment -name SEARCH_PATH Bacchus_PTP_ALTLVDS_DYN_LINERATE_MULTICHANNEL/rate_match_fifo/ + set_global_assignment -name SEARCH_PATH Bacchus_PTP_ALTLVDS_DYN_LINERATE_MULTICHANNEL/tx_phase_comp_fifo/ + set_global_assignment -name SEARCH_PATH altera/90/ip/altera/sopc_builder_ip/altera_avalon_clock_adapter/ + set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top + set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" + set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" + set_global_assignment -name MISC_FILE /home/mikael/opencores/versatile_mem_ctrl/trunk/syn/altera/run/versatile_mem_ctrl_top.dpf + set_global_assignment -name SDC_FILE ../bin/versatile_memory_controller.sdc + set_global_assignment -name VERILOG_FILE ../../../rtl/verilog/versatile_mem_ctrl_ip.v + set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY /home/mikael/opencores/versatile_mem_ctrl/trunk/syn/altera/run -section_id eda_simulation + set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (Verilog)" + set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top + + # Commit assignments + export_assignments + + # Compile + execute_flow -compile + + + # Close project + if {$need_to_close_project} { + project_close + } +} Index: versatile_mem_ctrl/tags/Rev2/syn/xilinx/bin/versatile_memory_controller.ucf =================================================================== --- versatile_mem_ctrl/tags/Rev2/syn/xilinx/bin/versatile_memory_controller.ucf (nonexistent) +++ versatile_mem_ctrl/tags/Rev2/syn/xilinx/bin/versatile_memory_controller.ucf (revision 109) @@ -0,0 +1,122 @@ +#************************************************************** +# System Level Constraints +#************************************************************** +NET sdram_clk LOC = "F13" | IOSTANDARD = LVCMOS33; +NET wb_clk LOC = "K14" | IOSTANDARD = LVCMOS33; +NET wb_rst LOC = "Y16" | IOSTANDARD = LVTTL; +NET wb_rst TIG; + +#************************************************************** +# Timing Constraints +#************************************************************** + +#************************************************************** +# Clocks +#************************************************************** +NET "sdram_clk" TNM_NET = sdram_clk; +TIMESPEC TS_sdram_clk = PERIOD "sdram_clk" 8 ns HIGH 50%; # 125 MHz +NET "wb_clk" TNM_NET = wb_clk; +TIMESPEC TS_wb_clk = PERIOD "wb_clk" 40 ns HIGH 50%; # 25 MHz + +# External feedback to DCM +NET "ck_fb_pad_i" FEEDBACK = 2 ns NET "ck_fb_pad_o"; + +# +NET "wb_clk" CLOCK_DEDICATED_ROUTE = FALSE; +NET "sdram_clk" CLOCK_DEDICATED_ROUTE = FALSE; +PIN "dcm_pll_0/DCM_external/DCM_SP.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE; + +#************************************************************** +# DDR2 IF +#************************************************************** +# Data +#NET dq_pad_io<31> LOC="U9" | IOSTANDARD = SSTL18_II | IOB = TRUE | FAST; +#NET dq_pad_io<30> LOC="V8" | IOSTANDARD = SSTL18_II | IOB = TRUE | FAST; +#NET dq_pad_io<29> LOC="AB1" | IOSTANDARD = SSTL18_II | IOB = TRUE | FAST; +#NET dq_pad_io<28> LOC="AC1" | IOSTANDARD = SSTL18_II | IOB = TRUE | FAST; +#NET dq_pad_io<27> LOC="Y5" | IOSTANDARD = SSTL18_II | IOB = TRUE | FAST; +#NET dq_pad_io<26> LOC="Y6" | IOSTANDARD = SSTL18_II | IOB = TRUE | FAST; +#NET dq_pad_io<25> LOC="U7" | IOSTANDARD = SSTL18_II | IOB = TRUE | FAST; +#NET dq_pad_io<24> LOC="U8" | IOSTANDARD = SSTL18_II | IOB = TRUE | FAST; +#NET dq_pad_io<23> LOC="AA2" | IOSTANDARD = SSTL18_II | IOB = TRUE | FAST; +#NET dq_pad_io<22> LOC="AA3" | IOSTANDARD = SSTL18_II | IOB = TRUE | FAST; +#NET dq_pad_io<21> LOC="Y1" | IOSTANDARD = SSTL18_II | IOB = TRUE | FAST; +#NET dq_pad_io<20> LOC="Y2" | IOSTANDARD = SSTL18_II | IOB = TRUE | FAST; +#NET dq_pad_io<19> LOC="T7" | IOSTANDARD = SSTL18_II | IOB = TRUE | FAST; +#NET dq_pad_io<18> LOC="U6" | IOSTANDARD = SSTL18_II | IOB = TRUE | FAST; +#NET dq_pad_io<17> LOC="U5" | IOSTANDARD = SSTL18_II | IOB = TRUE | FAST; +#NET dq_pad_io<16> LOC="V5" | IOSTANDARD = SSTL18_II | IOB = TRUE | FAST; +NET dq_pad_io<15> LOC="R8" |IOSTANDARD = SSTL18_II |IOB = TRUE |FAST; +NET dq_pad_io<14> LOC="R7" |IOSTANDARD = SSTL18_II |IOB = TRUE |FAST; +NET dq_pad_io<13> LOC="U1" |IOSTANDARD = SSTL18_II |IOB = TRUE |FAST; +NET dq_pad_io<12> LOC="U2" |IOSTANDARD = SSTL18_II |IOB = TRUE |FAST; +NET dq_pad_io<11> LOC="P8" |IOSTANDARD = SSTL18_II |IOB = TRUE |FAST; +NET dq_pad_io<10> LOC="P9" |IOSTANDARD = SSTL18_II |IOB = TRUE |FAST; +NET dq_pad_io<9> LOC="R5" |IOSTANDARD = SSTL18_II |IOB = TRUE |FAST; +NET dq_pad_io<8> LOC="R6" |IOSTANDARD = SSTL18_II |IOB = TRUE |FAST; +NET dq_pad_io<7> LOC="P7" |IOSTANDARD = SSTL18_II |IOB = TRUE |FAST; +NET dq_pad_io<6> LOC="P6" |IOSTANDARD = SSTL18_II |IOB = TRUE |FAST; +NET dq_pad_io<5> LOC="T3" |IOSTANDARD = SSTL18_II |IOB = TRUE |FAST; +NET dq_pad_io<4> LOC="T4" |IOSTANDARD = SSTL18_II |IOB = TRUE |FAST; +NET dq_pad_io<3> LOC="N9" |IOSTANDARD = SSTL18_II |IOB = TRUE |FAST; +NET dq_pad_io<2> LOC="P10" |IOSTANDARD = SSTL18_II |IOB = TRUE |FAST; +NET dq_pad_io<1> LOC="P4" |IOSTANDARD = SSTL18_II |IOB = TRUE |FAST; +NET dq_pad_io<0> LOC="P3" |IOSTANDARD = SSTL18_II |IOB = TRUE |FAST; +# Address +NET addr_pad_o<0> LOC="M4" |IOSTANDARD = SSTL18_I |IOB = TRUE; +NET addr_pad_o<1> LOC="M3" |IOSTANDARD = SSTL18_I |IOB = TRUE; +NET addr_pad_o<2> LOC="M8" |IOSTANDARD = SSTL18_I |IOB = TRUE; +NET addr_pad_o<3> LOC="M7" |IOSTANDARD = SSTL18_I |IOB = TRUE; +NET addr_pad_o<4> LOC="L4" |IOSTANDARD = SSTL18_I |IOB = TRUE; +NET addr_pad_o<5> LOC="L3" |IOSTANDARD = SSTL18_I |IOB = TRUE; +NET addr_pad_o<6> LOC="K3" |IOSTANDARD = SSTL18_I |IOB = TRUE; +NET addr_pad_o<7> LOC="K2" |IOSTANDARD = SSTL18_I |IOB = TRUE; +NET addr_pad_o<8> LOC="K5" |IOSTANDARD = SSTL18_I |IOB = TRUE; +NET addr_pad_o<9> LOC="K4" |IOSTANDARD = SSTL18_I |IOB = TRUE; +NET addr_pad_o<10> LOC="M10" |IOSTANDARD = SSTL18_I |IOB = TRUE; +NET addr_pad_o<11> LOC="M9" |IOSTANDARD = SSTL18_I |IOB = TRUE; +NET addr_pad_o<12> LOC="J5" |IOSTANDARD = SSTL18_I |IOB = TRUE; +# Bank address +NET ba_pad_o<0> LOC="J4" |IOSTANDARD = SSTL18_I |IOB = TRUE; +NET ba_pad_o<1> LOC="K6" |IOSTANDARD = SSTL18_I |IOB = TRUE; +# Control +NET cas_pad_o LOC="L10" |IOSTANDARD = SSTL18_I |IOB = TRUE; +NET cke_pad_o LOC="L7" |IOSTANDARD = SSTL18_I |IOB = TRUE; +NET cs_n_pad_o LOC="H2" |IOSTANDARD = SSTL18_I |IOB = TRUE; +NET ras_pad_o LOC="H1" |IOSTANDARD = SSTL18_I |IOB = TRUE; +NET we_pad_o LOC="L9" |IOSTANDARD = SSTL18_I |IOB = TRUE; +# Data mask +NET dm_rdqs_pad_io<0> LOC="M6" |IOSTANDARD = SSTL18_II |IOB = TRUE; +NET dm_rdqs_pad_io<1> LOC="R2" |IOSTANDARD = SSTL18_II |IOB = TRUE; +#NET dm_rdqs_pad_io<2> LOC="V1" | IOSTANDARD = SSTL18_II | IOB = TRUE; +#NET dm_rdqs_pad_io<3> LOC="V2" | IOSTANDARD = SSTL18_II | IOB = TRUE; +# Strobe +NET dqs_pad_io<0> LOC="R3" |IOSTANDARD = SSTL18_II |IOB = TRUE |FAST; +NET dqs_pad_io<1> LOC="T5" |IOSTANDARD = SSTL18_II |IOB = TRUE |FAST; +#NET dqs_pad_io<2> LOC="W3" | IOSTANDARD = SSTL18_II | IOB = TRUE | FAST; +#NET dqs_pad_io<3> LOC="V7" | IOSTANDARD = SSTL18_II | IOB = TRUE | FAST; +# Clocks +NET ck_pad_o LOC="N5" |IOSTANDARD = SSTL18_I |IOB = TRUE; +NET ck_n_pad_o LOC="N4" |IOSTANDARD = SSTL18_I |IOB = TRUE; +#NET ck_pad_o<1> LOC="N1" | IOSTANDARD = SSTL18_I | IOB = TRUE; +#NET ck_n_pad_o<1> LOC="N2" | IOSTANDARD = SSTL18_I | IOB = TRUE; +NET ck_fb_pad_o LOC="M2" |IOSTANDARD = LVCMOS18 |IOB = TRUE; +NET ck_fb_pad_i LOC="N7" |IOSTANDARD = LVCMOS18 |IOB = TRUE; +# +INST "dq_pad_io<0>" TNM = TNM_dq_in; +INST "dq_pad_io<1>" TNM = TNM_dq_in; +INST "dq_pad_io<2>" TNM = TNM_dq_in; +INST "dq_pad_io<3>" TNM = TNM_dq_in; +INST "dq_pad_io<4>" TNM = TNM_dq_in; +INST "dq_pad_io<5>" TNM = TNM_dq_in; +INST "dq_pad_io<6>" TNM = TNM_dq_in; +INST "dq_pad_io<7>" TNM = TNM_dq_in; +INST "dq_pad_io<8>" TNM = TNM_dq_in; +INST "dq_pad_io<9>" TNM = TNM_dq_in; +INST "dq_pad_io<10>" TNM = TNM_dq_in; +INST "dq_pad_io<11>" TNM = TNM_dq_in; +INST "dq_pad_io<12>" TNM = TNM_dq_in; +INST "dq_pad_io<13>" TNM = TNM_dq_in; +INST "dq_pad_io<14>" TNM = TNM_dq_in; +INST "dq_pad_io<15>" TNM = TNM_dq_in; + Index: versatile_mem_ctrl/tags/Rev2/backend/ACTEL/TwoPortRAM_256x36_work.ixf =================================================================== --- versatile_mem_ctrl/tags/Rev2/backend/ACTEL/TwoPortRAM_256x36_work.ixf (nonexistent) +++ versatile_mem_ctrl/tags/Rev2/backend/ACTEL/TwoPortRAM_256x36_work.ixf (revision 109) @@ -0,0 +1 @@ +TwoPortRAM_256x36WENinfalsefalsetrueRENinfalsefalsetrueWCLKinfalsefalsetrueRCLKinfalsefalsetrueWDin350falsefalsetrueRDout350falsefalsetrueWADDRin70falsefalsetrueRADDRin70falsefalsetrue \ No newline at end of file Index: versatile_mem_ctrl/tags/Rev2/backend/ACTEL/TwoPortRAM_256x36/TwoPortRAM_256x36.v =================================================================== --- versatile_mem_ctrl/tags/Rev2/backend/ACTEL/TwoPortRAM_256x36/TwoPortRAM_256x36.v (nonexistent) +++ versatile_mem_ctrl/tags/Rev2/backend/ACTEL/TwoPortRAM_256x36/TwoPortRAM_256x36.v (revision 109) @@ -0,0 +1,55 @@ +`timescale 1 ns/100 ps +// Version: 8.5 SP2 8.5.2.4 + + +module TwoPortRAM_256x36(WD,RD,WEN,REN,WADDR,RADDR,WCLK,RCLK); +input [35:0] WD; +output [35:0] RD; +input WEN, REN; +input [7:0] WADDR, RADDR; +input WCLK, RCLK; + + wire WEAP, WEBP, VCC, GND; + + VCC VCC_1_net(.Y(VCC)); + GND GND_1_net(.Y(GND)); + RAM512X18 TwoPortRAM_256x36_R0C1(.RADDR8(GND), .RADDR7( + RADDR[7]), .RADDR6(RADDR[6]), .RADDR5(RADDR[5]), .RADDR4( + RADDR[4]), .RADDR3(RADDR[3]), .RADDR2(RADDR[2]), .RADDR1( + RADDR[1]), .RADDR0(RADDR[0]), .WADDR8(GND), .WADDR7( + WADDR[7]), .WADDR6(WADDR[6]), .WADDR5(WADDR[5]), .WADDR4( + WADDR[4]), .WADDR3(WADDR[3]), .WADDR2(WADDR[2]), .WADDR1( + WADDR[1]), .WADDR0(WADDR[0]), .WD17(WD[35]), .WD16(WD[34]) + , .WD15(WD[33]), .WD14(WD[32]), .WD13(WD[31]), .WD12( + WD[30]), .WD11(WD[29]), .WD10(WD[28]), .WD9(WD[27]), .WD8( + WD[26]), .WD7(WD[25]), .WD6(WD[24]), .WD5(WD[23]), .WD4( + WD[22]), .WD3(WD[21]), .WD2(WD[20]), .WD1(WD[19]), .WD0( + WD[18]), .RW0(GND), .RW1(VCC), .WW0(GND), .WW1(VCC), + .PIPE(GND), .REN(WEBP), .WEN(WEAP), .RCLK(RCLK), .WCLK( + WCLK), .RESET(VCC), .RD17(RD[35]), .RD16(RD[34]), .RD15( + RD[33]), .RD14(RD[32]), .RD13(RD[31]), .RD12(RD[30]), + .RD11(RD[29]), .RD10(RD[28]), .RD9(RD[27]), .RD8(RD[26]), + .RD7(RD[25]), .RD6(RD[24]), .RD5(RD[23]), .RD4(RD[22]), + .RD3(RD[21]), .RD2(RD[20]), .RD1(RD[19]), .RD0(RD[18])); + RAM512X18 TwoPortRAM_256x36_R0C0(.RADDR8(GND), .RADDR7( + RADDR[7]), .RADDR6(RADDR[6]), .RADDR5(RADDR[5]), .RADDR4( + RADDR[4]), .RADDR3(RADDR[3]), .RADDR2(RADDR[2]), .RADDR1( + RADDR[1]), .RADDR0(RADDR[0]), .WADDR8(GND), .WADDR7( + WADDR[7]), .WADDR6(WADDR[6]), .WADDR5(WADDR[5]), .WADDR4( + WADDR[4]), .WADDR3(WADDR[3]), .WADDR2(WADDR[2]), .WADDR1( + WADDR[1]), .WADDR0(WADDR[0]), .WD17(WD[17]), .WD16(WD[16]) + , .WD15(WD[15]), .WD14(WD[14]), .WD13(WD[13]), .WD12( + WD[12]), .WD11(WD[11]), .WD10(WD[10]), .WD9(WD[9]), .WD8( + WD[8]), .WD7(WD[7]), .WD6(WD[6]), .WD5(WD[5]), .WD4(WD[4]) + , .WD3(WD[3]), .WD2(WD[2]), .WD1(WD[1]), .WD0(WD[0]), + .RW0(GND), .RW1(VCC), .WW0(GND), .WW1(VCC), .PIPE(GND), + .REN(WEBP), .WEN(WEAP), .RCLK(RCLK), .WCLK(WCLK), .RESET( + VCC), .RD17(RD[17]), .RD16(RD[16]), .RD15(RD[15]), .RD14( + RD[14]), .RD13(RD[13]), .RD12(RD[12]), .RD11(RD[11]), + .RD10(RD[10]), .RD9(RD[9]), .RD8(RD[8]), .RD7(RD[7]), + .RD6(RD[6]), .RD5(RD[5]), .RD4(RD[4]), .RD3(RD[3]), .RD2( + RD[2]), .RD1(RD[1]), .RD0(RD[0])); + INV WEBUBBLEB(.A(REN), .Y(WEBP)); + INV WEBUBBLEA(.A(WEN), .Y(WEAP)); + +endmodule Index: versatile_mem_ctrl/tags/Rev2/backend/ACTEL/TwoPortRAM_256x36/TwoPortRAM_256x36.gen =================================================================== --- versatile_mem_ctrl/tags/Rev2/backend/ACTEL/TwoPortRAM_256x36/TwoPortRAM_256x36.gen (nonexistent) +++ versatile_mem_ctrl/tags/Rev2/backend/ACTEL/TwoPortRAM_256x36/TwoPortRAM_256x36.gen (revision 109) @@ -0,0 +1,41 @@ +Version:8.5.2.4 +ACTGENU_CALL:1 +BATCH:T +FAM:ProASIC3 +OUTFORMAT:Verilog +LPMTYPE:LPM_RAM +LPM_HINT:TWO +INSERT_PAD:NO +INSERT_IOREG:NO +GEN_BHV_VHDL_VAL:F +GEN_BHV_VERILOG_VAL:F +MGNTIMER:F +MGNCMPL:T +DESDIR:L:/work/ocsvn/versatile_mem_ctrl/syn/ACTEL/vmc/smartgen\TwoPortRAM_256x36 +GEN_BEHV_MODULE:T +SMARTGEN_DIE:IS8X8M2 +SMARTGEN_PACKAGE:pq208 +AGENIII_IS_SUBPROJECT_LIBERO:T +WWIDTH:36 +WDEPTH:256 +RWIDTH:36 +RDEPTH:256 +CLKS:2 +RESET_POLARITY:2 +INIT_RAM:F +DEFAULT_WORD:0x000000000 +CASCADE:0 +WCLK_EDGE:RISE +RCLK_EDGE:RISE +WCLOCK_PN:WCLK +RCLOCK_PN:RCLK +PMODE2:0 +DATA_IN_PN:WD +WADDRESS_PN:WADDR +WE_PN:WEN +DATA_OUT_PN:RD +RADDRESS_PN:RADDR +RE_PN:REN +WE_POLARITY:1 +RE_POLARITY:1 +PTYPE:1 Index: versatile_mem_ctrl/tags/Rev2/backend/ACTEL/TwoPortRAM_256x36/TwoPortRAM_256x36.cxf =================================================================== --- versatile_mem_ctrl/tags/Rev2/backend/ACTEL/TwoPortRAM_256x36/TwoPortRAM_256x36.cxf (nonexistent) +++ versatile_mem_ctrl/tags/Rev2/backend/ACTEL/TwoPortRAM_256x36/TwoPortRAM_256x36.cxf (revision 109) @@ -0,0 +1 @@ +TwoPortRAM_256x36TwoPortRAM_256x36.vverilogSourceTwoPortRAM_256x36.genGENTwoPortRAM_256x36.logLOGTwoPortRAM_256x36.shxOtherTwoPortRAM_256x36_R0C0.memMEMTwoPortRAM_256x36_R0C1.memMEMHDL_FILESETHDLOTHER_FILESETOTHERANY_SIMULATION_FILESETSIMULATIONRAMRAMTwo Port RAMActel2.2WDin350falsefalsetrueRDout350falsefalsetrueWENinfalsefalsetrueRENinfalsefalsetrueWADDRin70falsefalsetrueRADDRin70falsefalsetrueWCLKinfalsefalsetrueRCLKinfalsefalsetrue \ No newline at end of file Index: versatile_mem_ctrl/tags/Rev2/backend/ACTEL/TwoPortRAM_256x36/TwoPortRAM_256x36.log =================================================================== --- versatile_mem_ctrl/tags/Rev2/backend/ACTEL/TwoPortRAM_256x36/TwoPortRAM_256x36.log (nonexistent) +++ versatile_mem_ctrl/tags/Rev2/backend/ACTEL/TwoPortRAM_256x36/TwoPortRAM_256x36.log (revision 109) @@ -0,0 +1,87 @@ + ** Message System Log + ** Database: + ** Date: Thu Jun 25 17:18:45 2009 + + +**************** +Macro Parameters +**************** + +Name : TwoPortRAM_256x36 +Family : ProASIC3 +Output Format : VERILOG +Type : RAM +Write Enable : Active High +Read Enable : Active High +Reset : None +LP : None +FF : None +Read Clock : Rising +Write Clock : Rising +Write Depth : 256 +Write Width : 36 +Read Depth : 256 +Read Width : 36 +RAM Type : Two Port +Clocks : Independent Read and Write Clocks +Write Mode A : Hold Data +Write Mode B : Hold Data +Read Pipeline A : No +Read Pipeline B : No +Optimized for : Speed +Portname DataIn : WD +Portname DataOut : RD +Portname Write En : WEN +Portname Read En : REN +Portname WClock : WCLK +Portname RClock : RCLK +Portname WAddress : WADDR +Portname RAddress : RADDR +Portname Reset : +Portname Clock : +Portname DataAIn : +Portname DataBIn : +Portname DataAOut : +Portname DataBOut : +Portname AddressA : +Portname AddressB : +Portname CLKA : +Portname CLKB : +Portname RWA : +Portname RWB : +Portname BLKA : +Portname BLKB : +Portname LP : +Portname FF : +Initialize RAM : False + +Cascade Configuration: + Write Port configuration : 256x18 + Read Port configuration : 256x18 + Number of blocks depth wise: 1 + Number of blocks width wise: 2 + +************** +Compile Report +************** + + +Netlist Resource Report +======================= + + CORE Used: 2 Total: 24576 (0.01%) + IO (W/ clocks) Used: 0 Total: 154 (0.00%) + Differential IO Used: 0 Total: 35 (0.00%) + GLOBAL (Chip+Quadrant) Used: 0 Total: 18 (0.00%) + PLL Used: 0 Total: 1 (0.00%) + RAM/FIFO Used: 2 Total: 32 (6.25%) + Low Static ICC Used: 0 Total: 1 (0.00%) + FlashROM Used: 0 Total: 1 (0.00%) + User JTAG Used: 0 Total: 1 (0.00%) + +Wrote Verilog netlist to +L:/work/ocsvn/versatile_mem_ctrl/syn/ACTEL/vmc/smartgen\TwoPortRAM_256x36\Two\ +PortRAM_256x36.v. + + ** Log Ended: Thu Jun 25 17:18:46 2009 + Index: versatile_mem_ctrl/tags/Rev2/backend/ACTEL/TwoPortRAM_256x36/TwoPortRAM_256x36.shx =================================================================== --- versatile_mem_ctrl/tags/Rev2/backend/ACTEL/TwoPortRAM_256x36/TwoPortRAM_256x36.shx (nonexistent) +++ versatile_mem_ctrl/tags/Rev2/backend/ACTEL/TwoPortRAM_256x36/TwoPortRAM_256x36.shx (revision 109) @@ -0,0 +1,256 @@ +0:0000000000 +1:0000000000 +2:0000000000 +3:0000000000 +4:0000000000 +5:0000000000 +6:0000000000 +7:0000000000 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