URL
https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk
Subversion Repositories xulalx25soc
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- This comparison shows the changes necessary to convert path
/
- from Rev 108 to Rev 109
- ↔ Reverse comparison
Rev 108 → Rev 109
/xulalx25soc/trunk/rtl/wbudecompress.v
2,7 → 2,7
// |
// Filename: wbudecompress.v |
// |
// Project: XuLA2 board |
// Project: FPGA library |
// |
// Purpose: Compression via this interface is simply a lookup table. |
// When writing, if requested, rather than writing a new 36-bit |
17,7 → 17,7
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// Copyright (C) 2015-2016, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
94,7 → 94,7
if (~r_word[34]) |
rd_len <= 10'h01 + { 6'h00, r_word[33:31] }; |
else |
rd_len <= 10'h08 + { 1'b0, r_word[33:31], r_word[29:24] }; |
rd_len <= 10'h09 + { 1'b0, r_word[33:31], r_word[29:24] }; |
|
// Clock three, read the table value |
// { o_stb, r_stb } = 4'h4 when done |
/xulalx25soc/trunk/rtl/wbuexec.v
2,7 → 2,7
// |
// Filename: wbuexec.v |
// |
// Project: XuLA2 board |
// Project: FPGA library |
// |
// Purpose: This is the part of the USB-JTAG to wishbone conversion that |
// actually conducts a wishbone transaction. Transactions are |
52,7 → 52,8
input [35:0] i_codword; |
output wire o_busy; |
// Wishbone outputs |
output wire o_wb_cyc, o_wb_stb; |
output reg o_wb_cyc; |
output reg o_wb_stb; |
output reg o_wb_we; |
output reg [31:0] o_wb_addr, o_wb_data; |
// Wishbone inputs |
79,6 → 80,7
reg [2:0] wb_state; |
reg [9:0] r_acks_needed, r_len; |
reg r_inc, r_new_addr, last_read_request, last_ack, zero_acks; |
reg single_read_request; |
|
initial r_new_addr = 1'b1; |
initial wb_state = `WB_IDLE; |
88,9 → 90,13
begin |
wb_state <= `WB_IDLE; |
o_stb <= 1'b1; |
o_codword <= { 6'h3, i_wb_data[29:0] }; |
o_codword <= { 6'h3, i_wb_data[29:0] }; // BUS Reset |
o_wb_cyc <= 1'b0; |
o_wb_stb <= 1'b0; |
end else case(wb_state) |
`WB_IDLE: begin |
o_wb_cyc <= 1'b0; |
o_wb_stb <= 1'b0; |
// Now output codewords while we're idle, |
// ... unless we get an address command (later). |
o_stb <= 1'b0; |
127,18 → 133,21
// |
casez(i_codword[35:32]) |
4'b0000: begin // Set a new (arbitrary) address |
r_new_addr <= 1'b1; |
o_wb_addr <= i_codword[31:0]; |
// r_new_addr <= 1'b1; |
o_wb_addr <= i_codword[31:0]; //w_cod_data |
end |
4'b001?: begin // Set a new relative address |
r_new_addr <= 1'b1; |
o_wb_addr <= o_wb_addr |
// r_new_addr <= 1'b1; |
o_wb_addr <= o_wb_addr // + w_cod_data; |
|
+ { i_codword[32:31], i_codword[29:0] }; |
end |
4'b01??: begin // Start a write transaction, |
// address is alrdy set |
r_new_addr <= 1'b1; |
// r_new_addr <= 1'b1; |
wb_state <= `WB_WRITE_REQUEST; |
o_wb_cyc <= 1'b1; |
o_wb_stb <= 1'b1; |
end |
4'b11??: begin // Start a vector read |
// Address is already set ... |
146,6 → 155,8
if (r_new_addr) |
o_stb <= 1'b1; |
wb_state <= `WB_READ_REQUEST; |
o_wb_cyc <= 1'b1; |
o_wb_stb <= 1'b1; |
end |
default: |
; |
152,7 → 163,8
endcase |
end end |
`WB_READ_REQUEST: begin |
r_new_addr <= 1'b0; |
o_wb_cyc <= 1'b1; |
o_wb_stb <= 1'b1; |
|
if (i_wb_err) |
wb_state <= `WB_IDLE; |
159,9 → 171,9
|
o_stb <= (i_wb_err)||(i_wb_ack); |
|
if (i_wb_err) |
if (i_wb_err) // Bus Error |
o_codword <= { 6'h5, i_wb_data[29:0] }; |
else |
else // Read data on ack |
o_codword <= { 3'h7, i_wb_data[31:30], r_inc, |
i_wb_data[29:0] }; |
|
171,15 → 183,20
|
if (~i_wb_stall) // Deal with the strobe line |
begin // Strobe was accepted, busy should be '1' here |
if (last_read_request) // (r_len != 0) // read |
if ((single_read_request)||(last_read_request)) // (r_len != 0) // read |
begin |
wb_state <= `WB_ACK; |
o_wb_stb <= 1'b0; |
end |
end end |
`WB_WRITE_REQUEST: begin |
r_new_addr <= 1'b0; |
o_wb_cyc <= 1'b1; |
o_wb_stb <= 1'b1; |
// |
|
if (i_wb_err) |
if (i_wb_err) // Bus Err |
o_codword <= { 6'h5, i_wb_data[29:0] }; |
else |
else // Write acknowledgement |
o_codword <= { 6'h2, i_wb_data[29:0] }; |
|
if ((r_inc)&&(~i_wb_stall)) |
196,11 → 213,16
begin |
wb_state <= `WB_FLUSH_WRITE_REQUESTS; |
// |
o_wb_cyc <= 1'b0; |
o_wb_stb <= 1'b0; |
end else if (~i_wb_stall) |
begin |
wb_state <= `WB_WAIT_ON_NEXT_WRITE; |
end |
o_wb_stb <= 1'b0; |
end end |
`WB_ACK: begin |
r_new_addr <= 1'b0; |
o_wb_cyc <= 1'b1; |
o_wb_stb <= 1'b0; |
// |
// No strobes are being sent out. No further |
// bus transactions are requested. We only need |
208,9 → 230,9
// for (and recording?) their acks. |
// |
// Process acknowledgements |
if (i_wb_err) |
if (i_wb_err) // Bus error |
o_codword <= { 6'h5, i_wb_data[29:0] }; |
else |
else // Read data |
o_codword <= { 3'h7, i_wb_data[31:30], r_inc, |
i_wb_data[29:0] }; |
|
219,22 → 241,33
o_stb <= (((i_wb_ack)&&(~o_wb_we)) || (i_wb_err)); |
|
if (((last_ack)&&(i_wb_ack))||(zero_acks)||(i_wb_err)) |
begin |
o_wb_cyc <= 1'b0; |
wb_state <= `WB_IDLE; |
end |
end end |
`WB_WAIT_ON_NEXT_WRITE: begin |
r_new_addr <= 1'b0; |
|
o_codword <= { 6'h5, i_wb_data[29:0] }; |
o_stb <= (i_wb_err)||(w_new_err); |
|
o_wb_data <= w_cod_data; |
o_wb_cyc <= 1'b1; |
o_wb_stb <= 1'b0; |
|
if (w_new_err) // Something other than a write or EOW |
begin |
o_wb_cyc <= 1'b0; |
wb_state <= `WB_IDLE; |
else if (i_wb_err) // Bus returns an error |
end else if (i_wb_err) // Bus returns an error |
begin |
o_wb_cyc <= 1'b0; |
wb_state <= `WB_FLUSH_WRITE_REQUESTS; |
end |
else if (w_newwr) // Need to make a new write request |
begin |
wb_state <= `WB_WRITE_REQUEST; |
o_wb_stb <= 1'b1; |
end |
else if (w_eow) // All done writing, wait for last ack |
wb_state <= `WB_ACK; |
end |
247,8 → 280,9
// In the off chance that we are in here in error, or |
// out of sync, we'll transition to WB_IDLE and just |
// issue a second error token. |
r_new_addr <= 1'b0; |
|
o_wb_cyc <= 1'b0; |
o_wb_stb <= 1'b0; |
o_codword <= { 6'h5, i_wb_data[29:0] }; |
o_stb <= (w_new_err); |
|
259,6 → 293,8
o_stb <= 1'b1; |
o_codword <= { 6'h3, i_wb_data[29:0] }; |
wb_state <= `WB_IDLE; |
o_wb_cyc <= 1'b0; |
o_wb_stb <= 1'b0; |
end |
endcase |
|
265,15 → 301,23
assign o_busy = (wb_state != `WB_IDLE) |
&&(wb_state != `WB_WAIT_ON_NEXT_WRITE) |
&&(wb_state != `WB_FLUSH_WRITE_REQUESTS); |
assign o_wb_cyc = (wb_state == `WB_READ_REQUEST) |
||(wb_state == `WB_WRITE_REQUEST) |
||(wb_state == `WB_ACK) |
||(wb_state == `WB_WAIT_ON_NEXT_WRITE); |
assign o_wb_stb = (wb_state == `WB_READ_REQUEST) |
||(wb_state == `WB_WRITE_REQUEST); |
//assign o_wb_cyc = (wb_state == `WB_READ_REQUEST) |
//||(wb_state == `WB_WRITE_REQUEST) |
//||(wb_state == `WB_ACK) |
//||(wb_state == `WB_WAIT_ON_NEXT_WRITE); |
//assign o_wb_stb = (wb_state == `WB_READ_REQUEST) |
// ||(wb_state == `WB_WRITE_REQUEST); |
|
always @(posedge i_clk) |
if (wb_state == `WB_IDLE) |
if (i_rst) |
r_new_addr <= 1'b1; |
else if ((~o_wb_cyc)&&(i_stb)&&(~i_codword[35])) |
r_new_addr <= 1'b1; |
else if (o_wb_cyc) |
r_new_addr <= 1'b0; |
|
always @(posedge i_clk) |
if (~o_wb_cyc) |
r_acks_needed <= 10'h00; // (i_codword[35])?i_codword[9:0]:10'h00; |
else if ((o_wb_stb)&&(~i_wb_stall)&&(~i_wb_ack)) |
r_acks_needed <= r_acks_needed + 10'h01; |
281,18 → 325,26
r_acks_needed <= r_acks_needed - 10'h01; |
|
always @(posedge i_clk) |
last_ack <= (~o_wb_stb)&&(r_acks_needed == 10'h01); |
last_ack <= (~o_wb_stb)&&(r_acks_needed == 10'h01) |
||(o_wb_stb)&&(r_acks_needed == 10'h00); |
|
always @(posedge i_clk) |
zero_acks <= (~o_wb_stb)&&(r_acks_needed == 10'h00); |
|
always @(posedge i_clk) |
if ((wb_state == `WB_IDLE)&&(i_codword[35:34] == 2'b11)) |
r_len <= i_codword[9:0] - 10'h01; |
if (~o_wb_cyc) // &&(i_codword[35:34] == 2'b11)) |
r_len <= i_codword[9:0]; |
else if ((o_wb_stb)&&(~i_wb_stall)&&(|r_len)) |
r_len <= r_len - 10'h01; |
|
always @(posedge i_clk) |
last_read_request <= (r_len[9:0] == 10'h000); |
begin |
single_read_request <= (~o_wb_cyc)&&(i_codword[9:0] == 10'h01); |
// When there is one read request left, it will be the last one |
// will be the last one |
last_read_request <= (o_wb_stb)&&(r_len[9:2] == 8'h00) |
&&((~r_len[1]) |
||((~r_len[0])&&(~i_wb_stall))); |
end |
|
endmodule |
/xulalx25soc/trunk/rtl/wbucompress.v
2,7 → 2,7
// |
// Filename: wbucompress.v |
// |
// Project: XuLA2 board |
// Project: FPGA library |
// |
// Purpose: When reading many words that are identical, it makes no sense |
// to spend the time transmitting the same thing over and over |
26,7 → 26,7
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// Copyright (C) 2015-2016, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
133,7 → 133,7
// table is full or not. This logic follows: |
// |
reg [(TBITS-1):0] tbl_addr; |
reg r_compressed, tbl_filled; |
reg tbl_filled; |
// First part, write the compression table |
always @(posedge i_clk) |
// If we send a new address, then reset the table to empty |
175,29 → 175,58
// If we find any that matches, we're there. We might (or might not) |
// make it through the table first. That's irrelevant. We just look |
// while we can. |
reg tbl_match, nxt_match; // <= (nxt_rd_addr == tbl_addr); |
reg [(TBITS-1):0] rd_addr; |
wire [(TBITS-1):0] nxt_rd_addr; |
assign nxt_rd_addr = rd_addr - { {(TBITS-1){1'b0}}, 1'b1 }; |
reg [(TBITS-1):0] nxt_rd_addr; |
initial rd_addr = 0; |
initial tbl_match = 0; |
always @(posedge i_clk) |
begin |
nxt_match <= ((nxt_rd_addr-tbl_addr)=={{(TBITS-1){1'b0}},1'b1}); |
if ((w_accepted)||(~a_stb)) |
begin |
// Keep in mind, if a write was just accepted, then |
// rd_addr will need to be reset on the next clock |
// when (~a_stb). Hence this must be a two clock |
// update |
rd_addr <= tbl_addr + {(TBITS){1'b1}}; |
else if ((nxt_rd_addr != tbl_addr)&&(~match) |
nxt_rd_addr = tbl_addr + { {(TBITS-1){1'b1}}, 1'b0 }; |
tbl_match <= 1'b0; |
end else if ((~tbl_match)&&(~match) |
&&((~nxt_rd_addr[TBITS-1])||(tbl_filled))) |
begin |
rd_addr <= nxt_rd_addr; |
nxt_rd_addr = nxt_rd_addr - { {(TBITS-1){1'b0}}, 1'b1 }; |
tbl_match <= nxt_match; |
end |
end |
|
reg [1:0] pmatch; |
reg dmatch, // Match, on clock 'd' |
vaddr; // Was the address valid then? |
reg [(DW-1):0] cword; |
reg [(TBITS-1):0] caddr; |
reg [(TBITS-1):0] caddr, daddr, maddr; |
always @(posedge i_clk) |
begin |
cword <= compression_tbl[rd_addr]; |
caddr <= rd_addr; |
|
dmatch <= (cword == { r_word[32:31], r_word[29:0] }); |
daddr <= caddr; |
maddr <= tbl_addr - caddr; |
|
vaddr <= ( {1'b0, caddr} < {tbl_filled, tbl_addr} ) |
&&(caddr != tbl_addr); |
end |
|
always @(posedge i_clk) |
if ((w_accepted)||(~a_stb)) |
pmatch <= 0; // rd_addr is set on this clock |
else |
// cword is set on the next clock, pmatch = 3'b001 |
// dmatch is set on the next clock, pmatch = 3'b011 |
pmatch <= { pmatch[0], 1'b1 }; |
|
reg match; |
reg [9:0] matchaddr; |
always @(posedge i_clk) |
206,17 → 235,20
else if (~match) |
begin |
// To be a match, the table must not be empty, |
match <= (({1'b0, caddr } < {tbl_filled, tbl_addr})) |
// the word we are matching to must be |
// in the form of a read command |
&&(r_word[35:33] == 3'b111) |
// And the word in the table must be |
// identical to the word we are about |
// to send. |
&&(cword == { r_word[32:31], r_word[29:0] }); |
matchaddr <= tbl_addr-caddr; |
match <= (vaddr)&&(dmatch)&&(r_word[35:33]==3'b111) |
&&(pmatch == 2'b11); |
end |
|
reg zmatch, hmatch, fmatch; |
always @(posedge i_clk) |
if (~match) |
begin |
matchaddr <= maddr; |
fmatch <= (maddr < 10'h521); |
zmatch <= (maddr == 10'h1); |
hmatch <= (maddr < 10'd10); |
end |
|
// Did we find something? |
wire [(TBITS-1):0] adr_diff; |
wire [9:0] adr_dbld; |
224,24 → 256,22
assign adr_diff = matchaddr; |
assign adr_hlfd = matchaddr[2:0]- 3'd2; |
assign adr_dbld = matchaddr- 10'd10; |
initial r_compressed = 1'b0; |
reg [(CW-1):0] r_cword; // Record our result |
always @(posedge i_clk) |
begin |
if ((~a_stb)||(~r_stb)||(w_accepted))//Reset whenever word gets written |
r_compressed <= 1'b0; // to our output |
else if (r_compressed)//Already compressed, wait 'til sent |
; |
else if ((match)&&(matchaddr < 10'd521)) // &&(r_word == a_addrword)) |
begin |
if (matchaddr == 10'h1) |
r_cword <= r_word; |
end else if ((match)&&(fmatch)) // &&(r_word == a_addrword)) |
begin |
r_cword <= r_word; |
if (zmatch) // matchaddr == 1 |
r_cword[35:30] <= { 5'h3, r_word[30] }; |
else if (adr_diff < 10'd10) |
else if (hmatch) // 2 <= matchaddr <= 9 |
r_cword[35:30] <= { 2'b10, adr_hlfd, r_word[30] }; |
else // if (adr_diff < 10'd521) |
r_cword[35:24] <= { 2'b01, adr_dbld[8:6], |
r_word[30], adr_dbld[5:0] }; |
r_compressed <= 1'b1; |
end else |
r_cword <= r_word; |
end |
248,6 → 278,6
|
// Can we do this without a clock delay? |
assign o_stb = a_stb; |
assign o_cword = (r_compressed)?(r_cword):(a_addrword); |
assign o_cword = (r_stb)?(r_cword):(a_addrword); |
endmodule |
|
/xulalx25soc/trunk/sw/ttybus.cpp
68,14 → 68,14
const unsigned TTYBUS::MAXRDLEN = 1024; |
const unsigned TTYBUS::MAXWRLEN = 32; |
|
// #define DBGPRINTF printf |
#define DBGPRINTF filedump |
#ifndef DBGPRINTF |
#define DBGPRINTF null |
// #define DBGPRINTF printf |
// #define DBGPRINTF filedump |
#endif |
|
void null(...) {} |
#include <stdarg.h> |
// #include <varargs.h> |
/* |
#include <stdarg.h> // replaces the (defunct) varargs.h include file |
void filedump(const char *fmt, ...) { |
static FILE *dbgfp = NULL; |
va_list args; |
86,8 → 86,13
vfprintf(dbgfp, fmt, args); |
va_end(args); |
fflush(dbgfp); |
|
// If you want the debug output to go to stderr as well, you can |
// uncomment the next couple of lines |
// va_start(args, fmt); |
// vfprintf(stderr, fmt, args); |
// va_end(args); |
} |
*/ |
|
char TTYBUS::charenc(const int sixbitval) const { |
if (sixbitval < 10) |
124,6 → 129,7
int TTYBUS::lclreadcode(char *buf, int len) { |
char *sp, *dp; |
int nr, ret; |
static int lastskip = 0; |
|
nr = m_dev->read(buf, len); |
m_total_nread += nr; |
130,10 → 136,18
ret = nr; sp = buf; dp = buf; |
for(int i=0; i<nr; i++) { |
if (chardec(*sp)&(~0x3f)) { |
int uv = (*sp)&0x0ff; |
ret--; // Skip this value, not a valid codeword |
if ((false)&&((!lastskip)||(uv != lastskip))) { |
DBGPRINTF("lclreadcode: Skipping %02x\n", uv); |
lastskip = uv; |
} |
sp++; |
} else { |
*sp++ = *dp++; |
lastskip = 0; |
// DBGPRINTF("lclreadcode: Read %c (%02x -> %02x)\n", |
// *sp, *sp, chardec(*sp)); |
*dp++ = *sp++; |
} |
} return ret; |
} |
188,6 → 202,7
|
void TTYBUS::writev(const BUSW a, const int p, const int len, const BUSW *buf) { |
char *ptr; |
int nw = 0; |
|
// We'll never be called with more than MAXWRLEN words to write at once. |
// This is a configurable option length, set at the top of this file. |
206,21 → 221,26
ptr = encode_address(a); |
m_lastaddr = a; m_addr_set = true; |
|
for(int i=0; i<len; i++) { |
BUSW val = buf[i]; |
while(nw < len) { |
int ln = len-nw; |
if ((unsigned)ln > MAXWRLEN) |
ln = MAXWRLEN; |
|
int caddr = 0; |
// Let's try compression |
for(int i=1; i<256; i++) { |
unsigned tstaddr; |
tstaddr = (m_wraddr - i) & 0x0ff; |
if ((!m_wrloaded)&&(tstaddr > (unsigned)m_wraddr)) |
break; |
if (m_writetbl[tstaddr] == val) { |
caddr = ( m_wraddr- tstaddr ) & 0x0ff; |
break; |
for(int i=0; i<ln; i++) { |
BUSW val = buf[nw+i]; |
|
int caddr = 0; |
// Let's try compression |
for(int i=1; i<256; i++) { |
unsigned tstaddr; |
tstaddr = (m_wraddr - i) & 0x0ff; |
if ((!m_wrloaded)&&(tstaddr > (unsigned)m_wraddr)) |
break; |
if (m_writetbl[tstaddr] == val) { |
caddr = ( m_wraddr- tstaddr ) & 0x0ff; |
break; |
} |
} |
} |
|
/* |
if (caddr != 0) |
229,33 → 249,40
DBGPRINTF("WR[%08x] = %08x\n", m_lastaddr, val); |
*/ |
|
if (caddr != 0) { |
*ptr++ = charenc( (((caddr>>6)&0x03)<<1) + (p?1:0) + 0x010); |
*ptr++ = charenc( caddr &0x3f ); |
if (caddr != 0) { |
*ptr++ = charenc( (((caddr>>6)&0x03)<<1) + (p?1:0) + 0x010); |
*ptr++ = charenc( caddr &0x3f ); |
|
} else { |
// For testing, let's start just doing this the hard way |
*ptr++ = charenc( (((val>>30)&0x03)<<1) + (p?1:0) + 0x018); |
*ptr++ = charenc( (val>>24)&0x3f); |
*ptr++ = charenc( (val>>18)&0x3f); |
*ptr++ = charenc( (val>>12)&0x3f); |
*ptr++ = charenc( (val>> 6)&0x3f); |
*ptr++ = charenc( (val )&0x3f); |
} else { |
// For testing, let's start just doing this the hard way |
*ptr++ = charenc( (((val>>30)&0x03)<<1) + (p?1:0) + 0x018); |
*ptr++ = charenc( (val>>24)&0x3f); |
*ptr++ = charenc( (val>>18)&0x3f); |
*ptr++ = charenc( (val>>12)&0x3f); |
*ptr++ = charenc( (val>> 6)&0x3f); |
*ptr++ = charenc( (val )&0x3f); |
|
m_writetbl[m_wraddr++] = val; |
m_wraddr &= 0x0ff; |
if (m_wraddr == 0) { |
m_wrloaded = true; |
m_writetbl[m_wraddr++] = val; |
m_wraddr &= 0x0ff; |
if (m_wraddr == 0) { |
m_wrloaded = true; |
} |
} |
|
if (p == 1) m_lastaddr++; |
} |
// *ptr++ = charenc(0x2e); |
if (ln == len-nw) |
*ptr++ = '\n'; |
*ptr = '\0'; |
m_dev->write(m_buf, ptr-m_buf); |
DBGPRINTF(">> %s\n", m_buf); |
|
if (p == 1) m_lastaddr++; |
readidle(); |
|
nw += ln; |
ptr = m_buf; |
} |
// *ptr++ = charenc(0x2e); |
*ptr++ = '\n'; *ptr = '\0'; |
m_dev->write(m_buf, ptr-m_buf); |
|
DBGPRINTF(">> %s\n", m_buf); |
DBGPRINTF("WR: LAST ADDRESS LEFT AT %08x\n", m_lastaddr); |
|
// Need to clear the incoming queue ... if there's anything there. |
272,6 → 299,7
} |
|
void TTYBUS::writez(const BUSW a, const int len, const BUSW *buf) { |
/* |
int ln = len; |
const TTYBUS::BUSW *bptr = buf; |
TTYBUS::BUSW addr = a; |
283,9 → 311,12
// addr += MAXWRLEN; |
} if ((unsigned)ln > 0) |
writev(addr, 0, ln, bptr); |
*/ |
writev(a, 0, len, buf); |
} |
|
void TTYBUS::writei(const BUSW a, const int len, const BUSW *buf) { |
/* |
int ln = len; |
const TTYBUS::BUSW *bptr = buf; |
TTYBUS::BUSW addr = a; |
297,6 → 328,8
addr += MAXWRLEN; |
} if ((unsigned)ln > 0) |
writev(addr, 1, ln, bptr); |
*/ |
writev(a, 1, len, buf); |
} |
|
TTYBUS::BUSW TTYBUS::readio(const TTYBUS::BUSW a) { |
308,6 → 341,7
try { |
readv(a, 0, 1, &v); |
} catch(BUSERR b) { |
DBGPRINTF("BUSERR trying to read %08x\n", a); |
throw BUSERR(a); |
} |
|
325,10 → 359,6
TTYBUS::BUSW addr = a; |
char *ptr = m_buf; |
|
// #warning DEBUG_APPROACH |
// encode(0, addr, ptr); |
// return ptr+6; |
|
if ((m_addr_set)&&(a == m_lastaddr)) |
return ptr; |
|
356,7 → 386,10
*ptr++ = charenc( diffaddr & 0x03f); |
} |
*ptr = '\0'; |
DBGPRINTF("DIF-ADDR: (%ld) \'%s\'\n", ptr-m_buf, m_buf); |
DBGPRINTF("DIF-ADDR: (%ld) \'%s\' encodes last_addr(0x%08x) %c %d(0x%08x)\n", |
ptr-m_buf, m_buf, |
m_lastaddr, (diffaddr<0)?'-':'+', |
diffaddr, diffaddr&0x0ffffffff); |
} |
|
{ |
369,13 → 402,13
*ptr++ = charenc(0x08); |
*ptr++ = charenc(addr); |
} else if((addr <= 0x0fff)&&((ptr == m_buf)||(ptr >= &m_buf[3]))) { |
DBGPRINTF("Setting ADDR.3 to %08x\n", addr); |
// DBGPRINTF("Setting ADDR.3 to %08x\n", addr); |
ptr = m_buf; |
*ptr++ = charenc(0x0a); |
*ptr++ = charenc((addr>> 6) & 0x03f); |
*ptr++ = charenc( addr & 0x03f); |
} else if((addr <= 0x03ffff)&&((ptr == m_buf)||(ptr >= &m_buf[4]))) { |
DBGPRINTF("Setting ADDR.4 to %08x\n", addr); |
// DBGPRINTF("Setting ADDR.4 to %08x\n", addr); |
ptr = m_buf; |
*ptr++ = charenc(0x0c); |
*ptr++ = charenc((addr>>12) & 0x03f); |
382,7 → 415,7
*ptr++ = charenc((addr>> 6) & 0x03f); |
*ptr++ = charenc( addr & 0x03f); |
} else if((addr <= 0x0ffffff)&&((ptr == m_buf)||(ptr >= &m_buf[5]))) { |
DBGPRINTF("Setting ADDR.5 to %08x\n", addr); |
// DBGPRINTF("Setting ADDR.5 to %08x\n", addr); |
ptr = m_buf; |
*ptr++ = charenc(0x0e); |
*ptr++ = charenc((addr>>18) & 0x03f); |
397,7 → 430,7
} |
|
*ptr = '\0'; |
DBGPRINTF("ADDR-CMD: (%ld) \'%s\'\n", ptr-m_buf, m_buf); |
// DBGPRINTF("ADDR-CMD: (%ld) \'%s\'\n", ptr-m_buf, m_buf); |
m_rdaddr = 0; |
|
return ptr; |
406,15 → 439,17
char *TTYBUS::readcmd(const int inc, const int len, char *buf) { |
char *ptr = buf; |
|
DBGPRINTF("READCMD: LEN = %d\n", len); |
DBGPRINTF("READCMD: LEN = %d: ", len); |
assert(len < 520); |
assert(len > 0); |
|
if ((len < 8)||((len == 8)&&(inc))) { |
if (len <= 8) { |
*ptr++ = charenc(0x20 + (((len-1)&0x07)<<1) + (inc?1:0)); |
DBGPRINTF("%c\n", ptr[-1]); |
} else { |
*ptr++ = charenc(0x30 + (((len-8)>>5)&0x0e) + (inc?1:0)); |
*ptr++ = charenc( (len-8) & 0x03f); |
*ptr++ = charenc(0x30 + (((len-9)>>5)&0x0e) + (inc?1:0)); |
*ptr++ = charenc( (len-9) & 0x03f); |
DBGPRINTF("%c%c\n", ptr[-2], ptr[-1]); |
} |
|
return ptr; |
421,7 → 456,7
} |
|
void TTYBUS::readv(const TTYBUS::BUSW a, const int inc, const int len, TTYBUS::BUSW *buf) { |
const int READAHEAD = MAXRDLEN/2, READBLOCK=MAXRDLEN/2; |
const int READAHEAD = 0, READBLOCK=(MAXRDLEN/2>512)?512:MAXRDLEN/2; |
int cmdrd = 0, nread = 0; |
// TTYBUS::BUSW addr = a; |
char *ptr = m_buf; |
428,9 → 463,8
|
if (len <= 0) |
return; |
DBGPRINTF("READV(%08x,%d,#%4d)\n", a, inc, len); |
// DBGPRINTF("READV(%08x,%d,#%4d)\n", a, inc, len); |
|
// m_addr_set = false; |
ptr = encode_address(a); |
try { |
while(cmdrd < len) { |
451,10 → 485,12
while(nread<(cmdrd-READAHEAD)) { |
buf[nread++] = readword(); |
} ptr = m_buf; |
} while(nread<len) { |
} // DBGPRINTF("Reading %d words, to end the read\n", len-nread); |
while(nread<len) { |
buf[nread++] = readword(); |
} |
} catch(BUSERR b) { |
DBGPRINTF("READV::BUSERR trying to read %08x\n", a+((inc)?nread:0)); |
throw BUSERR(a+((inc)?nread:0)); |
} |
|
465,6 → 501,8
assert((int)m_lastaddr == (a+(inc)?(len):0)); |
exit(-3); |
} |
|
DBGPRINTF("READV::COMPLETE\n"); |
} |
|
void TTYBUS::readi(const TTYBUS::BUSW a, const int len, TTYBUS::BUSW *buf) { |
578,12 → 616,14
m_lastaddr += (sixbits&1); |
DBGPRINTF("READ-WORD() -- long table value[%3d], %08x, A=%08x\n", idx, val, m_lastaddr); |
} else if (0x20 == (sixbits & 0x030)) { // Tbl read, 2-9 into past |
rdaddr = (m_rdaddr - (((sixbits>>1)&0x07)+2)) & 0x03ff; |
int idx; |
idx = (((sixbits>>1)&0x07)+2); |
rdaddr = (m_rdaddr - idx) & 0x03ff; |
val = m_readtbl[rdaddr]; |
m_lastaddr += (sixbits&1); |
DBGPRINTF("READ-WORD() -- short table value[%3d], %08x, A=%08x\n", rdaddr, val, m_lastaddr); |
DBGPRINTF("READ-WORD() -- short table value[%3d], %08x, A=%08x\n", idx, val, m_lastaddr); |
} else if (0x38 == (sixbits & 0x038)) { // Raw read |
DBGPRINTF("READ-WORD() -- RAW-READ, nr = %d\n", nr); |
// DBGPRINTF("READ-WORD() -- RAW-READ, nr = %d\n", nr); |
do { |
nr += lclreadcode(&m_buf[nr], 6-nr); |
} while (nr < 6); |
627,7 → 667,11
switch(sixbits) { |
case 0: break; // Idle -- ignore |
case 1: break; // Idle, but the bus is busy |
case 2: break; // Write acknowledgement, ignore it here |
case 2: |
// Write acknowledgement, ignore it here |
// This is one of the big reasons why we are |
// doing this. |
break; |
case 3: |
m_bus_err = true; |
DBGPRINTF("READ-IDLE() - BUSERR\n"); |
696,7 → 740,7
// But ... we did. So, just read it off and ignore it. |
int rdaddr; |
|
// DBGPRINTF("READ-WORD() -- sixbits = %02x\n", sixbits); |
DBGPRINTF("READ-IDLE() PANIC! -- sixbits = %02x\n", sixbits); |
if (0x06 == (sixbits & 0x03e)) { // Tbl read, last value |
rdaddr = (m_rdaddr-1)&0x03ff; |
val = m_readtbl[rdaddr]; |
720,7 → 764,6
m_lastaddr += (sixbits&1); |
DBGPRINTF("READ-IDLE() -- short table value[%3d], %08x\n", rdaddr, val); |
} else if (0x38 == (sixbits & 0x038)) { // Raw read |
DBGPRINTF("READ-IDLE() -- RAW-READ, nr = %d\n", nr); |
do { |
nr += lclreadcode(&m_buf[nr], 6-nr); |
} while (nr < 6); |