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https://opencores.org/ocsvn/aemb/aemb/trunk
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- from Rev 109 to Rev 110
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Rev 109 → Rev 110
/trunk/sw/cc/aemb/msr.hh
1,4 → 1,4
/* $Id: msr.hh,v 1.2 2008-04-11 11:48:37 sybreon Exp $ |
/* $Id: msr.hh,v 1.3 2008-04-11 12:24:12 sybreon Exp $ |
** |
** AEMB2 HI-PERFORMANCE CPU |
** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net> |
61,39 → 61,39
/** |
Write a value to the MSR register |
@param rmsr value to write |
*/ |
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inline void setMSR(int rmsr) |
{ |
asm volatile ("mts rmsr, %0"::"r"(rmsr)); |
} |
*/ |
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/** |
Enable global interrupts |
*/ |
inline void enableInterrupts() |
{ |
int rmsr = getMSR(); |
rmsr |= MSR_IE; |
setMSR(rmsr); |
inline void setMSR(int rmsr) |
{ |
asm volatile ("mts rmsr, %0"::"r"(rmsr)); |
} |
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/** |
Disable global interrupts |
*/ |
inline void disableInterrupts() |
{ |
int rmsr = getMSR(); |
rmsr &= ~MSR_IE; |
setMSR(rmsr); |
} |
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/** Enable global interrupts */ |
inline void enableInterrupts() { setMSR(getMSR() | MSR_IE); } |
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/** Disable global interrupts */ |
inline void disableInterrupts() { setMSR(getMSR() & ~MSR_IE); } |
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/** Enable data caches */ |
inline void enableDataCache() { setMSR(getMSR() | MSR_DCE); } |
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/** Disable data caches */ |
inline void disableDataCache() { setMSR(getMSR() & ~MSR_DCE); } |
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/** Enable inst caches */ |
inline void enableInstCache() { setMSR(getMSR() | MSR_ICE); } |
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/** Disable inst caches */ |
inline void disableInstCache() { setMSR(getMSR() & ~MSR_ICE); } |
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}; |
#endif |
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/* |
$Log: not supported by cvs2svn $ |
Revision 1.2 2008/04/11 11:48:37 sybreon |
added interrupt controls (may need to be factorised out) |
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Revision 1.1 2008/04/09 19:48:37 sybreon |
Added new C++ files |
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