OpenCores
URL https://opencores.org/ocsvn/ac97/ac97/trunk

Subversion Repositories ac97

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /
    from Rev 11 to Rev 12
    ↔ Reverse comparison
  •

Rev 11 → Rev 12

/trunk/bench/verilog/test_bench_top.v
37,10 → 37,10
 
// CVS Log
//
// $Id: test_bench_top.v,v 1.2 2002-03-05 04:44:04 rudi Exp $
// $Id: test_bench_top.v,v 1.3 2002-03-11 03:21:12 rudi Exp $
//
// $Date: 2002-03-05 04:44:04 $
// $Revision: 1.2 $
// $Date: 2002-03-11 03:21:12 $
// $Revision: 1.3 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
47,6 → 47,11
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.2 2002/03/05 04:44:04 rudi
//
// - Fixed the order of the thrash hold bits to match the spec.
// - Many minor synthesis cleanup items ...
//
// Revision 1.1 2002/02/13 08:22:32 rudi
//
// Added test bench for public release
139,7 → 144,7
reg [31:0] data1;
reg [31:0] data2;
reg [31:0] tmp;
integer size, frames, m;
integer size, frames, m, p;
 
/////////////////////////////////////////////////////////////////////
//
248,6 → 253,50
ic1_ptr = 0;
ic2_ptr = 0;
 
 
oc0_th = 4;
oc1_th = 4;
oc2_th = 4;
oc3_th = 4;
oc4_th = 4;
oc5_th = 4;
ic0_th = 4;
ic1_th = 4;
ic2_th = 4;
 
 
`ifdef AC97_OUT_FIFO_DEPTH_8
oc0_th = oc0_th * 2;
oc1_th = oc1_th * 2;
oc2_th = oc2_th * 2;
oc3_th = oc3_th * 2;
oc4_th = oc4_th * 2;
oc5_th = oc5_th * 2;
`endif
 
`ifdef AC97_OUT_FIFO_DEPTH_16
oc0_th = oc0_th * 4;
oc1_th = oc1_th * 4;
oc2_th = oc2_th * 4;
oc3_th = oc3_th * 4;
oc4_th = oc4_th * 4;
oc5_th = oc5_th * 4;
`endif
 
`ifdef AC97_IN_FIFO_DEPTH_8
ic0_th = ic0_th * 2;
ic1_th = ic1_th * 2;
ic2_th = ic2_th * 2;
`endif
 
`ifdef AC97_IN_FIFO_DEPTH_16
ic0_th = ic0_th * 4;
ic1_th = ic1_th * 4;
ic2_th = ic2_th * 4;
`endif
 
 
 
repeat(48) @(posedge clk);
rst = 1;
repeat(48) @(posedge clk);
758,11 → 807,11
begin
while(wb_busy) @(posedge clk);
wb_busy = 1;
m0.wb_wr4(`OC0, 4'hf, 0, oc0_mem[oc0_ptr+0],
oc0_mem[oc0_ptr+1],
oc0_mem[oc0_ptr+2],
oc0_mem[oc0_ptr+3]);
oc0_ptr = oc0_ptr + 4;
 
for(p=0;p<oc0_th;p=p+1)
m0.wb_wr1(`OC0,4'hf, oc0_mem[oc0_ptr+p] );
oc0_ptr = oc0_ptr + oc0_th;
 
wb_busy = 0;
dma_ack[0] = 1;
@(posedge clk);
775,11 → 824,9
begin
while(wb_busy) @(posedge clk);
wb_busy = 1;
m0.wb_wr4(`OC1, 4'hf, 0, oc1_mem[oc1_ptr+0],
oc1_mem[oc1_ptr+1],
oc1_mem[oc1_ptr+2],
oc1_mem[oc1_ptr+3]);
oc1_ptr = oc1_ptr + 4;
for(p=0;p<oc1_th;p=p+1)
m0.wb_wr1(`OC1,4'hf, oc1_mem[oc1_ptr+p] );
oc1_ptr = oc1_ptr + oc1_th;
wb_busy = 0;
dma_ack[1] = 1;
@(posedge clk);
791,11 → 838,9
begin
while(wb_busy) @(posedge clk);
wb_busy = 1;
m0.wb_wr4(`OC2, 4'hf, 0, oc2_mem[oc2_ptr+0],
oc2_mem[oc2_ptr+1],
oc2_mem[oc2_ptr+2],
oc2_mem[oc2_ptr+3]);
oc2_ptr = oc2_ptr + 4;
for(p=0;p<oc2_th;p=p+1)
m0.wb_wr1(`OC2,4'hf, oc2_mem[oc2_ptr+p] );
oc2_ptr = oc2_ptr + oc2_th;
wb_busy = 0;
dma_ack[2] = 1;
@(posedge clk);
807,11 → 852,9
begin
while(wb_busy) @(posedge clk);
wb_busy = 1;
m0.wb_wr4(`OC3, 4'hf, 0, oc3_mem[oc3_ptr+0],
oc3_mem[oc3_ptr+1],
oc3_mem[oc3_ptr+2],
oc3_mem[oc3_ptr+3]);
oc3_ptr = oc3_ptr + 4;
for(p=0;p<oc3_th;p=p+1)
m0.wb_wr1(`OC3,4'hf, oc3_mem[oc3_ptr+p] );
oc3_ptr = oc3_ptr + oc3_th;
wb_busy = 0;
dma_ack[3] = 1;
@(posedge clk);
823,11 → 866,9
begin
while(wb_busy) @(posedge clk);
wb_busy = 1;
m0.wb_wr4(`OC4, 4'hf, 0, oc4_mem[oc4_ptr+0],
oc4_mem[oc4_ptr+1],
oc4_mem[oc4_ptr+2],
oc4_mem[oc4_ptr+3]);
oc4_ptr = oc4_ptr + 4;
for(p=0;p<oc4_th;p=p+1)
m0.wb_wr1(`OC4,4'hf, oc4_mem[oc4_ptr+p] );
oc4_ptr = oc4_ptr + oc4_th;
wb_busy = 0;
dma_ack[4] = 1;
@(posedge clk);
839,11 → 880,9
begin
while(wb_busy) @(posedge clk);
wb_busy = 1;
m0.wb_wr4(`OC5, 4'hf, 0, oc5_mem[oc5_ptr+0],
oc5_mem[oc5_ptr+1],
oc5_mem[oc5_ptr+2],
oc5_mem[oc5_ptr+3]);
oc5_ptr = oc5_ptr + 4;
for(p=0;p<oc5_th;p=p+1)
m0.wb_wr1(`OC5,4'hf, oc5_mem[oc5_ptr+p] );
oc5_ptr = oc5_ptr + oc5_th;
wb_busy = 0;
dma_ack[5] = 1;
@(posedge clk);
855,11 → 894,9
begin
while(wb_busy) @(posedge clk);
wb_busy = 1;
m0.wb_rd4(`IC0, 4'hf, 0, ic0_mem[ic0_ptr+0],
ic0_mem[ic0_ptr+1],
ic0_mem[ic0_ptr+2],
ic0_mem[ic0_ptr+3]);
ic0_ptr = ic0_ptr + 4;
for(p=0;p<ic0_th;p=p+1)
m0.wb_rd1(`IC0,4'hf, ic0_mem[ic0_ptr+p] );
ic0_ptr = ic0_ptr + ic0_th;
wb_busy = 0;
dma_ack[6] = 1;
@(posedge clk);
871,11 → 908,9
begin
while(wb_busy) @(posedge clk);
wb_busy = 1;
m0.wb_rd4(`IC1, 4'hf, 0, ic1_mem[ic1_ptr+0],
ic1_mem[ic1_ptr+1],
ic1_mem[ic1_ptr+2],
ic1_mem[ic1_ptr+3]);
ic1_ptr = ic1_ptr + 4;
for(p=0;p<ic1_th;p=p+1)
m0.wb_rd1(`IC1,4'hf, ic1_mem[ic1_ptr+p] );
ic1_ptr = ic1_ptr + ic1_th;
wb_busy = 0;
dma_ack[7] = 1;
@(posedge clk);
887,11 → 922,9
begin
while(wb_busy) @(posedge clk);
wb_busy = 1;
m0.wb_rd4(`IC2, 4'hf, 0, ic2_mem[ic2_ptr+0],
ic2_mem[ic2_ptr+1],
ic2_mem[ic2_ptr+2],
ic2_mem[ic2_ptr+3]);
ic2_ptr = ic2_ptr + 4;
for(p=0;p<ic2_th;p=p+1)
m0.wb_rd1(`IC2,4'hf, ic2_mem[ic2_ptr+p] );
ic2_ptr = ic2_ptr + ic2_th;
wb_busy = 0;
dma_ack[8] = 1;
@(posedge clk);
/trunk/bench/verilog/tests.v
37,10 → 37,10
 
// CVS Log
//
// $Id: tests.v,v 1.3 2002-03-05 04:54:08 rudi Exp $
// $Id: tests.v,v 1.4 2002-03-11 03:21:12 rudi Exp $
//
// $Date: 2002-03-05 04:54:08 $
// $Revision: 1.3 $
// $Date: 2002-03-11 03:21:12 $
// $Revision: 1.4 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
47,6 → 47,10
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.3 2002/03/05 04:54:08 rudi
//
// - fixed spelling
//
// Revision 1.2 2002/03/05 04:44:04 rudi
//
// - Fixed the order of the thrash hold bits to match the spec.
174,7 → 178,7
 
end
 
size = frames - 4;
size = frames - 12;
 
for(n=0;n<size;n=n+1)
begin
986,9 → 990,41
m0.wb_wr1(`OCC1,4'hf, 32'h0000_0303);
m0.wb_wr1(`ICC,4'hf, 32'h0003_0303);
end
 
endcase
 
 
`ifdef AC97_OUT_FIFO_DEPTH_8
oc0_th = oc0_th * 2;
oc1_th = oc1_th * 2;
oc2_th = oc2_th * 2;
oc3_th = oc3_th * 2;
oc4_th = oc4_th * 2;
oc5_th = oc5_th * 2;
`endif
 
`ifdef AC97_OUT_FIFO_DEPTH_16
oc0_th = oc0_th * 4;
oc1_th = oc1_th * 4;
oc2_th = oc2_th * 4;
oc3_th = oc3_th * 4;
oc4_th = oc4_th * 4;
oc5_th = oc5_th * 4;
`endif
 
 
 
`ifdef AC97_IN_FIFO_DEPTH_8
ic0_th = ic0_th * 2;
ic1_th = ic1_th * 2;
ic2_th = ic2_th * 2;
`endif
 
`ifdef AC97_IN_FIFO_DEPTH_16
ic0_th = ic0_th * 4;
ic1_th = ic1_th * 4;
ic2_th = ic2_th * 4;
`endif
 
wb_busy = 0;
 
oc0_dma_en = 0;
/trunk/rtl/verilog/ac97_in_fifo.v
38,10 → 38,10
 
// CVS Log
//
// $Id: ac97_in_fifo.v,v 1.2 2002-03-05 04:44:05 rudi Exp $
// $Id: ac97_in_fifo.v,v 1.3 2002-03-11 03:21:22 rudi Exp $
//
// $Date: 2002-03-05 04:44:05 $
// $Revision: 1.2 $
// $Date: 2002-03-11 03:21:22 $
// $Revision: 1.3 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
48,6 → 48,11
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.2 2002/03/05 04:44:05 rudi
//
// - Fixed the order of the thrash hold bits to match the spec.
// - Many minor synthesis cleanup items ...
//
// Revision 1.1 2001/08/03 06:54:50 rudi
//
//
62,6 → 67,10
 
`include "ac97_defines.v"
 
`ifdef AC97_IN_FIFO_DEPTH_4
 
// 4 entry deep verion of the input FIFO
 
module ac97_in_fifo(clk, rst, en, mode, din, we, dout, re, status, full, empty);
 
input clk, rst;
115,7 → 124,7
if(re) rp <= #1 rp + 3'h1;
 
always @(posedge clk)
status <= #1 ((rp - wp[2:1]) - 2'h1);
status <= #1 ((rp[1:0] - wp[2:1]) - 2'h1);
 
always @(posedge clk)
empty <= #1 (wp[3:1] == rp[2:0]) & (m16b ? !wp[0] : 1'b0);
133,9 → 142,9
 
always @(mode or din_tmp1 or din)
case(mode) // synopsys parallel_case full_case
0: din_tmp = {din[19:4], din_tmp1}; // 16 Bit Output
1: din_tmp = {13'h0, din[17:0]}; // 18 bit Output
2: din_tmp = {11'h0, din[19:0]}; // 20 Bit Output
2'h0: din_tmp = {din[19:4], din_tmp1}; // 16 Bit Output
2'h1: din_tmp = {13'h0, din[17:0]}; // 18 bit Output
2'h2: din_tmp = {11'h0, din[19:0]}; // 20 Bit Output
endcase
 
always @(posedge clk)
142,3 → 151,180
if(we & (!m16b | (m16b & wp[0]) ) ) mem[ wp[2:1] ] <= #1 din_tmp;
 
endmodule
 
`endif
 
`ifdef AC97_IN_FIFO_DEPTH_8
 
// 8 entry deep verion of the input FIFO
 
module ac97_in_fifo(clk, rst, en, mode, din, we, dout, re, status, full, empty);
 
input clk, rst;
input en;
input [1:0] mode;
input [19:0] din;
input we;
output [31:0] dout;
input re;
output [1:0] status;
output full;
output empty;
 
 
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
 
reg [31:0] mem[0:7];
reg [31:0] dout;
 
reg [4:0] wp;
reg [3:0] rp;
 
wire [4:0] wp_p1;
 
reg [1:0] status;
reg [15:0] din_tmp1;
reg [31:0] din_tmp;
wire m16b;
reg full, empty;
 
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
 
assign m16b = (mode == 2'h0); // 16 Bit Mode
 
always @(posedge clk)
if(!en) wp <= #1 5'h0;
else
if(we) wp <= #1 wp_p1;
 
assign wp_p1 = m16b ? (wp + 5'h1) : (wp + 5'h2);
 
always @(posedge clk)
if(!en) rp <= #1 4'h0;
else
if(re) rp <= #1 rp + 4'h1;
 
always @(posedge clk)
status <= #1 ((rp[2:1] - wp[3:2]) - 2'h1);
 
always @(posedge clk)
empty <= #1 (wp[4:1] == rp[3:0]) & (m16b ? !wp[0] : 1'b0);
 
always @(posedge clk)
full <= #1 (wp[3:1] == rp[2:0]) & (wp[4] != rp[3]);
 
// Fifo Output
always @(posedge clk)
dout <= #1 mem[ rp[2:0] ];
 
// Fifo Input Half Word Latch
always @(posedge clk)
if(we & !wp[0]) din_tmp1 <= #1 din[19:4];
 
always @(mode or din_tmp1 or din)
case(mode) // synopsys parallel_case full_case
2'h0: din_tmp = {din[19:4], din_tmp1}; // 16 Bit Output
2'h1: din_tmp = {13'h0, din[17:0]}; // 18 bit Output
2'h2: din_tmp = {11'h0, din[19:0]}; // 20 Bit Output
endcase
 
always @(posedge clk)
if(we & (!m16b | (m16b & wp[0]) ) ) mem[ wp[3:1] ] <= #1 din_tmp;
 
endmodule
 
`endif
 
 
`ifdef AC97_IN_FIFO_DEPTH_16
 
// 16 entry deep verion of the input FIFO
 
module ac97_in_fifo(clk, rst, en, mode, din, we, dout, re, status, full, empty);
 
input clk, rst;
input en;
input [1:0] mode;
input [19:0] din;
input we;
output [31:0] dout;
input re;
output [1:0] status;
output full;
output empty;
 
 
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
 
reg [31:0] mem[0:15];
reg [31:0] dout;
 
reg [5:0] wp;
reg [4:0] rp;
 
wire [5:0] wp_p1;
 
reg [1:0] status;
reg [15:0] din_tmp1;
reg [31:0] din_tmp;
wire m16b;
reg full, empty;
 
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
 
assign m16b = (mode == 2'h0); // 16 Bit Mode
 
always @(posedge clk)
if(!en) wp <= #1 6'h0;
else
if(we) wp <= #1 wp_p1;
 
assign wp_p1 = m16b ? (wp + 6'h1) : (wp + 6'h2);
 
always @(posedge clk)
if(!en) rp <= #1 5'h0;
else
if(re) rp <= #1 rp + 5'h1;
 
always @(posedge clk)
status <= #1 ((rp[3:2] - wp[4:3]) - 2'h1);
 
always @(posedge clk)
empty <= #1 (wp[5:1] == rp[4:0]) & (m16b ? !wp[0] : 1'b0);
 
always @(posedge clk)
full <= #1 (wp[4:1] == rp[3:0]) & (wp[5] != rp[4]);
 
// Fifo Output
always @(posedge clk)
dout <= #1 mem[ rp[3:0] ];
 
// Fifo Input Half Word Latch
always @(posedge clk)
if(we & !wp[0]) din_tmp1 <= #1 din[19:4];
 
always @(mode or din_tmp1 or din)
case(mode) // synopsys parallel_case full_case
2'h0: din_tmp = {din[19:4], din_tmp1}; // 16 Bit Output
2'h1: din_tmp = {13'h0, din[17:0]}; // 18 bit Output
2'h2: din_tmp = {11'h0, din[19:0]}; // 20 Bit Output
endcase
 
always @(posedge clk)
if(we & (!m16b | (m16b & wp[0]) ) ) mem[ wp[4:1] ] <= #1 din_tmp;
 
endmodule
 
`endif
/trunk/rtl/verilog/ac97_out_fifo.v
38,10 → 38,10
 
// CVS Log
//
// $Id: ac97_out_fifo.v,v 1.2 2002-03-05 04:44:05 rudi Exp $
// $Id: ac97_out_fifo.v,v 1.3 2002-03-11 03:21:22 rudi Exp $
//
// $Date: 2002-03-05 04:44:05 $
// $Revision: 1.2 $
// $Date: 2002-03-11 03:21:22 $
// $Revision: 1.3 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
62,6 → 62,10
 
`include "ac97_defines.v"
 
`ifdef AC97_OUT_FIFO_DEPTH_4
 
// 4 Entry Deep version of the Output FIFO
 
module ac97_out_fifo(clk, rst, en, mode, din, we, dout, re, status, full, empty);
 
input clk, rst;
137,9 → 141,9
else
if(re)
case(mode) // synopsys parallel_case full_case
0: dout <= #1 {dout_tmp1, 4'h0}; // 16 Bit Output
1: dout <= #1 {dout_tmp[17:0], 2'h0}; // 18 bit Output
2: dout <= #1 dout_tmp[19:0]; // 20 Bit Output
2'h0: dout <= #1 {dout_tmp1, 4'h0}; // 16 Bit Output
2'h1: dout <= #1 {dout_tmp[17:0], 2'h0}; // 18 bit Output
2'h2: dout <= #1 dout_tmp[19:0]; // 20 Bit Output
endcase
 
always @(posedge clk)
147,3 → 151,189
 
endmodule
 
`endif
 
`ifdef AC97_OUT_FIFO_DEPTH_8
 
// 8 Entry Deep version of the Output FIFO
 
module ac97_out_fifo(clk, rst, en, mode, din, we, dout, re, status, full, empty);
 
input clk, rst;
input en;
input [1:0] mode;
input [31:0] din;
input we;
output [19:0] dout;
input re;
output [1:0] status;
output full;
output empty;
 
 
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
 
reg [31:0] mem[0:7];
 
reg [3:0] wp;
reg [4:0] rp;
 
wire [3:0] wp_p1;
 
reg [1:0] status;
reg [19:0] dout;
wire [31:0] dout_tmp;
wire [15:0] dout_tmp1;
wire m16b;
reg empty;
 
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
 
assign m16b = (mode == 2'h0); // 16 Bit Mode
 
always @(posedge clk)
if(!en) wp <= #1 4'h0;
else
if(we) wp <= #1 wp_p1;
 
assign wp_p1 = wp + 4'h1;
 
always @(posedge clk)
if(!en) rp <= #1 5'h0;
else
if(re & m16b) rp <= #1 rp + 5'h1;
else
if(re & !m16b) rp <= #1 rp + 5'h2;
 
always @(posedge clk)
status <= #1 (wp[2:1] - rp[3:2]) - 2'h1;
 
wire [4:0] rp_p1 = rp[4:0] + 5'h1;
 
always @(posedge clk)
empty <= #1 (rp_p1[4:1] == wp[3:0]) & (m16b ? rp_p1[0] : 1'b1);
 
assign full = (wp[2:0] == rp[3:1]) & (wp[3] != rp[4]);
 
// Fifo Output
assign dout_tmp = mem[ rp[3:1] ];
 
// Fifo Output Half Word Select
assign dout_tmp1 = rp[0] ? dout_tmp[31:16] : dout_tmp[15:0];
 
always @(posedge clk)
if(!en) dout <= #1 20'h0;
else
if(re)
case(mode) // synopsys parallel_case full_case
2'h0: dout <= #1 {dout_tmp1, 4'h0}; // 16 Bit Output
2'h1: dout <= #1 {dout_tmp[17:0], 2'h0}; // 18 bit Output
2'h2: dout <= #1 dout_tmp[19:0]; // 20 Bit Output
endcase
 
 
always @(posedge clk)
if(we) mem[wp[2:0]] <= #1 din;
 
endmodule
 
`endif
 
 
`ifdef AC97_OUT_FIFO_DEPTH_16
 
// 16 Entry Deep version of the Output FIFO
 
module ac97_out_fifo(clk, rst, en, mode, din, we, dout, re, status, full, empty);
 
input clk, rst;
input en;
input [1:0] mode;
input [31:0] din;
input we;
output [19:0] dout;
input re;
output [1:0] status;
output full;
output empty;
 
 
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
 
reg [31:0] mem[0:15];
 
reg [4:0] wp;
reg [5:0] rp;
 
wire [4:0] wp_p1;
 
reg [1:0] status;
reg [19:0] dout;
wire [31:0] dout_tmp;
wire [15:0] dout_tmp1;
wire m16b;
reg empty;
 
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
 
assign m16b = (mode == 2'h0); // 16 Bit Mode
 
always @(posedge clk)
if(!en) wp <= #1 5'h0;
else
if(we) wp <= #1 wp_p1;
 
assign wp_p1 = wp + 4'h1;
 
always @(posedge clk)
if(!en) rp <= #1 6'h0;
else
if(re & m16b) rp <= #1 rp + 6'h1;
else
if(re & !m16b) rp <= #1 rp + 6'h2;
 
always @(posedge clk)
status <= #1 (wp[3:2] - rp[4:3]) - 2'h1;
 
wire [5:0] rp_p1 = rp[5:0] + 6'h1;
 
always @(posedge clk)
empty <= #1 (rp_p1[5:1] == wp[4:0]) & (m16b ? rp_p1[0] : 1'b1);
 
assign full = (wp[3:0] == rp[4:1]) & (wp[4] != rp[5]);
 
// Fifo Output
assign dout_tmp = mem[ rp[4:1] ];
 
// Fifo Output Half Word Select
assign dout_tmp1 = rp[0] ? dout_tmp[31:16] : dout_tmp[15:0];
 
always @(posedge clk)
if(!en) dout <= #1 20'h0;
else
if(re)
case(mode) // synopsys parallel_case full_case
2'h0: dout <= #1 {dout_tmp1, 4'h0}; // 16 Bit Output
2'h1: dout <= #1 {dout_tmp[17:0], 2'h0}; // 18 bit Output
2'h2: dout <= #1 dout_tmp[19:0]; // 20 Bit Output
endcase
 
 
always @(posedge clk)
if(we) mem[wp[3:0]] <= #1 din;
 
endmodule
 
`endif
/trunk/rtl/verilog/ac97_defines.v
37,10 → 37,10
 
// CVS Log
//
// $Id: ac97_defines.v,v 1.3 2002-03-05 04:44:05 rudi Exp $
// $Id: ac97_defines.v,v 1.4 2002-03-11 03:21:22 rudi Exp $
//
// $Date: 2002-03-05 04:44:05 $
// $Revision: 1.3 $
// $Date: 2002-03-11 03:21:22 $
// $Revision: 1.4 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
47,6 → 47,11
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.3 2002/03/05 04:44:05 rudi
//
// - Fixed the order of the thrash hold bits to match the spec.
// - Many minor synthesis cleanup items ...
//
// Revision 1.2 2001/08/10 08:09:42 rudi
//
// - Removed RTY_O output.
134,3 → 139,26
// For a 200 MHz WISHBONE clock this would be about (163/5) 33 cycles.
`define AC97_SUSP_DET 6'h21
 
/////////////////////////////////////////////////////////////////////
//
// Select FIFO Depth. For most applications a FIFO depth of 4 should
// be sufficient. For systems with slow interrupt processing or slow
// DMA response or systems with low internal bus bandwidth you might
// want to increase the FIFO sizes to reduce the interrupt/DMA service
// request frequencies.
// Service request frequency can be calculated as follows:
// Channel bandwidth / FIFO size = Service Request Frequency
// For Example: 48KHz / 4 = 12 kHz
//
// Select Input FIFO depth by uncommenting ONE of the following define
// statements:
`define AC97_IN_FIFO_DEPTH_4
//`define AC97_IN_FIFO_DEPTH_8
//`define AC97_IN_FIFO_DEPTH_16
//
// Select Output FIFO depth by uncommenting ONE of the following define
// statements:
`define AC97_OUT_FIFO_DEPTH_4
//`define AC97_OUT_FIFO_DEPTH_8
//`define AC97_OUT_FIFO_DEPTH_16
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.