OpenCores
URL https://opencores.org/ocsvn/alternascope/alternascope/trunk

Subversion Repositories alternascope

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Rev 11 → Rev 12

/trunk/d_TopLevel.v
1,6 → 1,6
//==================================================================//
// File: d_TopLevel.v //
// Version: 0.0.0.2 //
// Version: 0.0.0.3 //
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -//
// Copyright (C) Stephen Pickett //
// Jun 08, 2005 //
25,6 → 25,7
// Revisions: //
// Ver 0.0.0.1 Apr , 2005 Under Development //
// Ver 0.0.0.2 Jun 08, 2005 Updates //
// Ver 0.0.0.3 Jun 19, 2005 Added Character Display //
// //
//==================================================================//
 
99,25 → 100,50
 
wire VGA_RAM_ACCESS_OK;
wire CLK_50MHZ, CLK_64MHZ, CLK180_64MHZ;
reg CLK_VGA;
wire[6:0] SEG_OUT;
wire[3:0] SEG_SEL;
 
wire[7:0] data_charRamRead;
reg[7:0] data_charRamRead_buf;
wire[7:0] mask_charMap;
reg[7:0] mask_charMap_buf;
 
always @ (posedge CLK_50MHZ) begin
if(R_BUTTON) begin
data_charRamRead_buf <= data_charRamRead_buf;
mask_charMap_buf <= mask_charMap_buf;
end else begin
data_charRamRead_buf <= data_charRamRead;
mask_charMap_buf <= mask_charMap;
end
end
 
sub_SegDriver segs(
.CLK_50MHZ(CLK_50MHZ), .MASTER_RST(MASTER_RST),
.DATA_IN(),
.DATA_IN(data_charRamRead_buf),
.SEG_OUT(SEG_OUT), .SEG_SEL(SEG_SEL)
);
 
wire[7:0] leds;
assign leds[0] = L_BUTTON;
assign leds[1] = M_BUTTON;
assign leds[2] = R_BUTTON;
assign leds[3] = 1'b0;
assign leds[7:4] = 4'b0;
assign leds = mask_charMap_buf;
 
//==================================================================//
// SUBROUTINES //
//==================================================================//
//wire CLK_50MHZ, CLK_64MHZ, CLK180_64MHZ;
//d_DCM_VGA clock_gen_VGA (
// .CLKIN_IN(CLK_50MHZ_IN),
// .RST_IN(MASTER_RST),
// .CLKFX_OUT(CLK_VGA),
// .CLKIN_IBUFG_OUT(CLK_50MHZ_B),
// .LOCKED_OUT(CLK_VGA_LOCKED)
// );
 
always @ (posedge CLK_50MHZ or posedge MASTER_RST)
if(MASTER_RST) CLK_VGA <= 1'b0;
else CLK_VGA <= ~CLK_VGA;
 
 
wire CLK_64MHZ_LOCKED;
d_DCM clock_generator(
.CLKIN_IN(CLK_50MHZ_IN),
163,6 → 189,21
 
 
 
//------------------------------------------------------------------//
// VGA //
//------------------------------------------------------------------//
wire[9:0] HCNT, VCNT;
wire[2:0] RGB_CHAR;
 
 
CharacterDisplay charTest(
.MASTER_CLK(CLK_50MHZ), .MASTER_RST(MASTER_RST),
.CLK_VGA(CLK_VGA), .HCNT(HCNT), .VCNT(VCNT),
.RGB_OUT(RGB_CHAR),
.data_charMap(mask_charMap), .data_charRamRead(data_charRamRead)
);
 
 
//wire[17:0] VGA_RAM_ADDRESS_w;
//wire[15:0] VGA_RAM_DATA_w;
wire VGA_RAM_OE_w, VGA_RAM_WE_w, VGA_RAM_CS_w;
188,6 → 229,7
 
Driver_VGA driver_VGA(
.CLK_50MHZ(CLK_50MHZ), .MASTER_RST(MASTER_RST),
.CLK_VGA(CLK_VGA),
.H_SYNC(H_SYNC), .V_SYNC(V_SYNC), .VGA_OUTPUT(VGA_OUTPUT),
.XCOORD(XCOORD), .YCOORD(YCOORD),
.VGA_RAM_DATA(VGA_RAM_DATA), .VGA_RAM_ADDR(VGA_RAM_ADDRESS_r),
194,7 → 236,9
.VGA_RAM_OE(VGA_RAM_OE_r), .VGA_RAM_WE(VGA_RAM_WE_r), .VGA_RAM_CS(VGA_RAM_CS_r),
.VGA_RAM_ACCESS_OK(VGA_RAM_ACCESS_OK),
.TRIGGER_LEVEL(TRIGGER_LEVEL[8:0]),
.SHOW_LEVELS(SHOW_LEVELS_BUTTON)
.SHOW_LEVELS(SHOW_LEVELS_BUTTON),
.HCNT(HCNT), .VCNT(VCNT),
.RGB_CHAR(RGB_CHAR)
);
 
 
/trunk/Mouse/.#d_DriverMouse.v.1.1
0,0 → 1,359
//==================================================================
// File: d_MouseDriver.v
// Version: 0.01
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// Copyright Stephen Pickett
// April 28, 2005
//------------------------------------------------------------------
// Revisions:
// Ver 0.01 Apr 28, 2005 Initial Release
//
//==================================================================
 
module Driver_mouse(
CLK_50MHZ, MASTER_RST,
PS2C, PS2D,
XCOORD, YCOORD,
L_BUTTON, R_BUTTON, M_BUTTON
);
//==================================================================//
// DEFINITIONS //
//==================================================================//
parameter ss_CLK_LOW_100US = 4'b0000;
parameter ss_DATA_LOW = 4'b0001;
parameter ss_SET_BIT_0 = 4'b0011;
parameter ss_SET_BIT_1 = 4'b0010;
parameter ss_SET_BIT_2 = 4'b0110;
parameter ss_SET_BIT_3 = 4'b0111;
parameter ss_SET_BIT_4 = 4'b0101;
parameter ss_SET_BIT_5 = 4'b0100;
parameter ss_SET_BIT_6 = 4'b1100;
parameter ss_SET_BIT_7 = 4'b1101;
parameter ss_SET_BIT_PARITY = 4'b1111;
parameter ss_SET_BIT_STOP = 4'b1110;
parameter ss_WAIT_BIT_ACK = 4'b1010;
parameter ss_GET_MOVEMENT = 4'b1000;
 
parameter P_Lbut_index = 1;
parameter P_Mbut_index = 2;
parameter P_Rbut_index = 3;
 
//==================================================================//
// VARIABLE DEFINITIONS //
//==================================================================//
//----------------------//
// INPUTS //
//----------------------//
input CLK_50MHZ; // System wide clock
input MASTER_RST; // System wide reset
inout PS2C; // PS2 clock
inout PS2D; // PS2 data
 
//----------------------//
// OUTPUTS //
//----------------------//
output[11:0] XCOORD; // X coordinate of the cursor
output[11:0] YCOORD; // Y coordinate of the cursor
output L_BUTTON, R_BUTTON, M_BUTTON;
 
//----------------------//
// WIRES / NODES //
//----------------------//
wire CLK_50MHZ, MASTER_RST;
wire PS2C, PS2D;
reg[11:0] XCOORD;
reg[11:0] YCOORD;
reg L_BUTTON, R_BUTTON, M_BUTTON;
 
//----------------------//
// REGISTERS //
//----------------------//
reg[12:0] Counter_timer;
reg[5:0] Counter_bits;
reg[3:0] sm_ps2mouse;
reg[32:0] data_in_buf;
 
 
 
 
//==================================================================//
// FUNCTIONAL DEFINITIONS //
//==================================================================//
 
//------------------------------------------------------------------//
// INTERMEDIATE VALUES //
//------------------------------------------------------------------//
reg[7:0] Counter_PS2C;
reg CLK_ps2c_debounced;
 
// Debounce the PS2C line.
// The mouse is generally not outputting a nice rising clock edge.
// To eliminate the false edge detection, make sure it is high/low
// for at least 256 counts before triggering the CLK.
always @ (posedge CLK_50MHZ or posedge MASTER_RST) begin
if(MASTER_RST == 1'b1) begin
Counter_PS2C <= 8'b0;
end else begin
if(PS2C == 1'b1) begin
if(Counter_PS2C == 8'hFF)
Counter_PS2C <= Counter_PS2C;
else
Counter_PS2C <= Counter_PS2C + 1;
end else begin
if(Counter_PS2C == 8'b0)
Counter_PS2C <= Counter_PS2C;
else
Counter_PS2C <= Counter_PS2C - 1;
end
end
end
 
always @ (posedge CLK_50MHZ or posedge MASTER_RST) begin
if(MASTER_RST == 1'b1)
CLK_ps2c_debounced <= 1'b0;
else if(Counter_PS2C == 8'b0)
CLK_ps2c_debounced <= 1'b0;
else if(Counter_PS2C == 8'hFF)
CLK_ps2c_debounced <= 1'b1;
else
CLK_ps2c_debounced <= CLK_ps2c_debounced;
end
 
 
//------------------------------------------------------------------//
// INTERPRETING MOVEMENTS //
//------------------------------------------------------------------//
reg[7:0] xcoord_buf;
reg[7:0] ycoord_buf;
 
always @ (posedge CLK_50MHZ or posedge MASTER_RST) begin
if(MASTER_RST == 1'b1) begin
xcoord_buf <= 8'b0;
end else if(data_in_buf[5] == 1'b0) begin
xcoord_buf <= data_in_buf[19:12];
end else begin
xcoord_buf <= ((~(data_in_buf[19:12]))+1);
end
end
 
always @ (posedge CLK_50MHZ or posedge MASTER_RST) begin
if(MASTER_RST == 1'b1) begin
ycoord_buf <= 8'b0;
end else if(data_in_buf[6] == 1'b0) begin
ycoord_buf <= data_in_buf[30:23];
end else begin
ycoord_buf <= ((~(data_in_buf[30:23]))+1);
end
end
 
 
always @ (posedge CLK_ps2c_debounced or posedge MASTER_RST) begin
if(MASTER_RST == 1'b1) begin
XCOORD <= 12'd320;
end else if(Counter_bits == 6'd32 && (data_in_buf[7] == 1'b0)) begin
if(data_in_buf[5] == 1'b1) begin // NEGITIVE
if(XCOORD <= xcoord_buf)
XCOORD <= 12'b0;
else
XCOORD <= XCOORD - xcoord_buf;
end else begin // POSITIVE
if((XCOORD + xcoord_buf) >= 11'd639)
XCOORD <= 12'd639;
else
XCOORD <= XCOORD + xcoord_buf;
end
end else begin
XCOORD <= XCOORD;
end
end
 
always @ (posedge CLK_ps2c_debounced or posedge MASTER_RST) begin
if(MASTER_RST == 1'b1) begin
YCOORD <= 12'd100;
end else if(Counter_bits == 6'd32 && (data_in_buf[8] == 1'b0)) begin
if(data_in_buf[6] == 1'b1) begin // POSITIVE
if((YCOORD + ycoord_buf) >= 11'd479)
YCOORD <= 12'd479;
else
YCOORD <= YCOORD + ycoord_buf;
end else begin // POSITIVE
if(YCOORD <= ycoord_buf)
YCOORD <= 12'd0;
else
YCOORD <= YCOORD - ycoord_buf;
end
end else begin
YCOORD <= YCOORD;
end
end
 
//------------------------------------------------------------------//
// INTERPRETING BUTTONS //
//------------------------------------------------------------------//
always @ (posedge CLK_50MHZ or posedge MASTER_RST) begin
if(MASTER_RST == 1'b1) begin
L_BUTTON <= 1'b0;
M_BUTTON <= 1'b0;
R_BUTTON <= 1'b0;
end else if(Counter_bits == 6'd32) begin
L_BUTTON <= data_in_buf[P_Lbut_index];
M_BUTTON <= data_in_buf[P_Mbut_index];
R_BUTTON <= data_in_buf[P_Rbut_index];
end else begin
L_BUTTON <= L_BUTTON;
M_BUTTON <= M_BUTTON;
R_BUTTON <= R_BUTTON;
end
end
 
 
//------------------------------------------------------------------//
// SENDING DATA //
//------------------------------------------------------------------//
reg PS2C_out, PS2D_out;
 
assign PS2C = PS2C_out;
assign PS2D = PS2D_out;
 
always @ (Counter_timer or MASTER_RST) begin
if(MASTER_RST == 1'b1) begin
PS2C_out = 1'bZ;
end else if((Counter_timer <= 13'd5500) && (MASTER_RST == 1'b0))
PS2C_out = 1'b0;
else
PS2C_out = 1'bZ;
end
 
always @ (sm_ps2mouse or Counter_timer or MASTER_RST) begin
if(MASTER_RST == 1'b1) begin
PS2D_out = 1'bZ;
end else if(Counter_timer >= 13'd5000 && sm_ps2mouse == ss_DATA_LOW) begin
PS2D_out = 1'b0;
end else if(sm_ps2mouse == ss_SET_BIT_0) begin
PS2D_out = 1'b0;
end else if(sm_ps2mouse == ss_SET_BIT_1) begin
PS2D_out = 1'b0;
end else if(sm_ps2mouse == ss_SET_BIT_2) begin
PS2D_out = 1'b1;
end else if(sm_ps2mouse == ss_SET_BIT_3) begin
PS2D_out = 1'b0;
end else if(sm_ps2mouse == ss_SET_BIT_4) begin
PS2D_out = 1'b1;
end else if(sm_ps2mouse == ss_SET_BIT_5) begin
PS2D_out = 1'b1;
end else if(sm_ps2mouse == ss_SET_BIT_6) begin
PS2D_out = 1'b1;
end else if(sm_ps2mouse == ss_SET_BIT_7) begin
PS2D_out = 1'b1;
end else if(sm_ps2mouse == ss_SET_BIT_PARITY) begin
PS2D_out = 1'b0;
end else if(sm_ps2mouse == ss_SET_BIT_STOP) begin
PS2D_out = 1'b1;
end else begin
PS2D_out = 1'bZ;
end
end
 
//------------------------------------------------------------------//
// RECIEVING DATA //
//------------------------------------------------------------------//
always @ (negedge CLK_ps2c_debounced or posedge MASTER_RST) begin
if(MASTER_RST == 1'b1) begin
data_in_buf <= 33'b0;
end else if(sm_ps2mouse == ss_GET_MOVEMENT) begin
data_in_buf <= data_in_buf >> 1;
data_in_buf[32] <= PS2D;
end else
data_in_buf <= data_in_buf;
end
 
 
 
//------------------------------------------------------------------//
// COUNTERS FOR STATE MACHINE //
//------------------------------------------------------------------//
// COUNTER: timer
always @ (posedge CLK_50MHZ or posedge MASTER_RST) begin
if(MASTER_RST == 1'b1)
Counter_timer <= 13'b0;
else if(Counter_timer == 13'd6000)
Counter_timer <= Counter_timer;
else
Counter_timer <= Counter_timer + 1;
end
 
// COUNTER: rec_data_bit_cnt
always @ (negedge CLK_ps2c_debounced or posedge MASTER_RST) begin
if(MASTER_RST == 1'b1) begin
Counter_bits <= 6'd22;
end else if(sm_ps2mouse == ss_GET_MOVEMENT) begin
if(Counter_bits == 6'd32)
Counter_bits <= 6'd0;
else
Counter_bits <= Counter_bits + 1;
end else begin
Counter_bits <= Counter_bits;
end
end
 
 
//------------------------------------------------------------------//
// MOUSE STATE MACHINE //
//------------------------------------------------------------------//
always @ (negedge CLK_ps2c_debounced or posedge MASTER_RST) begin
if(MASTER_RST == 1'b1) begin
sm_ps2mouse <= ss_DATA_LOW;
end else if(sm_ps2mouse == ss_DATA_LOW) begin
sm_ps2mouse <= ss_SET_BIT_0;
end else if(sm_ps2mouse == ss_SET_BIT_0) begin
sm_ps2mouse <= ss_SET_BIT_1;
end else if(sm_ps2mouse == ss_SET_BIT_1) begin
sm_ps2mouse <= ss_SET_BIT_2;
end else if(sm_ps2mouse == ss_SET_BIT_2) begin
sm_ps2mouse <= ss_SET_BIT_3;
end else if(sm_ps2mouse == ss_SET_BIT_3) begin
sm_ps2mouse <= ss_SET_BIT_4;
end else if(sm_ps2mouse == ss_SET_BIT_4) begin
sm_ps2mouse <= ss_SET_BIT_5;
end else if(sm_ps2mouse == ss_SET_BIT_5) begin
sm_ps2mouse <= ss_SET_BIT_6;
end else if(sm_ps2mouse == ss_SET_BIT_6) begin
sm_ps2mouse <= ss_SET_BIT_7;
end else if(sm_ps2mouse == ss_SET_BIT_7) begin
sm_ps2mouse <= ss_SET_BIT_PARITY;
end else if(sm_ps2mouse == ss_SET_BIT_PARITY) begin
sm_ps2mouse <= ss_SET_BIT_STOP;
end else if(sm_ps2mouse == ss_SET_BIT_STOP) begin
sm_ps2mouse <= ss_WAIT_BIT_ACK;
end else if(sm_ps2mouse == ss_WAIT_BIT_ACK) begin
sm_ps2mouse <= ss_GET_MOVEMENT;
end else if(sm_ps2mouse == ss_GET_MOVEMENT) begin
sm_ps2mouse <= sm_ps2mouse;
end else begin
sm_ps2mouse <= ss_DATA_LOW;
end
end
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
endmodule
 
/trunk/Mouse/d_DriverMouse.v
171,14 → 171,14
 
always @ (posedge CLK_ps2c_debounced or posedge MASTER_RST) begin
if(MASTER_RST == 1'b1) begin
YCOORD <= 12'd100;
YCOORD <= 12'd199;
end else if(Counter_bits == 6'd32 && (data_in_buf[8] == 1'b0)) begin
if(data_in_buf[6] == 1'b1) begin // POSITIVE
if(data_in_buf[6] == 1'b0) begin
if((YCOORD + ycoord_buf) >= 11'd479)
YCOORD <= 12'd479;
else
YCOORD <= YCOORD + ycoord_buf;
end else begin // POSITIVE
end else begin
if(YCOORD <= ycoord_buf)
YCOORD <= 12'd0;
else
/trunk/VGA/d_VGAdriver.v
25,11 → 25,14
// Revisions: //
// Ver 0.0.0.1 Apr 28, 2005 Under Development //
// 0.0.0.2 Jun 09, 2005 Cleaning //
// 0.0.0.3 Jun 10, 2005 Re-structuerd the VCNT and HCNT //
// so they line up with the PXLs. //
// //
//==================================================================//
 
module Driver_VGA(
CLK_50MHZ, MASTER_RST,
CLK_VGA,
VGA_RAM_DATA, VGA_RAM_ADDR,
VGA_RAM_OE, VGA_RAM_WE, VGA_RAM_CS,
VGA_RAM_ACCESS_OK,
36,7 → 39,9
H_SYNC, V_SYNC, VGA_OUTPUT,
XCOORD, YCOORD, ram_vshift,
TRIGGER_LEVEL,
SHOW_LEVELS
SHOW_LEVELS,
HCNT, VCNT,
RGB_CHAR
);
//==================================================================//
56,6 → 61,7
//----------------------//
input CLK_50MHZ; // System wide clock
input MASTER_RST; // System wide reset
input CLK_VGA;
output H_SYNC; // The H_SYNC timing signal to the VGA monitor
output V_SYNC; // The V_SYNC timing signal to the VGA monitor
output[2:0] VGA_OUTPUT; // The 3-bit VGA output
66,11 → 72,14
output VGA_RAM_ACCESS_OK;
input[8:0] TRIGGER_LEVEL;
input SHOW_LEVELS;
output[9:0] HCNT, VCNT;
input[2:0] RGB_CHAR;
 
output[15:0] ram_vshift;
 
 
 
 
//----------------------//
// WIRES / NODES //
//----------------------//
77,6 → 86,7
reg H_SYNC, V_SYNC;
reg [2:0] VGA_OUTPUT;
wire CLK_50MHZ, MASTER_RST;
wire CLK_VGA;
wire[11:0] XCOORD, YCOORD;
wire[15:0] VGA_RAM_DATA;
reg[17:0] VGA_RAM_ADDR;
84,12 → 94,15
reg VGA_RAM_ACCESS_OK;
wire[8:0] TRIGGER_LEVEL;
wire SHOW_LEVELS;
wire[9:0] HCNT, VCNT;
wire[2:0] RGB_CHAR;
 
 
//----------------------//
// REGISTERS //
//----------------------//
reg CLK_25MHZ; // General system clock for VGA timing
//reg CLK_25MHZ; // General system clock for VGA timing
wire CLK_25MHZ = CLK_VGA;
reg [9:0] hcnt; // Counter - generates the H_SYNC signal
reg [9:0] vcnt; // Counter - counts the H_SYNC pulses to generate V_SYNC signal
reg[2:0] vga_out;
97,15 → 110,17
//==================================================================//
// FUNCTIONAL DEFINITIONS //
//==================================================================//
assign HCNT = hcnt;
assign VCNT = vcnt;
 
//------------------------------------------------------------------//
// CLOCK FUNCTIONS //
//------------------------------------------------------------------//
always @ (posedge CLK_50MHZ or posedge MASTER_RST)
if (MASTER_RST == 1'b1)
CLK_25MHZ <= 1'b0;
else
CLK_25MHZ <= ~CLK_25MHZ;
//always @ (posedge CLK_50MHZ or posedge MASTER_RST)
// if (MASTER_RST == 1'b1)
// CLK_25MHZ <= 1'b0;
// else
// CLK_25MHZ <= ~CLK_25MHZ;
 
 
//------------------------------------------------------------------//
114,13 → 129,13
always @ (posedge CLK_25MHZ or posedge MASTER_RST) begin
if (MASTER_RST == 1'b1) begin
hcnt <= 10'd0;
vcnt <= 10'd0;
vcnt <= 10'd430;
end else if (hcnt == 10'd0799) begin
hcnt <= 10'd0;
if (vcnt == 10'd0520)
vcnt <= 10'd0;
if (vcnt == 10'd0)
vcnt <= 10'd520;
else
vcnt <= vcnt + 1'b1;
vcnt <= vcnt - 1'b1;
end else
hcnt <= hcnt + 1'b1;
end
130,7 → 145,7
// HORIZONTAL SYNC TIMING //
//------------------------------------------------------------------//
always @ (hcnt)
if (hcnt <= 10'd0095)
if (hcnt >= 10'd656 && hcnt <= 10'd751)
H_SYNC = 1'b0;
else
H_SYNC = 1'b1;
140,7 → 155,7
// VERTICAL SYNC TIMING //
//------------------------------------------------------------------//
always @ (vcnt)
if (vcnt <= 10'd0001)
if (vcnt == 10'd430 || vcnt == 10'd429)
V_SYNC = 1'b0;
else
V_SYNC = 1'b1;
154,63 → 169,58
VGA_OUTPUT = P_black;
//------------------------------------------------------------------------------//
// UNSEEN BORDERS //
end else if( (vcnt <= 10'd30) || (vcnt >= 10'd511) ) begin
end else if( (vcnt >= 10'd400) && (vcnt <= 10'd440) ) begin
VGA_OUTPUT = P_black;
end else if( (hcnt <= 10'd143) || (hcnt >= 10'd784) ) begin
end else if( (hcnt >= 10'd640) ) begin
VGA_OUTPUT = P_black;
//------------------------------------------------------------------------------//
// MOUSE CURSORS //
end else if(vcnt == (YCOORD+10'd31)) begin
end else if(vcnt == YCOORD) begin
VGA_OUTPUT = P_green;
end else if(hcnt == (XCOORD+10'd144)) begin
end else if(hcnt == XCOORD) begin
VGA_OUTPUT = P_green;
//------------------------------------------------------------------------------//
// TRIGGER SPRITE (shows as ------T------ ) //
end else if(SHOW_LEVELS == 1'b1 && vcnt == (TRIGGER_LEVEL+10'd31) && hcnt != 10'd700 && hcnt != 10'd702) begin
end else if(SHOW_LEVELS == 1'b1 && vcnt == (TRIGGER_LEVEL) && hcnt != 10'd556 && hcnt != 10'd558) begin
VGA_OUTPUT = P_yellow;
end else if(SHOW_LEVELS == 1'b1 && vcnt == (TRIGGER_LEVEL-1'b1+10'd31) && hcnt >= 10'd700 && hcnt <= 10'd702) begin
end else if(SHOW_LEVELS == 1'b1 && vcnt == (TRIGGER_LEVEL+1'b1) && hcnt >= 10'd556 && hcnt <= 10'd558) begin
VGA_OUTPUT = P_yellow;
end else if(SHOW_LEVELS == 1'b1 && vcnt == (TRIGGER_LEVEL+1'b1+10'd31) && hcnt == 10'd701) begin
end else if(SHOW_LEVELS == 1'b1 && vcnt == (TRIGGER_LEVEL-1'b1) && hcnt == 10'd557) begin
VGA_OUTPUT = P_yellow;
///*
//------------------------------------------------------------------------------//
// MOVE THE WAVEFORM TO THE 'TOP' //
end else if(vga_out != 0 && (vcnt < 10'd431)) begin
end else if(vga_out != 0) begin
VGA_OUTPUT = vga_out;
//*/
//------------------------------------------------------------------------------//
// TOP, BOTTOM, LEFT AND RIGHT GRID LINES //
end else if( vcnt == 10'd031 || vcnt == 10'd431 || vcnt == 10'd510) begin
end else if(vcnt == 10'd0 || vcnt == 10'd399 || vcnt == 10'd441) begin
VGA_OUTPUT = P_cyan;
end else if( hcnt == 10'd144 || hcnt == 10'd783) begin
end else if(hcnt == 10'd0 || hcnt == 10'd639) begin
VGA_OUTPUT = P_cyan;
//------------------------------------------------------------------------------//
// MIDDLE GRID LINES (dashed at 8pxls) //
end else if(vcnt == 10'd231 && hcnt[3] == 1'b1) begin
end else if(vcnt == 10'd199 && hcnt[3] == 1'b1) begin
VGA_OUTPUT = P_cyan;
end else if((hcnt == 10'd464) && (vcnt <= 10'd431) && (vcnt[3] == 1'b1)) begin
end else if((hcnt == 10'd319) && (vcnt <= 10'd399) && (vcnt[3] == 1'b1)) begin
VGA_OUTPUT = P_cyan;
//------------------------------------------------------------------------------//
// OTHER HORIZONTAL LINES (dashed at 4pxls) //
end else if((vcnt == 10'd071 || vcnt == 10'd111 || vcnt == 10'd151 || vcnt == 10'd191 || vcnt == 10'd271 || vcnt == 10'd311 || vcnt == 10'd351 || vcnt == 10'd391) && (hcnt[2] == 1'b1)) begin
end else if((vcnt == 10'd39 || vcnt == 10'd79 || vcnt == 10'd119 || vcnt == 10'd159 || vcnt == 10'd239 || vcnt == 10'd279 || vcnt == 10'd319 || vcnt == 10'd359) && (hcnt[2] == 1'b1)) begin
VGA_OUTPUT = P_cyan;
//------------------------------------------------------------------------------//
// OTHER VERTICAL LINES (dashed at 4pxls) //
end else if(((hcnt[5:0] == 6'b010000) && (vcnt <= 10'd431)) && (vcnt[2] == 1'b1)) begin
end else if(((hcnt[5:0] == 6'b111111) && (vcnt <= 10'd399)) && (vcnt[2] == 1'b1)) begin
VGA_OUTPUT = P_cyan;
//------------------------------------------------------------------------------//
// CHARACTER DISPLAY
end else if(vcnt <= 10'd520 && vcnt >= 10'd441) begin
VGA_OUTPUT = RGB_CHAR;
//------------------------------------------------------------------------------//
// OTHERWISE... //
end else
VGA_OUTPUT = P_black;
/*
//------------------------------------------------------------------------------//
// DISPLAY DATA //
end else if(vcnt >= 10'd431) begin
VGA_OUTPUT = P_black;
end else begin
VGA_OUTPUT = vga_out;
end
*/
end
 
//------------------------------------------------------------------//
224,11 → 234,11
// row 16: ram_addr = 23 and 25 for each pxl *
// row 17: ram_addr = 23 and 25 for each pxl *
// ...
reg[9:0] ram_hcnt;
/*reg[9:0] ram_hcnt;*/
reg[4:0] ram_vcnt;
reg[15:0] ram_vshift;
 
 
/*
always @ (posedge CLK_25MHZ or posedge MASTER_RST) begin
if(MASTER_RST == 1'b1) begin
ram_hcnt <= 10'd639;
241,13 → 251,14
ram_hcnt <= 10'd639;
end
end
*/
 
always @ (posedge CLK_25MHZ or posedge MASTER_RST) begin
if(MASTER_RST == 1'b1) begin
ram_vshift <= 16'h8000;
end else if(vcnt < 10'd31) begin
end else if(vcnt > 10'd399) begin
ram_vshift <= 16'h8000;
end else if((vcnt >= 10'd31) && (hcnt == 10'd0799)) begin
end else if((vcnt <= 10'd399) && (hcnt == 10'd655)) begin
if(ram_vshift == 16'h0001)
ram_vshift <= 16'h8000;
else
261,10 → 272,10
ram_vcnt <= 5'd0;
end else if(vcnt < 10'd30) begin
ram_vcnt <= 5'd0;
end else if((vcnt >= 10'd30) && (hcnt == 10'd0799) && (ram_vshift == 16'h0001)) begin
end else if((vcnt >= 10'd30) && (hcnt == 10'd655) && (ram_vshift == 16'h0001)) begin
if(ram_vcnt == 5'd0)
ram_vcnt <= 5'd24;
else
else
ram_vcnt <= ram_vcnt - 1'b1;
end else begin
ram_vcnt <= ram_vcnt;
273,8 → 284,8
 
 
 
always @ (ram_hcnt or ram_vcnt) begin
VGA_RAM_ADDR = ram_vcnt + (ram_hcnt * 7'd025);
always @ (hcnt or ram_vcnt) begin
VGA_RAM_ADDR = ram_vcnt + (hcnt * 7'd25);
end
 
 
297,7 → 308,7
// ALL CLEAR? //
//------------------------------------------------------------------//
always @ (vcnt) begin
if(vcnt >= 10'd512 || vcnt < 10'd30)
if((vcnt >= 10'd400) && (vcnt <= 10'd440))
VGA_RAM_ACCESS_OK = 1'b1;
else
VGA_RAM_ACCESS_OK = 1'b0;
/trunk/VGA/CharDecode/d_CharDecode.v
0,0 → 1,430
//==================================================================//
// File: d_xxxxxxxxxxxx //
// Version: 0.0.0.1 //
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -//
// Copyright (C) Stephen Pickett //
// Jun 17, 2005 //
// //
// This program is free software; you can redistribute it and/or //
// modify it under the terms of the GNU General Public License //
// as published by the Free Software Foundation; either version 2 //
// of the License, or (at your option) any later version. //
// //
// This program is distributed in the hope that it will be useful, //
// but WITHOUT ANY WARRANTY; without even the implied warranty of //
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the //
// GNU General Public License for more details. //
// //
// If you have not received a copy of the GNU General Public License//
// along with this program; write to: //
// Free Software Foundation, Inc., //
// 51 Franklin Street, Fifth Floor, //
// Boston, MA 02110-1301, USA. //
// //
//------------------------------------------------------------------//
// Revisions: //
// Ver 0.0.0.1 Jun 17, 2005 Initial Development Release //
// //
//==================================================================//
 
module CharacterDisplay(
MASTER_CLK, MASTER_RST,
CLK_VGA, HCNT, VCNT,
RGB_OUT,
data_charRamRead, data_charMap
);
//==================================================================//
// PARAMETER DEFINITIONS //
//==================================================================//
parameter P_black = 3'b000;
parameter P_yellow = 3'b110;
parameter P_cyan = 3'b011;
parameter P_green = 3'b010;
parameter P_white = 3'b111;
parameter P_blue = 3'b111;
 
//==================================================================//
// VARIABLE DEFINITIONS //
//==================================================================//
//----------------------//
// INPUTS / OUTPUTS //
//----------------------//
input MASTER_CLK; // System wide clock
input MASTER_RST; // System wide reset
input CLK_VGA; // Pixel Clk
input[9:0] HCNT; // Horizontal Sync Counter
input[9:0] VCNT; // Vertical Sync Counter
output[2:0] RGB_OUT; // The RGB data
 
output[7:0] data_charRamRead;
output[7:0] data_charMap;
 
 
//----------------------//
// WIRES / NODES //
//----------------------//
wire MASTER_CLK, MASTER_RST, CLK_VGA;
wire[9:0] HCNT, VCNT;
reg[2:0] RGB_OUT;
 
 
 
//----------------------//
// REGISTERS //
//----------------------//
reg[3:0] cnt_charPxls;
reg[5:0] cnt_Hchar;
reg[10:0] cnt_Vchar;
wire charRow1, charRow2, charRow3, charRow4;
 
wire[10:0] addr_charRamRead;
wire[7:0] data_charRamRead;
 
reg[7:0] mask_charMap;
wire[10:0] addr_charMap;
wire[7:0] data_charMap;
 
 
//==================================================================//
// FUNCTIONAL DEFINITIONS //
//==================================================================//
 
 
 
//------------------------------------------------------------------//
// Character Input / Storage //
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - //
// A useful description could go here! //
//------------------------------------------------------------------//
 
 
 
 
 
//------------------------------------------------------------------//
// Character Decode //
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - //
// A useful description could go here! //
//------------------------------------------------------------------//
 
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - //
// DECODE the Character RAM Address via HCNT and VCNT //
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - //
 
always @ (posedge CLK_VGA or posedge MASTER_RST) begin
if(MASTER_RST) begin
cnt_charPxls <= 4'd10;
end else if(HCNT >= 10'd6) begin //7
if(cnt_charPxls == 4'd0)
cnt_charPxls <= 4'd10;
else
cnt_charPxls <= cnt_charPxls-1;
end else begin
cnt_charPxls <= 4'd10;
end
end
 
always @ (posedge CLK_VGA or posedge MASTER_RST) begin
if(MASTER_RST) begin
cnt_Hchar <= 6'd0;
end else if(HCNT >= 10'd6 && cnt_charPxls == 4'd0) begin
if(cnt_Hchar == 6'd56)
cnt_Hchar <= 6'd0;
else
cnt_Hchar <= cnt_Hchar+1;
end else if(HCNT < 10'd6) begin
cnt_Hchar <= 6'd0;
end else begin
cnt_Hchar <= cnt_Hchar;
end
end
 
assign charRow1 = ((VCNT <= 512) && (VCNT >= 498)); // one more
assign charRow2 = ((VCNT <= 494) && (VCNT >= 480));
assign charRow3 = ((VCNT <= 476) && (VCNT >= 462));
assign charRow4 = ((VCNT <= 458) && (VCNT >= 444));
 
always @ (charRow1 or charRow2 or charRow3 or charRow4) begin
if(charRow1) cnt_Vchar = 11'd0;
else if(charRow2) cnt_Vchar = 11'd57;
else if(charRow3) cnt_Vchar = 11'd114;
else cnt_Vchar = 11'd174;
end
 
assign addr_charRamRead = cnt_Vchar + cnt_Hchar;
 
 
 
 
 
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - //
// DECODE the Character Map via HCNT and VCNT and CHAR_DATA //
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - //
always @ (posedge CLK_VGA or posedge MASTER_RST) begin
if(MASTER_RST) begin
mask_charMap <= 8'd0;
end else if(VCNT <= 10'd512) begin
if(HCNT == 10'd0 && VCNT[0] == 1'b1) begin //1B0
if(mask_charMap == 8'd0)
mask_charMap <= 8'b10000000;
else
mask_charMap <= mask_charMap >> 1;
end else
mask_charMap <= mask_charMap;
end else begin
mask_charMap <= 8'd0;
end
end
 
 
 
assign addr_charMap = (data_charRamRead * 8'd5) + (cnt_charPxls[3:1]);
 
 
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - //
// DECODE the VGA_OUTPUT via the Character Map //
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - //
reg[2:0] rgb_buf;
 
always @ (mask_charMap or data_charMap) begin
if((charRow1 | charRow2 | charRow3 | charRow4) && ((mask_charMap & data_charMap) != 8'b0) && (cnt_charPxls != 4'd10) && (HCNT >= 10'd7) && (HCNT <= 10'd632))
rgb_buf = P_yellow;
else
rgb_buf = P_black;
end
always @ (posedge CLK_VGA) begin
RGB_OUT <= rgb_buf;
end
 
 
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - //
// COUNTER TESTING //
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - //
reg[63:0] test_cnt;
reg[10:0] test_cntAddr;
reg[7:0] data_time;
always @ (posedge MASTER_CLK or posedge MASTER_RST) begin
if(MASTER_RST)
test_cnt <= 64'd0;
else
test_cnt <= test_cnt+1;
end
 
always @ (posedge MASTER_CLK or posedge MASTER_RST) begin
if(MASTER_RST)
test_cntAddr <= 11'd41;
else if(test_cntAddr == 11'd56)
test_cntAddr <= 11'd41;
else
test_cntAddr <= test_cntAddr+1;
end
 
always @ (test_cntAddr or test_cnt) begin
if(test_cntAddr == 11'd41) data_time[3:0] = test_cnt[63:60];
else if(test_cntAddr == 11'd42) data_time[3:0] = test_cnt[59:56];
else if(test_cntAddr == 11'd43) data_time[3:0] = test_cnt[55:52];
else if(test_cntAddr == 11'd44) data_time[3:0] = test_cnt[51:48];
else if(test_cntAddr == 11'd45) data_time[3:0] = test_cnt[47:44];
else if(test_cntAddr == 11'd46) data_time[3:0] = test_cnt[43:40];
else if(test_cntAddr == 11'd47) data_time[3:0] = test_cnt[39:36];
else if(test_cntAddr == 11'd48) data_time[3:0] = test_cnt[35:32];
else if(test_cntAddr == 11'd49) data_time[3:0] = test_cnt[31:28];
else if(test_cntAddr == 11'd50) data_time[3:0] = test_cnt[27:24];
else if(test_cntAddr == 11'd51) data_time[3:0] = test_cnt[23:20];
else if(test_cntAddr == 11'd52) data_time[3:0] = test_cnt[19:16];
else if(test_cntAddr == 11'd53) data_time[3:0] = test_cnt[15:12];
else if(test_cntAddr == 11'd54) data_time[3:0] = test_cnt[11:8];
else if(test_cntAddr == 11'd55) data_time[3:0] = test_cnt[7:4];
else if(test_cntAddr == 11'd56) data_time[3:0] = test_cnt[3:0];
else data_time[3:0] = 4'b0000;
end
 
always begin
data_time[7:4] = 4'b0;
end
 
 
 
 
 
 
 
 
 
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - //
// Character Decode RAM INSTANTIATION //
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - //
// A useful description could go here! //
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - //
wire VCC, GND;
assign VCC = 1'b1;
assign GND = 1'b0;
 
RAMB16_S9_S9 #(
// 6666555555555544444444443333333333222222222211111111110000000000
.INIT_00(256'h920de29292928ee0101010fe449292927c668A9292662242FE02027C8282827C),
// CCCCCCCCBBBBBBBBBBAAAAAAAAAA999999999988888888887777777777666666
.INIT_01(256'h828282c6Fe9292926c7e9090907e609292927d6d9292926d808698a0C07d9292),
// --SPACE---FFFFFFFFFFEEEEEEEEEEDDDDDDDDDDCC
.INIT_02(256'h00000000000000000000000000000000Fe909090c0Fe929292c6FE8282827c7c),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000)
) RAM_Character_Map (
.DOA(), .DOB(data_charMap),
.DOPA(), .DOPB(),
.ADDRA(11'b111), .ADDRB(addr_charMap),
.CLKA(GND), .CLKB(MASTER_CLK),
.DIA(8'b0), .DIB(8'b0),
.DIPA(GND), .DIPB(GND),
.ENA(GND), .ENB(VCC),
.WEA(GND), .WEB(GND),
.SSRA(GND), .SSRB(GND)
);
 
 
RAMB16_S9_S9 #(
.INIT_00(256'h1010101010101010101010100F0E0D0C0B0A0908070605040302010010101010),
.INIT_01(256'h1010101010101010101010101010101010101010101010101010101010101010),
.INIT_02(256'h1010101010101010101010101010101010101010101010101010101010101010),
.INIT_03(256'h1010101010101010101010101010101010101010101010101010101010101010),
.INIT_04(256'h1010101010101010101010101010101010101010101010101010101010101010),
.INIT_05(256'h1010101010101010101010101010101010101010101010101010101010101010),
.INIT_06(256'h1010101010101010101010101010101010101010101010101010101010101010),
.INIT_07(256'h1010101010101010101010101010101010101010101010101010101010101010),
.INIT_08(256'h1010101010101010101010101010101010101010101010101010101010101010),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000)
) RAM_Character_Test (
.DOA(), .DOB(data_charRamRead),
.DOPA(), .DOPB(),
.ADDRA(test_cntAddr), .ADDRB(addr_charRamRead),
.CLKA(MASTER_CLK), .CLKB(MASTER_CLK),
.DIA(data_time), .DIB(8'b0),
.DIPA(GND), .DIPB(GND),
.ENA(VCC), .ENB(VCC),
.WEA(VCC), .WEB(GND),
.SSRA(GND), .SSRB(GND)
);
 
 
 
 
 
 
 
 
endmodule
/trunk/UserInput/.#d_MouseInput.v.1.1
0,0 → 1,144
//==================================================================//
// File: d_MouseInput.v //
// Version: 0.0.0.2 //
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -//
// Copyright (C) Stephen Pickett //
// Jun 08, 2005 //
// //
// This program is free software; you can redistribute it and/or //
// modify it under the terms of the GNU General Public License //
// as published by the Free Software Foundation; either version 2 //
// of the License, or (at your option) any later version. //
// //
// This program is distributed in the hope that it will be useful, //
// but WITHOUT ANY WARRANTY; without even the implied warranty of //
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the //
// GNU General Public License for more details. //
// //
// If you have not received a copy of the GNU General Public License//
// along with this program; write to: //
// Free Software Foundation, Inc., //
// 51 Franklin Street, Fifth Floor, //
// Boston, MA 02110-1301, USA. //
// //
//------------------------------------------------------------------//
// Revisions: //
// Ver 0.0.0.1 May , 2005 Under Development //
// Ver 0.0.0.2 Jun 08, 2005 Modulized 'UserLines' //
// //
//==================================================================//
 
module Driver_MouseInput(
CLK_50MHZ, MASTER_RST,
XCOORD, YCOORD, L_BUTTON, R_BUTTON, M_BUTTON,
TRIGGER_LEVEL
);
 
 
//==================================================================//
// PARAMETER DEFINITIONS //
//==================================================================//
parameter P_trigger_clickLimit_left = 10'd556;
parameter P_trigger_clickLimit_right = 10'd558;
 
 
//==================================================================//
// VARIABLE DEFINITIONS //
//==================================================================//
//----------------------//
// INPUTS / OUTPUTS //
//----------------------//
input CLK_50MHZ; // System wide clock
input MASTER_RST; // System wide reset
input[9:0] XCOORD; // X coordinate of the cursor
input[9:0] YCOORD; // Y coordinate of the cursor
input L_BUTTON; // Left Mouse Button Press
input R_BUTTON; // Right Mouse Button Press
input M_BUTTON; // Middle Mouse Button Press
output[9:0] TRIGGER_LEVEL; // Current Trigger Level
 
//----------------------//
// WIRES / NODES //
//----------------------//
wire CLK_50MHZ, MASTER_RST;
wire[9:0] XCOORD;
wire[9:0] YCOORD;
wire L_BUTTON, R_BUTTON, M_BUTTON;
wire[9:0] TRIGGER_LEVEL;
 
//----------------------//
// REGISTERS //
//----------------------//
 
 
//----------------------//
// TESTING //
//----------------------//
 
 
 
 
//==================================================================//
// FUNCTIONAL DEFINITIONS //
//==================================================================//
 
//------------------------------------------------------------------//
// INTERMEDIATES //
//------------------------------------------------------------------//
 
// -- LEFT BUTTON --
wire Lrise, Lfall;
reg Lbuf;
always @ (posedge CLK_50MHZ or posedge MASTER_RST) begin
if(MASTER_RST == 1'b1) Lbuf <= 1'b0;
else Lbuf <= L_BUTTON;
end
 
assign Lrise = (!Lbuf & L_BUTTON);
assign Lfall = ( Lbuf & !L_BUTTON);
 
// -- RIGHT BUTTON --
wire Rrise, Rfall;
reg Rbuf;
always @ (posedge CLK_50MHZ or posedge MASTER_RST) begin
if(MASTER_RST == 1'b1) Rbuf <= 1'b0;
else Rbuf <= R_BUTTON;
end
 
assign Rrise = (!Rbuf & R_BUTTON);
assign Rfall = ( Rbuf & !R_BUTTON);
 
 
// -- MIDDLE BUTTON --
wire Mrise, Mfall;
reg Mbuf;
always @ (posedge CLK_50MHZ or posedge MASTER_RST) begin
if(MASTER_RST == 1'b1) Mbuf <= 1'b0;
else Mbuf <= M_BUTTON;
end
 
assign Mrise = (!Mbuf & M_BUTTON);
assign Mfall = ( Mbuf & !M_BUTTON);
 
 
//------------------------------------------------------------------//
// USER MODIFIABLE LINES //
//------------------------------------------------------------------//
sub_UserLines set_trigger(
.MASTER_CLK(CLK_50MHZ), .MASTER_RST(MASTER_RST),
.LINE_VALUE_OUT(TRIGGER_LEVEL),
.BUTTON_RISE(Lrise),
.BUTTON_FALL(Lfall),
.XCOORD(XCOORD),
.YCOORD(YCOORD),
.LEFT(P_trigger_clickLimit_left),
.RGHT(P_trigger_clickLimit_right),
.BOT(TRIGGER_LEVEL-1'b1),
.TOP(TRIGGER_LEVEL+1'b1),
.SETXnY(1'b0)
);
 
 
 
endmodule
 

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