URL
https://opencores.org/ocsvn/ata/ata/trunk
Subversion Repositories ata
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 11 to Rev 12
- ↔ Reverse comparison
Rev 11 → Rev 12
/trunk/verilog/ocidec-1/atahost.v
6,6 → 6,7
// rev.: 1.1 July 3rd, 2001. Changed 'ADR_I[5:2]' into 'ADR_I' on output multiplexor sensitivity list. |
// rev.: 1.2 July 9th, 2001. Fixed register control; registers latched data on all edge cycles instead when selected. |
// rev.: 1.3 July 11th, 2001. Fixed case sensitivity error (nRESET instead of nReset) in "controller" module declaration. |
// rev.: 1.4 July 26th, 2001. Fixed non-blocking assignments. |
|
// DeviceType: OCIDEC-1: OpenCores IDE Controller type1 |
// Features: PIO Compatible Timing |
175,24 → 176,24
always@(posedge CLK_I or negedge nReset) |
if (~nReset) |
begin |
PIO_cmdport_T1 = PIO_mode0_T1; |
PIO_cmdport_T2 = PIO_mode0_T2; |
PIO_cmdport_T4 = PIO_mode0_T4; |
PIO_cmdport_Teoc = PIO_mode0_Teoc; |
PIO_cmdport_T1 <= PIO_mode0_T1; |
PIO_cmdport_T2 <= PIO_mode0_T2; |
PIO_cmdport_T4 <= PIO_mode0_T4; |
PIO_cmdport_Teoc <= PIO_mode0_Teoc; |
end |
else if (RST_I) |
begin |
PIO_cmdport_T1 = PIO_mode0_T1; |
PIO_cmdport_T2 = PIO_mode0_T2; |
PIO_cmdport_T4 = PIO_mode0_T4; |
PIO_cmdport_Teoc = PIO_mode0_Teoc; |
PIO_cmdport_T1 <= PIO_mode0_T1; |
PIO_cmdport_T2 <= PIO_mode0_T2; |
PIO_cmdport_T4 <= PIO_mode0_T4; |
PIO_cmdport_Teoc <= PIO_mode0_Teoc; |
end |
else if(sel_PIO_cmdport) |
begin |
PIO_cmdport_T1 = DAT_I[ 7: 0]; |
PIO_cmdport_T2 = DAT_I[15: 8]; |
PIO_cmdport_T4 = DAT_I[23:16]; |
PIO_cmdport_Teoc = DAT_I[31:24]; |
PIO_cmdport_T1 <= DAT_I[ 7: 0]; |
PIO_cmdport_T2 <= DAT_I[15: 8]; |
PIO_cmdport_T4 <= DAT_I[23:16]; |
PIO_cmdport_Teoc <= DAT_I[31:24]; |
end |
|
|
229,3 → 230,5
// assign DAT_O output |
assign DAT_O = ADR_I[6] ? {16'h0000, PIOq} : Q; |
endmodule |
|
|
/trunk/verilog/ocidec-1/controller.v
5,7 → 5,8
// rev.: 1.0 june 28th, 2001. Initial Verilog release |
// rev.: 1.1 July 3rd, 2001. Rewrote "IORDY" and "INTRQ" capture section. |
// rev.: 1.2 July 9th, 2001. Added "timescale". Undid "IORDY & INTRQ" rewrite. |
// rev.: 1.3 july 11th, 2001. Changed PIOreq & PIOack generation (made them synchronous). |
// rev.: 1.3 July 11th, 2001. Changed PIOreq & PIOack generation (made them synchronous). |
// rev.: 1.4 July 26th, 2001. Fixed non-blocking assignments. |
|
// OCIDEC1 supports: |
// -Common Compatible timing access to all connected devices |
172,7 → 173,7
always@(posedge clk) |
begin |
dPIOreq <= PIOreq & !PIOack; |
PIOgo = (PIOreq & !dPIOreq) & IDEctrl_IDEen; |
PIOgo <= (PIOreq & !dPIOreq) & IDEctrl_IDEen; |
end |
|
// set Timing signals |
188,9 → 189,5
.go(PIOgo), .we(PIOwe), .oe(PIOoe), .done(PIOdone), .dstrb(dstrb), .DIOR(PIOdior), .DIOW(PIOdiow), .IORDY(sIORDY) ); |
|
always@(posedge clk) |
PIOack = PIOdone | (PIOreq & !IDEctrl_IDEen); // acknowledge when done or when IDE not enabled (discard request) |
PIOack <= PIOdone | (PIOreq & !IDEctrl_IDEen); // acknowledge when done or when IDE not enabled (discard request) |
endmodule |
|
|
|
|
/trunk/verilog/ocidec-1/revision_history.txt
38,3 → 38,10
- Changed PIOreq & PIOack generation (controller.vhd); made them synchronous |
- Changed 'go' & 'igo' generation (pio_tctrl.vhdl). |
----------------------------- |
|
----------------------------- |
Revision: 1.4 |
Date: July 26th, 2001 |
Author: Richard Herveille |
- Fixed some blocking versus non-blocking statement issues. |
----------------------------- |