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URL https://opencores.org/ocsvn/axi4_tlm_bfm/axi4_tlm_bfm/trunk

Subversion Repositories axi4_tlm_bfm

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    from Rev 11 to Rev 12
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Rev 11 → Rev 12

/axi4_tlm_bfm/trunk/rtl/axi4-stream-bfm-master.vhdl
36,7 → 36,7
from http://www.opencores.org/lgpl.shtml.
*/
library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all;
library tauhop; use tauhop.transactor.all, tauhop.axiTransactor.all;
library tauhop; use tauhop.axiTransactor.all;
 
--/* TODO remove once generic packages are supported. */
--library tauhop; use tauhop.tlm.all, tauhop.axiTLM.all;
44,8 → 44,10
entity axiBfmMaster is --generic(constant maxTransactions:positive);
port(aclk,n_areset:in std_ulogic;
/* BFM signalling. */
readRequest,writeRequest:in t_bfm:=((others=>'X'),(others=>'X'),false); -- this is tauhop.transactor.t_bfm.
readResponse,writeResponse:buffer t_bfm; -- use buffer until synthesis tools support reading from out ports.
/* FIXME Generic package defect. ModelSim currently can't make tauhop.axiTransactor.i_transactor visible. */
readRequest,writeRequest:in i_transactor.t_bfm:=((others=>'X'),(others=>'X'),false);
--readRequest,writeRequest:in i_transactor.t_bfm:=((others=>'X'),(others=>'X'),false);
readResponse,writeResponse:buffer i_transactor.t_bfm; -- use buffer until synthesis tools support reading from out ports.
/* AXI Master interface */
axiMaster_in:in t_axi4StreamTransactor_s2m;
55,8 → 57,8
-- axiSlave_in:in tAxi4Transactor_m2s;
-- axiSlave_out:buffer tAxi4Transactor_s2m;
symbolsPerTransfer:in t_cnt;
outstandingTransactions:buffer t_cnt
symbolsPerTransfer:in i_transactor.t_cnt;
outstandingTransactions:buffer i_transactor.t_cnt
/* Debug ports. */
-- dbg_cnt:out unsigned(9 downto 0);
70,10 → 72,10
signal axiTxState,next_axiTxState:axiBfmStatesTx:=idle;
/* BFM signalling. */
signal i_readRequest:t_bfm:=((others=>'0'),(others=>'0'),false);
signal i_writeRequest:t_bfm:=((others=>'0'),(others=>'0'),false);
signal i_readRequest:i_transactor.t_bfm:=((others=>'0'),(others=>'0'),false);
signal i_writeRequest:i_transactor.t_bfm:=((others=>'0'),(others=>'0'),false);
signal i_readResponse,i_writeResponse:t_bfm;
signal i_readResponse,i_writeResponse:i_transactor.t_bfm;
begin
/* Transaction counter. */
/axi4_tlm_bfm/trunk/rtl/user.vhdl
35,7 → 35,7
from http://www.opencores.org/lgpl.shtml.
*/
library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all; use ieee.math_real.all;
library tauhop; use tauhop.transactor.all, tauhop.axiTransactor.all; --TODO just use axiTransactor here as transactor should already be wrapped up.
library tauhop; use tauhop.axiTransactor.all;
 
/* TODO remove once generic packages are supported. */
--library tauhop; use tauhop.tlm.all, tauhop.axiTLM.all;
59,14 → 59,14
architecture rtl of user is
/* Global counters. */
constant maxSymbols:positive:=2048; --maximum number of symbols allowed to be transmitted in a frame. Each symbol's width equals tData's width.
signal symbolsPerTransfer:t_cnt;
signal outstandingTransactions:t_cnt;
signal symbolsPerTransfer:i_transactor.t_cnt;
signal outstandingTransactions:i_transactor.t_cnt;
/* BFM signalling. */
signal readRequest:t_bfm:=((others=>'0'),(others=>'0'),false);
signal writeRequest:t_bfm:=((others=>'0'),(others=>'0'),false);
signal readResponse:t_bfm;
signal writeResponse:t_bfm;
signal readRequest:i_transactor.t_bfm:=((others=>'0'),(others=>'0'),false);
signal writeRequest:i_transactor.t_bfm:=((others=>'0'),(others=>'0'),false);
signal readResponse:i_transactor.t_bfm;
signal writeResponse:i_transactor.t_bfm;
type txStates is (idle,transmitting);
signal txFSM,i_txFSM:txStates;
166,12 → 166,12
/* Data transmitter. */
sequencer: process(nReset,irq_write) is
/* Local procedures to map BFM signals with the package procedure. */
procedure read(address:in t_addr) is begin
read(readRequest,address);
procedure read(address:in i_transactor.t_addr) is begin
i_transactor.read(readRequest,address);
end procedure read;
procedure write(data:in t_msg) is begin
write(request=>writeRequest, address=>(others=>'-'), data=>data);
procedure write(data:in i_transactor.t_msg) is begin
i_transactor.write(request=>writeRequest, address=>(others=>'-'), data=>data);
end procedure write;
variable isPktError:boolean;
/axi4_tlm_bfm/trunk/rtl/quartus-synthesis/pkg-axi-tlm.vhdl
50,6 → 50,8
/* TODO remove once generic packages are supported. */
use tauhop.tlm.all;
--type boolean_vector is array(natural range<>) of boolean;
--subtype t_qualifier is boolean_vector(32/8-1 downto 0);
subtype t_qualifier is std_ulogic_vector(32/8-1 downto 0);
subtype t_id is unsigned(31 downto 0);
subtype t_dest is unsigned(3 downto 0);
/axi4_tlm_bfm/trunk/rtl/packages/pkg-tlm.vhdl
59,13 → 59,13
end record t_bfm;
procedure write(
signal request:inout t_bfm; --FIXME use inout because Quartus doesn't yet allow reading of "out" within a procedure. VHDL-2008 allows this, and QuestaSim works fine.
signal request:out t_bfm; --FIXME use inout because Quartus doesn't yet allow reading of "out" within a procedure. VHDL-2008 allows this, and QuestaSim works fine.
address:in t_addr; -- used only for non-stream interfaces.
data:in t_msg
);
procedure read(
signal request:inout t_bfm; --FIXME use inout because Quartus doesn't yet allow reading of "out" within a procedure. VHDL-2008 allows this, and QuestaSim works fine.
signal request:out t_bfm; --FIXME use inout because Quartus doesn't yet allow reading of "out" within a procedure. VHDL-2008 allows this, and QuestaSim works fine.
address:in t_addr -- used only for non-stream interfaces.
);
end package tlm;
72,7 → 72,7
 
package body tlm is
procedure write(
signal request:inout t_bfm; --FIXME use inout because Quartus doesn't yet allow reading of "out" within a procedure. VHDL-2008 allows this, and QuestaSim works fine.
signal request:out t_bfm; --FIXME use inout because Quartus doesn't yet allow reading of "out" within a procedure. VHDL-2008 allows this, and QuestaSim works fine.
address:in t_addr; -- used only for non-stream interfaces.
data:in t_msg
) is begin
82,7 → 82,7
end procedure write;
procedure read(
signal request:inout t_bfm; --FIXME use inout because Quartus doesn't yet allow reading of "out" within a procedure. VHDL-2008 allows this, and QuestaSim works fine.
signal request:out t_bfm; --FIXME use inout because Quartus doesn't yet allow reading of "out" within a procedure. VHDL-2008 allows this, and QuestaSim works fine.
address:in t_addr -- used only for non-stream interfaces.
) is begin
request.address<=address;

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