OpenCores
URL https://opencores.org/ocsvn/dmt_tx/dmt_tx/trunk

Subversion Repositories dmt_tx

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /
    from Rev 11 to Rev 12
    ↔ Reverse comparison
  •

Rev 11 → Rev 12

/trunk/const_encoder/rtl/const_enc.v
0,0 → 1,32
 
 
module const_encoder(
clk,
reset,
input_ready_o,
we_data_i,
data_i,
addr_i,
we_conf_i,
conf_data_i,
xy_ready_o,
bin_num_o,
x_o,
y_o);
 
input clk;
input reset;
output input_ready_o;
input we_data_i;
input data_i;
input addr_i;
input we_conf_i;
input conf_data_i;
output xy_ready_o;
output bin_num_o;
output x_o;
output y_o;
 
 
 
endmodule
/trunk/const_encoder/rtl/fifo.v
0,0 → 1,124
 
module fifo(
clk,
reset,
empty_o,
full_o,
one_available_o,
two_available_o,
we_i,
data_i,
re_i,
data_o);
 
parameter DWIDTH = 8;
parameter AWIDTH = 4;
input clk;
input reset;
output empty_o;
output full_o;
output one_available_o;
output two_available_o;
input we_i;
input [DWIDTH-1:0] data_i;
input re_i;
output [DWIDTH-1:0] data_o;
 
 
 
 
//
// local reg/wires
//
reg [AWIDTH-1:0] read_ptr;
reg [AWIDTH-1:0] write_ptr;
reg [AWIDTH:0] fill_ctr;
 
wire dp_we_i;
wire dp_re_i;
 
//
// instantiate the dual port ram
//
generic_dpram #(.aw(AWIDTH),
.dw(DWIDTH)
)
dpram ( .rclk(clk),
.rrst(reset),
.rce(ce),
.oe(dp_re_i),
.raddr(read_ptr),
.do(data_o),
.wclk(clk),
.wrst(reset),
.wce(ce),
.we(dp_we_i),
.waddr(write_ptr),
.di(data_i));
 
 
//
// control logic
//
assign ce = 1'b1;
 
assign one_available_o = (fill_ctr > 1'b0) ? 1'b1 : 1'b0;
assign two_available_o = (fill_ctr > 1'b1) ? 1'b1 : 1'b0;
assign empty_o = |fill_ctr ? 1'b0 : 1'b1;
assign full_o = fill_ctr[AWIDTH] ? 1'b1 : 1'b0;
 
// make sure a write only happens to dp_ram when not full
assign dp_we_i = ~full_o ? we_i : 1'b0;
// make sure a read only happens to the dp_ram when not empty
assign dp_re_i = ~empty_o ? re_i : 1'b0;
 
//
// fill counter
//
always @(posedge clk or posedge reset) begin
if(reset) begin
fill_ctr <= 0;
end
else begin
if(dp_we_i) begin
fill_ctr <= fill_ctr + 1;
end
 
if(dp_re_i) begin
fill_ctr <= fill_ctr - 1;
end
end
end
 
//
// read pointer
//
always @(posedge clk or posedge reset) begin
if(reset) begin
read_ptr <= 0;
end
else begin
if(dp_re_i) begin
read_ptr <= read_ptr + 1;
end
end
end
 
//
// write pointer
//
always @(posedge clk or posedge reset) begin
if(reset) begin
write_ptr <= 0;
end
else begin
if(dp_we_i) begin
write_ptr <= write_ptr + 1;
end
end
end
 
 
endmodule
/trunk/const_encoder/rtl/defs.vh
0,0 → 1,5
 
 
`define VENDOR_FPGA
 
 
/trunk/const_encoder/tb/tb_const_enc.v
0,0 → 1,46
 
 
module tb_const_encoder();
 
reg clk;
reg reset;
wire input_ready_o;
reg we_data_i;
 
 
//
// instantiate the DUT
//
const_encoder dut ( .clk(clk),
.reset(reset),
.input_ready_o(input_ready_o),
.we_data_i(we_data_i),
.data_i(data_i),
.addr_i(addr_i),
.we_conf_i(we_conf_i),
.conf_data_i(conf_data_i),
.xy_ready_o(xy_ready_o),
.bin_num_o(bin_num_o),
.x_o(x_o),
.y_o(y_o));
 
 
initial begin
 
$monitor($time, " clk: ", clk, " reset: ", reset);
clk = 0;
reset = 0;
 
#50 reset = 1;
#50 reset = 0;
 
#1000 $finish();
 
end
 
 
 
endmodule
/trunk/const_encoder/tb/tb_fifo.v
0,0 → 1,220
 
module tb_fifo;
 
parameter AWIDTH = 2;
parameter DWIDTH = 8;
parameter TW=10;
 
 
 
//
// to interface the dut
//
reg clk;
reg reset;
reg [DWIDTH-1:0] data_i;
reg re_i;
wire empty_o;
wire full_o;
wire one_available_o;
wire two_available_o;
reg we_i;
reg [DWIDTH-1:0] data_i;
reg re_i;
wire [DWIDTH-1:0] data_o;
 
 
 
//
// instantiate the DUT
//
fifo #(.AWIDTH(AWIDTH), .DWIDTH(DWIDTH))
 
dut ( .clk(clk),
.reset(reset),
.empty_o(empty_o),
.full_o(full_o),
.one_available_o(one_available_o),
.two_available_o(two_available_o),
.we_i(we_i),
.data_i(data_i),
.re_i(re_i),
.data_o(data_o));
 
//
// local reg/wires
//
reg [DWIDTH-1:0] got_data;
 
//
// main tests
//
initial begin
clk = 0;
we_i = 0;
re_i = 0;
reset = 0;
end
 
always begin
#TW clk = ~clk;
end
 
//
// dump signals
//
initial begin
$dumpfile("tb_fifo.vcd");
$dumpvars;
end
 
 
initial begin
$display("Verifing FIFO");
 
test_reset;
check_control(5'b0001);
 
write_data(8'haa);
check_control(5'b0100);
 
read_data(got_data);
check_result(got_data, 8'haa);
check_control(5'b0001);
// fifo is empty again
// fill it and only expect after the 4th write a full signal
// #1
write_data(8'h70);
check_control(5'b0100);
// #2
write_data(8'h71);
check_control(5'b1100);
// #3
write_data(8'h72);
check_control(5'b1100);
// #4
write_data(8'h73);
check_control(5'b1110);
// fifo full, should not get written
write_data(8'hab);
check_control(5'b1110);
 
// #1
read_data(got_data);
check_result(got_data, 8'h70);
check_control(5'b1100);
// #2
read_data(got_data);
check_result(got_data, 8'h71);
check_control(5'b1100);
// #3
read_data(got_data);
check_result(got_data, 8'h72);
check_control(5'b0100);
// #4
read_data(got_data);
check_result(got_data, 8'h73);
check_control(5'b0001);
 
 
$finish();
 
end
 
 
 
 
// =====================================================================
// bus functional models
//
task test_reset;
begin
$display("Testing reset");
reset = 0;
#10 reset = 1;
#20 reset = 0;
end
endtask
 
 
// =====================================================================
// check the expected control line status
//
// exp_ctrl[4:0] == {two_available, one_available, full, empty}
//
task check_control(input [4:0]exp_ctrl);
begin
$display("# %d expCtrl: %d", $time, exp_ctrl);
if(empty_o !== exp_ctrl[0])
$display("ERROR! => Expected empty_o == %d, got %d", exp_ctrl[0], empty_o);
if(full_o !== exp_ctrl[1])
$display("ERROR! => Expected full_o == %d, got %d", exp_ctrl[1], full_o);
 
if(one_available_o !== exp_ctrl[2])
$display("ERROR! => Expected one_available_o == %d, got %d", exp_ctrl[3], one_available_o);
if(two_available_o !== exp_ctrl[3])
$display("ERROR! => Expected two_available_o == %d, got %d", exp_ctrl[4], two_available_o);
 
end
endtask
 
 
// =====================================================================
//
// write data to the fifo
//
task write_data(input [DWIDTH-1:0]data);
begin
$display("# %d Writing data", $time);
@(negedge clk);
data_i = data;
we_i = 1;
@(negedge clk);
we_i = 0;
 
end
endtask
 
// =====================================================================
//
// read data from the fifo
//
//
task read_data(output [DWIDTH-1:0]data);
begin
 
$display("# %d Reading data", $time);
@(negedge clk);
re_i = 1;
@(negedge clk);
data = data_o;
re_i = 0;
 
end
endtask
 
 
// =====================================================================
//
// check result
//
//
task check_result(input [DWIDTH-1:0]got, input [DWIDTH-1:0]expected);
begin
if(got !== expected)
$display("ERROR! => Result does not match! Got: %d (%x) expected: %d (%x)", got, got, expected, expected);
end
endtask
 
endmodule
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.