OpenCores
URL https://opencores.org/ocsvn/fade_ether_protocol/fade_ether_protocol/trunk

Subversion Repositories fade_ether_protocol

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Rev 11 → Rev 12

/fade_ether_protocol/trunk/experimental_fade_10g/linux/fpga_l3_fade.h
0,0 → 1,59
/*
* fpga_l3_fade - header for L3 communication protocol with FPGA based system
* Copyright (C) 2012 by Wojciech M. Zabolotny
* Institute of Electronic Systems, Warsaw University of Technology
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
* Additionally I (Wojciech Zabolotny) allow you to include this header file
* to compile your closed source applications (however yo should check, that
* license terms of other include files used by this one allow you to do it...).
*/
 
#ifndef _FPGA_L3_FADE_H_
 
 
#include <linux/socket.h>
#include <linux/if_ether.h>
#include <linux/if.h>
 
struct l3_v1_buf_pointers {
int head;
int tail;
} __attribute__ ((__packed__));
 
struct l3_v1_slave {
unsigned char mac[ETH_ALEN];
char devname[IFNAMSIZ];
} __attribute__ ((__packed__));
 
#define L3_V1_IOC_MAGIC 0xa5
 
#define L3_V1_IOC_SETWAKEUP _IO(L3_V1_IOC_MAGIC,0x30)
#define L3_V1_IOC_GETBUFLEN _IO(L3_V1_IOC_MAGIC,0x31)
#define L3_V1_IOC_READPTRS _IOR(L3_V1_IOC_MAGIC,0x32,struct l3_v1_buf_pointers)
#define L3_V1_IOC_WRITEPTRS _IO(L3_V1_IOC_MAGIC,0x33)
#define L3_V1_IOC_STARTMAC _IOW(L3_V1_IOC_MAGIC,0x34,struct l3_v1_slave)
#define L3_V1_IOC_STOPMAC _IO(L3_V1_IOC_MAGIC,0x35)
 
/* Error flags */
#define FADE_ERR_INCORRECT_PACKET_TYPE (1<<0)
#define FADE_ERR_INCORRECT_SET (1<<1)
#define FADE_ERR_INCORRECT_LENGTH (1<<2)
 
 
 
#define _FPGA_L3_FADE_H_
#endif
/fade_ether_protocol/trunk/experimental_fade_10g/linux/receiver2.c
0,0 → 1,157
/*
* fpga_l3_fade - driver for L3 communication protocol with FPGA based system
* Copyright (C) 2012 by Wojciech M. Zabolotny
* Institute of Electronic Systems, Warsaw University of Technology
*
* This code is PUBLIC DOMAIN
*/
 
#include<termios.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <sys/mman.h>
#include <sys/ioctl.h>
#include <fcntl.h>
#include <poll.h>
#include <unistd.h>
#include <stdio.h>
#include <strings.h>
#include <stdlib.h>
#include <stdint.h>
 
#include <sys/socket.h>
#include <linux/serial.h>
#include <sched.h>
#include "fpga_l3_fade.h"
#include <sys/time.h>
 
void main(int argc, char * argv[])
{
int active[3]={0,0,0};
struct l3_v1_buf_pointers bp;
struct l3_v1_slave sl[3] = {
{
.mac = {0xde, 0xad, 0xba, 0xbe, 0xbe,0xef},
.devname = "eth3"
},
{
.mac = {0xde, 0xad, 0xba, 0xbe, 0xbe,0xe1},
.devname = "eth3"
},
{
.mac = {0xde, 0xad, 0xba, 0xbe, 0xbe,0xe2},
.devname = "eth3"
}
};
int i,j;
int res;
int blen[3];
uint32_t data[3] = {0,0,0};
long long total_len[3]={0,0,0};
unsigned char * v[3];
int frs[3]={-1,-1,-1};
struct timeval tv;
double tstart=0.0 , tend=0.0;
int stop;
struct sched_param s;
s.sched_priority = 90;
//Read active channels
for(i=1;i<argc;i++) {
int n = atoi(argv[i]);
if ((n>=0) && (n<=2))
active[n]=1;
}
printf("sched=%d\n",sched_setscheduler(0,SCHED_RR,&s));
//Prepare all slaves to work
for(i=0;i<3;i++) {
char devname[30];
sprintf(devname,"/dev/l3_fpga%d",i);
frs[i]=open(devname,O_RDONLY);
if(frs[i]<0) {
printf("I can't open device %s\b",devname);
perror("");
exit(1);
}
//Get the length of the buffer
blen[i] = ioctl(frs[i],L3_V1_IOC_GETBUFLEN,NULL);
//Set the wakeup threshold
res=ioctl(frs[i],L3_V1_IOC_SETWAKEUP,2000000);
printf("length of buffer: %d, result of set wakeup: %d\n",blen[i],res);
v[i]=(unsigned char *)mmap(0,blen[i],PROT_READ,MAP_PRIVATE,frs[i],0);
if(!v[i]) {
printf("mmap for device %s failed\n",devname);
exit(1);
}
}
//Start the transmission
gettimeofday(&tv, NULL);
tstart=tv.tv_sec+1.0e-6*tv.tv_usec;
stop=tv.tv_sec+300;
for(i=0;i<=2;i++) {
if(active[i]) {
res = ioctl(frs[i],L3_V1_IOC_STARTMAC,&sl[i]);
printf("Result of start for slave %d : %d\n",i,res);
}
}
int first_served=0;
do{
struct pollfd pfd[3] = {{.fd = frs[0], .events = POLLIN, .revents = 0},
{.fd = frs[1], .events = POLLIN, .revents = 0},
{.fd = frs[2], .events = POLLIN, .revents = 0},
};
int ptr=0;
int len=0;
int pres;
//Wait for data using "poll"
pres = poll(pfd,3,-1);
if(pres<0) {
perror("Error in poll:");
exit(1);
}
first_served = (first_served+1) %3; //Rotate priority of slaves
for(j=0;j<3;j++) {
i=(j+first_served) % 3;
if(pfd[i].revents) {
int ofs=0;
len = ioctl(frs[i],L3_V1_IOC_READPTRS,&bp);
//OK. The data are read, let's analyze them
while (bp.head != bp.tail) {
uint32_t c;
c = *(uint32_t *)(v[i]+bp.tail);
c = ntohl(c);
bp.tail=(bp.tail+4) & (blen[i]-1); //Adjust tail pointer modulo blen[i]-1
if (__builtin_expect((c != data[i]), 0)) {
printf("Error! received: %lld expected: %lld position: %8.8x\n",c,data[i],total_len[i]+ofs);
exit(1);
}
if (data[i]<2000000001)
data[i] ++;
else
data[i] = 0;
//ofs++;
}
total_len[i] += len;
printf("i=%d len=%d total=%lld head:%d tail: %d\n",i,len,total_len[i],bp.head, bp.tail);
ioctl(frs[i],L3_V1_IOC_WRITEPTRS,len);
}
}
fflush(stdout);
gettimeofday(&tv, NULL);
if(tv.tv_sec > stop) {
tend=tv.tv_sec+1.0e-6*tv.tv_usec;
break;
}
} while (1);
tend=tend-tstart;
fprintf(stderr,"act0:%d act1:%d act2:%d\n",active[0],active[1],active[2]);
for(i=0;i<3;i++) {
fprintf(stderr,"total data %d=%lld time=%g throughput=%g [Mb/s]\n",i,total_len[i], tend, total_len[i]/tend*8.0);
}
for(i=0;i<=2;i++) {
res = ioctl(frs[i],L3_V1_IOC_STOPMAC,0);
munmap(v[i],blen[i]);
close(frs[i]);
}
}
/fade_ether_protocol/trunk/experimental_fade_10g/linux/fpga_l3_fade.c
0,0 → 1,824
/*
* fpga_l3_fade - driver for L3 communication protocol with FPGA based system
* Copyright (C) 2012 by Wojciech M. Zabolotny
* Institute of Electronic Systems, Warsaw University of Technology
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
 
#include <linux/kernel.h>
#include <linux/module.h>
#include <asm/uaccess.h>
 
MODULE_LICENSE("GPL v2");
 
#include <linux/device.h>
#include <linux/netdevice.h>
#include <linux/fs.h>
#include <linux/cdev.h>
#include <linux/poll.h>
#include <linux/mm.h>
#include <asm/io.h>
#include <linux/wait.h>
#include <linux/sched.h>
#include <asm/uaccess.h> /* for put_user */
 
#include "fpga_l3_fade.h"
 
#define SUCCESS 0
#define DEVICE_NAME "fpga_l3_fade"
 
/* Maximum number of packets' set (the set counter will wrap
* after this number is reached) should be power of two!*/
#define SET_NUMBER (1<<16)
#define SET_NUMBER_MASK (SET_NUMBER-1)
 
/* Number of packets in set - this number depends on amount of RAM
* in the FPGA - all set must fit in the FPGA RAM
* Should be power of two! */
#define PKTS_IN_SET (1<<5)
#define PKT_IN_SET_MASK (PKTS_IN_SET-1)
 
/* Capacity of kernel buffer (mmapped into user space) measured in
* number of sets - should be equal to power of two, to simplify
* the modulo operation (replacing it by binary AND) */
#define SETS_IN_BUFFER (1<<8)
 
#define MY_BUF_LEN (SETS_IN_BUFFER * PKTS_IN_SET * 8192)
#define MY_BUF_LEN_MASK (MY_BUF_LEN-1)
 
/* Length of the user header in the packet -
* command - 2 bytes
* set number - 2 bytes,
* packet number and retry number (not used
* yet) 2 bytes
* current inter-packet delay (used to monitor the
* process of delay adaptation) 4 bytes
*/
#define USER_HDR_LEN 10
 
/* Number of bytes of user data in a packet */
#define USER_LEN 8192
#define PAYL_LEN ( USER_HDR_LEN + USER_LEN )
 
/* Length of the acknowledment packet and command packets */
#define MY_ACK_LEN 64
 
/* Number of bytes to be copied from data packet to ack packet */
#define MY_ACK_COPIED 4
 
/* The Ethernet type of our packet. This is NOT OFFICIALLY REGISTERED type,
* however our protocol is:
* 1. experimental,
* 2. supposed to be used only in private networks
*/
#define MY_PROTO_ID 0xfade
 
static int max_slaves = 4;
module_param(max_slaves,int,1);
MODULE_PARM_DESC(max_slaves,"Maximum number of slave FPGA devices serviced by the system.");
 
static int proto_registered = 0; //Was the protocol registred? Should be deregistered at exit?
 
DEFINE_RWLOCK(slave_table_lock); //Used to protect table of slaves
 
/* Structure used to store offset of two currently serviced sets in the data buffer */
struct pkt_map {
int num;
int offset;
};
 
typedef struct
{
// fields related to the circular buffer
volatile int head;
volatile int tail;
rwlock_t ptrs_lock; //Used to protect the head and tail pointers
 
unsigned char * buffer;
 
rwlock_t pkts_rwlock; //Protects the pkts table and last_pkt
int last_pkt; /* position of the last packet, which is still
replaced with the packet from the next set */
int pkts[PKTS_IN_SET];
 
rwlock_t maps_rwlock; //Protects the maps table
struct pkt_map maps[2];
 
rwlock_t flags_lock; //Protects other fields of the slave_data struct
char err_flag;
char active;
char is_open;
int rx_wakeup_thr;
unsigned char mac[ETH_ALEN];
struct net_device * dev;
} slave_data;
 
/*
* The array pkts holds the number of set, from which we expect the particulal packet
* (so we can safely start with this array filled with zeroes).
* After the packet is sent and acknowledged, we increase the number corresponding
* to this packet.
* At each moment this table may be filled with two different values - n, and n+1
* because we service two consecutive sets
*/
static slave_data * slave_table = NULL;
 
static int my_proto_rcv(struct sk_buff * skb, struct net_device * dev, struct packet_type * pt,
struct net_device * orig_dev);
 
static struct packet_type my_proto_pt __read_mostly = {
.type = cpu_to_be16(MY_PROTO_ID),
.dev = NULL,
.func = my_proto_rcv,
};
 
// Prototypes of functions defined in module
void cleanup_my_proto1( void );
int init_my_proto1( void );
static int my_proto1_open(struct inode *inode, struct file *file);
static int my_proto1_release(struct inode *inode, struct file *file);
static long my_proto1_ioctl (struct file *filp, unsigned int cmd, unsigned long arg);
int my_proto1_mmap(struct file *filp, struct vm_area_struct *vma);
unsigned int my_proto1_poll(struct file *filp,poll_table *wait);
 
//Wait queue for user application
DECLARE_WAIT_QUEUE_HEAD (read_queue);
 
dev_t my_dev=0;
struct cdev * my_cdev = NULL;
static struct class *class_my_proto = NULL;
 
struct file_operations Fops = {
.owner = THIS_MODULE,
.open=my_proto1_open,
.release=my_proto1_release, /* a.k.a. close */
.poll = my_proto1_poll,
.unlocked_ioctl=my_proto1_ioctl,
.mmap=my_proto1_mmap
};
 
static long my_proto1_ioctl (struct file *filp,
unsigned int cmd, unsigned long arg)
{
slave_data * sd = filp->private_data;
if (_IOC_TYPE(cmd) != L3_V1_IOC_MAGIC) {
return -EINVAL;
}
switch (cmd) {
case L3_V1_IOC_SETWAKEUP:
if (arg > MY_BUF_LEN/2)
return -EINVAL; //Don't allow to set too high read threshold!
write_lock_bh(&sd->flags_lock);
sd->rx_wakeup_thr = arg;
write_unlock_bh(&sd->flags_lock);
return 0;
case L3_V1_IOC_GETBUFLEN:
/* Inform the user application about the length of the buffer */
return MY_BUF_LEN;
case L3_V1_IOC_READPTRS:
{
void * res = (void *) arg;
struct l3_v1_buf_pointers bp;
if (!access_ok(VERIFY_WRITE,res,sizeof(bp))) {
return -EFAULT;
} else {
read_lock_bh(&sd->ptrs_lock);
bp.head=sd->head;
bp.tail=sd->tail;
read_unlock_bh(&sd->ptrs_lock);
__copy_to_user(res,&bp,sizeof(bp));
if (sd->err_flag)
return -EIO; /* In this case user must him/herself
calculate the number of available bytes */
else
return (bp.head-bp.tail) & MY_BUF_LEN_MASK;
/* Return the number of available bytes */
}
}
case L3_V1_IOC_WRITEPTRS:
/* Update the read pointer
* The argument contains information about the number of bytes
* consumed by the application
*/
{
int rptr;
int wptr;
int available_data;
//We need to check if the amount of consumed data is correct
write_lock_bh(&sd->ptrs_lock);
wptr = sd->head;
rptr = sd->tail;
available_data = (wptr - rptr) & MY_BUF_LEN_MASK;
if (arg>available_data)
{
write_unlock_bh(&sd->ptrs_lock);
return -EINVAL;
}
//If the number of consumed bytes is correct, update the number of bytes
sd->tail = (rptr + arg) & MY_BUF_LEN_MASK;
write_unlock_bh(&sd->ptrs_lock);
return SUCCESS;
}
case L3_V1_IOC_STARTMAC: //Open the slave
{
void * source = (void *) arg;
struct l3_v1_slave sl;
struct sk_buff *newskb = NULL;
struct net_device *dev = NULL;
char * my_data = NULL;
if (!access_ok(VERIFY_READ,source,sizeof(sl))) {
return -EFAULT;
}
/* First deactivate the slave to avoid situation where data are modified
* while slave is active */
if (sd->active) sd->active = 0;
/* Prepare the data structure for reception of packets */
write_lock_bh(&sd->maps_rwlock);
sd->maps[0].num = 0;
sd->maps[0].offset = 0;
sd->maps[1].num=1;
sd->maps[1].offset = PKTS_IN_SET*USER_LEN;
write_unlock_bh(&sd->maps_rwlock);
write_lock_bh(&sd->pkts_rwlock);
memset(&sd->pkts,0,sizeof(sd->pkts));
sd->last_pkt=0;
write_unlock_bh(&sd->pkts_rwlock);
__copy_from_user(&sl,source,sizeof(sl));
write_lock_bh(&slave_table_lock);
/* Copy the MAC address */
memcpy(&sd->mac,sl.mac,ETH_ALEN);
sd->active = 1;
write_unlock_bh(&slave_table_lock);
/* Now send the "start transmission" packet to the slave */
/* Find the net device */
sl.devname[IFNAMSIZ-1]=0; // Protect against incorrect device name
if (sd->dev) {
//Maybe there was no STOPMAC call after previous STARTMAC?
dev_put(sd->dev);
sd->dev=NULL;
}
dev = dev_get_by_name(&init_net,sl.devname);
if (!dev) return -ENODEV;
sd->dev = dev;
newskb = alloc_skb(LL_RESERVED_SPACE(dev)+MY_ACK_LEN, GFP_ATOMIC);
skb_reserve(newskb,LL_RESERVED_SPACE(dev));
skb_reset_network_header(newskb);
newskb->dev = dev;
newskb->protocol = htons(MY_PROTO_ID);
//Build the MAC header for the new packet
// Based on http://lxr.linux.no/#linux+v3.3.4/net/ipv4/arp.c#L586 !
if (dev_hard_header(newskb,dev,MY_PROTO_ID,&sl.mac,dev->dev_addr,MY_ACK_LEN+ETH_HLEN) < 0) {
kfree_skb(newskb);
return -EINVAL;
}
//Put the "start" command to the packet
my_data = skb_put(newskb,2);
*(my_data++) = 0;
*(my_data++) = 1;
my_data = skb_put(newskb,MY_ACK_LEN -2);
memset(my_data,0xa5,MY_ACK_LEN - 2);
#ifdef FADE_DEBUG
printk(KERN_INFO "skb_nh: %x, skb_dt: %x, skb_nh2: %x, skb_t: %x\n tail: %d head: %d\n",skb_network_header(newskb),newskb->data,
newskb->network_header,newskb->tail, sd->tail, sd->head) ;
#endif
dev_queue_xmit(newskb);
return SUCCESS;
}
case L3_V1_IOC_STOPMAC: //Close the slave and reset it to stop transmission immediately
{
struct sk_buff *newskb = NULL;
char * my_data = NULL;
write_lock_bh(&slave_table_lock);
/* Clear the MAC address */
sd->active = 0;
memset(&sd->mac,0,ETH_ALEN);
write_unlock_bh(&slave_table_lock);
/* Now send the "stop transmission" packet to the slave */
/* Find the net device */
if (!sd->dev) return -ENODEV;
newskb = alloc_skb(LL_RESERVED_SPACE(sd->dev)+MY_ACK_LEN, GFP_ATOMIC);
skb_reserve(newskb,LL_RESERVED_SPACE(sd->dev));
skb_reset_network_header(newskb);
newskb->dev = sd->dev;
newskb->protocol = htons(MY_PROTO_ID);
//Build the MAC header for the new packet
// Based on http://lxr.linux.no/#linux+v3.3.4/net/ipv4/arp.c#L586 !
if (dev_hard_header(newskb,sd->dev,MY_PROTO_ID,&sd->mac,sd->dev->dev_addr,MY_ACK_LEN+ETH_HLEN) < 0) {
kfree_skb(newskb);
return -EINVAL;
}
//Put the "stop" command to the packet
my_data = skb_put(newskb,2);
*(my_data++) = 0;
*(my_data++) = 5;
my_data = skb_put(newskb,MY_ACK_LEN -2);
memset(my_data,0xa5,MY_ACK_LEN - 2);
#ifdef FADE_DEBUG
printk(KERN_INFO "skb_nh: %x, skb_dt: %x, skb_nh2: %x, skb_t: %x\n tail: %d head: %d\n",skb_network_header(newskb),newskb->data,
newskb->network_header,newskb->tail, sd->tail, sd->head) ;
#endif
dev_queue_xmit(newskb);
dev_put(sd->dev);
sd->dev=NULL;
return SUCCESS;
}
}
return -EINVAL;
}
/*
Implementation of the poll method
*/
unsigned int my_proto1_poll(struct file *filp,poll_table *wait)
{
unsigned int mask =0;
slave_data * sd = filp->private_data;
unsigned int data_available;
poll_wait(filp,&read_queue,wait);
read_lock_bh(&sd->ptrs_lock);
data_available = (sd->head - sd->tail) & MY_BUF_LEN_MASK;
if (data_available>=sd->rx_wakeup_thr) mask |= POLLIN |POLLRDNORM;
#ifdef FADE_DEBUG
printk(KERN_INFO "poll head: %d tail: %d data: %d prog: %d.\n",sd->head,sd->tail,data_available,sd->rx_wakeup_thr);
#endif
//Check if the error occured
if (sd->err_flag) mask |= POLLERR;
read_unlock_bh(&sd->ptrs_lock);
return mask;
}
 
/* Module initialization */
int init_my_proto1( void )
{
int res;
int i;
/* Create the device class for udev */
class_my_proto = class_create(THIS_MODULE, "my_proto");
if (IS_ERR(class_my_proto)) {
printk(KERN_ERR "Error creating my_proto class.\n");
res=PTR_ERR(class_my_proto);
goto err1;
}
/* Allocate the device number */
res=alloc_chrdev_region(&my_dev, 0, max_slaves, DEVICE_NAME);
if (res) {
printk (KERN_ERR "Alocation of the device number for %s failed\n",
DEVICE_NAME);
goto err1;
};
/* Allocate the character device structure */
my_cdev = cdev_alloc( );
if (my_cdev == NULL) {
printk (KERN_ERR "Allocation of cdev for %s failed\n",
DEVICE_NAME);
goto err1;
}
my_cdev->ops = &Fops;
my_cdev->owner = THIS_MODULE;
/* Add the character device to the system */
res=cdev_add(my_cdev, my_dev, max_slaves);
if (res) {
printk (KERN_ERR "Registration of the device number for %s failed\n",
DEVICE_NAME);
goto err1;
};
/* Create our devices in the system */
for (i=0;i<max_slaves;i++) {
device_create(class_my_proto,NULL,MKDEV(MAJOR(my_dev),MINOR(my_dev)+i),NULL,"l3_fpga%d",i);
}
printk (KERN_ERR "%s The major device number is %d.\n",
"Registration is a success.",
MAJOR(my_dev));
//Prepare the table of slaves
slave_table = kzalloc(sizeof(slave_data)*max_slaves, GFP_KERNEL);
if (!slave_table) return -ENOMEM;
for (i=0;i<max_slaves;i++) {
slave_data * sd = &slave_table[i];
sd->active=0; //Entry not used
sd->dev=NULL;
rwlock_init(&sd->maps_rwlock);
rwlock_init(&sd->pkts_rwlock);
rwlock_init(&sd->ptrs_lock);
rwlock_init(&sd->flags_lock);
}
//Install our protocol sniffer
dev_add_pack(&my_proto_pt);
proto_registered = 1;
return SUCCESS;
err1:
/* In case of error free all allocated resources */
cleanup_my_proto1();
return res;
}
 
module_init(init_my_proto1);
 
/* Clean-up when removing the module */
void cleanup_my_proto1( void )
{
/* Unregister the protocol sniffer */
if (proto_registered) dev_remove_pack(&my_proto_pt);
/* Free the slave table */
if (slave_table) {
int i;
for (i=0;i<max_slaves;i++) {
if (slave_table[i].buffer) {
vfree(slave_table[i].buffer);
slave_table[i].buffer = NULL;
}
if (slave_table[i].dev) {
dev_put(slave_table[i].dev);
slave_table[i].dev=NULL;
}
if (slave_table[i].active) {
slave_table[i].active = 0;
}
}
kfree(slave_table);
slave_table=NULL;
}
/* Remove device from the class */
if (my_dev && class_my_proto) {
int i;
for (i=0;i<max_slaves;i++) {
device_destroy(class_my_proto,MKDEV(MAJOR(my_dev),MINOR(my_dev)+i));
}
}
/* Deregister device */
if (my_cdev) cdev_del(my_cdev);
my_cdev=NULL;
/* Free the device number */
unregister_chrdev_region(my_dev, max_slaves);
/* Deregister class */
if (class_my_proto) {
class_destroy(class_my_proto);
class_my_proto=NULL;
}
 
}
module_exit(cleanup_my_proto1);
/*
Function, which receives my packet, copies the data and acknowledges the packet
as soon as possible...
I've tried to allow this function to handle multiple packets in parallel
in the SMP system, however I've used rwlocks for that.
Probably it should be improved, according to the last tendency to avoid
rwlocks in the kernel...
*/
 
static int my_proto_rcv(struct sk_buff * skb, struct net_device * dev, struct packet_type * pt,
struct net_device * orig_dev)
{
struct sk_buff *newskb = NULL;
struct ethhdr * rcv_hdr = NULL;
//unsigned int head;
//unsigned int tail;
int res;
unsigned int set_number;
unsigned int packet_number;
int ns; //Number of slave
slave_data * sd = NULL;
int set_num_diff;
unsigned int buf_free = 0;
char * my_data = NULL;
unsigned char tmp_buf[USER_HDR_LEN];
char ack_packet = 0; //Should we acknowledge the packet?
//Extract the MAC header from the received packet
rcv_hdr=eth_hdr(skb);
//First we try to identify the sender so we search the table of active slaves
//The table is protected during the search, so it should not be changed
#ifdef FADE_DEBUG
printk("snd: %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n",(int)rcv_hdr->h_source[0],
(int)rcv_hdr->h_source[1],(int)rcv_hdr->h_source[2],(int)rcv_hdr->h_source[3],
(int)rcv_hdr->h_source[4],(int)rcv_hdr->h_source[5]);
#endif
read_lock_bh(&slave_table_lock);
for (ns=0;ns<max_slaves;ns++) {
#ifdef FADE_DEBUG
printk("slv: %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x act: %d\n",
(int)slave_table[ns].mac[0],(int)slave_table[ns].mac[1],(int)slave_table[ns].mac[2],
(int)slave_table[ns].mac[3],(int)slave_table[ns].mac[4],(int)slave_table[ns].mac[5],
(int)slave_table[ns].active);
#endif
if (
slave_table[ns].active!=0 &&
memcmp(slave_table[ns].mac,rcv_hdr->h_source, sizeof(slave_table[0].mac))==0
) break;
}
read_unlock_bh(&slave_table_lock);
//Now we know which slave sent us the packet (ns<max_slaves) or that
//the packet came from an unknown slave (ns==max_slaves)
if (unlikely(ns==max_slaves)) {
printk(KERN_WARNING " Received packet from incorrect slave!\n");
//Sender is not opened, so ignore the packet, and send
//to the sender request to stop the transmission immediately
newskb = alloc_skb(LL_RESERVED_SPACE(dev)+MY_ACK_LEN, GFP_ATOMIC);
skb_reserve(newskb,LL_RESERVED_SPACE(dev));
skb_reset_network_header(newskb);
newskb->dev = dev;
newskb->protocol = htons(MY_PROTO_ID);
//Build the MAC header for the new packet
// Here is shown how to build a packet: http://lxr.linux.no/linux+*/net/ipv4/arp.c#L586
if (dev_hard_header(newskb,dev,MY_PROTO_ID,&rcv_hdr->h_source,&rcv_hdr->h_dest,MY_ACK_LEN+ETH_HLEN) < 0)
goto error;
//Put the "restart" command to the packet
my_data = skb_put(newskb,2);
*(my_data++) = 0;
*(my_data++) = 5;
my_data = skb_put(newskb,MY_ACK_LEN -2);
memset(my_data,0xa5,MY_ACK_LEN - 2);
dev_queue_xmit(newskb);
kfree_skb(skb);
return NET_RX_DROP;
}
sd = &slave_table[ns]; //To speed up access to the data describing state of the slave
#ifdef FADE_DEBUG
printk(KERN_INFO " Received packet!\n");
#endif
//Now we should analyze the origin and meaning of the packet
//To avoid problems with scattered packets, we copy initial part of data to the buffer
//using the skb_copy_bits
skb_copy_bits(skb,0,tmp_buf,USER_HDR_LEN);
/* We extract the information from the user header
* First we check if this is a data packet: */
if (unlikely((tmp_buf[0] != 0xa5) ||
(tmp_buf[1] != 0xa5))) {
kfree_skb(skb);
write_lock_bh(&sd->flags_lock);
sd->err_flag |= FADE_ERR_INCORRECT_PACKET_TYPE;
write_unlock_bh(&sd->flags_lock);
return NET_RX_DROP;
}
/* Now we check the set number and the packet number:
PLEASE NOTE, THAT THIS MUST TIGHTLY CORRESPOND
TO YOUR FPGA IMPLEMENTATION! */
set_number = (int)tmp_buf[2]*256+tmp_buf[3];
packet_number = ((int)tmp_buf[4]>>2);
#ifdef FADE_DEBUG
printk(KERN_INFO "set=%d pkt=%d\n",set_number,packet_number);
#endif
/* To know if this is a new packet, we compare the set number
* in the received packet with the expected set number,
* calculating the difference between those two numbers: */
read_lock_bh(&sd->pkts_rwlock);
set_num_diff=(set_number - sd->pkts[packet_number]) & SET_NUMBER_MASK;
read_unlock_bh(&sd->pkts_rwlock);
if (likely(set_num_diff==0)) {
/* This is the expected data packet. */
int set = -1;
/* Because we often handle two sets of packets
simultaneously, we use "set" variable to store the relative set number */
int needed_space;
/* We determine the relative set number: 1 or 0 */
read_lock_bh(&sd->maps_rwlock);
if (set_number == sd->maps[0].num) set = 0;
else if (set_number == sd->maps[1].num) set = 1;
//Set equal to -1 should never happen!
if (set==-1) {
printk(KERN_WARNING "Incorrect set number in received packet!\n");
read_unlock_bh(&sd->maps_rwlock);
write_lock_bh(&sd->flags_lock);
sd->err_flag |= FADE_ERR_INCORRECT_SET;
write_unlock_bh(&sd->flags_lock);
kfree_skb(skb);
return NET_RX_DROP;
}
/* Now we can calculate how much free space requires this packet
Amount of space is calculated between the byte after the received packet
and the byte pointed by the head pointer */
needed_space = (sd->maps[set].offset + USER_LEN*(packet_number+1) - sd->head) & MY_BUF_LEN_MASK;
read_unlock_bh(&sd->maps_rwlock); //We stop to use the "maps" table
read_lock_bh(&sd->ptrs_lock);
buf_free=( sd->tail - sd->head -1 ) & MY_BUF_LEN_MASK;
#ifdef FADE_DEBUG
printk(KERN_INFO "Offset: %d packet_nr: %d Free buffer: %d needed space: %d set=%d offset=%d head=%d last=%d\n",
sd->maps[set].offset, packet_number, buf_free, needed_space,set,sd->maps[set].offset,sd->head,sd->last_pkt);
#endif
read_unlock_bh(&sd->ptrs_lock);
if ( buf_free > needed_space ) {
int ackd_set_nr;
//Packet fits in the buffer!
// Length of the payload should be 1024+header???
if (skb->len != PAYL_LEN) {
printk(KERN_ERR "Error! Length of data should be %d but is %d!\n",PAYL_LEN, skb->len);
sd->err_flag |= FADE_ERR_INCORRECT_LENGTH;
kfree_skb(skb);
return NET_RX_DROP;
}
// We can safely copy all the packet to the buffer:
// As buffer's boundary never is located in the middle of the packet set,
// we can simply calculate the begining of the data in the buffer
// as &sd->buffer[sd->maps[set].offset+USER_LEN*packet_number
res = skb_copy_bits(skb,10,&sd->buffer[sd->maps[set].offset+USER_LEN*packet_number],USER_LEN);
#ifdef FADE_DEBUG
printk(KERN_INFO " skb_copy_bits: %d", res);
#endif
//Packet was copied, so note, that we should confirm it
if (res>=0) {
ack_packet=1;
/* We modify the expected set number for the packet, to modify the
* pkts table, we must close pkts_rwlock for writing */
write_lock_bh(&sd->pkts_rwlock);
ackd_set_nr = (set_number + 1) & SET_NUMBER_MASK;
sd->pkts[packet_number]= ackd_set_nr;
if (packet_number == sd->last_pkt) {
/* If our packet was the last, which prevented shifting of the head pointer,
* we can try now to move the head pointer.
* We browse the pkts table, looking for the first uncorfirmed packet.
*/
while ((++(sd->last_pkt)) < PKTS_IN_SET) {
if (sd->pkts[sd->last_pkt] != ackd_set_nr) break; //Packet not confirmed
}
if (sd->last_pkt == PKTS_IN_SET) {
/* All packets from the "old" set are received, so we can change
* the set_nr
*/
sd->last_pkt = 0;
/* Update the maps table. Remove the 0th set, move the 1st to the 0th.
* Add the new set as the 1st one */
write_lock_bh(&sd->maps_rwlock);
memcpy(&sd->maps[0],&sd->maps[1],sizeof(sd->maps[0]));
sd->maps[1].num = (sd->maps[1].num + 1) & SET_NUMBER_MASK;
sd->maps[1].offset = (sd->maps[1].offset + USER_LEN*PKTS_IN_SET) & MY_BUF_LEN_MASK;
write_unlock_bh(&sd->maps_rwlock);
/* Now we need to check for confirmed packet from the next set */
ackd_set_nr = (ackd_set_nr + 1) & SET_NUMBER_MASK;
while (sd->last_pkt < PKTS_IN_SET) {
if (sd->pkts[sd->last_pkt] != ackd_set_nr) break; //Packet not cofirmed
else sd->last_pkt++;
}
write_unlock_bh(&sd->pkts_rwlock);
} else {
//No need to change packet sets, simply release the lock
write_unlock_bh(&sd->pkts_rwlock);
}
/* Now we can move the head position right after the last serviced packet */
write_lock_bh(&sd->ptrs_lock);
sd->head = sd->maps[0].offset+sd->last_pkt*USER_LEN;
/* When we have moved the head pointer, we can try to wake up the reading processes */
wake_up_interruptible(&read_queue);
write_unlock_bh(&sd->ptrs_lock);
} else {
// It was not the last packet, no need to move the head pointer
write_unlock_bh(&sd->pkts_rwlock);
}
}
}
} else {
/* This packet has incorrect set number. If the number is too low, we ignore the packet,
* but send the confirmation (ack was received too late, or was lost?) */
if (set_num_diff>(SET_NUMBER/2)) {
/* In fact it means, that set_num_diff is negative, but we calculate
* it modulo SET_NUMBER! */
ack_packet = 1;
#ifdef FADE_DEBUG
printk(KERN_INFO "Packet already confirmed: pkt=%d set=%d expect=%d last=%d\n",packet_number, set_number, sd->pkts[packet_number], sd->last_pkt);
#endif
} else {
/* This is a packet with too high set number (packet "from the future"
* it my be a symptom of serious communication problem! */
printk(KERN_ERR "Packet from the future! number: %d expected: %d\n", set_number, sd->pkts[packet_number]);
}
}
//Now send the confirmation
if (likely(ack_packet)) {
newskb = alloc_skb(LL_RESERVED_SPACE(dev)+MY_ACK_LEN, GFP_ATOMIC);
skb_reserve(newskb,LL_RESERVED_SPACE(dev));
skb_reset_network_header(newskb);
newskb->dev = dev;
newskb->protocol = htons(MY_PROTO_ID);
//Build the MAC header for the new packet
// Tu http://lxr.linux.no/linux+*/net/ipv4/arp.c#L586 jest pokazane jak zbudować pakiet!
if (dev_hard_header(newskb,dev,MY_PROTO_ID,&rcv_hdr->h_source,&rcv_hdr->h_dest,MY_ACK_LEN+ETH_HLEN) < 0)
goto error;
//Put the "ACKNOWLEDGE" type
my_data = skb_put(newskb,2);
*(my_data++) = 0;
*(my_data++) = 3; //ACK!
//Copy the begining of the received packet to the acknowledge packet
my_data = skb_put(newskb,MY_ACK_COPIED);
res = skb_copy_bits(skb,2,my_data,MY_ACK_COPIED);
my_data = skb_put(newskb,MY_ACK_LEN -MY_ACK_COPIED-2);
memset(my_data,0xa5,MY_ACK_LEN - MY_ACK_COPIED-2);
#ifdef FADE_DEBUG
printk(KERN_INFO " skb_nh: %x, skb_dt: %x, skb_nh2: %x, skb_t: %x\n tail: %d head: %d\n",skb_network_header(newskb),newskb->data,
newskb->network_header,newskb->tail, sd->tail, sd->head) ;
#endif
dev_queue_xmit(newskb);
}
kfree_skb(skb);
return NET_RX_SUCCESS;
 
error:
if (newskb) kfree_skb(newskb);
if (skb) kfree_skb(skb);
return NET_RX_DROP;
}
 
/*
Implementation of the "device open" function
*/
static int my_proto1_open(struct inode *inode,
struct file *file)
{
int i;
slave_data * sd = NULL;
unsigned long flags;
i=iminor(inode)-MINOR(my_dev);
if (i >= max_slaves) {
printk(KERN_WARNING "Trying to access %s slave with too high minor number: %d\n",
DEVICE_NAME, i);
return -ENODEV;
}
read_lock_irqsave(&slave_table_lock,flags);
sd = &slave_table[i];
//Each device may be opened only once!
if (sd->is_open) {
return -EBUSY;
read_unlock_irqrestore(&slave_table_lock,flags);
}
//Prepare slave_table for operation
read_unlock_irqrestore(&slave_table_lock,flags);
sd->buffer = vmalloc_user(MY_BUF_LEN);
if (!sd->buffer) return -ENOMEM;
//Set the MAC address to 0
memset(sd->mac,0,sizeof(sd->mac));
sd->head = 0;
sd->tail = 0;
sd->err_flag = 0;
sd->last_pkt = 0;
sd->rx_wakeup_thr = 1;
sd->active = 0;
sd->is_open = 1;
file->private_data=sd;
return SUCCESS;
}
 
 
static int my_proto1_release(struct inode *inode,
struct file *file)
{
slave_data * sd = file->private_data;
#ifdef FADE_DEBUG
printk (KERN_INFO "device_release(%p,%p)\n", inode, file);
#endif
//Release resources associated with servicing of the particular device
if (sd) {
if (sd->is_open) {
sd->is_open = 0; //It can be dangerous! Before freeing the buffer, we must be sure, that
//no our packet is being processed!
if (sd->active) {
sd->active = 0;
}
if (sd->buffer) {
vfree(sd->buffer);
sd->buffer = NULL;
}
}
}
return SUCCESS;
}
 
/* Memory mapping */
void my_proto1_vma_open (struct vm_area_struct * area)
{ }
 
void my_proto1_vma_close (struct vm_area_struct * area)
{ }
 
static struct vm_operations_struct my_proto1_vm_ops = {
my_proto1_vma_open,
my_proto1_vma_close,
};
 
/*
mmap method implementation
*/
int my_proto1_mmap(struct file *filp,
struct vm_area_struct *vma)
{
slave_data * sd = filp->private_data;
unsigned long vsize = vma->vm_end - vma->vm_start;
unsigned long psize = MY_BUF_LEN;
if (vsize>psize)
return -EINVAL;
remap_vmalloc_range(vma,sd->buffer, 0);
if (vma->vm_ops)
return -EINVAL; //It should never happen...
vma->vm_ops = &my_proto1_vm_ops;
my_proto1_vma_open(vma); //No open(vma) was called, we have called it ourselves
return 0;
}
 
/fade_ether_protocol/trunk/experimental_fade_10g/linux/Makefile
0,0 → 1,9
ifneq ($(KERNELRELEASE),)
obj-m := fpga_l3_fade.o
else
KDIR := /lib/modules/$(shell uname -r)/build
PWD := $(shell pwd)
default:
$(MAKE) -C $(KDIR) SUBDIRS=$(PWD) modules
gcc -O2 -o receiver2 receiver2.c
endif
/fade_ether_protocol/trunk/experimental_fade_10g/fpga/ten_gig_eth_pcs_pma_0.xci
0,0 → 1,50
<?xml version="1.0" encoding="UTF-8"?>
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>xilinx.com</spirit:vendor>
<spirit:library>xci</spirit:library>
<spirit:name>unknown</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:componentInstances>
<spirit:componentInstance>
<spirit:instanceName>ten_gig_eth_pcs_pma_0</spirit:instanceName>
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="ten_gig_eth_pcs_pma" spirit:version="4.1"/>
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">ten_gig_eth_pcs_pma_0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MDIO_Management">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.base_kr">BASE-R</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.autonegotiation">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.fec">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IEEE_1588">None</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SupportLevel">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TransceiverControl">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_family">kintex7</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_component_name">ten_gig_eth_pcs_pma_0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_has_mdio">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_has_fec">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_has_an">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_is_kr">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gttype">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_1588">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_data_width">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_sub_core_name">ten_gig_eth_pcs_pma_0_gt</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k325t</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USER_REPO_PATHS"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD">xilinx.com:kintex7:kc705:1.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2013.4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
</spirit:configurableElementValues>
</spirit:componentInstance>
</spirit:componentInstances>
</spirit:design>
/fade_ether_protocol/trunk/experimental_fade_10g/fpga/dpram_inf.vhd
0,0 → 1,61
-- A parameterized, inferable, true dual-port, common-clock block RAM in VHDL.
-- Original file was taken from: http://danstrother.com/2010/09/11/inferring-rams-in-fpgas/
-- No license information were provided by the original author.
-- Minimal modifications were introduced by me to make it suitable for my FPGA
-- interface.
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity dp_ram_scl is
generic (
DATA_WIDTH : integer := 72;
ADDR_WIDTH : integer := 10
);
port (
-- Port A
clk_a : in std_logic;
we_a : in std_logic;
addr_a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
data_a : in std_logic_vector(DATA_WIDTH-1 downto 0);
q_a : out std_logic_vector(DATA_WIDTH-1 downto 0);
 
-- Port B
clk_b : in std_logic;
we_b : in std_logic;
addr_b : in std_logic_vector(ADDR_WIDTH-1 downto 0);
data_b : in std_logic_vector(DATA_WIDTH-1 downto 0);
q_b : out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end dp_ram_scl;
 
architecture rtl of dp_ram_scl is
-- Shared memory
type mem_type is array ((2**ADDR_WIDTH)-1 downto 0) of std_logic_vector(DATA_WIDTH-1 downto 0);
shared variable mem : mem_type;
begin
 
-- Port A
process(clk_a)
begin
if(clk_a'event and clk_a = '1') then
if(we_a = '1') then
mem(conv_integer(addr_a)) := data_a;
end if;
q_a <= mem(conv_integer(addr_a));
end if;
end process;
 
-- Port B
process(clk_b)
begin
if(clk_b'event and clk_b = '1') then
if(we_b = '1') then
mem(conv_integer(addr_b)) := data_b;
end if;
q_b <= mem(conv_integer(addr_b));
end if;
end process;
 
end rtl;
/fade_ether_protocol/trunk/experimental_fade_10g/fpga/desc_manager_simple.vhd
0,0 → 1,592
-------------------------------------------------------------------------------
-- Title : FPGA Ethernet interface - descriptor manager
-- Project :
-------------------------------------------------------------------------------
-- File : desc_manager.vhd
-- Author : Wojciech M. Zabolotny (wzab@ise.pw.edu.pl)
-- License : BSD License
-- Company :
-- Created : 2012-03-30
-- Last update: 2014-04-20
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: This file implements the state machine, which manages the
-- table of packet descriptors, used to resend only not confirmed packets
-------------------------------------------------------------------------------
-- Copyright (c) 2012
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-03-30 1.0 WZab Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use ieee.std_logic_textio.all;
library work;
use work.pkt_ack_pkg.all;
 
package desc_mgr_pkg is
 
constant LOG2_N_OF_PKTS : integer := 5;
constant N_OF_PKTS : integer := 2**LOG2_N_OF_PKTS;
constant LOG2_NWRDS_IN_PKT : integer := 10;
constant NWRDS_IN_PKT : integer := 1024;
constant N_OF_SETS : integer := 65536;
 
type T_PKT_DESC is record
set : integer range 0 to N_OF_SETS-1; -- number of sets
confirmed : std_logic;
valid : std_logic;
sent : std_logic;
end record;
 
end desc_mgr_pkg;
 
 
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
library work;
use work.pkt_ack_pkg.all;
use work.desc_mgr_pkg.all;
 
-- The below implementation of the descriptor memory is awfull,
-- but seemed to be necessary to force XST to infer it as an
-- single port BRAM.
-- I simply provide vector long enough to accomodate my T_PKT_DESC
-- type, and hope that the synthesis tool (XST) will optimize out
-- unused bits.should be inferred as block memory (so be carefull
-- when modifying the below process)!
 
entity desc_memory is
 
port (
clk : in std_logic;
desc_we : in std_logic;
desc_addr : in integer range 0 to N_OF_PKTS-1;
desc_out : in T_PKT_DESC;
desc_in : out T_PKT_DESC);
 
end desc_memory;
 
architecture beh1 of desc_memory is
 
type T_PKT_DESC_MEM is array (0 to N_OF_PKTS-1) of unsigned(22 downto 0);
signal desc_mem : T_PKT_DESC_MEM := (others => (others => '0'));
signal din : unsigned(22 downto 0) := (others => '0');
signal dout : unsigned(22 downto 0) := (others => '0');
signal rdaddr : integer range 0 to N_OF_PKTS-1;
begin -- beh1
 
process (desc_out, dout)
begin -- process
din <= (others => '0');
din(22) <= desc_out.valid;
din(21) <= desc_out.confirmed;
din(20) <= desc_out.sent;
din(19 downto 0) <= to_unsigned(desc_out.set, 20);
desc_in.valid <= dout(22);
desc_in.confirmed <= dout(21);
desc_in.sent <= dout(20);
desc_in.set <= to_integer(dout(19 downto 0));
end process;
 
process (clk)
begin -- process
if (clk'event and clk = '1') then -- rising clock edge
if (desc_we = '1') then
desc_mem(desc_addr) <= din;
end if;
rdaddr <= desc_addr;
end if;
end process;
dout <= desc_mem(rdaddr);
 
end beh1;
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
library work;
use work.pkt_ack_pkg.all;
use work.desc_mgr_pkg.all;
 
entity desc_manager is
generic (
LOG2_N_OF_PKTS : integer := LOG2_N_OF_PKTS;
N_OF_PKTS : integer := N_OF_PKTS
); -- Number of packet_logi buffers
 
port (
-- Data input interface
dta : in std_logic_vector(63 downto 0);
dta_we : in std_logic;
dta_ready : out std_logic;
-- ETH Sender interface
set_number : out unsigned(15 downto 0);
pkt_number : out unsigned(15 downto 0);
snd_start : out std_logic;
snd_ready : in std_logic;
 
-- Data memory interface
dmem_addr : out std_logic_vector(LOG2_NWRDS_IN_PKT+LOG2_N_OF_PKTS-1 downto 0);
dmem_dta : out std_logic_vector(63 downto 0);
dmem_we : out std_logic;
-- Interface to the ACK FIFO
ack_fifo_empty : in std_logic;
ack_fifo_rd_en : out std_logic;
ack_fifo_dout : in std_logic_vector(pkt_ack_width-1 downto 0);
 
--
transmit_data : in std_logic;
transm_delay : out unsigned(31 downto 0);
 
--
clk : in std_logic;
rst_n : in std_logic);
 
end desc_manager;
 
architecture dmgr_a1 of desc_manager is
 
constant PKT_CNT_MAX : integer := 3000;
 
-- To simplify description of state machines, all registers are grouped
-- in a record:
 
type T_DESC_MGR_REGS is record
set : integer range 0 to N_OF_SETS-1;
cur_set : integer range 0 to N_OF_SETS-1;
all_pkt_count : integer range 0 to PKT_CNT_MAX;
retr_pkt_count : integer range 0 to PKT_CNT_MAX;
retr_delay : unsigned(31 downto 0);
transm_delay : unsigned(31 downto 0);
nxt : integer range 0 to N_OF_PKTS-1;
tail_ptr : integer range 0 to N_OF_PKTS-1;
head_ptr : integer range 0 to N_OF_PKTS-1;
retr_ptr : integer range 0 to N_OF_PKTS-1; -- buffer, which is retransmitted
-- when equal to head_ptr -
-- retransmission is finished
retr_nxt : integer range 0 to N_OF_PKTS-1; -- buffer, which will be
-- retransmitted next
-- when equal to head_ptr -- no retransmission
-- is performed
end record;
 
constant DESC_MGR_REGS_INI : T_DESC_MGR_REGS := (
retr_delay => (others => '0'),
transm_delay => to_unsigned(10000, 32),
all_pkt_count => 0,
retr_pkt_count => 0,
set => 0,
cur_set => 0,
nxt => 0,
tail_ptr => 0,
head_ptr => 0,
retr_ptr => 0,
retr_nxt => 0
);
 
-- To simplify setting of outputs of my Mealy state machine, all combinatorial
-- outputs are grouped in a record
type T_DESC_MGR_COMB is record
dta_buf_free : std_logic;
desc_addr : integer range 0 to N_OF_PKTS-1;
desc_we : std_logic;
ack_rd : std_logic;
snd_start : std_logic;
desc_out : T_PKT_DESC;
end record;
constant DESC_MGR_COMB_DEFAULT : T_DESC_MGR_COMB := (
dta_buf_free => '0',
desc_addr => 0,
desc_we => '0',
ack_rd => '0',
snd_start => '0',
desc_out => (confirmed => '0', valid => '0', sent => '0', set => 0)
);
 
type T_DESC_MGR_STATE is (ST_DMGR_IDLE, ST_DMGR_START, ST_DMGR_RST, ST_DMGR_RST1,
ST_DMGR_ACK1, ST_DMGR_INS1, ST_DMGR_INS2, ST_DMGR_ACK_TAIL,
ST_DMGR_ACK_TAIL_1,
ST_DMGR_RETR, ST_DMGR_RETR_2);
 
signal desc_in : T_PKT_DESC;
 
signal r, r_i : T_DESC_MGR_REGS := DESC_MGR_REGS_INI;
signal c : T_DESC_MGR_COMB;
signal dmgr_state, dmgr_state_next : T_DESC_MGR_STATE := ST_DMGR_RST;
attribute keep : string;
attribute keep of dmgr_state : signal is "true";
 
signal dta_buf_full : std_logic := '0';
 
signal ack_pkt_in : pkt_ack;
 
signal wrd_addr : integer range 0 to NWRDS_IN_PKT-1; -- We use 64-bit words, so the
-- data word address is between
-- 0 and 1023
 
component desc_memory
port (
clk : in std_logic;
desc_we : in std_logic;
desc_addr : in integer range 0 to N_OF_PKTS-1;
desc_out : in T_PKT_DESC;
desc_in : out T_PKT_DESC);
end component;
 
 
begin -- dmgr_a1
 
transm_delay <= r.transm_delay;
set_number <= to_unsigned(r.set, 16);
pkt_number <= to_unsigned(r.retr_ptr, 16);
dta_ready <= not dta_buf_full;
snd_start <= c.snd_start;
ack_fifo_rd_en <= c.ack_rd;
 
ack_pkt_in <= stlv_to_pkt_ack(ack_fifo_dout);
 
 
-- Packet descriptors are stored in the desc_memory
 
desc_memory_1 : desc_memory
port map (
clk => clk,
desc_we => c.desc_we,
desc_addr => c.desc_addr,
desc_out => c.desc_out,
desc_in => desc_in);
 
-- Process used to fill the buffer memory with the data to be transmitted
-- We simply write words to the memory buffer pointed by r.head_ptr
-- When we write the last (0xff-th) word, we signal that the buffer
-- is full. Only after reception of
dta_rcv : process (clk, rst_n)
begin -- process dta_rcv
if rst_n = '0' then -- asynchronous reset (active low)
wrd_addr <= 0;
dta_buf_full <= '0';
dmem_we <= '0';
elsif clk'event and clk = '1' then -- rising clock edge
dmem_we <= '0';
-- if we signalled "data full", we are only waiting for
-- dta_buf_free;
if dta_buf_full = '1' then
if c.dta_buf_free = '1' then
dta_buf_full <= '0';
wrd_addr <= 0;
end if;
else
-- if data write requested - write it
if dta_we = '1' then
dmem_addr <= std_logic_vector(to_unsigned(r.head_ptr, LOG2_N_OF_PKTS)) &
std_logic_vector(to_unsigned(wrd_addr, LOG2_NWRDS_IN_PKT));
dmem_we <= '1';
dmem_dta <= dta;
if wrd_addr < NWRDS_IN_PKT-1 then
wrd_addr <= wrd_addr + 1;
else
dta_buf_full <= '1';
end if;
end if;
end if;
end if;
end process dta_rcv;
 
 
c1 : process (ack_fifo_empty, ack_pkt_in, desc_in, dmgr_state, dta_buf_full,
r, snd_ready)
begin -- process c1
c <= DESC_MGR_COMB_DEFAULT; -- set defaults
r_i <= r; -- avoid latches
 
if r.retr_delay /= to_unsigned(0, r.retr_delay'length) then
r_i.retr_delay <= r.retr_delay-1;
end if;
dmgr_state_next <= dmgr_state;
-- State machine
case dmgr_state is
when ST_DMGR_RST =>
dmgr_state_next <= ST_DMGR_RST1;
when ST_DMGR_RST1 =>
-- We should initialize the 0th position of list descriptors
c.desc_addr <= r.head_ptr;
c.desc_out <= desc_in;
c.desc_out.confirmed <= '0';
c.desc_out.valid <= '0';
c.desc_out.sent <= '0';
c.desc_out.set <= 0;
c.desc_we <= '1';
dmgr_state_next <= ST_DMGR_IDLE;
when ST_DMGR_IDLE =>
-- First we check, if there are any packets to acknowledge
if ack_fifo_empty = '0' then
-- Read the description of the acknowledged packet
c.desc_addr <= to_integer(ack_pkt_in.pkt);
dmgr_state_next <= ST_DMGR_ACK1;
elsif dta_buf_full = '1' then
-- We should handle reception of data.
-- If the previously filled buffer is full, pass it for transmission,
-- and allocate the next one.
--
-- Calculate the number of the packet, which shoud be the next "head"
-- packet.
if r.head_ptr = N_OF_PKTS-1 then
r_i.nxt <= 0;
else
r_i.nxt <= r.head_ptr + 1;
end if;
-- Prepare for reading of the current "head" descriptor
c.desc_addr <= r.head_ptr;
dmgr_state_next <= ST_DMGR_INS1;
elsif (r.tail_ptr /= r.head_ptr) and (r.retr_delay = to_unsigned(0, r.retr_delay'length)) then
-- We need to (re)transmit some buffers
-- prepare reading of the descriptor, which should be transmitted
c.desc_addr <= r.retr_nxt;
dmgr_state_next <= ST_DMGR_RETR;
end if;
when ST_DMGR_INS1 =>
-- First we check, if there is free space, r.nxt is the number of the
-- future head packet.
if (r.nxt = r.tail_ptr) then
-- No free place! The packet, which we would like to fill is still
-- occupied.
-- Return to idle, waiting until something is freed.
-- In this case we should also force retransmission
if r.retr_delay = 0 then
c.desc_addr <= r.retr_nxt;
dmgr_state_next <= ST_DMGR_RETR;
else
dmgr_state_next <= ST_DMGR_IDLE;
end if;
else
-- We can fill the next buffer
-- First we mark the previous head packet
-- as valid and not confirmed
c.desc_addr <= r.head_ptr;
c.desc_out <= desc_in;
c.desc_out.confirmed <= '0';
c.desc_out.valid <= '1';
c.desc_we <= '1';
-- Now we move the "head" pointer
r_i.head_ptr <= r.nxt;
-- Increase the set number if we wrapped around
if r.nxt = 0 then
if r.cur_set = N_OF_SETS-1 then
r_i.cur_set <= 0;
else
r_i.cur_set <= r.cur_set + 1;
end if;
end if;
dmgr_state_next <= ST_DMGR_INS2;
end if;
when ST_DMGR_INS2 =>
-- We fill the new head descriptor
c.desc_addr <= r.head_ptr;
c.desc_out.set <= r.cur_set;
c.desc_out.confirmed <= '0';
c.desc_out.valid <= '0';
c.desc_out.sent <= '0';
c.desc_we <= '1';
-- Signal, that the buffer is freed
c.dta_buf_free <= '1';
dmgr_state_next <= ST_DMGR_IDLE;
when ST_DMGR_ACK1 =>
-- In this state the desc memory should respond with the data of the
-- buffered packet, so we can state, if this packet is really correctly
-- acknowledged (here we also ignore the NACK packets!
if (ack_pkt_in.set = desc_in.set) and
(ack_pkt_in.cmd = to_unsigned(3,ack_pkt_in.cmd'length)) and
(desc_in.valid = '1') then
-- This is really correct, unconfirmed packet
-- Increase the counter of not-repeated ACK packets
-- Write the confirmation
c.desc_addr <= to_integer(ack_pkt_in.pkt);
c.desc_out <= desc_in;
c.desc_out.valid <= '0';
c.desc_out.confirmed <= '1';
c.desc_we <= '1';
-- Here we also handle the case, if the acknowledged packet was
-- the one which is now scheduled for retransmission...
if ack_pkt_in.pkt = r.retr_nxt then
if r.retr_nxt < N_OF_PKTS-1 then
r_i.retr_nxt <= r.retr_nxt + 1;
else
r_i.retr_nxt <= 0;
end if;
end if;
-- Check, if we need to update the "tail" pointer
if r.tail_ptr = ack_pkt_in.pkt then
c.ack_rd <= '1';
dmgr_state_next <= ST_DMGR_ACK_TAIL;
else
c.ack_rd <= '1';
dmgr_state_next <= ST_DMGR_IDLE;
end if;
else
-- This packet was already confirmed or it was NACK
-- just flush the ack_fifo
c.ack_rd <= '1';
dmgr_state_next <= ST_DMGR_IDLE;
end if;
when ST_DMGR_ACK_TAIL =>
c.desc_addr <= r.tail_ptr;
dmgr_state_next <= ST_DMGR_ACK_TAIL_1;
when ST_DMGR_ACK_TAIL_1 =>
-- In this state we update the "tail" pointer if necessary
if r.tail_ptr /= r.head_ptr then
if desc_in.confirmed = '1' then
if r.tail_ptr < N_OF_PKTS-1 then
r_i.tail_ptr <= r.tail_ptr + 1;
c.desc_addr <= r.tail_ptr + 1;
else
r_i.tail_ptr <= 0;
c.desc_addr <= 0;
end if;
-- We remain in that state, to check the next packet descriptor
else
-- We return to idle
dmgr_state_next <= ST_DMGR_IDLE;
end if;
else
-- Buffer is empty - return to idle
dmgr_state_next <= ST_DMGR_IDLE;
end if;
when ST_DMGR_RETR =>
-- Here we handle the transmission of a new packet,
-- retransmission of not confirmed packet
-- We must be sure, that the transmitter is ready
if snd_ready = '0' then
-- transmitter not ready, return to idle
dmgr_state_next <= ST_DMGR_IDLE;
else
-- We will be able to send the next packet, but let's check if
-- this is not the currently filled packet
if r.retr_nxt = r.head_ptr then
-- All packets (re)transmitted, go to the begining of the list
-- and return to idle.
r_i.retr_nxt <= r.tail_ptr;
dmgr_state_next <= ST_DMGR_IDLE;
else
-- before jumping to ST_DMGR_RETR, the address bus
-- was set to the address of r.retr_nxt, so now
-- we can read the descriptor, and check if the packet
-- needs to be retransmitted at all...
r_i.set <= desc_in.set;
r_i.retr_ptr <= r.retr_nxt;
if r.retr_nxt < N_OF_PKTS-1 then
r_i.retr_nxt <= r.retr_nxt + 1;
else
r_i.retr_nxt <= 0;
end if;
if desc_in.valid = '1' and desc_in.confirmed = '0' then
if desc_in.sent = '1' then
-- Increase count of retransmitted packets for
-- adaptive adjustment of delay
if r.retr_pkt_count < PKT_CNT_MAX then
r_i.retr_pkt_count <= r.retr_pkt_count + 1;
end if;
end if;
-- Increase count of all packets for adaptive adjustment
-- of delay
if r.all_pkt_count < PKT_CNT_MAX then
r_i.all_pkt_count <= r.all_pkt_count + 1;
end if;
-- Mark the packet as sent
c.desc_addr <= r.retr_nxt;
c.desc_out <= desc_in;
c.desc_out.sent <= '1';
c.desc_we <= '1';
dmgr_state_next <= ST_DMGR_RETR_2;
else
dmgr_state_next <= ST_DMGR_IDLE;
end if;
end if;
end if;
when ST_DMGR_RETR_2 =>
-- In this state, we simply trigger the sender!
c.snd_start <= '1';
r_i.retr_delay <= r.transm_delay;
-- And we update the delay using the packet statistics
-- You may change the constants used in expressions
-- below to change speed of adjustment
if r.all_pkt_count >= PKT_CNT_MAX then
if r.retr_pkt_count < PKT_CNT_MAX/32 then
if r.transm_delay > 16 then
r_i.transm_delay <= r.transm_delay-r.transm_delay/16;
end if;
elsif r.retr_pkt_count > PKT_CNT_MAX/8 then
if r.transm_delay < 1000000 then
r_i.transm_delay <= r.transm_delay+r.transm_delay/4;
end if;
end if;
r_i.all_pkt_count <= 0;
r_i.retr_pkt_count <= 0;
end if;
dmgr_state_next <= ST_DMGR_IDLE;
when others => null;
end case;
end process c1;
 
-- Synchronous process
process (clk, rst_n)
begin -- process
if rst_n = '0' then -- asynchronous reset (active low)
r <= DESC_MGR_REGS_INI;
dmgr_state <= ST_DMGR_RST;
elsif clk'event and clk = '1' then -- rising clock edge
r <= r_i;
dmgr_state <= dmgr_state_next;
end if;
end process;
 
-- Process debugging the descriptors memory - for simulation only!
-- process (clk, rst_n)
-- variable L : line;
-- begin -- process
-- if rst_n = '0' then -- asynchronous reset (active low)
-- null;
-- elsif clk'event and clk = '1' then -- rising clock edge
-- if c.desc_we = '1' then
-- write(L, string'("nr="));
-- write(L, c.desc_addr);
-- write(L, string'(" set="));
-- write(L, c.desc_out.set);
-- write(L, string'(" valid="));
-- --write(L,c.desc_out.valid);
-- if c.desc_out.valid = '1' then
-- write(L, string'("1"));
-- else
-- write(L, string'("0"));
-- end if;
-- write(L, string'(" confirmed="));
-- --write(L,c.desc_out.valid);
-- if c.desc_out.confirmed = '1' then
-- write(L, string'("1"));
-- else
-- write(L, string'("0"));
-- end if;
-- write(L, string'(" r.tail="));
-- write(L, r.tail_ptr);
-- write(L, string'(" r.head="));
-- write(L, r.head_ptr);
-- writeline(output, L);
-- end if;
-- end if;
-- end process;
 
end dmgr_a1;
 
 
 
/fade_ether_protocol/trunk/experimental_fade_10g/fpga/PCK_CRC32_D32.vhd
0,0 → 1,86
--------------------------------------------------------------------------------
-- Copyright (C) 1999-2008 Easics NV.
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains the original copyright notice
-- and the associated disclaimer.
--
-- THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS
-- OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
-- WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
--
-- Purpose : synthesizable CRC function
-- * polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
-- * data width: 32
--
-- Info : tools@easics.be
-- http://www.easics.com
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
 
package PCK_CRC32_D32 is
-- polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
-- data width: 32
-- convention: the first serial bit is D[31]
function nextCRC32_D32
(Data: std_logic_vector(31 downto 0);
crc: std_logic_vector(31 downto 0))
return std_logic_vector;
end PCK_CRC32_D32;
 
 
package body PCK_CRC32_D32 is
 
-- polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
-- data width: 32
-- convention: the first serial bit is D[31]
function nextCRC32_D32
(Data: std_logic_vector(31 downto 0);
crc: std_logic_vector(31 downto 0))
return std_logic_vector is
 
variable d: std_logic_vector(31 downto 0);
variable c: std_logic_vector(31 downto 0);
variable newcrc: std_logic_vector(31 downto 0);
 
begin
d := Data;
c := crc;
 
newcrc(0) := d(31) xor d(30) xor d(29) xor d(28) xor d(26) xor d(25) xor d(24) xor d(16) xor d(12) xor d(10) xor d(9) xor d(6) xor d(0) xor c(0) xor c(6) xor c(9) xor c(10) xor c(12) xor c(16) xor c(24) xor c(25) xor c(26) xor c(28) xor c(29) xor c(30) xor c(31);
newcrc(1) := d(28) xor d(27) xor d(24) xor d(17) xor d(16) xor d(13) xor d(12) xor d(11) xor d(9) xor d(7) xor d(6) xor d(1) xor d(0) xor c(0) xor c(1) xor c(6) xor c(7) xor c(9) xor c(11) xor c(12) xor c(13) xor c(16) xor c(17) xor c(24) xor c(27) xor c(28);
newcrc(2) := d(31) xor d(30) xor d(26) xor d(24) xor d(18) xor d(17) xor d(16) xor d(14) xor d(13) xor d(9) xor d(8) xor d(7) xor d(6) xor d(2) xor d(1) xor d(0) xor c(0) xor c(1) xor c(2) xor c(6) xor c(7) xor c(8) xor c(9) xor c(13) xor c(14) xor c(16) xor c(17) xor c(18) xor c(24) xor c(26) xor c(30) xor c(31);
newcrc(3) := d(31) xor d(27) xor d(25) xor d(19) xor d(18) xor d(17) xor d(15) xor d(14) xor d(10) xor d(9) xor d(8) xor d(7) xor d(3) xor d(2) xor d(1) xor c(1) xor c(2) xor c(3) xor c(7) xor c(8) xor c(9) xor c(10) xor c(14) xor c(15) xor c(17) xor c(18) xor c(19) xor c(25) xor c(27) xor c(31);
newcrc(4) := d(31) xor d(30) xor d(29) xor d(25) xor d(24) xor d(20) xor d(19) xor d(18) xor d(15) xor d(12) xor d(11) xor d(8) xor d(6) xor d(4) xor d(3) xor d(2) xor d(0) xor c(0) xor c(2) xor c(3) xor c(4) xor c(6) xor c(8) xor c(11) xor c(12) xor c(15) xor c(18) xor c(19) xor c(20) xor c(24) xor c(25) xor c(29) xor c(30) xor c(31);
newcrc(5) := d(29) xor d(28) xor d(24) xor d(21) xor d(20) xor d(19) xor d(13) xor d(10) xor d(7) xor d(6) xor d(5) xor d(4) xor d(3) xor d(1) xor d(0) xor c(0) xor c(1) xor c(3) xor c(4) xor c(5) xor c(6) xor c(7) xor c(10) xor c(13) xor c(19) xor c(20) xor c(21) xor c(24) xor c(28) xor c(29);
newcrc(6) := d(30) xor d(29) xor d(25) xor d(22) xor d(21) xor d(20) xor d(14) xor d(11) xor d(8) xor d(7) xor d(6) xor d(5) xor d(4) xor d(2) xor d(1) xor c(1) xor c(2) xor c(4) xor c(5) xor c(6) xor c(7) xor c(8) xor c(11) xor c(14) xor c(20) xor c(21) xor c(22) xor c(25) xor c(29) xor c(30);
newcrc(7) := d(29) xor d(28) xor d(25) xor d(24) xor d(23) xor d(22) xor d(21) xor d(16) xor d(15) xor d(10) xor d(8) xor d(7) xor d(5) xor d(3) xor d(2) xor d(0) xor c(0) xor c(2) xor c(3) xor c(5) xor c(7) xor c(8) xor c(10) xor c(15) xor c(16) xor c(21) xor c(22) xor c(23) xor c(24) xor c(25) xor c(28) xor c(29);
newcrc(8) := d(31) xor d(28) xor d(23) xor d(22) xor d(17) xor d(12) xor d(11) xor d(10) xor d(8) xor d(4) xor d(3) xor d(1) xor d(0) xor c(0) xor c(1) xor c(3) xor c(4) xor c(8) xor c(10) xor c(11) xor c(12) xor c(17) xor c(22) xor c(23) xor c(28) xor c(31);
newcrc(9) := d(29) xor d(24) xor d(23) xor d(18) xor d(13) xor d(12) xor d(11) xor d(9) xor d(5) xor d(4) xor d(2) xor d(1) xor c(1) xor c(2) xor c(4) xor c(5) xor c(9) xor c(11) xor c(12) xor c(13) xor c(18) xor c(23) xor c(24) xor c(29);
newcrc(10) := d(31) xor d(29) xor d(28) xor d(26) xor d(19) xor d(16) xor d(14) xor d(13) xor d(9) xor d(5) xor d(3) xor d(2) xor d(0) xor c(0) xor c(2) xor c(3) xor c(5) xor c(9) xor c(13) xor c(14) xor c(16) xor c(19) xor c(26) xor c(28) xor c(29) xor c(31);
newcrc(11) := d(31) xor d(28) xor d(27) xor d(26) xor d(25) xor d(24) xor d(20) xor d(17) xor d(16) xor d(15) xor d(14) xor d(12) xor d(9) xor d(4) xor d(3) xor d(1) xor d(0) xor c(0) xor c(1) xor c(3) xor c(4) xor c(9) xor c(12) xor c(14) xor c(15) xor c(16) xor c(17) xor c(20) xor c(24) xor c(25) xor c(26) xor c(27) xor c(28) xor c(31);
newcrc(12) := d(31) xor d(30) xor d(27) xor d(24) xor d(21) xor d(18) xor d(17) xor d(15) xor d(13) xor d(12) xor d(9) xor d(6) xor d(5) xor d(4) xor d(2) xor d(1) xor d(0) xor c(0) xor c(1) xor c(2) xor c(4) xor c(5) xor c(6) xor c(9) xor c(12) xor c(13) xor c(15) xor c(17) xor c(18) xor c(21) xor c(24) xor c(27) xor c(30) xor c(31);
newcrc(13) := d(31) xor d(28) xor d(25) xor d(22) xor d(19) xor d(18) xor d(16) xor d(14) xor d(13) xor d(10) xor d(7) xor d(6) xor d(5) xor d(3) xor d(2) xor d(1) xor c(1) xor c(2) xor c(3) xor c(5) xor c(6) xor c(7) xor c(10) xor c(13) xor c(14) xor c(16) xor c(18) xor c(19) xor c(22) xor c(25) xor c(28) xor c(31);
newcrc(14) := d(29) xor d(26) xor d(23) xor d(20) xor d(19) xor d(17) xor d(15) xor d(14) xor d(11) xor d(8) xor d(7) xor d(6) xor d(4) xor d(3) xor d(2) xor c(2) xor c(3) xor c(4) xor c(6) xor c(7) xor c(8) xor c(11) xor c(14) xor c(15) xor c(17) xor c(19) xor c(20) xor c(23) xor c(26) xor c(29);
newcrc(15) := d(30) xor d(27) xor d(24) xor d(21) xor d(20) xor d(18) xor d(16) xor d(15) xor d(12) xor d(9) xor d(8) xor d(7) xor d(5) xor d(4) xor d(3) xor c(3) xor c(4) xor c(5) xor c(7) xor c(8) xor c(9) xor c(12) xor c(15) xor c(16) xor c(18) xor c(20) xor c(21) xor c(24) xor c(27) xor c(30);
newcrc(16) := d(30) xor d(29) xor d(26) xor d(24) xor d(22) xor d(21) xor d(19) xor d(17) xor d(13) xor d(12) xor d(8) xor d(5) xor d(4) xor d(0) xor c(0) xor c(4) xor c(5) xor c(8) xor c(12) xor c(13) xor c(17) xor c(19) xor c(21) xor c(22) xor c(24) xor c(26) xor c(29) xor c(30);
newcrc(17) := d(31) xor d(30) xor d(27) xor d(25) xor d(23) xor d(22) xor d(20) xor d(18) xor d(14) xor d(13) xor d(9) xor d(6) xor d(5) xor d(1) xor c(1) xor c(5) xor c(6) xor c(9) xor c(13) xor c(14) xor c(18) xor c(20) xor c(22) xor c(23) xor c(25) xor c(27) xor c(30) xor c(31);
newcrc(18) := d(31) xor d(28) xor d(26) xor d(24) xor d(23) xor d(21) xor d(19) xor d(15) xor d(14) xor d(10) xor d(7) xor d(6) xor d(2) xor c(2) xor c(6) xor c(7) xor c(10) xor c(14) xor c(15) xor c(19) xor c(21) xor c(23) xor c(24) xor c(26) xor c(28) xor c(31);
newcrc(19) := d(29) xor d(27) xor d(25) xor d(24) xor d(22) xor d(20) xor d(16) xor d(15) xor d(11) xor d(8) xor d(7) xor d(3) xor c(3) xor c(7) xor c(8) xor c(11) xor c(15) xor c(16) xor c(20) xor c(22) xor c(24) xor c(25) xor c(27) xor c(29);
newcrc(20) := d(30) xor d(28) xor d(26) xor d(25) xor d(23) xor d(21) xor d(17) xor d(16) xor d(12) xor d(9) xor d(8) xor d(4) xor c(4) xor c(8) xor c(9) xor c(12) xor c(16) xor c(17) xor c(21) xor c(23) xor c(25) xor c(26) xor c(28) xor c(30);
newcrc(21) := d(31) xor d(29) xor d(27) xor d(26) xor d(24) xor d(22) xor d(18) xor d(17) xor d(13) xor d(10) xor d(9) xor d(5) xor c(5) xor c(9) xor c(10) xor c(13) xor c(17) xor c(18) xor c(22) xor c(24) xor c(26) xor c(27) xor c(29) xor c(31);
newcrc(22) := d(31) xor d(29) xor d(27) xor d(26) xor d(24) xor d(23) xor d(19) xor d(18) xor d(16) xor d(14) xor d(12) xor d(11) xor d(9) xor d(0) xor c(0) xor c(9) xor c(11) xor c(12) xor c(14) xor c(16) xor c(18) xor c(19) xor c(23) xor c(24) xor c(26) xor c(27) xor c(29) xor c(31);
newcrc(23) := d(31) xor d(29) xor d(27) xor d(26) xor d(20) xor d(19) xor d(17) xor d(16) xor d(15) xor d(13) xor d(9) xor d(6) xor d(1) xor d(0) xor c(0) xor c(1) xor c(6) xor c(9) xor c(13) xor c(15) xor c(16) xor c(17) xor c(19) xor c(20) xor c(26) xor c(27) xor c(29) xor c(31);
newcrc(24) := d(30) xor d(28) xor d(27) xor d(21) xor d(20) xor d(18) xor d(17) xor d(16) xor d(14) xor d(10) xor d(7) xor d(2) xor d(1) xor c(1) xor c(2) xor c(7) xor c(10) xor c(14) xor c(16) xor c(17) xor c(18) xor c(20) xor c(21) xor c(27) xor c(28) xor c(30);
newcrc(25) := d(31) xor d(29) xor d(28) xor d(22) xor d(21) xor d(19) xor d(18) xor d(17) xor d(15) xor d(11) xor d(8) xor d(3) xor d(2) xor c(2) xor c(3) xor c(8) xor c(11) xor c(15) xor c(17) xor c(18) xor c(19) xor c(21) xor c(22) xor c(28) xor c(29) xor c(31);
newcrc(26) := d(31) xor d(28) xor d(26) xor d(25) xor d(24) xor d(23) xor d(22) xor d(20) xor d(19) xor d(18) xor d(10) xor d(6) xor d(4) xor d(3) xor d(0) xor c(0) xor c(3) xor c(4) xor c(6) xor c(10) xor c(18) xor c(19) xor c(20) xor c(22) xor c(23) xor c(24) xor c(25) xor c(26) xor c(28) xor c(31);
newcrc(27) := d(29) xor d(27) xor d(26) xor d(25) xor d(24) xor d(23) xor d(21) xor d(20) xor d(19) xor d(11) xor d(7) xor d(5) xor d(4) xor d(1) xor c(1) xor c(4) xor c(5) xor c(7) xor c(11) xor c(19) xor c(20) xor c(21) xor c(23) xor c(24) xor c(25) xor c(26) xor c(27) xor c(29);
newcrc(28) := d(30) xor d(28) xor d(27) xor d(26) xor d(25) xor d(24) xor d(22) xor d(21) xor d(20) xor d(12) xor d(8) xor d(6) xor d(5) xor d(2) xor c(2) xor c(5) xor c(6) xor c(8) xor c(12) xor c(20) xor c(21) xor c(22) xor c(24) xor c(25) xor c(26) xor c(27) xor c(28) xor c(30);
newcrc(29) := d(31) xor d(29) xor d(28) xor d(27) xor d(26) xor d(25) xor d(23) xor d(22) xor d(21) xor d(13) xor d(9) xor d(7) xor d(6) xor d(3) xor c(3) xor c(6) xor c(7) xor c(9) xor c(13) xor c(21) xor c(22) xor c(23) xor c(25) xor c(26) xor c(27) xor c(28) xor c(29) xor c(31);
newcrc(30) := d(30) xor d(29) xor d(28) xor d(27) xor d(26) xor d(24) xor d(23) xor d(22) xor d(14) xor d(10) xor d(8) xor d(7) xor d(4) xor c(4) xor c(7) xor c(8) xor c(10) xor c(14) xor c(22) xor c(23) xor c(24) xor c(26) xor c(27) xor c(28) xor c(29) xor c(30);
newcrc(31) := d(31) xor d(30) xor d(29) xor d(28) xor d(27) xor d(25) xor d(24) xor d(23) xor d(15) xor d(11) xor d(9) xor d(8) xor d(5) xor c(5) xor c(8) xor c(9) xor c(11) xor c(15) xor c(23) xor c(24) xor c(25) xor c(27) xor c(28) xor c(29) xor c(30) xor c(31);
return newcrc;
end nextCRC32_D32;
 
end PCK_CRC32_D32;
/fade_ether_protocol/trunk/experimental_fade_10g/fpga/ack_fifo.xci
0,0 → 1,387
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RDCH_TYPE">FIFO</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_APPLICATION_TYPE_RDCH">Data_FIFO</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_EMPTY_TYPE_RDCH">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXIS_TYPE">FIFO</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_FULL_TYPE_AXIS">No_Programmable_Full_Threshold</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_EMPTY_TYPE_AXIS">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EMPTY_THRESHOLD_ASSERT_VALUE_AXIS">1022</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REGISTER_SLICE_MODE_WACH">Fully_Registered</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REGISTER_SLICE_MODE_WDCH">Fully_Registered</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REGISTER_SLICE_MODE_WRCH">Fully_Registered</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REGISTER_SLICE_MODE_RACH">Fully_Registered</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REGISTER_SLICE_MODE_AXIS">Fully_Registered</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERFLOW_FLAG_AXI">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERFLOW_SENSE_AXI">Active_High</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DISABLE_TIMING_VIOLATIONS_AXI">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADD_NGC_CONSTRAINT_AXI">false</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_EMBEDDED_REGISTERS_AXIS">false</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_WIDTH">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RLOCS">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_EMPTY">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_FULL">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_BACKUP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNT">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_INT_CLK">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEMINIT_FILE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_OVERFLOW">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_RST">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_UNDERFLOW">0</spirit:configurableElementValue>
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/fade_ether_protocol/trunk/experimental_fade_10g/fpga/rec_to_pkg.py
0,0 → 1,124
#!/usr/bin/python
# The script below is written by Wojciech M. Zabolotny
# wzab<at>ise.pw.edu.pl 19.03.2012
# it is published as PUBLIC DOMAIN
import sys
class field:
last_bit = 0;
def __init__(self,field_desc):
fd = field_desc.split(",")
self.fname = fd[0]
if not fd[1] in ["signed","unsigned","std_logic_vector"]:
raise Exception("Wrong field type")
self.ftype = fd[1]
if len(fd)==3:
self.b1=int(fd[2])-1
self.b2=0
elif len(fd)==4:
self.b1=int(fd[2])
self.b2=int(fd[3])
else:
raise Exception("Syntax error in line: "+field_desc)
#Assign vector bits
self.v1=field.last_bit
self.v2=field.last_bit+abs(self.b2-self.b1)
field.last_bit = self.v2+1
if len(sys.argv) != 2:
print """
The rec_to_pkg scripts creates VHDL package for conversion
between the VHDL records containing "signed" and "unsigned"
fields and std_logic_vectors.
It should be called as: rec_to_pkg.py description_file
where the description file should have the following syntax:
 
#Optional comment line
record record_name
#optional comment lines
#[...]
field_name,signed_or_unsigned,width
#or
field_name,signed_or_unsigned,left_bit_nr,right_bit_nr
end
 
The generated package is written to the record_name_pkg.vhd file
"""
exit(0)
fin=open(sys.argv[1])
#Read the full description of the type
type_desc=[l.strip() for l in fin.readlines() if len(l) > 0 and l[0] != "#" ]
#The first line should contain the record name
l=type_desc[0].split(" ")
if l[0] != "record":
raise Exception("Syntax error! The first line should have form \"record name_of_type\"")
type_name=l[1]
pkg_name=type_name+"_pkg"
#Prepare for analysis of fields
msb=0
fields=[]
end_found = False
#Find the field definitions
for l in type_desc[1:]:
if l=="end":
end_found=True
break
fields.append(field(l))
if not end_found:
raise Exception("Syntax error: no \"end\" found")
#If we got here, probably the syntax was correct
#Lets generate the package
p="""\
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
"""
p+="package "+pkg_name+" is\n\n"
p+="type "+type_name+" is record\n"
for f in fields:
s=" "+f.fname+" : "+f.ftype+"("
if f.b1 > f.b2:
s=s+str(f.b1)+" downto "+str(f.b2)+");\n"
else:
s=s+str(f.b1)+" to "+str(f.b2)+");\n"
p+=s
p+="end record;\n\n"
#Write width of our type
p+="constant "+type_name+"_width : integer := "+str(field.last_bit)+";\n\n"
#Write headers of conversion functions
p+="function "+type_name+"_to_stlv(\n"
p+=" constant din : "+type_name+")\n"
p+=" return std_logic_vector;\n\n"
p+="function stlv_to_"+type_name+"(\n"
p+=" constant din : std_logic_vector)\n"
p+=" return "+type_name+";\n\n"
p+="end "+pkg_name+";\n\n"
#Now the body of the package - the conversion functions
p+="package body "+pkg_name+" is\n\n"
#
p+="function "+type_name+"_to_stlv(\n"
p+=" constant din : "+type_name+")\n"
p+=" return std_logic_vector is\n"
p+=" variable res : std_logic_vector("+str(field.last_bit-1)+" downto 0);\n"
p+="begin\n"
for f in fields:
p+=" res("+str(f.v2)+" downto "+str(f.v1)+ ") := std_logic_vector(din."+f.fname+");\n"
p+=" return res;\n"
p+="end "+type_name+"_to_stlv;\n\n"
#
p+="function stlv_to_"+type_name+"(\n"
p+=" constant din : std_logic_vector)\n"
p+=" return "+type_name+" is\n"
p+=" variable res : "+type_name+";\n"
p+="begin\n"
for f in fields:
p+=" res."+f.fname+":="+f.ftype+"(din("+str(f.v2)+" downto "+str(f.v1)+"));\n"
p+=" return res;\n"
p+="end stlv_to_"+type_name+";\n\n"
p+="end "+pkg_name+";\n"
 
#The output file name
fout_name=type_name+"_pkg.vhd"
fout=open(fout_name,"w")
fout.write(p)
fout.close()
 
fade_ether_protocol/trunk/experimental_fade_10g/fpga/rec_to_pkg.py Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: fade_ether_protocol/trunk/experimental_fade_10g/fpga/PCK_CRC32_D16.vhd =================================================================== --- fade_ether_protocol/trunk/experimental_fade_10g/fpga/PCK_CRC32_D16.vhd (nonexistent) +++ fade_ether_protocol/trunk/experimental_fade_10g/fpga/PCK_CRC32_D16.vhd (revision 12) @@ -0,0 +1,86 @@ +-------------------------------------------------------------------------------- +-- Copyright (C) 1999-2008 Easics NV. +-- This source file may be used and distributed without restriction +-- provided that this copyright statement is not removed from the file +-- and that any derivative work contains the original copyright notice +-- and the associated disclaimer. +-- +-- THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS +-- OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED +-- WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. +-- +-- Purpose : synthesizable CRC function +-- * polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32) +-- * data width: 16 +-- +-- Info : tools@easics.be +-- http://www.easics.com +-------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; + +package PCK_CRC32_D16 is + -- polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32) + -- data width: 16 + -- convention: the first serial bit is D[15] + function nextCRC32_D16 + (Data: std_logic_vector(15 downto 0); + crc: std_logic_vector(31 downto 0)) + return std_logic_vector; +end PCK_CRC32_D16; + + +package body PCK_CRC32_D16 is + + -- polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32) + -- data width: 16 + -- convention: the first serial bit is D[15] + function nextCRC32_D16 + (Data: std_logic_vector(15 downto 0); + crc: std_logic_vector(31 downto 0)) + return std_logic_vector is + + variable d: std_logic_vector(15 downto 0); + variable c: std_logic_vector(31 downto 0); + variable newcrc: std_logic_vector(31 downto 0); + + begin + d := Data; + c := crc; + + newcrc(0) := d(12) xor d(10) xor d(9) xor d(6) xor d(0) xor c(16) xor c(22) xor c(25) xor c(26) xor c(28); + newcrc(1) := d(13) xor d(12) xor d(11) xor d(9) xor d(7) xor d(6) xor d(1) xor d(0) xor c(16) xor c(17) xor c(22) xor c(23) xor c(25) xor c(27) xor c(28) xor c(29); + newcrc(2) := d(14) xor d(13) xor d(9) xor d(8) xor d(7) xor d(6) xor d(2) xor d(1) xor d(0) xor c(16) xor c(17) xor c(18) xor c(22) xor c(23) xor c(24) xor c(25) xor c(29) xor c(30); + newcrc(3) := d(15) xor d(14) xor d(10) xor d(9) xor d(8) xor d(7) xor d(3) xor d(2) xor d(1) xor c(17) xor c(18) xor c(19) xor c(23) xor c(24) xor c(25) xor c(26) xor c(30) xor c(31); + newcrc(4) := d(15) xor d(12) xor d(11) xor d(8) xor d(6) xor d(4) xor d(3) xor d(2) xor d(0) xor c(16) xor c(18) xor c(19) xor c(20) xor c(22) xor c(24) xor c(27) xor c(28) xor c(31); + newcrc(5) := d(13) xor d(10) xor d(7) xor d(6) xor d(5) xor d(4) xor d(3) xor d(1) xor d(0) xor c(16) xor c(17) xor c(19) xor c(20) xor c(21) xor c(22) xor c(23) xor c(26) xor c(29); + newcrc(6) := d(14) xor d(11) xor d(8) xor d(7) xor d(6) xor d(5) xor d(4) xor d(2) xor d(1) xor c(17) xor c(18) xor c(20) xor c(21) xor c(22) xor c(23) xor c(24) xor c(27) xor c(30); + newcrc(7) := d(15) xor d(10) xor d(8) xor d(7) xor d(5) xor d(3) xor d(2) xor d(0) xor c(16) xor c(18) xor c(19) xor c(21) xor c(23) xor c(24) xor c(26) xor c(31); + newcrc(8) := d(12) xor d(11) xor d(10) xor d(8) xor d(4) xor d(3) xor d(1) xor d(0) xor c(16) xor c(17) xor c(19) xor c(20) xor c(24) xor c(26) xor c(27) xor c(28); + newcrc(9) := d(13) xor d(12) xor d(11) xor d(9) xor d(5) xor d(4) xor d(2) xor d(1) xor c(17) xor c(18) xor c(20) xor c(21) xor c(25) xor c(27) xor c(28) xor c(29); + newcrc(10) := d(14) xor d(13) xor d(9) xor d(5) xor d(3) xor d(2) xor d(0) xor c(16) xor c(18) xor c(19) xor c(21) xor c(25) xor c(29) xor c(30); + newcrc(11) := d(15) xor d(14) xor d(12) xor d(9) xor d(4) xor d(3) xor d(1) xor d(0) xor c(16) xor c(17) xor c(19) xor c(20) xor c(25) xor c(28) xor c(30) xor c(31); + newcrc(12) := d(15) xor d(13) xor d(12) xor d(9) xor d(6) xor d(5) xor d(4) xor d(2) xor d(1) xor d(0) xor c(16) xor c(17) xor c(18) xor c(20) xor c(21) xor c(22) xor c(25) xor c(28) xor c(29) xor c(31); + newcrc(13) := d(14) xor d(13) xor d(10) xor d(7) xor d(6) xor d(5) xor d(3) xor d(2) xor d(1) xor c(17) xor c(18) xor c(19) xor c(21) xor c(22) xor c(23) xor c(26) xor c(29) xor c(30); + newcrc(14) := d(15) xor d(14) xor d(11) xor d(8) xor d(7) xor d(6) xor d(4) xor d(3) xor d(2) xor c(18) xor c(19) xor c(20) xor c(22) xor c(23) xor c(24) xor c(27) xor c(30) xor c(31); + newcrc(15) := d(15) xor d(12) xor d(9) xor d(8) xor d(7) xor d(5) xor d(4) xor d(3) xor c(19) xor c(20) xor c(21) xor c(23) xor c(24) xor c(25) xor c(28) xor c(31); + newcrc(16) := d(13) xor d(12) xor d(8) xor d(5) xor d(4) xor d(0) xor c(0) xor c(16) xor c(20) xor c(21) xor c(24) xor c(28) xor c(29); + newcrc(17) := d(14) xor d(13) xor d(9) xor d(6) xor d(5) xor d(1) xor c(1) xor c(17) xor c(21) xor c(22) xor c(25) xor c(29) xor c(30); + newcrc(18) := d(15) xor d(14) xor d(10) xor d(7) xor d(6) xor d(2) xor c(2) xor c(18) xor c(22) xor c(23) xor c(26) xor c(30) xor c(31); + newcrc(19) := d(15) xor d(11) xor d(8) xor d(7) xor d(3) xor c(3) xor c(19) xor c(23) xor c(24) xor c(27) xor c(31); + newcrc(20) := d(12) xor d(9) xor d(8) xor d(4) xor c(4) xor c(20) xor c(24) xor c(25) xor c(28); + newcrc(21) := d(13) xor d(10) xor d(9) xor d(5) xor c(5) xor c(21) xor c(25) xor c(26) xor c(29); + newcrc(22) := d(14) xor d(12) xor d(11) xor d(9) xor d(0) xor c(6) xor c(16) xor c(25) xor c(27) xor c(28) xor c(30); + newcrc(23) := d(15) xor d(13) xor d(9) xor d(6) xor d(1) xor d(0) xor c(7) xor c(16) xor c(17) xor c(22) xor c(25) xor c(29) xor c(31); + newcrc(24) := d(14) xor d(10) xor d(7) xor d(2) xor d(1) xor c(8) xor c(17) xor c(18) xor c(23) xor c(26) xor c(30); + newcrc(25) := d(15) xor d(11) xor d(8) xor d(3) xor d(2) xor c(9) xor c(18) xor c(19) xor c(24) xor c(27) xor c(31); + newcrc(26) := d(10) xor d(6) xor d(4) xor d(3) xor d(0) xor c(10) xor c(16) xor c(19) xor c(20) xor c(22) xor c(26); + newcrc(27) := d(11) xor d(7) xor d(5) xor d(4) xor d(1) xor c(11) xor c(17) xor c(20) xor c(21) xor c(23) xor c(27); + newcrc(28) := d(12) xor d(8) xor d(6) xor d(5) xor d(2) xor c(12) xor c(18) xor c(21) xor c(22) xor c(24) xor c(28); + newcrc(29) := d(13) xor d(9) xor d(7) xor d(6) xor d(3) xor c(13) xor c(19) xor c(22) xor c(23) xor c(25) xor c(29); + newcrc(30) := d(14) xor d(10) xor d(8) xor d(7) xor d(4) xor c(14) xor c(20) xor c(23) xor c(24) xor c(26) xor c(30); + newcrc(31) := d(15) xor d(11) xor d(9) xor d(8) xor d(5) xor c(15) xor c(21) xor c(24) xor c(25) xor c(27) xor c(31); + return newcrc; + end nextCRC32_D16; + +end PCK_CRC32_D16; Index: fade_ether_protocol/trunk/experimental_fade_10g/fpga/PCK_CRC32_D8.vhd =================================================================== --- fade_ether_protocol/trunk/experimental_fade_10g/fpga/PCK_CRC32_D8.vhd (nonexistent) +++ fade_ether_protocol/trunk/experimental_fade_10g/fpga/PCK_CRC32_D8.vhd (revision 12) @@ -0,0 +1,86 @@ +-------------------------------------------------------------------------------- +-- Copyright (C) 1999-2008 Easics NV. +-- This source file may be used and distributed without restriction +-- provided that this copyright statement is not removed from the file +-- and that any derivative work contains the original copyright notice +-- and the associated disclaimer. +-- +-- THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS +-- OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED +-- WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. +-- +-- Purpose : synthesizable CRC function +-- * polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32) +-- * data width: 8 +-- +-- Info : tools@easics.be +-- http://www.easics.com +-------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; + +package PCK_CRC32_D8 is + -- polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32) + -- data width: 8 + -- convention: the first serial bit is D[7] + function nextCRC32_D8 + (Data: std_logic_vector(7 downto 0); + crc: std_logic_vector(31 downto 0)) + return std_logic_vector; +end PCK_CRC32_D8; + + +package body PCK_CRC32_D8 is + + -- polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32) + -- data width: 8 + -- convention: the first serial bit is D[7] + function nextCRC32_D8 + (Data: std_logic_vector(7 downto 0); + crc: std_logic_vector(31 downto 0)) + return std_logic_vector is + + variable d: std_logic_vector(7 downto 0); + variable c: std_logic_vector(31 downto 0); + variable newcrc: std_logic_vector(31 downto 0); + + begin + d := Data; + c := crc; + + newcrc(0) := d(6) xor d(0) xor c(24) xor c(30); + newcrc(1) := d(7) xor d(6) xor d(1) xor d(0) xor c(24) xor c(25) xor c(30) xor c(31); + newcrc(2) := d(7) xor d(6) xor d(2) xor d(1) xor d(0) xor c(24) xor c(25) xor c(26) xor c(30) xor c(31); + newcrc(3) := d(7) xor d(3) xor d(2) xor d(1) xor c(25) xor c(26) xor c(27) xor c(31); + newcrc(4) := d(6) xor d(4) xor d(3) xor d(2) xor d(0) xor c(24) xor c(26) xor c(27) xor c(28) xor c(30); + newcrc(5) := d(7) xor d(6) xor d(5) xor d(4) xor d(3) xor d(1) xor d(0) xor c(24) xor c(25) xor c(27) xor c(28) xor c(29) xor c(30) xor c(31); + newcrc(6) := d(7) xor d(6) xor d(5) xor d(4) xor d(2) xor d(1) xor c(25) xor c(26) xor c(28) xor c(29) xor c(30) xor c(31); + newcrc(7) := d(7) xor d(5) xor d(3) xor d(2) xor d(0) xor c(24) xor c(26) xor c(27) xor c(29) xor c(31); + newcrc(8) := d(4) xor d(3) xor d(1) xor d(0) xor c(0) xor c(24) xor c(25) xor c(27) xor c(28); + newcrc(9) := d(5) xor d(4) xor d(2) xor d(1) xor c(1) xor c(25) xor c(26) xor c(28) xor c(29); + newcrc(10) := d(5) xor d(3) xor d(2) xor d(0) xor c(2) xor c(24) xor c(26) xor c(27) xor c(29); + newcrc(11) := d(4) xor d(3) xor d(1) xor d(0) xor c(3) xor c(24) xor c(25) xor c(27) xor c(28); + newcrc(12) := d(6) xor d(5) xor d(4) xor d(2) xor d(1) xor d(0) xor c(4) xor c(24) xor c(25) xor c(26) xor c(28) xor c(29) xor c(30); + newcrc(13) := d(7) xor d(6) xor d(5) xor d(3) xor d(2) xor d(1) xor c(5) xor c(25) xor c(26) xor c(27) xor c(29) xor c(30) xor c(31); + newcrc(14) := d(7) xor d(6) xor d(4) xor d(3) xor d(2) xor c(6) xor c(26) xor c(27) xor c(28) xor c(30) xor c(31); + newcrc(15) := d(7) xor d(5) xor d(4) xor d(3) xor c(7) xor c(27) xor c(28) xor c(29) xor c(31); + newcrc(16) := d(5) xor d(4) xor d(0) xor c(8) xor c(24) xor c(28) xor c(29); + newcrc(17) := d(6) xor d(5) xor d(1) xor c(9) xor c(25) xor c(29) xor c(30); + newcrc(18) := d(7) xor d(6) xor d(2) xor c(10) xor c(26) xor c(30) xor c(31); + newcrc(19) := d(7) xor d(3) xor c(11) xor c(27) xor c(31); + newcrc(20) := d(4) xor c(12) xor c(28); + newcrc(21) := d(5) xor c(13) xor c(29); + newcrc(22) := d(0) xor c(14) xor c(24); + newcrc(23) := d(6) xor d(1) xor d(0) xor c(15) xor c(24) xor c(25) xor c(30); + newcrc(24) := d(7) xor d(2) xor d(1) xor c(16) xor c(25) xor c(26) xor c(31); + newcrc(25) := d(3) xor d(2) xor c(17) xor c(26) xor c(27); + newcrc(26) := d(6) xor d(4) xor d(3) xor d(0) xor c(18) xor c(24) xor c(27) xor c(28) xor c(30); + newcrc(27) := d(7) xor d(5) xor d(4) xor d(1) xor c(19) xor c(25) xor c(28) xor c(29) xor c(31); + newcrc(28) := d(6) xor d(5) xor d(2) xor c(20) xor c(26) xor c(29) xor c(30); + newcrc(29) := d(7) xor d(6) xor d(3) xor c(21) xor c(27) xor c(30) xor c(31); + newcrc(30) := d(7) xor d(4) xor c(22) xor c(28) xor c(31); + newcrc(31) := d(5) xor c(23) xor c(29); + return newcrc; + end nextCRC32_D8; + +end PCK_CRC32_D8; Index: fade_ether_protocol/trunk/experimental_fade_10g/fpga/ack.rec =================================================================== --- fade_ether_protocol/trunk/experimental_fade_10g/fpga/ack.rec (nonexistent) +++ fade_ether_protocol/trunk/experimental_fade_10g/fpga/ack.rec (revision 12) @@ -0,0 +1,12 @@ +# This is a test record - packet acknowledgment +record pkt_ack +# Below are fields definitions +# First two pointers fo linked list +# pkt - number of the packet +pkt,unsigned,8 +# set - number of the set +set,unsigned,16 +# cmd - command - 1 for ACK +cmd,unsigned,8 +end + Index: fade_ether_protocol/trunk/experimental_fade_10g/fpga/PCK_CRC32_D64.vhd =================================================================== --- fade_ether_protocol/trunk/experimental_fade_10g/fpga/PCK_CRC32_D64.vhd (nonexistent) +++ fade_ether_protocol/trunk/experimental_fade_10g/fpga/PCK_CRC32_D64.vhd (revision 12) @@ -0,0 +1,86 @@ +-------------------------------------------------------------------------------- +-- Copyright (C) 1999-2008 Easics NV. +-- This source file may be used and distributed without restriction +-- provided that this copyright statement is not removed from the file +-- and that any derivative work contains the original copyright notice +-- and the associated disclaimer. +-- +-- THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS +-- OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED +-- WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. +-- +-- Purpose : synthesizable CRC function +-- * polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32) +-- * data width: 64 +-- +-- Info : tools@easics.be +-- http://www.easics.com +-------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; + +package PCK_CRC32_D64 is + -- polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32) + -- data width: 64 + -- convention: the first serial bit is D[63] + function nextCRC32_D64 + (Data: std_logic_vector(63 downto 0); + crc: std_logic_vector(31 downto 0)) + return std_logic_vector; +end PCK_CRC32_D64; + + +package body PCK_CRC32_D64 is + + -- polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32) + -- data width: 64 + -- convention: the first serial bit is D[63] + function nextCRC32_D64 + (Data: std_logic_vector(63 downto 0); + crc: std_logic_vector(31 downto 0)) + return std_logic_vector is + + variable d: std_logic_vector(63 downto 0); + variable c: std_logic_vector(31 downto 0); + variable newcrc: std_logic_vector(31 downto 0); + + begin + d := Data; + c := crc; + + newcrc(0) := d(63) xor d(61) xor d(60) xor d(58) xor d(55) xor d(54) xor d(53) xor d(50) xor d(48) xor d(47) xor d(45) xor d(44) xor d(37) xor d(34) xor d(32) xor d(31) xor d(30) xor d(29) xor d(28) xor d(26) xor d(25) xor d(24) xor d(16) xor d(12) xor d(10) xor d(9) xor d(6) xor d(0) xor c(0) xor c(2) xor c(5) xor c(12) xor c(13) xor c(15) xor c(16) xor c(18) xor c(21) xor c(22) xor c(23) xor c(26) xor c(28) xor c(29) xor c(31); + newcrc(1) := d(63) xor d(62) xor d(60) xor d(59) xor d(58) xor d(56) xor d(53) xor d(51) xor d(50) xor d(49) xor d(47) xor d(46) xor d(44) xor d(38) xor d(37) xor d(35) xor d(34) xor d(33) xor d(28) xor d(27) xor d(24) xor d(17) xor d(16) xor d(13) xor d(12) xor d(11) xor d(9) xor d(7) xor d(6) xor d(1) xor d(0) xor c(1) xor c(2) xor c(3) xor c(5) xor c(6) xor c(12) xor c(14) xor c(15) xor c(17) xor c(18) xor c(19) xor c(21) xor c(24) xor c(26) xor c(27) xor c(28) xor c(30) xor c(31); + newcrc(2) := d(59) xor d(58) xor d(57) xor d(55) xor d(53) xor d(52) xor d(51) xor d(44) xor d(39) xor d(38) xor d(37) xor d(36) xor d(35) xor d(32) xor d(31) xor d(30) xor d(26) xor d(24) xor d(18) xor d(17) xor d(16) xor d(14) xor d(13) xor d(9) xor d(8) xor d(7) xor d(6) xor d(2) xor d(1) xor d(0) xor c(0) xor c(3) xor c(4) xor c(5) xor c(6) xor c(7) xor c(12) xor c(19) xor c(20) xor c(21) xor c(23) xor c(25) xor c(26) xor c(27); + newcrc(3) := d(60) xor d(59) xor d(58) xor d(56) xor d(54) xor d(53) xor d(52) xor d(45) xor d(40) xor d(39) xor d(38) xor d(37) xor d(36) xor d(33) xor d(32) xor d(31) xor d(27) xor d(25) xor d(19) xor d(18) xor d(17) xor d(15) xor d(14) xor d(10) xor d(9) xor d(8) xor d(7) xor d(3) xor d(2) xor d(1) xor c(0) xor c(1) xor c(4) xor c(5) xor c(6) xor c(7) xor c(8) xor c(13) xor c(20) xor c(21) xor c(22) xor c(24) xor c(26) xor c(27) xor c(28); + newcrc(4) := d(63) xor d(59) xor d(58) xor d(57) xor d(50) xor d(48) xor d(47) xor d(46) xor d(45) xor d(44) xor d(41) xor d(40) xor d(39) xor d(38) xor d(33) xor d(31) xor d(30) xor d(29) xor d(25) xor d(24) xor d(20) xor d(19) xor d(18) xor d(15) xor d(12) xor d(11) xor d(8) xor d(6) xor d(4) xor d(3) xor d(2) xor d(0) xor c(1) xor c(6) xor c(7) xor c(8) xor c(9) xor c(12) xor c(13) xor c(14) xor c(15) xor c(16) xor c(18) xor c(25) xor c(26) xor c(27) xor c(31); + newcrc(5) := d(63) xor d(61) xor d(59) xor d(55) xor d(54) xor d(53) xor d(51) xor d(50) xor d(49) xor d(46) xor d(44) xor d(42) xor d(41) xor d(40) xor d(39) xor d(37) xor d(29) xor d(28) xor d(24) xor d(21) xor d(20) xor d(19) xor d(13) xor d(10) xor d(7) xor d(6) xor d(5) xor d(4) xor d(3) xor d(1) xor d(0) xor c(5) xor c(7) xor c(8) xor c(9) xor c(10) xor c(12) xor c(14) xor c(17) xor c(18) xor c(19) xor c(21) xor c(22) xor c(23) xor c(27) xor c(29) xor c(31); + newcrc(6) := d(62) xor d(60) xor d(56) xor d(55) xor d(54) xor d(52) xor d(51) xor d(50) xor d(47) xor d(45) xor d(43) xor d(42) xor d(41) xor d(40) xor d(38) xor d(30) xor d(29) xor d(25) xor d(22) xor d(21) xor d(20) xor d(14) xor d(11) xor d(8) xor d(7) xor d(6) xor d(5) xor d(4) xor d(2) xor d(1) xor c(6) xor c(8) xor c(9) xor c(10) xor c(11) xor c(13) xor c(15) xor c(18) xor c(19) xor c(20) xor c(22) xor c(23) xor c(24) xor c(28) xor c(30); + newcrc(7) := d(60) xor d(58) xor d(57) xor d(56) xor d(54) xor d(52) xor d(51) xor d(50) xor d(47) xor d(46) xor d(45) xor d(43) xor d(42) xor d(41) xor d(39) xor d(37) xor d(34) xor d(32) xor d(29) xor d(28) xor d(25) xor d(24) xor d(23) xor d(22) xor d(21) xor d(16) xor d(15) xor d(10) xor d(8) xor d(7) xor d(5) xor d(3) xor d(2) xor d(0) xor c(0) xor c(2) xor c(5) xor c(7) xor c(9) xor c(10) xor c(11) xor c(13) xor c(14) xor c(15) xor c(18) xor c(19) xor c(20) xor c(22) xor c(24) xor c(25) xor c(26) xor c(28); + newcrc(8) := d(63) xor d(60) xor d(59) xor d(57) xor d(54) xor d(52) xor d(51) xor d(50) xor d(46) xor d(45) xor d(43) xor d(42) xor d(40) xor d(38) xor d(37) xor d(35) xor d(34) xor d(33) xor d(32) xor d(31) xor d(28) xor d(23) xor d(22) xor d(17) xor d(12) xor d(11) xor d(10) xor d(8) xor d(4) xor d(3) xor d(1) xor d(0) xor c(0) xor c(1) xor c(2) xor c(3) xor c(5) xor c(6) xor c(8) xor c(10) xor c(11) xor c(13) xor c(14) xor c(18) xor c(19) xor c(20) xor c(22) xor c(25) xor c(27) xor c(28) xor c(31); + newcrc(9) := d(61) xor d(60) xor d(58) xor d(55) xor d(53) xor d(52) xor d(51) xor d(47) xor d(46) xor d(44) xor d(43) xor d(41) xor d(39) xor d(38) xor d(36) xor d(35) xor d(34) xor d(33) xor d(32) xor d(29) xor d(24) xor d(23) xor d(18) xor d(13) xor d(12) xor d(11) xor d(9) xor d(5) xor d(4) xor d(2) xor d(1) xor c(0) xor c(1) xor c(2) xor c(3) xor c(4) xor c(6) xor c(7) xor c(9) xor c(11) xor c(12) xor c(14) xor c(15) xor c(19) xor c(20) xor c(21) xor c(23) xor c(26) xor c(28) xor c(29); + newcrc(10) := d(63) xor d(62) xor d(60) xor d(59) xor d(58) xor d(56) xor d(55) xor d(52) xor d(50) xor d(42) xor d(40) xor d(39) xor d(36) xor d(35) xor d(33) xor d(32) xor d(31) xor d(29) xor d(28) xor d(26) xor d(19) xor d(16) xor d(14) xor d(13) xor d(9) xor d(5) xor d(3) xor d(2) xor d(0) xor c(0) xor c(1) xor c(3) xor c(4) xor c(7) xor c(8) xor c(10) xor c(18) xor c(20) xor c(23) xor c(24) xor c(26) xor c(27) xor c(28) xor c(30) xor c(31); + newcrc(11) := d(59) xor d(58) xor d(57) xor d(56) xor d(55) xor d(54) xor d(51) xor d(50) xor d(48) xor d(47) xor d(45) xor d(44) xor d(43) xor d(41) xor d(40) xor d(36) xor d(33) xor d(31) xor d(28) xor d(27) xor d(26) xor d(25) xor d(24) xor d(20) xor d(17) xor d(16) xor d(15) xor d(14) xor d(12) xor d(9) xor d(4) xor d(3) xor d(1) xor d(0) xor c(1) xor c(4) xor c(8) xor c(9) xor c(11) xor c(12) xor c(13) xor c(15) xor c(16) xor c(18) xor c(19) xor c(22) xor c(23) xor c(24) xor c(25) xor c(26) xor c(27); + newcrc(12) := d(63) xor d(61) xor d(59) xor d(57) xor d(56) xor d(54) xor d(53) xor d(52) xor d(51) xor d(50) xor d(49) xor d(47) xor d(46) xor d(42) xor d(41) xor d(31) xor d(30) xor d(27) xor d(24) xor d(21) xor d(18) xor d(17) xor d(15) xor d(13) xor d(12) xor d(9) xor d(6) xor d(5) xor d(4) xor d(2) xor d(1) xor d(0) xor c(9) xor c(10) xor c(14) xor c(15) xor c(17) xor c(18) xor c(19) xor c(20) xor c(21) xor c(22) xor c(24) xor c(25) xor c(27) xor c(29) xor c(31); + newcrc(13) := d(62) xor d(60) xor d(58) xor d(57) xor d(55) xor d(54) xor d(53) xor d(52) xor d(51) xor d(50) xor d(48) xor d(47) xor d(43) xor d(42) xor d(32) xor d(31) xor d(28) xor d(25) xor d(22) xor d(19) xor d(18) xor d(16) xor d(14) xor d(13) xor d(10) xor d(7) xor d(6) xor d(5) xor d(3) xor d(2) xor d(1) xor c(0) xor c(10) xor c(11) xor c(15) xor c(16) xor c(18) xor c(19) xor c(20) xor c(21) xor c(22) xor c(23) xor c(25) xor c(26) xor c(28) xor c(30); + newcrc(14) := d(63) xor d(61) xor d(59) xor d(58) xor d(56) xor d(55) xor d(54) xor d(53) xor d(52) xor d(51) xor d(49) xor d(48) xor d(44) xor d(43) xor d(33) xor d(32) xor d(29) xor d(26) xor d(23) xor d(20) xor d(19) xor d(17) xor d(15) xor d(14) xor d(11) xor d(8) xor d(7) xor d(6) xor d(4) xor d(3) xor d(2) xor c(0) xor c(1) xor c(11) xor c(12) xor c(16) xor c(17) xor c(19) xor c(20) xor c(21) xor c(22) xor c(23) xor c(24) xor c(26) xor c(27) xor c(29) xor c(31); + newcrc(15) := d(62) xor d(60) xor d(59) xor d(57) xor d(56) xor d(55) xor d(54) xor d(53) xor d(52) xor d(50) xor d(49) xor d(45) xor d(44) xor d(34) xor d(33) xor d(30) xor d(27) xor d(24) xor d(21) xor d(20) xor d(18) xor d(16) xor d(15) xor d(12) xor d(9) xor d(8) xor d(7) xor d(5) xor d(4) xor d(3) xor c(1) xor c(2) xor c(12) xor c(13) xor c(17) xor c(18) xor c(20) xor c(21) xor c(22) xor c(23) xor c(24) xor c(25) xor c(27) xor c(28) xor c(30); + newcrc(16) := d(57) xor d(56) xor d(51) xor d(48) xor d(47) xor d(46) xor d(44) xor d(37) xor d(35) xor d(32) xor d(30) xor d(29) xor d(26) xor d(24) xor d(22) xor d(21) xor d(19) xor d(17) xor d(13) xor d(12) xor d(8) xor d(5) xor d(4) xor d(0) xor c(0) xor c(3) xor c(5) xor c(12) xor c(14) xor c(15) xor c(16) xor c(19) xor c(24) xor c(25); + newcrc(17) := d(58) xor d(57) xor d(52) xor d(49) xor d(48) xor d(47) xor d(45) xor d(38) xor d(36) xor d(33) xor d(31) xor d(30) xor d(27) xor d(25) xor d(23) xor d(22) xor d(20) xor d(18) xor d(14) xor d(13) xor d(9) xor d(6) xor d(5) xor d(1) xor c(1) xor c(4) xor c(6) xor c(13) xor c(15) xor c(16) xor c(17) xor c(20) xor c(25) xor c(26); + newcrc(18) := d(59) xor d(58) xor d(53) xor d(50) xor d(49) xor d(48) xor d(46) xor d(39) xor d(37) xor d(34) xor d(32) xor d(31) xor d(28) xor d(26) xor d(24) xor d(23) xor d(21) xor d(19) xor d(15) xor d(14) xor d(10) xor d(7) xor d(6) xor d(2) xor c(0) xor c(2) xor c(5) xor c(7) xor c(14) xor c(16) xor c(17) xor c(18) xor c(21) xor c(26) xor c(27); + newcrc(19) := d(60) xor d(59) xor d(54) xor d(51) xor d(50) xor d(49) xor d(47) xor d(40) xor d(38) xor d(35) xor d(33) xor d(32) xor d(29) xor d(27) xor d(25) xor d(24) xor d(22) xor d(20) xor d(16) xor d(15) xor d(11) xor d(8) xor d(7) xor d(3) xor c(0) xor c(1) xor c(3) xor c(6) xor c(8) xor c(15) xor c(17) xor c(18) xor c(19) xor c(22) xor c(27) xor c(28); + newcrc(20) := d(61) xor d(60) xor d(55) xor d(52) xor d(51) xor d(50) xor d(48) xor d(41) xor d(39) xor d(36) xor d(34) xor d(33) xor d(30) xor d(28) xor d(26) xor d(25) xor d(23) xor d(21) xor d(17) xor d(16) xor d(12) xor d(9) xor d(8) xor d(4) xor c(1) xor c(2) xor c(4) xor c(7) xor c(9) xor c(16) xor c(18) xor c(19) xor c(20) xor c(23) xor c(28) xor c(29); + newcrc(21) := d(62) xor d(61) xor d(56) xor d(53) xor d(52) xor d(51) xor d(49) xor d(42) xor d(40) xor d(37) xor d(35) xor d(34) xor d(31) xor d(29) xor d(27) xor d(26) xor d(24) xor d(22) xor d(18) xor d(17) xor d(13) xor d(10) xor d(9) xor d(5) xor c(2) xor c(3) xor c(5) xor c(8) xor c(10) xor c(17) xor c(19) xor c(20) xor c(21) xor c(24) xor c(29) xor c(30); + newcrc(22) := d(62) xor d(61) xor d(60) xor d(58) xor d(57) xor d(55) xor d(52) xor d(48) xor d(47) xor d(45) xor d(44) xor d(43) xor d(41) xor d(38) xor d(37) xor d(36) xor d(35) xor d(34) xor d(31) xor d(29) xor d(27) xor d(26) xor d(24) xor d(23) xor d(19) xor d(18) xor d(16) xor d(14) xor d(12) xor d(11) xor d(9) xor d(0) xor c(2) xor c(3) xor c(4) xor c(5) xor c(6) xor c(9) xor c(11) xor c(12) xor c(13) xor c(15) xor c(16) xor c(20) xor c(23) xor c(25) xor c(26) xor c(28) xor c(29) xor c(30); + newcrc(23) := d(62) xor d(60) xor d(59) xor d(56) xor d(55) xor d(54) xor d(50) xor d(49) xor d(47) xor d(46) xor d(42) xor d(39) xor d(38) xor d(36) xor d(35) xor d(34) xor d(31) xor d(29) xor d(27) xor d(26) xor d(20) xor d(19) xor d(17) xor d(16) xor d(15) xor d(13) xor d(9) xor d(6) xor d(1) xor d(0) xor c(2) xor c(3) xor c(4) xor c(6) xor c(7) xor c(10) xor c(14) xor c(15) xor c(17) xor c(18) xor c(22) xor c(23) xor c(24) xor c(27) xor c(28) xor c(30); + newcrc(24) := d(63) xor d(61) xor d(60) xor d(57) xor d(56) xor d(55) xor d(51) xor d(50) xor d(48) xor d(47) xor d(43) xor d(40) xor d(39) xor d(37) xor d(36) xor d(35) xor d(32) xor d(30) xor d(28) xor d(27) xor d(21) xor d(20) xor d(18) xor d(17) xor d(16) xor d(14) xor d(10) xor d(7) xor d(2) xor d(1) xor c(0) xor c(3) xor c(4) xor c(5) xor c(7) xor c(8) xor c(11) xor c(15) xor c(16) xor c(18) xor c(19) xor c(23) xor c(24) xor c(25) xor c(28) xor c(29) xor c(31); + newcrc(25) := d(62) xor d(61) xor d(58) xor d(57) xor d(56) xor d(52) xor d(51) xor d(49) xor d(48) xor d(44) xor d(41) xor d(40) xor d(38) xor d(37) xor d(36) xor d(33) xor d(31) xor d(29) xor d(28) xor d(22) xor d(21) xor d(19) xor d(18) xor d(17) xor d(15) xor d(11) xor d(8) xor d(3) xor d(2) xor c(1) xor c(4) xor c(5) xor c(6) xor c(8) xor c(9) xor c(12) xor c(16) xor c(17) xor c(19) xor c(20) xor c(24) xor c(25) xor c(26) xor c(29) xor c(30); + newcrc(26) := d(62) xor d(61) xor d(60) xor d(59) xor d(57) xor d(55) xor d(54) xor d(52) xor d(49) xor d(48) xor d(47) xor d(44) xor d(42) xor d(41) xor d(39) xor d(38) xor d(31) xor d(28) xor d(26) xor d(25) xor d(24) xor d(23) xor d(22) xor d(20) xor d(19) xor d(18) xor d(10) xor d(6) xor d(4) xor d(3) xor d(0) xor c(6) xor c(7) xor c(9) xor c(10) xor c(12) xor c(15) xor c(16) xor c(17) xor c(20) xor c(22) xor c(23) xor c(25) xor c(27) xor c(28) xor c(29) xor c(30); + newcrc(27) := d(63) xor d(62) xor d(61) xor d(60) xor d(58) xor d(56) xor d(55) xor d(53) xor d(50) xor d(49) xor d(48) xor d(45) xor d(43) xor d(42) xor d(40) xor d(39) xor d(32) xor d(29) xor d(27) xor d(26) xor d(25) xor d(24) xor d(23) xor d(21) xor d(20) xor d(19) xor d(11) xor d(7) xor d(5) xor d(4) xor d(1) xor c(0) xor c(7) xor c(8) xor c(10) xor c(11) xor c(13) xor c(16) xor c(17) xor c(18) xor c(21) xor c(23) xor c(24) xor c(26) xor c(28) xor c(29) xor c(30) xor c(31); + newcrc(28) := d(63) xor d(62) xor d(61) xor d(59) xor d(57) xor d(56) xor d(54) xor d(51) xor d(50) xor d(49) xor d(46) xor d(44) xor d(43) xor d(41) xor d(40) xor d(33) xor d(30) xor d(28) xor d(27) xor d(26) xor d(25) xor d(24) xor d(22) xor d(21) xor d(20) xor d(12) xor d(8) xor d(6) xor d(5) xor d(2) xor c(1) xor c(8) xor c(9) xor c(11) xor c(12) xor c(14) xor c(17) xor c(18) xor c(19) xor c(22) xor c(24) xor c(25) xor c(27) xor c(29) xor c(30) xor c(31); + newcrc(29) := d(63) xor d(62) xor d(60) xor d(58) xor d(57) xor d(55) xor d(52) xor d(51) xor d(50) xor d(47) xor d(45) xor d(44) xor d(42) xor d(41) xor d(34) xor d(31) xor d(29) xor d(28) xor d(27) xor d(26) xor d(25) xor d(23) xor d(22) xor d(21) xor d(13) xor d(9) xor d(7) xor d(6) xor d(3) xor c(2) xor c(9) xor c(10) xor c(12) xor c(13) xor c(15) xor c(18) xor c(19) xor c(20) xor c(23) xor c(25) xor c(26) xor c(28) xor c(30) xor c(31); + newcrc(30) := d(63) xor d(61) xor d(59) xor d(58) xor d(56) xor d(53) xor d(52) xor d(51) xor d(48) xor d(46) xor d(45) xor d(43) xor d(42) xor d(35) xor d(32) xor d(30) xor d(29) xor d(28) xor d(27) xor d(26) xor d(24) xor d(23) xor d(22) xor d(14) xor d(10) xor d(8) xor d(7) xor d(4) xor c(0) xor c(3) xor c(10) xor c(11) xor c(13) xor c(14) xor c(16) xor c(19) xor c(20) xor c(21) xor c(24) xor c(26) xor c(27) xor c(29) xor c(31); + newcrc(31) := d(62) xor d(60) xor d(59) xor d(57) xor d(54) xor d(53) xor d(52) xor d(49) xor d(47) xor d(46) xor d(44) xor d(43) xor d(36) xor d(33) xor d(31) xor d(30) xor d(29) xor d(28) xor d(27) xor d(25) xor d(24) xor d(23) xor d(15) xor d(11) xor d(9) xor d(8) xor d(5) xor c(1) xor c(4) xor c(11) xor c(12) xor c(14) xor c(15) xor c(17) xor c(20) xor c(21) xor c(22) xor c(25) xor c(27) xor c(28) xor c(30); + return newcrc; + end nextCRC32_D64; + +end PCK_CRC32_D64; Index: fade_ether_protocol/trunk/experimental_fade_10g/fpga/kc705_fade_top.vhd =================================================================== --- fade_ether_protocol/trunk/experimental_fade_10g/fpga/kc705_fade_top.vhd (nonexistent) +++ fade_ether_protocol/trunk/experimental_fade_10g/fpga/kc705_fade_top.vhd (revision 12) @@ -0,0 +1,580 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.pkt_ack_pkg.all; +use work.desc_mgr_pkg.all; + +entity kc705_10g_2 is + + port ( + gtx10g_txn : out std_logic; + gtx10g_txp : out std_logic; + gtx10g_rxn : in std_logic; + gtx10g_rxp : in std_logic; + gtx_refclk_n : in std_logic; + gtx_refclk_p : in std_logic; + --xgmii_txd : in std_logic_vector(63 downto 0); + --xgmii_txc : in std_logic_vector(7 downto 0); + --xgmii_rxd : out std_logic_vector(63 downto 0); + --xgmii_rxc : out std_logic_vector(7 downto 0); + txusrclk_out : out std_logic; + txusrclk2_out : out std_logic; + resetdone : out std_logic; + core_ready : out std_logic; + trig_ack : out std_logic; + led5 : out std_logic; + clk_2 : in std_logic; + start : in std_logic; + rst_p : in std_logic); + +end kc705_10g_2; + +architecture beh1 of kc705_10g_2 is + + signal heart_bit : integer := 0; + + signal refclk_p : std_logic := '0'; + signal refclk_n : std_logic := '0'; + signal reset : std_logic := '0'; + signal s_resetdone : std_logic := '0'; + signal core_clk156_out : std_logic := '0'; + signal txp : std_logic := '0'; + signal txn : std_logic := '0'; + signal rxp : std_logic := '0'; + signal rxn : std_logic := '0'; + signal dclk_out : std_logic := '0'; + signal s_txusrclk_out : std_logic := '0'; + signal s_txusrclk2_out : std_logic := '0'; + signal areset_clk156_out : std_logic := '0'; + signal gttxreset_out : std_logic := '0'; + signal gtrxreset_out : std_logic := '0'; + signal txuserrdy_out : std_logic := '0'; + signal reset_counter_done_out : std_logic := '0'; + signal qplllock_out : std_logic := '0'; + signal qplloutclk_out : std_logic := '0'; + signal qplloutrefclk_out : std_logic := '0'; + signal xgmii_txd : std_logic_vector(63 downto 0) := (others => '0'); + signal xgmii_txc : std_logic_vector(7 downto 0) := (others => '0'); + signal xgmii_rxd : std_logic_vector(63 downto 0) := (others => '0'); + signal xgmii_rxc : std_logic_vector(7 downto 0) := (others => '0'); + signal configuration_vector : std_logic_vector(535 downto 0) := (others => '0'); + signal status_vector : std_logic_vector(447 downto 0) := (others => '0'); + signal core_status : std_logic_vector(7 downto 0) := (others => '0'); + signal signal_detect : std_logic := '0'; + signal tx_fault : std_logic := '0'; + signal drp_req : std_logic := '0'; + signal drp_gnt : std_logic := '0'; + signal drp_den_o : std_logic := '0'; + signal drp_dwe_o : std_logic := '0'; + signal drp_daddr_o : std_logic_vector(15 downto 0) := (others => '0'); + signal drp_di_o : std_logic_vector(15 downto 0) := (others => '0'); + signal drp_drdy_o : std_logic := '0'; + signal drp_drpdo_o : std_logic_vector(15 downto 0) := (others => '0'); + signal drp_den_i : std_logic := '0'; + signal drp_dwe_i : std_logic := '0'; + signal drp_daddr_i : std_logic_vector(15 downto 0) := (others => '0'); + signal drp_di_i : std_logic_vector(15 downto 0) := (others => '0'); + signal drp_drdy_i : std_logic := '0'; + signal drp_drpdo_i : std_logic_vector(15 downto 0) := (others => '0'); + signal tx_disable : std_logic := '0'; + + signal counter : integer := 0; + signal probe2 : std_logic_vector(0 downto 0); + signal trig_in, trig_in_ack : std_logic := '0'; + signal rst_n, rst1, clk1 : std_logic := '0'; + signal hb_led : std_logic := '0'; + signal s_led5 : std_logic := '0'; + + -- Signals associated with the FADE core + signal my_mac : std_logic_vector(47 downto 0); + signal sender : std_logic_vector(47 downto 0); + signal peer_mac : std_logic_vector(47 downto 0); + constant my_ether_type : std_logic_vector(15 downto 0) := x"fade"; + signal transm_delay : unsigned(31 downto 0); + signal restart : std_logic; + signal fade_rst_n, fade_rst_del : std_logic := '0'; + signal fade_rst_p : std_logic; + + signal dta : std_logic_vector(63 downto 0); + signal test_dta : unsigned(31 downto 0); + signal s_dta_we, dta_we : std_logic := '0'; + signal dta_ready : std_logic; + signal snd_start : std_logic; + signal snd_ready : std_logic; + signal clk_user : std_logic; + signal dmem_we : std_logic; + signal dmem_addr : std_logic_vector(LOG2_N_OF_PKTS+LOG2_NWRDS_IN_PKT-1 downto 0); + signal dmem_dta : std_logic_vector(63 downto 0); + signal tx_mem_addr : std_logic_vector(LOG2_N_OF_PKTS+LOG2_NWRDS_IN_PKT-1 downto 0); + signal tx_mem_data : std_logic_vector(63 downto 0); + signal set_number : unsigned(15 downto 0); + signal pkt_number : unsigned(15 downto 0); + signal retry_number : unsigned(15 downto 0) := (others => '0'); + signal start_pkt, stop_pkt : unsigned(7 downto 0) := (others => '0'); + + -- debug signals + signal dbg : std_logic_vector(3 downto 0); + signal rx_crc : std_logic_vector(31 downto 0); + signal rx_cmd : std_logic_vector(31 downto 0); + signal rx_arg : std_logic_vector(31 downto 0); + + signal ack_fifo_din, ack_fifo_dout : std_logic_vector(pkt_ack_width-1 downto 0); + signal ack_fifo_wr_en, ack_fifo_rd_en, ack_fifo_empty, ack_fifo_full : std_logic; + signal ack_fifo_dbg : pkt_ack; + signal transmit_data : std_logic := '0'; + + component ila_0 + port ( + clk : in std_logic; + trig_in : in std_logic; + trig_in_ack : out std_logic; + probe0 : in std_logic_vector(63 downto 0); + probe1 : in std_logic_vector(7 downto 0); + probe2 : in std_logic_vector(0 downto 0); + probe3 : in std_logic_vector(7 downto 0); + probe4 : in std_logic_vector(3 downto 0); + probe5 : in std_logic_vector(31 downto 0); + probe6 : in std_logic_vector(7 downto 0); + probe7 : in std_logic_vector(15 downto 0); + probe8 : in std_logic_vector(7 downto 0); + probe9 : in std_logic_vector(31 downto 0); + probe10 : in std_logic_vector(31 downto 0) + ); + end component; + + component ten_gig_eth_pcs_pma_0 + port ( + refclk_p : in std_logic; + refclk_n : in std_logic; + reset : in std_logic; + resetdone : out std_logic; + core_clk156_out : out std_logic; + txp : out std_logic; + txn : out std_logic; + rxp : in std_logic; + rxn : in std_logic; + dclk_out : out std_logic; + txusrclk_out : out std_logic; + txusrclk2_out : out std_logic; + areset_clk156_out : out std_logic; + gttxreset_out : out std_logic; + gtrxreset_out : out std_logic; + txuserrdy_out : out std_logic; + reset_counter_done_out : out std_logic; + qplllock_out : out std_logic; + qplloutclk_out : out std_logic; + qplloutrefclk_out : out std_logic; + xgmii_txd : in std_logic_vector(63 downto 0); + xgmii_txc : in std_logic_vector(7 downto 0); + xgmii_rxd : out std_logic_vector(63 downto 0); + xgmii_rxc : out std_logic_vector(7 downto 0); + configuration_vector : in std_logic_vector(535 downto 0); + status_vector : out std_logic_vector(447 downto 0); + core_status : out std_logic_vector(7 downto 0); + signal_detect : in std_logic; + tx_fault : in std_logic; + drp_req : out std_logic; + drp_gnt : in std_logic; + drp_den_o : out std_logic; + drp_dwe_o : out std_logic; + drp_daddr_o : out std_logic_vector(15 downto 0); + drp_di_o : out std_logic_vector(15 downto 0); + drp_drdy_o : out std_logic; + drp_drpdo_o : out std_logic_vector(15 downto 0); + drp_den_i : in std_logic; + drp_dwe_i : in std_logic; + drp_daddr_i : in std_logic_vector(15 downto 0); + drp_di_i : in std_logic_vector(15 downto 0); + drp_drdy_i : in std_logic; + drp_drpdo_i : in std_logic_vector(15 downto 0); + tx_disable : out std_logic; + gt0_eyescanreset : in std_logic; + gt0_eyescandataerror : out std_logic; + gt0_txbufstatus : out std_logic_vector(1 downto 0); + gt0_rxbufstatus : out std_logic_vector(2 downto 0); + gt0_eyescantrigger : in std_logic; + gt0_rxcdrhold : in std_logic; + gt0_txprbsforceerr : in std_logic; + gt0_txpolarity : in std_logic; + gt0_rxpolarity : in std_logic; + gt0_rxprbserr : out std_logic; + gt0_txpmareset : in std_logic; + gt0_rxpmareset : in std_logic; + gt0_txresetdone : out std_logic; + gt0_rxresetdone : out std_logic; + gt0_rxdfelpmreset : in std_logic; + gt0_rxlpmen : in std_logic; + gt0_dmonitorout : out std_logic_vector(7 downto 0); + gt0_rxrate : in std_logic_vector(2 downto 0); + gt0_txprecursor : in std_logic_vector(4 downto 0); + gt0_txpostcursor : in std_logic_vector(4 downto 0); + gt0_txdiffctrl : in std_logic_vector(3 downto 0) + ); + end component; + + component eth_receiver is + port ( + peer_mac : out std_logic_vector(47 downto 0); + my_mac : in std_logic_vector(47 downto 0); + my_ether_type : in std_logic_vector(15 downto 0); + transmit_data : out std_logic; + restart : out std_logic; + ack_fifo_full : in std_logic; + ack_fifo_wr_en : out std_logic; + ack_fifo_din : out std_logic_vector(pkt_ack_width-1 downto 0); + clk : in std_logic; + rst_n : in std_logic; + dbg : out std_logic_vector(3 downto 0); + crc : out std_logic_vector(31 downto 0); + cmd : out std_logic_vector(31 downto 0); + arg : out std_logic_vector(31 downto 0); + Rx_Clk : in std_logic; + RxC : in std_logic_vector(7 downto 0); + RxD : in std_logic_vector(63 downto 0)); + end component eth_receiver; + + component eth_sender is + port ( + peer_mac : in std_logic_vector(47 downto 0); + my_mac : in std_logic_vector(47 downto 0); + my_ether_type : in std_logic_vector(15 downto 0); + set_number : in unsigned(15 downto 0); + pkt_number : in unsigned(15 downto 0); + retry_number : in unsigned(15 downto 0); + transm_delay : in unsigned(31 downto 0); + clk : in std_logic; + rst_n : in std_logic; + ready : out std_logic; + start : in std_logic; + tx_mem_addr : out std_logic_vector(LOG2_N_OF_PKTS+LOG2_NWRDS_IN_PKT-1 downto 0); + tx_mem_data : in std_logic_vector(63 downto 0); + Tx_Clk : in std_logic; + TxC : out std_logic_vector(7 downto 0); + TxD : out std_logic_vector(63 downto 0)); + end component eth_sender; + + component dp_ram_scl + generic ( + DATA_WIDTH : integer; + ADDR_WIDTH : integer); + port ( + clk_a : in std_logic; + we_a : in std_logic; + addr_a : in std_logic_vector(ADDR_WIDTH-1 downto 0); + data_a : in std_logic_vector(DATA_WIDTH-1 downto 0); + q_a : out std_logic_vector(DATA_WIDTH-1 downto 0); + clk_b : in std_logic; + we_b : in std_logic; + addr_b : in std_logic_vector(ADDR_WIDTH-1 downto 0); + data_b : in std_logic_vector(DATA_WIDTH-1 downto 0); + q_b : out std_logic_vector(DATA_WIDTH-1 downto 0)); + end component; + + component ack_fifo + port ( + rst : in std_logic; + wr_clk : in std_logic; + rd_clk : in std_logic; + din : in std_logic_vector(pkt_ack_width-1 downto 0); + wr_en : in std_logic; + rd_en : in std_logic; + dout : out std_logic_vector(pkt_ack_width-1 downto 0); + full : out std_logic; + empty : out std_logic); + end component; + + + component desc_manager + generic ( + N_OF_PKTS : integer); + port ( + dta : in std_logic_vector(63 downto 0); + dta_we : in std_logic; + dta_ready : out std_logic; + set_number : out unsigned(15 downto 0); + pkt_number : out unsigned(15 downto 0); + snd_start : out std_logic; + snd_ready : in std_logic; + dmem_addr : out std_logic_vector(LOG2_N_OF_PKTS+LOG2_NWRDS_IN_PKT-1 downto 0); + dmem_dta : out std_logic_vector(63 downto 0); + dmem_we : out std_logic; + ack_fifo_empty : in std_logic; + ack_fifo_rd_en : out std_logic; + ack_fifo_dout : in std_logic_vector(pkt_ack_width-1 downto 0); + transmit_data : in std_logic; + transm_delay : out unsigned(31 downto 0); + clk : in std_logic; + rst_n : in std_logic); + end component; + +begin -- beh1 + my_mac <= x"de_ad_ba_be_be_ef"; + -- Initialization vector + configuration_vector(33) <= '1'; -- training + configuration_vector(284) <= '1'; -- auto negotiation + + signal_detect <= '1'; -- allow transmission! + + rst_n <= not rst_p; + refclk_n <= gtx_refclk_n; + refclk_p <= gtx_refclk_p; + reset <= not rst_n; + + trig_in <= '1' when xgmii_rxc /= x"ff" else '0'; + + + ila_0_1 : entity work.ila_0 + port map ( + clk => clk1, + trig_in => trig_in, + trig_in_ack => trig_ack, + probe0 => xgmii_rxd, + probe1 => xgmii_rxc, + probe2 => probe2, + probe3 => core_status, + probe4 => dbg, + probe5 => rx_crc, + probe6 => std_logic_vector(ack_fifo_dbg.pkt), + probe7 => std_logic_vector(ack_fifo_dbg.set), + probe8 => std_logic_vector(ack_fifo_dbg.cmd), + probe9 => rx_cmd, + probe10 => rx_arg + ); + + probe2(0) <= ack_fifo_full; + ack_fifo_dbg <= stlv_to_pkt_ack(ack_fifo_din); + + ten_gig_eth_pcs_pma_0_1 : ten_gig_eth_pcs_pma_0 + + port map ( + refclk_p => refclk_p, + refclk_n => refclk_n, + reset => reset, + resetdone => s_resetdone, + core_clk156_out => core_clk156_out, + txp => gtx10g_txp, + txn => gtx10g_txn, + rxp => gtx10g_rxp, + rxn => gtx10g_rxn, + dclk_out => dclk_out, + txusrclk_out => s_txusrclk_out, + txusrclk2_out => s_txusrclk2_out, + areset_clk156_out => areset_clk156_out, + gttxreset_out => gttxreset_out, + gtrxreset_out => gtrxreset_out, + txuserrdy_out => txuserrdy_out, + reset_counter_done_out => reset_counter_done_out, + qplllock_out => qplllock_out, + qplloutclk_out => qplloutclk_out, + qplloutrefclk_out => qplloutrefclk_out, + xgmii_txd => xgmii_txd, + xgmii_txc => xgmii_txc, + xgmii_rxd => xgmii_rxd, + xgmii_rxc => xgmii_rxc, + configuration_vector => configuration_vector, + status_vector => status_vector, + core_status => core_status, + signal_detect => signal_detect, + tx_fault => tx_fault, + drp_req => drp_req, + drp_gnt => drp_gnt, + drp_den_o => drp_den_o, + drp_dwe_o => drp_dwe_o, + drp_daddr_o => drp_daddr_o, + drp_di_o => drp_di_o, + drp_drdy_o => drp_drdy_o, + drp_drpdo_o => drp_drpdo_o, + drp_den_i => drp_den_i, + drp_dwe_i => drp_dwe_i, + drp_daddr_i => drp_daddr_i, + drp_di_i => drp_di_i, + drp_drdy_i => drp_drdy_i, + drp_drpdo_i => drp_drpdo_i, + tx_disable => tx_disable, + gt0_eyescanreset => '0', + gt0_eyescandataerror => open, + gt0_txbufstatus => open, + gt0_rxbufstatus => open, + gt0_eyescantrigger => '0', + gt0_rxcdrhold => '0', + gt0_txprbsforceerr => '0', + gt0_txpolarity => '1', + gt0_rxpolarity => '1', + gt0_rxprbserr => open, + gt0_txpmareset => '0', + gt0_rxpmareset => '0', + gt0_txresetdone => open, + gt0_rxresetdone => open, + gt0_rxdfelpmreset => '0', + gt0_rxlpmen => '0', + gt0_dmonitorout => open, + gt0_rxrate => (others => '0'), + gt0_txprecursor => (others => '0'), + gt0_txpostcursor => (others => '0'), + gt0_txdiffctrl => "1110" + + ); + + drp_gnt <= drp_req; + drp_den_i <= drp_den_o; + drp_dwe_i <= drp_dwe_o; + drp_daddr_i <= drp_daddr_o; + drp_di_i <= drp_di_o; + drp_drpdo_i <= drp_drpdo_o; + + txusrclk_out <= rst_n; --s_txusrclk_out; + resetdone <= hb_led; --s_resetdone; + + rst1 <= core_status(0); + core_ready <= core_status(0); + clk1 <= core_clk156_out; + clk_user <= core_clk156_out; + + + + p1 : process (clk1, rst_n) + begin -- process p1 + if rst_n = '0' then -- asynchronous reset (active low) + heart_bit <= 0; + elsif clk1'event and clk1 = '1' then -- rising clock edge + if heart_bit < 80000000 then + heart_bit <= heart_bit + 1; + else + heart_bit <= 0; + hb_led <= not hb_led; + end if; + end if; + end process p1; + + --addr_a <= to_integer(unsigned(dmem_addr)); + --addr_b <= to_integer(unsigned(tx_mem_addr)); + + dp_ram_scl_1 : dp_ram_scl + generic map ( + DATA_WIDTH => 64, + ADDR_WIDTH => LOG2_N_OF_PKTS+LOG2_NWRDS_IN_PKT) + port map ( + clk_a => clk_user, + we_a => dmem_we, + addr_a => dmem_addr, + data_a => dmem_dta, + q_a => open, + clk_b => clk1, + we_b => '0', + addr_b => tx_mem_addr, + data_b => (others => '0'), + q_b => tx_mem_data); + + desc_manager_1 : desc_manager + generic map ( + N_OF_PKTS => N_OF_PKTS) + port map ( + dta => dta, + dta_we => dta_we, + dta_ready => dta_ready, + set_number => set_number, + pkt_number => pkt_number, + snd_start => snd_start, + snd_ready => snd_ready, + dmem_addr => dmem_addr, + dmem_dta => dmem_dta, + dmem_we => dmem_we, + ack_fifo_empty => ack_fifo_empty, + ack_fifo_rd_en => ack_fifo_rd_en, + ack_fifo_dout => ack_fifo_dout, + transmit_data => transmit_data, + transm_delay => transm_delay, + clk => clk_user, + rst_n => fade_rst_n); + + eth_sender_1 : eth_sender + port map ( + peer_mac => peer_mac, + my_mac => my_mac, + my_ether_type => my_ether_type, + set_number => set_number, + pkt_number => pkt_number, + retry_number => retry_number, + transm_delay => transm_delay, + clk => clk_user, + rst_n => fade_rst_n, + ready => snd_ready, + start => snd_start, + tx_mem_addr => tx_mem_addr, + tx_mem_data => tx_mem_data, + Tx_Clk => clk1, + TxC => xgmii_txc, + TxD => xgmii_txd); + + eth_receiver_2 : eth_receiver + port map ( + peer_mac => peer_mac, + my_mac => my_mac, + my_ether_type => my_ether_type, + transmit_data => transmit_data, + restart => restart, + ack_fifo_full => ack_fifo_full, + ack_fifo_wr_en => ack_fifo_wr_en, + ack_fifo_din => ack_fifo_din, + clk => clk_user, + rst_n => fade_rst_n, + dbg => dbg, + cmd => rx_cmd, + arg => rx_arg, + Rx_Clk => clk1, + RxC => xgmii_rxc, + RxD => xgmii_rxd); + + ack_fifo_1 : ack_fifo + port map ( + rst => fade_rst_p, + wr_clk => clk1, + rd_clk => Clk_user, + din => ack_fifo_din, + wr_en => ack_fifo_wr_en, + rd_en => ack_fifo_rd_en, + dout => ack_fifo_dout, + full => ack_fifo_full, + empty => ack_fifo_empty); + + + -- signal generator + + dta <= std_logic_vector(test_dta) & std_logic_vector(test_dta+1); + s_dta_we <= '1' when dta_ready = '1' and transmit_data = '1' else '0'; + dta_we <= s_dta_we; + + process (Clk_user, rst_n) + begin -- process + if rst_n = '0' then -- asynchronous reset (active low) + test_dta <= (others => '0'); + elsif Clk_user'event and Clk_user = '1' then -- rising clock edge + if s_dta_we = '1' then + if test_dta < 2_000_000_000 then + test_dta <= test_dta + 2; + else + test_dta <= (others => '0'); + end if; + end if; + end if; + end process; + + process (Clk_user, rst_n) + begin -- process + if rst_n = '0' then -- asynchronous reset (active low) + fade_rst_n <= '0'; + fade_rst_del <= '0'; + elsif Clk_user'event and Clk_user = '1' then -- rising clock edge + if restart = '1' then + fade_rst_n <= '0'; + fade_rst_del <= '0'; + else + fade_rst_del <= '1'; + fade_rst_n <= fade_rst_del; + end if; + end if; + end process; + + fade_rst_p <= not fade_rst_p; + +end beh1; Index: fade_ether_protocol/trunk/experimental_fade_10g/fpga/eth_sender64.vhd =================================================================== --- fade_ether_protocol/trunk/experimental_fade_10g/fpga/eth_sender64.vhd (nonexistent) +++ fade_ether_protocol/trunk/experimental_fade_10g/fpga/eth_sender64.vhd (revision 12) @@ -0,0 +1,369 @@ +------------------------------------------------------------------------------- +-- Title : FPGA Ethernet interface - block sending packets via XGMII Phy +-- Project : +------------------------------------------------------------------------------- +-- File : eth_sender64.vhd +-- Author : Wojciech M. Zabolotny (wzab@ise.pw.edu.pl) +-- License : BSD License +-- Company : +-- Created : 2012-03-30 +-- Last update: 2014-04-20 +-- Platform : +-- Standard : VHDL'93 +------------------------------------------------------------------------------- +-- Description: This file implements the state machine, which manages the +-- table of packet descriptors, used to resend only not confirmed packets +------------------------------------------------------------------------------- +-- Copyright (c) 2012 +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2012-03-30 1.0 WZab Created +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library work; +use work.desc_mgr_pkg.all; +use work.PCK_CRC32_D64.all; +use work.PCK_CRC32_D32.all; + +entity eth_sender is + + port ( + -- Configuration + peer_mac : in std_logic_vector(47 downto 0); + my_mac : in std_logic_vector(47 downto 0); + my_ether_type : in std_logic_vector(15 downto 0); + set_number : in unsigned(15 downto 0); + pkt_number : in unsigned(15 downto 0); + retry_number : in unsigned(15 downto 0); + transm_delay : in unsigned(31 downto 0); + -- System interface + clk : in std_logic; + rst_n : in std_logic; + -- Control interface + ready : out std_logic; + start : in std_logic; + -- Data memory interface + tx_mem_addr : out std_logic_vector(LOG2_N_OF_PKTS+LOG2_NWRDS_IN_PKT-1 downto 0); + tx_mem_data : in std_logic_vector(63 downto 0); + -- TX Phy interface + Tx_Clk : in std_logic; + TxC : out std_logic_vector(7 downto 0); + TxD : out std_logic_vector(63 downto 0) + ); + +end eth_sender; + + +architecture beh1 of eth_sender is + + type T_ETH_SENDER_STATE is (WST_IDLE, WST_SEND_PREAMB_AND_SOF, + WST_SEND_HEADER, WST_SEND_DATA, WST_SEND_CRC_AND_EOF, + WST_SEND_COMPLETED); + + type T_ETH_SENDER_REGS is record + state : T_ETH_SENDER_STATE; + ready : std_logic; + count : integer; + word : integer; + mem_addr : unsigned (LOG2_NWRDS_IN_PKT-1 downto 0); + crc32 : std_logic_vector(31 downto 0); + end record; + + constant ETH_SENDER_REGS_INI : T_ETH_SENDER_REGS := ( + state => WST_IDLE, + ready => '1', + count => 0, + word => 0, + mem_addr => (others => '0'), + crc32 => (others => '0') + ) ; + + signal r, r_n : T_ETH_SENDER_REGS := ETH_SENDER_REGS_INI; + + type T_ETH_SENDER_COMB is record + TxD : std_logic_vector(63 downto 0); + TxC : std_logic_vector(7 downto 0); + mem_addr : unsigned(LOG2_NWRDS_IN_PKT-1 downto 0); + end record; + + constant ETH_SENDER_COMB_DEFAULT : T_ETH_SENDER_COMB := ( + TxD => x"07_07_07_07_07_07_07_07", + TxC => (others => '1'), + mem_addr => (others => '0') + ); + + signal c : T_ETH_SENDER_COMB := ETH_SENDER_COMB_DEFAULT; + + signal s_header : std_logic_vector(6*32-1 downto 0) := (others => '0'); + constant HEADER_LEN : integer := 3; -- 3 words, 8 bytes each + + + -- The function select_8bytes changes order of bytes, ensuring + -- that the MSB is transmitted first... + + function select_8bytes ( + constant vec : std_logic_vector; + constant chunk_num : integer) + return std_logic_vector is + variable byte_ofs : integer; + variable chunk_ofs : integer; + variable v_bytes : std_logic_vector(63 downto 0); + begin + chunk_ofs := chunk_num*64; + -- first select byte + for byte_num in 0 to 7 loop + byte_ofs := byte_num * 8; + v_bytes(byte_ofs+7 downto byte_ofs) := vec(vec'left-chunk_ofs-byte_ofs downto vec'left-chunk_ofs-byte_ofs-7); + end loop; -- byte_num + return v_bytes; + end select_8bytes; + + + function rev(a : in std_logic_vector) + return std_logic_vector is + variable result : std_logic_vector(a'range); + alias aa : std_logic_vector(a'reverse_range) is a; + begin + for i in aa'range loop + result(i) := aa(i); + end loop; + return result; + end; -- function reverse_any_bus + + -- The function below changes the order of bytes and order of bits in the + -- bytes so that the CRC32 is correctly updated... + -- We assume, that argument of this function are the data delivered + -- to the TxD, so they are transmitted starting from the least significant + -- byte + function crc_8bytes ( + constant vec : std_logic_vector(63 downto 0); + constant old_crc : std_logic_vector(31 downto 0)) + return std_logic_vector is + variable new_crc : std_logic_vector(31 downto 0); + variable reordered_data : std_logic_vector(63 downto 0); + begin -- function crc_8bytes + -- for bn in 0 to 7 loop + -- for i in 0 to 7 loop + -- reordered_data(bn*8+i) := vec(bn*8+7-i); + -- end loop; + --end loop; + new_crc := nextCRC32_D64(rev(vec), old_crc); + return new_crc; + end function crc_8bytes; + + signal tx_rst_n, tx_rst_n_0, tx_rst_n_1 : std_logic := '0'; + signal update_flag_0, update_flag_1, update_flag : std_logic := '0'; + + signal start_0, tx_start, tx_start_1, tx_start_0 : std_logic := '0'; + signal tx_ready, ready_0, ready_1 : std_logic := '0'; + + type T_STATE1 is (ST1_IDLE, ST1_WAIT_NOT_READY, ST1_WAIT_NOT_START, + ST1_WAIT_READY); + signal state1 : T_STATE1; + + type T_STATE2 is (ST2_IDLE, ST2_WAIT_NOT_READY, ST2_WAIT_READY); + signal state2 : T_STATE2; +begin -- beh1 + + -- Packet header + s_header <= peer_mac & my_mac & my_ether_type & x"a5a5" & + std_logic_vector(set_number(15 downto 0)) & + std_logic_vector(pkt_number(5 downto 0)) & + std_logic_vector(retry_number(9 downto 0)) & + std_logic_vector(transm_delay); + -- Connection of the signals + + -- The memory address is built from the packet number (6 bits) and word + -- number (8 bits) + tx_mem_addr <= std_logic_vector(pkt_number(LOG2_N_OF_PKTS-1 downto 0)) & std_logic_vector(c.mem_addr); + + -- Main state machine used to send the packet + -- W calej maszynie trzeba jeszcze dodac obsluge kolizji!!! + -- Oprocz tego trzeba przeanalizowac poprawnosc przejsc miedzy domenami zegara + + + snd1 : process (Tx_Clk, tx_rst_n) + begin + if tx_rst_n = '0' then -- asynchronous reset (active low) + r <= ETH_SENDER_REGS_INI; + TxD <= x"07_07_07_07_07_07_07_07"; + TxC <= (others => '1'); + elsif Tx_Clk'event and Tx_Clk = '1' then -- rising clock edge + r <= r_n; + -- To minimize glitches and propagation delay, let's add pipeline register + TxC <= c.TxC; + TxD <= c.TxD; + end if; + end process snd1; -- snd1 + + snd2 : process (r, s_header, tx_mem_data, tx_start) + variable v_TxD : std_logic_vector(63 downto 0); + begin -- process snd1 + -- default values + c <= ETH_SENDER_COMB_DEFAULT; + r_n <= r; + case r.state is + when WST_IDLE => + c.TxD <= x"07_07_07_07_07_07_07_07"; + c.TxC <= "11111111"; + r_n.ready <= '1'; + if tx_start = '1' then + r_n.ready <= '0'; + r_n.state <= WST_SEND_PREAMB_AND_SOF; + r_n.count <= 7; + end if; + when WST_SEND_PREAMB_AND_SOF => + -- Collision detection should be added? + c.TxD <= x"d5_55_55_55_55_55_55_fb"; + c.TxC <= "00000001"; + -- Prepare for sending of header + r_n.crc32 <= (others => '1'); + r_n.state <= WST_SEND_HEADER; + r_n.count <= 0; + when WST_SEND_HEADER => + v_TxD := select_8bytes(s_header, r.count); + c.TxD <= v_TxD; + c.TxC <= (others => '0'); + r_n.crc32 <= crc_8bytes(v_TxD, r.crc32); + if r.count < HEADER_LEN-1 then + r_n.count <= r.count + 1; + else + r_n.count <= 0; + r_n.word <= 0; + r_n.mem_addr <= (others => '0'); + c.mem_addr <= (others => '0'); + r_n.state <= WST_SEND_DATA; + end if; + when WST_SEND_DATA => + -- send the data byte by byte + -- we send data in the reversed byte order! (MSB first) + v_TxD := select_8bytes(tx_mem_data,0); + -- therefore to calculate the CRC we can simply reverse bits... + r_n.crc32 <= crc_8bytes(v_TxD, r.crc32); + c.TxD <= v_TxD; + c.TxC <= (others => '0'); + -- Check, if we have sent all the data + if r.mem_addr < NWRDS_IN_PKT-1 then + r_n.mem_addr <= r.mem_addr + 1; + c.mem_addr <= r.mem_addr + 1; + else + -- We send the CRC + r_n.state <= WST_SEND_CRC_AND_EOF; + end if; + when WST_SEND_CRC_AND_EOF => + -- The CRC should be send starting from the most significant bit, so + -- we don't need to reorder bytes in any way... + -- we only reverse it and complement it + v_TxD := x"07_07_07_fd" & not (rev(r.crc32)); + c.TxD <= v_TxD; + c.TxC <= "11110000"; + r_n.count <= 2; -- generate the IFG - 16 bytes = 2 words + r_n.state <= WST_SEND_COMPLETED; + when WST_SEND_COMPLETED => + c.TxD <= x"07_07_07_07_07_07_07_07"; + c.TxC <= "11111111"; + if r.count > 0 then + r_n.count <= r.count - 1; + else + r_n.ready <= '1'; + r_n.state <= WST_IDLE; + end if; + end case; + end process snd2; + + + -- Synchronization of the reset signal for the Tx_Clk domain + process (Tx_Clk, rst_n) + begin -- process + if rst_n = '0' then -- asynchronous reset (active low) + tx_rst_n_0 <= '0'; + tx_rst_n_1 <= '0'; + tx_rst_n <= '0'; + elsif Tx_Clk'event and Tx_Clk = '1' then -- rising clock edge + tx_rst_n_0 <= rst_n; + tx_rst_n_1 <= tx_rst_n_0; + tx_rst_n <= tx_rst_n_1; + end if; + end process; + + -- Synchronization of signals passing clock domains + -- Signal start is sent from the Clk domain. + -- When it is asserted, we must immediately deassert signal ready, + -- then generate the synchronized start and after internal ready + -- is asserted, we can output it again... + + -- Ustawienie na 1 takt zegara "clk" sygnalu start powinno zainicjowac wysylanie + -- w tym bloku musimy zadbac o stosowne wydluzenie sygnalu start i jego synchronizacje + -- miedzy domenami zegara... + process (clk, rst_n) + begin -- process + if rst_n = '0' then -- asynchronous reset (active low) + ready <= '0'; + ready_1 <= '0'; + ready_0 <= '0'; + state2 <= ST2_IDLE; + elsif clk'event and clk = '1' then -- rising clock edge + ready_1 <= tx_ready; + ready_0 <= ready_1; + case state2 is + when ST2_IDLE => + if start = '1' and ready_0 = '1' then + start_0 <= '1'; + ready <= '0'; + state2 <= ST2_WAIT_NOT_READY; + else + ready <= ready_0; -- Needed to provide correct start! + end if; + when ST2_WAIT_NOT_READY => + if ready_0 = '0' then + start_0 <= '0'; + state2 <= ST2_WAIT_READY; + end if; + when ST2_WAIT_READY => + if ready_0 = '1' then + ready <= '1'; + state2 <= ST2_IDLE; + end if; + when others => null; + end case; + end if; + end process; + + process (Tx_Clk, tx_rst_n) + begin -- process + if tx_rst_n = '0' then -- asynchronous reset (active low) + tx_start <= '0'; + tx_start_0 <= '0'; + state1 <= ST1_IDLE; + tx_ready <= '1'; + elsif Tx_Clk'event and Tx_Clk = '1' then -- rising clock edge + tx_start_0 <= start_0; + tx_start <= tx_start_0; + case state1 is + when ST1_IDLE => + if tx_start = '1' then + tx_ready <= '0'; -- this should cause tx_start to go low + state1 <= ST1_WAIT_NOT_READY; + end if; + when ST1_WAIT_NOT_READY => + if r.ready = '0' then + state1 <= ST1_WAIT_NOT_START; + end if; + when ST1_WAIT_NOT_START => + if tx_start = '0' then + state1 <= ST1_WAIT_READY; + end if; + when ST1_WAIT_READY => + if r.ready = '1' then + tx_ready <= '1'; + state1 <= ST1_IDLE; + end if; + when others => null; + end case; + end if; + end process; + +end beh1; Index: fade_ether_protocol/trunk/experimental_fade_10g/fpga/pkt_ack_pkg.vhd =================================================================== --- fade_ether_protocol/trunk/experimental_fade_10g/fpga/pkt_ack_pkg.vhd (nonexistent) +++ fade_ether_protocol/trunk/experimental_fade_10g/fpga/pkt_ack_pkg.vhd (revision 12) @@ -0,0 +1,48 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +package pkt_ack_pkg is + +type pkt_ack is record + pkt : unsigned(7 downto 0); + set : unsigned(15 downto 0); + cmd : unsigned(7 downto 0); +end record; + +constant pkt_ack_width : integer := 32; + +function pkt_ack_to_stlv( + constant din : pkt_ack) + return std_logic_vector; + +function stlv_to_pkt_ack( + constant din : std_logic_vector) + return pkt_ack; + +end pkt_ack_pkg; + +package body pkt_ack_pkg is + +function pkt_ack_to_stlv( + constant din : pkt_ack) + return std_logic_vector is + variable res : std_logic_vector(31 downto 0); +begin + res(7 downto 0) := std_logic_vector(din.pkt); + res(23 downto 8) := std_logic_vector(din.set); + res(31 downto 24) := std_logic_vector(din.cmd); + return res; +end pkt_ack_to_stlv; + +function stlv_to_pkt_ack( + constant din : std_logic_vector) + return pkt_ack is + variable res : pkt_ack; +begin + res.pkt:=unsigned(din(7 downto 0)); + res.set:=unsigned(din(23 downto 8)); + res.cmd:=unsigned(din(31 downto 24)); + return res; +end stlv_to_pkt_ack; + +end pkt_ack_pkg; Index: fade_ether_protocol/trunk/experimental_fade_10g/fpga/xc7k325ffg900.ucf =================================================================== --- fade_ether_protocol/trunk/experimental_fade_10g/fpga/xc7k325ffg900.ucf (nonexistent) +++ fade_ether_protocol/trunk/experimental_fade_10g/fpga/xc7k325ffg900.ucf (revision 12) @@ -0,0 +1,344 @@ +##----------------------------------------------------------------------------- +##----------------------------------------------------------------------------- +## Project : Series-7 Integrated Block for PCI Express +## File : xilinx_pcie_2_1_ep_7x_01_lane_gen2_xc7k325t-ffg900-2-PCIE_X0Y0.ucf +## Version : 1.6 +# +############################################################################### +# Define Device, Package And Speed Grade +############################################################################### + +CONFIG PART = xc7k325t-ffg900-2; + +######################################################################################################################### +# User Constraints +######################################################################################################################### + +############################################################################### +# User Time Names / User Time Groups / Time Specs +############################################################################### + +############################################################################### +# User Physical Constraints +############################################################################### +########### PCIE ######################### +#PCIe reset +NET "sys_rst_n" NODELAY = "TRUE"; +# Bank 16 VCCO - VADJ_FPGA - IO_25_16 +NET "sys_rst_n" IOSTANDARD = LVCMOS25; +NET "sys_rst_n" PULLUP; +NET "sys_rst_n" LOC = G25; +#PCIe clock +NET SYS_CLK_N LOC = U7; +# Bank 115 - MGTREFCLK1N_115 +NET "sys_clk_p" LOC = U8; # Bank 115 - MGTREFCLK1P_115 + +########### DDR controller ############## +NET "ddr3_dq[0]" LOC = "AA15" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L20P_T3_32 +NET "ddr3_dq[1]" LOC = "AA16" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L23N_T3_32 +NET "ddr3_dq[2]" LOC = "AC14" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L22P_T3_32 +NET "ddr3_dq[3]" LOC = "AD14" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L22N_T3_32 +NET "ddr3_dq[4]" LOC = "AA17" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L23P_T3_32 +NET "ddr3_dq[5]" LOC = "AB15" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L20N_T3_32 +NET "ddr3_dq[6]" LOC = "AE15" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L19P_T3_32 +NET "ddr3_dq[7]" LOC = "Y15" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L24N_T3_32 +NET "ddr3_dq[8]" LOC = "AB19" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L17P_T2_32 +NET "ddr3_dq[9]" LOC = "AD16" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L14N_T2_SRCC_32 +NET "ddr3_dq[10]" LOC = "AC19" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L17N_T2_32 +NET "ddr3_dq[11]" LOC = "AD17" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L14P_T2_SRCC_32 +NET "ddr3_dq[12]" LOC = "AA18" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L16P_T2_32 +NET "ddr3_dq[13]" LOC = "AB18" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L16N_T2_32 +NET "ddr3_dq[14]" LOC = "AE18" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L13N_T2_MRCC_32 +NET "ddr3_dq[15]" LOC = "AD18" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L13P_T2_MRCC_32 +NET "ddr3_dq[16]" LOC = "AG19" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L8P_T1_32 +NET "ddr3_dq[17]" LOC = "AK19" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L7N_T1_32 +NET "ddr3_dq[18]" LOC = "AG18" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L11N_T1_SRCC_32 +NET "ddr3_dq[19]" LOC = "AF18" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L11P_T1_SRCC_32 +NET "ddr3_dq[20]" LOC = "AH19" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L8N_T1_32 +NET "ddr3_dq[21]" LOC = "AJ19" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L7P_T1_32 +NET "ddr3_dq[22]" LOC = "AE19" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L10N_T1_32 +NET "ddr3_dq[23]" LOC = "AD19" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L10P_T1_32 +NET "ddr3_dq[24]" LOC = "AK16" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L1P_T0_32 +NET "ddr3_dq[25]" LOC = "AJ17" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L5N_T0_32 +NET "ddr3_dq[26]" LOC = "AG15" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L2P_T0_32 +NET "ddr3_dq[27]" LOC = "AF15" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L4P_T0_32 +NET "ddr3_dq[28]" LOC = "AH17" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L5P_T0_32 +NET "ddr3_dq[29]" LOC = "AG14" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L4N_T0_32 +NET "ddr3_dq[30]" LOC = "AH15" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L2N_T0_32 +NET "ddr3_dq[31]" LOC = "AK15" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L1N_T0_32 +NET "ddr3_dq[32]" LOC = "AK8" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L23N_T3_34 +NET "ddr3_dq[33]" LOC = "AK6" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L22N_T3_34 +NET "ddr3_dq[34]" LOC = "AG7" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L20N_T3_34 +NET "ddr3_dq[35]" LOC = "AF7" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L20P_T3_34 +NET "ddr3_dq[36]" LOC = "AF8" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L19P_T3_34 +NET "ddr3_dq[37]" LOC = "AK4" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L24N_T3_34 +NET "ddr3_dq[38]" LOC = "AJ8" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L23P_T3_34 +NET "ddr3_dq[39]" LOC = "AJ6" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L22P_T3_34 +NET "ddr3_dq[40]" LOC = "AH5" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L14N_T2_SRCC_34 +NET "ddr3_dq[41]" LOC = "AH6" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L14P_T2_SRCC_34 +NET "ddr3_dq[42]" LOC = "AJ2" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L16N_T2_34 +NET "ddr3_dq[43]" LOC = "AH2" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L16P_T2_34 +NET "ddr3_dq[44]" LOC = "AH4" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L13P_T2_MRCC_34 +NET "ddr3_dq[45]" LOC = "AJ4" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L13N_T2_MRCC_34 +NET "ddr3_dq[46]" LOC = "AK1" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L17N_T2_34 +NET "ddr3_dq[47]" LOC = "AJ1" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L17P_T2_34 +NET "ddr3_dq[48]" LOC = "AF1" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L8N_T1_34 +NET "ddr3_dq[49]" LOC = "AF2" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L7N_T1_34 +NET "ddr3_dq[50]" LOC = "AE4" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L10P_T1_34 +NET "ddr3_dq[51]" LOC = "AE3" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L10N_T1_34 +NET "ddr3_dq[52]" LOC = "AF3" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L7P_T1_34 +NET "ddr3_dq[53]" LOC = "AF5" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L11N_T1_SRCC_34 +NET "ddr3_dq[54]" LOC = "AE1" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L8P_T1_34 +NET "ddr3_dq[55]" LOC = "AE5" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L11P_T1_SRCC_34 +NET "ddr3_dq[56]" LOC = "AC1" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L2N_T0_34 +NET "ddr3_dq[57]" LOC = "AD3" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L1N_T0_34 +NET "ddr3_dq[58]" LOC = "AC4" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L4N_T0_34 +NET "ddr3_dq[59]" LOC = "AC5" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L4P_T0_34 +NET "ddr3_dq[60]" LOC = "AE6" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L5N_T0_34 +NET "ddr3_dq[61]" LOC = "AD6" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L5P_T0_34 +NET "ddr3_dq[62]" LOC = "AC2" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L2P_T0_34 +NET "ddr3_dq[63]" LOC = "AD4" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L1P_T0_34 +NET "ddr3_addr[13]" LOC = "AH11" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L18P_T2_33 +NET "ddr3_addr[12]" LOC = "AJ11" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L18N_T2_33 +NET "ddr3_addr[11]" LOC = "AE13" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L19P_T3_33 +NET "ddr3_addr[10]" LOC = "AF13" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L19N_T3_VREF_33 +NET "ddr3_addr[9]" LOC = "AK14" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L20P_T3_33 +NET "ddr3_addr[8]" LOC = "AK13" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L20N_T3_33 +NET "ddr3_addr[7]" LOC = "AH14" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L21P_T3_DQS_33 +NET "ddr3_addr[6]" LOC = "AJ14" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L21N_T3_DQS_33 +NET "ddr3_addr[5]" LOC = "AJ13" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L22P_T3_33 +NET "ddr3_addr[4]" LOC = "AJ12" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L22N_T3_33 +NET "ddr3_addr[3]" LOC = "AF12" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L23P_T3_33 +NET "ddr3_addr[2]" LOC = "AG12" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L23N_T3_33 +NET "ddr3_addr[1]" LOC = "AG13" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L24P_T3_33 +NET "ddr3_addr[0]" LOC = "AH12" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L24N_T3_33 +NET "ddr3_ba[2]" LOC = "AK9" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L15N_T2_DQS_33 +NET "ddr3_ba[1]" LOC = "AG9" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L16P_T2_33 +NET "ddr3_ba[0]" LOC = "AH9" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L16N_T2_33 +NET "ddr3_ras_n" LOC = "AD9" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L10P_T1_33 +NET "ddr3_cas_n" LOC = "AC11" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L9N_T1_DQS_33 +NET "ddr3_we_n" LOC = "AE9" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L10N_T1_33 +NET "ddr3_reset_n" LOC = "AK3" | IOSTANDARD = LVCMOS15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L18N_T2_34 +NET "ddr3_cke[0]" LOC = "AF10" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L14N_T2_SRCC_33 +NET "ddr3_odt[0]" LOC = "AD8" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L8P_T1_33 +NET "ddr3_cs_n[0]" LOC = "AC12" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L9P_T1_DQS_33 +NET "ddr3_dm[0]" LOC = "Y16" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L24P_T3_32 +NET "ddr3_dm[1]" LOC = "AB17" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L18P_T2_32 +NET "ddr3_dm[2]" LOC = "AF17" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L12P_T1_MRCC_32 +NET "ddr3_dm[3]" LOC = "AE16" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L6P_T0_32 +NET "ddr3_dm[4]" LOC = "AK5" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L24P_T3_34 +NET "ddr3_dm[5]" LOC = "AJ3" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L18P_T2_34 +NET "ddr3_dm[6]" LOC = "AF6" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L12P_T1_MRCC_34 +NET "ddr3_dm[7]" LOC = "AC7" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L6P_T0_34 +NET "ddr_sys_clk_p" LOC = "AD12" | IOSTANDARD = DIFF_SSTL15 | VCCAUX_IO = DONTCARE ; # Pad function: IO_L12P_T1_MRCC_33 +NET "ddr_sys_clk_n" LOC = "AD11" | IOSTANDARD = DIFF_SSTL15 | VCCAUX_IO = DONTCARE ; # Pad function: IO_L12N_T1_MRCC_33 +NET "ddr3_dqs_p[0]" LOC = "AC16" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L21P_T3_DQS_32 +NET "ddr3_dqs_n[0]" LOC = "AC15" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L21N_T3_DQS_32 +NET "ddr3_dqs_p[1]" LOC = "Y19" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L15P_T2_DQS_32 +NET "ddr3_dqs_n[1]" LOC = "Y18" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L15N_T2_DQS_32 +NET "ddr3_dqs_p[2]" LOC = "AJ18" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L9P_T1_DQS_32 +NET "ddr3_dqs_n[2]" LOC = "AK18" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L9N_T1_DQS_32 +NET "ddr3_dqs_p[3]" LOC = "AH16" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L3P_T0_DQS_32 +NET "ddr3_dqs_n[3]" LOC = "AJ16" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L3N_T0_DQS_32 +NET "ddr3_dqs_p[4]" LOC = "AH7" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L21P_T3_DQS_34 +NET "ddr3_dqs_n[4]" LOC = "AJ7" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L21N_T3_DQS_34 +NET "ddr3_dqs_p[5]" LOC = "AG2" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L15P_T2_DQS_34 +NET "ddr3_dqs_n[5]" LOC = "AH1" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L15N_T2_DQS_34 +NET "ddr3_dqs_p[6]" LOC = "AG4" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L9P_T1_DQS_34 +NET "ddr3_dqs_n[6]" LOC = "AG3" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L9N_T1_DQS_34 +NET "ddr3_dqs_p[7]" LOC = "AD2" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L3P_T0_DQS_34 +NET "ddr3_dqs_n[7]" LOC = "AD1" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L3N_T0_DQS_34 +NET "ddr3_ck_p[0]" LOC = "AG10" | IOSTANDARD = DIFF_SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L13P_T2_MRCC_33 +NET "ddr3_ck_n[0]" LOC = "AH10" | IOSTANDARD = DIFF_SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L13N_T2_MRCC_33 + +######################################################################################################################### +# End User Constraints +######################################################################################################################### +# +# +# +######################################################################################################################### +# PCIE Core Constraints +######################################################################################################################### + +############################################################################### +# Pinout and Related I/O Constraints +############################################################################### + +NET "sys_rst_n" TIG; + +# +# SYS clock 100 MHz (input) signal. The sys_clk_p and sys_clk_n +# signals are the PCI Express reference clock. Virtex-7 GT +# Transceiver architecture requires the use of a dedicated clock +# resources (FPGA input pins) associated with each GT Transceiver. +# To use these pins an IBUFDS primitive (refclk_ibuf) is +# instantiated in user's design. +# Please refer to the Virtex-7 GT Transceiver User Guide +# (UG) for guidelines regarding clock resource selection. +# + +INST "*/pcieclk_ibuf" LOC = IBUFDS_GTE2_X0Y1; + +# +# Transceiver instance placement. This constraint selects the +# transceivers to be used, which also dictates the pinout for the +# transmit and receive differential pairs. Please refer to the +# Virtex-7 GT Transceiver User Guide (UG) for more information. +# +# PCIe Lane 0 +INST "*/pcie_core_i/gt_top.gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gtx_channel.gtxe2_channel_i" LOC = GTXE2_CHANNEL_X0Y7; +# PCIe Lane 1 +INST "*/pcie_core_i/gt_top.gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/gtx_channel.gtxe2_channel_i" LOC = GTXE2_CHANNEL_X0Y6; +# PCIe Lane 2 +INST "*/pcie_core_i/gt_top.gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/gtx_channel.gtxe2_channel_i" LOC = GTXE2_CHANNEL_X0Y5; +# PCIe Lane 3 +INST "*/pcie_core_i/gt_top.gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/gtx_channel.gtxe2_channel_i" LOC = GTXE2_CHANNEL_X0Y4; + +# +# PCI Express Block placement. This constraint selects the PCI Express +# Block to be used. +# +INST "*/pcie_core_i/pcie_top_i/pcie_7x_i/pcie_block_i" LOC = PCIE_X0Y0; + +# +# BlockRAM placement +# +INST "*/pcie_core_i/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_rx/brams[3].ram/use_tdp.ramb36/bram36_tdp_bl.bram36_tdp_bl" LOC = RAMB36_X5Y35; +INST "*/pcie_core_i/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_rx/brams[2].ram/use_tdp.ramb36/bram36_tdp_bl.bram36_tdp_bl" LOC = RAMB36_X4Y36; +INST "*/pcie_core_i/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_rx/brams[1].ram/use_tdp.ramb36/bram36_tdp_bl.bram36_tdp_bl" LOC = RAMB36_X4Y35; +INST "*/pcie_core_i/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_rx/brams[0].ram/use_tdp.ramb36/bram36_tdp_bl.bram36_tdp_bl" LOC = RAMB36_X4Y34; +INST "*/pcie_core_i/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_tx/brams[0].ram/use_tdp.ramb36/bram36_tdp_bl.bram36_tdp_bl" LOC = RAMB36_X4Y33; +INST "*/pcie_core_i/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_tx/brams[1].ram/use_tdp.ramb36/bram36_tdp_bl.bram36_tdp_bl" LOC = RAMB36_X4Y32; +INST "*/pcie_core_i/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_tx/brams[2].ram/use_tdp.ramb36/bram36_tdp_bl.bram36_tdp_bl" LOC = RAMB36_X4Y31; +INST "*/pcie_core_i/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_tx/brams[3].ram/use_tdp.ramb36/bram36_tdp_bl.bram36_tdp_bl" LOC = RAMB36_X4Y30; + +# +# DDR controller component placement +# Check it after changing memory controller paramenters +# +INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out" LOC=PHASER_OUT_PHY_X1Y3; +INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out" LOC=PHASER_OUT_PHY_X1Y2; +INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out" LOC=PHASER_OUT_PHY_X1Y1; +INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out" LOC=PHASER_OUT_PHY_X1Y0; +INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out" LOC=PHASER_OUT_PHY_X1Y6; +INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out" LOC=PHASER_OUT_PHY_X1Y5; +INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out" LOC=PHASER_OUT_PHY_X1Y4; +INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out" LOC=PHASER_OUT_PHY_X1Y11; +INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out" LOC=PHASER_OUT_PHY_X1Y10; +INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out" LOC=PHASER_OUT_PHY_X1Y9; +INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out" LOC=PHASER_OUT_PHY_X1Y8; + +INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y3; +INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y2; +INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y1; +INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y0; +## INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y6; +## INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y5; +## INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y4; +INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y11; +INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y10; +INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y9; +INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y8; + + + +INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo" LOC=OUT_FIFO_X1Y3; +INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo" LOC=OUT_FIFO_X1Y2; +INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo" LOC=OUT_FIFO_X1Y1; +INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo" LOC=OUT_FIFO_X1Y0; +INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo" LOC=OUT_FIFO_X1Y6; +INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo" LOC=OUT_FIFO_X1Y5; +INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo" LOC=OUT_FIFO_X1Y4; +INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo" LOC=OUT_FIFO_X1Y11; +INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo" LOC=OUT_FIFO_X1Y10; +INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo" LOC=OUT_FIFO_X1Y9; +INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo" LOC=OUT_FIFO_X1Y8; + +INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo" LOC=IN_FIFO_X1Y3; +INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo" LOC=IN_FIFO_X1Y2; +INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/in_fifo_gen.in_fifo" LOC=IN_FIFO_X1Y1; +INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/in_fifo_gen.in_fifo" LOC=IN_FIFO_X1Y0; +INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo" LOC=IN_FIFO_X1Y11; +INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo" LOC=IN_FIFO_X1Y10; +INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/in_fifo_gen.in_fifo" LOC=IN_FIFO_X1Y9; +INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/in_fifo_gen.in_fifo" LOC=IN_FIFO_X1Y8; + +INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/phy_control_i" LOC=PHY_CONTROL_X1Y0; +INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/phy_control_i" LOC=PHY_CONTROL_X1Y1; +INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i" LOC=PHY_CONTROL_X1Y2; + +INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/phaser_ref_i" LOC=PHASER_REF_X1Y0; +INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/phaser_ref_i" LOC=PHASER_REF_X1Y1; +INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phaser_ref_i" LOC=PHASER_REF_X1Y2; + + +INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/*slave_ts" LOC=OLOGIC_X1Y43; +INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/*slave_ts" LOC=OLOGIC_X1Y31; +INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/*slave_ts" LOC=OLOGIC_X1Y19; +INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/*slave_ts" LOC=OLOGIC_X1Y7; +INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/*slave_ts" LOC=OLOGIC_X1Y143; +INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/*slave_ts" LOC=OLOGIC_X1Y131; +INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/*slave_ts" LOC=OLOGIC_X1Y119; +INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/*slave_ts" LOC=OLOGIC_X1Y107; + +INST "*/u_ddr3_infrastructure/plle2_i" LOC=PLLE2_ADV_X1Y1; +INST "*/u_ddr3_infrastructure/mmcm_i" LOC=MMCME2_ADV_X1Y1; + +############################################################################### +# Timing Constraints +############################################################################### + +NET "*/sys_clk_c" TNM_NET = "SYSCLK"; +NET "*/pcie_core_i/gt_top.gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/clk_125mhz" TNM_NET = "CLK_125"; +NET "*/pcie_core_i/gt_top.gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/clk_250mhz" TNM_NET = "CLK_250"; +NET "*/pcie_core_i/gt_top.gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/userclk1" TNM_NET = "CLK_USERCLK"; +NET "*/pcie_core_i/gt_top.gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/userclk2" TNM_NET = "CLK_USERCLK2"; + +TIMESPEC TS_SYSCLK = PERIOD "SYSCLK" 100 MHz HIGH 50 %; +TIMESPEC TS_CLK_125 = PERIOD "CLK_125" TS_SYSCLK * 1.25 HIGH 50 % PRIORITY 1; +#TIMESPEC TS_CLK_250 = PERIOD "CLK_250" TS_SYSCLK * 2.5 HIGH 50 % PRIORITY 2; +TIMESPEC TS_CLK_USERCLK = PERIOD "CLK_USERCLK" TS_SYSCLK / 1.6 HIGH 50 %; +TIMESPEC TS_CLK_USERCLK2 = PERIOD "CLK_USERCLK2" TS_SYSCLK / 1.6 HIGH 50 %; + +INST "*/pcie_core_i/gt_top.gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/mmcm_i" LOC = MMCME2_ADV_X0Y2; + +PIN "*/pcie_core_i/pcie_top_i/pcie_7x_i/pcie_block_i.PLPHYLNKUPN" TIG; +PIN "*/pcie_core_i/pcie_top_i/pcie_7x_i/pcie_block_i.PLRECEIVEDHOTRST" TIG; + +PIN "*/pcie_core_i/gt_top.gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/mmcm_i.RST" TIG; +NET "*/pcie_core_i/gt_top.gt_top_i/pipe_wrapper_i/user_resetdone*" TIG; +NET "*/pcie_core_i/gt_top.gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/pclk_sel" TIG; +NET "*/pcie_core_i/gt_top.gt_top_i/pipe_wrapper_i/pipe_lane[0].pipe_rate.pipe_rate_i/*" TNM_NET = FFS "MC_PIPE"; +NET "*/pcie_core_i/gt_top.gt_top_i/pipe_wrapper_i/pipe_lane[1].pipe_rate.pipe_rate_i/*" TNM_NET = FFS "MC_PIPE"; +NET "*/pcie_core_i/gt_top.gt_top_i/pipe_wrapper_i/pipe_lane[2].pipe_rate.pipe_rate_i/*" TNM_NET = FFS "MC_PIPE"; +NET "*/pcie_core_i/gt_top.gt_top_i/pipe_wrapper_i/pipe_lane[3].pipe_rate.pipe_rate_i/*" TNM_NET = FFS "MC_PIPE"; + +TIMESPEC TS_PIPE_RATE = FROM "MC_PIPE" TS_CLK_USERCLK * 0.5; + +NET "*/pcie_core_i/gt_top.gt_top_i/pipe_wrapper_i/pipe_reset.pipe_reset_i/cpllreset" TIG; + +####### DDR ########### +NET "ddr_sys_clk_p" TNM_NET = TNM_ddr_sys_clk; +TIMESPEC "TS_ddr_sys_clk" = PERIOD "TNM_ddr_sys_clk" 5 ns; + +#NET "clk_ref_i" TNM_NET = TNM_clk_ref; +#TIMESPEC "TS_clk_ref" = PERIOD "TNM_clk_ref" 5 ns ; +# +NET "*/iserdes_clk" TNM_NET = "TNM_ISERDES_CLK"; +INST "*/mc0/mc_read_idle_r" TNM = "TNM_SOURCE_IDLE"; +INST "*/input_[?].iserdes_dq_.iserdesdq" TNM = "TNM_DEST_ISERDES"; +TIMESPEC "TS_ISERDES_CLOCK" = PERIOD "TNM_ISERDES_CLK" 2500 ps; +TIMESPEC TS_MULTICYCLEPATH = FROM "TNM_SOURCE_IDLE" TO "TNM_DEST_ISERDES" TS_ISERDES_CLOCK*6; + +INST "*/device_temp_sync_r1*" TNM="TNM_MULTICYCLEPATH_DEVICE_TEMP_SYNC"; +TIMESPEC "TS_MULTICYCLEPATH_DEVICE_TEMP_SYNC" = TO "TNM_MULTICYCLEPATH_DEVICE_TEMP_SYNC" 20 ns DATAPATHONLY; + +############################################################################### +# Physical Constraints +############################################################################### +######################################################################################################################### +# End PCIe Core Constraints +######################################################################################################################### + +# PlanAhead Generated physical constraints Index: fade_ether_protocol/trunk/experimental_fade_10g/fpga/eth_receiver64.vhd =================================================================== --- fade_ether_protocol/trunk/experimental_fade_10g/fpga/eth_receiver64.vhd (nonexistent) +++ fade_ether_protocol/trunk/experimental_fade_10g/fpga/eth_receiver64.vhd (revision 12) @@ -0,0 +1,439 @@ +------------------------------------------------------------------------------- +-- Title : FPGA Ethernet interface - block receiving packets from MII PHY +-- Project : +------------------------------------------------------------------------------- +-- File : eth_receiver4.vhd +-- Author : Wojciech M. Zabolotny (wzab@ise.pw.edu.pl) +-- License : BSD License +-- Company : +-- Created : 2012-03-30 +-- Last update: 2014-04-20 +-- Platform : +-- Standard : VHDL'93 +------------------------------------------------------------------------------- +-- Description: This file implements the state machine, which manages the +-- table of packet descriptors, used to resend only not confirmed packets +------------------------------------------------------------------------------- +-- Copyright (c) 2012 +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2012-03-30 1.0 WZab Created +------------------------------------------------------------------------------- + +-- Uwaga! Tu mamy rzeczywiste problemy z obsluga odebranych pakietow! +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library work; +use work.pkt_ack_pkg.all; +use work.PCK_CRC32_D64.all; +use work.PCK_CRC32_D32.all; +use work.PCK_CRC32_D16.all; +use work.PCK_CRC32_D8.all; + +entity eth_receiver is + + port ( + -- Configuration + peer_mac : out std_logic_vector(47 downto 0); + my_mac : in std_logic_vector(47 downto 0); + my_ether_type : in std_logic_vector(15 downto 0); + transmit_data : out std_logic; + restart : out std_logic; + -- ACK FIFO interface + ack_fifo_full : in std_logic; + ack_fifo_wr_en : out std_logic; + ack_fifo_din : out std_logic_vector(pkt_ack_width-1 downto 0); + -- System interface + clk : in std_logic; + rst_n : in std_logic; + dbg : out std_logic_vector(3 downto 0); + cmd : out std_logic_vector(31 downto 0); + arg : out std_logic_vector(31 downto 0); + crc : out std_logic_vector(31 downto 0); + -- MAC interface + Rx_Clk : in std_logic; + RxC : in std_logic_vector(7 downto 0); + RxD : in std_logic_vector(63 downto 0) + ); + +end eth_receiver; + + +architecture beh1 of eth_receiver is + + type T_STATE is (ST_RCV_IDLE, ST_RCV_PREAMB, ST_CHECK_PREAMB, + ST_RCV_HEADER1, ST_RCV_HEADER2, ST_RCV_CMD, + ST_RCV_WAIT_IDLE, ST_RCV_ARGS, ST_RCV_PROCESS, ST_RCV_UPDATE, + ST_RCV_TRAILER); + + + + function rev(a : in std_logic_vector) + return std_logic_vector is + variable result : std_logic_vector(a'range); + alias aa : std_logic_vector(a'reverse_range) is a; + begin + for i in aa'range loop + result(i) := aa(i); + end loop; + return result; + end; -- function reverse_any_bus + + -- The function below changes the order of bytes and order of bits in the + -- bytes so that the CRC32 is correctly updated... + -- We assume, that argument of this function are the data delivered + -- to the TxD, so they are transmitted starting from the least significant + -- byte + function crc_8bytes ( + constant vec : std_logic_vector(63 downto 0); + constant old_crc : std_logic_vector(31 downto 0)) + return std_logic_vector is + variable new_crc : std_logic_vector(31 downto 0); + variable reordered_data : std_logic_vector(63 downto 0); + begin -- function crc_8bytes + -- for bn in 0 to 7 loop + -- for i in 0 to 7 loop + -- reordered_data(bn*8+i) := vec(bn*8+7-i); + -- end loop; + --end loop; + new_crc := nextCRC32_D64(rev(vec), old_crc); + return new_crc; + end function crc_8bytes; + + + type T_RCV_REGS is record + state : T_STATE; + swap_lanes : std_logic; + transmit_data : std_logic; + restart : std_logic; + update_flag : std_logic; + count : integer; + dbg : std_logic_vector(3 downto 0); + crc32 : std_logic_vector(31 downto 0); + cmd : std_logic_vector(31 downto 0); + arg : std_logic_vector(31 downto 0); + mac_addr : std_logic_vector(47 downto 0); + peer_mac : std_logic_vector(47 downto 0); + end record; + + constant RCV_REGS_INI : T_RCV_REGS := ( + state => ST_RCV_IDLE, + swap_lanes => '0', + transmit_data => '0', + restart => '0', + update_flag => '0', + count => 0, + dbg => (others => '0'), + crc32 => (others => '0'), + cmd => (others => '0'), + arg => (others => '0'), + mac_addr => (others => '0'), + peer_mac => (others => '0') + ); + + signal r, r_n : T_RCV_REGS := RCV_REGS_INI; + + type T_RCV_COMB is record + ack_fifo_wr_en : std_logic; + Rx_mac_rd : std_logic; + ack_fifo_din : std_logic_vector(pkt_ack_width-1 downto 0); + restart : std_logic; + end record; + + constant RCV_COMB_DEFAULT : T_RCV_COMB := ( + ack_fifo_wr_en => '0', + Rx_mac_rd => '0', + ack_fifo_din => (others => '0'), + restart => '0' + ); + + signal c : T_RCV_COMB := RCV_COMB_DEFAULT; + + signal rxd_sw, rxd_del : std_logic_vector(63 downto 0); + signal rxc_sw, rxc_del : std_logic_vector(7 downto 0); + + signal rx_rst_n, rx_rst_n_0, rx_rst_n_1 : std_logic := '0'; + signal update_flag_0, update_flag_1, update_flag : std_logic := '0'; + +begin -- beh1 + + ack_fifo_din <= c.ack_fifo_din; + ack_fifo_wr_en <= c.ack_fifo_wr_en; + + --dbg <= r.dbg; + crc <= r.crc32; + cmd <= r.cmd; + arg <= r.arg; + -- Lane switcher processes + lsw_c1 : process (RxC, RxC(3 downto 0), RxC_del(7 downto 4), RxD, + RxD(31 downto 0), RxD_del(63 downto 32), r.swap_lanes) is + begin -- process lsw_c1 + if r.swap_lanes = '1' then + RxD_Sw(63 downto 32) <= RxD(31 downto 0); + RxD_Sw(31 downto 0) <= RxD_del(63 downto 32); + RxC_Sw(7 downto 4) <= RxC(3 downto 0); + RxC_Sw(3 downto 0) <= RxC_del(7 downto 4); + else + RxD_Sw <= RxD; + RxC_Sw <= RxC; + end if; + end process lsw_c1; + + process (Rx_Clk, rx_rst_n) is + begin -- process + if rx_rst_n = '0' then -- asynchronous reset (active low) + RxD_del <= (others => '0'); + RxC_del <= (others => '0'); + elsif Rx_Clk'event and Rx_Clk = '1' then -- rising clock edge + RxD_del <= RxD; + RxC_del <= RxC; + end if; + end process; + + -- Reading of ethernet data + rdp1 : process (Rx_Clk, rx_rst_n) + begin -- process rdp1 + if rx_rst_n = '0' then -- asynchronous reset (active low) + r <= RCV_REGS_INI; + elsif Rx_Clk'event and Rx_Clk = '1' then -- rising clock edge + r <= r_n; + end if; + end process rdp1; + + rdp2 : process (RxC, RxC_Sw, RxD, RxD_Sw, ack_fifo_full, my_ether_type, + my_mac, r, r.arg(15 downto 10), r.arg(31 downto 16), + r.cmd(15 downto 0), r.cmd(31 downto 16), r.crc32, r.dbg(0), + r.dbg(1), r.dbg(2), r.dbg(3), r.mac_addr, r.state, + r.update_flag) + + variable ack_pkt_in : pkt_ack; + variable v_mac_addr : std_logic_vector(47 downto 0); + variable v_cmd, v_arg : std_logic_vector(31 downto 0); + variable v_crc : std_logic_vector(31 downto 0); + + begin -- process + c <= RCV_COMB_DEFAULT; + r_n <= r; + dbg <= "1111"; + case r.state is + when ST_RCV_IDLE => + dbg <= "0000"; + -- We must be prepared to one of two possible events + -- Either we receive the SOF in the 0-th lane (and then we proceed + -- normally) or we receive the SOF in the 4-th lane (and then we have + -- to switch lanes, delaying 4 of them). + if RxC = b"00011111" and RxD = x"55_55_55_fb_07_07_07_07" then + -- shifted lanes + -- switch on the "lane shifter" and go to the state, + -- where we can check the proper preamble after lane switching + r_n.swap_lanes <= '1'; + r_n.state <= ST_CHECK_PREAMB; + elsif RxC = b"00000001" and RxD = x"d5_55_55_55_55_55_55_fb" then + -- normal lanes + r_n.swap_lanes <= '0'; + r_n.crc32 <= (others => '1'); + r_n.state <= ST_RCV_HEADER1; + end if; + when ST_CHECK_PREAMB => + dbg <= "0001"; + if RxC_Sw = b"00000001" and RxD_Sw = x"d5_55_55_55_55_55_55_fb" then + r_n.crc32 <= (others => '1'); + r_n.state <= ST_RCV_HEADER1; + else + -- interrupted preamble reception + r_n.state <= ST_RCV_IDLE; + end if; + when ST_RCV_HEADER1 => + dbg <= "0010"; + if RxC_Sw = b"00000000" then + r_n.crc32 <= crc_8bytes(RxD_Sw, r.crc32); + -- Change the order of bytes! + for i in 0 to 5 loop + v_mac_addr(47-i*8 downto 40-i*8) := RxD_Sw(i*8+7 downto i*8); + end loop; -- i + if v_mac_addr /= my_mac then + -- This packet is not for us - ignore it! + r_n.state <= ST_RCV_WAIT_IDLE; + else + -- Our packet! + r_n.count <= 0; + -- Read the lower 16 bits of the sender address + -- Again, we have to change the order of bytes! + r_n.mac_addr(39 downto 32) <= RxD_Sw(63 downto 56); + r_n.mac_addr(47 downto 40) <= RxD_Sw(55 downto 48); + r_n.state <= ST_RCV_HEADER2; + end if; + else + -- packet broken? + r_n.state <= ST_RCV_IDLE; + end if; + when ST_RCV_HEADER2 => + dbg <= "0010"; + if RxC_Sw = b"00000000" then + r_n.crc32 <= crc_8bytes(RxD_Sw, r.crc32); + v_mac_addr := r.mac_addr; + for i in 0 to 3 loop + v_mac_addr(31-i*8 downto 24-i*8) := RxD_Sw(i*8+7 downto i*8); + end loop; -- i + --v_mac_addr(47 downto 16) := RxD_Sw(31 downto 0); + r_n.mac_addr <= v_mac_addr; + for i in 0 to 3 loop + r_n.cmd(i*8+7 downto i*8) <= RxD_Sw(63-i*8 downto 56-i*8); + end loop; -- i + --r_n.cmd <= rev(RxD_Sw(63 downto 32)); + r_n.state <= ST_RCV_ARGS; + else + -- packet broken? + r_n.state <= ST_RCV_IDLE; + end if; + when ST_RCV_ARGS => + if RxC_Sw = b"0000_0000" then + r_n.crc32 <= crc_8bytes(RxD_Sw, r.crc32); + -- Copy the argument, changing order of bytes! + for i in 0 to 3 loop + r_n.arg(i*8+7 downto i*8) <= RxD_Sw(31-i*8 downto 24-i*8); + end loop; -- i + --r_n.cmd <= rev(RxD_Sw(31 downto 0)); + r_n.state <= ST_RCV_TRAILER; + else + -- packet broken? + r_n.state <= ST_RCV_IDLE; + end if; + when ST_RCV_TRAILER => + -- No detection of too long frames! + dbg <= "0110"; + if RxC_Sw /= b"0000_0000" then + -- It should be a packet with the checksum + -- The EOF may be on any of 8th positions. + -- To avoid too big combinational functions, + -- we handle it in a few states (but this increases requirements + -- on IFC!) + -- Current implementation assumes fixed length of frames + -- but the optimal one should probably pass received data for further + -- checking, why this machine continues to receive next frame... + if RxC_Sw = b"1111_1100" then + v_crc := r.crc32; + v_crc := nextCRC32_D16(rev(RxD_Sw(15 downto 0)), v_crc); + r_n.crc32 <= v_crc; + if ( RxD_Sw(23 downto 16)=x"fd" ) and + ( v_crc = x"c704dd7b" ) then + -- Correct packet, go to processing + r_n.peer_mac <= r.mac_addr; + r_n.state <= ST_RCV_PROCESS; + else + -- Wrong CRC or EOF + r_n.state <= ST_RCV_IDLE; + end if; + else + -- Wrong packet + r_n.state <= ST_RCV_IDLE; + end if; + else + -- Ignore received data, only updating the checksum + r_n.crc32 <= crc_8bytes(RxD_Sw, r.crc32); + end if; + when ST_RCV_PROCESS => + dbg <= "0111"; + if r.cmd(31 downto 16) /= my_ether_type then + r_n.state <= ST_RCV_WAIT_IDLE; + else + case r.cmd(15 downto 0) is + when x"0001" => + r_n.dbg(0) <= not r.dbg(0); + -- Start transmission command + r_n.transmit_data <= '1'; + r_n.state <= ST_RCV_UPDATE; + when x"0002" => + r_n.dbg(1) <= not r.dbg(1); + -- Stop transmission command + r_n.transmit_data <= '0'; + r_n.state <= ST_RCV_UPDATE; + when x"0003" => + r_n.dbg(2) <= not r.dbg(2); + -- Packet ACK command + if ack_fifo_full = '0' then + ack_pkt_in.cmd := to_unsigned(3, ack_pkt_in.cmd'length); + ack_pkt_in.set := unsigned(r.arg(31 downto 16)); + ack_pkt_in.pkt := "00" & unsigned(r.arg(15 downto 10)); + c.ack_fifo_din <= pkt_ack_to_stlv(ack_pkt_in); + c.ack_fifo_wr_en <= '1'; + end if; + + r_n.state <= ST_RCV_UPDATE; + when x"0004" => + -- Packet NACK command (currently not used) + if ack_fifo_full = '0' then + ack_pkt_in.cmd := to_unsigned(4, ack_pkt_in.cmd'length); + ack_pkt_in.set := unsigned(r.arg(31 downto 16)); + ack_pkt_in.pkt := "00" & unsigned(r.arg(15 downto 10)); + c.ack_fifo_din <= pkt_ack_to_stlv(ack_pkt_in); + c.ack_fifo_wr_en <= '1'; + end if; + r_n.state <= ST_RCV_UPDATE; + when x"0005" => + r_n.dbg(3) <= not r.dbg(3); + + -- Stop transmission and retransmission + r_n.restart <= '1'; + r_n.state <= ST_RCV_UPDATE; + when others => + r_n.state <= ST_RCV_IDLE; + end case; + end if; + when ST_RCV_UPDATE => + dbg <= "1000"; + r_n.update_flag <= not r.update_flag; + r_n.state <= ST_RCV_IDLE; + when ST_RCV_WAIT_IDLE => + dbg <= "1001"; + if RxC_Sw = b"1111_1111" then + r_n.state <= ST_RCV_IDLE; + end if; + when others => null; + end case; + end process rdp2; + + -- Synchronization of the reset signal for the Rx_Clk domain + process (Rx_Clk, rst_n) + begin -- process + if rst_n = '0' then -- asynchronous reset (active low) + rx_rst_n_0 <= '0'; + rx_rst_n_1 <= '0'; + rx_rst_n <= '0'; + elsif Rx_Clk'event and Rx_Clk = '1' then -- rising clock edge + rx_rst_n_0 <= rst_n; + rx_rst_n_1 <= rx_rst_n_0; + rx_rst_n <= rx_rst_n_1; + end if; + end process; + + + -- Synchronization of output signals between the clock domains + process (clk, rst_n) + begin -- process + if rst_n = '0' then -- asynchronous reset (active low) + peer_mac <= (others => '0'); + transmit_data <= '0'; + restart <= '0'; + update_flag_0 <= '0'; + update_flag_1 <= '0'; + update_flag <= '0'; + elsif clk'event and clk = '1' then -- rising clock edge + -- Synchronization of the update_flag + update_flag_0 <= r.update_flag; + update_flag_1 <= update_flag_0; + update_flag <= update_flag_1; + -- When update flag has changed, rewrite synchronized fields + if update_flag /= update_flag_1 then + peer_mac <= r.peer_mac; + transmit_data <= r.transmit_data; + restart <= r.restart; + end if; + end if; + end process; + +end beh1; Index: fade_ether_protocol/trunk/desc.txt =================================================================== --- fade_ether_protocol/trunk/desc.txt (revision 11) +++ fade_ether_protocol/trunk/desc.txt (revision 12) @@ -140,3 +140,13 @@ provide information about my project (especially if you cite my article, after it is ready and published) +EXPERIMENTAL 10Gb/s IMPLEMENTATION +In the directory experimental_fade_10g you can find experimental +version of my protocol, working with the 10Gb/s link on the +KC705 board. +The design has been initially tested, and is working, but it still +needs some improvments. +Please note, that this version uses the "jumbo" frames, +with 8192 bytes of user data in each packet (plus header). +Therefore it was necessary to make some changes in the kernel +driver.

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