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Rev 11 → Rev 12

/i650/trunk/rtl/operator_ctl.v
56,7 → 56,7
);
//-----------------------------------------------------------------------------
// Operator console switch settings
// Operator console switch settings and their control signals.
//-----------------------------------------------------------------------------
reg pgm_sw_stop, pgm_sw_run,
half_cycle_sw_run, half_cycle_sw_half,
72,10 → 72,9
assign ro_storage = disp_sw_ro;
assign storage_control = run_control | disp_sw_ro;
reg do_power_on_reset, do_reset_console, do_err_reset, do_err_sense_reset,
do_pgm_reset, do_acc_reset, do_hard_reset, do_clear_drum;
reg [0:5] state;
//-----------------------------------------------------------------------------
// Calculate the RAM address of the general storage word at address gs_addr_.
//-----------------------------------------------------------------------------
reg [0:6] gs_addr_th, gs_addr_h, gs_addr_t, gs_addr_u;
wire [0:14] gs_band_addr;
wire [0:9] gs_word_offset;
83,6 → 82,13
ram_word_offset rwo(gs_addr_t, gs_addr_u, gs_word_offset);
wire [0:14] gs_word_addr = gs_band_addr + gs_word_offset;
 
//-----------------------------------------------------------------------------
// Operator console state machine
//-----------------------------------------------------------------------------
reg do_power_on_reset, do_reset_console, do_err_reset, do_err_sense_reset,
do_pgm_reset, do_acc_reset, do_hard_reset, do_clear_drum;
reg [0:5] state;
`define state_idle 6'd0
`define state_reset_console_1 6'd1
114,14 → 120,12
`define state_read_gs_3 6'd32
`define state_read_gs_4 6'd33
`define state_read_gs_5 6'd34
`define state_read_gs_6 6'd35
`define state_clear_drum_1 6'd50
`define state_clear_drum_2 6'd51
`define state_clear_drum_3 6'd52
//-----------------------------------------------------------------------------
// Operator console state machine
//-----------------------------------------------------------------------------
always @(posedge clk) begin
if (rst) begin
console_to_addr <= 0;
632,8 → 636,8
// --> 4 digits address, little-endian
// <-- 1 digit sign, 10 digits, little-endian
// 0 : Ignore if CPU not stopped
// Accept low-order address digit
// 1 : Accept remaining address digits
// 1 : Accept first address digit
// 2 : Accept remaining address digits
// 2 : Calculate word origin in gs RAM
// Validate address
// console_read_gs <= 1;
659,14 → 663,32
end
`state_read_gs_3: begin
gs_ram_addr <= gs_word_addr;
state <= `state_read_gs_4;
if (d10) begin
gs_ram_addr <= gs_word_addr;
read_gs <= 1;
state <= `state_read_gs_4;
end
end
`state_read_gs_4: begin
cmd_digit_out <= gs_in;
state <= `state_read_gs_5;
gs_ram_addr <= gs_ram_addr + 1;
end
`state_read_gs_5: begin
digit_ready <= 1;
cmd_digit_out <= gs_in;
gs_ram_addr <= gs_ram_addr + 1;
if (dx) begin
state <= `state_read_gs_6;
read_gs <= 0;
end
end
`state_read_gs_6: begin
digit_ready <= 0;
state <= `state_idle;
end
// 0 : Ignore if not in manual
// Clear gs_ram_addr
/i650/trunk/rtl/gen_store.v
48,18 → 48,27
reg [0:4] gs_mem [0:32767]; // Rounded size up from 24000 to next 2^n.
//-----------------------------------------------------------------------------
//
// Calculate the early (next digit) and on-time RAM addresses. Console read
// and write are implementation extensions.
//-----------------------------------------------------------------------------
wire [0:14] band_addr, gs_addr, gs_addr_early;
ram_band_addr rba(addr_th, addr_h, addr_t, band_addr);
wire console_acc = console_read_gs | console_write_gs;
assign gs_addr = console_acc? console_ram_addr : (band_addr + dynamic_addr);
assign gs_addr_early = console_acc? console_ram_addr
: (band_addr + ((dynamic_addr + 1) % 600)) % 32768;
// The % operator fixes a spurious warning from XST synthesis due to use of a
// 32-bit mux for ? operator. Uses no gates.
assign gs_addr_early = (console_acc? console_ram_addr
: (band_addr + ((dynamic_addr + 1) % 600))) % 32768;
//-----------------------------------------------------------------------------
// These 650 write errors are not possible for this implementation.
//-----------------------------------------------------------------------------
assign double_write = 0;
assign no_write = 0;
//-----------------------------------------------------------------------------
// A : Read from RAM at on-time address.
//-----------------------------------------------------------------------------
always @(posedge ap) begin
if (rst) begin
gs_out <= `biq_blank;
68,6 → 77,9
end
end;
//-----------------------------------------------------------------------------
// D : Write to RAM at early address.
//-----------------------------------------------------------------------------
always @(posedge dp) begin
if (write_gate)
gs_mem[gs_addr_early] <= gs_in;
/i650/trunk/rtl/toplev.v
0,0 → 1,223
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// IBM 650 Reconstruction in Verilog (i650)
//
// This file is part of the IBM 650 Reconstruction in Verilog (i650) project
// http:////www.opencores.org/project,i650
//
// Description: Top level.
//
// Additional Comments: See US 2959351, Fig. 53, 54 and 55. Additional index
// counters provided to address general storage and register RAMs.
//
// Copyright (c) 2015 Robert Abeles
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, download it
// from http://www.opencores.org/lgpl.shtml
//////////////////////////////////////////////////////////////////////////////////
`include "defines.v"
 
module toplev (
input clk,
input rst,
 
input [0:6] cmd_digit_in, io_buffer_in,
input [0:5] command,
 
output [0:6] cmd_digit_out,
output busy, digit_ready, punch_card, read_card, card_digit_ready,
output synch
);
wire ap, bp, cp, dp;
wire dx, d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10,
d1_d5, d5_dx, d5_d10, d1_dx, d5_d9, d10_d1_d5,
dxl, dxu, d0l, d0u, d1l, d1u, d2l, d10u;
wire w0, w1, w2, w3, w4, w5, w6, w7, w8, w9,
wl, wu, ewl;
wire s0, s1, s2, s3, s4, hp;
wire [0:9] digit_idx;
wire [0:3] early_idx, ontime_idx;
assign synch = bp;
timing tm (
.clk(clk),
.rst(rst),
.ap(ap),
.bp(bp),
.cp(cp),
.dp(dp),
.dx(dx),
.d0(d0),
.d1(d1),
.d2(d2),
.d3(d3),
.d4(d4),
.d5(d5),
.d6(d6),
.d7(d7),
.d8(d8),
.d9(d9),
.d10(d10),
.d1_d5(d1_d5),
.d5_dx(d5_dx),
.d5_d10(d5_d10),
.d1_dx(d1_dx),
.d5_d9(d5_d9),
.d10_d1_d5(d10_d1_d5),
.dxl(dxl),
.dxu(dxu),
.d0l(d0l),
.d0u(d0u),
.d1l(d1l),
.d1u(d1u),
.d2l(d2l),
.d10u(d10u),
.w0(w0),
.w1(w1),
.w2(w2),
.w3(w3),
.w4(w4),
.w5(w5),
.w6(w6),
.w7(w7),
.w8(w8),
.w9(w9),
.wl(wl),
.wu(wu),
.ewl(ewl),
.s0(s0),
.s1(s1),
.s2(s2),
.s3(s3),
.s4(s4),
.hp(hp),
.digit_idx(digit_idx),
.early_idx(early_idx),
.ontime_idx(ontime_idx)
);
//-----------------------------------------------------------------------------
// General storage
//-----------------------------------------------------------------------------
wire [0:4] gs_out;
wire gs_double_write, gs_no_write;
//-----------------------------------------------------------------------------
// Operator controls
//-----------------------------------------------------------------------------
wire [0:6] oc_data_out, oc_addr_out, oc_console_out;
wire oc_console_to_addr;
wire [0:14] oc_gs_ram_addr;
wire oc_read_gs, oc_write_gs;
wire oc_pgm_start, oc_pgm_stop, oc_err_reset, oc_err_sense_reset;
wire oc_run_control, oc_half_or_pgm_stop, oc_ri_storage, oc_ro_storage,
oc_storage_control;
wire oc_man_pgm_reset, oc_man_acc_reset, oc_set_8000, oc_reset_8000,
oc_hard_reset;
//-----------------------------------------------------------------------------
// Translators
//-----------------------------------------------------------------------------
wire tr_gs_write;
wire [0:4] tr_gs_in;
wire [0:6] tr_select_out;
 
gen_store gs (
.rst(oc_hard_reset),
.ap(ap),
.dp(dp),
.write_gate(tr_gs_write),
.addr_th(`biq_blank),
.addr_h(`biq_blank),
.addr_t(`biq_blank),
.dynamic_addr(digit_idx),
.gs_in(tr_gs_in),
.console_ram_addr(oc_gs_ram_addr),
.console_read_gs(oc_read_gs),
.console_write_gs(oc_write_gs),
.gs_out(gs_out),
.double_write(gs_double_write),
.no_write(gs_no_write)
);
 
operator_ctl oc (
.rst(rst),
.clk(clk),
.ap(ap),
.dp(dp),
.dx(dx),
.d0(d0),
.d1(d1),
.d2(d2),
.d3(d3),
.d4(d4),
.d5(d5),
.d6(d6),
.d10(d10),
.wu(wu),
.hp(hp),
.early_idx(early_idx),
.ontime_idx(ontime_idx),
.cmd_digit_in(cmd_digit_in),
.io_buffer_in(io_buffer_in),
.gs_in(tr_select_out),
.command(command),
.data_out(oc_data_out),
.addr_out(oc_addr_out),
.console_out(oc_console_out),
.console_to_addr(oc_console_to_addr),
.gs_ram_addr(oc_gs_ram_addr),
.read_gs(oc_read_gs),
.write_gs(oc_write_gs),
.pgm_start(oc_pgm_start),
.pgm_stop(oc_pgm_stop),
.err_reset(oc_err_reset),
.err_sense_reset(oc_err_sense_reset),
.run_control(oc_run_control),
.half_or_pgm_stop(oc_half_or_pgm_stop),
.ri_storage(oc_ri_storage),
.ro_storage(oc_ro_storage),
.storage_control(oc_storage_control),
.man_pgm_reset(oc_man_pgm_reset),
.man_acc_reset(oc_man_acc_reset),
.set_8000(oc_set_8000),
.reset_8000(oc_reset_8000),
.hard_reset(oc_hard_reset),
.cmd_digit_out(cmd_digit_out),
.busy(busy),
.digit_ready(digit_ready),
.punch_card(punch_card),
.read_card(read_card),
.card_digit_ready(card_digit_ready)
);
 
translators tr (
.dist_early_out(`biq_blank),
.bs_out(`biq_blank),
.console_out(oc_console_out),
.ri_gs(1'b0),
.ri_bs(1'b0),
.ri_console(oc_write_gs),
.n800x(1'b1),
.gs_out(gs_out),
.gs_write(tr_gs_write),
.gs_in(tr_gs_in),
.select_out(tr_select_out)
);
 
endmodule

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