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URL https://opencores.org/ocsvn/lcd_block/lcd_block/trunk

Subversion Repositories lcd_block

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    from Rev 11 to Rev 12
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Rev 11 → Rev 12

/lcd_block/trunk/hdl/iseProject/_xmsgs/pn_parser.xmsgs
8,8 → 8,5
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
 
<messages>
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;E:/lcd_block/hdl/iseProject/top_hw_testbench.v&quot; into library work</arg>
</msg>
 
</messages>
 
/lcd_block/trunk/hdl/iseProject/pins_hw_testbench.ucf
1,12 → 1,14
# Pins used by Spartan3E starter Kit
#NET "lcd_e" LOC = "M18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
#NET "lcd_rs" LOC = "L18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
#NET "lcd_rw" LOC = "L17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
#NET "hw_lcd_e" LOC = "M18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
#NET "hw_lcd_rs" LOC = "L18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
#NET "hw_lcd_rw" LOC = "L17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
# The LCD four-bit data interface is shared with the StrataFlash.
#NET "lcd_nibble<0>" LOC = "R15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
#NET "lcd_nibble<1>" LOC = "R16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
#NET "lcd_nibble<2>" LOC = "P17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
#NET "lcd_nibble<3>" LOC = "M15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
#NET "hw_lcd_nibble<0>" LOC = "R15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
#NET "hw_lcd_nibble<1>" LOC = "R16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
#NET "hw_lcd_nibble<2>" LOC = "P17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
#NET "hw_lcd_nibble<3>" LOC = "M15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
 
#NET "hw_strata_flash_disable" LOC = "D16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
 
#NET "rst" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP ;
NET "clk" LOC = "C9" | IOSTANDARD = LVCMOS33 ;
NET "clk" LOC = "C9" | IOSTANDARD = LVCMOS33 ;
/lcd_block/trunk/hdl/iseProject/top_hw_testbench.v
3,7 → 3,12
Top module that will instantiate and connect our DUT (lcd_controller) the ICON, VIO , ILA cores
*/
module top_hw_testbench(
input clk
input clk/*,
output hw_lcd_e,
output hw_lcd_rs,
output hw_lcd_rw,
output [3:0] hw_lcd_nibble,
output hw_strata_flash_disable*/
);
// Declare some wires to connect the components
60,5 → 65,12
assign trig_0 = lcd_e;
assign {rst, rs_in, data_in, strobe_in, period_clk_ns} = async_out;
assign data = {7'd1,lcd_e, lcd_nibble[3:0], lcd_rs, lcd_rw, disable_flash, done, strobe_in};
// Send all interest output to outside
/*assign hw_lcd_e = lcd_e;
assign hw_lcd_rs = lcd_rs;
assign hw_lcd_rw = lcd_rw;
assign hw_lcd_nibble = lcd_nibble;
assign hw_strata_flash_disable = disable_flash;*/
 
endmodule
/lcd_block/trunk/hdl/iseProject/top_hw_testbench.cpj
1,5 → 1,5
#ChipScope Pro Analyzer Project File, Version 3.0
#Wed May 23 02:07:27 CEST 2012
#Wed May 23 02:46:29 CEST 2012
device.0.configFileDir=E\:\\lcd_block\\hdl\\iseProject
device.0.configFilename=top_hw_testbench.bit
device.0.inserterCDCFileDir=E\:\\lcd_block\\hdl\\iseProject
20,17 → 20,18
mdiDevice0=0
mdiDevice1=0
mdiDevice2=0
mdiType0=1
mdiType1=0
mdiType2=6
mdiUnit0=0
mdiType0=6
mdiType1=1
mdiType2=0
mdiUnit0=1
mdiUnit1=0
mdiUnit2=1
mdiUnit2=0
navigatorHeight=0.17708333333333334
navigatorHeightLast=0.17939814814814814
navigatorWidth=0.1794871794871795
navigatorWidthLast=0.1794871794871795
signalDisplayPath=0
unit.-1.-1.username=
unit.0.0.0.HEIGHT0=0.36263737
unit.0.0.0.TriggerRow0=1
unit.0.0.0.TriggerRow1=1
277,7 → 278,7
unit.0.1.port.1.b.0.display=0
unit.0.1.port.1.b.0.name=AsyncOut_1
unit.0.1.port.1.b.0.orderindex=-1
unit.0.1.port.1.b.0.radix=Ascii
unit.0.1.port.1.b.0.radix=Hex
unit.0.1.port.1.b.0.signedOffset=0.0
unit.0.1.port.1.b.0.signedPrecision=0
unit.0.1.port.1.b.0.signedScaleFactor=1.0
285,7 → 286,7
unit.0.1.port.1.b.0.unsignedOffset=0.0
unit.0.1.port.1.b.0.unsignedPrecision=0
unit.0.1.port.1.b.0.unsignedScaleFactor=1.0
unit.0.1.port.1.b.0.value=A
unit.0.1.port.1.b.0.value=41
unit.0.1.port.1.b.0.visible=1
unit.0.1.port.1.b.1.alias=period_clk_ns
unit.0.1.port.1.b.1.channellist=0 1 2 3 4 5 6 7
383,7 → 384,7
unit.0.1.port.1.s.17.name=AsyncOut[17]
unit.0.1.port.1.s.17.orderindex=-1
unit.0.1.port.1.s.17.persistence=0
unit.0.1.port.1.s.17.value=0
unit.0.1.port.1.s.17.value=1
unit.0.1.port.1.s.17.visible=1
unit.0.1.port.1.s.18.alias=rst
unit.0.1.port.1.s.18.color=java.awt.Color[r\=0,g\=0,b\=124]
510,7 → 511,7
unit.0.1.vio.posn.2.channel=2147483646
unit.0.1.vio.posn.2.name=data_in
unit.0.1.vio.posn.2.port=1
unit.0.1.vio.posn.2.radix=5
unit.0.1.vio.posn.2.radix=1
unit.0.1.vio.posn.2.type=bus
unit.0.1.vio.posn.3.channel=17
unit.0.1.vio.posn.3.name=rs_in
/lcd_block/trunk/hdl/iseProject/iseProject.gise
226,7 → 226,7
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1337731537" xil_pn:in_ck="4747555295481960126" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="-5172275256582554922" xil_pn:start_ts="1337731528">
<transform xil_pn:end_ts="1337733755" xil_pn:in_ck="4747555295481960126" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="-5172275256582554922" xil_pn:start_ts="1337733747">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
246,11 → 246,11
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1337728164" xil_pn:in_ck="-296097539435913693" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="4191577380043050738" xil_pn:start_ts="1337728164">
<transform xil_pn:end_ts="1337733755" xil_pn:in_ck="-296097539435913693" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="4191577380043050738" xil_pn:start_ts="1337733755">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1337731541" xil_pn:in_ck="-5772489953451663748" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-7079812952058613934" xil_pn:start_ts="1337731537">
<transform xil_pn:end_ts="1337733760" xil_pn:in_ck="-5772489953451663748" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-7079812952058613934" xil_pn:start_ts="1337733755">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
260,7 → 260,7
<outfile xil_pn:name="top_hw_testbench.ngd"/>
<outfile xil_pn:name="top_hw_testbench_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1337731545" xil_pn:in_ck="-7080687810229386214" xil_pn:name="TRANEXT_map_spartan3" xil_pn:prop_ck="-5849673150125579957" xil_pn:start_ts="1337731541">
<transform xil_pn:end_ts="1337733763" xil_pn:in_ck="-7080687810229386214" xil_pn:name="TRANEXT_map_spartan3" xil_pn:prop_ck="-5849673150125579957" xil_pn:start_ts="1337733760">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
276,7 → 276,7
<outfile xil_pn:name="top_hw_testbench_summary.xml"/>
<outfile xil_pn:name="top_hw_testbench_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1337731578" xil_pn:in_ck="6001200367856259123" xil_pn:name="TRANEXT_par_spartan3" xil_pn:prop_ck="-5563652517805085498" xil_pn:start_ts="1337731545">
<transform xil_pn:end_ts="1337733796" xil_pn:in_ck="6001200367856259123" xil_pn:name="TRANEXT_par_spartan3" xil_pn:prop_ck="-5563652517805085498" xil_pn:start_ts="1337733763">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
291,7 → 291,7
<outfile xil_pn:name="top_hw_testbench_pad.txt"/>
<outfile xil_pn:name="top_hw_testbench_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1337731607" xil_pn:in_ck="5725138416503842291" xil_pn:name="TRANEXT_bitFile_spartan3e" xil_pn:prop_ck="287829442711806529" xil_pn:start_ts="1337731578">
<transform xil_pn:end_ts="1337733836" xil_pn:in_ck="5725138416503842291" xil_pn:name="TRANEXT_bitFile_spartan3e" xil_pn:prop_ck="287829442711806529" xil_pn:start_ts="1337733805">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
304,15 → 304,15
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
<transform xil_pn:end_ts="1337731654" xil_pn:in_ck="5725138416503829437" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="5582947192412673156" xil_pn:start_ts="1337731653">
<transform xil_pn:end_ts="1337733856" xil_pn:in_ck="5725138416503829437" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="5582947192412673156" xil_pn:start_ts="1337733855">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1337731691" xil_pn:in_ck="5725138416503829437" xil_pn:name="TRAN_analyzeDesignUsingChipscope" xil_pn:prop_ck="-7079812952058613934" xil_pn:start_ts="1337731690">
<transform xil_pn:end_ts="1337733889" xil_pn:in_ck="5725138416503829437" xil_pn:name="TRAN_analyzeDesignUsingChipscope" xil_pn:prop_ck="-7079812952058613934" xil_pn:start_ts="1337733889">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1337731578" xil_pn:in_ck="-7080687810229386346" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416186" xil_pn:start_ts="1337731575">
<transform xil_pn:end_ts="1337733796" xil_pn:in_ck="-7080687810229386346" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416186" xil_pn:start_ts="1337733794">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>

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