URL
https://opencores.org/ocsvn/mem_ctrl/mem_ctrl/trunk
Subversion Repositories mem_ctrl
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 11 to Rev 12
- ↔ Reverse comparison
Rev 11 → Rev 12
/trunk/rtl/verilog/mc_cs_rf.v
37,10 → 37,10
|
// CVS Log |
// |
// $Id: mc_cs_rf.v,v 1.2 2001-08-10 08:16:21 rudi Exp $ |
// $Id: mc_cs_rf.v,v 1.3 2001-09-24 00:38:21 rudi Exp $ |
// |
// $Date: 2001-08-10 08:16:21 $ |
// $Revision: 1.2 $ |
// $Date: 2001-09-24 00:38:21 $ |
// $Revision: 1.3 $ |
// $Author: rudi $ |
// $Locker: $ |
// $State: Exp $ |
47,6 → 47,12
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.2 2001/08/10 08:16:21 rudi |
// |
// - Changed IO names to be more clear. |
// - Uniquifyed define names to be core specific. |
// - Removed "Refresh Early" configuration |
// |
// Revision 1.1 2001/07/29 07:34:41 rudi |
// |
// |
129,14 → 135,14
|
assign sel = addr[6:3] == reg_select[3:0]; |
|
always @(posedge clk) |
if(!rst) csc <= #1 (this_cs[2:0] == `MC_DEF_SEL) ? |
always @(posedge clk or posedge rst) |
if(rst) csc <= #1 (this_cs[2:0] == `MC_DEF_SEL) ? |
{26'h0, poc[1:0], 1'b0, poc[3:2], (poc[3:2] != 2'b00)} : 32'h0; |
else |
if(rf_we & sel & !addr[2]) csc <= #1 din; |
|
always @(posedge clk) |
if(!rst) tms <= #1 (this_cs[2:0] == `MC_DEF_SEL) ? |
always @(posedge clk or posedge rst) |
if(rst) tms <= #1 (this_cs[2:0] == `MC_DEF_SEL) ? |
`MC_DEF_POR_TMS : 32'h0; |
else |
if(rf_we & sel & addr[2]) tms <= #1 din; |
148,8 → 154,8
always @(posedge clk) |
lmr_req_we <= #1 rf_we & sel & addr[2]; |
|
always @(posedge clk or negedge rst) |
if(!rst) lmr_req <= #1 1'b0; |
always @(posedge clk or posedge rst) |
if(rst) lmr_req <= #1 1'b0; |
else |
if(lmr_req_we & (csc[3:1] == `MC_MEM_TYPE_SDRAM)) |
lmr_req <= #1 inited; |
163,8 → 169,8
always @(posedge clk) |
init_req_we <= #1 rf_we & sel & !addr[2]; |
|
always @(posedge clk or negedge rst) |
if(!rst) init_req <= #1 1'b0; |
always @(posedge clk or posedge rst) |
if(rst) init_req <= #1 1'b0; |
else |
if(init_req_we & (csc[3:1] == `MC_MEM_TYPE_SDRAM) & csc[0] & !inited) |
init_req <= #1 1'b1; |
171,8 → 177,8
else |
if(init_ack) init_req <= #1 1'b0; |
|
always @(posedge clk or negedge rst) |
if(!rst) inited <= #1 1'b0; |
always @(posedge clk or posedge rst) |
if(rst) inited <= #1 1'b0; |
else |
if(init_ack) inited <= #1 1'b1; |
|
/trunk/rtl/verilog/mc_mem_if.v
38,10 → 38,10
|
// CVS Log |
// |
// $Id: mc_mem_if.v,v 1.2 2001-09-02 02:28:28 rudi Exp $ |
// $Id: mc_mem_if.v,v 1.3 2001-09-24 00:38:21 rudi Exp $ |
// |
// $Date: 2001-09-02 02:28:28 $ |
// $Revision: 1.2 $ |
// $Date: 2001-09-24 00:38:21 $ |
// $Revision: 1.3 $ |
// $Author: rudi $ |
// $Locker: $ |
// $State: Exp $ |
48,6 → 48,10
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.2 2001/09/02 02:28:28 rudi |
// |
// Many fixes for minor bugs that showed up in gate level simulations. |
// |
// Revision 1.1 2001/07/29 07:34:41 rudi |
// |
// |
187,8 → 191,9
always @(posedge mc_clk) |
mc_bg <= #1 mc_bg_d; |
|
always @(posedge mc_clk) |
mc_data_oe <= #1 data_oe & !susp_sel & mc_c_oe & rst; |
always @(posedge mc_clk or posedge rst) |
if(rst) mc_data_oe <= #1 1'b0; |
else mc_data_oe <= #1 data_oe & !susp_sel & mc_c_oe; |
|
always @(posedge mc_clk) |
mc_data_o <= #1 mc_data_od; |
208,8 → 213,8
data_oe ? ~mc_dqm_r : |
(wb_cycle & !wr_cycle) ? 4'h0 : 4'hf; |
|
always @(posedge mc_clk or negedge rst) |
if(!rst) mc_oe_ <= #1 1'b1; |
always @(posedge mc_clk or posedge rst) |
if(rst) mc_oe_ <= #1 1'b1; |
else mc_oe_ <= #1 oe_ | susp_sel; |
|
always @(posedge mc_clk) |
233,8 → 238,8
)); |
*/ |
|
always @(posedge mc_clk or negedge rst) |
if(!rst) mc_cs_[0] <= #1 1'b1; |
always @(posedge mc_clk or posedge rst) |
if(rst) mc_cs_[0] <= #1 1'b1; |
else |
mc_cs_[0] <= #1 ~(cs_en & ( |
(rfr_ack | susp_sel) ? cs_need_rfr[0] : |
242,8 → 247,8
cs[0] |
)); |
|
always @(posedge mc_clk or negedge rst) |
if(!rst) mc_cs_[1] <= #1 1'b1; |
always @(posedge mc_clk or posedge rst) |
if(rst) mc_cs_[1] <= #1 1'b1; |
else |
mc_cs_[1] <= #1 ~(cs_en & ( |
(rfr_ack | susp_sel) ? cs_need_rfr[1] : |
251,8 → 256,8
cs[1] |
)); |
|
always @(posedge mc_clk or negedge rst) |
if(!rst) mc_cs_[2] <= #1 1'b1; |
always @(posedge mc_clk or posedge rst) |
if(rst) mc_cs_[2] <= #1 1'b1; |
else |
mc_cs_[2] <= #1 ~(cs_en & ( |
(rfr_ack | susp_sel) ? cs_need_rfr[2] : |
260,8 → 265,8
cs[2] |
)); |
|
always @(posedge mc_clk or negedge rst) |
if(!rst) mc_cs_[3] <= #1 1'b1; |
always @(posedge mc_clk or posedge rst) |
if(rst) mc_cs_[3] <= #1 1'b1; |
else |
mc_cs_[3] <= #1 ~(cs_en & ( |
(rfr_ack | susp_sel) ? cs_need_rfr[3] : |
269,8 → 274,8
cs[3] |
)); |
|
always @(posedge mc_clk or negedge rst) |
if(!rst) mc_cs_[4] <= #1 1'b1; |
always @(posedge mc_clk or posedge rst) |
if(rst) mc_cs_[4] <= #1 1'b1; |
else |
mc_cs_[4] <= #1 ~(cs_en & ( |
(rfr_ack | susp_sel) ? cs_need_rfr[4] : |
278,8 → 283,8
cs[4] |
)); |
|
always @(posedge mc_clk or negedge rst) |
if(!rst) mc_cs_[5] <= #1 1'b1; |
always @(posedge mc_clk or posedge rst) |
if(rst) mc_cs_[5] <= #1 1'b1; |
else |
mc_cs_[5] <= #1 ~(cs_en & ( |
(rfr_ack | susp_sel) ? cs_need_rfr[5] : |
287,8 → 292,8
cs[5] |
)); |
|
always @(posedge mc_clk or negedge rst) |
if(!rst) mc_cs_[6] <= #1 1'b1; |
always @(posedge mc_clk or posedge rst) |
if(rst) mc_cs_[6] <= #1 1'b1; |
else |
mc_cs_[6] <= #1 ~(cs_en & ( |
(rfr_ack | susp_sel) ? cs_need_rfr[6] : |
296,8 → 301,8
cs[6] |
)); |
|
always @(posedge mc_clk or negedge rst) |
if(!rst) mc_cs_[7] <= #1 1'b1; |
always @(posedge mc_clk or posedge rst) |
if(rst) mc_cs_[7] <= #1 1'b1; |
else |
mc_cs_[7] <= #1 ~(cs_en & ( |
(rfr_ack | susp_sel) ? cs_need_rfr[7] : |
/trunk/rtl/verilog/mc_refresh.v
38,10 → 38,10
|
// CVS Log |
// |
// $Id: mc_refresh.v,v 1.1 2001-07-29 07:34:41 rudi Exp $ |
// $Id: mc_refresh.v,v 1.2 2001-09-24 00:38:21 rudi Exp $ |
// |
// $Date: 2001-07-29 07:34:41 $ |
// $Revision: 1.1 $ |
// $Date: 2001-09-24 00:38:21 $ |
// $Revision: 1.2 $ |
// $Author: rudi $ |
// $Locker: $ |
// $State: Exp $ |
48,6 → 48,12
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.1 2001/07/29 07:34:41 rudi |
// |
// |
// 1) Changed Directory Structure |
// 2) Fixed several minor bugs |
// |
// Revision 1.3 2001/06/12 15:19:49 rudi |
// |
// |
139,8 → 145,8
always @(posedge clk) |
rfr_en <= #1 |cs_need_rfr; |
|
always @(posedge clk or negedge rst) |
if(!rst) ps_cnt <= #1 8'h0; |
always @(posedge clk or posedge rst) |
if(rst) ps_cnt <= #1 8'h0; |
else |
if(ps_cnt_clr) ps_cnt <= #1 8'h0; |
else |
159,8 → 165,8
always @(posedge clk) |
rfr_ce <= #1 ps_cnt_clr; |
|
always @(posedge clk or negedge rst) |
if(!rst) rfr_cnt <= #1 8'h0; |
always @(posedge clk or posedge rst) |
if(rst) rfr_cnt <= #1 8'h0; |
else |
if(rfr_ack) rfr_cnt <= #1 8'h0; |
else |
178,8 → 184,8
3'h7: rfr_clr <= #1 &rfr_cnt[7:0] & rfr_early; |
endcase |
|
always @(posedge clk or negedge rst) |
if(!rst) rfr_req <= #1 1'b0; |
always @(posedge clk or posedge rst) |
if(rst) rfr_req <= #1 1'b0; |
else |
if(rfr_ack) rfr_req <= #1 1'b0; |
else |
/trunk/rtl/verilog/mc_dp.v
38,10 → 38,10
|
// CVS Log |
// |
// $Id: mc_dp.v,v 1.2 2001-08-10 08:16:21 rudi Exp $ |
// $Id: mc_dp.v,v 1.3 2001-09-24 00:38:21 rudi Exp $ |
// |
// $Date: 2001-08-10 08:16:21 $ |
// $Revision: 1.2 $ |
// $Date: 2001-09-24 00:38:21 $ |
// $Revision: 1.3 $ |
// $Author: rudi $ |
// $Locker: $ |
// $State: Exp $ |
48,6 → 48,12
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.2 2001/08/10 08:16:21 rudi |
// |
// - Changed IO names to be more clear. |
// - Uniquifyed define names to be core specific. |
// - Removed "Refresh Early" configuration |
// |
// Revision 1.1 2001/07/29 07:34:41 rudi |
// |
// |
146,7 → 152,7
always @(posedge clk) |
mc_data_del <= #1 {mc_dp_i, mc_data_i}; |
|
assign rd_fifo_clr = rst & wb_cyc_i; |
assign rd_fifo_clr = !rst & wb_cyc_i; |
assign re = mem_wb_ack_o & wb_read_go; |
|
mc_rd_fifo u0( |
/trunk/rtl/verilog/mc_wb_if.v
38,10 → 38,10
|
// CVS Log |
// |
// $Id: mc_wb_if.v,v 1.2 2001-08-10 08:16:21 rudi Exp $ |
// $Id: mc_wb_if.v,v 1.3 2001-09-24 00:38:21 rudi Exp $ |
// |
// $Date: 2001-08-10 08:16:21 $ |
// $Revision: 1.2 $ |
// $Date: 2001-09-24 00:38:21 $ |
// $Revision: 1.3 $ |
// $Author: rudi $ |
// $Locker: $ |
// $State: Exp $ |
48,6 → 48,12
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.2 2001/08/10 08:16:21 rudi |
// |
// - Changed IO names to be more clear. |
// - Uniquifyed define names to be core specific. |
// - Removed "Refresh Early" configuration |
// |
// Revision 1.1 2001/07/29 07:34:41 rudi |
// |
// |
126,8 → 132,8
|
assign mem_sel = `MC_MEM_SEL; |
|
always @(posedge clk or negedge rst) |
if(!rst) rmw_en <= #1 1'b0; |
always @(posedge clk or posedge rst) |
if(rst) rmw_en <= #1 1'b0; |
else |
if(mem_ack) rmw_en <= #1 1'b1; |
else |
160,8 → 166,8
assign wb_first_set = mem_sel & wb_cyc_i & wb_stb_i & !(read_go_r | write_go_r); |
assign wb_first = wb_first_set | (wb_first_r & !mem_ack & !wb_err); |
|
always @(posedge clk or negedge rst) |
if(!rst) wb_first_r <= #1 1'b0; |
always @(posedge clk or posedge rst) |
if(rst) wb_first_r <= #1 1'b0; |
else |
if(wb_first_set) wb_first_r <= #1 1'b1; |
else |
/trunk/rtl/verilog/mc_obct.v
38,10 → 38,10
|
// CVS Log |
// |
// $Id: mc_obct.v,v 1.1 2001-07-29 07:34:41 rudi Exp $ |
// $Id: mc_obct.v,v 1.2 2001-09-24 00:38:21 rudi Exp $ |
// |
// $Date: 2001-07-29 07:34:41 $ |
// $Revision: 1.1 $ |
// $Date: 2001-09-24 00:38:21 $ |
// $Revision: 1.2 $ |
// $Author: rudi $ |
// $Locker: $ |
// $State: Exp $ |
48,6 → 48,12
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.1 2001/07/29 07:34:41 rudi |
// |
// |
// 1) Changed Directory Structure |
// 2) Fixed several minor bugs |
// |
// Revision 1.3 2001/06/12 15:19:49 rudi |
// |
// |
108,8 → 114,8
// Bank Open/Closed Tracking |
// |
|
always @(posedge clk or negedge rst) |
if(!rst) bank0_open <= #1 1'b0; |
always @(posedge clk or posedge rst) |
if(rst) bank0_open <= #1 1'b0; |
else |
if((bank_adr == 2'h0) & bank_set) bank0_open <= #1 1'b1; |
else |
117,8 → 123,8
else |
if(bank_clr_all) bank0_open <= #1 1'b0; |
|
always @(posedge clk or negedge rst) |
if(!rst) bank1_open <= #1 1'b0; |
always @(posedge clk or posedge rst) |
if(rst) bank1_open <= #1 1'b0; |
else |
if((bank_adr == 2'h1) & bank_set) bank1_open <= #1 1'b1; |
else |
126,8 → 132,8
else |
if(bank_clr_all) bank1_open <= #1 1'b0; |
|
always @(posedge clk or negedge rst) |
if(!rst) bank2_open <= #1 1'b0; |
always @(posedge clk or posedge rst) |
if(rst) bank2_open <= #1 1'b0; |
else |
if((bank_adr == 2'h2) & bank_set) bank2_open <= #1 1'b1; |
else |
135,8 → 141,8
else |
if(bank_clr_all) bank2_open <= #1 1'b0; |
|
always @(posedge clk or negedge rst) |
if(!rst) bank3_open <= #1 1'b0; |
always @(posedge clk or posedge rst) |
if(rst) bank3_open <= #1 1'b0; |
else |
if((bank_adr == 2'h3) & bank_set) bank3_open <= #1 1'b1; |
else |
/trunk/rtl/verilog/mc_rf.v
37,10 → 37,10
|
// CVS Log |
// |
// $Id: mc_rf.v,v 1.2 2001-08-10 08:16:21 rudi Exp $ |
// $Id: mc_rf.v,v 1.3 2001-09-24 00:38:21 rudi Exp $ |
// |
// $Date: 2001-08-10 08:16:21 $ |
// $Revision: 1.2 $ |
// $Date: 2001-09-24 00:38:21 $ |
// $Revision: 1.3 $ |
// $Author: rudi $ |
// $Locker: $ |
// $State: Exp $ |
47,6 → 47,12
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.2 2001/08/10 08:16:21 rudi |
// |
// - Changed IO names to be more clear. |
// - Uniquifyed define names to be core specific. |
// - Removed "Refresh Early" configuration |
// |
// Revision 1.1 2001/07/29 07:34:41 rudi |
// |
// |
179,7 → 185,6
wire wp_err4, wp_err5, wp_err6, wp_err7; |
reg wp_err; |
|
|
wire lmr_req7, lmr_req6, lmr_req5, lmr_req4; |
wire lmr_req3, lmr_req2, lmr_req1, lmr_req0; |
wire lmr_ack7, lmr_ack6, lmr_ack5, lmr_ack4; |
245,14 → 250,14
|
assign rf_we = `MC_REG_SEL & wb_we_i & wb_cyc_i & wb_stb_i; |
|
always @(posedge clk or negedge rst) |
if(!rst) csr_r2 <= #1 8'h0; |
always @(posedge clk or posedge rst) |
if(rst) csr_r2 <= #1 8'h0; |
else |
if(rf_we & (wb_addr_i[6:2] == 5'h0) ) |
csr_r2 <= #1 wb_data_i[31:24]; |
|
always @(posedge clk or negedge rst) |
if(!rst) csr_r[10:1] <= #1 10'h0; |
always @(posedge clk or posedge rst) |
if(rst) csr_r[10:1] <= #1 10'h0; |
else |
if(rf_we & (wb_addr_i[6:2] == 5'h0) ) |
csr_r[10:1] <= #1 wb_data_i[10:1]; |
264,14 → 269,14
assign fs = csr_r[2]; |
assign rfr_ps_val = csr_r2[7:0]; |
|
always @(posedge clk or negedge rst) |
if(!rst) csc_mask_r <= #1 11'h7ff; |
always @(posedge clk or posedge rst) |
if(rst) csc_mask_r <= #1 11'h7ff; |
else |
if(rf_we & (wb_addr_i[6:2] == 5'h2) ) |
csc_mask_r <= #1 wb_data_i[10:0]; |
|
always @(posedge clk) |
if(!rst) poc <= #1 mc_data_i; |
if(rst) poc <= #1 mc_data_i; |
|
//////////////////////////////////////////////////////////////////// |
// |
/trunk/rtl/verilog/mc_timing.v
37,10 → 37,10
|
// CVS Log |
// |
// $Id: mc_timing.v,v 1.3 2001-09-02 02:28:28 rudi Exp $ |
// $Id: mc_timing.v,v 1.4 2001-09-24 00:38:21 rudi Exp $ |
// |
// $Date: 2001-09-02 02:28:28 $ |
// $Revision: 1.3 $ |
// $Date: 2001-09-24 00:38:21 $ |
// $Revision: 1.4 $ |
// $Author: rudi $ |
// $Locker: $ |
// $State: Exp $ |
47,6 → 47,10
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.3 2001/09/02 02:28:28 rudi |
// |
// Many fixes for minor bugs that showed up in gate level simulations. |
// |
// Revision 1.2 2001/08/10 08:16:21 rudi |
// |
// - Changed IO names to be more clear. |
415,12 → 419,12
rsts <= #1 rsts1; |
|
// Control Signals Output Enable |
always @(posedge clk) |
if(!rst) mc_c_oe <= #1 1'b0; |
always @(posedge clk or posedge rst) |
if(rst) mc_c_oe <= #1 1'b0; |
else mc_c_oe <= #1 mc_c_oe_d; |
|
always @(posedge clk or negedge rsts) |
if(!rsts) mc_le <= #1 1'b0; |
always @(posedge clk or posedge rsts) |
if(rsts) mc_le <= #1 1'b0; |
else mc_le <= #1 ~mc_le; |
|
always @(posedge clk) |
514,8 → 518,8
lookup_ready2 <= #1 lookup_ready1; |
|
// Keep Track if it is a SDRAM write cycle |
always @(posedge clk or negedge rst) |
if(!rst) wr_cycle <= #1 1'b0; |
always @(posedge clk or posedge rst) |
if(rst) wr_cycle <= #1 1'b0; |
else |
if(wr_set) wr_cycle <= #1 1'b1; |
else |
522,8 → 526,8
if(wr_clr) wr_cycle <= #1 1'b0; |
|
// Track when a cycle is *still* active |
always @(posedge clk or negedge rst) |
if(!rst) wb_cycle <= #1 1'b0; |
always @(posedge clk or posedge rst) |
if(rst) wb_cycle <= #1 1'b0; |
else |
if(wb_cycle_set) wb_cycle <= #1 1'b1; |
else |
530,8 → 534,8
if(!wb_cyc_i) wb_cycle <= #1 1'b0; |
|
// Track ack's for read cycles |
always @(posedge clk or negedge rst) |
if(!rst) ack_cnt <= #1 4'h0; |
always @(posedge clk or posedge rst) |
if(rst) ack_cnt <= #1 4'h0; |
else |
if(!wb_read_go & !wb_write_go) ack_cnt <= #1 4'h0; |
else |
563,8 → 567,8
// Suspend Select Logic |
assign susp_sel = susp_sel_r | susp_sel_set; |
|
always @(posedge clk or negedge rst) |
if(!rst) susp_sel_r <= #1 0; |
always @(posedge clk or posedge rst) |
if(rst) susp_sel_r <= #1 0; |
else |
if(susp_sel_set) susp_sel_r <= #1 1'b1; |
else |
610,9 → 614,9
assign twrp = tms_x[16:15] + tms_x[23:20]; |
|
// SDRAM Memories timing tracker |
always @(posedge clk or negedge rst) |
always @(posedge clk or posedge rst) |
`ifdef MC_POR_DELAY |
if(!rst) timer <= #1 `MC_POR_DELAY_VAL ; |
if(rst) timer <= #1 `MC_POR_DELAY_VAL ; |
else |
`endif |
if(tmr_ld_twr2) timer <= #1 { 4'h0, tms_x[15:12] }; |
683,11 → 687,11
// Main State Machine |
// |
|
always @(posedge clk or negedge rst) |
always @(posedge clk or posedge rst) |
`ifdef MC_POR_DELAY |
if(!rst) state <= #1 POR; |
if(rst) state <= #1 POR; |
`else |
if(!rst) state <= #1 IDLE; |
if(rst) state <= #1 IDLE; |
`endif |
else state <= #1 next_state; |
|