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Rev 11 → Rev 12

/trunk/verilog/rtl/ex.v
0,0 → 1,86
//--------------------------------------------------------------------------------------------------
//
// Title : ex
// Design : MicroRISCII
// Author : Ali Mashtizadeh
//
//-------------------------------------------------------------------------------------------------
`timescale 1ps / 1ps
 
module ex(a,b,ex_op,ex_mux,clk,carryin,ex_flush,ex_halt,o,t_out);
// Inputs
input [31:0] a;
wire [31:0] a;
input [31:0] b;
wire [31:0] b;
input [3:0] ex_op;
wire [3:0] ex_op;
input [1:0] ex_mux;
wire [1:0] ex_mux;
input clk;
wire clk;
input carryin;
wire carryin;
input ex_flush;
wire ex_flush;
input ex_halt;
wire ex_halt;
// Outputs
output [31:0] o;
reg [31:0] o;
output t_out;
reg t_out;
// Internal
wire [31:0] au_o;
wire [31:0] lu_o;
wire testresult;
wire carryout;
wire testout;
wire rndau;
reg CARRYSTATE;
 
au arith_unit(
.a(a),
.b(b),
.arith_op(ex_op),
.carry(carryout),
.o(au_o),
.rndin(rndau)
);
 
lu logic_unit(
.a(a),
.b(b),
.logic_op(ex_op),
.o(lu_o)
);
 
cmp compare_unit(
.a(a),
.b(b),
.cmp_op(ex_op),
.true(testout),
.c(CARRYSTATE)
);
 
always @ (posedge clk || ex_flush || ex_halt || a || b || testout || carryout)
if (ex_halt == 1'b0)
if (ex_flush == 1'b0)
begin
case (ex_mux)
2'b00 : o = au_o;
2'b01 : o = lu_o;
2'b10 : o = a;
2'b11 : o = b;
endcase
t_out = testout;
if (ex_mux == 2'b0)
CARRYSTATE = carryout;
end
else
begin
o = 32'b0;
CARRYSTATE = carryin;
end
 
endmodule
/trunk/verilog/rtl/if.v
0,0 → 1,41
//--------------------------------------------------------------------------------------------------
//
// Title : if
// Design : MicroRISCII
// Author : Ali Mashtizadeh
//
//-------------------------------------------------------------------------------------------------
`timescale 1ps / 1ps
 
module wb(clk,if_halt,idata_in,idata_addr,idata_ready,opcode,opcode_pc);
// Inputs
input clk;
wire clk;
input if_halt;
wire if_halt;
input [31:0] idata_in;
wire [31:0] idata_in;
input [31:0] idata_addr;
wire [31:0] idata_addr;
input idata_ready;
wire idata_ready;
// Outputs
output [31:0] opcode;
reg [31:0] opcode;
output [31:0] opcode_pc;
reg [31:0] opcode_pc;
 
always @ (posedge clk)
if (if_halt == 1'b0)
if (idata_ready == 1'b1)
begin
opcode = idata_in;
opcode_pc = idata_addr;
end
else // NOP Until Instruction Found
begin // Don't stall pipeline ;)
opcode = 32'b0;
opcode_pc = 32'b0;
end
 
endmodule
/trunk/verilog/rtl/cmp.v
0,0 → 1,101
//--------------------------------------------------------------------------------------------------
//
// Title : cmp
// Design : MicroRISCII
// Author : Ali Mashtizadeh
//
//-------------------------------------------------------------------------------------------------
`timescale 1ps / 1ps
 
// Left to simplify decodeing
//`define CMP_J 4'b0000
//`define CMP_JR 4'b0001
`define CMP_EQ 4'b0010
`define CMP_NE 4'b0011
`define CMP_C 4'b0100
`define CMP_NC 4'b0101
`define CMP_Z 4'b0110
`define CMP_NZ 4'b0111
`define CMP_LT 4'b1000
`define CMP_NLT 4'b1001
`define CMP_LTS 4'b1010
`define CMP_NLTS 4'b1011
`define CMP_GT 4'b1100
`define CMP_NGT 4'b1101
`define CMP_GTS 4'b1110
`define CMP_NGTS 4'b1111
 
module cmp(a,b,cmp_op,true,c);
// Inputs
input [31:0] a;
wire [31:0] a;
input [31:0] b;
wire [31:0] b;
input [3:0] cmp_op;
wire [3:0] cmp_op;
input c;
wire c;
// Outputs
output true;
reg true;
// Internal
reg eq;
reg lt;
reg gt;
reg lts;
reg gts;
reg z;
 
always @ (a || b)
begin
if (a == b)
eq = 1'b1;
else
eq = 1'b0;
if (a < b)
lt = 1'b1;
else
lt = 1'b0;
if ((a[30:0] < b[30]) && a[31] && b[31])
lts = 1'b1;
else if (a[31] == 1'b1 && b[31] == 1'b0)
lts = 1'b1;
else
lts = 1'b0;
if (a > b)
gt = 1'b1;
else
gt = 1'b0;
if ((a[30:0] > b[30]) && a[31] && b[31])
gts = 1'b1;
else if (a[31] == 1'b0 && b[31] == 1'b1)
gts = 1'b1;
else
gts = 1'b0;
if (a == 32'b0)
z = 1'b1;
else
z = 1'b0;
end
 
always @ (cmp_op || eq || z || c || lt || gt)
case (cmp_op)
//`CMP_J : true = 1'b1; // Taken care of in decoder
//`CMP_JR : true = 1'b1; // Taken care of in decoder
`CMP_EQ : true = eq;
`CMP_NE : true = !(eq);
`CMP_Z : true = z;
`CMP_NZ : true = !(z);
`CMP_C : true = c;
`CMP_NC : true = !(c);
`CMP_LT : true = lts;
`CMP_NLT : true = !(lts);
`CMP_LTS : true = lt;
`CMP_NLTS : true = !(lt);
`CMP_GT : true = gts;
`CMP_NGT : true = !(gts);
`CMP_GTS : true = gt;
`CMP_NGTS : true = !(gt);
endcase
 
endmodule
/trunk/verilog/rtl/wb.v
0,0 → 1,46
//--------------------------------------------------------------------------------------------------
//
// Title : wb
// Design : MicroRISCII
// Author : Ali Mashtizadeh
//
//-------------------------------------------------------------------------------------------------
`timescale 1ps / 1ps
 
module wb(clk,wb_halt,d_in,d_out,d_sel_in,d_sel_out,dwe_in,dwe_out,wb_flush);
// Inputs
input clk;
wire clk;
input wb_halt;
wire wb_halt;
input [31:0] d_in;
wire [31:0] d_in;
input [3:0] d_sel_in;
wire [3:0] d_sel_in;
input dwe_in;
wire dwe_in;
input wb_flush;
wire wb_flush;
 
// Outputs
output [31:0] d_out;
reg [31:0] d_out;
output [3:0] d_sel_out;
reg [3:0] d_sel_out;
output dwe_out;
reg dwe_out;
 
always @ (posedge clk)
begin
if (wb_halt == 1'b0)
begin
d_out = d_in;
d_sel_out = d_sel_in;
if (wb_flush == 1'b1)
dwe_out = 1'b0;
else
dwe_out = dwe_in;
end
end
 
endmodule

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