URL
https://opencores.org/ocsvn/neorv32/neorv32/trunk
Subversion Repositories neorv32
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 11 to Rev 12
- ↔ Reverse comparison
Rev 11 → Rev 12
/neorv32/trunk/docs/figures/neorv32_cpu.png
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/neorv32/trunk/docs/figures/neorv32_processor.png
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/neorv32/trunk/docs/NEORV32.pdf
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svn:mime-type = application/octet-stream
/neorv32/trunk/rtl/core/neorv32_application_image.vhd
40,8 → 40,8
00000029 => x"8f13000e", |
00000030 => x"0f93000e", |
00000031 => x"0001000f", |
00000032 => x"fc5025f3", |
00000033 => x"fc702673", |
00000032 => x"ff402583", |
00000033 => x"ffc02603", |
00000034 => x"00c58133", |
00000035 => x"04131171", |
00000036 => x"01970001", |
48,11 → 48,11
00000037 => x"81938000", |
00000038 => x"05977ee1", |
00000039 => x"85930000", |
00000040 => x"90730925", |
00000041 => x"25f33055", |
00000042 => x"0617fc50", |
00000040 => x"90730965", |
00000041 => x"25833055", |
00000042 => x"0617ff40", |
00000043 => x"06130000", |
00000044 => x"069314c6", |
00000044 => x"06931506", |
00000045 => x"c1900200", |
00000046 => x"16fd0591", |
00000047 => x"fed01de3", |
59,1095 → 59,1160
00000048 => x"f8000593", |
00000049 => x"0005a023", |
00000050 => x"1de30591", |
00000051 => x"55fdfeb0", |
00000052 => x"f8b02c23", |
00000053 => x"f8b02e23", |
00000054 => x"80818593", |
00000055 => x"82c18613", |
00000056 => x"00c5d663", |
00000057 => x"00058023", |
00000058 => x"bfdd0585", |
00000059 => x"00001597", |
00000060 => x"0dc58593", |
00000061 => x"80000617", |
00000062 => x"f8c60613", |
00000063 => x"80818693", |
00000064 => x"00d65963", |
00000065 => x"00058703", |
00000066 => x"00e60023", |
00000067 => x"06050585", |
00000068 => x"0513bfc5", |
00000069 => x"05930000", |
00000070 => x"00ef0000", |
00000071 => x"00730e00", |
00000072 => x"70731050", |
00000073 => x"00733004", |
00000074 => x"a0011050", |
00000075 => x"f8810113", |
00000076 => x"c20ec006", |
00000077 => x"c616c412", |
00000078 => x"ca1ec81a", |
00000079 => x"ce26cc22", |
00000080 => x"d22ed02a", |
00000081 => x"d636d432", |
00000082 => x"da3ed83a", |
00000083 => x"de46dc42", |
00000084 => x"c2cec0ca", |
00000085 => x"c6d6c4d2", |
00000086 => x"cadec8da", |
00000087 => x"cee6cce2", |
00000088 => x"d2eed0ea", |
00000089 => x"d6f6d4f2", |
00000090 => x"dafed8fa", |
00000091 => x"342022f3", |
00000092 => x"00f2f313", |
00000093 => x"20f3030a", |
00000094 => x"9306fc50", |
00000095 => x"341020f3", |
00000096 => x"0002cd63", |
00000097 => x"00009283", |
00000098 => x"00300393", |
00000099 => x"0072f2b3", |
00000100 => x"96630089", |
00000101 => x"00890072", |
00000102 => x"0313a019", |
00000103 => x"22830403", |
00000104 => x"11710003", |
00000105 => x"80e7c006", |
00000106 => x"40820002", |
00000107 => x"90730111", |
00000108 => x"40823410", |
00000109 => x"42224192", |
00000110 => x"434242b2", |
00000111 => x"446243d2", |
00000112 => x"550244f2", |
00000113 => x"56225592", |
00000114 => x"574256b2", |
00000115 => x"586257d2", |
00000116 => x"490658f2", |
00000117 => x"4a264996", |
00000118 => x"4b464ab6", |
00000119 => x"4c664bd6", |
00000120 => x"5d064cf6", |
00000121 => x"5e265d96", |
00000122 => x"5f465eb6", |
00000123 => x"01135fd6", |
00000124 => x"00730781", |
00000125 => x"80823020", |
00000126 => x"71790000", |
00000127 => x"d422d606", |
00000128 => x"d04ad226", |
00000129 => x"00efce4e", |
00000130 => x"0a630870", |
00000131 => x"00ef0c05", |
00000132 => x"066325b0", |
00000133 => x"00ef0c05", |
00000134 => x"02637de0", |
00000135 => x"65150c05", |
00000136 => x"45814601", |
00000137 => x"b0050513", |
00000138 => x"06f000ef", |
00000139 => x"557d55fd", |
00000140 => x"7ce000ef", |
00000141 => x"05136505", |
00000142 => x"00efce85", |
00000143 => x"00ef0db0", |
00000144 => x"23997ae0", |
00000145 => x"05136505", |
00000146 => x"00efd045", |
00000147 => x"45810cb0", |
00000148 => x"67c00593", |
00000149 => x"21d54501", |
00000150 => x"842a4581", |
00000151 => x"68a00593", |
00000152 => x"29e14505", |
00000153 => x"942a4581", |
00000154 => x"69800593", |
00000155 => x"21f14509", |
00000156 => x"942a4581", |
00000157 => x"6a600593", |
00000158 => x"21c1450d", |
00000159 => x"942a4581", |
00000160 => x"6b400593", |
00000161 => x"29554511", |
00000162 => x"942a4581", |
00000163 => x"6c200593", |
00000164 => x"21654515", |
00000165 => x"942a4581", |
00000166 => x"6d000593", |
00000167 => x"29714519", |
00000168 => x"942a4581", |
00000169 => x"6de00593", |
00000170 => x"2941451d", |
00000171 => x"942a4581", |
00000172 => x"6ec00593", |
00000173 => x"2151452d", |
00000174 => x"942a4581", |
00000175 => x"6fa00593", |
00000176 => x"29a5454d", |
00000177 => x"942a4581", |
00000178 => x"71600593", |
00000179 => x"21b5455d", |
00000180 => x"cc11942a", |
00000181 => x"05136505", |
00000182 => x"00efd385", |
00000183 => x"50b203b0", |
00000184 => x"54925422", |
00000185 => x"49f25902", |
00000186 => x"61454501", |
00000187 => x"45818082", |
00000188 => x"70800593", |
00000189 => x"00ef4501", |
00000190 => x"842a17d0", |
00000191 => x"6505c509", |
00000192 => x"d4850513", |
00000193 => x"6073bfd9", |
00000194 => x"65053004", |
00000195 => x"d6050513", |
00000196 => x"8201a423", |
00000197 => x"001000ef", |
00000198 => x"0ff0000f", |
00000199 => x"0000100f", |
00000200 => x"8281a783", |
00000201 => x"28078663", |
00000202 => x"05136505", |
00000203 => x"00efd705", |
00000204 => x"49017e60", |
00000205 => x"65054405", |
00000206 => x"d7c50513", |
00000207 => x"8201a423", |
00000208 => x"7d4000ef", |
00000209 => x"301027f3", |
00000210 => x"91638b91", |
00000211 => x"47892807", |
00000212 => x"a7039782", |
00000213 => x"57b78281", |
00000214 => x"87931234", |
00000215 => x"10636787", |
00000216 => x"650526f7", |
00000217 => x"d7850513", |
00000218 => x"7ac000ef", |
00000219 => x"a4230905", |
00000220 => x"49898201", |
00000221 => x"05136505", |
00000222 => x"00efdb85", |
00000223 => x"079379a0", |
00000224 => x"9782f000", |
00000225 => x"8281a703", |
00000226 => x"aabb17b7", |
00000227 => x"13378793", |
00000228 => x"24f71563", |
00000229 => x"05136505", |
00000230 => x"00efd785", |
00000231 => x"090577a0", |
00000232 => x"05136505", |
00000233 => x"a423dc85", |
00000234 => x"00ef8201", |
00000235 => x"07b776a0", |
00000236 => x"87938000", |
00000237 => x"80e70807", |
00000238 => x"a7030007", |
00000239 => x"27b78281", |
00000240 => x"87930199", |
00000241 => x"116303b7", |
00000242 => x"650522f7", |
00000243 => x"d7850513", |
00000244 => x"744000ef", |
00000245 => x"65050905", |
00000246 => x"dd850513", |
00000247 => x"8201a423", |
00000248 => x"734000ef", |
00000249 => x"a7039002", |
00000250 => x"27b78281", |
00000251 => x"87931232", |
00000252 => x"12633307", |
00000253 => x"650520f7", |
00000254 => x"d7850513", |
00000255 => x"718000ef", |
00000256 => x"65050905", |
00000257 => x"de850513", |
00000258 => x"8201a423", |
00000259 => x"708000ef", |
00000260 => x"00202003", |
00000261 => x"8281a703", |
00000262 => x"babcd7b7", |
00000263 => x"ccc78793", |
00000264 => x"1ef71263", |
00000265 => x"05136505", |
00000266 => x"00efd785", |
00000267 => x"09056ea0", |
00000268 => x"05136505", |
00000269 => x"a423df85", |
00000270 => x"00ef8201", |
00000271 => x"27836da0", |
00000272 => x"c63ef000", |
00000273 => x"8281a703", |
00000274 => x"def737b7", |
00000275 => x"8aa78793", |
00000276 => x"1cf71163", |
00000277 => x"05136505", |
00000278 => x"00efd785", |
00000279 => x"09056ba0", |
00000280 => x"05136505", |
00000281 => x"a423e085", |
00000282 => x"00ef8201", |
00000283 => x"21236aa0", |
00000284 => x"a7030000", |
00000285 => x"27b78281", |
00000286 => x"8793ff09", |
00000287 => x"11637dd7", |
00000288 => x"65051af7", |
00000289 => x"d7850513", |
00000290 => x"68c000ef", |
00000291 => x"65050905", |
00000292 => x"e1850513", |
00000293 => x"8201a423", |
00000294 => x"67c000ef", |
00000295 => x"f0002023", |
00000296 => x"8281a703", |
00000297 => x"200917b7", |
00000298 => x"77778793", |
00000299 => x"18f71163", |
00000051 => x"0597feb0", |
00000052 => x"85938000", |
00000053 => x"8613fba5", |
00000054 => x"d66382c1", |
00000055 => x"802300c5", |
00000056 => x"05850005", |
00000057 => x"1597bfdd", |
00000058 => x"85930000", |
00000059 => x"06171e65", |
00000060 => x"06138000", |
00000061 => x"0697f926", |
00000062 => x"86938000", |
00000063 => x"5963f926", |
00000064 => x"870300d6", |
00000065 => x"00230005", |
00000066 => x"058500e6", |
00000067 => x"bfc50605", |
00000068 => x"00000513", |
00000069 => x"00000593", |
00000070 => x"0ee000ef", |
00000071 => x"30047073", |
00000072 => x"10500073", |
00000073 => x"0013a001", |
00000074 => x"00130000", |
00000075 => x"00010000", |
00000076 => x"f8810113", |
00000077 => x"c20ec006", |
00000078 => x"c616c412", |
00000079 => x"ca1ec81a", |
00000080 => x"ce26cc22", |
00000081 => x"d22ed02a", |
00000082 => x"d636d432", |
00000083 => x"da3ed83a", |
00000084 => x"de46dc42", |
00000085 => x"c2cec0ca", |
00000086 => x"c6d6c4d2", |
00000087 => x"cadec8da", |
00000088 => x"cee6cce2", |
00000089 => x"d2eed0ea", |
00000090 => x"d6f6d4f2", |
00000091 => x"dafed8fa", |
00000092 => x"342022f3", |
00000093 => x"00f2f313", |
00000094 => x"2083030a", |
00000095 => x"9306ff40", |
00000096 => x"341020f3", |
00000097 => x"0002cd63", |
00000098 => x"00009283", |
00000099 => x"00300393", |
00000100 => x"0072f2b3", |
00000101 => x"96630089", |
00000102 => x"00890072", |
00000103 => x"0313a019", |
00000104 => x"22830403", |
00000105 => x"11710003", |
00000106 => x"80e7c006", |
00000107 => x"40820002", |
00000108 => x"90730111", |
00000109 => x"40823410", |
00000110 => x"42224192", |
00000111 => x"434242b2", |
00000112 => x"446243d2", |
00000113 => x"550244f2", |
00000114 => x"56225592", |
00000115 => x"574256b2", |
00000116 => x"586257d2", |
00000117 => x"490658f2", |
00000118 => x"4a264996", |
00000119 => x"4b464ab6", |
00000120 => x"4c664bd6", |
00000121 => x"5d064cf6", |
00000122 => x"5e265d96", |
00000123 => x"5f465eb6", |
00000124 => x"01135fd6", |
00000125 => x"00730781", |
00000126 => x"80823020", |
00000127 => x"00000000", |
00000128 => x"00000000", |
00000129 => x"71390000", |
00000130 => x"dc22de06", |
00000131 => x"d84ada26", |
00000132 => x"d452d64e", |
00000133 => x"00efd256", |
00000134 => x"00631230", |
00000135 => x"00ef0c05", |
00000136 => x"0c632fb0", |
00000137 => x"00ef0a05", |
00000138 => x"08630410", |
00000139 => x"65150a05", |
00000140 => x"45814601", |
00000141 => x"b0050513", |
00000142 => x"10b000ef", |
00000143 => x"45814501", |
00000144 => x"031000ef", |
00000145 => x"557d55fd", |
00000146 => x"063000ef", |
00000147 => x"05136505", |
00000148 => x"00efd9c5", |
00000149 => x"00ef16f0", |
00000150 => x"00ef0090", |
00000151 => x"650560a0", |
00000152 => x"db850513", |
00000153 => x"00ef4481", |
00000154 => x"059315b0", |
00000155 => x"450177e0", |
00000156 => x"842a232d", |
00000157 => x"77e00593", |
00000158 => x"23054505", |
00000159 => x"0593942a", |
00000160 => x"450977e0", |
00000161 => x"942a2b19", |
00000162 => x"77e00593", |
00000163 => x"2331450d", |
00000164 => x"0593942a", |
00000165 => x"451177e0", |
00000166 => x"942a2309", |
00000167 => x"77e00593", |
00000168 => x"29e54515", |
00000169 => x"0593942a", |
00000170 => x"451977e0", |
00000171 => x"942a21fd", |
00000172 => x"77e00593", |
00000173 => x"21d5451d", |
00000174 => x"0593942a", |
00000175 => x"452d77e0", |
00000176 => x"942a29e9", |
00000177 => x"77e00593", |
00000178 => x"29c1455d", |
00000179 => x"c005942a", |
00000180 => x"05136505", |
00000181 => x"00efdd05", |
00000182 => x"50f20eb0", |
00000183 => x"54d25462", |
00000184 => x"59b25942", |
00000185 => x"5a925a22", |
00000186 => x"61214501", |
00000187 => x"05938082", |
00000188 => x"450177e0", |
00000189 => x"22f000ef", |
00000190 => x"c509842a", |
00000191 => x"05136505", |
00000192 => x"bfd1de45", |
00000193 => x"30046073", |
00000194 => x"650554fd", |
00000195 => x"8291a423", |
00000196 => x"dfc50513", |
00000197 => x"a4236985", |
00000198 => x"00ef8291", |
00000199 => x"85130a70", |
00000200 => x"00efe0c9", |
00000201 => x"650509f0", |
00000202 => x"e2050513", |
00000203 => x"8291a423", |
00000204 => x"091000ef", |
00000205 => x"e0c98513", |
00000206 => x"089000ef", |
00000207 => x"05136505", |
00000208 => x"00efe305", |
00000209 => x"17b707f0", |
00000210 => x"87931bcd", |
00000211 => x"90732347", |
00000212 => x"47b7b007", |
00000213 => x"87930003", |
00000214 => x"90734557", |
00000215 => x"2773b807", |
00000216 => x"76c1b000", |
00000217 => x"06b78f75", |
00000218 => x"12631bcd", |
00000219 => x"277332d7", |
00000220 => x"1e63b800", |
00000221 => x"650530f7", |
00000222 => x"e4050513", |
00000223 => x"045000ef", |
00000224 => x"65054485", |
00000225 => x"e4c50513", |
00000226 => x"039000ef", |
00000227 => x"112247b7", |
00000228 => x"49978793", |
00000229 => x"b0279073", |
00000230 => x"000907b7", |
00000231 => x"907307c5", |
00000232 => x"2773b827", |
00000233 => x"76c1b020", |
00000234 => x"06b78f75", |
00000235 => x"18631122", |
00000236 => x"27732ed7", |
00000237 => x"1463b820", |
00000238 => x"65052ef7", |
00000239 => x"e4050513", |
00000240 => x"001000ef", |
00000241 => x"65050485", |
00000242 => x"e5c50513", |
00000243 => x"7f4000ef", |
00000244 => x"c01027f3", |
00000245 => x"2af3c83e", |
00000246 => x"79c1c810", |
00000247 => x"0137fa33", |
00000248 => x"00efca56", |
00000249 => x"f9b36aa0", |
00000250 => x"116300a9", |
00000251 => x"9f632d3a", |
00000252 => x"65052aba", |
00000253 => x"e4050513", |
00000254 => x"7c8000ef", |
00000255 => x"65050485", |
00000256 => x"051359fd", |
00000257 => x"a423e6c5", |
00000258 => x"00ef8331", |
00000259 => x"000f7b60", |
00000260 => x"100f0ff0", |
00000261 => x"a7830000", |
00000262 => x"80638281", |
00000263 => x"65052b37", |
00000264 => x"e4450513", |
00000265 => x"79c000ef", |
00000266 => x"65050405", |
00000267 => x"051357fd", |
00000268 => x"a423e7c5", |
00000269 => x"00ef82f1", |
00000270 => x"27f378a0", |
00000271 => x"8b913010", |
00000272 => x"28079b63", |
00000273 => x"97824789", |
00000274 => x"8281a783", |
00000275 => x"26079e63", |
00000276 => x"05136505", |
00000277 => x"00efe405", |
00000278 => x"048576a0", |
00000279 => x"65054995", |
00000280 => x"051357fd", |
00000281 => x"a423eb85", |
00000282 => x"00ef82f1", |
00000283 => x"07937560", |
00000284 => x"9782f000", |
00000285 => x"8281a703", |
00000286 => x"15634785", |
00000287 => x"650526f7", |
00000288 => x"e4050513", |
00000289 => x"73c000ef", |
00000290 => x"65050485", |
00000291 => x"051357fd", |
00000292 => x"a423ec85", |
00000293 => x"00ef82f1", |
00000294 => x"07b772a0", |
00000295 => x"87938000", |
00000296 => x"80e70807", |
00000297 => x"a7030007", |
00000298 => x"47898281", |
00000299 => x"24f71363", |
00000300 => x"05136505", |
00000301 => x"00efd785", |
00000302 => x"090565e0", |
00000303 => x"05136505", |
00000304 => x"a423e285", |
00000305 => x"00ef8201", |
00000306 => x"007364e0", |
00000307 => x"a7030000", |
00000308 => x"27b78281", |
00000309 => x"87935566", |
00000310 => x"11632447", |
00000311 => x"650516f7", |
00000312 => x"d7850513", |
00000313 => x"630000ef", |
00000314 => x"65050905", |
00000315 => x"e3850513", |
00000316 => x"8201a423", |
00000317 => x"620000ef", |
00000318 => x"34446073", |
00000319 => x"00010001", |
00000320 => x"8281a703", |
00000321 => x"cdece7b7", |
00000322 => x"ea978793", |
00000323 => x"12f71f63", |
00000324 => x"05136505", |
00000325 => x"00efd785", |
00000326 => x"09055fe0", |
00000327 => x"05136505", |
00000328 => x"a423e485", |
00000329 => x"00ef8201", |
00000330 => x"45015ee0", |
00000331 => x"00ef4581", |
00000332 => x"00014d00", |
00000333 => x"00010001", |
00000334 => x"a7030001", |
00000335 => x"07b78281", |
00000336 => x"87930013", |
00000337 => x"1963a537", |
00000338 => x"650510f7", |
00000339 => x"d7850513", |
00000340 => x"5c4000ef", |
00000341 => x"65050905", |
00000342 => x"e5850513", |
00000343 => x"8201a423", |
00000344 => x"5b4000ef", |
00000345 => x"00ef4501", |
00000346 => x"09ad7600", |
00000347 => x"00010001", |
00000348 => x"00010001", |
00000349 => x"8281a703", |
00000350 => x"eef337b7", |
00000351 => x"08878793", |
00000352 => x"0ef71363", |
00000353 => x"05136505", |
00000354 => x"00efd785", |
00000355 => x"090558a0", |
00000356 => x"86a26505", |
00000357 => x"85ce864a", |
00000358 => x"e6850513", |
00000359 => x"8201a423", |
00000360 => x"574000ef", |
00000361 => x"0c041863", |
00000362 => x"05136505", |
00000363 => x"b335e8c5", |
00000364 => x"05136505", |
00000365 => x"00efd785", |
00000366 => x"490555e0", |
00000367 => x"6505bbad", |
00000368 => x"d7050513", |
00000369 => x"550000ef", |
00000370 => x"b3550405", |
00000371 => x"05136505", |
00000372 => x"00efd8c5", |
00000373 => x"49855420", |
00000374 => x"6505bb71", |
00000375 => x"d7050513", |
00000376 => x"534000ef", |
00000377 => x"bb6d0405", |
00000378 => x"05136505", |
00000379 => x"00efd705", |
00000380 => x"04055260", |
00000381 => x"6505b3cd", |
00000382 => x"d7050513", |
00000383 => x"518000ef", |
00000384 => x"b5010405", |
00000385 => x"05136505", |
00000386 => x"00efd705", |
00000387 => x"040550a0", |
00000388 => x"6505b505", |
00000389 => x"d7050513", |
00000390 => x"4fc000ef", |
00000391 => x"b5890405", |
00000392 => x"05136505", |
00000393 => x"00efd705", |
00000394 => x"04054ee0", |
00000395 => x"6505b58d", |
00000396 => x"d7050513", |
00000397 => x"4e0000ef", |
00000398 => x"b5490405", |
00000399 => x"05136505", |
00000400 => x"00efd705", |
00000401 => x"04054d20", |
00000402 => x"6505b54d", |
00000403 => x"d7050513", |
00000404 => x"4c4000ef", |
00000405 => x"b5d90405", |
00000406 => x"05136505", |
00000407 => x"00efd705", |
00000408 => x"04054b60", |
00000409 => x"6505bdcd", |
00000410 => x"d7050513", |
00000411 => x"4a8000ef", |
00000412 => x"bf390405", |
00000413 => x"05136505", |
00000414 => x"b185e985", |
00000415 => x"123457b7", |
00000416 => x"67878793", |
00000417 => x"82f1a423", |
00000418 => x"17b78082", |
00000419 => x"8793aabb", |
00000420 => x"a4231337", |
00000421 => x"808282f1", |
00000422 => x"019927b7", |
00000423 => x"03b78793", |
00000424 => x"82f1a423", |
00000425 => x"27b78082", |
00000426 => x"87931232", |
00000427 => x"a4233307", |
00000428 => x"808282f1", |
00000429 => x"babcd7b7", |
00000430 => x"ccc78793", |
00000431 => x"82f1a423", |
00000432 => x"37b78082", |
00000433 => x"8793def7", |
00000434 => x"a4238aa7", |
00000435 => x"808282f1", |
00000436 => x"ff0927b7", |
00000437 => x"7dd78793", |
00000438 => x"82f1a423", |
00000439 => x"17b78082", |
00000440 => x"87932009", |
00000441 => x"a4237777", |
00000442 => x"808282f1", |
00000443 => x"556627b7", |
00000444 => x"24478793", |
00000445 => x"82f1a423", |
00000446 => x"e7b78082", |
00000447 => x"8793cdec", |
00000448 => x"a423ea97", |
00000449 => x"808282f1", |
00000450 => x"eef337b7", |
00000451 => x"08878793", |
00000452 => x"82f1a423", |
00000453 => x"07b78082", |
00000454 => x"87930013", |
00000455 => x"557da537", |
00000456 => x"a42355fd", |
00000457 => x"ace182f1", |
00000458 => x"6505c509", |
00000459 => x"ea850513", |
00000460 => x"6505a6d5", |
00000461 => x"eb050513", |
00000462 => x"1141bfe5", |
00000463 => x"c226c422", |
00000464 => x"479dc606", |
00000465 => x"84ae842a", |
00000466 => x"02a7f363", |
00000467 => x"006347ad", |
00000468 => x"47cd02f5", |
00000469 => x"00f50b63", |
00000470 => x"056347dd", |
00000471 => x"47ed02f5", |
00000472 => x"1c634505", |
00000473 => x"452d00f4", |
00000474 => x"450da011", |
00000475 => x"2573297d", |
00000476 => x"040afc50", |
00000477 => x"c004942a", |
00000478 => x"40b24501", |
00000479 => x"44924422", |
00000480 => x"80820141", |
00000481 => x"b7dd451d", |
00000482 => x"71796505", |
00000483 => x"eb850513", |
00000484 => x"d422d606", |
00000485 => x"d04ad226", |
00000486 => x"cc52ce4e", |
00000487 => x"c85aca56", |
00000488 => x"65052e95", |
00000489 => x"eec50513", |
00000490 => x"25f326b5", |
00000491 => x"6505f140", |
00000492 => x"f0c50513", |
00000493 => x"65052685", |
00000494 => x"f2450513", |
00000495 => x"29732ea1", |
00000496 => x"4b01f130", |
00000497 => x"4a2559e1", |
00000498 => x"44914a8d", |
00000499 => x"033b0433", |
00000500 => x"04614501", |
00000501 => x"00895433", |
00000502 => x"0ff47413", |
00000503 => x"1c8a6f63", |
00000504 => x"0513c511", |
00000505 => x"75130305", |
00000506 => x"26210ff5", |
00000507 => x"03040513", |
00000508 => x"0ff57513", |
00000509 => x"05632cfd", |
00000510 => x"0513015b", |
00000511 => x"2cd502e0", |
00000512 => x"15e30b05", |
00000513 => x"25f3fc9b", |
00000514 => x"6505f130", |
00000515 => x"f3850513", |
00000516 => x"65052611", |
00000517 => x"f4450513", |
00000518 => x"27f32cf5", |
00000519 => x"83f93010", |
00000520 => x"1a079463", |
00000521 => x"05136505", |
00000522 => x"24edf585", |
00000523 => x"05136505", |
00000524 => x"24cdf785", |
00000525 => x"301025f3", |
00000526 => x"49054401", |
00000527 => x"17b344e9", |
00000528 => x"8fed0089", |
00000529 => x"0513cb99", |
00000530 => x"75130414", |
00000531 => x"c62e0ff5", |
00000532 => x"0513244d", |
00000533 => x"2c710200", |
00000534 => x"040545b2", |
00000535 => x"fe9411e3", |
00000536 => x"05136505", |
00000537 => x"247df8c5", |
00000538 => x"05136505", |
00000539 => x"245df945", |
00000540 => x"fc002573", |
00000541 => x"02057513", |
00000542 => x"25f33d45", |
00000543 => x"6505fc10", |
00000544 => x"fa850513", |
00000545 => x"65052c41", |
00000546 => x"fc450513", |
00000547 => x"25f32461", |
00000548 => x"2673fc60", |
00000549 => x"6505fc40", |
00000550 => x"fe450513", |
00000551 => x"65052ca5", |
00000552 => x"00c50513", |
00000553 => x"25732c85", |
00000554 => x"8911fc00", |
00000555 => x"65053db5", |
00000556 => x"02450513", |
00000557 => x"25732485", |
00000558 => x"8921fc00", |
00000559 => x"25f335b5", |
00000560 => x"2673fc70", |
00000561 => x"6505fc50", |
00000562 => x"03c50513", |
00000563 => x"650524a1", |
00000564 => x"06450513", |
00000565 => x"25732481", |
00000566 => x"8941fc00", |
00000567 => x"650535b1", |
00000568 => x"07c50513", |
00000569 => x"25732c05", |
00000570 => x"8905fc00", |
00000571 => x"65053d35", |
00000572 => x"09450513", |
00000573 => x"25732405", |
00000574 => x"8909fc00", |
00000575 => x"65053535", |
00000576 => x"0ac50513", |
00000577 => x"24732c01", |
00000578 => x"6505fc00", |
00000579 => x"0c050513", |
00000580 => x"65412411", |
00000581 => x"3d098d61", |
00000582 => x"05136505", |
00000583 => x"2add0cc5", |
00000584 => x"00020537", |
00000585 => x"35098d61", |
00000586 => x"05136505", |
00000587 => x"22dd0d85", |
00000588 => x"00040537", |
00000589 => x"3bcd8d61", |
00000590 => x"05136505", |
00000591 => x"2ad90e45", |
00000592 => x"00080537", |
00000593 => x"33cd8d61", |
00000594 => x"05136505", |
00000595 => x"22d90f05", |
00000596 => x"00100537", |
00000597 => x"3bc98d61", |
00000598 => x"05136505", |
00000599 => x"2a5d0fc5", |
00000600 => x"00200537", |
00000601 => x"33c98d61", |
00000602 => x"05136505", |
00000603 => x"225d1085", |
00000604 => x"00400537", |
00000605 => x"3b4d8d61", |
00000606 => x"05136505", |
00000607 => x"2a591145", |
00000608 => x"00800537", |
00000609 => x"334d8d61", |
00000610 => x"05136505", |
00000611 => x"22591205", |
00000612 => x"01000537", |
00000613 => x"3b498d61", |
00000614 => x"05136505", |
00000615 => x"2a9d12c5", |
00000616 => x"02000537", |
00000617 => x"54228d61", |
00000618 => x"549250b2", |
00000619 => x"49f25902", |
00000620 => x"4ad24a62", |
00000621 => x"61454b42", |
00000622 => x"1459bb85", |
00000623 => x"74130505", |
00000624 => x"75130ff4", |
00000625 => x"bd190ff5", |
00000626 => x"89634705", |
00000627 => x"470900e7", |
00000628 => x"00e79a63", |
00000629 => x"05136505", |
00000630 => x"bd81f705", |
00000631 => x"05136505", |
00000632 => x"b5a1f605", |
00000633 => x"05136505", |
00000634 => x"b581f685", |
00000635 => x"05136505", |
00000636 => x"a2191385", |
00000637 => x"fc002573", |
00000638 => x"89058145", |
00000639 => x"06938082", |
00000640 => x"567df980", |
00000641 => x"c288c290", |
00000642 => x"8082c2cc", |
00000643 => x"68051141", |
00000644 => x"00058523", |
00000645 => x"00544781", |
00000646 => x"1ac80813", |
00000647 => x"76334729", |
00000648 => x"88b302e5", |
00000649 => x"078500f6", |
00000650 => x"46039642", |
00000651 => x"55330006", |
00000652 => x"802302e5", |
00000653 => x"94e300c8", |
00000654 => x"8636fee7", |
00000655 => x"05134725", |
00000656 => x"48030300", |
00000657 => x"87ba0096", |
00000658 => x"0742177d", |
00000659 => x"17638341", |
00000660 => x"04a300a8", |
00000661 => x"167d0006", |
00000662 => x"4781f76d", |
00000663 => x"470197b6", |
00000664 => x"0007c603", |
00000665 => x"0513ca09", |
00000666 => x"972e0017", |
00000667 => x"00c70023", |
00000668 => x"01051713", |
00000669 => x"86138341", |
00000670 => x"9763fff7", |
00000671 => x"95ba00f6", |
00000672 => x"00058023", |
00000673 => x"80820141", |
00000674 => x"bfd987b2", |
00000675 => x"fc002573", |
00000676 => x"89058149", |
00000677 => x"20238082", |
00000678 => x"26f3fa00", |
00000679 => x"4701fc10", |
00000680 => x"f5630506", |
00000681 => x"668502a6", |
00000682 => x"16f94781", |
00000683 => x"02e6e763", |
00000684 => x"89858a05", |
00000685 => x"067a07e2", |
00000686 => x"05f68fd1", |
00000687 => x"8fd98fcd", |
00000688 => x"10000737", |
00000689 => x"20238fd9", |
00000690 => x"8082faf0", |
00000691 => x"00170793", |
00000692 => x"01079713", |
00000693 => x"83418e89", |
00000694 => x"8513b7e9", |
00000695 => x"7513ffe7", |
00000696 => x"e5110fd5", |
00000697 => x"0785830d", |
00000698 => x"0ff7f793", |
00000699 => x"8305b7c1", |
00000700 => x"2e23bfdd", |
00000701 => x"8082fea0", |
00000702 => x"46b54729", |
00000703 => x"00054783", |
00000704 => x"e3910505", |
00000705 => x"94638082", |
00000706 => x"2e2300e7", |
00000707 => x"2e23fed0", |
00000708 => x"b7edfef0", |
00000709 => x"d422715d", |
00000710 => x"6405c2be", |
00000711 => x"d226185c", |
00000712 => x"cc52ce4e", |
00000713 => x"c85aca56", |
00000714 => x"d04ad606", |
00000715 => x"dc32da2e", |
00000716 => x"c0bade36", |
00000717 => x"c6c6c4c2", |
00000718 => x"0993c03e", |
00000719 => x"4a290250", |
00000720 => x"04934ab5", |
00000721 => x"0b130730", |
00000722 => x"04130750", |
00000723 => x"47831b84", |
00000724 => x"c39d0005", |
00000725 => x"0d379463", |
00000726 => x"00154783", |
00000727 => x"00250913", |
00000728 => x"06978563", |
00000729 => x"02f4e463", |
00000730 => x"06300713", |
00000731 => x"06e78763", |
00000732 => x"06900713", |
00000733 => x"06e78c63", |
00000734 => x"542250b2", |
00000735 => x"59025492", |
00000736 => x"4a6249f2", |
00000737 => x"4b424ad2", |
00000738 => x"80826161", |
00000739 => x"09678163", |
00000740 => x"07800713", |
00000741 => x"fee792e3", |
00000742 => x"00544782", |
00000743 => x"438c8536", |
00000744 => x"00478713", |
00000745 => x"0613c03a", |
00000746 => x"47010200", |
00000747 => x"00e5d7b3", |
00000748 => x"97a28bbd", |
00000749 => x"0007c783", |
00000750 => x"16fd0711", |
00000751 => x"00f68423", |
00000752 => x"fec716e3", |
00000753 => x"00010623", |
00000754 => x"4782a031", |
00000755 => x"87134388", |
00000756 => x"c03a0047", |
00000757 => x"854a3715", |
00000758 => x"4782bf9d", |
00000759 => x"00478713", |
00000760 => x"0007c783", |
00000761 => x"2e23c03a", |
00000762 => x"b7f5fef0", |
00000763 => x"43884782", |
00000764 => x"00478713", |
00000765 => x"5863c03a", |
00000766 => x"07930005", |
00000767 => x"053302d0", |
00000768 => x"2e2340a0", |
00000769 => x"004cfef0", |
00000770 => x"00483511", |
00000771 => x"4782b7e1", |
00000772 => x"8713004c", |
00000773 => x"43880047", |
00000774 => x"b7fdc03a", |
00000775 => x"01479463", |
00000776 => x"ff502e23", |
00000777 => x"00150913", |
00000778 => x"7693bf7d", |
00000779 => x"470d0fb5", |
00000780 => x"866387aa", |
00000781 => x"472d00e6", |
00000782 => x"98634505", |
00000783 => x"450500e7", |
00000784 => x"00f517b3", |
00000785 => x"3047a073", |
00000786 => x"80824501", |
00000787 => x"f8800713", |
00000788 => x"e693431c", |
00000789 => x"c3140087", |
00000790 => x"078a8b8d", |
00000791 => x"80818713", |
00000792 => x"a30397ba", |
00000793 => x"83020007", |
00000794 => x"fc002573", |
00000795 => x"8905815d", |
00000796 => x"479d8082", |
00000797 => x"00a7fa63", |
00000798 => x"80824505", |
00000799 => x"40b24505", |
00000800 => x"44924422", |
00000801 => x"80820141", |
00000802 => x"c2261141", |
00000803 => x"658584ae", |
00000804 => x"8593c422", |
00000805 => x"842ac4c5", |
00000806 => x"c606456d", |
00000807 => x"a9fff0ef", |
00000808 => x"1713fd71", |
00000809 => x"87930024", |
00000810 => x"97ba8081", |
00000811 => x"2703c384", |
00000812 => x"0421f880", |
00000813 => x"97b34785", |
00000814 => x"8fd90087", |
00000815 => x"0107e793", |
00000816 => x"f8f02423", |
00000817 => x"479dbf6d", |
00000818 => x"00a7ed63", |
00000819 => x"f8802783", |
00000820 => x"8d5d0542", |
00000821 => x"000807b7", |
00000822 => x"24238d5d", |
00000823 => x"4501f8a0", |
00000824 => x"45058082", |
00000825 => x"00008082", |
00000826 => x"2d2d0a0a", |
00000827 => x"2d2d2d2d", |
00000828 => x"55504320", |
00000829 => x"53455420", |
00000830 => x"2d2d2054", |
00000831 => x"2d2d2d2d", |
00000832 => x"00000a0a", |
00000833 => x"454e0a0a", |
00000834 => x"3356524f", |
00000835 => x"78652032", |
00000836 => x"74706563", |
00000837 => x"736e6f69", |
00000838 => x"646e6120", |
00000839 => x"746e6920", |
00000840 => x"75727265", |
00000841 => x"20737470", |
00000842 => x"74736574", |
00000843 => x"6f727020", |
00000844 => x"6d617267", |
00000845 => x"00000a0a", |
00000846 => x"74736e69", |
00000847 => x"206c6c61", |
00000848 => x"6f727265", |
00000849 => x"000a2172", |
00000850 => x"43494c43", |
00000851 => x"736e6920", |
00000852 => x"6c6c6174", |
00000853 => x"72726520", |
00000854 => x"0a21726f", |
00000855 => x"00000000", |
00000856 => x"434e4546", |
00000857 => x"492e2845", |
00000858 => x"20203a29", |
00000859 => x"00000020", |
00000860 => x"6c696166", |
00000861 => x"0000000a", |
00000862 => x"000a6b6f", |
00000863 => x"20435845", |
00000864 => x"4c415f49", |
00000865 => x"3a4e4749", |
00000866 => x"00000020", |
00000867 => x"70696b73", |
00000868 => x"20646570", |
00000869 => x"746f6e28", |
00000870 => x"736f7020", |
00000871 => x"6c626973", |
00000872 => x"68772065", |
00000873 => x"43206e65", |
00000874 => x"5458452d", |
00000875 => x"616e6520", |
00000876 => x"64656c62", |
00000877 => x"00000a29", |
00000878 => x"20435845", |
00000879 => x"43415f49", |
00000880 => x"20203a43", |
00000881 => x"00000020", |
00000882 => x"20435845", |
00000883 => x"4c495f49", |
00000884 => x"3a47454c", |
00000885 => x"00000020", |
00000886 => x"20435845", |
00000887 => x"41455242", |
00000888 => x"20203a4b", |
00000889 => x"00000020", |
00000890 => x"20435845", |
00000891 => x"4c415f4c", |
00000892 => x"3a4e4749", |
00000893 => x"00000020", |
00000894 => x"20435845", |
00000895 => x"43415f4c", |
00000896 => x"20203a43", |
00000897 => x"00000020", |
00000898 => x"20435845", |
00000899 => x"4c415f53", |
00000900 => x"3a4e4749", |
00000901 => x"00000020", |
00000902 => x"20435845", |
00000903 => x"43415f53", |
00000904 => x"20203a43", |
00000905 => x"00000020", |
00000906 => x"20435845", |
00000907 => x"43564e45", |
00000908 => x"3a4c4c41", |
00000909 => x"00000020", |
00000910 => x"20515249", |
00000911 => x"3a49534d", |
00000912 => x"20202020", |
00000913 => x"00000020", |
00000914 => x"20515249", |
00000915 => x"3a49544d", |
00000916 => x"20202020", |
00000917 => x"00000020", |
00000918 => x"20515249", |
00000919 => x"3a49454d", |
00000920 => x"20202020", |
00000921 => x"00000020", |
00000922 => x"65540a0a", |
00000923 => x"3a737473", |
00000924 => x"0a692520", |
00000925 => x"203a4b4f", |
00000926 => x"25202020", |
00000927 => x"41460a69", |
00000928 => x"203a4c49", |
00000929 => x"0a692520", |
00000930 => x"0000000a", |
00000931 => x"54534554", |
00000932 => x"214b4f20", |
00000933 => x"0000000a", |
00000934 => x"54534554", |
00000935 => x"49414620", |
00000936 => x"2144454c", |
00000937 => x"0000000a", |
00000938 => x"65757254", |
00000939 => x"0000000a", |
00000940 => x"736c6146", |
00000941 => x"00000a65", |
00000942 => x"3c3c0a0a", |
00000943 => x"4f454e20", |
00000944 => x"32335652", |
00000945 => x"72614820", |
00000946 => x"72617764", |
00000947 => x"6f432065", |
00000948 => x"6769666e", |
00000949 => x"74617275", |
00000950 => x"206e6f69", |
00000951 => x"7265764f", |
00000952 => x"77656976", |
00000953 => x"0a3e3e20", |
00000954 => x"00000000", |
00000955 => x"202d2d0a", |
00000956 => x"746e6543", |
00000957 => x"206c6172", |
00000958 => x"636f7250", |
00000959 => x"69737365", |
00000960 => x"5520676e", |
00000961 => x"2074696e", |
00000962 => x"000a2d2d", |
00000963 => x"74726148", |
00000964 => x"3a444920", |
00000965 => x"20202020", |
00000966 => x"20202020", |
00000967 => x"78302020", |
00000968 => x"000a7825", |
00000969 => x"64726148", |
00000970 => x"65726177", |
00000971 => x"72657620", |
00000972 => x"6e6f6973", |
00000973 => x"0000203a", |
00000974 => x"78302820", |
00000975 => x"0a297825", |
00000976 => x"00000000", |
00000977 => x"68637241", |
00000978 => x"63657469", |
00000979 => x"65727574", |
00000980 => x"2020203a", |
00000981 => x"00002020", |
00000982 => x"6e6b6e75", |
00000983 => x"006e776f", |
00000984 => x"32335652", |
00000985 => x"00000000", |
00000986 => x"32315652", |
00000987 => x"00000038", |
00000988 => x"34365652", |
00000989 => x"00000000", |
00000990 => x"5550430a", |
00000991 => x"74786520", |
00000992 => x"69736e65", |
00000993 => x"3a736e6f", |
00000994 => x"00202020", |
00000995 => x"25783028", |
00000996 => x"000a2978", |
00000997 => x"20544e43", |
00000998 => x"69742026", |
00000999 => x"4320656d", |
00001000 => x"3a735253", |
00001001 => x"00002020", |
00001002 => x"636f6c43", |
00001003 => x"7073206b", |
00001004 => x"3a646565", |
00001005 => x"20202020", |
00001006 => x"75252020", |
00001007 => x"0a7a4820", |
00001008 => x"00000000", |
00001009 => x"202d2d0a", |
00001010 => x"6f6d654d", |
00001011 => x"43207972", |
00001012 => x"69666e6f", |
00001013 => x"61727567", |
00001014 => x"6e6f6974", |
00001015 => x"0a2d2d20", |
00001016 => x"00000000", |
00001017 => x"74736e49", |
00001018 => x"74637572", |
00001019 => x"206e6f69", |
00001020 => x"6f6d656d", |
00001021 => x"203a7972", |
00001022 => x"75252020", |
00001023 => x"74796220", |
00001024 => x"40207365", |
00001025 => x"25783020", |
00001026 => x"00000a78", |
00001027 => x"65746e49", |
00001028 => x"6c616e72", |
00001029 => x"454d4920", |
00001030 => x"20203a4d", |
00001031 => x"20202020", |
00001032 => x"00002020", |
00001033 => x"65746e49", |
00001034 => x"6c616e72", |
00001035 => x"454d4920", |
00001036 => x"7361204d", |
00001037 => x"4d4f5220", |
00001038 => x"0000203a", |
00001039 => x"61746144", |
00001040 => x"6d656d20", |
00001041 => x"3a79726f", |
00001042 => x"20202020", |
00001043 => x"20202020", |
00001044 => x"75252020", |
00001045 => x"74796220", |
00001046 => x"40207365", |
00001047 => x"25783020", |
00001048 => x"00000a78", |
00001049 => x"65746e49", |
00001050 => x"6c616e72", |
00001051 => x"454d4420", |
00001052 => x"20203a4d", |
00001053 => x"20202020", |
00001054 => x"00002020", |
00001055 => x"746f6f42", |
00001056 => x"64616f6c", |
00001057 => x"203a7265", |
00001058 => x"20202020", |
00001059 => x"20202020", |
00001060 => x"00002020", |
00001061 => x"65747845", |
00001062 => x"6c616e72", |
00001063 => x"746e6920", |
00001064 => x"61667265", |
00001065 => x"203a6563", |
00001066 => x"00002020", |
00001067 => x"202d2d0a", |
00001068 => x"69726550", |
00001069 => x"72656870", |
00001070 => x"20736c61", |
00001071 => x"000a2d2d", |
00001072 => x"4f495047", |
00001073 => x"2020203a", |
00001074 => x"00000020", |
00001075 => x"4d49544d", |
00001076 => x"20203a45", |
00001077 => x"00000020", |
00001078 => x"54524155", |
00001079 => x"2020203a", |
00001080 => x"00000020", |
00001081 => x"3a495053", |
00001082 => x"20202020", |
00001083 => x"00000020", |
00001084 => x"3a495754", |
00001085 => x"20202020", |
00001086 => x"00000020", |
00001087 => x"3a4d5750", |
00001088 => x"20202020", |
00001089 => x"00000020", |
00001090 => x"3a544457", |
00001091 => x"20202020", |
00001092 => x"00000020", |
00001093 => x"43494c43", |
00001094 => x"2020203a", |
00001095 => x"00000020", |
00001096 => x"474e5254", |
00001097 => x"2020203a", |
00001098 => x"00000020", |
00001099 => x"4e564544", |
00001100 => x"3a4c4c55", |
00001101 => x"00000020", |
00001102 => x"68540a0a", |
00001103 => x"454e2065", |
00001104 => x"3356524f", |
00001105 => x"72502032", |
00001106 => x"7365636f", |
00001107 => x"20726f73", |
00001108 => x"6a6f7250", |
00001109 => x"0a746365", |
00001110 => x"53207962", |
00001111 => x"68706574", |
00001112 => x"4e206e61", |
00001113 => x"69746c6f", |
00001114 => x"680a676e", |
00001115 => x"73707474", |
00001116 => x"672f2f3a", |
00001117 => x"75687469", |
00001118 => x"6f632e62", |
00001119 => x"74732f6d", |
00001120 => x"746c6f6e", |
00001121 => x"2f676e69", |
00001122 => x"726f656e", |
00001123 => x"0a323376", |
00001124 => x"6564616d", |
00001125 => x"206e6920", |
00001126 => x"6e6e6148", |
00001127 => x"7265766f", |
00001128 => x"6547202c", |
00001129 => x"6e616d72", |
00001130 => x"000a0a79", |
00001131 => x"33323130", |
00001132 => x"37363534", |
00001133 => x"00003938", |
00001134 => x"33323130", |
00001135 => x"37363534", |
00001136 => x"62613938", |
00001137 => x"66656463", |
00001138 => x"dead007f", |
00001139 => x"00008067", |
00000301 => x"00efe405", |
00000302 => x"048570a0", |
00000303 => x"57fd6505", |
00000304 => x"ed850513", |
00000305 => x"82f1a423", |
00000306 => x"6f8000ef", |
00000307 => x"a7039002", |
00000308 => x"478d8281", |
00000309 => x"22f71663", |
00000310 => x"05136505", |
00000311 => x"00efe405", |
00000312 => x"04856e20", |
00000313 => x"57fd6505", |
00000314 => x"ee850513", |
00000315 => x"82f1a423", |
00000316 => x"6d0000ef", |
00000317 => x"00202003", |
00000318 => x"8281a703", |
00000319 => x"18634791", |
00000320 => x"650520f7", |
00000321 => x"e4050513", |
00000322 => x"6b8000ef", |
00000323 => x"65050485", |
00000324 => x"051357fd", |
00000325 => x"a423ef85", |
00000326 => x"00ef82f1", |
00000327 => x"27836a60", |
00000328 => x"c63ef000", |
00000329 => x"8281a703", |
00000330 => x"19634795", |
00000331 => x"65051ef7", |
00000332 => x"e4050513", |
00000333 => x"68c000ef", |
00000334 => x"65050485", |
00000335 => x"051357fd", |
00000336 => x"a423f085", |
00000337 => x"00ef82f1", |
00000338 => x"212367a0", |
00000339 => x"a7030000", |
00000340 => x"47998281", |
00000341 => x"1cf71b63", |
00000342 => x"05136505", |
00000343 => x"00efe405", |
00000344 => x"04856620", |
00000345 => x"57fd6505", |
00000346 => x"f1850513", |
00000347 => x"82f1a423", |
00000348 => x"650000ef", |
00000349 => x"f0002023", |
00000350 => x"8281a703", |
00000351 => x"1d63479d", |
00000352 => x"65051af7", |
00000353 => x"e4050513", |
00000354 => x"638000ef", |
00000355 => x"65050485", |
00000356 => x"051357fd", |
00000357 => x"a423f285", |
00000358 => x"00ef82f1", |
00000359 => x"00736260", |
00000360 => x"a7030000", |
00000361 => x"47ad8281", |
00000362 => x"18f71f63", |
00000363 => x"05136505", |
00000364 => x"00efe405", |
00000365 => x"048560e0", |
00000366 => x"57fd6505", |
00000367 => x"f3850513", |
00000368 => x"82f1a423", |
00000369 => x"5fc000ef", |
00000370 => x"45814501", |
00000371 => x"4de000ef", |
00000372 => x"00010001", |
00000373 => x"00010001", |
00000374 => x"8281a703", |
00000375 => x"800007b7", |
00000376 => x"1863079d", |
00000377 => x"650516f7", |
00000378 => x"e4050513", |
00000379 => x"5d4000ef", |
00000380 => x"55fd0485", |
00000381 => x"00ef557d", |
00000382 => x"65054b40", |
00000383 => x"051357fd", |
00000384 => x"a423f485", |
00000385 => x"00ef82f1", |
00000386 => x"45015ba0", |
00000387 => x"76e000ef", |
00000388 => x"00010001", |
00000389 => x"00010001", |
00000390 => x"8281a703", |
00000391 => x"800007b7", |
00000392 => x"1e6307ad", |
00000393 => x"650512f7", |
00000394 => x"e4050513", |
00000395 => x"594000ef", |
00000396 => x"65050485", |
00000397 => x"051357fd", |
00000398 => x"a423f585", |
00000399 => x"00ef82f1", |
00000400 => x"21a95820", |
00000401 => x"051387aa", |
00000402 => x"37b33e85", |
00000403 => x"95be00f5", |
00000404 => x"29a109ad", |
00000405 => x"10500073", |
00000406 => x"8281a703", |
00000407 => x"800007b7", |
00000408 => x"0463079d", |
00000409 => x"650510f7", |
00000410 => x"e4450513", |
00000411 => x"554000ef", |
00000412 => x"65050405", |
00000413 => x"862686a2", |
00000414 => x"051385ce", |
00000415 => x"00eff685", |
00000416 => x"1a635420", |
00000417 => x"65050e04", |
00000418 => x"f8c50513", |
00000419 => x"6505b1a9", |
00000420 => x"e4450513", |
00000421 => x"52c000ef", |
00000422 => x"44054481", |
00000423 => x"6505b1dd", |
00000424 => x"e4450513", |
00000425 => x"51c000ef", |
00000426 => x"bb310405", |
00000427 => x"05136505", |
00000428 => x"00efe445", |
00000429 => x"040550e0", |
00000430 => x"6505b399", |
00000431 => x"e4050513", |
00000432 => x"500000ef", |
00000433 => x"b3950485", |
00000434 => x"05136505", |
00000435 => x"00efe445", |
00000436 => x"04054f20", |
00000437 => x"6505b361", |
00000438 => x"e8c50513", |
00000439 => x"4e4000ef", |
00000440 => x"bbb54991", |
00000441 => x"05136505", |
00000442 => x"00efe445", |
00000443 => x"04054d60", |
00000444 => x"6505bb69", |
00000445 => x"e4450513", |
00000446 => x"4c8000ef", |
00000447 => x"bb7d0405", |
00000448 => x"05136505", |
00000449 => x"00efe445", |
00000450 => x"04054ba0", |
00000451 => x"6505bbe1", |
00000452 => x"e4450513", |
00000453 => x"4ac000ef", |
00000454 => x"bbd50405", |
00000455 => x"05136505", |
00000456 => x"00efe445", |
00000457 => x"040549e0", |
00000458 => x"6505bd09", |
00000459 => x"e4450513", |
00000460 => x"490000ef", |
00000461 => x"b53d0405", |
00000462 => x"05136505", |
00000463 => x"00efe445", |
00000464 => x"04054820", |
00000465 => x"6505b5a9", |
00000466 => x"e4450513", |
00000467 => x"04052995", |
00000468 => x"6505b5a5", |
00000469 => x"e4450513", |
00000470 => x"040521a5", |
00000471 => x"6505bd59", |
00000472 => x"e4450513", |
00000473 => x"040529b1", |
00000474 => x"6505b5e9", |
00000475 => x"e4050513", |
00000476 => x"04852981", |
00000477 => x"6505bdfd", |
00000478 => x"f9850513", |
00000479 => x"2773bea9", |
00000480 => x"a4233420", |
00000481 => x"808282e1", |
00000482 => x"6505c509", |
00000483 => x"fa850513", |
00000484 => x"6505a905", |
00000485 => x"fb050513", |
00000486 => x"1141bfe5", |
00000487 => x"c226c422", |
00000488 => x"479dc606", |
00000489 => x"84ae842a", |
00000490 => x"02a7f363", |
00000491 => x"006347ad", |
00000492 => x"47cd02f5", |
00000493 => x"00f50b63", |
00000494 => x"056347dd", |
00000495 => x"47ed02f5", |
00000496 => x"1c634505", |
00000497 => x"452d00f4", |
00000498 => x"450da011", |
00000499 => x"25032329", |
00000500 => x"040aff40", |
00000501 => x"c004942a", |
00000502 => x"40b24501", |
00000503 => x"44924422", |
00000504 => x"80820141", |
00000505 => x"b7dd451d", |
00000506 => x"ce061101", |
00000507 => x"ca26cc22", |
00000508 => x"c64ec84a", |
00000509 => x"c256c452", |
00000510 => x"2973c05a", |
00000511 => x"4b01f130", |
00000512 => x"4a2559e1", |
00000513 => x"44914a8d", |
00000514 => x"033b0433", |
00000515 => x"04614501", |
00000516 => x"00895433", |
00000517 => x"0ff47413", |
00000518 => x"028a6f63", |
00000519 => x"0513c511", |
00000520 => x"75130305", |
00000521 => x"2ea50ff5", |
00000522 => x"03040513", |
00000523 => x"0ff57513", |
00000524 => x"056326bd", |
00000525 => x"0513015b", |
00000526 => x"269502e0", |
00000527 => x"15e30b05", |
00000528 => x"40f2fc9b", |
00000529 => x"44d24462", |
00000530 => x"49b24942", |
00000531 => x"4a924a22", |
00000532 => x"61054b02", |
00000533 => x"14598082", |
00000534 => x"74130505", |
00000535 => x"75130ff4", |
00000536 => x"bf5d0ff5", |
00000537 => x"11016505", |
00000538 => x"fb850513", |
00000539 => x"cc22ce06", |
00000540 => x"c84aca26", |
00000541 => x"650526b1", |
00000542 => x"fec50513", |
00000543 => x"25f32691", |
00000544 => x"6505f140", |
00000545 => x"00c50513", |
00000546 => x"25832e25", |
00000547 => x"6505fe40", |
00000548 => x"02450513", |
00000549 => x"65052635", |
00000550 => x"03c50513", |
00000551 => x"37a92615", |
00000552 => x"f13025f3", |
00000553 => x"05136505", |
00000554 => x"2e190505", |
00000555 => x"05136505", |
00000556 => x"263905c5", |
00000557 => x"301027f3", |
00000558 => x"906383f9", |
00000559 => x"65051807", |
00000560 => x"07050513", |
00000561 => x"65052cf5", |
00000562 => x"09050513", |
00000563 => x"25f32cd5", |
00000564 => x"44013010", |
00000565 => x"44e94905", |
00000566 => x"008917b3", |
00000567 => x"cb998fed", |
00000568 => x"04140513", |
00000569 => x"0ff57513", |
00000570 => x"2c55c62e", |
00000571 => x"02000513", |
00000572 => x"45b2247d", |
00000573 => x"11e30405", |
00000574 => x"6505fe94", |
00000575 => x"0a450513", |
00000576 => x"258324c1", |
00000577 => x"6505fe00", |
00000578 => x"0ac50513", |
00000579 => x"65052c55", |
00000580 => x"0c850513", |
00000581 => x"25832475", |
00000582 => x"2603ff80", |
00000583 => x"6505ff00", |
00000584 => x"0e850513", |
00000585 => x"65052c71", |
00000586 => x"11050513", |
00000587 => x"25032c51", |
00000588 => x"8911fe80", |
00000589 => x"65053d91", |
00000590 => x"12850513", |
00000591 => x"25032451", |
00000592 => x"8921fe80", |
00000593 => x"25833591", |
00000594 => x"2603ffc0", |
00000595 => x"6505ff40", |
00000596 => x"14050513", |
00000597 => x"650524b5", |
00000598 => x"16850513", |
00000599 => x"25032495", |
00000600 => x"8941fe80", |
00000601 => x"65053515", |
00000602 => x"18050513", |
00000603 => x"25032c91", |
00000604 => x"8905fe80", |
00000605 => x"65053d11", |
00000606 => x"19850513", |
00000607 => x"25032491", |
00000608 => x"8909fe80", |
00000609 => x"65053511", |
00000610 => x"1b050513", |
00000611 => x"65052c15", |
00000612 => x"fe802403", |
00000613 => x"1c450513", |
00000614 => x"65412425", |
00000615 => x"33ed8d61", |
00000616 => x"05136505", |
00000617 => x"2c291d05", |
00000618 => x"00020537", |
00000619 => x"3be98d61", |
00000620 => x"05136505", |
00000621 => x"24291dc5", |
00000622 => x"00040537", |
00000623 => x"33e98d61", |
00000624 => x"05136505", |
00000625 => x"2aed1e85", |
00000626 => x"00080537", |
00000627 => x"3b6d8d61", |
00000628 => x"05136505", |
00000629 => x"22ed1f45", |
00000630 => x"00100537", |
00000631 => x"336d8d61", |
00000632 => x"05136505", |
00000633 => x"2ae92005", |
00000634 => x"00200537", |
00000635 => x"3b698d61", |
00000636 => x"05136505", |
00000637 => x"22e920c5", |
00000638 => x"00400537", |
00000639 => x"33698d61", |
00000640 => x"05136505", |
00000641 => x"2a6d2185", |
00000642 => x"00800537", |
00000643 => x"3bad8d61", |
00000644 => x"05136505", |
00000645 => x"226d2245", |
00000646 => x"01000537", |
00000647 => x"33ad8d61", |
00000648 => x"05136505", |
00000649 => x"2a692305", |
00000650 => x"02000537", |
00000651 => x"44628d61", |
00000652 => x"44d240f2", |
00000653 => x"61054942", |
00000654 => x"4705bb81", |
00000655 => x"00e78963", |
00000656 => x"9a634709", |
00000657 => x"650500e7", |
00000658 => x"08850513", |
00000659 => x"6505bda5", |
00000660 => x"07850513", |
00000661 => x"6505bd85", |
00000662 => x"08050513", |
00000663 => x"6505b5a5", |
00000664 => x"23c50513", |
00000665 => x"2503a281", |
00000666 => x"8145fe80", |
00000667 => x"80828905", |
00000668 => x"c02a1141", |
00000669 => x"0793c22e", |
00000670 => x"a023f900", |
00000671 => x"47120007", |
00000672 => x"f8e02a23", |
00000673 => x"c3984702", |
00000674 => x"80820141", |
00000675 => x"27831141", |
00000676 => x"2703f940", |
00000677 => x"2683f900", |
00000678 => x"9ae3f940", |
00000679 => x"c03afed7", |
00000680 => x"4502c23e", |
00000681 => x"01414592", |
00000682 => x"06938082", |
00000683 => x"567df980", |
00000684 => x"c288c290", |
00000685 => x"8082c2cc", |
00000686 => x"68051141", |
00000687 => x"00058523", |
00000688 => x"00544781", |
00000689 => x"2b080813", |
00000690 => x"76334729", |
00000691 => x"88b302e5", |
00000692 => x"078500f6", |
00000693 => x"46039642", |
00000694 => x"55330006", |
00000695 => x"802302e5", |
00000696 => x"94e300c8", |
00000697 => x"8636fee7", |
00000698 => x"05134725", |
00000699 => x"48030300", |
00000700 => x"87ba0096", |
00000701 => x"0742177d", |
00000702 => x"17638341", |
00000703 => x"04a300a8", |
00000704 => x"167d0006", |
00000705 => x"4781f76d", |
00000706 => x"470197b6", |
00000707 => x"0007c603", |
00000708 => x"0513ca09", |
00000709 => x"972e0017", |
00000710 => x"00c70023", |
00000711 => x"01051713", |
00000712 => x"86138341", |
00000713 => x"9763fff7", |
00000714 => x"95ba00f6", |
00000715 => x"00058023", |
00000716 => x"80820141", |
00000717 => x"bfd987b2", |
00000718 => x"fe802503", |
00000719 => x"89058149", |
00000720 => x"20238082", |
00000721 => x"2683fa00", |
00000722 => x"0506fe00", |
00000723 => x"f5634701", |
00000724 => x"668502a6", |
00000725 => x"16f94781", |
00000726 => x"02e6e763", |
00000727 => x"89858a05", |
00000728 => x"067a07e2", |
00000729 => x"05f68fd1", |
00000730 => x"8fd98fcd", |
00000731 => x"10000737", |
00000732 => x"20238fd9", |
00000733 => x"8082faf0", |
00000734 => x"00170793", |
00000735 => x"01079713", |
00000736 => x"83418e89", |
00000737 => x"8513b7e9", |
00000738 => x"7513ffe7", |
00000739 => x"e5110fd5", |
00000740 => x"0785830d", |
00000741 => x"0ff7f793", |
00000742 => x"8305b7c1", |
00000743 => x"2423bfdd", |
00000744 => x"8082fca0", |
00000745 => x"46b54729", |
00000746 => x"00054783", |
00000747 => x"e3910505", |
00000748 => x"94638082", |
00000749 => x"242300e7", |
00000750 => x"2423fcd0", |
00000751 => x"b7edfcf0", |
00000752 => x"d422715d", |
00000753 => x"6405c2be", |
00000754 => x"d226185c", |
00000755 => x"cc52ce4e", |
00000756 => x"c85aca56", |
00000757 => x"d04ad606", |
00000758 => x"dc32da2e", |
00000759 => x"c0bade36", |
00000760 => x"c6c6c4c2", |
00000761 => x"0993c03e", |
00000762 => x"4a290250", |
00000763 => x"04934ab5", |
00000764 => x"0b130730", |
00000765 => x"04130750", |
00000766 => x"47832bc4", |
00000767 => x"c39d0005", |
00000768 => x"0d379463", |
00000769 => x"00154783", |
00000770 => x"00250913", |
00000771 => x"06978563", |
00000772 => x"02f4e463", |
00000773 => x"06300713", |
00000774 => x"06e78763", |
00000775 => x"06900713", |
00000776 => x"06e78c63", |
00000777 => x"542250b2", |
00000778 => x"59025492", |
00000779 => x"4a6249f2", |
00000780 => x"4b424ad2", |
00000781 => x"80826161", |
00000782 => x"09678163", |
00000783 => x"07800713", |
00000784 => x"fee792e3", |
00000785 => x"00544782", |
00000786 => x"438c8536", |
00000787 => x"00478713", |
00000788 => x"0613c03a", |
00000789 => x"47010200", |
00000790 => x"00e5d7b3", |
00000791 => x"97a28bbd", |
00000792 => x"0007c783", |
00000793 => x"16fd0711", |
00000794 => x"00f68423", |
00000795 => x"fec716e3", |
00000796 => x"00010623", |
00000797 => x"4782a031", |
00000798 => x"87134388", |
00000799 => x"c03a0047", |
00000800 => x"854a3715", |
00000801 => x"4782bf9d", |
00000802 => x"00478713", |
00000803 => x"0007c783", |
00000804 => x"2423c03a", |
00000805 => x"b7f5fcf0", |
00000806 => x"43884782", |
00000807 => x"00478713", |
00000808 => x"5863c03a", |
00000809 => x"07930005", |
00000810 => x"053302d0", |
00000811 => x"242340a0", |
00000812 => x"004cfcf0", |
00000813 => x"00483511", |
00000814 => x"4782b7e1", |
00000815 => x"8713004c", |
00000816 => x"43880047", |
00000817 => x"b7fdc03a", |
00000818 => x"01479463", |
00000819 => x"fd502423", |
00000820 => x"00150913", |
00000821 => x"7693bf7d", |
00000822 => x"470d0fb5", |
00000823 => x"866387aa", |
00000824 => x"472d00e6", |
00000825 => x"98634505", |
00000826 => x"450500e7", |
00000827 => x"00f517b3", |
00000828 => x"3047a073", |
00000829 => x"80824501", |
00000830 => x"f8800713", |
00000831 => x"e693431c", |
00000832 => x"c3140087", |
00000833 => x"07378b8d", |
00000834 => x"078a8000", |
00000835 => x"08870713", |
00000836 => x"a30397ba", |
00000837 => x"83020007", |
00000838 => x"fe802503", |
00000839 => x"8905815d", |
00000840 => x"479d8082", |
00000841 => x"00a7fa63", |
00000842 => x"80824505", |
00000843 => x"40b24505", |
00000844 => x"44924422", |
00000845 => x"80820141", |
00000846 => x"c2261141", |
00000847 => x"658584ae", |
00000848 => x"8593c422", |
00000849 => x"842acf85", |
00000850 => x"c606456d", |
00000851 => x"a4fff0ef", |
00000852 => x"07b7fd71", |
00000853 => x"17138000", |
00000854 => x"87930024", |
00000855 => x"97ba0887", |
00000856 => x"2703c384", |
00000857 => x"0421f880", |
00000858 => x"97b34785", |
00000859 => x"8fd90087", |
00000860 => x"0107e793", |
00000861 => x"f8f02423", |
00000862 => x"479dbf5d", |
00000863 => x"00a7ed63", |
00000864 => x"f8802783", |
00000865 => x"8d5d0542", |
00000866 => x"000807b7", |
00000867 => x"24238d5d", |
00000868 => x"4501f8a0", |
00000869 => x"45058082", |
00000870 => x"00008082", |
00000871 => x"2d2d0a0a", |
00000872 => x"2d2d2d2d", |
00000873 => x"55504320", |
00000874 => x"53455420", |
00000875 => x"2d2d2054", |
00000876 => x"2d2d2d2d", |
00000877 => x"00000a0a", |
00000878 => x"74530a0a", |
00000879 => x"69747261", |
00000880 => x"7420676e", |
00000881 => x"73747365", |
00000882 => x"0a2e2e2e", |
00000883 => x"0000000a", |
00000884 => x"20455452", |
00000885 => x"74736e69", |
00000886 => x"206c6c61", |
00000887 => x"6f727265", |
00000888 => x"000a2172", |
00000889 => x"43494c43", |
00000890 => x"736e6920", |
00000891 => x"6c6c6174", |
00000892 => x"72726520", |
00000893 => x"0a21726f", |
00000894 => x"00000000", |
00000895 => x"4d454d49", |
00000896 => x"5345545f", |
00000897 => x"20203a54", |
00000898 => x"00000020", |
00000899 => x"70696b73", |
00000900 => x"20646570", |
00000901 => x"73696428", |
00000902 => x"656c6261", |
00000903 => x"000a2964", |
00000904 => x"4d454d44", |
00000905 => x"5345545f", |
00000906 => x"20203a54", |
00000907 => x"00000020", |
00000908 => x"4359434d", |
00000909 => x"485b454c", |
00000910 => x"20203a5d", |
00000911 => x"00000020", |
00000912 => x"000a6b6f", |
00000913 => x"6c696166", |
00000914 => x"0000000a", |
00000915 => x"534e494d", |
00000916 => x"54455254", |
00000917 => x"3a5d485b", |
00000918 => x"00000020", |
00000919 => x"454d4954", |
00000920 => x"3a5d485b", |
00000921 => x"20202020", |
00000922 => x"00000020", |
00000923 => x"434e4546", |
00000924 => x"492e2845", |
00000925 => x"20203a29", |
00000926 => x"00000020", |
00000927 => x"20435845", |
00000928 => x"4c415f49", |
00000929 => x"3a4e4749", |
00000930 => x"00000020", |
00000931 => x"70696b73", |
00000932 => x"20646570", |
00000933 => x"746f6e28", |
00000934 => x"736f7020", |
00000935 => x"6c626973", |
00000936 => x"68772065", |
00000937 => x"43206e65", |
00000938 => x"5458452d", |
00000939 => x"616e6520", |
00000940 => x"64656c62", |
00000941 => x"00000a29", |
00000942 => x"20435845", |
00000943 => x"43415f49", |
00000944 => x"20203a43", |
00000945 => x"00000020", |
00000946 => x"20435845", |
00000947 => x"4c495f49", |
00000948 => x"3a47454c", |
00000949 => x"00000020", |
00000950 => x"20435845", |
00000951 => x"41455242", |
00000952 => x"20203a4b", |
00000953 => x"00000020", |
00000954 => x"20435845", |
00000955 => x"4c415f4c", |
00000956 => x"3a4e4749", |
00000957 => x"00000020", |
00000958 => x"20435845", |
00000959 => x"43415f4c", |
00000960 => x"20203a43", |
00000961 => x"00000020", |
00000962 => x"20435845", |
00000963 => x"4c415f53", |
00000964 => x"3a4e4749", |
00000965 => x"00000020", |
00000966 => x"20435845", |
00000967 => x"43415f53", |
00000968 => x"20203a43", |
00000969 => x"00000020", |
00000970 => x"20435845", |
00000971 => x"43564e45", |
00000972 => x"3a4c4c41", |
00000973 => x"00000020", |
00000974 => x"20515249", |
00000975 => x"3a49544d", |
00000976 => x"20202020", |
00000977 => x"00000020", |
00000978 => x"20515249", |
00000979 => x"3a49454d", |
00000980 => x"20202020", |
00000981 => x"00000020", |
00000982 => x"3a494657", |
00000983 => x"20202020", |
00000984 => x"20202020", |
00000985 => x"00000020", |
00000986 => x"65540a0a", |
00000987 => x"3a737473", |
00000988 => x"0a692520", |
00000989 => x"203a4b4f", |
00000990 => x"25202020", |
00000991 => x"41460a69", |
00000992 => x"203a4c49", |
00000993 => x"0a692520", |
00000994 => x"0000000a", |
00000995 => x"54534554", |
00000996 => x"214b4f20", |
00000997 => x"0000000a", |
00000998 => x"54534554", |
00000999 => x"49414620", |
00001000 => x"2144454c", |
00001001 => x"0000000a", |
00001002 => x"65757254", |
00001003 => x"0000000a", |
00001004 => x"736c6146", |
00001005 => x"00000a65", |
00001006 => x"3c3c0a0a", |
00001007 => x"4f454e20", |
00001008 => x"32335652", |
00001009 => x"72614820", |
00001010 => x"72617764", |
00001011 => x"6f432065", |
00001012 => x"6769666e", |
00001013 => x"74617275", |
00001014 => x"206e6f69", |
00001015 => x"7265764f", |
00001016 => x"77656976", |
00001017 => x"0a3e3e20", |
00001018 => x"00000000", |
00001019 => x"202d2d0a", |
00001020 => x"746e6543", |
00001021 => x"206c6172", |
00001022 => x"636f7250", |
00001023 => x"69737365", |
00001024 => x"5520676e", |
00001025 => x"2074696e", |
00001026 => x"000a2d2d", |
00001027 => x"74726148", |
00001028 => x"3a444920", |
00001029 => x"20202020", |
00001030 => x"20202020", |
00001031 => x"78302020", |
00001032 => x"000a7825", |
00001033 => x"72657355", |
00001034 => x"646f6320", |
00001035 => x"20203a65", |
00001036 => x"20202020", |
00001037 => x"78302020", |
00001038 => x"000a7825", |
00001039 => x"64726148", |
00001040 => x"65726177", |
00001041 => x"72657620", |
00001042 => x"6e6f6973", |
00001043 => x"0000203a", |
00001044 => x"78302820", |
00001045 => x"0a297825", |
00001046 => x"00000000", |
00001047 => x"68637241", |
00001048 => x"63657469", |
00001049 => x"65727574", |
00001050 => x"2020203a", |
00001051 => x"00002020", |
00001052 => x"6e6b6e75", |
00001053 => x"006e776f", |
00001054 => x"32335652", |
00001055 => x"00000000", |
00001056 => x"32315652", |
00001057 => x"00000038", |
00001058 => x"34365652", |
00001059 => x"00000000", |
00001060 => x"5550430a", |
00001061 => x"74786520", |
00001062 => x"69736e65", |
00001063 => x"3a736e6f", |
00001064 => x"00202020", |
00001065 => x"25783028", |
00001066 => x"000a2978", |
00001067 => x"636f6c43", |
00001068 => x"7073206b", |
00001069 => x"3a646565", |
00001070 => x"20202020", |
00001071 => x"75252020", |
00001072 => x"0a7a4820", |
00001073 => x"00000000", |
00001074 => x"202d2d0a", |
00001075 => x"6f6d654d", |
00001076 => x"43207972", |
00001077 => x"69666e6f", |
00001078 => x"61727567", |
00001079 => x"6e6f6974", |
00001080 => x"0a2d2d20", |
00001081 => x"00000000", |
00001082 => x"74736e49", |
00001083 => x"74637572", |
00001084 => x"206e6f69", |
00001085 => x"6f6d656d", |
00001086 => x"203a7972", |
00001087 => x"75252020", |
00001088 => x"74796220", |
00001089 => x"40207365", |
00001090 => x"25783020", |
00001091 => x"00000a78", |
00001092 => x"65746e49", |
00001093 => x"6c616e72", |
00001094 => x"454d4920", |
00001095 => x"20203a4d", |
00001096 => x"20202020", |
00001097 => x"00002020", |
00001098 => x"65746e49", |
00001099 => x"6c616e72", |
00001100 => x"454d4920", |
00001101 => x"7361204d", |
00001102 => x"4d4f5220", |
00001103 => x"0000203a", |
00001104 => x"61746144", |
00001105 => x"6d656d20", |
00001106 => x"3a79726f", |
00001107 => x"20202020", |
00001108 => x"20202020", |
00001109 => x"75252020", |
00001110 => x"74796220", |
00001111 => x"40207365", |
00001112 => x"25783020", |
00001113 => x"00000a78", |
00001114 => x"65746e49", |
00001115 => x"6c616e72", |
00001116 => x"454d4420", |
00001117 => x"20203a4d", |
00001118 => x"20202020", |
00001119 => x"00002020", |
00001120 => x"746f6f42", |
00001121 => x"64616f6c", |
00001122 => x"203a7265", |
00001123 => x"20202020", |
00001124 => x"20202020", |
00001125 => x"00002020", |
00001126 => x"65747845", |
00001127 => x"6c616e72", |
00001128 => x"746e6920", |
00001129 => x"61667265", |
00001130 => x"203a6563", |
00001131 => x"00002020", |
00001132 => x"202d2d0a", |
00001133 => x"69726550", |
00001134 => x"72656870", |
00001135 => x"20736c61", |
00001136 => x"000a2d2d", |
00001137 => x"4f495047", |
00001138 => x"2020203a", |
00001139 => x"00000020", |
00001140 => x"4d49544d", |
00001141 => x"20203a45", |
00001142 => x"00000020", |
00001143 => x"54524155", |
00001144 => x"2020203a", |
00001145 => x"00000020", |
00001146 => x"3a495053", |
00001147 => x"20202020", |
00001148 => x"00000020", |
00001149 => x"3a495754", |
00001150 => x"20202020", |
00001151 => x"00000020", |
00001152 => x"3a4d5750", |
00001153 => x"20202020", |
00001154 => x"00000020", |
00001155 => x"3a544457", |
00001156 => x"20202020", |
00001157 => x"00000020", |
00001158 => x"43494c43", |
00001159 => x"2020203a", |
00001160 => x"00000020", |
00001161 => x"474e5254", |
00001162 => x"2020203a", |
00001163 => x"00000020", |
00001164 => x"4e564544", |
00001165 => x"3a4c4c55", |
00001166 => x"00000020", |
00001167 => x"68540a0a", |
00001168 => x"454e2065", |
00001169 => x"3356524f", |
00001170 => x"72502032", |
00001171 => x"7365636f", |
00001172 => x"20726f73", |
00001173 => x"6a6f7250", |
00001174 => x"0a746365", |
00001175 => x"53207962", |
00001176 => x"68706574", |
00001177 => x"4e206e61", |
00001178 => x"69746c6f", |
00001179 => x"680a676e", |
00001180 => x"73707474", |
00001181 => x"672f2f3a", |
00001182 => x"75687469", |
00001183 => x"6f632e62", |
00001184 => x"74732f6d", |
00001185 => x"746c6f6e", |
00001186 => x"2f676e69", |
00001187 => x"726f656e", |
00001188 => x"0a323376", |
00001189 => x"6564616d", |
00001190 => x"206e6920", |
00001191 => x"6e6e6148", |
00001192 => x"7265766f", |
00001193 => x"6547202c", |
00001194 => x"6e616d72", |
00001195 => x"000a0a79", |
00001196 => x"33323130", |
00001197 => x"37363534", |
00001198 => x"00003938", |
00001199 => x"33323130", |
00001200 => x"37363534", |
00001201 => x"62613938", |
00001202 => x"66656463", |
00001203 => x"dead007f", |
00001204 => x"00008067", |
others => x"00000000" |
); |
|
/neorv32/trunk/rtl/core/neorv32_bootloader_image.vhd
8,13 → 8,13
|
type bootloader_init_image_t is array (0 to 65535) of std_ulogic_vector(31 downto 0); |
constant bootloader_init_image : bootloader_init_image_t := ( |
00000000 => x"fc5015f3", |
00000001 => x"fc701673", |
00000000 => x"ff402583", |
00000001 => x"ffc02603", |
00000002 => x"00c58133", |
00000003 => x"ffc10113", |
00000004 => x"00000597", |
00000005 => x"05058593", |
00000006 => x"30559073", |
00000004 => x"00000697", |
00000005 => x"04468693", |
00000006 => x"30569073", |
00000007 => x"00000013", |
00000008 => x"00000093", |
00000009 => x"00000193", |
25,1004 → 25,1002
00000014 => x"00000413", |
00000015 => x"00000493", |
00000016 => x"00000513", |
00000017 => x"00000593", |
00000018 => x"00000613", |
00000019 => x"00000693", |
00000020 => x"00000713", |
00000021 => x"00000793", |
00000022 => x"028000ef", |
00000023 => x"fa5ff06f", |
00000024 => x"ffc10113", |
00000025 => x"00112023", |
00000026 => x"341010f3", |
00000027 => x"00408093", |
00000028 => x"34109073", |
00000029 => x"00012083", |
00000030 => x"00410113", |
00000031 => x"30200073", |
00000032 => x"fd010113", |
00000033 => x"00000513", |
00000034 => x"00000593", |
00000035 => x"02112623", |
00000036 => x"02812423", |
00000037 => x"02912223", |
00000038 => x"03212023", |
00000039 => x"01312e23", |
00000040 => x"01412c23", |
00000041 => x"01512a23", |
00000042 => x"01612823", |
00000043 => x"01712623", |
00000044 => x"01812423", |
00000045 => x"2c1000ef", |
00000046 => x"4f9000ef", |
00000047 => x"4cd000ef", |
00000048 => x"435000ef", |
00000049 => x"299000ef", |
00000050 => x"4d5000ef", |
00000051 => x"281000ef", |
00000052 => x"fc102473", |
00000053 => x"026267b7", |
00000054 => x"9ff78793", |
00000055 => x"00000713", |
00000056 => x"00000693", |
00000057 => x"00000613", |
00000058 => x"00000593", |
00000059 => x"00200513", |
00000060 => x"0087f463", |
00000061 => x"00400513", |
00000062 => x"3b1000ef", |
00000063 => x"00005537", |
00000064 => x"00000613", |
00000065 => x"00000593", |
00000066 => x"b0050513", |
00000067 => x"299000ef", |
00000068 => x"271000ef", |
00000069 => x"00245793", |
00000070 => x"00a78533", |
00000071 => x"00f537b3", |
00000072 => x"00b785b3", |
00000073 => x"269000ef", |
00000074 => x"ffff07b7", |
00000075 => x"43478793", |
00000076 => x"30579073", |
00000077 => x"08000793", |
00000078 => x"30479073", |
00000079 => x"30046073", |
00000080 => x"00100513", |
00000081 => x"43d000ef", |
00000082 => x"00000793", |
00000083 => x"34079073", |
00000084 => x"ffff1537", |
00000085 => x"ef450513", |
00000086 => x"2f9000ef", |
00000087 => x"3d0000ef", |
00000088 => x"ffff1537", |
00000089 => x"f2c50513", |
00000090 => x"2e9000ef", |
00000091 => x"fc102573", |
00000092 => x"254000ef", |
00000093 => x"ffff1537", |
00000094 => x"f3450513", |
00000095 => x"2d5000ef", |
00000096 => x"f1402573", |
00000097 => x"240000ef", |
00000098 => x"ffff1537", |
00000099 => x"f4050513", |
00000100 => x"2c1000ef", |
00000101 => x"30102573", |
00000102 => x"22c000ef", |
00000103 => x"ffff1537", |
00000104 => x"f4850513", |
00000105 => x"2ad000ef", |
00000106 => x"fc002573", |
00000107 => x"218000ef", |
00000017 => x"00000713", |
00000018 => x"00000793", |
00000019 => x"030000ef", |
00000020 => x"0000006f", |
00000021 => x"ffc10113", |
00000022 => x"00812023", |
00000023 => x"34202473", |
00000024 => x"00044863", |
00000025 => x"34102473", |
00000026 => x"00440413", |
00000027 => x"34141073", |
00000028 => x"00012403", |
00000029 => x"00410113", |
00000030 => x"30200073", |
00000031 => x"fd010113", |
00000032 => x"02112623", |
00000033 => x"02812423", |
00000034 => x"02912223", |
00000035 => x"03212023", |
00000036 => x"01312e23", |
00000037 => x"01412c23", |
00000038 => x"01512a23", |
00000039 => x"01612823", |
00000040 => x"01712623", |
00000041 => x"01812423", |
00000042 => x"f8002823", |
00000043 => x"f8002a23", |
00000044 => x"1c9000ef", |
00000045 => x"4f5000ef", |
00000046 => x"4c9000ef", |
00000047 => x"431000ef", |
00000048 => x"281000ef", |
00000049 => x"4d1000ef", |
00000050 => x"fe002403", |
00000051 => x"026267b7", |
00000052 => x"9ff78793", |
00000053 => x"00000713", |
00000054 => x"00000693", |
00000055 => x"00000613", |
00000056 => x"00000593", |
00000057 => x"00200513", |
00000058 => x"0087f463", |
00000059 => x"00400513", |
00000060 => x"3b1000ef", |
00000061 => x"00005537", |
00000062 => x"00000613", |
00000063 => x"00000593", |
00000064 => x"b0050513", |
00000065 => x"299000ef", |
00000066 => x"251000ef", |
00000067 => x"00245793", |
00000068 => x"00a78533", |
00000069 => x"00f537b3", |
00000070 => x"00b785b3", |
00000071 => x"269000ef", |
00000072 => x"ffff07b7", |
00000073 => x"41878793", |
00000074 => x"30579073", |
00000075 => x"08000793", |
00000076 => x"30479073", |
00000077 => x"30046073", |
00000078 => x"00100513", |
00000079 => x"43d000ef", |
00000080 => x"00000793", |
00000081 => x"34079073", |
00000082 => x"ffff1537", |
00000083 => x"eec50513", |
00000084 => x"2f9000ef", |
00000085 => x"135000ef", |
00000086 => x"ffff1537", |
00000087 => x"f2450513", |
00000088 => x"2e9000ef", |
00000089 => x"fe002503", |
00000090 => x"240000ef", |
00000091 => x"ffff1537", |
00000092 => x"f2c50513", |
00000093 => x"2d5000ef", |
00000094 => x"fe402503", |
00000095 => x"22c000ef", |
00000096 => x"ffff1537", |
00000097 => x"f3850513", |
00000098 => x"2c1000ef", |
00000099 => x"30102573", |
00000100 => x"218000ef", |
00000101 => x"ffff1537", |
00000102 => x"f4050513", |
00000103 => x"2ad000ef", |
00000104 => x"fe802503", |
00000105 => x"ffff14b7", |
00000106 => x"00341413", |
00000107 => x"1fc000ef", |
00000108 => x"ffff1537", |
00000109 => x"f5050513", |
00000110 => x"299000ef", |
00000111 => x"fc602573", |
00000112 => x"ffff14b7", |
00000113 => x"200000ef", |
00000114 => x"f5848513", |
00000115 => x"285000ef", |
00000116 => x"fc402573", |
00000117 => x"1f0000ef", |
00000109 => x"f4850513", |
00000110 => x"291000ef", |
00000111 => x"ff802503", |
00000112 => x"ffff1937", |
00000113 => x"1e4000ef", |
00000114 => x"f5048513", |
00000115 => x"27d000ef", |
00000116 => x"ff002503", |
00000117 => x"1d4000ef", |
00000118 => x"ffff1537", |
00000119 => x"f6450513", |
00000120 => x"271000ef", |
00000121 => x"fc702573", |
00000122 => x"1dc000ef", |
00000123 => x"f5848513", |
00000124 => x"261000ef", |
00000125 => x"fc502573", |
00000126 => x"1cc000ef", |
00000127 => x"ffff1537", |
00000128 => x"f6c50513", |
00000129 => x"24d000ef", |
00000130 => x"00341413", |
00000131 => x"00000493", |
00000132 => x"ffff1937", |
00000133 => x"fa402783", |
00000134 => x"0607d063", |
00000135 => x"ffff1537", |
00000136 => x"f9850513", |
00000137 => x"22d000ef", |
00000138 => x"ffff1937", |
00000139 => x"0f4000ef", |
00000140 => x"ffff19b7", |
00000141 => x"07200a13", |
00000142 => x"06800a93", |
00000143 => x"07500b13", |
00000144 => x"07300b93", |
00000145 => x"ffff14b7", |
00000146 => x"ffff1c37", |
00000147 => x"fa490513", |
00000148 => x"201000ef", |
00000149 => x"1ed000ef", |
00000150 => x"00050413", |
00000151 => x"1d5000ef", |
00000152 => x"f9498513", |
00000153 => x"1ed000ef", |
00000154 => x"09440263", |
00000155 => x"03541863", |
00000156 => x"0b0000ef", |
00000157 => x"fd9ff06f", |
00000158 => x"109000ef", |
00000159 => x"00b49463", |
00000160 => x"f8856ae3", |
00000161 => x"00100513", |
00000162 => x"508000ef", |
00000163 => x"f9490513", |
00000164 => x"1c1000ef", |
00000165 => x"098000ef", |
00000166 => x"f7dff06f", |
00000167 => x"00000513", |
00000168 => x"01640e63", |
00000169 => x"01741663", |
00000170 => x"72c000ef", |
00000171 => x"fa1ff06f", |
00000172 => x"06c00793", |
00000173 => x"00f41863", |
00000174 => x"00100513", |
00000175 => x"4d4000ef", |
00000176 => x"f8dff06f", |
00000177 => x"06500793", |
00000178 => x"00f41663", |
00000179 => x"060000ef", |
00000180 => x"f7dff06f", |
00000181 => x"03f00793", |
00000182 => x"facc0513", |
00000183 => x"00f40463", |
00000184 => x"fc048513", |
00000185 => x"16d000ef", |
00000186 => x"f65ff06f", |
00000187 => x"02c12083", |
00000188 => x"02812403", |
00000189 => x"02412483", |
00000190 => x"02012903", |
00000191 => x"01c12983", |
00000192 => x"01812a03", |
00000193 => x"01412a83", |
00000194 => x"01012b03", |
00000195 => x"00c12b83", |
00000196 => x"00812c03", |
00000197 => x"00000513", |
00000198 => x"03010113", |
00000199 => x"00008067", |
00000200 => x"ffff1537", |
00000201 => x"dc450513", |
00000202 => x"1290006f", |
00000203 => x"340027f3", |
00000204 => x"00079863", |
00000205 => x"ffff1537", |
00000206 => x"e2850513", |
00000207 => x"1150006f", |
00000208 => x"ff010113", |
00000209 => x"00112623", |
00000210 => x"30047073", |
00000211 => x"00000793", |
00000212 => x"30479073", |
00000213 => x"ffff1537", |
00000214 => x"e4450513", |
00000215 => x"0f5000ef", |
00000216 => x"fa002783", |
00000217 => x"fe07cee3", |
00000218 => x"fc4027f3", |
00000219 => x"00078067", |
00000220 => x"ff9ff06f", |
00000221 => x"ff010113", |
00000222 => x"00812423", |
00000223 => x"00050413", |
00000224 => x"ffff1537", |
00000225 => x"e5450513", |
00000226 => x"00112623", |
00000227 => x"0c5000ef", |
00000228 => x"00500793", |
00000229 => x"0287e063", |
00000230 => x"03040513", |
00000231 => x"0ff57513", |
00000232 => x"091000ef", |
00000233 => x"30047073", |
00000234 => x"00100513", |
00000235 => x"1d5000ef", |
00000236 => x"0000006f", |
00000119 => x"f5c50513", |
00000120 => x"269000ef", |
00000121 => x"ffc02503", |
00000122 => x"1c0000ef", |
00000123 => x"f5048513", |
00000124 => x"259000ef", |
00000125 => x"ff402503", |
00000126 => x"00000493", |
00000127 => x"1ac000ef", |
00000128 => x"ffff1537", |
00000129 => x"f6450513", |
00000130 => x"241000ef", |
00000131 => x"fa402783", |
00000132 => x"0607d263", |
00000133 => x"ffff1537", |
00000134 => x"f9050513", |
00000135 => x"22d000ef", |
00000136 => x"ffff1937", |
00000137 => x"0d0000ef", |
00000138 => x"ffff19b7", |
00000139 => x"07200a13", |
00000140 => x"06800a93", |
00000141 => x"07500b13", |
00000142 => x"07300b93", |
00000143 => x"ffff14b7", |
00000144 => x"ffff1c37", |
00000145 => x"f9c90513", |
00000146 => x"201000ef", |
00000147 => x"1ed000ef", |
00000148 => x"00050413", |
00000149 => x"1d5000ef", |
00000150 => x"f8c98513", |
00000151 => x"1ed000ef", |
00000152 => x"03441c63", |
00000153 => x"30047073", |
00000154 => x"ffff02b7", |
00000155 => x"00028067", |
00000156 => x"0000006f", |
00000157 => x"0e5000ef", |
00000158 => x"00b49463", |
00000159 => x"f88568e3", |
00000160 => x"00100513", |
00000161 => x"438000ef", |
00000162 => x"f8c90513", |
00000163 => x"1bd000ef", |
00000164 => x"070000ef", |
00000165 => x"f79ff06f", |
00000166 => x"01541663", |
00000167 => x"058000ef", |
00000168 => x"fa5ff06f", |
00000169 => x"00000513", |
00000170 => x"01640e63", |
00000171 => x"01741663", |
00000172 => x"650000ef", |
00000173 => x"f91ff06f", |
00000174 => x"06c00793", |
00000175 => x"00f41863", |
00000176 => x"00100513", |
00000177 => x"3f8000ef", |
00000178 => x"f7dff06f", |
00000179 => x"06500793", |
00000180 => x"00f41663", |
00000181 => x"02c000ef", |
00000182 => x"f6dff06f", |
00000183 => x"03f00793", |
00000184 => x"fa4c0513", |
00000185 => x"00f40463", |
00000186 => x"fb848513", |
00000187 => x"15d000ef", |
00000188 => x"f55ff06f", |
00000189 => x"ffff1537", |
00000190 => x"dbc50513", |
00000191 => x"14d0006f", |
00000192 => x"340027f3", |
00000193 => x"00079863", |
00000194 => x"ffff1537", |
00000195 => x"e2050513", |
00000196 => x"1390006f", |
00000197 => x"ff010113", |
00000198 => x"00112623", |
00000199 => x"30047073", |
00000200 => x"00000793", |
00000201 => x"30479073", |
00000202 => x"ffff1537", |
00000203 => x"e3c50513", |
00000204 => x"119000ef", |
00000205 => x"fa002783", |
00000206 => x"fe07cee3", |
00000207 => x"b0001073", |
00000208 => x"b8001073", |
00000209 => x"b0201073", |
00000210 => x"b8201073", |
00000211 => x"ff002783", |
00000212 => x"00078067", |
00000213 => x"ff9ff06f", |
00000214 => x"ff010113", |
00000215 => x"00812423", |
00000216 => x"00050413", |
00000217 => x"ffff1537", |
00000218 => x"e4c50513", |
00000219 => x"00112623", |
00000220 => x"0d9000ef", |
00000221 => x"00500793", |
00000222 => x"0287e063", |
00000223 => x"03040513", |
00000224 => x"0ff57513", |
00000225 => x"0a5000ef", |
00000226 => x"30047073", |
00000227 => x"00100513", |
00000228 => x"1e9000ef", |
00000229 => x"0000006f", |
00000230 => x"ffff1537", |
00000231 => x"e5450513", |
00000232 => x"0a9000ef", |
00000233 => x"fe5ff06f", |
00000234 => x"fe010113", |
00000235 => x"01212823", |
00000236 => x"00050913", |
00000237 => x"ffff1537", |
00000238 => x"e5c50513", |
00000239 => x"095000ef", |
00000240 => x"fe5ff06f", |
00000241 => x"fe010113", |
00000242 => x"01212823", |
00000243 => x"00050913", |
00000244 => x"ffff1537", |
00000245 => x"00912a23", |
00000246 => x"e6450513", |
00000247 => x"ffff14b7", |
00000248 => x"00812c23", |
00000249 => x"01312623", |
00000250 => x"00112e23", |
00000251 => x"01c00413", |
00000252 => x"061000ef", |
00000253 => x"fcc48493", |
00000254 => x"ffc00993", |
00000255 => x"008957b3", |
00000256 => x"00f7f793", |
00000257 => x"00f487b3", |
00000258 => x"0007c503", |
00000259 => x"ffc40413", |
00000260 => x"021000ef", |
00000261 => x"ff3414e3", |
00000262 => x"01c12083", |
00000263 => x"01812403", |
00000264 => x"01412483", |
00000265 => x"01012903", |
00000266 => x"00c12983", |
00000267 => x"02010113", |
00000268 => x"00008067", |
00000269 => x"fb010113", |
00000270 => x"04112623", |
00000271 => x"04512423", |
00000272 => x"04612223", |
00000273 => x"04712023", |
00000274 => x"02812e23", |
00000275 => x"02a12c23", |
00000276 => x"02b12a23", |
00000277 => x"02c12823", |
00000278 => x"02d12623", |
00000279 => x"02e12423", |
00000280 => x"02f12223", |
00000281 => x"03012023", |
00000282 => x"01112e23", |
00000283 => x"01c12c23", |
00000284 => x"01d12a23", |
00000285 => x"01e12823", |
00000286 => x"01f12623", |
00000287 => x"34202473", |
00000288 => x"800007b7", |
00000289 => x"00778793", |
00000290 => x"02f40a63", |
00000291 => x"ffff1537", |
00000292 => x"e6850513", |
00000293 => x"7bc000ef", |
00000294 => x"00040513", |
00000295 => x"f29ff0ef", |
00000296 => x"ffff1537", |
00000297 => x"e7850513", |
00000298 => x"7a8000ef", |
00000299 => x"34102573", |
00000300 => x"f15ff0ef", |
00000301 => x"00500513", |
00000302 => x"ebdff0ef", |
00000303 => x"00000513", |
00000304 => x"0a1000ef", |
00000305 => x"6bc000ef", |
00000306 => x"fc1027f3", |
00000307 => x"0027d793", |
00000308 => x"00a78533", |
00000309 => x"00f537b3", |
00000310 => x"00b785b3", |
00000311 => x"6b0000ef", |
00000312 => x"03c12403", |
00000313 => x"04c12083", |
00000314 => x"04812283", |
00000315 => x"04412303", |
00000316 => x"04012383", |
00000317 => x"03812503", |
00000318 => x"03412583", |
00000319 => x"03012603", |
00000320 => x"02c12683", |
00000321 => x"02812703", |
00000322 => x"02412783", |
00000323 => x"02012803", |
00000324 => x"01c12883", |
00000325 => x"01812e03", |
00000326 => x"01412e83", |
00000327 => x"01012f03", |
00000328 => x"00c12f83", |
00000329 => x"05010113", |
00000330 => x"30200073", |
00000331 => x"fe010113", |
00000332 => x"00112e23", |
00000333 => x"00812c23", |
00000334 => x"00912a23", |
00000335 => x"01212823", |
00000336 => x"01312623", |
00000337 => x"01412423", |
00000338 => x"01512223", |
00000339 => x"f1302973", |
00000340 => x"00000a93", |
00000341 => x"00900993", |
00000342 => x"00300a13", |
00000343 => x"00400493", |
00000344 => x"41500433", |
00000345 => x"00341413", |
00000346 => x"01840413", |
00000347 => x"00895433", |
00000348 => x"0ff47413", |
00000349 => x"00000513", |
00000350 => x"0489ec63", |
00000351 => x"00050863", |
00000352 => x"03050513", |
00000353 => x"0ff57513", |
00000354 => x"6a8000ef", |
00000355 => x"03040513", |
00000356 => x"0ff57513", |
00000357 => x"69c000ef", |
00000358 => x"014a8663", |
00000359 => x"02e00513", |
00000360 => x"690000ef", |
00000361 => x"001a8a93", |
00000362 => x"fa9a9ce3", |
00000363 => x"01c12083", |
00000364 => x"01812403", |
00000365 => x"01412483", |
00000366 => x"01012903", |
00000367 => x"00c12983", |
00000368 => x"00812a03", |
00000369 => x"00412a83", |
00000370 => x"02010113", |
00000371 => x"00008067", |
00000372 => x"ff640413", |
00000373 => x"00150513", |
00000374 => x"0ff47413", |
00000375 => x"0ff57513", |
00000376 => x"f99ff06f", |
00000377 => x"ff010113", |
00000378 => x"00000513", |
00000379 => x"00112623", |
00000380 => x"00812423", |
00000381 => x"714000ef", |
00000382 => x"00500513", |
00000383 => x"750000ef", |
00000384 => x"00000513", |
00000385 => x"748000ef", |
00000386 => x"00050413", |
00000387 => x"00000513", |
00000388 => x"718000ef", |
00000389 => x"00c12083", |
00000390 => x"0ff47513", |
00000391 => x"00812403", |
00000392 => x"01010113", |
00000393 => x"00008067", |
00000394 => x"ff010113", |
00000395 => x"00000513", |
00000396 => x"00112623", |
00000397 => x"00812423", |
00000398 => x"6d0000ef", |
00000399 => x"09e00513", |
00000400 => x"70c000ef", |
00000401 => x"00000513", |
00000402 => x"704000ef", |
00000403 => x"00050413", |
00000404 => x"00000513", |
00000405 => x"6d4000ef", |
00000406 => x"00c12083", |
00000407 => x"0ff47513", |
00000408 => x"00812403", |
00000409 => x"01010113", |
00000410 => x"00008067", |
00000411 => x"ff010113", |
00000412 => x"00000513", |
00000413 => x"00112623", |
00000414 => x"690000ef", |
00000415 => x"00600513", |
00000416 => x"6cc000ef", |
00000417 => x"00c12083", |
00000418 => x"00000513", |
00000419 => x"01010113", |
00000420 => x"6980006f", |
00000421 => x"ff010113", |
00000422 => x"00812423", |
00000423 => x"00050413", |
00000424 => x"01055513", |
00000425 => x"0ff57513", |
00000426 => x"00112623", |
00000427 => x"6a0000ef", |
00000428 => x"00845513", |
00000429 => x"0ff57513", |
00000430 => x"694000ef", |
00000431 => x"0ff47513", |
00000432 => x"00812403", |
00000433 => x"00c12083", |
00000434 => x"01010113", |
00000435 => x"6800006f", |
00000436 => x"ff010113", |
00000437 => x"00812423", |
00000438 => x"00050413", |
00000439 => x"00000513", |
00000440 => x"00112623", |
00000441 => x"624000ef", |
00000442 => x"00300513", |
00000443 => x"660000ef", |
00000444 => x"00040513", |
00000445 => x"fa1ff0ef", |
00000446 => x"00000513", |
00000447 => x"650000ef", |
00000448 => x"00050413", |
00000449 => x"00000513", |
00000450 => x"620000ef", |
00000451 => x"00c12083", |
00000452 => x"0ff47513", |
00000453 => x"00812403", |
00000454 => x"01010113", |
00000455 => x"00008067", |
00000456 => x"fd010113", |
00000457 => x"02812423", |
00000458 => x"02912223", |
00000459 => x"03212023", |
00000460 => x"01312e23", |
00000461 => x"02112623", |
00000462 => x"00050493", |
00000463 => x"00300413", |
00000464 => x"00358913", |
00000465 => x"fff00993", |
00000466 => x"02049e63", |
00000467 => x"4f4000ef", |
00000468 => x"00c10793", |
00000469 => x"008787b3", |
00000470 => x"00a78023", |
00000471 => x"fff40413", |
00000472 => x"ff3414e3", |
00000473 => x"02c12083", |
00000474 => x"02812403", |
00000475 => x"00c12503", |
00000476 => x"02412483", |
00000477 => x"02012903", |
00000478 => x"01c12983", |
00000479 => x"03010113", |
00000480 => x"00008067", |
00000481 => x"40890533", |
00000482 => x"f49ff0ef", |
00000483 => x"fc5ff06f", |
00000484 => x"fd010113", |
00000485 => x"02112623", |
00000486 => x"02812423", |
00000487 => x"02912223", |
00000488 => x"03212023", |
00000489 => x"01312e23", |
00000490 => x"01412c23", |
00000491 => x"01512a23", |
00000492 => x"01612823", |
00000493 => x"01712623", |
00000494 => x"fc002473", |
00000495 => x"00847413", |
00000496 => x"00040663", |
00000497 => x"00400513", |
00000498 => x"badff0ef", |
00000499 => x"00050493", |
00000500 => x"02051863", |
00000501 => x"ffff1537", |
00000502 => x"e8050513", |
00000503 => x"474000ef", |
00000504 => x"008005b7", |
00000505 => x"00048513", |
00000506 => x"f39ff0ef", |
00000507 => x"4788d7b7", |
00000508 => x"afe78793", |
00000509 => x"02f50463", |
00000510 => x"00000513", |
00000511 => x"fcdff06f", |
00000512 => x"ffff1537", |
00000513 => x"ea050513", |
00000514 => x"448000ef", |
00000515 => x"e1dff0ef", |
00000516 => x"fc0518e3", |
00000517 => x"00300513", |
00000518 => x"fb1ff06f", |
00000519 => x"00800a37", |
00000520 => x"004a0593", |
00000521 => x"00048513", |
00000522 => x"ef9ff0ef", |
00000523 => x"00050913", |
00000524 => x"008a0593", |
00000525 => x"00048513", |
00000526 => x"ee9ff0ef", |
00000527 => x"00050a93", |
00000528 => x"fc6027f3", |
00000529 => x"00100513", |
00000530 => x"f927e0e3", |
00000531 => x"fc402bf3", |
00000532 => x"00000993", |
00000533 => x"ffc97b13", |
00000534 => x"00ca0a13", |
00000535 => x"014985b3", |
00000536 => x"053b1663", |
00000537 => x"01540433", |
00000538 => x"00200513", |
00000539 => x"f4041ee3", |
00000540 => x"ffff1537", |
00000541 => x"eac50513", |
00000542 => x"3d8000ef", |
00000543 => x"34091073", |
00000544 => x"02c12083", |
00000545 => x"02812403", |
00000546 => x"02412483", |
00000547 => x"02012903", |
00000548 => x"01c12983", |
00000549 => x"01812a03", |
00000550 => x"01412a83", |
00000551 => x"01012b03", |
00000552 => x"00c12b83", |
00000553 => x"03010113", |
00000554 => x"00008067", |
00000555 => x"00048513", |
00000556 => x"e71ff0ef", |
00000557 => x"017987b3", |
00000558 => x"00a40433", |
00000559 => x"00a7a023", |
00000560 => x"00498993", |
00000561 => x"f99ff06f", |
00000562 => x"ff010113", |
00000563 => x"00112623", |
00000564 => x"00812423", |
00000565 => x"00912223", |
00000566 => x"00058413", |
00000567 => x"00050493", |
00000568 => x"d8dff0ef", |
00000569 => x"00000513", |
00000570 => x"420000ef", |
00000571 => x"00200513", |
00000572 => x"45c000ef", |
00000573 => x"00048513", |
00000574 => x"d9dff0ef", |
00000575 => x"00040513", |
00000576 => x"44c000ef", |
00000577 => x"00000513", |
00000578 => x"420000ef", |
00000579 => x"cd9ff0ef", |
00000580 => x"00157513", |
00000581 => x"fe051ce3", |
00000582 => x"00c12083", |
00000583 => x"00812403", |
00000584 => x"00412483", |
00000585 => x"01010113", |
00000586 => x"00008067", |
00000587 => x"fe010113", |
00000588 => x"00812c23", |
00000589 => x"00912a23", |
00000590 => x"01212823", |
00000591 => x"00112e23", |
00000592 => x"00b12623", |
00000593 => x"00300413", |
00000594 => x"00350493", |
00000595 => x"fff00913", |
00000596 => x"00c10793", |
00000597 => x"008787b3", |
00000598 => x"0007c583", |
00000599 => x"40848533", |
00000600 => x"fff40413", |
00000601 => x"f65ff0ef", |
00000602 => x"ff2414e3", |
00000603 => x"01c12083", |
00000604 => x"01812403", |
00000605 => x"01412483", |
00000606 => x"01012903", |
00000607 => x"02010113", |
00000608 => x"00008067", |
00000609 => x"ff010113", |
00000610 => x"00112623", |
00000611 => x"00812423", |
00000612 => x"00050413", |
00000613 => x"cd9ff0ef", |
00000614 => x"00000513", |
00000615 => x"36c000ef", |
00000616 => x"0d800513", |
00000617 => x"3a8000ef", |
00000618 => x"00040513", |
00000619 => x"ce9ff0ef", |
00000620 => x"00000513", |
00000621 => x"374000ef", |
00000622 => x"c2dff0ef", |
00000623 => x"00157513", |
00000624 => x"fe051ce3", |
00000625 => x"00c12083", |
00000626 => x"00812403", |
00000627 => x"01010113", |
00000628 => x"00008067", |
00000629 => x"fe010113", |
00000630 => x"00112e23", |
00000631 => x"00812c23", |
00000632 => x"00912a23", |
00000633 => x"01212823", |
00000634 => x"01312623", |
00000635 => x"01412423", |
00000636 => x"01512223", |
00000637 => x"34002473", |
00000638 => x"02041863", |
00000639 => x"ffff1537", |
00000640 => x"e2850513", |
00000641 => x"01812403", |
00000642 => x"01c12083", |
00000643 => x"01412483", |
00000644 => x"01012903", |
00000645 => x"00c12983", |
00000646 => x"00812a03", |
00000647 => x"00412a83", |
00000648 => x"02010113", |
00000649 => x"22c0006f", |
00000650 => x"ffff1537", |
00000651 => x"eb050513", |
00000652 => x"220000ef", |
00000653 => x"00040513", |
00000654 => x"98dff0ef", |
00000655 => x"ffff1537", |
00000656 => x"ebc50513", |
00000657 => x"20c000ef", |
00000658 => x"00800537", |
00000659 => x"979ff0ef", |
00000660 => x"ffff1537", |
00000661 => x"ed850513", |
00000662 => x"1f8000ef", |
00000663 => x"1e4000ef", |
00000664 => x"00050493", |
00000665 => x"1cc000ef", |
00000666 => x"07900793", |
00000667 => x"0af49e63", |
00000668 => x"bb9ff0ef", |
00000669 => x"00051663", |
00000670 => x"00300513", |
00000671 => x"8f9ff0ef", |
00000672 => x"ffff1537", |
00000673 => x"ee450513", |
00000674 => x"01045493", |
00000675 => x"1c4000ef", |
00000676 => x"00148493", |
00000677 => x"00800937", |
00000678 => x"fff00993", |
00000679 => x"00010a37", |
00000680 => x"fff48493", |
00000681 => x"07349063", |
00000682 => x"4788d5b7", |
00000683 => x"afe58593", |
00000684 => x"00800537", |
00000685 => x"e79ff0ef", |
00000686 => x"00800537", |
00000687 => x"00040593", |
00000688 => x"00450513", |
00000689 => x"e69ff0ef", |
00000690 => x"fc402a73", |
00000691 => x"008009b7", |
00000692 => x"ffc47413", |
00000693 => x"00000493", |
00000694 => x"00000913", |
00000695 => x"00c98a93", |
00000696 => x"01548533", |
00000697 => x"014487b3", |
00000698 => x"02849663", |
00000699 => x"00898513", |
00000700 => x"412005b3", |
00000701 => x"e39ff0ef", |
00000702 => x"ffff1537", |
00000703 => x"eac50513", |
00000704 => x"f05ff06f", |
00000705 => x"00090513", |
00000706 => x"e7dff0ef", |
00000707 => x"01490933", |
00000708 => x"f91ff06f", |
00000709 => x"0007a583", |
00000710 => x"00448493", |
00000711 => x"00b90933", |
00000712 => x"e0dff0ef", |
00000713 => x"fbdff06f", |
00000714 => x"01c12083", |
00000715 => x"01812403", |
00000716 => x"01412483", |
00000717 => x"01012903", |
00000718 => x"00c12983", |
00000719 => x"00812a03", |
00000720 => x"00412a83", |
00000721 => x"02010113", |
00000722 => x"00008067", |
00000723 => x"000047b7", |
00000724 => x"70078793", |
00000725 => x"f8f02623", |
00000726 => x"00008067", |
00000727 => x"fc000713", |
00000728 => x"00072783", |
00000729 => x"00179793", |
00000730 => x"0017d793", |
00000731 => x"00f72023", |
00000732 => x"00008067", |
00000733 => x"f8a02823", |
00000734 => x"f8b02a23", |
00000735 => x"00008067", |
00000736 => x"f9002503", |
00000737 => x"f9402583", |
00000738 => x"00008067", |
00000739 => x"f9800693", |
00000740 => x"fff00613", |
00000741 => x"00c6a023", |
00000742 => x"00a6a023", |
00000743 => x"00b6a223", |
00000744 => x"00008067", |
00000745 => x"fa002023", |
00000746 => x"fc1026f3", |
00000747 => x"00000713", |
00000748 => x"00151513", |
00000749 => x"04a6f263", |
00000750 => x"000016b7", |
00000751 => x"00000793", |
00000752 => x"ffe68693", |
00000753 => x"04e6e463", |
00000754 => x"00167613", |
00000755 => x"0015f593", |
00000756 => x"01879793", |
00000757 => x"01e61613", |
00000758 => x"00c7e7b3", |
00000759 => x"01d59593", |
00000760 => x"00b7e7b3", |
00000238 => x"00912a23", |
00000239 => x"e5c50513", |
00000240 => x"ffff14b7", |
00000241 => x"00812c23", |
00000242 => x"01312623", |
00000243 => x"00112e23", |
00000244 => x"01c00413", |
00000245 => x"075000ef", |
00000246 => x"fc448493", |
00000247 => x"ffc00993", |
00000248 => x"008957b3", |
00000249 => x"00f7f793", |
00000250 => x"00f487b3", |
00000251 => x"0007c503", |
00000252 => x"ffc40413", |
00000253 => x"035000ef", |
00000254 => x"ff3414e3", |
00000255 => x"01c12083", |
00000256 => x"01812403", |
00000257 => x"01412483", |
00000258 => x"01012903", |
00000259 => x"00c12983", |
00000260 => x"02010113", |
00000261 => x"00008067", |
00000262 => x"fb010113", |
00000263 => x"04112623", |
00000264 => x"04512423", |
00000265 => x"04612223", |
00000266 => x"04712023", |
00000267 => x"02812e23", |
00000268 => x"02a12c23", |
00000269 => x"02b12a23", |
00000270 => x"02c12823", |
00000271 => x"02d12623", |
00000272 => x"02e12423", |
00000273 => x"02f12223", |
00000274 => x"03012023", |
00000275 => x"01112e23", |
00000276 => x"01c12c23", |
00000277 => x"01d12a23", |
00000278 => x"01e12823", |
00000279 => x"01f12623", |
00000280 => x"34202473", |
00000281 => x"800007b7", |
00000282 => x"00778793", |
00000283 => x"02f40a63", |
00000284 => x"ffff1537", |
00000285 => x"e6050513", |
00000286 => x"7d0000ef", |
00000287 => x"00040513", |
00000288 => x"f29ff0ef", |
00000289 => x"ffff1537", |
00000290 => x"e7050513", |
00000291 => x"7bc000ef", |
00000292 => x"34102573", |
00000293 => x"f15ff0ef", |
00000294 => x"00500513", |
00000295 => x"ebdff0ef", |
00000296 => x"00000513", |
00000297 => x"0b5000ef", |
00000298 => x"6b0000ef", |
00000299 => x"fe002783", |
00000300 => x"0027d793", |
00000301 => x"00a78533", |
00000302 => x"00f537b3", |
00000303 => x"00b785b3", |
00000304 => x"6c4000ef", |
00000305 => x"03c12403", |
00000306 => x"04c12083", |
00000307 => x"04812283", |
00000308 => x"04412303", |
00000309 => x"04012383", |
00000310 => x"03812503", |
00000311 => x"03412583", |
00000312 => x"03012603", |
00000313 => x"02c12683", |
00000314 => x"02812703", |
00000315 => x"02412783", |
00000316 => x"02012803", |
00000317 => x"01c12883", |
00000318 => x"01812e03", |
00000319 => x"01412e83", |
00000320 => x"01012f03", |
00000321 => x"00c12f83", |
00000322 => x"05010113", |
00000323 => x"30200073", |
00000324 => x"ff010113", |
00000325 => x"00000513", |
00000326 => x"00112623", |
00000327 => x"00812423", |
00000328 => x"7e0000ef", |
00000329 => x"00500513", |
00000330 => x"01d000ef", |
00000331 => x"00000513", |
00000332 => x"015000ef", |
00000333 => x"00050413", |
00000334 => x"00000513", |
00000335 => x"7e4000ef", |
00000336 => x"00c12083", |
00000337 => x"0ff47513", |
00000338 => x"00812403", |
00000339 => x"01010113", |
00000340 => x"00008067", |
00000341 => x"ff010113", |
00000342 => x"00000513", |
00000343 => x"00112623", |
00000344 => x"00812423", |
00000345 => x"79c000ef", |
00000346 => x"09e00513", |
00000347 => x"7d8000ef", |
00000348 => x"00000513", |
00000349 => x"7d0000ef", |
00000350 => x"00050413", |
00000351 => x"00000513", |
00000352 => x"7a0000ef", |
00000353 => x"00c12083", |
00000354 => x"0ff47513", |
00000355 => x"00812403", |
00000356 => x"01010113", |
00000357 => x"00008067", |
00000358 => x"ff010113", |
00000359 => x"00000513", |
00000360 => x"00112623", |
00000361 => x"75c000ef", |
00000362 => x"00600513", |
00000363 => x"798000ef", |
00000364 => x"00c12083", |
00000365 => x"00000513", |
00000366 => x"01010113", |
00000367 => x"7640006f", |
00000368 => x"ff010113", |
00000369 => x"00812423", |
00000370 => x"00050413", |
00000371 => x"01055513", |
00000372 => x"0ff57513", |
00000373 => x"00112623", |
00000374 => x"76c000ef", |
00000375 => x"00845513", |
00000376 => x"0ff57513", |
00000377 => x"760000ef", |
00000378 => x"0ff47513", |
00000379 => x"00812403", |
00000380 => x"00c12083", |
00000381 => x"01010113", |
00000382 => x"74c0006f", |
00000383 => x"ff010113", |
00000384 => x"00812423", |
00000385 => x"00050413", |
00000386 => x"00000513", |
00000387 => x"00112623", |
00000388 => x"6f0000ef", |
00000389 => x"00300513", |
00000390 => x"72c000ef", |
00000391 => x"00040513", |
00000392 => x"fa1ff0ef", |
00000393 => x"00000513", |
00000394 => x"71c000ef", |
00000395 => x"00050413", |
00000396 => x"00000513", |
00000397 => x"6ec000ef", |
00000398 => x"00c12083", |
00000399 => x"0ff47513", |
00000400 => x"00812403", |
00000401 => x"01010113", |
00000402 => x"00008067", |
00000403 => x"fd010113", |
00000404 => x"02812423", |
00000405 => x"02912223", |
00000406 => x"03212023", |
00000407 => x"01312e23", |
00000408 => x"02112623", |
00000409 => x"00050493", |
00000410 => x"00300413", |
00000411 => x"00358913", |
00000412 => x"fff00993", |
00000413 => x"02049e63", |
00000414 => x"5c0000ef", |
00000415 => x"00c10793", |
00000416 => x"008787b3", |
00000417 => x"00a78023", |
00000418 => x"fff40413", |
00000419 => x"ff3414e3", |
00000420 => x"02c12083", |
00000421 => x"02812403", |
00000422 => x"00c12503", |
00000423 => x"02412483", |
00000424 => x"02012903", |
00000425 => x"01c12983", |
00000426 => x"03010113", |
00000427 => x"00008067", |
00000428 => x"40890533", |
00000429 => x"f49ff0ef", |
00000430 => x"fc5ff06f", |
00000431 => x"fd010113", |
00000432 => x"02812423", |
00000433 => x"fe802403", |
00000434 => x"02112623", |
00000435 => x"02912223", |
00000436 => x"03212023", |
00000437 => x"01312e23", |
00000438 => x"01412c23", |
00000439 => x"01512a23", |
00000440 => x"01612823", |
00000441 => x"01712623", |
00000442 => x"00847413", |
00000443 => x"00040663", |
00000444 => x"00400513", |
00000445 => x"c65ff0ef", |
00000446 => x"00050493", |
00000447 => x"02051863", |
00000448 => x"ffff1537", |
00000449 => x"e7850513", |
00000450 => x"540000ef", |
00000451 => x"008005b7", |
00000452 => x"00048513", |
00000453 => x"f39ff0ef", |
00000454 => x"4788d7b7", |
00000455 => x"afe78793", |
00000456 => x"02f50463", |
00000457 => x"00000513", |
00000458 => x"fcdff06f", |
00000459 => x"ffff1537", |
00000460 => x"e9850513", |
00000461 => x"514000ef", |
00000462 => x"e1dff0ef", |
00000463 => x"fc0518e3", |
00000464 => x"00300513", |
00000465 => x"fb1ff06f", |
00000466 => x"00800a37", |
00000467 => x"004a0593", |
00000468 => x"00048513", |
00000469 => x"ef9ff0ef", |
00000470 => x"00050913", |
00000471 => x"008a0593", |
00000472 => x"00048513", |
00000473 => x"ee9ff0ef", |
00000474 => x"ff802783", |
00000475 => x"00050a93", |
00000476 => x"00100513", |
00000477 => x"f927e0e3", |
00000478 => x"ff002b83", |
00000479 => x"ffc97b13", |
00000480 => x"00000993", |
00000481 => x"00ca0a13", |
00000482 => x"014985b3", |
00000483 => x"053b1663", |
00000484 => x"01540433", |
00000485 => x"00200513", |
00000486 => x"f4041ee3", |
00000487 => x"ffff1537", |
00000488 => x"ea450513", |
00000489 => x"4a4000ef", |
00000490 => x"34091073", |
00000491 => x"02c12083", |
00000492 => x"02812403", |
00000493 => x"02412483", |
00000494 => x"02012903", |
00000495 => x"01c12983", |
00000496 => x"01812a03", |
00000497 => x"01412a83", |
00000498 => x"01012b03", |
00000499 => x"00c12b83", |
00000500 => x"03010113", |
00000501 => x"00008067", |
00000502 => x"00048513", |
00000503 => x"e71ff0ef", |
00000504 => x"013b87b3", |
00000505 => x"00a40433", |
00000506 => x"00a7a023", |
00000507 => x"00498993", |
00000508 => x"f99ff06f", |
00000509 => x"ff010113", |
00000510 => x"00112623", |
00000511 => x"00812423", |
00000512 => x"00912223", |
00000513 => x"00058413", |
00000514 => x"00050493", |
00000515 => x"d8dff0ef", |
00000516 => x"00000513", |
00000517 => x"4ec000ef", |
00000518 => x"00200513", |
00000519 => x"528000ef", |
00000520 => x"00048513", |
00000521 => x"d9dff0ef", |
00000522 => x"00040513", |
00000523 => x"518000ef", |
00000524 => x"00000513", |
00000525 => x"4ec000ef", |
00000526 => x"cd9ff0ef", |
00000527 => x"00157513", |
00000528 => x"fe051ce3", |
00000529 => x"00c12083", |
00000530 => x"00812403", |
00000531 => x"00412483", |
00000532 => x"01010113", |
00000533 => x"00008067", |
00000534 => x"fe010113", |
00000535 => x"00812c23", |
00000536 => x"00912a23", |
00000537 => x"01212823", |
00000538 => x"00112e23", |
00000539 => x"00b12623", |
00000540 => x"00300413", |
00000541 => x"00350493", |
00000542 => x"fff00913", |
00000543 => x"00c10793", |
00000544 => x"008787b3", |
00000545 => x"0007c583", |
00000546 => x"40848533", |
00000547 => x"fff40413", |
00000548 => x"f65ff0ef", |
00000549 => x"ff2414e3", |
00000550 => x"01c12083", |
00000551 => x"01812403", |
00000552 => x"01412483", |
00000553 => x"01012903", |
00000554 => x"02010113", |
00000555 => x"00008067", |
00000556 => x"ff010113", |
00000557 => x"00112623", |
00000558 => x"00812423", |
00000559 => x"00050413", |
00000560 => x"cd9ff0ef", |
00000561 => x"00000513", |
00000562 => x"438000ef", |
00000563 => x"0d800513", |
00000564 => x"474000ef", |
00000565 => x"00040513", |
00000566 => x"ce9ff0ef", |
00000567 => x"00000513", |
00000568 => x"440000ef", |
00000569 => x"c2dff0ef", |
00000570 => x"00157513", |
00000571 => x"fe051ce3", |
00000572 => x"00c12083", |
00000573 => x"00812403", |
00000574 => x"01010113", |
00000575 => x"00008067", |
00000576 => x"fe010113", |
00000577 => x"00112e23", |
00000578 => x"00812c23", |
00000579 => x"00912a23", |
00000580 => x"01212823", |
00000581 => x"01312623", |
00000582 => x"01412423", |
00000583 => x"01512223", |
00000584 => x"34002473", |
00000585 => x"02041863", |
00000586 => x"ffff1537", |
00000587 => x"e2050513", |
00000588 => x"01812403", |
00000589 => x"01c12083", |
00000590 => x"01412483", |
00000591 => x"01012903", |
00000592 => x"00c12983", |
00000593 => x"00812a03", |
00000594 => x"00412a83", |
00000595 => x"02010113", |
00000596 => x"2f80006f", |
00000597 => x"ffff1537", |
00000598 => x"ea850513", |
00000599 => x"2ec000ef", |
00000600 => x"00040513", |
00000601 => x"a45ff0ef", |
00000602 => x"ffff1537", |
00000603 => x"eb450513", |
00000604 => x"2d8000ef", |
00000605 => x"00800537", |
00000606 => x"a31ff0ef", |
00000607 => x"ffff1537", |
00000608 => x"ed050513", |
00000609 => x"2c4000ef", |
00000610 => x"2b0000ef", |
00000611 => x"00050493", |
00000612 => x"298000ef", |
00000613 => x"07900793", |
00000614 => x"0af49e63", |
00000615 => x"bb9ff0ef", |
00000616 => x"00051663", |
00000617 => x"00300513", |
00000618 => x"9b1ff0ef", |
00000619 => x"ffff1537", |
00000620 => x"edc50513", |
00000621 => x"01045493", |
00000622 => x"290000ef", |
00000623 => x"00148493", |
00000624 => x"00800937", |
00000625 => x"fff00993", |
00000626 => x"00010a37", |
00000627 => x"fff48493", |
00000628 => x"07349063", |
00000629 => x"4788d5b7", |
00000630 => x"afe58593", |
00000631 => x"00800537", |
00000632 => x"e79ff0ef", |
00000633 => x"00800537", |
00000634 => x"00040593", |
00000635 => x"00450513", |
00000636 => x"e69ff0ef", |
00000637 => x"ff002a03", |
00000638 => x"008009b7", |
00000639 => x"ffc47413", |
00000640 => x"00000493", |
00000641 => x"00000913", |
00000642 => x"00c98a93", |
00000643 => x"01548533", |
00000644 => x"009a07b3", |
00000645 => x"02849663", |
00000646 => x"00898513", |
00000647 => x"412005b3", |
00000648 => x"e39ff0ef", |
00000649 => x"ffff1537", |
00000650 => x"ea450513", |
00000651 => x"f05ff06f", |
00000652 => x"00090513", |
00000653 => x"e7dff0ef", |
00000654 => x"01490933", |
00000655 => x"f91ff06f", |
00000656 => x"0007a583", |
00000657 => x"00448493", |
00000658 => x"00b90933", |
00000659 => x"e0dff0ef", |
00000660 => x"fbdff06f", |
00000661 => x"01c12083", |
00000662 => x"01812403", |
00000663 => x"01412483", |
00000664 => x"01012903", |
00000665 => x"00c12983", |
00000666 => x"00812a03", |
00000667 => x"00412a83", |
00000668 => x"02010113", |
00000669 => x"00008067", |
00000670 => x"000047b7", |
00000671 => x"70078793", |
00000672 => x"f8f02623", |
00000673 => x"00008067", |
00000674 => x"fe010113", |
00000675 => x"00112e23", |
00000676 => x"00812c23", |
00000677 => x"00912a23", |
00000678 => x"01212823", |
00000679 => x"01312623", |
00000680 => x"01412423", |
00000681 => x"01512223", |
00000682 => x"f1302973", |
00000683 => x"00000a93", |
00000684 => x"00900993", |
00000685 => x"00300a13", |
00000686 => x"00400493", |
00000687 => x"41500433", |
00000688 => x"00341413", |
00000689 => x"01840413", |
00000690 => x"00895433", |
00000691 => x"0ff47413", |
00000692 => x"00000513", |
00000693 => x"0489ec63", |
00000694 => x"00050863", |
00000695 => x"03050513", |
00000696 => x"0ff57513", |
00000697 => x"144000ef", |
00000698 => x"03040513", |
00000699 => x"0ff57513", |
00000700 => x"138000ef", |
00000701 => x"014a8663", |
00000702 => x"02e00513", |
00000703 => x"12c000ef", |
00000704 => x"001a8a93", |
00000705 => x"fa9a9ce3", |
00000706 => x"01c12083", |
00000707 => x"01812403", |
00000708 => x"01412483", |
00000709 => x"01012903", |
00000710 => x"00c12983", |
00000711 => x"00812a03", |
00000712 => x"00412a83", |
00000713 => x"02010113", |
00000714 => x"00008067", |
00000715 => x"ff640413", |
00000716 => x"00150513", |
00000717 => x"0ff47413", |
00000718 => x"0ff57513", |
00000719 => x"f99ff06f", |
00000720 => x"fc000713", |
00000721 => x"00072783", |
00000722 => x"00179793", |
00000723 => x"0017d793", |
00000724 => x"00f72023", |
00000725 => x"00008067", |
00000726 => x"ff010113", |
00000727 => x"f9402783", |
00000728 => x"f9002703", |
00000729 => x"f9402683", |
00000730 => x"fed79ae3", |
00000731 => x"00e12023", |
00000732 => x"00f12223", |
00000733 => x"00012503", |
00000734 => x"00412583", |
00000735 => x"01010113", |
00000736 => x"00008067", |
00000737 => x"f9800693", |
00000738 => x"fff00613", |
00000739 => x"00c6a023", |
00000740 => x"00a6a023", |
00000741 => x"00b6a223", |
00000742 => x"00008067", |
00000743 => x"fa002023", |
00000744 => x"fe002683", |
00000745 => x"00151513", |
00000746 => x"00000713", |
00000747 => x"04a6f263", |
00000748 => x"000016b7", |
00000749 => x"00000793", |
00000750 => x"ffe68693", |
00000751 => x"04e6e463", |
00000752 => x"00167613", |
00000753 => x"0015f593", |
00000754 => x"01879793", |
00000755 => x"01e61613", |
00000756 => x"00c7e7b3", |
00000757 => x"01d59593", |
00000758 => x"00b7e7b3", |
00000759 => x"00e7e7b3", |
00000760 => x"10000737", |
00000761 => x"00e7e7b3", |
00000762 => x"10000737", |
00000763 => x"00e7e7b3", |
00000764 => x"faf02023", |
00000765 => x"00008067", |
00000766 => x"00170793", |
00000767 => x"01079713", |
00000768 => x"40a686b3", |
00000769 => x"01075713", |
00000770 => x"fadff06f", |
00000771 => x"ffe78513", |
00000772 => x"0fd57513", |
00000773 => x"00051a63", |
00000774 => x"00375713", |
00000775 => x"00178793", |
00000776 => x"0ff7f793", |
00000777 => x"fa1ff06f", |
00000778 => x"00175713", |
00000779 => x"ff1ff06f", |
00000780 => x"fa002783", |
00000781 => x"fe07cee3", |
00000782 => x"faa02223", |
00000783 => x"00008067", |
00000784 => x"fa402503", |
00000785 => x"fe055ee3", |
00000786 => x"0ff57513", |
00000787 => x"00008067", |
00000788 => x"ff010113", |
00000789 => x"00812423", |
00000790 => x"01212023", |
00000791 => x"00112623", |
00000792 => x"00912223", |
00000793 => x"00050413", |
00000794 => x"00a00913", |
00000795 => x"00044483", |
00000796 => x"00140413", |
00000797 => x"00049e63", |
00000798 => x"00c12083", |
00000799 => x"00812403", |
00000800 => x"00412483", |
00000801 => x"00012903", |
00000802 => x"01010113", |
00000803 => x"00008067", |
00000804 => x"01249663", |
00000805 => x"00d00513", |
00000806 => x"f99ff0ef", |
00000807 => x"00048513", |
00000808 => x"f91ff0ef", |
00000809 => x"fc9ff06f", |
00000810 => x"00757513", |
00000811 => x"00177793", |
00000812 => x"01079793", |
00000813 => x"0036f693", |
00000814 => x"00a51513", |
00000815 => x"00f56533", |
00000816 => x"00167613", |
00000817 => x"00e69793", |
00000818 => x"0015f593", |
00000819 => x"00f567b3", |
00000820 => x"00d61613", |
00000821 => x"00c7e7b3", |
00000822 => x"00959593", |
00000823 => x"fa800813", |
00000824 => x"00b7e7b3", |
00000825 => x"00082023", |
00000826 => x"1007e793", |
00000827 => x"00f82023", |
00000828 => x"00008067", |
00000829 => x"fa800713", |
00000830 => x"00072783", |
00000831 => x"eff7f793", |
00000832 => x"00f72023", |
00000833 => x"00008067", |
00000834 => x"fa800713", |
00000835 => x"00072683", |
00000836 => x"00757793", |
00000837 => x"00100513", |
00000838 => x"00f51533", |
00000839 => x"00d56533", |
00000840 => x"00a72023", |
00000841 => x"00008067", |
00000842 => x"fa800713", |
00000843 => x"00072683", |
00000844 => x"00757513", |
00000845 => x"00100793", |
00000846 => x"00a797b3", |
00000847 => x"fff7c793", |
00000848 => x"00d7f7b3", |
00000849 => x"00f72023", |
00000850 => x"00008067", |
00000851 => x"faa02623", |
00000852 => x"fa802783", |
00000853 => x"fe07cee3", |
00000854 => x"fac02503", |
00000855 => x"00008067", |
00000856 => x"f8400713", |
00000857 => x"00072683", |
00000858 => x"00f57793", |
00000859 => x"00100513", |
00000860 => x"00f51533", |
00000861 => x"00d54533", |
00000862 => x"00a72023", |
00000762 => x"faf02023", |
00000763 => x"00008067", |
00000764 => x"00170793", |
00000765 => x"01079713", |
00000766 => x"40a686b3", |
00000767 => x"01075713", |
00000768 => x"fadff06f", |
00000769 => x"ffe78513", |
00000770 => x"0fd57513", |
00000771 => x"00051a63", |
00000772 => x"00375713", |
00000773 => x"00178793", |
00000774 => x"0ff7f793", |
00000775 => x"fa1ff06f", |
00000776 => x"00175713", |
00000777 => x"ff1ff06f", |
00000778 => x"fa002783", |
00000779 => x"fe07cee3", |
00000780 => x"faa02223", |
00000781 => x"00008067", |
00000782 => x"fa402503", |
00000783 => x"fe055ee3", |
00000784 => x"0ff57513", |
00000785 => x"00008067", |
00000786 => x"ff010113", |
00000787 => x"00812423", |
00000788 => x"01212023", |
00000789 => x"00112623", |
00000790 => x"00912223", |
00000791 => x"00050413", |
00000792 => x"00a00913", |
00000793 => x"00044483", |
00000794 => x"00140413", |
00000795 => x"00049e63", |
00000796 => x"00c12083", |
00000797 => x"00812403", |
00000798 => x"00412483", |
00000799 => x"00012903", |
00000800 => x"01010113", |
00000801 => x"00008067", |
00000802 => x"01249663", |
00000803 => x"00d00513", |
00000804 => x"f99ff0ef", |
00000805 => x"00048513", |
00000806 => x"f91ff0ef", |
00000807 => x"fc9ff06f", |
00000808 => x"00757513", |
00000809 => x"00177793", |
00000810 => x"01079793", |
00000811 => x"0036f693", |
00000812 => x"00a51513", |
00000813 => x"00f56533", |
00000814 => x"00167613", |
00000815 => x"00e69793", |
00000816 => x"0015f593", |
00000817 => x"00f567b3", |
00000818 => x"00d61613", |
00000819 => x"00c7e7b3", |
00000820 => x"00959593", |
00000821 => x"fa800813", |
00000822 => x"00b7e7b3", |
00000823 => x"00082023", |
00000824 => x"1007e793", |
00000825 => x"00f82023", |
00000826 => x"00008067", |
00000827 => x"fa800713", |
00000828 => x"00072783", |
00000829 => x"eff7f793", |
00000830 => x"00f72023", |
00000831 => x"00008067", |
00000832 => x"fa800713", |
00000833 => x"00072683", |
00000834 => x"00757793", |
00000835 => x"00100513", |
00000836 => x"00f51533", |
00000837 => x"00d56533", |
00000838 => x"00a72023", |
00000839 => x"00008067", |
00000840 => x"fa800713", |
00000841 => x"00072683", |
00000842 => x"00757513", |
00000843 => x"00100793", |
00000844 => x"00a797b3", |
00000845 => x"fff7c793", |
00000846 => x"00d7f7b3", |
00000847 => x"00f72023", |
00000848 => x"00008067", |
00000849 => x"faa02623", |
00000850 => x"fa802783", |
00000851 => x"fe07cee3", |
00000852 => x"fac02503", |
00000853 => x"00008067", |
00000854 => x"f8400713", |
00000855 => x"00072683", |
00000856 => x"00f57793", |
00000857 => x"00100513", |
00000858 => x"00f51533", |
00000859 => x"00d54533", |
00000860 => x"00a72023", |
00000861 => x"00008067", |
00000862 => x"f8a02223", |
00000863 => x"00008067", |
00000864 => x"f8a02223", |
00000865 => x"00008067", |
00000866 => x"fb800713", |
00000867 => x"00072783", |
00000868 => x"ffe7f793", |
00000869 => x"00f72023", |
00000870 => x"00008067", |
00000871 => x"fb000713", |
00000872 => x"00072783", |
00000873 => x"ff77f793", |
00000874 => x"00f72023", |
00000875 => x"00008067", |
00000876 => x"f8800713", |
00000877 => x"00072783", |
00000878 => x"fef7f793", |
00000879 => x"00f72023", |
00000880 => x"00008067", |
00000881 => x"69617641", |
00000882 => x"6c62616c", |
00000883 => x"4d432065", |
00000884 => x"0a3a7344", |
00000885 => x"203a6820", |
00000886 => x"706c6548", |
00000887 => x"3a72200a", |
00000888 => x"73655220", |
00000889 => x"74726174", |
00000890 => x"3a75200a", |
00000891 => x"6c705520", |
00000892 => x"0a64616f", |
00000893 => x"203a7320", |
00000894 => x"726f7453", |
00000895 => x"6f742065", |
00000896 => x"616c6620", |
00000897 => x"200a6873", |
00000898 => x"4c203a6c", |
00000899 => x"2064616f", |
00000900 => x"6d6f7266", |
00000901 => x"616c6620", |
00000902 => x"200a6873", |
00000903 => x"45203a65", |
00000904 => x"75636578", |
00000905 => x"00006574", |
00000906 => x"65206f4e", |
00000907 => x"75636578", |
00000908 => x"6c626174", |
00000909 => x"76612065", |
00000910 => x"616c6961", |
00000911 => x"2e656c62", |
00000912 => x"00000000", |
00000913 => x"746f6f42", |
00000914 => x"2e676e69", |
00000915 => x"0a0a2e2e", |
00000916 => x"00000000", |
00000917 => x"52450a07", |
00000918 => x"00005f52", |
00000919 => x"6e6b6e75", |
00000920 => x"006e776f", |
00000921 => x"00007830", |
00000922 => x"58450a0a", |
00000923 => x"54504543", |
00000924 => x"3a4e4f49", |
00000925 => x"00000020", |
00000926 => x"30204020", |
00000927 => x"00000078", |
00000928 => x"69617741", |
00000929 => x"676e6974", |
00000930 => x"6f656e20", |
00000931 => x"32337672", |
00000932 => x"6578655f", |
00000933 => x"6e69622e", |
00000934 => x"202e2e2e", |
00000935 => x"00000000", |
00000936 => x"64616f4c", |
00000937 => x"2e676e69", |
00000938 => x"00202e2e", |
00000939 => x"00004b4f", |
00000940 => x"74697257", |
00000941 => x"78302065", |
00000942 => x"00000000", |
00000943 => x"74796220", |
00000944 => x"74207365", |
00000945 => x"5053206f", |
00000946 => x"6c662049", |
00000947 => x"20687361", |
00000948 => x"78302040", |
00000949 => x"00000000", |
00000950 => x"7928203f", |
00000951 => x"20296e2f", |
00000952 => x"00000000", |
00000953 => x"616c460a", |
00000954 => x"6e696873", |
00000955 => x"2e2e2e67", |
00000956 => x"00000020", |
00000957 => x"0a0a0a0a", |
00000958 => x"4e203c3c", |
00000959 => x"56524f45", |
00000960 => x"42203233", |
00000961 => x"6c746f6f", |
00000962 => x"6564616f", |
00000963 => x"3e3e2072", |
00000964 => x"4c420a0a", |
00000965 => x"203a5644", |
00000966 => x"206c754a", |
00000967 => x"32203920", |
00000968 => x"0a303230", |
00000969 => x"3a565748", |
00000970 => x"00002020", |
00000971 => x"4b4c430a", |
00000972 => x"0020203a", |
00000973 => x"0a7a4820", |
00000974 => x"4449484d", |
00000975 => x"0000203a", |
00000976 => x"53494d0a", |
00000977 => x"00203a41", |
00000978 => x"4e4f430a", |
00000979 => x"00203a46", |
00000980 => x"454d490a", |
00000981 => x"00203a4d", |
00000982 => x"74796220", |
00000983 => x"40207365", |
00000984 => x"00000020", |
00000985 => x"454d440a", |
00000986 => x"00203a4d", |
00000987 => x"75410a0a", |
00000988 => x"6f626f74", |
00000989 => x"6920746f", |
00000990 => x"7338206e", |
00000991 => x"7250202e", |
00000992 => x"20737365", |
00000993 => x"2079656b", |
00000994 => x"61206f74", |
00000995 => x"74726f62", |
00000996 => x"00000a2e", |
00000997 => x"0000000a", |
00000998 => x"726f6241", |
00000999 => x"2e646574", |
00001000 => x"00000a0a", |
00001001 => x"444d430a", |
00001002 => x"00203e3a", |
00001003 => x"53207962", |
00001004 => x"68706574", |
00001005 => x"4e206e61", |
00001006 => x"69746c6f", |
00001007 => x"0000676e", |
00001008 => x"61766e49", |
00001009 => x"2064696c", |
00001010 => x"00444d43", |
00001011 => x"33323130", |
00001012 => x"37363534", |
00001013 => x"42413938", |
00001014 => x"46454443", |
00000864 => x"fb800713", |
00000865 => x"00072783", |
00000866 => x"ffe7f793", |
00000867 => x"00f72023", |
00000868 => x"00008067", |
00000869 => x"fb000713", |
00000870 => x"00072783", |
00000871 => x"ff77f793", |
00000872 => x"00f72023", |
00000873 => x"00008067", |
00000874 => x"f8800713", |
00000875 => x"00072783", |
00000876 => x"fef7f793", |
00000877 => x"00f72023", |
00000878 => x"00008067", |
00000879 => x"69617641", |
00000880 => x"6c62616c", |
00000881 => x"4d432065", |
00000882 => x"0a3a7344", |
00000883 => x"203a6820", |
00000884 => x"706c6548", |
00000885 => x"3a72200a", |
00000886 => x"73655220", |
00000887 => x"74726174", |
00000888 => x"3a75200a", |
00000889 => x"6c705520", |
00000890 => x"0a64616f", |
00000891 => x"203a7320", |
00000892 => x"726f7453", |
00000893 => x"6f742065", |
00000894 => x"616c6620", |
00000895 => x"200a6873", |
00000896 => x"4c203a6c", |
00000897 => x"2064616f", |
00000898 => x"6d6f7266", |
00000899 => x"616c6620", |
00000900 => x"200a6873", |
00000901 => x"45203a65", |
00000902 => x"75636578", |
00000903 => x"00006574", |
00000904 => x"65206f4e", |
00000905 => x"75636578", |
00000906 => x"6c626174", |
00000907 => x"76612065", |
00000908 => x"616c6961", |
00000909 => x"2e656c62", |
00000910 => x"00000000", |
00000911 => x"746f6f42", |
00000912 => x"2e676e69", |
00000913 => x"0a0a2e2e", |
00000914 => x"00000000", |
00000915 => x"52450a07", |
00000916 => x"00005f52", |
00000917 => x"6e6b6e75", |
00000918 => x"006e776f", |
00000919 => x"00007830", |
00000920 => x"58450a0a", |
00000921 => x"54504543", |
00000922 => x"3a4e4f49", |
00000923 => x"00000020", |
00000924 => x"30204020", |
00000925 => x"00000078", |
00000926 => x"69617741", |
00000927 => x"676e6974", |
00000928 => x"6f656e20", |
00000929 => x"32337672", |
00000930 => x"6578655f", |
00000931 => x"6e69622e", |
00000932 => x"202e2e2e", |
00000933 => x"00000000", |
00000934 => x"64616f4c", |
00000935 => x"2e676e69", |
00000936 => x"00202e2e", |
00000937 => x"00004b4f", |
00000938 => x"74697257", |
00000939 => x"78302065", |
00000940 => x"00000000", |
00000941 => x"74796220", |
00000942 => x"74207365", |
00000943 => x"5053206f", |
00000944 => x"6c662049", |
00000945 => x"20687361", |
00000946 => x"78302040", |
00000947 => x"00000000", |
00000948 => x"7928203f", |
00000949 => x"20296e2f", |
00000950 => x"00000000", |
00000951 => x"616c460a", |
00000952 => x"6e696873", |
00000953 => x"2e2e2e67", |
00000954 => x"00000020", |
00000955 => x"0a0a0a0a", |
00000956 => x"4e203c3c", |
00000957 => x"56524f45", |
00000958 => x"42203233", |
00000959 => x"6c746f6f", |
00000960 => x"6564616f", |
00000961 => x"3e3e2072", |
00000962 => x"4c420a0a", |
00000963 => x"203a5644", |
00000964 => x"206c754a", |
00000965 => x"32203032", |
00000966 => x"0a303230", |
00000967 => x"3a565748", |
00000968 => x"00002020", |
00000969 => x"4b4c430a", |
00000970 => x"0020203a", |
00000971 => x"0a7a4820", |
00000972 => x"52455355", |
00000973 => x"0000203a", |
00000974 => x"53494d0a", |
00000975 => x"00203a41", |
00000976 => x"4e4f430a", |
00000977 => x"00203a46", |
00000978 => x"454d490a", |
00000979 => x"00203a4d", |
00000980 => x"74796220", |
00000981 => x"40207365", |
00000982 => x"00000020", |
00000983 => x"454d440a", |
00000984 => x"00203a4d", |
00000985 => x"75410a0a", |
00000986 => x"6f626f74", |
00000987 => x"6920746f", |
00000988 => x"7338206e", |
00000989 => x"7250202e", |
00000990 => x"20737365", |
00000991 => x"2079656b", |
00000992 => x"61206f74", |
00000993 => x"74726f62", |
00000994 => x"00000a2e", |
00000995 => x"0000000a", |
00000996 => x"726f6241", |
00000997 => x"2e646574", |
00000998 => x"00000a0a", |
00000999 => x"444d430a", |
00001000 => x"00203e3a", |
00001001 => x"53207962", |
00001002 => x"68706574", |
00001003 => x"4e206e61", |
00001004 => x"69746c6f", |
00001005 => x"0000676e", |
00001006 => x"61766e49", |
00001007 => x"2064696c", |
00001008 => x"00444d43", |
00001009 => x"33323130", |
00001010 => x"37363534", |
00001011 => x"42413938", |
00001012 => x"46454443", |
others => x"00000000" |
); |
|
/neorv32/trunk/rtl/core/neorv32_busswitch.vhd
0,0 → 1,278
-- ################################################################################################# |
-- # << NEORV32 - Bus Switch >> # |
-- # ********************************************************************************************* # |
-- # Allows to access a single peripheral bus ("p_bus") by two controller busses. Controller port # |
-- # A ("ca_bus") has priority over controller port B ("cb_bus"). # |
-- # ********************************************************************************************* # |
-- # BSD 3-Clause License # |
-- # # |
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. # |
-- # # |
-- # Redistribution and use in source and binary forms, with or without modification, are # |
-- # permitted provided that the following conditions are met: # |
-- # # |
-- # 1. Redistributions of source code must retain the above copyright notice, this list of # |
-- # conditions and the following disclaimer. # |
-- # # |
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # |
-- # conditions and the following disclaimer in the documentation and/or other materials # |
-- # provided with the distribution. # |
-- # # |
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # |
-- # endorse or promote products derived from this software without specific prior written # |
-- # permission. # |
-- # # |
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # |
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # |
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # |
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # |
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # |
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # |
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # |
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # |
-- # OF THE POSSIBILITY OF SUCH DAMAGE. # |
-- # ********************************************************************************************* # |
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # |
-- ################################################################################################# |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |
|
library neorv32; |
use neorv32.neorv32_package.all; |
|
entity neorv32_busswitch is |
generic ( |
PORT_CA_READ_ONLY : boolean := false; -- set if controller port A is read-only |
PORT_CB_READ_ONLY : boolean := false -- set if controller port B is read-only |
); |
port ( |
-- global control -- |
clk_i : in std_ulogic; -- global clock, rising edge |
rstn_i : in std_ulogic; -- global reset, low-active, async |
-- controller interface a -- |
ca_bus_addr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
ca_bus_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
ca_bus_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
ca_bus_ben_i : in std_ulogic_vector(03 downto 0); -- byte enable |
ca_bus_we_i : in std_ulogic; -- write enable |
ca_bus_re_i : in std_ulogic; -- read enable |
ca_bus_cancel_i : in std_ulogic; -- cancel current bus transaction |
ca_bus_ack_o : out std_ulogic; -- bus transfer acknowledge |
ca_bus_err_o : out std_ulogic; -- bus transfer error |
-- controller interface b -- |
cb_bus_addr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
cb_bus_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
cb_bus_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
cb_bus_ben_i : in std_ulogic_vector(03 downto 0); -- byte enable |
cb_bus_we_i : in std_ulogic; -- write enable |
cb_bus_re_i : in std_ulogic; -- read enable |
cb_bus_cancel_i : in std_ulogic; -- cancel current bus transaction |
cb_bus_ack_o : out std_ulogic; -- bus transfer acknowledge |
cb_bus_err_o : out std_ulogic; -- bus transfer error |
-- peripheral bus -- |
p_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
p_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
p_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
p_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable |
p_bus_we_o : out std_ulogic; -- write enable |
p_bus_re_o : out std_ulogic; -- read enable |
p_bus_cancel_o : out std_ulogic; -- cancel current bus transaction |
p_bus_ack_i : in std_ulogic; -- bus transfer acknowledge |
p_bus_err_i : in std_ulogic -- bus transfer error |
); |
end neorv32_busswitch; |
|
architecture neorv32_busswitch_rtl of neorv32_busswitch is |
|
-- access buffer -- |
signal ca_rd_req_buf : std_ulogic; |
signal ca_wr_req_buf : std_ulogic; |
signal cb_rd_req_buf : std_ulogic; |
signal cb_wr_req_buf : std_ulogic; |
|
-- access requests -- |
signal ca_req_current : std_ulogic; |
signal cb_req_current : std_ulogic; |
signal ca_req_buffered : std_ulogic; |
signal cb_req_buffered : std_ulogic; |
|
-- internal bus lines -- |
signal ca_bus_ack : std_ulogic; |
signal cb_bus_ack : std_ulogic; |
signal ca_bus_err : std_ulogic; |
signal cb_bus_err : std_ulogic; |
signal p_bus_we : std_ulogic; |
signal p_bus_re : std_ulogic; |
|
-- access arbiter -- |
type arbiter_state_t is (IDLE, BUSY, RETIRE, BUSY_SWITCHED, RETIRE_SWITCHED); |
type arbiter_t is record |
state : arbiter_state_t; |
state_nxt : arbiter_state_t; |
bus_sel : std_ulogic; |
re_trig : std_ulogic; |
we_trig : std_ulogic; |
end record; |
signal arbiter : arbiter_t; |
|
begin |
|
-- Access Buffer -------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
access_buffer: process(rstn_i, clk_i) |
begin |
if (rstn_i = '0') then |
ca_rd_req_buf <= '0'; |
ca_wr_req_buf <= '0'; |
cb_rd_req_buf <= '0'; |
cb_wr_req_buf <= '0'; |
elsif rising_edge(clk_i) then |
|
-- controller A requests -- |
if (ca_rd_req_buf = '0') and (ca_wr_req_buf = '0') then -- idle |
ca_rd_req_buf <= ca_bus_re_i; |
ca_wr_req_buf <= ca_bus_we_i; |
elsif (ca_bus_cancel_i = '1') or -- controller cancels access |
(ca_bus_err = '1') or -- peripheral cancels access |
(ca_bus_ack = '1') then -- normal termination |
ca_rd_req_buf <= '0'; |
ca_wr_req_buf <= '0'; |
end if; |
|
-- controller B requests -- |
if (cb_rd_req_buf = '0') and (cb_wr_req_buf = '0') then |
cb_rd_req_buf <= cb_bus_re_i; |
cb_wr_req_buf <= cb_bus_we_i; |
elsif (cb_bus_cancel_i = '1') or -- controller cancels access |
(cb_bus_err = '1') or -- peripheral cancels access |
(cb_bus_ack = '1') then -- normal termination |
cb_rd_req_buf <= '0'; |
cb_wr_req_buf <= '0'; |
end if; |
|
end if; |
end process access_buffer; |
|
-- any current requests? -- |
ca_req_current <= (ca_bus_re_i or ca_bus_we_i) when (PORT_CA_READ_ONLY = false) else ca_bus_re_i; |
cb_req_current <= (cb_bus_re_i or cb_bus_we_i) when (PORT_CB_READ_ONLY = false) else cb_bus_re_i; |
|
-- any buffered requests? -- |
ca_req_buffered <= (ca_rd_req_buf or ca_wr_req_buf) when (PORT_CA_READ_ONLY = false) else ca_rd_req_buf; |
cb_req_buffered <= (cb_rd_req_buf or cb_wr_req_buf) when (PORT_CB_READ_ONLY = false) else cb_rd_req_buf; |
|
|
-- Access Arbiter Sync -------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
-- for registers that require a specific reset state -- |
arbiter_sync: process(rstn_i, clk_i) |
begin |
if (rstn_i = '0') then |
arbiter.state <= IDLE; |
elsif rising_edge(clk_i) then |
arbiter.state <= arbiter.state_nxt; |
end if; |
end process arbiter_sync; |
|
|
-- Peripheral Bus Arbiter ----------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
arbiter_comb: process(arbiter, ca_req_current, cb_req_current, ca_req_buffered, cb_req_buffered, |
ca_rd_req_buf, ca_wr_req_buf, cb_rd_req_buf, cb_wr_req_buf, |
ca_bus_cancel_i, cb_bus_cancel_i, p_bus_ack_i, p_bus_err_i) |
begin |
-- arbiter defaults -- |
arbiter.state_nxt <= arbiter.state; |
arbiter.bus_sel <= '0'; |
arbiter.we_trig <= '0'; |
arbiter.re_trig <= '0'; |
|
-- state machine -- |
case arbiter.state is |
|
when IDLE => -- Controller a has full bus access |
-- ------------------------------------------------------------ |
if (ca_req_current = '1') then -- current request? |
arbiter.bus_sel <= '0'; |
arbiter.state_nxt <= BUSY; |
elsif (ca_req_buffered = '1') then -- buffered request? |
arbiter.bus_sel <= '0'; |
arbiter.state_nxt <= RETIRE; |
elsif (cb_req_current = '1') then -- current request from controller b? |
arbiter.bus_sel <= '1'; |
arbiter.state_nxt <= BUSY_SWITCHED; |
elsif (cb_req_buffered = '1') then -- buffered request from controller b? |
arbiter.bus_sel <= '1'; |
arbiter.state_nxt <= RETIRE_SWITCHED; |
end if; |
|
when BUSY => -- transaction in progress |
-- ------------------------------------------------------------ |
arbiter.bus_sel <= '0'; |
if (ca_bus_cancel_i = '1') or -- controller cancels access |
(p_bus_err_i = '1') or -- peripheral cancels access |
(p_bus_ack_i = '1') then -- normal termination |
arbiter.state_nxt <= IDLE; |
end if; |
|
when RETIRE => -- retire pending access |
-- ------------------------------------------------------------ |
arbiter.bus_sel <= '0'; |
if (PORT_CA_READ_ONLY = false) then |
arbiter.we_trig <= ca_wr_req_buf; |
end if; |
arbiter.re_trig <= ca_rd_req_buf; |
arbiter.state_nxt <= BUSY; |
|
when BUSY_SWITCHED => -- switched transaction in progress |
-- ------------------------------------------------------------ |
arbiter.bus_sel <= '1'; |
if (cb_bus_cancel_i = '1') or -- controller cancels access |
(p_bus_err_i = '1') or -- peripheral cancels access |
(p_bus_ack_i = '1') then -- normal termination |
arbiter.state_nxt <= IDLE; |
end if; |
|
when RETIRE_SWITCHED => -- retire pending switched access |
-- ------------------------------------------------------------ |
arbiter.bus_sel <= '1'; |
if (PORT_CB_READ_ONLY = false) then |
arbiter.we_trig <= cb_wr_req_buf; |
end if; |
arbiter.re_trig <= cb_rd_req_buf; |
arbiter.state_nxt <= BUSY_SWITCHED; |
|
end case; |
end process arbiter_comb; |
|
|
-- Peripheral Bus Switch ------------------------------------------------------------------ |
-- ------------------------------------------------------------------------------------------- |
p_bus_addr_o <= ca_bus_addr_i when (arbiter.bus_sel = '0') else cb_bus_addr_i; |
p_bus_wdata_o <= cb_bus_wdata_i when (PORT_CA_READ_ONLY = true) else ca_bus_wdata_i when (PORT_CB_READ_ONLY = true) else |
ca_bus_wdata_i when (arbiter.bus_sel = '0') else cb_bus_wdata_i; |
p_bus_ben_o <= cb_bus_ben_i when (PORT_CA_READ_ONLY = true) else ca_bus_ben_i when (PORT_CB_READ_ONLY = true) else |
ca_bus_ben_i when (arbiter.bus_sel = '0') else cb_bus_ben_i; |
p_bus_we <= ca_bus_we_i when (arbiter.bus_sel = '0') else cb_bus_we_i; |
p_bus_re <= ca_bus_re_i when (arbiter.bus_sel = '0') else cb_bus_re_i; |
p_bus_cancel_o <= ca_bus_cancel_i when (arbiter.bus_sel = '0') else cb_bus_cancel_i; |
p_bus_we_o <= (p_bus_we or arbiter.we_trig); |
p_bus_re_o <= (p_bus_re or arbiter.re_trig); |
|
ca_bus_rdata_o <= p_bus_rdata_i; |
cb_bus_rdata_o <= p_bus_rdata_i; |
|
ca_bus_ack <= p_bus_ack_i and (not arbiter.bus_sel); |
cb_bus_ack <= p_bus_ack_i and ( arbiter.bus_sel); |
ca_bus_ack_o <= ca_bus_ack; |
cb_bus_ack_o <= cb_bus_ack; |
|
ca_bus_err <= p_bus_err_i and (not arbiter.bus_sel); |
cb_bus_err <= p_bus_err_i and ( arbiter.bus_sel); |
ca_bus_err_o <= ca_bus_err; |
cb_bus_err_o <= cb_bus_err; |
|
|
end neorv32_busswitch_rtl; |
/neorv32/trunk/rtl/core/neorv32_cpu.vhd
2,10 → 2,10
-- # << NEORV32 - CPU Top Entity >> # |
-- # ********************************************************************************************* # |
-- # Top NEORV32 CPU: # |
-- # * neorv32_cpu_alu: Arithemtical/logical unit # |
-- # * neorv32_cpu_alu: Arithemtic/logic unit # |
-- # * neorv32_cpu_ctrl: CPU control and CSR system # |
-- # * neorv32_cpu_decompressor: Compressed instructions decoder # |
-- # * neorv32_cpu_bus: Memory/IO bus interface unit # |
-- # * neorv32_cpu_bus: Instruction and data bus interface unit # |
-- # * neorv32_cpu_cp_muldiv: MULDIV co-processor # |
-- # * neorv32_cpu_regfile: Data register file # |
-- # ********************************************************************************************* # |
50,61 → 50,50
entity neorv32_cpu is |
generic ( |
-- General -- |
CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz |
HART_ID : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom hardware thread ID |
BOOTLOADER_USE : boolean := true; -- implement processor-internal bootloader? |
CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])? |
CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])? |
HW_THREAD_ID : std_ulogic_vector(31 downto 0):= x"00000000"; -- hardware thread id |
CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0):= x"00000000"; -- cpu boot address |
-- RISC-V CPU Extensions -- |
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension? |
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension? |
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension? |
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system? |
CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.? |
-- Memory configuration: Instruction memory -- |
MEM_ISPACE_BASE : std_ulogic_vector(31 downto 0) := x"00000000"; -- base address of instruction memory space |
MEM_ISPACE_SIZE : natural := 8*1024; -- total size of instruction memory space in byte |
MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory |
MEM_INT_IMEM_SIZE : natural := 8*1024; -- size of processor-internal instruction memory in bytes |
MEM_INT_IMEM_ROM : boolean := false; -- implement processor-internal instruction memory as ROM |
-- Memory configuration: Data memory -- |
MEM_DSPACE_BASE : std_ulogic_vector(31 downto 0) := x"80000000"; -- base address of data memory space |
MEM_DSPACE_SIZE : natural := 4*1024; -- total size of data memory space in byte |
MEM_INT_DMEM_USE : boolean := true; -- implement processor-internal data memory |
MEM_INT_DMEM_SIZE : natural := 4*1024; -- size of processor-internal data memory in bytes |
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension? |
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension? |
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension? |
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system? |
CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.? |
-- Memory configuration: External memory interface -- |
MEM_EXT_USE : boolean := false; -- implement external memory bus interface? |
MEM_EXT_TIMEOUT : natural := 15; -- cycles after which a valid bus access will timeout |
-- Processor peripherals -- |
IO_GPIO_USE : boolean := true; -- implement general purpose input/output port unit (GPIO)? |
IO_MTIME_USE : boolean := true; -- implement machine system timer (MTIME)? |
IO_UART_USE : boolean := true; -- implement universal asynchronous receiver/transmitter (UART)? |
IO_SPI_USE : boolean := true; -- implement serial peripheral interface (SPI)? |
IO_TWI_USE : boolean := true; -- implement two-wire interface (TWI)? |
IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)? |
IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)? |
IO_CLIC_USE : boolean := true; -- implement core local interrupt controller (CLIC)? |
IO_TRNG_USE : boolean := true; -- implement true random number generator (TRNG)? |
IO_DEVNULL_USE : boolean := true -- implement dummy device (DEVNULL)? |
MEM_EXT_TIMEOUT : natural := 15 -- cycles after which a valid bus access will timeout |
); |
port ( |
-- global control -- |
clk_i : in std_ulogic; -- global clock, rising edge |
rstn_i : in std_ulogic; -- global reset, low-active, async |
-- bus interface -- |
bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable |
bus_we_o : out std_ulogic; -- write enable |
bus_re_o : out std_ulogic; -- read enable |
bus_cancel_o : out std_ulogic; -- cancel current bus transaction |
bus_ack_i : in std_ulogic; -- bus transfer acknowledge |
bus_err_i : in std_ulogic; -- bus transfer error |
clk_i : in std_ulogic; -- global clock, rising edge |
rstn_i : in std_ulogic; -- global reset, low-active, async |
-- instruction bus interface -- |
i_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
i_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
i_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable |
i_bus_we_o : out std_ulogic; -- write enable |
i_bus_re_o : out std_ulogic; -- read enable |
i_bus_cancel_o : out std_ulogic; -- cancel current bus transaction |
i_bus_ack_i : in std_ulogic; -- bus transfer acknowledge |
i_bus_err_i : in std_ulogic; -- bus transfer error |
i_bus_fence_o : out std_ulogic; -- executed FENCEI operation |
-- data bus interface -- |
d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable |
d_bus_we_o : out std_ulogic; -- write enable |
d_bus_re_o : out std_ulogic; -- read enable |
d_bus_cancel_o : out std_ulogic; -- cancel current bus transaction |
d_bus_ack_i : in std_ulogic; -- bus transfer acknowledge |
d_bus_err_i : in std_ulogic; -- bus transfer error |
d_bus_fence_o : out std_ulogic; -- executed FENCE operation |
-- system time input from MTIME -- |
time_i : in std_ulogic_vector(63 downto 0); -- current system time |
time_i : in std_ulogic_vector(63 downto 0); -- current system time |
-- external interrupts -- |
clic_irq_i : in std_ulogic; -- CLIC interrupt request |
mtime_irq_i : in std_ulogic -- machine timer interrupt |
msw_irq_i : in std_ulogic; -- software interrupt |
clic_irq_i : in std_ulogic; -- CLIC interrupt request |
mtime_irq_i : in std_ulogic -- machine timer interrupt |
); |
end neorv32_cpu; |
|
111,28 → 100,28
architecture neorv32_cpu_rtl of neorv32_cpu is |
|
-- local signals -- |
signal ctrl : std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus |
signal alu_cmp : std_ulogic_vector(1 downto 0); -- alu comparator result |
signal imm : std_ulogic_vector(data_width_c-1 downto 0); -- immediate |
signal instr : std_ulogic_vector(data_width_c-1 downto 0); -- new instruction |
signal rs1, rs2 : std_ulogic_vector(data_width_c-1 downto 0); -- source registers |
signal alu_res : std_ulogic_vector(data_width_c-1 downto 0); -- alu result |
signal alu_add : std_ulogic_vector(data_width_c-1 downto 0); -- alu adder result |
signal rdata : std_ulogic_vector(data_width_c-1 downto 0); -- memory read data |
signal alu_wait : std_ulogic; -- alu is busy due to iterative unit |
signal bus_wait : std_ulogic; -- wait for bus to finish operation |
signal csr_rdata : std_ulogic_vector(data_width_c-1 downto 0); -- csr read data |
signal mar : std_ulogic_vector(data_width_c-1 downto 0); -- current memory address register |
signal ma_instr : std_ulogic; -- misaligned instruction address |
signal ma_load : std_ulogic; -- misaligned load data address |
signal ma_store : std_ulogic; -- misaligned store data address |
signal be_instr : std_ulogic; -- bus error on instruction access |
signal be_load : std_ulogic; -- bus error on load data access |
signal be_store : std_ulogic; -- bus error on store data access |
signal bus_busy : std_ulogic; -- bus unit is busy |
signal fetch_pc : std_ulogic_vector(data_width_c-1 downto 0); -- pc for instruction fetch |
signal curr_pc : std_ulogic_vector(data_width_c-1 downto 0); -- current pc (for current executed instruction) |
signal next_pc : std_ulogic_vector(data_width_c-1 downto 0); -- next pc (for current executed instruction) |
signal ctrl : std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus |
signal alu_cmp : std_ulogic_vector(1 downto 0); -- alu comparator result |
signal imm : std_ulogic_vector(data_width_c-1 downto 0); -- immediate |
signal instr : std_ulogic_vector(data_width_c-1 downto 0); -- new instruction |
signal rs1, rs2 : std_ulogic_vector(data_width_c-1 downto 0); -- source registers |
signal alu_res : std_ulogic_vector(data_width_c-1 downto 0); -- alu result |
signal alu_add : std_ulogic_vector(data_width_c-1 downto 0); -- alu adder result |
signal rdata : std_ulogic_vector(data_width_c-1 downto 0); -- memory read data |
signal alu_wait : std_ulogic; -- alu is busy due to iterative unit |
signal bus_i_wait : std_ulogic; -- wait for current bus instruction fetch |
signal bus_d_wait : std_ulogic; -- wait for current bus data access |
signal csr_rdata : std_ulogic_vector(data_width_c-1 downto 0); -- csr read data |
signal mar : std_ulogic_vector(data_width_c-1 downto 0); -- current memory address register |
signal ma_instr : std_ulogic; -- misaligned instruction address |
signal ma_load : std_ulogic; -- misaligned load data address |
signal ma_store : std_ulogic; -- misaligned store data address |
signal be_instr : std_ulogic; -- bus error on instruction access |
signal be_load : std_ulogic; -- bus error on load data access |
signal be_store : std_ulogic; -- bus error on store data access |
signal fetch_pc : std_ulogic_vector(data_width_c-1 downto 0); -- pc for instruction fetch |
signal curr_pc : std_ulogic_vector(data_width_c-1 downto 0); -- current pc (for current executed instruction) |
signal next_pc : std_ulogic_vector(data_width_c-1 downto 0); -- next pc (for current executed instruction) |
|
-- co-processor interface -- |
signal cp0_data, cp1_data : std_ulogic_vector(data_width_c-1 downto 0); |
145,40 → 134,15
neorv32_cpu_control_inst: neorv32_cpu_control |
generic map ( |
-- General -- |
CLOCK_FREQUENCY => CLOCK_FREQUENCY, -- clock frequency of clk_i in Hz |
HART_ID => HART_ID, -- custom hardware thread ID |
BOOTLOADER_USE => BOOTLOADER_USE, -- implement processor-internal bootloader? |
CSR_COUNTERS_USE => CSR_COUNTERS_USE, -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])? |
HW_THREAD_ID => HW_THREAD_ID, -- hardware thread id |
CPU_BOOT_ADDR => CPU_BOOT_ADDR, -- cpu boot address |
-- RISC-V CPU Extensions -- |
CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension? |
CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E, -- implement embedded RF extension? |
CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement muld/div extension? |
CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr, -- implement CSR system? |
CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.? |
-- Memory configuration: Instruction memory -- |
MEM_ISPACE_BASE => MEM_ISPACE_BASE, -- base address of instruction memory space |
MEM_ISPACE_SIZE => MEM_ISPACE_SIZE, -- total size of instruction memory space in byte |
MEM_INT_IMEM_USE => MEM_INT_IMEM_USE, -- implement processor-internal instruction memory |
MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes |
MEM_INT_IMEM_ROM => MEM_INT_IMEM_ROM, -- implement processor-internal instruction memory as ROM |
-- Memory configuration: Data memory -- |
MEM_DSPACE_BASE => MEM_DSPACE_BASE, -- base address of data memory space |
MEM_DSPACE_SIZE => MEM_DSPACE_SIZE, -- total size of data memory space in byte |
MEM_INT_DMEM_USE => MEM_INT_DMEM_USE, -- implement processor-internal data memory |
MEM_INT_DMEM_SIZE => MEM_INT_DMEM_SIZE, -- size of processor-internal data memory in bytes |
-- Memory configuration: External memory interface -- |
MEM_EXT_USE => MEM_EXT_USE, -- implement external memory bus interface? |
-- Processor peripherals -- |
IO_GPIO_USE => IO_GPIO_USE, -- implement general purpose input/output port unit (GPIO)? |
IO_MTIME_USE => IO_MTIME_USE, -- implement machine system timer (MTIME)? |
IO_UART_USE => IO_UART_USE, -- implement universal asynchronous receiver/transmitter (UART)? |
IO_SPI_USE => IO_SPI_USE, -- implement serial peripheral interface (SPI)? |
IO_TWI_USE => IO_TWI_USE, -- implement two-wire interface (TWI)? |
IO_PWM_USE => IO_PWM_USE, -- implement pulse-width modulation unit (PWM)? |
IO_WDT_USE => IO_WDT_USE, -- implement watch dog timer (WDT)? |
IO_CLIC_USE => IO_CLIC_USE, -- implement core local interrupt controller (CLIC)? |
IO_TRNG_USE => IO_TRNG_USE, -- implement true random number generator (TRNG)? |
IO_DEVNULL_USE => IO_DEVNULL_USE -- implement dummy device (DEVNULL)? |
CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension? |
CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E, -- implement embedded RF extension? |
CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement muld/div extension? |
CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr, -- implement CSR system? |
CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei -- implement instruction stream sync.? |
) |
port map ( |
-- global control -- |
187,7 → 151,8
ctrl_o => ctrl, -- main control bus |
-- status input -- |
alu_wait_i => alu_wait, -- wait for ALU |
bus_wait_i => bus_wait, -- wait for bus |
bus_i_wait_i => bus_i_wait, -- wait for bus |
bus_d_wait_i => bus_d_wait, -- wait for bus |
-- data input -- |
instr_i => instr, -- instruction |
cmp_i => alu_cmp, -- comparator status |
201,6 → 166,7
csr_wdata_i => alu_res, -- CSR write data |
csr_rdata_o => csr_rdata, -- CSR read data |
-- external interrupt -- |
msw_irq_i => msw_irq_i, -- software interrupt |
clic_irq_i => clic_irq_i, -- CLIC interrupt request |
mtime_irq_i => mtime_irq_i, -- machine timer interrupt |
-- system time input from MTIME -- |
212,8 → 178,7
ma_store_i => ma_store, -- misaligned store data address |
be_instr_i => be_instr, -- bus error on instruction access |
be_load_i => be_load, -- bus error on load data access |
be_store_i => be_store, -- bus error on store data access |
bus_busy_i => bus_busy -- bus unit is busy |
be_store_i => be_store -- bus error on store data access |
); |
|
|
301,7 → 266,7
cp1_valid <= '0'; |
|
|
-- Bus Unit ------------------------------------------------------------------------------- |
-- Bus Interface Unit --------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
neorv32_cpu_bus_inst: neorv32_cpu_bus |
generic map ( |
310,36 → 275,49
) |
port map ( |
-- global control -- |
clk_i => clk_i, -- global clock, rising edge |
rstn_i => rstn_i, -- global reset, low-active, async |
ctrl_i => ctrl, -- main control bus |
-- data input -- |
wdata_i => rs2, -- write data |
pc_i => fetch_pc, -- current PC for instruction fetch |
alu_i => alu_res, -- ALU result |
-- data output -- |
instr_o => instr, -- instruction |
rdata_o => rdata, -- read data |
-- status -- |
mar_o => mar, -- current memory address register |
ma_instr_o => ma_instr, -- misaligned instruction address |
ma_load_o => ma_load, -- misaligned load data address |
ma_store_o => ma_store, -- misaligned store data address |
be_instr_o => be_instr, -- bus error on instruction access |
be_load_o => be_load, -- bus error on load data access |
be_store_o => be_store, -- bus error on store data access |
bus_wait_o => bus_wait, -- wait for bus operation to finish |
bus_busy_o => bus_busy, -- bus unit is busy |
-- bus system -- |
bus_addr_o => bus_addr_o, -- bus access address |
bus_rdata_i => bus_rdata_i, -- bus read data |
bus_wdata_o => bus_wdata_o, -- bus write data |
bus_ben_o => bus_ben_o, -- byte enable |
bus_we_o => bus_we_o, -- write enable |
bus_re_o => bus_re_o, -- read enable |
bus_cancel_o => bus_cancel_o, -- cancel current bus transaction |
bus_ack_i => bus_ack_i, -- bus transfer acknowledge |
bus_err_i => bus_err_i -- bus transfer error |
clk_i => clk_i, -- global clock, rising edge |
rstn_i => rstn_i, -- global reset, low-active, async |
ctrl_i => ctrl, -- main control bus |
-- cpu instruction fetch interface -- |
fetch_pc_i => fetch_pc, -- PC for instruction fetch |
instr_o => instr, -- instruction |
i_wait_o => bus_i_wait, -- wait for fetch to complete |
-- |
ma_instr_o => ma_instr, -- misaligned instruction address |
be_instr_o => be_instr, -- bus error on instruction access |
-- cpu data access interface -- |
addr_i => alu_add, -- ALU.add result -> access address |
wdata_i => rs2, -- write data |
rdata_o => rdata, -- read data |
mar_o => mar, -- current memory address register |
d_wait_o => bus_d_wait, -- wait for access to complete |
-- |
ma_load_o => ma_load, -- misaligned load data address |
ma_store_o => ma_store, -- misaligned store data address |
be_load_o => be_load, -- bus error on load data access |
be_store_o => be_store, -- bus error on store data access |
-- instruction bus -- |
i_bus_addr_o => i_bus_addr_o, -- bus access address |
i_bus_rdata_i => i_bus_rdata_i, -- bus read data |
i_bus_wdata_o => i_bus_wdata_o, -- bus write data |
i_bus_ben_o => i_bus_ben_o, -- byte enable |
i_bus_we_o => i_bus_we_o, -- write enable |
i_bus_re_o => i_bus_re_o, -- read enable |
i_bus_cancel_o => i_bus_cancel_o, -- cancel current bus transaction |
i_bus_ack_i => i_bus_ack_i, -- bus transfer acknowledge |
i_bus_err_i => i_bus_err_i, -- bus transfer error |
i_bus_fence_o => i_bus_fence_o, -- fence operation |
-- data bus -- |
d_bus_addr_o => d_bus_addr_o, -- bus access address |
d_bus_rdata_i => d_bus_rdata_i, -- bus read data |
d_bus_wdata_o => d_bus_wdata_o, -- bus write data |
d_bus_ben_o => d_bus_ben_o, -- byte enable |
d_bus_we_o => d_bus_we_o, -- write enable |
d_bus_re_o => d_bus_re_o, -- read enable |
d_bus_cancel_o => d_bus_cancel_o, -- cancel current bus transaction |
d_bus_ack_i => d_bus_ack_i, -- bus transfer acknowledge |
d_bus_err_i => d_bus_err_i, -- bus transfer error |
d_bus_fence_o => d_bus_fence_o -- fence operation |
); |
|
|
/neorv32/trunk/rtl/core/neorv32_cpu_alu.vhd
88,12 → 88,15
signal cmp_less : std_ulogic; |
|
-- shifter -- |
signal shift_cmd : std_ulogic; |
signal shift_cmd_ff : std_ulogic; |
signal shift_start : std_ulogic; |
signal shift_run : std_ulogic; |
signal shift_cnt : std_ulogic_vector(4 downto 0); |
signal shift_sreg : std_ulogic_vector(data_width_c-1 downto 0); |
type shifter_t is record |
cmd : std_ulogic; |
cmd_ff : std_ulogic; |
start : std_ulogic; |
run : std_ulogic; |
cnt : std_ulogic_vector(4 downto 0); |
sreg : std_ulogic_vector(data_width_c-1 downto 0); |
end record; |
signal shifter : shifter_t; |
|
-- co-processor interface -- |
signal cp_cmd_ff : std_ulogic; |
110,25 → 113,17
input_op_mux: process(ctrl_i, csr_i, pc2_i, rs1_i, rs2_i, imm_i) |
begin |
-- opa (first ALU input operand) -- |
if (ctrl_i(ctrl_alu_opa_mux_msb_c) = '0') then |
if (ctrl_i(ctrl_alu_opa_mux_lsb_c) = '0') then |
opa <= rs1_i; |
else |
opa <= pc2_i; |
end if; |
else |
opa <= csr_i; |
end if; |
case ctrl_i(ctrl_alu_opa_mux_msb_c downto ctrl_alu_opa_mux_lsb_c) is |
when "00" => opa <= rs1_i; |
when "01" => opa <= pc2_i; |
when others => opa <= csr_i; |
end case; |
-- opb (second ALU input operand) -- |
if (ctrl_i(ctrl_alu_opb_mux_msb_c) = '0') then |
if (ctrl_i(ctrl_alu_opb_mux_lsb_c) = '0') then |
opb <= rs2_i; |
else |
opb <= imm_i; |
end if; |
else |
opb <= rs1_i; |
end if; |
case ctrl_i(ctrl_alu_opb_mux_msb_c downto ctrl_alu_opb_mux_lsb_c) is |
when "00" => opb <= rs2_i; |
when "01" => opb <= imm_i; |
when others => opb <= rs1_i; |
end case; |
-- opc (second operand for comparison (and SUB)) -- |
if (ctrl_i(ctrl_alu_opc_mux_c) = '0') then |
opc <= imm_i; |
166,20 → 161,34
shifter_unit: process(rstn_i, clk_i) |
begin |
if (rstn_i = '0') then |
shift_sreg <= (others => '0'); |
shift_cnt <= (others => '0'); |
shift_cmd_ff <= '0'; |
shifter.sreg <= (others => '0'); |
shifter.cnt <= (others => '0'); |
shifter.cmd_ff <= '0'; |
elsif rising_edge(clk_i) then |
shift_cmd_ff <= shift_cmd; |
if (shift_start = '1') then -- trigger new shift |
shift_sreg <= opa; -- shift operand |
shift_cnt <= opb(index_size_f(data_width_c)-1 downto 0); -- shift amount |
elsif (shift_run = '1') then -- running shift |
shift_cnt <= std_ulogic_vector(unsigned(shift_cnt) - 1); |
if (ctrl_i(ctrl_alu_shift_dir_c) = '0') then -- SLL: shift left logical |
shift_sreg <= shift_sreg(shift_sreg'left-1 downto 0) & '0'; |
else -- SRL: shift right logical / SRA: shift right arithmetical |
shift_sreg <= (shift_sreg(shift_sreg'left) and ctrl_i(ctrl_alu_shift_ar_c)) & shift_sreg(shift_sreg'left downto 1); |
shifter.cmd_ff <= shifter.cmd; |
if (shifter.start = '1') then -- trigger new shift |
shifter.sreg <= opa; -- shift operand |
shifter.cnt <= opb(index_size_f(data_width_c)-1 downto 0); -- shift amount |
elsif (shifter.run = '1') then -- running shift |
-- coarse shift -> multiples of 4 -- |
if (or_all_f(shifter.cnt(shifter.cnt'left downto 2)) = '1') then -- shift amount >= 4 |
shifter.cnt <= std_ulogic_vector(unsigned(shifter.cnt) - 4); |
if (ctrl_i(ctrl_alu_shift_dir_c) = '0') then -- SLL: shift left logical |
shifter.sreg <= shifter.sreg(shifter.sreg'left-4 downto 0) & "0000"; |
else -- SRL: shift right logical / SRA: shift right arithmetical |
shifter.sreg <= (shifter.sreg(shifter.sreg'left) and ctrl_i(ctrl_alu_shift_ar_c)) & |
(shifter.sreg(shifter.sreg'left) and ctrl_i(ctrl_alu_shift_ar_c)) & |
(shifter.sreg(shifter.sreg'left) and ctrl_i(ctrl_alu_shift_ar_c)) & |
(shifter.sreg(shifter.sreg'left) and ctrl_i(ctrl_alu_shift_ar_c)) & shifter.sreg(shifter.sreg'left downto 4); |
end if; |
-- fine shift -> 0..3 -- |
else |
shifter.cnt <= std_ulogic_vector(unsigned(shifter.cnt) - 1); |
if (ctrl_i(ctrl_alu_shift_dir_c) = '0') then -- SLL: shift left logical |
shifter.sreg <= shifter.sreg(shifter.sreg'left-1 downto 0) & '0'; |
else -- SRL: shift right logical / SRA: shift right arithmetical |
shifter.sreg <= (shifter.sreg(shifter.sreg'left) and ctrl_i(ctrl_alu_shift_ar_c)) & shifter.sreg(shifter.sreg'left downto 1); |
end if; |
end if; |
end if; |
end if; |
186,11 → 195,11
end process shifter_unit; |
|
-- is shift operation? -- |
shift_cmd <= '1' when (ctrl_i(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) = alu_cmd_shift_c) else '0'; |
shift_start <= '1' when (shift_cmd = '1') and (shift_cmd_ff = '0') else '0'; |
shifter.cmd <= '1' when (ctrl_i(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) = alu_cmd_shift_c) else '0'; |
shifter.start <= '1' when (shifter.cmd = '1') and (shifter.cmd_ff = '0') else '0'; |
|
-- shift operation running? -- |
shift_run <= '1' when (or_all_f(shift_cnt) = '1') or (shift_start = '1') else '0'; |
shifter.run <= '1' when (or_all_f(shifter.cnt) = '1') or (shifter.start = '1') else '0'; |
|
|
-- Coprocessor Interface ------------------------------------------------------------------ |
231,7 → 240,7
|
-- ALU Function Select -------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
alu_function_mux: process(ctrl_i, opa, opb, add_res, sub_res, cmp_less, shift_sreg) |
alu_function_mux: process(ctrl_i, opa, opb, add_res, sub_res, cmp_less, shifter) |
begin |
case ctrl_i(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) is |
when alu_cmd_bitc_c => alu_res <= opa and (not opb); -- bit clear (for CSR modifications only) |
240,7 → 249,7
when alu_cmd_and_c => alu_res <= opa and opb; |
when alu_cmd_sub_c => alu_res <= sub_res; |
when alu_cmd_add_c => alu_res <= add_res; |
when alu_cmd_shift_c => alu_res <= shift_sreg; |
when alu_cmd_shift_c => alu_res <= shifter.sreg; |
when alu_cmd_slt_c => alu_res <= (others => '0'); alu_res(0) <= cmp_less; |
when others => alu_res <= (others => '0'); -- undefined |
end case; |
249,7 → 258,7
|
-- ALU Result ----------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
wait_o <= shift_run or cp_run; -- wait until iterative units have completed |
wait_o <= shifter.run or cp_run; -- wait until iterative units have completed |
res_o <= (cp0_data_i or cp1_data_i) when (cp_rb_ff1 = '1') else alu_res; -- FIXME |
|
|
/neorv32/trunk/rtl/core/neorv32_cpu_bus.vhd
1,7 → 1,7
-- ################################################################################################# |
-- # << NEORV32 - Bus Interface Unit >> # |
-- # ********************************************************************************************* # |
-- # This unit connects the CPU to the memory/IO system. # |
-- # Instruction and data bus interfaces. # |
-- # ********************************************************************************************* # |
-- # BSD 3-Clause License # |
-- # # |
48,81 → 48,112
); |
port ( |
-- global control -- |
clk_i : in std_ulogic; -- global clock, rising edge |
rstn_i : in std_ulogic; -- global reset, low-active, async |
ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus |
-- data input -- |
wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- write data |
pc_i : in std_ulogic_vector(data_width_c-1 downto 0); -- current PC |
alu_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU result |
-- data output -- |
instr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- instruction |
rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- read data |
-- status -- |
mar_o : out std_ulogic_vector(data_width_c-1 downto 0); -- current memory address register |
ma_instr_o : out std_ulogic; -- misaligned instruction address |
ma_load_o : out std_ulogic; -- misaligned load data address |
ma_store_o : out std_ulogic; -- misaligned store data address |
be_instr_o : out std_ulogic; -- bus error on instruction access |
be_load_o : out std_ulogic; -- bus error on load data access |
be_store_o : out std_ulogic; -- bus error on store data access |
bus_wait_o : out std_ulogic; -- wait for bus operation to finish |
bus_busy_o : out std_ulogic; -- bus unit is busy |
-- bus system -- |
bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable |
bus_we_o : out std_ulogic; -- write enable |
bus_re_o : out std_ulogic; -- read enable |
bus_cancel_o : out std_ulogic; -- cancel current bus transaction |
bus_ack_i : in std_ulogic; -- bus transfer acknowledge |
bus_err_i : in std_ulogic -- bus transfer error |
clk_i : in std_ulogic; -- global clock, rising edge |
rstn_i : in std_ulogic; -- global reset, low-active, async |
ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus |
-- cpu instruction fetch interface -- |
fetch_pc_i : in std_ulogic_vector(data_width_c-1 downto 0); -- PC for instruction fetch |
instr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- instruction |
i_wait_o : out std_ulogic; -- wait for fetch to complete |
-- |
ma_instr_o : out std_ulogic; -- misaligned instruction address |
be_instr_o : out std_ulogic; -- bus error on instruction access |
-- cpu data access interface -- |
addr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU result -> access address |
wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- write data |
rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- read data |
mar_o : out std_ulogic_vector(data_width_c-1 downto 0); -- current memory address register |
d_wait_o : out std_ulogic; -- wait for access to complete |
-- |
ma_load_o : out std_ulogic; -- misaligned load data address |
ma_store_o : out std_ulogic; -- misaligned store data address |
be_load_o : out std_ulogic; -- bus error on load data access |
be_store_o : out std_ulogic; -- bus error on store data access |
-- instruction bus -- |
i_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
i_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
i_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable |
i_bus_we_o : out std_ulogic; -- write enable |
i_bus_re_o : out std_ulogic; -- read enable |
i_bus_cancel_o : out std_ulogic; -- cancel current bus transaction |
i_bus_ack_i : in std_ulogic; -- bus transfer acknowledge |
i_bus_err_i : in std_ulogic; -- bus transfer error |
i_bus_fence_o : out std_ulogic; -- fence operation |
-- data bus -- |
d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable |
d_bus_we_o : out std_ulogic; -- write enable |
d_bus_re_o : out std_ulogic; -- read enable |
d_bus_cancel_o : out std_ulogic; -- cancel current bus transaction |
d_bus_ack_i : in std_ulogic; -- bus transfer acknowledge |
d_bus_err_i : in std_ulogic; -- bus transfer error |
d_bus_fence_o : out std_ulogic -- fence operation |
); |
end neorv32_cpu_bus; |
|
architecture neorv32_cpu_bus_rtl of neorv32_cpu_bus is |
|
-- interface registers -- |
-- data interface registers -- |
signal mar, mdo, mdi : std_ulogic_vector(data_width_c-1 downto 0); |
|
-- bus request controller -- |
signal bus_busy : std_ulogic; |
signal bus_if_req : std_ulogic; |
signal bus_rd_req : std_ulogic; |
signal bus_wr_req : std_ulogic; |
signal access_err : std_ulogic; |
signal align_err : std_ulogic; |
signal bus_timeout : std_ulogic_vector(index_size_f(MEM_EXT_TIMEOUT)-1 downto 0); |
-- data access -- |
signal d_bus_wdata : std_ulogic_vector(data_width_c-1 downto 0); -- write data |
signal d_bus_rdata : std_ulogic_vector(data_width_c-1 downto 0); -- read data |
signal d_bus_ben : std_ulogic_vector(3 downto 0); -- write data byte enable |
|
-- misaligned access? -- |
signal misaligned_data, misaligned_instr : std_ulogic; |
signal d_misaligned, i_misaligned : std_ulogic; |
|
-- bus arbiter -- |
type bus_arbiter_t is record |
rd_req : std_ulogic; -- read access in progress |
wr_req : std_ulogic; -- write access in progress |
err_align : std_ulogic; -- alignment error |
err_bus : std_ulogic; -- bus access error |
timeout : std_ulogic_vector(index_size_f(MEM_EXT_TIMEOUT)-1 downto 0); |
end record; |
signal i_arbiter, d_arbiter : bus_arbiter_t; |
|
begin |
|
-- Address and Control -------------------------------------------------------------------- |
-- Data Interface: Access Address --------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
mem_adr_reg: process(rstn_i, clk_i) |
begin |
if rising_edge(clk_i) then |
if (ctrl_i(ctrl_bus_mar_we_c) = '1') then |
mar <= alu_i; |
mar <= addr_i; |
end if; |
end if; |
end process mem_adr_reg; |
|
-- address output -- |
bus_addr_o <= pc_i when ((bus_if_req or ctrl_i(ctrl_bus_if_c)) = '1') else mar; -- is instruction fetch? keep output at PC as long as IF request is active |
mar_o <= mar; |
-- read-back for exception controller -- |
mar_o <= mar; |
|
-- write request output -- |
bus_we_o <= ctrl_i(ctrl_bus_wr_c) and (not misaligned_data); |
-- alignment check -- |
misaligned_d_check: process(mar, ctrl_i) |
begin |
-- check data access -- |
d_misaligned <= '0'; -- default |
case ctrl_i(ctrl_bus_size_msb_c downto ctrl_bus_size_lsb_c) is -- data size |
when "00" => -- byte |
d_misaligned <= '0'; |
when "01" => -- half-word |
if (mar(0) /= '0') then |
d_misaligned <= '1'; |
end if; |
when others => -- word |
if (mar(1 downto 0) /= "00") then |
d_misaligned <= '1'; |
end if; |
end case; |
end process misaligned_d_check; |
|
-- read request output (also used for instruction fetch) -- |
bus_re_o <= (ctrl_i(ctrl_bus_rd_c) and (not misaligned_data)) or (ctrl_i(ctrl_bus_if_c) and (not misaligned_instr)); -- FIXME i_reg and misaligned |
|
|
-- Write Data ----------------------------------------------------------------------------- |
-- Data Interface: Write Data ------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
mem_do_reg: process(clk_i) |
begin |
138,28 → 169,28
begin |
case ctrl_i(ctrl_bus_size_msb_c downto ctrl_bus_size_lsb_c) is -- data size |
when "00" => -- byte |
bus_wdata_o(07 downto 00) <= mdo(07 downto 00); |
bus_wdata_o(15 downto 08) <= mdo(07 downto 00); |
bus_wdata_o(23 downto 16) <= mdo(07 downto 00); |
bus_wdata_o(31 downto 24) <= mdo(07 downto 00); |
bus_ben_o <= (others => '0'); |
bus_ben_o(to_integer(unsigned(mar(1 downto 0)))) <= '1'; |
d_bus_wdata(07 downto 00) <= mdo(07 downto 00); |
d_bus_wdata(15 downto 08) <= mdo(07 downto 00); |
d_bus_wdata(23 downto 16) <= mdo(07 downto 00); |
d_bus_wdata(31 downto 24) <= mdo(07 downto 00); |
d_bus_ben <= (others => '0'); |
d_bus_ben(to_integer(unsigned(mar(1 downto 0)))) <= '1'; |
when "01" => -- half-word |
bus_wdata_o(31 downto 16) <= mdo(15 downto 00); |
bus_wdata_o(15 downto 00) <= mdo(15 downto 00); |
d_bus_wdata(31 downto 16) <= mdo(15 downto 00); |
d_bus_wdata(15 downto 00) <= mdo(15 downto 00); |
if (mar(1) = '0') then |
bus_ben_o <= "0011"; -- low half-word |
d_bus_ben <= "0011"; -- low half-word |
else |
bus_ben_o <= "1100"; -- high half-word |
d_bus_ben <= "1100"; -- high half-word |
end if; |
when others => -- word |
bus_wdata_o <= mdo; |
bus_ben_o <= "1111"; -- full word |
d_bus_wdata <= mdo; |
d_bus_ben <= "1111"; -- full word |
end case; |
end process byte_enable; |
|
|
-- Read Data ------------------------------------------------------------------------------ |
-- Data Interface: Read Data -------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
mem_out_buf: process(clk_i) |
begin |
166,15 → 197,12
if rising_edge(clk_i) then |
-- memory data in register (MDI) -- |
if (ctrl_i(ctrl_bus_mdi_we_c) = '1') then |
mdi <= bus_rdata_i; |
mdi <= d_bus_rdata; |
end if; |
end if; |
end process mem_out_buf; |
|
-- instruction output -- |
instr_o <= bus_rdata_i; |
|
-- input data align and sign extension -- |
-- input data alignment and sign extension -- |
read_align: process(mdi, mar, ctrl_i) |
variable signed_v : std_ulogic; |
begin |
209,98 → 237,134
end process read_align; |
|
|
-- Bus Status Controller ------------------------------------------------------------------ |
-- Instruction Interface: Check for Misaligned Access ------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
bus_ctrl: process(rstn_i, clk_i) |
misaligned_i_check: process(ctrl_i, fetch_pc_i) |
begin |
-- check instruction access -- |
i_misaligned <= '0'; -- default |
if (CPU_EXTENSION_RISCV_C = true) then -- 16-bit and 32-bit instruction accesses |
i_misaligned <= '0'; -- no alignment exceptions possible |
else -- 32-bit instruction accesses only |
if (fetch_pc_i(1) = '1') then -- PC(0) is always zero |
i_misaligned <= '1'; |
end if; |
end if; |
end process misaligned_i_check; |
|
|
-- Instruction Fetch Arbiter -------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
ifetch_arbiter: process(rstn_i, clk_i) |
begin |
if (rstn_i = '0') then |
bus_busy <= '0'; |
bus_if_req <= '0'; |
bus_rd_req <= '0'; |
bus_wr_req <= '0'; |
access_err <= '0'; |
align_err <= '0'; |
bus_timeout <= (others => '0'); |
i_arbiter.rd_req <= '0'; |
i_arbiter.wr_req <= '0'; |
i_arbiter.err_align <= '0'; |
i_arbiter.err_bus <= '0'; |
i_arbiter.timeout <= (others => '0'); |
elsif rising_edge(clk_i) then |
if (bus_busy = '0') or (ctrl_i(ctrl_bus_reset_c) = '1') then -- wait for new request or reset |
bus_busy <= ctrl_i(ctrl_bus_if_c) or ctrl_i(ctrl_bus_rd_c) or ctrl_i(ctrl_bus_wr_c); -- any request at all? |
bus_if_req <= ctrl_i(ctrl_bus_if_c); -- instruction fetch |
bus_rd_req <= ctrl_i(ctrl_bus_rd_c); -- store access |
bus_wr_req <= ctrl_i(ctrl_bus_wr_c); -- load access |
bus_timeout <= std_ulogic_vector(to_unsigned(MEM_EXT_TIMEOUT, index_size_f(MEM_EXT_TIMEOUT))); |
access_err <= '0'; |
align_err <= '0'; |
else -- bus transfer in progress |
bus_timeout <= std_ulogic_vector(unsigned(bus_timeout) - 1); |
align_err <= (align_err or misaligned_data or misaligned_instr) and (not ctrl_i(ctrl_bus_exc_ack_c)); |
access_err <= (access_err or (not or_all_f(bus_timeout)) or bus_err_i) and (not ctrl_i(ctrl_bus_exc_ack_c)); |
if (align_err = '1') or (access_err = '1') then |
if (ctrl_i(ctrl_bus_exc_ack_c) = '1') then -- wait for controller to ack exception |
bus_if_req <= '0'; |
bus_rd_req <= '0'; |
bus_wr_req <= '0'; |
bus_busy <= '0'; |
i_arbiter.wr_req <= '0'; -- instruction fetch is read-only |
|
-- instruction fetch request -- |
if (i_arbiter.rd_req = '0') then -- idle |
i_arbiter.rd_req <= ctrl_i(ctrl_bus_if_c); |
i_arbiter.err_align <= i_misaligned; |
i_arbiter.err_bus <= '0'; |
i_arbiter.timeout <= std_ulogic_vector(to_unsigned(MEM_EXT_TIMEOUT, index_size_f(MEM_EXT_TIMEOUT))); |
else -- in progress |
i_arbiter.timeout <= std_ulogic_vector(unsigned(i_arbiter.timeout) - 1); |
i_arbiter.err_align <= (i_arbiter.err_align or i_misaligned) and (not ctrl_i(ctrl_bus_ierr_ack_c)); |
i_arbiter.err_bus <= (i_arbiter.err_bus or (not or_all_f(i_arbiter.timeout)) or i_bus_err_i) and (not ctrl_i(ctrl_bus_ierr_ack_c)); |
if (i_arbiter.err_align = '1') or (i_arbiter.err_bus = '1') then -- any error? |
if (ctrl_i(ctrl_bus_ierr_ack_c) = '1') then -- wait for controller to acknowledge error |
i_arbiter.rd_req <= '0'; |
end if; |
elsif (bus_ack_i = '1') then -- normal termination |
bus_if_req <= '0'; |
bus_rd_req <= '0'; |
bus_wr_req <= '0'; |
bus_busy <= '0'; |
elsif (i_bus_ack_i = '1') then -- wait for normal termination |
i_arbiter.rd_req <= '0'; |
end if; |
end if; |
|
-- cancel bus access -- |
i_bus_cancel_o <= i_arbiter.rd_req and ctrl_i(ctrl_bus_ierr_ack_c); |
end if; |
end process bus_ctrl; |
end process ifetch_arbiter; |
|
-- output bus access error to controller -- |
be_instr_o <= bus_if_req and access_err; |
be_load_o <= bus_rd_req and access_err; |
be_store_o <= bus_wr_req and access_err; |
|
-- output alignment error to controller -- |
ma_instr_o <= bus_if_req and align_err; |
ma_load_o <= bus_rd_req and align_err; |
ma_store_o <= bus_wr_req and align_err; |
-- wait for bus transaction to finish -- |
i_wait_o <= i_arbiter.rd_req and (not i_bus_ack_i); |
|
-- terminate bus access -- |
bus_cancel_o <= (bus_busy and (align_err or access_err)) or ctrl_i(ctrl_bus_reset_c); |
-- output instruction fetch error to controller -- |
ma_instr_o <= i_arbiter.err_align; |
be_instr_o <= i_arbiter.err_bus; |
|
-- wait for bus -- |
bus_busy_o <= bus_busy; |
bus_wait_o <= bus_busy and (not bus_ack_i); -- FIXME: 'async' ack |
-- instruction bus (read-only) -- |
i_bus_addr_o <= fetch_pc_i; |
i_bus_wdata_o <= (others => '0'); |
i_bus_ben_o <= (others => '0'); |
i_bus_we_o <= '0'; |
i_bus_re_o <= ctrl_i(ctrl_bus_if_c) and (not i_misaligned); -- no actual read when misaligned |
i_bus_fence_o <= ctrl_i(ctrl_bus_fencei_c); |
instr_o <= i_bus_rdata_i; |
|
|
-- Check for Misaligned Access ------------------------------------------------------------ |
-- Data Access Arbiter -------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
misaligned_d_check: process(mar, ctrl_i) |
data_access_arbiter: process(rstn_i, clk_i) |
begin |
-- check data access -- |
misaligned_data <= '0'; -- default |
case ctrl_i(ctrl_bus_size_msb_c downto ctrl_bus_size_lsb_c) is -- data size |
when "00" => -- byte |
misaligned_data <= '0'; |
when "01" => -- half-word |
if (mar(0) /= '0') then |
misaligned_data <= '1'; |
if (rstn_i = '0') then |
d_arbiter.rd_req <= '0'; |
d_arbiter.wr_req <= '0'; |
d_arbiter.err_align <= '0'; |
d_arbiter.err_bus <= '0'; |
d_arbiter.timeout <= (others => '0'); |
elsif rising_edge(clk_i) then |
|
-- data access request -- |
if (d_arbiter.wr_req = '0') and (d_arbiter.rd_req = '0') then -- idle |
d_arbiter.wr_req <= ctrl_i(ctrl_bus_wr_c); |
d_arbiter.rd_req <= ctrl_i(ctrl_bus_rd_c); |
d_arbiter.err_align <= d_misaligned; |
d_arbiter.err_bus <= '0'; |
d_arbiter.timeout <= std_ulogic_vector(to_unsigned(MEM_EXT_TIMEOUT, index_size_f(MEM_EXT_TIMEOUT))); |
else -- in progress |
d_arbiter.timeout <= std_ulogic_vector(unsigned(d_arbiter.timeout) - 1); |
d_arbiter.err_align <= (d_arbiter.err_align or d_misaligned) and (not ctrl_i(ctrl_bus_derr_ack_c)); |
d_arbiter.err_bus <= (d_arbiter.err_bus or (not or_all_f(d_arbiter.timeout)) or d_bus_err_i) and (not ctrl_i(ctrl_bus_derr_ack_c)); |
if (d_arbiter.err_align = '1') or (d_arbiter.err_bus = '1') then -- any error? |
if (ctrl_i(ctrl_bus_derr_ack_c) = '1') then -- wait for controller to acknowledge error |
d_arbiter.wr_req <= '0'; |
d_arbiter.rd_req <= '0'; |
end if; |
elsif (d_bus_ack_i = '1') then -- wait for normal termination |
d_arbiter.wr_req <= '0'; |
d_arbiter.rd_req <= '0'; |
end if; |
when others => -- word |
if (mar(1 downto 0) /= "00") then |
misaligned_data <= '1'; |
end if; |
end case; |
end process misaligned_d_check; |
end if; |
|
misaligned_i_check: process(ctrl_i, pc_i) |
begin |
-- check instruction access -- |
misaligned_instr <= '0'; -- default |
if (CPU_EXTENSION_RISCV_C = true) then -- 16-bit and 32-bit instruction accesses |
misaligned_instr <= '0'; -- no alignment exceptions possible |
else -- 32-bit instruction accesses only |
if (pc_i(1) = '1') then -- PC(0) is always zero |
misaligned_instr <= '1'; |
end if; |
-- cancel bus access -- |
d_bus_cancel_o <= (d_arbiter.wr_req or d_arbiter.rd_req) and ctrl_i(ctrl_bus_derr_ack_c); |
end if; |
end process misaligned_i_check; |
end process data_access_arbiter; |
|
|
-- wait for bus transaction to finish -- |
d_wait_o <= (d_arbiter.wr_req or d_arbiter.rd_req) and (not d_bus_ack_i); |
|
-- output data access error to controller -- |
ma_load_o <= d_arbiter.rd_req and d_arbiter.err_align; |
be_load_o <= d_arbiter.rd_req and d_arbiter.err_bus; |
ma_store_o <= d_arbiter.wr_req and d_arbiter.err_align; |
be_store_o <= d_arbiter.wr_req and d_arbiter.err_bus; |
|
-- data bus -- |
d_bus_addr_o <= mar; |
d_bus_wdata_o <= d_bus_wdata; |
d_bus_ben_o <= d_bus_ben; |
d_bus_we_o <= ctrl_i(ctrl_bus_wr_c) and (not d_misaligned); -- no actual write when misaligned |
d_bus_re_o <= ctrl_i(ctrl_bus_rd_c) and (not d_misaligned); -- no actual read when misaligned |
d_bus_fence_o <= ctrl_i(ctrl_bus_fence_c); |
d_bus_rdata <= d_bus_rdata_i; |
|
|
end neorv32_cpu_bus_rtl; |
/neorv32/trunk/rtl/core/neorv32_cpu_control.vhd
46,40 → 46,15
entity neorv32_cpu_control is |
generic ( |
-- General -- |
CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz |
HART_ID : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom hardware thread ID |
BOOTLOADER_USE : boolean := true; -- implement processor-internal bootloader? |
CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])? |
CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])? |
HW_THREAD_ID : std_ulogic_vector(31 downto 0):= x"00000000"; -- hardware thread id |
CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0):= x"00000000"; -- cpu boot address |
-- RISC-V CPU Extensions -- |
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension? |
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension? |
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension? |
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system? |
CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.? |
-- Memory configuration: Instruction memory -- |
MEM_ISPACE_BASE : std_ulogic_vector(31 downto 0) := x"00000000"; -- base address of instruction memory space |
MEM_ISPACE_SIZE : natural := 8*1024; -- total size of instruction memory space in byte |
MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory |
MEM_INT_IMEM_SIZE : natural := 8*1024; -- size of processor-internal instruction memory in bytes |
MEM_INT_IMEM_ROM : boolean := false; -- implement processor-internal instruction memory as ROM |
-- Memory configuration: Data memory -- |
MEM_DSPACE_BASE : std_ulogic_vector(31 downto 0) := x"80000000"; -- base address of data memory space |
MEM_DSPACE_SIZE : natural := 4*1024; -- total size of data memory space in byte |
MEM_INT_DMEM_USE : boolean := true; -- implement processor-internal data memory |
MEM_INT_DMEM_SIZE : natural := 4*1024; -- size of processor-internal data memory in bytes |
-- Memory configuration: External memory interface -- |
MEM_EXT_USE : boolean := false; -- implement external memory bus interface? |
-- Processor peripherals -- |
IO_GPIO_USE : boolean := true; -- implement general purpose input/output port unit (GPIO)? |
IO_MTIME_USE : boolean := true; -- implement machine system timer (MTIME)? |
IO_UART_USE : boolean := true; -- implement universal asynchronous receiver/transmitter (UART)? |
IO_SPI_USE : boolean := true; -- implement serial peripheral interface (SPI)? |
IO_TWI_USE : boolean := true; -- implement two-wire interface (TWI)? |
IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)? |
IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)? |
IO_CLIC_USE : boolean := true; -- implement core local interrupt controller (CLIC)? |
IO_TRNG_USE : boolean := true; -- implement true random number generator (TRNG)? |
IO_DEVNULL_USE : boolean := true -- implement dummy device (DEVNULL)? |
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension? |
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension? |
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension? |
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system? |
CPU_EXTENSION_RISCV_Zifencei : boolean := true -- implement instruction stream sync.? |
); |
port ( |
-- global control -- |
88,7 → 63,8
ctrl_o : out std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus |
-- status input -- |
alu_wait_i : in std_ulogic; -- wait for ALU |
bus_wait_i : in std_ulogic; -- wait for bus |
bus_i_wait_i : in std_ulogic; -- wait for bus |
bus_d_wait_i : in std_ulogic; -- wait for bus |
-- data input -- |
instr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- instruction |
cmp_i : in std_ulogic_vector(1 downto 0); -- comparator status |
102,6 → 78,7
csr_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- CSR write data |
csr_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data |
-- external interrupt -- |
msw_irq_i : in std_ulogic; -- software interrupt |
clic_irq_i : in std_ulogic; -- CLIC interrupt request |
mtime_irq_i : in std_ulogic; -- machine timer interrupt |
-- system time input from MTIME -- |
113,8 → 90,7
ma_store_i : in std_ulogic; -- misaligned store data address |
be_instr_i : in std_ulogic; -- bus error on instruction access |
be_load_i : in std_ulogic; -- bus error on load data access |
be_store_i : in std_ulogic; -- bus error on store data access |
bus_busy_i : in std_ulogic -- bus unit is busy |
be_store_i : in std_ulogic -- bus error on store data access |
); |
end neorv32_cpu_control; |
|
141,7 → 117,6
ci_return_nxt : std_ulogic; |
reset : std_ulogic; |
bus_err_ack : std_ulogic; |
bus_reset : std_ulogic; |
end record; |
signal fetch_engine : fetch_engine_t; |
|
165,11 → 140,10
signal ipb : ipb_t; |
|
-- instruction execution engine -- |
type execute_engine_state_t is (SYS_WAIT, DISPATCH, TRAP, EXECUTE, ALU_WAIT, BRANCH, STORE, LOAD, LOADSTORE_0, LOADSTORE_1, CSR_ACCESS); |
type execute_engine_state_t is (SYS_WAIT, DISPATCH, TRAP, EXECUTE, ALU_WAIT, BRANCH, LOADSTORE_0, LOADSTORE_1, LOADSTORE_2, CSR_ACCESS); |
type execute_engine_t is record |
state : execute_engine_state_t; |
state_nxt : execute_engine_state_t; |
state_prev : execute_engine_state_t; |
i_reg : std_ulogic_vector(31 downto 0); |
i_reg_nxt : std_ulogic_vector(31 downto 0); |
is_ci : std_ulogic; -- current instruction is de-compressed instruction |
186,6 → 160,8
end record; |
signal execute_engine : execute_engine_t; |
|
signal next_pc_tmp : std_ulogic_vector(data_width_c-1 downto 0); |
|
-- trap controller -- |
type trap_ctrl_t is record |
exc_buf : std_ulogic_vector(exception_width_c-1 downto 0); |
195,9 → 171,8
exc_ack : std_ulogic; -- acknowledge all exceptions |
irq_ack : std_ulogic_vector(interrupt_width_c-1 downto 0); -- acknowledge specific interrupt |
irq_ack_nxt : std_ulogic_vector(interrupt_width_c-1 downto 0); |
cause : std_ulogic_vector(data_width_c-1 downto 0); -- trap ID (for "mcause") |
cause_nxt : std_ulogic_vector(data_width_c-1 downto 0); |
exc_src : std_ulogic_vector(exception_width_c-1 downto 0); |
cause : std_ulogic_vector(4 downto 0); -- trap ID (for "mcause"), only for hw |
cause_nxt : std_ulogic_vector(4 downto 0); |
-- |
env_start : std_ulogic; -- start trap handler env |
env_start_ack : std_ulogic; -- start of trap handler acknowledged |
225,24 → 200,24
re_nxt : std_ulogic; |
mstatus_mie : std_ulogic; -- mstatus.MIE: global IRQ enable (R/W) |
mstatus_mpie : std_ulogic; -- mstatus.MPIE: previous global IRQ enable (R/-) |
mip_msip : std_ulogic; -- mip.MSIP: machine software interrupt pending (R/W) |
mie_msie : std_ulogic; -- mie.MSIE: machine software interrupt enable (R/W) |
mie_meie : std_ulogic; -- mie.MEIE: machine external interrupt enable (R/W) |
mie_mtie : std_ulogic; -- mie.MEIE: machine timer interrupt enable (R/W) |
mepc : std_ulogic_vector(data_width_c-1 downto 0); -- mepc: machine exception pc (R/W) |
mcause : std_ulogic_vector(data_width_c-1 downto 0); -- mcause: machine trap cause (R/W) |
mtvec : std_ulogic_vector(data_width_c-1 downto 0); -- mtvec: machine trap-handler base address (R/W) |
mtvec : std_ulogic_vector(data_width_c-1 downto 0); -- mtvec: machine trap-handler base address (R/W), bit 1:0 == 00 |
mtval : std_ulogic_vector(data_width_c-1 downto 0); -- mtval: machine bad address or isntruction (R/W) |
mscratch : std_ulogic_vector(data_width_c-1 downto 0); -- mscratch: scratch register (R/W) |
mcycle : std_ulogic_vector(32 downto 0); -- mcycle (R/W), plus carry bit |
minstret : std_ulogic_vector(32 downto 0); -- minstret (R/W), plus carry bit |
mcycleh : std_ulogic_vector(31 downto 0); -- mcycleh (R/W) |
minstreth : std_ulogic_vector(31 downto 0); -- minstreth (R/W) |
mcycleh : std_ulogic_vector(19 downto 0); -- mcycleh (R/W) - REDUCED BIT-WIDTH! |
minstreth : std_ulogic_vector(19 downto 0); -- minstreth (R/W) - REDUCED BIT-WIDTH! |
end record; |
signal csr : csr_t; |
|
signal mcycle_msb : std_ulogic; |
signal minstret_msb : std_ulogic; |
signal systime : std_ulogic_vector(63 downto 0); |
|
-- illegal instruction check -- |
signal illegal_instruction : std_ulogic; |
314,10 → 289,13
end if; |
end process fetch_engine_fsm_sync; |
|
-- PC output -- |
fetch_pc_o <= fetch_engine.pc_fetch(data_width_c-1 downto 1) & '0'; |
|
|
-- Fetch Engine FSM Comb ------------------------------------------------------------------ |
-- ------------------------------------------------------------------------------------------- |
fetch_engine_fsm_comb: process(fetch_engine, execute_engine, csr, ipb, instr_i, bus_wait_i, bus_busy_i, ci_instr32, be_instr_i, ma_instr_i) |
fetch_engine_fsm_comb: process(fetch_engine, csr, ipb, instr_i, bus_i_wait_i, ci_instr32, be_instr_i, ma_instr_i) |
begin |
-- arbiter defaults -- |
fetch_engine.state_nxt <= fetch_engine.state; |
330,7 → 308,6
fetch_engine.ci_reg_nxt <= fetch_engine.ci_reg; |
fetch_engine.ci_return_nxt <= fetch_engine.ci_return; |
fetch_engine.bus_err_ack <= '0'; |
fetch_engine.bus_reset <= '0'; |
|
-- instruction prefetch buffer interface -- |
ipb.we <= '0'; |
345,82 → 322,71
-- ------------------------------------------------------------ |
fetch_engine.i_buf_state_nxt <= (others => '0'); |
fetch_engine.ci_return_nxt <= '0'; |
fetch_engine.bus_reset <= '1'; -- reset bus unit |
ipb.clear <= '1'; -- clear instruction prefetch buffer |
fetch_engine.state_nxt <= IFETCH_0; |
|
when IFETCH_0 => -- output current PC to bus system, request 32-bit word |
-- ------------------------------------------------------------ |
if (bus_busy_i = '0') and (execute_engine.state /= LOAD) and (execute_engine.state /= STORE) and |
(execute_engine.state /= LOADSTORE_0) and (execute_engine.state /= LOADSTORE_1) then -- wait if execute engine is using bus unit |
bus_fast_ir <= '1'; -- fast instruction fetch request (output PC to bus.address) |
fetch_engine.state_nxt <= IFETCH_1; |
end if; |
bus_fast_ir <= '1'; -- fast instruction fetch request |
fetch_engine.state_nxt <= IFETCH_1; |
|
when IFETCH_1 => -- store data from memory to buffer(s) |
-- ------------------------------------------------------------ |
fetch_engine.i_buf_nxt <= be_instr_i & ma_instr_i & instr_i(31 downto 0); -- store data word and exception info |
if (bus_wait_i = '0') then -- wait for bus response |
fetch_engine.i_buf2_nxt <= fetch_engine.i_buf; |
fetch_engine.i_buf_state_nxt(1) <= fetch_engine.i_buf_state(0); |
fetch_engine.state_nxt <= IFETCH_2; |
if (bus_i_wait_i = '0') or (be_instr_i = '1') or (ma_instr_i = '1') then -- wait for bus response |
fetch_engine.i_buf_nxt <= be_instr_i & ma_instr_i & instr_i(31 downto 0); -- store data word and exception info |
fetch_engine.i_buf2_nxt <= fetch_engine.i_buf; |
fetch_engine.i_buf_state_nxt <= fetch_engine.i_buf_state(0) & '1'; |
fetch_engine.bus_err_ack <= '1'; -- acknowledge any instruction bus errors, the execute engine has to take care of them |
if (fetch_engine.i_buf_state(0) = '1') then -- buffer filled? |
fetch_engine.state_nxt <= IFETCH_2; |
else |
fetch_engine.pc_fetch_add <= std_ulogic_vector(to_unsigned(4, data_width_c)); |
fetch_engine.state_nxt <= IFETCH_0; -- get another instruction word |
end if; |
end if; |
|
fetch_engine.i_buf_state_nxt(0) <= '1'; |
if (be_instr_i = '1') or (ma_instr_i = '1') then -- any fetch exception? |
fetch_engine.bus_err_ack <= '1'; -- ack bus errors, the execute engine has to take care of them |
end if; |
|
when IFETCH_2 => -- construct instruction and issue |
when IFETCH_2 => -- construct instruction word and issue |
-- ------------------------------------------------------------ |
if (fetch_engine.i_buf_state(1) = '1') then |
if (fetch_engine.pc_fetch(1) = '0') or (CPU_EXTENSION_RISCV_C = false) then -- 32-bit aligned |
fetch_engine.ci_reg_nxt <= fetch_engine.i_buf2(33 downto 32) & fetch_engine.i_buf2(15 downto 00); |
ipb.wdata <= fetch_engine.i_buf2(33 downto 32) & '0' & fetch_engine.i_buf2(31 downto 0); |
|
if (fetch_engine.i_buf2(01 downto 00) = "11") or (CPU_EXTENSION_RISCV_C = false) then -- uncompressed |
if (ipb.free = '1') then -- free entry in buffer? |
ipb.we <= '1'; |
fetch_engine.pc_real_add <= std_ulogic_vector(to_unsigned(4, data_width_c)); |
fetch_engine.pc_fetch_add <= std_ulogic_vector(to_unsigned(4, data_width_c)); |
fetch_engine.state_nxt <= IFETCH_0; |
end if; |
|
else -- compressed |
fetch_engine.pc_fetch_add <= std_ulogic_vector(to_unsigned(2, data_width_c)); |
fetch_engine.ci_return_nxt <= '1'; -- come back here after issueing |
fetch_engine.state_nxt <= IFETCH_3; |
end if; |
|
else -- 16-bit aligned |
fetch_engine.ci_reg_nxt <= fetch_engine.i_buf2(33 downto 32) & fetch_engine.i_buf2(31 downto 16); |
ipb.wdata <= fetch_engine.i_buf(33 downto 32) & '0' & fetch_engine.i_buf(15 downto 00) & fetch_engine.i_buf2(31 downto 16); |
|
if (fetch_engine.i_buf2(17 downto 16) = "11") then -- uncompressed |
if (ipb.free = '1') then -- free entry in buffer? |
ipb.we <= '1'; |
fetch_engine.pc_real_add <= std_ulogic_vector(to_unsigned(4, data_width_c)); |
fetch_engine.pc_fetch_add <= std_ulogic_vector(to_unsigned(4, data_width_c)); |
fetch_engine.state_nxt <= IFETCH_0; |
end if; |
|
else -- compressed |
fetch_engine.pc_fetch_add <= std_ulogic_vector(to_unsigned(2, data_width_c)); |
fetch_engine.ci_return_nxt <= '0'; -- start next fetch after issueing |
fetch_engine.state_nxt <= IFETCH_3; |
end if; |
end if; |
else |
fetch_engine.pc_fetch_add <= std_ulogic_vector(to_unsigned(4, data_width_c)); |
fetch_engine.state_nxt <= IFETCH_0; |
end if; |
if (fetch_engine.pc_fetch(1) = '0') or (CPU_EXTENSION_RISCV_C = false) then -- 32-bit aligned |
fetch_engine.ci_reg_nxt <= fetch_engine.i_buf2(33 downto 32) & fetch_engine.i_buf2(15 downto 00); |
ipb.wdata <= fetch_engine.i_buf2(33 downto 32) & '0' & fetch_engine.i_buf2(31 downto 0); |
|
if (fetch_engine.i_buf2(01 downto 00) = "11") or (CPU_EXTENSION_RISCV_C = false) then -- uncompressed |
if (ipb.free = '1') then -- free entry in buffer? |
ipb.we <= '1'; |
fetch_engine.pc_real_add <= std_ulogic_vector(to_unsigned(4, data_width_c)); |
fetch_engine.pc_fetch_add <= std_ulogic_vector(to_unsigned(4, data_width_c)); |
fetch_engine.state_nxt <= IFETCH_0; |
end if; |
else -- compressed |
fetch_engine.ci_return_nxt <= '1'; -- come back here after issueing |
fetch_engine.state_nxt <= IFETCH_3; |
end if; |
|
else -- 16-bit aligned |
fetch_engine.ci_reg_nxt <= fetch_engine.i_buf2(33 downto 32) & fetch_engine.i_buf2(31 downto 16); |
ipb.wdata <= fetch_engine.i_buf(33 downto 32) & '0' & fetch_engine.i_buf(15 downto 00) & fetch_engine.i_buf2(31 downto 16); |
|
if (fetch_engine.i_buf2(17 downto 16) = "11") then -- uncompressed |
if (ipb.free = '1') then -- free entry in buffer? |
ipb.we <= '1'; |
fetch_engine.pc_real_add <= std_ulogic_vector(to_unsigned(4, data_width_c)); |
fetch_engine.pc_fetch_add <= std_ulogic_vector(to_unsigned(4, data_width_c)); |
fetch_engine.state_nxt <= IFETCH_0; |
end if; |
else -- compressed |
fetch_engine.ci_return_nxt <= '0'; -- start next fetch after issueing |
fetch_engine.state_nxt <= IFETCH_3; |
end if; |
end if; |
|
when IFETCH_3 => -- additional cycle for issueing decompressed instructions |
-- ------------------------------------------------------------ |
if (ipb.free = '1') then -- free entry in buffer? |
ipb.we <= '1'; |
ipb.wdata <= fetch_engine.ci_reg(17 downto 16) & '1' & ci_instr32; |
fetch_engine.pc_real_add <= std_ulogic_vector(to_unsigned(2, data_width_c)); |
ipb.we <= '1'; |
ipb.wdata <= fetch_engine.ci_reg(17 downto 16) & '1' & ci_instr32; |
fetch_engine.pc_fetch_add <= std_ulogic_vector(to_unsigned(2, data_width_c)); |
fetch_engine.pc_real_add <= std_ulogic_vector(to_unsigned(2, data_width_c)); |
if (fetch_engine.ci_return = '0') then |
fetch_engine.state_nxt <= IFETCH_0; |
else |
536,19 → 502,13
|
-- Execute Engine FSM Sync ---------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
-- for registers that require a specific reset state -- |
-- for registers that DO require a specific reset state -- |
execute_engine_fsm_sync_rst: process(rstn_i, clk_i) |
begin |
if (rstn_i = '0') then |
if (BOOTLOADER_USE = true) then -- boot from bootloader ROM |
execute_engine.pc <= boot_base_c(data_width_c-1 downto 1) & '0'; |
execute_engine.last_pc <= boot_base_c(data_width_c-1 downto 1) & '0'; |
else -- boot from IMEM |
execute_engine.pc <= MEM_ISPACE_BASE(data_width_c-1 downto 1) & '0'; |
execute_engine.last_pc <= MEM_ISPACE_BASE(data_width_c-1 downto 1) & '0'; |
end if; |
execute_engine.state <= SYS_WAIT; |
execute_engine.state_prev <= SYS_WAIT; |
execute_engine.pc <= CPU_BOOT_ADDR(data_width_c-1 downto 1) & '0'; |
execute_engine.last_pc <= CPU_BOOT_ADDR(data_width_c-1 downto 1) & '0'; |
execute_engine.state <= SYS_WAIT; |
-- |
execute_engine.sleep <= '0'; |
elsif rising_edge(clk_i) then |
556,8 → 516,7
if (execute_engine.state = EXECUTE) then |
execute_engine.last_pc <= execute_engine.pc(data_width_c-1 downto 1) & '0'; |
end if; |
execute_engine.state <= execute_engine.state_nxt; |
execute_engine.state_prev <= execute_engine.state; |
execute_engine.state <= execute_engine.state_nxt; |
-- |
execute_engine.sleep <= execute_engine.sleep_nxt; |
end if; |
564,7 → 523,7
end process execute_engine_fsm_sync_rst; |
|
|
-- for registers that DO NOT require a specific reset state -- |
-- for registers that do NOT require a specific reset state -- |
execute_engine_fsm_sync: process(clk_i) |
begin |
if rising_edge(clk_i) then |
576,13 → 535,11
end if; |
end process execute_engine_fsm_sync; |
|
|
-- PC output -- |
execute_engine.next_pc <= std_ulogic_vector(unsigned(execute_engine.pc(data_width_c-1 downto 1) & '0') + 2) when (execute_engine.is_ci = '1') else |
std_ulogic_vector(unsigned(execute_engine.pc(data_width_c-1 downto 1) & '0') + 4); |
fetch_pc_o <= fetch_engine.pc_fetch(data_width_c-1 downto 1) & '0'; |
curr_pc_o <= execute_engine.pc(data_width_c-1 downto 1) & '0'; |
next_pc_o <= execute_engine.next_pc(data_width_c-1 downto 1) & '0'; |
next_pc_tmp <= std_ulogic_vector(unsigned(execute_engine.pc) + 2) when (execute_engine.is_ci = '1') else std_ulogic_vector(unsigned(execute_engine.pc) + 4); |
execute_engine.next_pc <= next_pc_tmp(data_width_c-1 downto 1) & '0'; |
next_pc_o <= next_pc_tmp(data_width_c-1 downto 1) & '0'; |
curr_pc_o <= execute_engine.pc(data_width_c-1 downto 1) & '0'; |
|
|
-- CPU Control Bus Output ----------------------------------------------------------------- |
594,11 → 551,11
ctrl_o(ctrl_rf_rd_adr4_c downto ctrl_rf_rd_adr0_c) <= execute_engine.i_reg(instr_rd_msb_c downto instr_rd_lsb_c); |
ctrl_o(ctrl_rf_rs1_adr4_c downto ctrl_rf_rs1_adr0_c) <= execute_engine.i_reg(instr_rs1_msb_c downto instr_rs1_lsb_c); |
ctrl_o(ctrl_rf_rs2_adr4_c downto ctrl_rf_rs2_adr0_c) <= execute_engine.i_reg(instr_rs2_msb_c downto instr_rs2_lsb_c); |
-- bus access requests -- |
-- fast bus access requests -- |
ctrl_o(ctrl_bus_if_c) <= ctrl(ctrl_bus_if_c) or bus_fast_ir; |
-- bus control -- |
ctrl_o(ctrl_bus_exc_ack_c) <= trap_ctrl.env_start_ack or fetch_engine.bus_err_ack; |
ctrl_o(ctrl_bus_reset_c) <= fetch_engine.bus_reset; |
-- bus error control -- |
ctrl_o(ctrl_bus_ierr_ack_c) <= fetch_engine.bus_err_ack; |
ctrl_o(ctrl_bus_derr_ack_c) <= trap_ctrl.env_start_ack; |
end process ctrl_output; |
|
|
605,10 → 562,9
-- Execute Engine FSM Comb ---------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
execute_engine_fsm_comb: process(execute_engine, fetch_engine, ipb, trap_ctrl, csr, ctrl, |
alu_add_i, alu_wait_i, bus_wait_i, ma_load_i, be_load_i, ma_store_i, be_store_i) |
alu_add_i, alu_wait_i, bus_d_wait_i, ma_load_i, be_load_i, ma_store_i, be_store_i) |
variable alu_immediate_v : std_ulogic; |
variable alu_operation_v : std_ulogic_vector(2 downto 0); |
variable rd_is_r0_v : std_ulogic; |
variable rs1_is_r0_v : std_ulogic; |
begin |
-- arbiter defaults -- |
639,19 → 595,18
|
-- control defaults -- |
ctrl_nxt <= (others => '0'); -- all off at first |
ctrl_nxt(ctrl_bus_unsigned_c) <= execute_engine.i_reg(instr_funct3_msb_c); -- unsigned LOAD (LBU, LHU) |
if (execute_engine.i_reg(instr_opcode_lsb_c+4) = '1') then -- ALU ops |
ctrl_nxt(ctrl_alu_unsigned_c) <= execute_engine.i_reg(instr_funct3_lsb_c+0); -- unsigned ALU operation (SLTIU, SLTU) |
else -- branches |
ctrl_nxt(ctrl_alu_unsigned_c) <= execute_engine.i_reg(instr_funct3_lsb_c+1); -- unsigned branches (BLTU, BGEU) |
end if; |
ctrl_nxt(ctrl_bus_unsigned_c) <= execute_engine.i_reg(instr_funct3_msb_c); -- unsigned LOAD (LBU, LHU) |
ctrl_nxt(ctrl_alu_shift_dir_c) <= execute_engine.i_reg(instr_funct3_msb_c); -- shift direction |
ctrl_nxt(ctrl_alu_shift_ar_c) <= execute_engine.i_reg(30); -- arithmetic shift |
ctrl_nxt(ctrl_bus_size_lsb_c) <= execute_engine.i_reg(instr_funct3_lsb_c+0); -- transfer size lsb (00=byte, 01=half-word) |
ctrl_nxt(ctrl_bus_size_msb_c) <= execute_engine.i_reg(instr_funct3_lsb_c+1); -- transfer size msb (10=word, 11=?) |
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_add_c; -- actual ALU operation = add |
ctrl_nxt(ctrl_cp_cmd2_c downto ctrl_cp_cmd0_c) <= execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c); -- CP operation |
ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_muldiv_c; -- only CP0 implemented yet |
ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_muldiv_c; -- only CP0 (MULDIV) implemented yet |
|
-- is immediate operation? -- |
alu_immediate_v := '0'; |
677,12 → 632,6
when others => alu_operation_v := (others => '0'); -- undefined |
end case; |
|
-- is rd = r0? -- |
rd_is_r0_v := '0'; |
if (execute_engine.i_reg(instr_rd_msb_c downto instr_rd_lsb_c) = "00000") then |
rd_is_r0_v := '1'; |
end if; |
|
-- is rs1 = r0? -- |
rs1_is_r0_v := '0'; |
if (execute_engine.i_reg(instr_rs1_msb_c downto instr_rs1_lsb_c) = "00000") then |
722,7 → 671,7
if (trap_ctrl.env_start = '1') then |
trap_ctrl.env_start_ack <= '1'; |
execute_engine.sleep_nxt <= '0'; -- waky waky |
execute_engine.pc_nxt <= csr.mtvec(data_width_c-1 downto 1) & '0'; |
execute_engine.pc_nxt <= csr.mtvec(data_width_c-1 downto 2) & "00"; -- has to be here for wfi to work |
execute_engine.state_nxt <= SYS_WAIT; |
end if; |
|
740,7 → 689,7
-- multi cycle alu operation? -- |
if (alu_operation_v = alu_cmd_shift_c) or -- shift operation |
((CPU_EXTENSION_RISCV_M = true) and (execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c) = opcode_alu_c) and |
(execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0000001")) then -- MULDIV? |
(execute_engine.i_reg(instr_funct7_lsb_c) = '1')) then -- MULDIV? |
execute_engine.state_nxt <= ALU_WAIT; |
else |
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back |
748,15 → 697,14
end if; |
-- cp access? -- |
if (CPU_EXTENSION_RISCV_M = true) and (execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c) = opcode_alu_c) and |
(execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0000001") then -- MULDIV? |
(execute_engine.i_reg(instr_funct7_lsb_c) = '1') then -- MULDIV? |
ctrl_nxt(ctrl_cp_use_c) <= '1'; -- use CP |
ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_muldiv_c; -- muldiv CP |
end if; |
|
|
when opcode_lui_c | opcode_auipc_c => -- load upper immediate (add to PC) |
-- ------------------------------------------------------------ |
ctrl_nxt(ctrl_rf_clear_rs1_c) <= '1'; -- force RS1 = r0 |
ctrl_nxt(ctrl_rf_clear_rs1_c) <= '1'; -- force RS1 = r0 (only relevant for LUI) |
if (execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c) = opcode_auipc_c) then -- AUIPC |
ctrl_nxt(ctrl_alu_opa_mux_lsb_c) <= '1'; -- use PC as ALU.OPA |
else -- LUI |
775,13 → 723,7
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_add_c; -- actual ALU operation |
ctrl_nxt(ctrl_bus_mar_we_c) <= '1'; -- write to MAR |
ctrl_nxt(ctrl_bus_mdo_we_c) <= '1'; -- write to MDO (only relevant for stores) |
if (fetch_engine.state /= IFETCH_0) then |
if (execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c) = opcode_load_c) then -- LOAD |
execute_engine.state_nxt <= LOAD; |
else -- STORE |
execute_engine.state_nxt <= STORE; |
end if; |
end if; |
execute_engine.state_nxt <= LOADSTORE_0; |
|
when opcode_branch_c => -- branch instruction |
-- ------------------------------------------------------------ |
808,22 → 750,19
|
when opcode_fence_c => -- fence operations |
-- ------------------------------------------------------------ |
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_fencei_c) and (CPU_EXTENSION_RISCV_Zifencei = true) then -- FENCE.I |
fetch_engine.reset <= '1'; |
execute_engine.pc_nxt <= execute_engine.next_pc; |
execute_engine.state_nxt <= SYS_WAIT; |
else |
execute_engine.state_nxt <= DISPATCH; |
execute_engine.pc_nxt <= execute_engine.next_pc; -- "refetch" next instruction (only relevant for fencei) |
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_fencei_c) and (CPU_EXTENSION_RISCV_Zifencei = true) then -- FENCEI |
fetch_engine.reset <= '1'; |
ctrl_nxt(ctrl_bus_fencei_c) <= '1'; |
end if; |
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_fence_c) then -- FENCE |
ctrl_nxt(ctrl_bus_fence_c) <= '1'; |
end if; |
execute_engine.state_nxt <= SYS_WAIT; |
|
when opcode_syscsr_c => -- system/csr access |
-- ------------------------------------------------------------ |
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrw_c) or |
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrwi_c) then |
csr.re_nxt <= not rd_is_r0_v; -- only read CSR if not writing to zero_reg |
else |
csr.re_nxt <= '1'; -- always read CSR |
end if; |
csr.re_nxt <= '1'; -- always read CSR |
-- |
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_env_c) then -- system |
case execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) is |
841,10 → 780,12
NULL; |
end case; |
execute_engine.state_nxt <= SYS_WAIT; |
elsif (CPU_EXTENSION_RISCV_Zicsr = true) then -- CSR access |
execute_engine.state_nxt <= CSR_ACCESS; |
else |
execute_engine.state_nxt <= DISPATCH; |
if (CPU_EXTENSION_RISCV_Zicsr = true) then -- CSR access |
execute_engine.state_nxt <= CSR_ACCESS; |
else -- undefined |
execute_engine.state_nxt <= DISPATCH; |
end if; |
end if; |
|
when others => -- undefined |
859,6 → 800,7
ctrl_nxt(ctrl_alu_opa_mux_lsb_c) <= '0'; -- default |
ctrl_nxt(ctrl_alu_opb_mux_msb_c) <= '0'; -- default |
ctrl_nxt(ctrl_alu_opb_mux_lsb_c) <= '0'; -- default |
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_or_c; -- default ALU operation = OR |
case execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) is |
-- register operations -- |
when funct3_csrrw_c => -- CSRRW |
865,11 → 807,11
ctrl_nxt(ctrl_alu_opa_mux_lsb_c) <= '0'; -- OPA = rs1 |
ctrl_nxt(ctrl_alu_opb_mux_lsb_c) <= '0'; -- OPB = rs2 |
ctrl_nxt(ctrl_rf_clear_rs2_c) <= '1'; -- rs2 = 0 |
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_add_c; -- actual ALU operation = ADD |
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_or_c; -- actual ALU operation = OR |
csr.we_nxt <= '1'; -- always write CSR |
when funct3_csrrs_c => -- CSRRS |
ctrl_nxt(ctrl_alu_opa_mux_msb_c) <= '1'; -- OPA = csr |
ctrl_nxt(ctrl_alu_opb_mux_msb_c) <= '1'; -- OPB = crs1 |
ctrl_nxt(ctrl_alu_opb_mux_msb_c) <= '1'; -- OPB = rs1 |
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_or_c; -- actual ALU operation = OR |
csr.we_nxt <= not rs1_is_r0_v; -- write CSR if rs1 is not zero_reg |
when funct3_csrrc_c => -- CSRRC |
882,7 → 824,7
ctrl_nxt(ctrl_alu_opa_mux_lsb_c) <= '0'; -- OPA = rs1 |
ctrl_nxt(ctrl_rf_clear_rs1_c) <= '1'; -- rs1 = 0 |
ctrl_nxt(ctrl_alu_opb_mux_lsb_c) <= '1'; -- OPB = immediate |
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_add_c; -- actual ALU operation = ADD |
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_or_c; -- actual ALU operation = OR |
csr.we_nxt <= '1'; -- always write CSR |
when funct3_csrrsi_c => -- CSRRSI |
ctrl_nxt(ctrl_alu_opa_mux_msb_c) <= '1'; -- OPA = csr |
898,7 → 840,7
NULL; |
end case; |
-- RF write back -- |
ctrl_nxt(ctrl_rf_in_mux_msb_c downto ctrl_rf_in_mux_lsb_c) <= "11"; -- RF input = CSR output register |
ctrl_nxt(ctrl_rf_in_mux_msb_c downto ctrl_rf_in_mux_lsb_c) <= "11"; -- RF input = CSR output |
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back |
execute_engine.state_nxt <= DISPATCH; -- FIXME should be SYS_WAIT? have another cycle to let side-effects kick in |
|
906,9 → 848,9
-- ------------------------------------------------------------ |
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_operation_v; -- actual ALU operation |
ctrl_nxt(ctrl_rf_in_mux_msb_c downto ctrl_rf_in_mux_lsb_c) <= "00"; -- RF input = ALU result |
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back (write back all the time) |
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back (permanent write-back) |
if (alu_wait_i = '0') then |
execute_engine.state_nxt <= DISPATCH; |
execute_engine.state_nxt <= DISPATCH; |
end if; |
|
when BRANCH => -- update PC for taken branches and jumps |
921,28 → 863,27
execute_engine.state_nxt <= DISPATCH; |
end if; |
|
when LOAD => -- trigger memory read request |
when LOADSTORE_0 => -- trigger memory request |
-- ------------------------------------------------------------ |
ctrl_nxt(ctrl_bus_rd_c) <= '1'; -- fast read request |
execute_engine.state_nxt <= LOADSTORE_0; |
if (execute_engine.i_reg(instr_opcode_msb_c-1) = '0') then -- LOAD |
ctrl_nxt(ctrl_bus_rd_c) <= '1'; -- read request |
else -- STORE |
ctrl_nxt(ctrl_bus_wr_c) <= '1'; -- write request |
end if; |
execute_engine.state_nxt <= LOADSTORE_1; |
|
when STORE => -- trigger memory write request |
when LOADSTORE_1 => -- memory latency |
-- ------------------------------------------------------------ |
ctrl_nxt(ctrl_bus_wr_c) <= '1'; -- fast write request |
execute_engine.state_nxt <= LOADSTORE_0; |
|
when LOADSTORE_0 => -- memory latency |
-- ------------------------------------------------------------ |
ctrl_nxt(ctrl_bus_mdi_we_c) <= '1'; -- write input data to MDI (only relevant for LOAD) |
execute_engine.state_nxt <= LOADSTORE_1; |
execute_engine.state_nxt <= LOADSTORE_2; |
|
when LOADSTORE_1 => -- wait for bus transaction to finish |
when LOADSTORE_2 => -- wait for bus transaction to finish |
-- ------------------------------------------------------------ |
ctrl_nxt(ctrl_bus_mdi_we_c) <= '1'; -- keep writing input data to MDI (only relevant for LOAD) |
ctrl_nxt(ctrl_rf_in_mux_msb_c downto ctrl_rf_in_mux_lsb_c) <= "01"; -- RF input = memory input (only relevant for LOAD) |
if (ma_load_i = '1') or (be_load_i = '1') or (ma_store_i = '1') or (be_store_i = '1') then -- abort if exception |
execute_engine.state_nxt <= SYS_WAIT; |
elsif (bus_wait_i = '0') then -- wait here for bus to finish transaction |
elsif (bus_d_wait_i = '0') then -- wait here for bus to finish transaction |
if (execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c) = opcode_load_c) then -- LOAD? |
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back |
end if; |
1075,27 → 1016,22
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"343") or -- mtval |
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"344") or -- mip |
-- |
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"c00") and (CPU_EXTENSION_RISCV_E = false) and (CSR_COUNTERS_USE = true)) or -- cycle |
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"c01") and (IO_MTIME_USE = true)) or -- time |
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"c02") and (CPU_EXTENSION_RISCV_E = false) and (CSR_COUNTERS_USE = true)) or -- instret |
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"c80") and (CPU_EXTENSION_RISCV_E = false) and (CSR_COUNTERS_USE = true)) or -- cycleh |
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"c81") and (IO_MTIME_USE = true)) or -- timeh |
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"c82") and (CPU_EXTENSION_RISCV_E = false) and (CSR_COUNTERS_USE = true)) or -- instreth |
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"c00") and (CSR_COUNTERS_USE = true)) or -- cycle |
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"c01") and (CSR_COUNTERS_USE = true)) or -- time |
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"c02") and (CSR_COUNTERS_USE = true)) or -- instret |
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"c80") and (CSR_COUNTERS_USE = true)) or -- cycleh |
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"c81") and (CSR_COUNTERS_USE = true)) or -- timeh |
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"c82") and (CSR_COUNTERS_USE = true)) or -- instreth |
-- |
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"b00") and (CPU_EXTENSION_RISCV_E = false) and (CSR_COUNTERS_USE = true)) or -- mcycle |
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"b02") and (CPU_EXTENSION_RISCV_E = false) and (CSR_COUNTERS_USE = true)) or -- minstret |
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"b80") and (CPU_EXTENSION_RISCV_E = false) and (CSR_COUNTERS_USE = true)) or -- mcycleh |
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"b82") and (CPU_EXTENSION_RISCV_E = false) and (CSR_COUNTERS_USE = true)) or -- minstreth |
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"b00") and (CSR_COUNTERS_USE = true)) or -- mcycle |
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"b02") and (CSR_COUNTERS_USE = true)) or -- minstret |
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"b80") and (CSR_COUNTERS_USE = true)) or -- mcycleh |
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"b82") and (CSR_COUNTERS_USE = true)) or -- minstreth |
-- |
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"f11") or -- mvendorid |
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"f12") or -- marchid |
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"f13") or -- mimpid |
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"f14") or -- mhartid |
-- |
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"fc0") or -- mfeatures |
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"fc1") or -- mclock |
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"fc4") or -- mispacebase |
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"fc5") or -- mispacesize |
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"fc6") or -- mdspacebase |
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"fc7") then -- mdspacesize |
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"f14") then -- mhartid |
illegal_instruction <= '0'; |
else |
illegal_instruction <= '1'; |
1119,7 → 1055,7
when others => -- compressed instruction or undefined instruction |
if (execute_engine.i_reg(1 downto 0) = "11") then -- undefined/unimplemented opcode |
illegal_instruction <= '1'; |
else -- compressed instruction: illegal or disabled / not implemented |
else -- compressed instruction: illegal or not implemented |
illegal_compressed <= ci_illegal; |
end if; |
|
1150,7 → 1086,6
trap_ctrl.exc_ack <= '0'; |
trap_ctrl.irq_ack <= (others => '0'); |
trap_ctrl.cause <= (others => '0'); |
trap_ctrl.exc_src <= (others => '0'); |
trap_ctrl.env_start <= '0'; |
elsif rising_edge(clk_i) then |
if (CPU_EXTENSION_RISCV_Zicsr = true) then |
1167,7 → 1102,7
trap_ctrl.exc_buf(exception_break_c) <= (trap_ctrl.exc_buf(exception_break_c) or trap_ctrl.break_point) and (not trap_ctrl.exc_ack); |
trap_ctrl.exc_buf(exception_iillegal_c) <= (trap_ctrl.exc_buf(exception_iillegal_c) or trap_ctrl.instr_il) and (not trap_ctrl.exc_ack); |
-- interrupt buffer: machine software/external/timer interrupt |
trap_ctrl.irq_buf(interrupt_msw_irq_c) <= csr.mie_msie and (trap_ctrl.irq_buf(interrupt_msw_irq_c) or csr.mip_msip) and (not trap_ctrl.irq_ack(interrupt_msw_irq_c)); |
trap_ctrl.irq_buf(interrupt_msw_irq_c) <= csr.mie_msie and (trap_ctrl.irq_buf(interrupt_msw_irq_c) or msw_irq_i) and (not trap_ctrl.irq_ack(interrupt_msw_irq_c)); |
trap_ctrl.irq_buf(interrupt_mext_irq_c) <= csr.mie_meie and (trap_ctrl.irq_buf(interrupt_mext_irq_c) or clic_irq_i) and (not trap_ctrl.irq_ack(interrupt_mext_irq_c)); |
trap_ctrl.irq_buf(interrupt_mtime_irq_c) <= csr.mie_mtie and (trap_ctrl.irq_buf(interrupt_mtime_irq_c) or mtime_irq_i) and (not trap_ctrl.irq_ack(interrupt_mtime_irq_c)); |
|
1176,7 → 1111,6
if (trap_ctrl.exc_fire = '1') or ((trap_ctrl.irq_fire = '1') and -- exception/IRQ detected! |
((execute_engine.state = EXECUTE) or (execute_engine.state = TRAP))) then -- sample IRQs in EXECUTE or TRAP state only |
trap_ctrl.cause <= trap_ctrl.cause_nxt; -- capture source ID for program |
trap_ctrl.exc_src <= trap_ctrl.exc_buf; -- capture exception source for hardware |
trap_ctrl.exc_ack <= '1'; -- clear execption |
trap_ctrl.irq_ack <= trap_ctrl.irq_ack_nxt; -- capture and clear with interrupt ACK mask |
trap_ctrl.env_start <= '1'; -- now we want to start the trap handler |
1206,77 → 1140,65
trap_ctrl.irq_ack_nxt <= (others => '0'); |
|
-- the following traps are caused by asynchronous exceptions (-> interrupts) |
-- here we do need an acknowledge mask since several sources can trigger at once |
-- here we do need a specific acknowledge mask since several sources can trigger at once |
|
-- interrupt: 1.11 machine external interrupt -- |
if (trap_ctrl.irq_buf(interrupt_mext_irq_c) = '1') then |
trap_ctrl.cause_nxt(data_width_c-1) <= '1'; |
trap_ctrl.cause_nxt(3 downto 0) <= "1011"; |
trap_ctrl.cause_nxt <= trap_mei_c; |
trap_ctrl.irq_ack_nxt(interrupt_mext_irq_c) <= '1'; |
|
-- interrupt: 1.7 machine timer interrupt -- |
elsif (trap_ctrl.irq_buf(interrupt_mtime_irq_c) = '1') then |
trap_ctrl.cause_nxt(data_width_c-1) <= '1'; |
trap_ctrl.cause_nxt(3 downto 0) <= "0111"; |
trap_ctrl.cause_nxt <= trap_mti_c; |
trap_ctrl.irq_ack_nxt(interrupt_mtime_irq_c) <= '1'; |
|
-- interrupt: 1.3 machine SW interrupt -- |
elsif (trap_ctrl.irq_buf(interrupt_msw_irq_c) = '1') then |
trap_ctrl.cause_nxt(data_width_c-1) <= '1'; |
trap_ctrl.cause_nxt(3 downto 0) <= "0011"; |
trap_ctrl.cause_nxt <= trap_msi_c; |
trap_ctrl.irq_ack_nxt(interrupt_msw_irq_c) <= '1'; |
|
|
-- the following traps are caused by synchronous exceptions |
-- here we do not need an acknowledge mask since only one exception (the one |
-- here we do not need a specific acknowledge mask since only one exception (the one |
-- with highest priority) can trigger at once |
|
-- trap/fault: 0.0 instruction address misaligned -- |
elsif (trap_ctrl.exc_buf(exception_ialign_c) = '1') then |
trap_ctrl.cause_nxt(data_width_c-1) <= '0'; |
trap_ctrl.cause_nxt(3 downto 0) <= "0000"; |
|
-- trap/fault: 0.1 instruction access fault -- |
elsif (trap_ctrl.exc_buf(exception_iaccess_c) = '1') then |
trap_ctrl.cause_nxt(data_width_c-1) <= '0'; |
trap_ctrl.cause_nxt(3 downto 0) <= "0001"; |
trap_ctrl.cause_nxt <= trap_iba_c; |
|
-- trap/fault: 0.2 illegal instruction -- |
elsif (trap_ctrl.exc_buf(exception_iillegal_c) = '1') then |
trap_ctrl.cause_nxt(data_width_c-1) <= '0'; |
trap_ctrl.cause_nxt(3 downto 0) <= "0010"; |
trap_ctrl.cause_nxt <= trap_iil_c; |
|
-- trap/fault: 0.0 instruction address misaligned -- |
elsif (trap_ctrl.exc_buf(exception_ialign_c) = '1') then |
trap_ctrl.cause_nxt <= trap_ima_c; |
|
|
-- trap/fault: 0.11 environment call from M-mode -- |
elsif (trap_ctrl.exc_buf(exception_m_envcall_c) = '1') then |
trap_ctrl.cause_nxt(data_width_c-1) <= '0'; |
trap_ctrl.cause_nxt(3 downto 0) <= "1011"; |
trap_ctrl.cause_nxt <= trap_env_c; |
|
-- trap/fault: 0.3 breakpoint -- |
elsif (trap_ctrl.exc_buf(exception_break_c) = '1') then |
trap_ctrl.cause_nxt(data_width_c-1) <= '0'; |
trap_ctrl.cause_nxt(3 downto 0) <= "0011"; |
trap_ctrl.cause_nxt <= trap_brk_c; |
|
|
-- trap/fault: 0.6 store address misaligned - |
elsif (trap_ctrl.exc_buf(exception_salign_c) = '1') then |
trap_ctrl.cause_nxt(data_width_c-1) <= '0'; |
trap_ctrl.cause_nxt(3 downto 0) <= "0110"; |
trap_ctrl.cause_nxt <= trap_sma_c; |
|
-- trap/fault: 0.4 load address misaligned -- |
elsif (trap_ctrl.exc_buf(exception_lalign_c) = '1') then |
trap_ctrl.cause_nxt(data_width_c-1) <= '0'; |
trap_ctrl.cause_nxt(3 downto 0) <= "0100"; |
trap_ctrl.cause_nxt <= trap_lma_c; |
|
-- trap/fault: 0.7 store access fault -- |
elsif (trap_ctrl.exc_buf(exception_saccess_c) = '1') then |
trap_ctrl.cause_nxt(data_width_c-1) <= '0'; |
trap_ctrl.cause_nxt(3 downto 0) <= "0111"; |
trap_ctrl.cause_nxt <= trap_sbe_c; |
|
-- trap/fault: 0.5 load access fault -- |
elsif (trap_ctrl.exc_buf(exception_laccess_c) = '1') then |
trap_ctrl.cause_nxt(data_width_c-1) <= '0'; |
trap_ctrl.cause_nxt(3 downto 0) <= "0101"; |
trap_ctrl.cause_nxt <= trap_lbe_c; |
|
-- undefined / not implemented -- |
else |
1304,9 → 1226,10
csr.mie_meie <= '0'; |
csr.mie_mtie <= '0'; |
csr.mtvec <= (others => '0'); |
csr.mscratch <= (others => '0'); |
csr.mepc <= (others => '0'); |
csr.mcause <= (others => '0'); |
csr.mtval <= (others => '0'); |
csr.mepc <= (others => '0'); |
csr.mip_msip <= '0'; |
elsif rising_edge(clk_i) then |
if (CPU_EXTENSION_RISCV_Zicsr = true) then |
-- access -- |
1313,9 → 1236,6
csr.we <= csr.we_nxt; |
csr.re <= csr.re_nxt; |
|
-- defaults -- |
csr.mip_msip <= '0'; |
|
-- registers that can be modified by user -- |
if (csr.we = '1') then -- manual update |
|
1324,17 → 1244,17
-- machine trap setup -- |
if (execute_engine.i_reg(27 downto 24) = x"0") then |
case execute_engine.i_reg(23 downto 20) is |
when x"0" => -- R/W: mstatus - machine status register |
csr.mstatus_mie <= csr_wdata_i(03); |
csr.mstatus_mpie <= csr_wdata_i(07); |
when x"4" => -- R/W: mie - machine interrupt-enable register |
csr.mie_msie <= csr_wdata_i(03); -- SW IRQ enable |
csr.mie_mtie <= csr_wdata_i(07); -- TIMER IRQ enable |
csr.mie_meie <= csr_wdata_i(11); -- EXT IRQ enable |
when x"5" => -- R/W: mtvec - machine trap-handler base address (for ALL exceptions) |
csr.mtvec <= csr_wdata_i; |
when others => |
NULL; |
when x"0" => -- R/W: mstatus - machine status register |
csr.mstatus_mie <= csr_wdata_i(03); |
csr.mstatus_mpie <= csr_wdata_i(07); |
when x"4" => -- R/W: mie - machine interrupt-enable register |
csr.mie_msie <= csr_wdata_i(03); -- SW IRQ enable |
csr.mie_mtie <= csr_wdata_i(07); -- TIMER IRQ enable |
csr.mie_meie <= csr_wdata_i(11); -- EXT IRQ enable |
when x"5" => -- R/W: mtvec - machine trap-handler base address (for ALL exceptions) |
csr.mtvec <= csr_wdata_i(data_width_c-1 downto 2) & "00"; -- mtvec.MODE=0 |
when others => |
NULL; |
end case; |
end if; |
-- machine trap handling -- |
1343,13 → 1263,11
when x"0" => -- R/W: mscratch - machine scratch register |
csr.mscratch <= csr_wdata_i; |
when x"1" => -- R/W: mepc - machine exception program counter |
csr.mepc <= csr_wdata_i; |
csr.mepc <= csr_wdata_i(data_width_c-1 downto 1) & '0'; |
when x"2" => -- R/W: mcause - machine trap cause |
csr.mcause <= csr_wdata_i; |
when x"3" => -- R/W: mtval - machine bad address or instruction |
csr.mtval <= csr_wdata_i; |
when x"4" => -- R/W: mip - machine interrupt pending |
csr.mip_msip <= csr_wdata_i(03); -- manual SW IRQ trigger |
when others => |
NULL; |
end case; |
1359,19 → 1277,22
-- automatic update by hardware -- |
else |
|
-- machine exception PC & exception value register -- |
if (trap_ctrl.env_start_ack = '1') then -- trap handler started? |
csr.mcause <= trap_ctrl.cause; |
if (csr.mcause(data_width_c-1) = '1') then -- for INTERRUPTS only |
-- machine exception PC & trap value register -- |
if (trap_ctrl.env_start_ack = '1') then -- trap handler starting? |
csr.mcause <= trap_ctrl.cause(4) & "000" & x"000000" & trap_ctrl.cause(3 downto 0); |
if (trap_ctrl.cause(4) = '1') then -- for INTERRUPTS only |
csr.mepc <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- this is the CURRENT pc = interrupted instruction |
csr.mtval <= (others => '0'); -- mtval not defined for interrupts |
csr.mtval <= (others => '0'); -- mtval is zero for interrupts |
else -- for EXCEPTIONS (according to their priority) |
csr.mepc <= execute_engine.last_pc(data_width_c-1 downto 1) & '0'; -- this is the LAST pc = last executed instruction |
if ((trap_ctrl.exc_src(exception_iaccess_c) or trap_ctrl.exc_src(exception_ialign_c)) = '1') then -- instruction access error OR misaligned instruction |
if (trap_ctrl.cause(3 downto 0) = trap_iba_c(3 downto 0)) or -- instr access error OR |
(trap_ctrl.cause(3 downto 0) = trap_ima_c(3 downto 0)) or -- misaligned instruction OR |
(trap_ctrl.cause(3 downto 0) = trap_brk_c(3 downto 0)) or -- breakpoint OR |
(trap_ctrl.cause(3 downto 0) = trap_env_c(3 downto 0)) then -- env call OR |
csr.mtval <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- address of faulting instruction |
elsif (trap_ctrl.exc_src(exception_iillegal_c) = '1') then -- illegal instruction |
csr.mtval <= execute_engine.i_reg; -- the faulting instruction itself |
else -- load/store msialignments/access errors |
elsif (trap_ctrl.cause(3 downto 0) = trap_iil_c(3 downto 0)) then -- illegal instruction |
csr.mtval <= execute_engine.i_reg; -- faulting instruction itself |
else -- load/store misalignments/access errors |
csr.mtval <= mar_i; -- faulting data access address |
end if; |
end if; |
1378,7 → 1299,7
end if; |
|
-- context switch in mstatus -- |
if (trap_ctrl.env_start_ack = '1') then -- actually entering trap |
if (trap_ctrl.env_start_ack = '1') then -- trap handler starting? |
csr.mstatus_mie <= '0'; |
if (csr.mstatus_mpie = '0') then -- prevent loosing the prev MIE state in nested traps |
csr.mstatus_mpie <= csr.mstatus_mie; |
1406,8 → 1327,8
when x"300" => -- R/W: mstatus - machine status register |
csr_rdata_o(03) <= csr.mstatus_mie; -- MIE |
csr_rdata_o(07) <= csr.mstatus_mpie; -- MPIE |
csr_rdata_o(11) <= '1'; -- MPP low |
csr_rdata_o(12) <= '1'; -- MPP high |
csr_rdata_o(11) <= '1'; -- MPP low - M-mode |
csr_rdata_o(12) <= '1'; -- MPP high - M-mode |
when x"301" => -- R/-: misa - ISA and extensions |
csr_rdata_o(02) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_C); -- C CPU extension |
csr_rdata_o(04) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E); -- E CPU extension |
1421,13 → 1342,13
csr_rdata_o(07) <= csr.mie_mtie; -- timer IRQ enable |
csr_rdata_o(11) <= csr.mie_meie; -- external IRQ enable |
when x"305" => -- R/W: mtvec - machine trap-handler base address (for ALL exceptions) |
csr_rdata_o <= csr.mtvec; |
csr_rdata_o <= csr.mtvec(data_width_c-1 downto 2) & "00"; -- mtvec.MODE=0 |
|
-- machine trap handling -- |
when x"340" => -- R/W: mscratch - machine scratch register |
csr_rdata_o <= csr.mscratch; |
when x"341" => -- R/W: mepc - machine exception program counter |
csr_rdata_o <= csr.mepc; |
csr_rdata_o <= csr.mepc(data_width_c-1 downto 1) & '0'; |
when x"342" => -- R/W: mcause - machine trap cause |
csr_rdata_o <= csr.mcause; |
when x"343" => -- R/W: mtval - machine bad address or instruction |
1440,64 → 1361,42
-- counter and timers -- |
when x"c00" | x"b00" => -- R/(W): cycle/mcycle: Cycle counter LOW |
csr_rdata_o <= csr.mcycle(31 downto 0); |
when x"c01" => -- R/-: time: System time LOW (from MTIME unit) |
csr_rdata_o <= systime(31 downto 0); |
when x"c02" | x"b02" => -- R/(W): instret/minstret: Instructions-retired counter LOW |
csr_rdata_o <= csr.minstret(31 downto 0); |
when x"c80" | x"b80" => -- R/(W): cycleh/mcycleh: Cycle counter HIGH |
csr_rdata_o <= csr.mcycleh; |
csr_rdata_o <= x"000" & csr.mcycleh(19 downto 0); -- only the lowest 20 bit! |
when x"c81" => -- R/-: timeh: System time HIGH (from MTIME unit) |
csr_rdata_o <= systime(63 downto 32); |
when x"c82" | x"b82" => -- R/(W): instreth/minstreth: Instructions-retired counter HIGH |
csr_rdata_o <= csr.minstreth; |
csr_rdata_o <= x"000" & csr.minstreth(19 downto 0); -- only the lowest 20 bit! |
|
when x"c01" => -- R/-: time: System time LOW (from MTIME unit) |
csr_rdata_o <= time_i(31 downto 0); |
when x"c81" => -- R/-: timeh: System time HIGH (from MTIME unit) |
csr_rdata_o <= time_i(63 downto 32); |
|
-- machine information registers -- |
when x"f13" => -- R/-: mimpid - implementation ID / version |
when x"f11" => -- R/-: mvendorid |
csr_rdata_o <= (others => '0'); -- not yet assigned for NEORV32 |
when x"f12" => -- R/-: marchid |
csr_rdata_o <= (others => '0'); -- not yet assigned for NEORV32 |
when x"f13" => -- R/-: mimpid - implementation ID / NEORV32: version |
csr_rdata_o <= hw_version_c; |
when x"f14" => -- R/-: mhartid - hardware thread ID |
csr_rdata_o <= HART_ID; |
csr_rdata_o <= HW_THREAD_ID; |
|
-- CUSTOM read-only machine CSRs -- |
when x"fc0" => -- R/-: mfeatures - implemented processor devices/features |
csr_rdata_o(00) <= bool_to_ulogic_f(BOOTLOADER_USE); -- implement processor-internal bootloader? |
csr_rdata_o(01) <= bool_to_ulogic_f(MEM_EXT_USE); -- implement external memory bus interface? |
csr_rdata_o(02) <= bool_to_ulogic_f(MEM_INT_IMEM_USE); -- implement processor-internal instruction memory? |
csr_rdata_o(03) <= bool_to_ulogic_f(MEM_INT_IMEM_ROM); -- implement processor-internal instruction memory as ROM? |
csr_rdata_o(04) <= bool_to_ulogic_f(MEM_INT_DMEM_USE); -- implement processor-internal data memory? |
csr_rdata_o(05) <= bool_to_ulogic_f(CSR_COUNTERS_USE); -- implement RISC-V (performance) counter? |
-- |
csr_rdata_o(16) <= bool_to_ulogic_f(IO_GPIO_USE); -- implement general purpose input/output port unit (GPIO)? |
csr_rdata_o(17) <= bool_to_ulogic_f(IO_MTIME_USE); -- implement machine system timer (MTIME)? |
csr_rdata_o(18) <= bool_to_ulogic_f(IO_UART_USE); -- implement universal asynchronous receiver/transmitter (UART)? |
csr_rdata_o(19) <= bool_to_ulogic_f(IO_SPI_USE); -- implement serial peripheral interface (SPI)? |
csr_rdata_o(20) <= bool_to_ulogic_f(IO_TWI_USE); -- implement two-wire interface (TWI)? |
csr_rdata_o(21) <= bool_to_ulogic_f(IO_PWM_USE); -- implement pulse-width modulation unit (PWM)? |
csr_rdata_o(22) <= bool_to_ulogic_f(IO_WDT_USE); -- implement watch dog timer (WDT)? |
csr_rdata_o(23) <= bool_to_ulogic_f(IO_CLIC_USE); -- implement core local interrupt controller (CLIC)? |
csr_rdata_o(24) <= bool_to_ulogic_f(IO_TRNG_USE); -- implement true random number generator (TRNG)? |
csr_rdata_o(25) <= bool_to_ulogic_f(IO_DEVNULL_USE); -- implement dummy device (DEVNULL)? |
when x"fc1" => -- R/-: mclock - processor clock speed |
csr_rdata_o <= std_ulogic_vector(to_unsigned(CLOCK_FREQUENCY, 32)); |
when x"fc4" => -- R/-: mispacebase - Base address of instruction memory space |
csr_rdata_o <= MEM_ISPACE_BASE; |
when x"fc5" => -- R/-: mdspacebase - Base address of data memory space |
csr_rdata_o <= MEM_DSPACE_BASE; |
when x"fc6" => -- R/-: mispacesize - Total size of instruction memory space in byte |
csr_rdata_o <= std_ulogic_vector(to_unsigned(MEM_ISPACE_SIZE, 32)); |
when x"fc7" => -- R/-: mdspacesize - Total size of data memory space in byte |
csr_rdata_o <= std_ulogic_vector(to_unsigned(MEM_DSPACE_SIZE, 32)); |
|
-- undefined/unavailable -- |
when others => |
csr_rdata_o <= (others => '0'); -- not implemented |
|
end case; |
else |
csr_rdata_o <= (others => '0'); |
end if; |
end if; |
end process csr_read_access; |
|
-- time[h] CSR -- |
systime <= time_i when (CSR_COUNTERS_USE = true) else (others => '0'); |
|
|
-- RISC-V Counter CSRs -------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
csr_counters: process(rstn_i, clk_i) |
1510,7 → 1409,7
mcycle_msb <= '0'; |
minstret_msb <= '0'; |
elsif rising_edge(clk_i) then |
if (CPU_EXTENSION_RISCV_E = false) and (CSR_COUNTERS_USE = true) then |
if (CSR_COUNTERS_USE = true) then |
|
-- mcycle (cycle) -- |
mcycle_msb <= csr.mcycle(csr.mcycle'left); |
1523,7 → 1422,7
|
-- mcycleh (cycleh) -- |
if (csr.we = '1') and (execute_engine.i_reg(31 downto 20) = x"b80") then -- write access |
csr.mcycleh <= csr_wdata_i; |
csr.mcycleh <= csr_wdata_i(19 downto 0); |
elsif ((mcycle_msb xor csr.mcycle(csr.mcycle'left)) = '1') then -- automatic update |
csr.mcycleh <= std_ulogic_vector(unsigned(csr.mcycleh) + 1); |
end if; |
1533,17 → 1432,24
if (csr.we = '1') and (execute_engine.i_reg(31 downto 20) = x"b02") then -- write access |
csr.minstret(31 downto 0) <= csr_wdata_i; |
csr.minstret(32) <= '0'; |
elsif (execute_engine.state_prev /= EXECUTE) and (execute_engine.state = EXECUTE) then -- automatic update |
elsif (execute_engine.state_nxt /= EXECUTE) and (execute_engine.state = EXECUTE) then -- automatic update |
csr.minstret <= std_ulogic_vector(unsigned(csr.minstret) + 1); |
end if; |
|
-- minstreth (instreth) -- |
if (csr.we = '1') and (execute_engine.i_reg(31 downto 20) = x"b82") then -- write access |
csr.minstreth <= csr_wdata_i; |
csr.minstreth <= csr_wdata_i(19 downto 0); |
elsif ((minstret_msb xor csr.minstret(csr.minstret'left)) = '1') then -- automatic update |
csr.minstreth <= std_ulogic_vector(unsigned(csr.minstreth) + 1); |
end if; |
|
else -- if not implemented |
csr.mcycle <= (others => '0'); |
csr.minstret <= (others => '0'); |
csr.mcycleh <= (others => '0'); |
csr.minstreth <= (others => '0'); |
mcycle_msb <= '0'; |
minstret_msb <= '0'; |
end if; |
end if; |
end process csr_counters; |
/neorv32/trunk/rtl/core/neorv32_cpu_cp_muldiv.vhd
60,8 → 60,8
|
architecture neorv32_cpu_cp_muldiv_rtl of neorv32_cpu_cp_muldiv is |
|
-- constants -- |
constant all_zero_c : std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); |
-- configuration - still experimental -- |
constant FAST_MUL_EN : boolean := false; -- use DSPs for faster multiplication |
|
-- controller -- |
type state_t is (IDLE, DECODE, INIT_OPX, INIT_OPY, PROCESSING, FINALIZE, COMPLETED); |
86,9 → 86,13
|
-- multiplier core -- |
signal mul_product : std_ulogic_vector(63 downto 0); |
signal mul_do_add : std_ulogic_vector(32 downto 0); |
signal mul_do_add : std_ulogic_vector(data_width_c downto 0); |
signal mul_sign_cycle : std_ulogic; |
signal mul_p_sext : std_ulogic; |
signal mul_op_x : std_ulogic_vector(32 downto 0); |
signal mul_op_y : std_ulogic_vector(32 downto 0); |
signal mul_buf_ff0 : std_ulogic_vector(65 downto 0); |
signal mul_buf_ff1 : std_ulogic_vector(65 downto 0); |
|
begin |
|
122,7 → 126,7
end if; |
|
when DECODE => |
cnt <= "11111"; |
-- |
if (cp_op = cp_op_div_c) then -- result sign compensation for div? |
div_res_corr <= opx(opx'left) xor opy(opy'left); |
elsif (cp_op = cp_op_rem_c) then -- result sign compensation for rem? |
130,15 → 134,22
else |
div_res_corr <= '0'; |
end if; |
-- if (cp_op = cp_op_div_c) and (opy = all_zero_c) then -- *divide* by 0? |
if (opy = all_zero_c) then -- *divide* by 0? |
-- |
if (or_all_f(opy) = '0') then -- *divide* by 0? |
opy_is_zero <= '1'; |
else |
opy_is_zero <= '0'; |
end if; |
-- |
if (operation = '1') then -- division |
cnt <= "11111"; |
state <= INIT_OPX; |
else -- multiplication |
if (FAST_MUL_EN = false) then |
cnt <= "11111"; |
else |
cnt <= "00101"; -- FIXME |
end if; |
start <= '1'; |
state <= PROCESSING; |
end if; |
182,17 → 193,27
opy_is_signed <= '1' when (cp_op = cp_op_mulh_c) or (cp_op = cp_op_div_c) or (cp_op = cp_op_rem_c) else '0'; |
|
|
-- Multiplier Core ------------------------------------------------------------------------ |
-- Multiplier Core (signed) --------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
multiplier_core: process(clk_i) |
begin |
if rising_edge(clk_i) then |
if (start = '1') then -- start new multiplication |
mul_product(63 downto 32) <= (others => '0'); |
mul_product(31 downto 00) <= opy; |
elsif ((state = PROCESSING) or (state = FINALIZE)) and (operation = '0') then |
mul_product(63 downto 31) <= mul_do_add(32 downto 0); |
mul_product(30 downto 00) <= mul_product(31 downto 1); |
if (FAST_MUL_EN = false) then -- use small iterative computation |
if (start = '1') then -- start new multiplication |
mul_product(63 downto 32) <= (others => '0'); |
mul_product(31 downto 00) <= opy; |
elsif ((state = PROCESSING) or (state = FINALIZE)) and (operation = '0') then |
mul_product(63 downto 31) <= mul_do_add(32 downto 0); |
mul_product(30 downto 00) <= mul_product(31 downto 1); |
end if; |
else -- use direct approach using (several!) DSP blocks |
if (start = '1') then |
mul_op_x <= (opx(opx'left) and opx_is_signed) & opx; |
mul_op_y <= (opy(opy'left) and opy_is_signed) & opy; |
end if; |
mul_buf_ff0 <= std_ulogic_vector(signed(mul_op_x) * signed(mul_op_y)); |
mul_buf_ff1 <= mul_buf_ff0; |
mul_product <= mul_buf_ff1(63 downto 0); -- let the register balancing do the magic here |
end if; |
end if; |
end process multiplier_core; |
200,13 → 221,14
-- MUL: do another addition -- |
mul_update: process(mul_product, mul_sign_cycle, mul_p_sext, opx_is_signed, opx) |
begin |
if (mul_product(0) = '1') then |
if (mul_sign_cycle = '1') then -- for signed operation only: take care of negative weighted MSB |
-- current bit of opy to take care of -- |
if (mul_product(0) = '1') then -- multiply with 1 |
if (mul_sign_cycle = '1') then -- for signed operations only: take care of negative weighted MSB -> multiply with -1 |
mul_do_add <= std_ulogic_vector(unsigned(mul_p_sext & mul_product(63 downto 32)) - unsigned((opx(opx'left) and opx_is_signed) & opx)); |
else |
else -- multiply with +1 |
mul_do_add <= std_ulogic_vector(unsigned(mul_p_sext & mul_product(63 downto 32)) + unsigned((opx(opx'left) and opx_is_signed) & opx)); |
end if; |
else |
else -- multiply with 0 |
mul_do_add <= mul_p_sext & mul_product(63 downto 32); |
end if; |
end process mul_update; |
216,7 → 238,7
mul_p_sext <= mul_product(mul_product'left) and opx_is_signed; |
|
|
-- Divider Core --------------------------------------------------------------------------- |
-- Divider Core (unsigned) ---------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
divider_core: process(clk_i) |
begin |
/neorv32/trunk/rtl/core/neorv32_cpu_regfile.vhd
75,6 → 75,20
-- reading from r0? -- |
signal rs1_clear, rs2_clear : std_ulogic; |
|
|
-- attributes - these are *NOT mandatory*; just for footprint / timing optimization -- |
-- -------------------------------------------------------------------------------- -- |
|
-- lattice radiant -- |
attribute syn_ramstyle : string; |
attribute syn_ramstyle of reg_file : signal is "no_rw_check"; |
attribute syn_ramstyle of reg_file_emb : signal is "no_rw_check"; |
|
-- intel quartus prime -- |
attribute ramstyle : string; |
attribute ramstyle of reg_file : signal is "no_rw_check"; |
attribute ramstyle of reg_file_emb : signal is "no_rw_check"; |
|
begin |
|
-- Input mux ------------------------------------------------------------------------------ |
/neorv32/trunk/rtl/core/neorv32_dmem.vhd
71,7 → 71,18
signal dmem_file_hl : dmem_file_t; |
signal dmem_file_hh : dmem_file_t; |
|
-- RAM attribute to inhibit bypass-logic - Intel only! -- |
|
-- attributes - these are *NOT mandatory*; just for footprint / timing optimization -- |
-- -------------------------------------------------------------------------------- -- |
|
-- lattice radiant -- |
attribute syn_ramstyle : string; |
attribute syn_ramstyle of dmem_file_ll : signal is "no_rw_check"; |
attribute syn_ramstyle of dmem_file_lh : signal is "no_rw_check"; |
attribute syn_ramstyle of dmem_file_hl : signal is "no_rw_check"; |
attribute syn_ramstyle of dmem_file_hh : signal is "no_rw_check"; |
|
-- intel quartus prime -- |
attribute ramstyle : string; |
attribute ramstyle of dmem_file_ll : signal is "no_rw_check"; |
attribute ramstyle of dmem_file_lh : signal is "no_rw_check"; |
/neorv32/trunk/rtl/core/neorv32_imem.vhd
112,16 → 112,31
signal imem_file_ram_hl : imem_file8_t; |
signal imem_file_ram_hh : imem_file8_t; |
|
-- RAM attribute to inhibit bypass-logic - Intel only! -- |
|
-- attributes - these are *NOT mandatory*; just for footprint / timing optimization -- |
-- -------------------------------------------------------------------------------- -- |
|
-- lattice radiant -- |
attribute syn_ramstyle : string; |
attribute syn_ramstyle of imem_file_ram_ll : signal is "no_rw_check"; |
attribute syn_ramstyle of imem_file_ram_lh : signal is "no_rw_check"; |
attribute syn_ramstyle of imem_file_ram_hl : signal is "no_rw_check"; |
attribute syn_ramstyle of imem_file_ram_hh : signal is "no_rw_check"; |
attribute syn_ramstyle of imem_file_init_ram_ll : signal is "no_rw_check"; |
attribute syn_ramstyle of imem_file_init_ram_lh : signal is "no_rw_check"; |
attribute syn_ramstyle of imem_file_init_ram_hl : signal is "no_rw_check"; |
attribute syn_ramstyle of imem_file_init_ram_hh : signal is "no_rw_check"; |
|
-- intel quartus prime -- |
attribute ramstyle : string; |
attribute ramstyle of imem_file_ram_ll : signal is "no_rw_check"; |
attribute ramstyle of imem_file_ram_lh : signal is "no_rw_check"; |
attribute ramstyle of imem_file_ram_hl : signal is "no_rw_check"; |
attribute ramstyle of imem_file_ram_hh : signal is "no_rw_check"; |
attribute ramstyle of imem_file_init_ram_ll : signal is "no_rw_check"; |
attribute ramstyle of imem_file_init_ram_lh : signal is "no_rw_check"; |
attribute ramstyle of imem_file_init_ram_hl : signal is "no_rw_check"; |
attribute ramstyle of imem_file_init_ram_hh : signal is "no_rw_check"; |
attribute ramstyle of imem_file_ram_ll : signal is "no_rw_check"; |
attribute ramstyle of imem_file_ram_lh : signal is "no_rw_check"; |
attribute ramstyle of imem_file_ram_hl : signal is "no_rw_check"; |
attribute ramstyle of imem_file_ram_hh : signal is "no_rw_check"; |
|
begin |
|
/neorv32/trunk/rtl/core/neorv32_package.vhd
41,9 → 41,9
-- Architecture Constants ----------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
constant data_width_c : natural := 32; -- data width - FIXED! |
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01000600"; -- no touchy! |
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01020005"; -- no touchy! |
|
-- Internal Functions --------------------------------------------------------------------- |
-- Helper Functions ----------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
function index_size_f(input : natural) return natural; |
function cond_sel_natural_f(cond : boolean; val_t : natural; val_f : natural) return natural; |
124,15 → 124,19
constant trng_ctrl_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(trng_base_c) + x"00000000"); |
constant trng_data_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(trng_base_c) + x"00000004"); |
|
-- RESERVED -- |
--constant ???_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC8"; -- base address, fixed! |
--constant ???_size_c : natural := 13*4; -- bytes, fixed! |
|
-- Dummy Device (with SIM output) (DEVNULL) -- |
constant devnull_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFFC"; -- base address, fixed! |
-- Dummy Device (with SIMULATION output) (DEVNULL) -- |
constant devnull_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC8"; -- base address, fixed! |
constant devnull_size_c : natural := 1*4; -- bytes, fixed! |
constant devnull_data_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(devnull_base_c) + x"00000000"); |
|
-- RESERVED -- |
--constant ???_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFCC"; -- base address, fixed! |
--constant ???_size_c : natural := 5*4; -- bytes, fixed! |
|
-- System Information Memory (with SIMULATION output) (SYSINFO) -- |
constant sysinfo_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFE0"; -- base address, fixed! |
constant sysinfo_size_c : natural := 8*4; -- bytes, fixed! |
|
-- Main Control Bus ----------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
-- register file -- |
161,9 → 165,9
constant ctrl_alu_cmd1_c : natural := 21; -- ALU command bit 1 |
constant ctrl_alu_cmd2_c : natural := 22; -- ALU command bit 2 |
constant ctrl_alu_opa_mux_lsb_c : natural := 23; -- operand A select lsb (00=rs1, 01=PC) |
constant ctrl_alu_opa_mux_msb_c : natural := 24; -- operand A select msb (10=CSR, 11=?) |
constant ctrl_alu_opa_mux_msb_c : natural := 24; -- operand A select msb (1-=CSR) |
constant ctrl_alu_opb_mux_lsb_c : natural := 25; -- operand B select lsb (00=rs2, 01=IMM) |
constant ctrl_alu_opb_mux_msb_c : natural := 26; -- operand B select msb (10=rs1, 11=?) |
constant ctrl_alu_opb_mux_msb_c : natural := 26; -- operand B select msb (1-=rs1) |
constant ctrl_alu_opc_mux_c : natural := 27; -- operand C select (0=IMM, 1=rs2) |
constant ctrl_alu_unsigned_c : natural := 28; -- is unsigned ALU operation |
constant ctrl_alu_shift_dir_c : natural := 29; -- shift direction (0=left, 1=right) |
173,22 → 177,24
constant ctrl_bus_size_msb_c : natural := 32; -- transfer size msb (10=word, 11=?) |
constant ctrl_bus_rd_c : natural := 33; -- read data request |
constant ctrl_bus_wr_c : natural := 34; -- write data request |
constant ctrl_bus_if_c : natural := 35; -- instruction fetch request (1: output PC, 0: output MAR) |
constant ctrl_bus_if_c : natural := 35; -- instruction fetch request |
constant ctrl_bus_mar_we_c : natural := 36; -- memory address register write enable |
constant ctrl_bus_mdo_we_c : natural := 37; -- memory data out register write enable |
constant ctrl_bus_mdi_we_c : natural := 38; -- memory data in register write enable |
constant ctrl_bus_unsigned_c : natural := 39; -- is unsigned load |
constant ctrl_bus_exc_ack_c : natural := 40; -- acknowledge bus exception |
constant ctrl_bus_reset_c : natural := 41; -- reset bus unit, terminate all actions |
constant ctrl_bus_ierr_ack_c : natural := 40; -- acknowledge instruction fetch bus exception |
constant ctrl_bus_derr_ack_c : natural := 41; -- acknowledge data access bus exception |
constant ctrl_bus_fence_c : natural := 42; -- executed fence operation |
constant ctrl_bus_fencei_c : natural := 43; -- executed fencei operation |
-- co-processor -- |
constant ctrl_cp_use_c : natural := 42; -- is cp operation |
constant ctrl_cp_id_lsb_c : natural := 43; -- cp select lsb |
constant ctrl_cp_id_msb_c : natural := 44; -- cp select msb |
constant ctrl_cp_cmd0_c : natural := 45; -- cp command bit 0 |
constant ctrl_cp_cmd1_c : natural := 46; -- cp command bit 1 |
constant ctrl_cp_cmd2_c : natural := 47; -- cp command bit 2 |
constant ctrl_cp_use_c : natural := 44; -- is cp operation |
constant ctrl_cp_id_lsb_c : natural := 45; -- cp select lsb |
constant ctrl_cp_id_msb_c : natural := 46; -- cp select msb |
constant ctrl_cp_cmd0_c : natural := 47; -- cp command bit 0 |
constant ctrl_cp_cmd1_c : natural := 48; -- cp command bit 1 |
constant ctrl_cp_cmd2_c : natural := 49; -- cp command bit 2 |
-- control bus size -- |
constant ctrl_width_c : natural := 48; -- control bus size |
constant ctrl_width_c : natural := 50; -- control bus size |
|
-- ALU Comparator Bus --------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
309,6 → 315,21
constant alu_cmd_and_c : std_ulogic_vector(2 downto 0) := "110"; -- r <= A and B |
constant alu_cmd_bitc_c : std_ulogic_vector(2 downto 0) := "111"; -- r <= A and (not B) |
|
-- Trap ID Codes -------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
constant trap_ima_c : std_ulogic_vector(4 downto 0) := "00000"; -- 0.0: instruction misaligned |
constant trap_iba_c : std_ulogic_vector(4 downto 0) := "00001"; -- 0.1: instruction access fault |
constant trap_iil_c : std_ulogic_vector(4 downto 0) := "00010"; -- 0.2: illegal instruction |
constant trap_brk_c : std_ulogic_vector(4 downto 0) := "00011"; -- 0.3: breakpoint |
constant trap_lma_c : std_ulogic_vector(4 downto 0) := "00100"; -- 0.4: load address misaligned |
constant trap_lbe_c : std_ulogic_vector(4 downto 0) := "00101"; -- 0.5: load access fault |
constant trap_sma_c : std_ulogic_vector(4 downto 0) := "00110"; -- 0.6: store address misaligned |
constant trap_sbe_c : std_ulogic_vector(4 downto 0) := "00111"; -- 0.7: store access fault |
constant trap_env_c : std_ulogic_vector(4 downto 0) := "01011"; -- 0.11: environment call from m-mode |
constant trap_msi_c : std_ulogic_vector(4 downto 0) := "10011"; -- 1.3: machine software interrupt |
constant trap_mti_c : std_ulogic_vector(4 downto 0) := "10111"; -- 1.7: machine timer interrupt |
constant trap_mei_c : std_ulogic_vector(4 downto 0) := "11011"; -- 1.11: machine external interrupt |
|
-- CPU Control Exception System ----------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
-- exception source bits -- |
323,8 → 344,8
constant exception_laccess_c : natural := 8; -- load access fault |
constant exception_width_c : natural := 9; -- length of this list in bits |
-- interrupt source bits -- |
constant interrupt_mtime_irq_c : natural := 0; -- machine timer interrupt |
constant interrupt_msw_irq_c : natural := 1; -- machine sw interrupt |
constant interrupt_msw_irq_c : natural := 0; -- machine software interrupt |
constant interrupt_mtime_irq_c : natural := 1; -- machine timer interrupt |
constant interrupt_mext_irq_c : natural := 2; -- machine external interrupt |
constant interrupt_width_c : natural := 3; -- length of this list in bits |
|
344,10 → 365,10
component neorv32_top |
generic ( |
-- General -- |
CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz |
HART_ID : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom hardware thread ID |
CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz |
BOOTLOADER_USE : boolean := true; -- implement processor-internal bootloader? |
CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])? |
USER_CODE : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code |
-- RISC-V CPU Extensions -- |
CPU_EXTENSION_RISCV_C : boolean := true; -- implement compressed extension? |
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension? |
395,6 → 416,9
wb_cyc_o : out std_ulogic; -- valid cycle |
wb_ack_i : in std_ulogic := '0'; -- transfer acknowledge |
wb_err_i : in std_ulogic := '0'; -- transfer error |
-- Advanced memory control signals (available if MEM_EXT_USE = true) -- |
fence_o : out std_ulogic; -- indicates an executed FENCE operation |
fencei_o : out std_ulogic; -- indicates an executed FENCEI operation |
-- GPIO -- |
gpio_o : out std_ulogic_vector(15 downto 0); -- parallel output |
gpio_i : in std_ulogic_vector(15 downto 0) := (others => '0'); -- parallel input |
422,61 → 446,50
component neorv32_cpu |
generic ( |
-- General -- |
CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz |
HART_ID : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom hardware thread ID |
BOOTLOADER_USE : boolean := true; -- implement processor-internal bootloader? |
CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])? |
CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])? |
HW_THREAD_ID : std_ulogic_vector(31 downto 0):= x"00000000"; -- hardware thread id |
CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0):= x"00000000"; -- cpu boot address |
-- RISC-V CPU Extensions -- |
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension? |
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension? |
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension? |
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system? |
CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.? |
-- Memory configuration: Instruction memory -- |
MEM_ISPACE_BASE : std_ulogic_vector(31 downto 0) := x"00000000"; -- base address of instruction memory space |
MEM_ISPACE_SIZE : natural := 8*1024; -- total size of instruction memory space in byte |
MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory |
MEM_INT_IMEM_SIZE : natural := 8*1024; -- size of processor-internal instruction memory in bytes |
MEM_INT_IMEM_ROM : boolean := false; -- implement processor-internal instruction memory as ROM |
-- Memory configuration: Data memory -- |
MEM_DSPACE_BASE : std_ulogic_vector(31 downto 0) := x"80000000"; -- base address of data memory space |
MEM_DSPACE_SIZE : natural := 4*1024; -- total size of data memory space in byte |
MEM_INT_DMEM_USE : boolean := true; -- implement processor-internal data memory |
MEM_INT_DMEM_SIZE : natural := 4*1024; -- size of processor-internal data memory in bytes |
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension? |
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension? |
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension? |
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system? |
CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.? |
-- Memory configuration: External memory interface -- |
MEM_EXT_USE : boolean := false; -- implement external memory bus interface? |
MEM_EXT_TIMEOUT : natural := 15; -- cycles after which a valid bus access will timeout |
-- Processor peripherals -- |
IO_GPIO_USE : boolean := true; -- implement general purpose input/output port unit (GPIO)? |
IO_MTIME_USE : boolean := true; -- implement machine system timer (MTIME)? |
IO_UART_USE : boolean := true; -- implement universal asynchronous receiver/transmitter (UART)? |
IO_SPI_USE : boolean := true; -- implement serial peripheral interface (SPI)? |
IO_TWI_USE : boolean := true; -- implement two-wire interface (TWI)? |
IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)? |
IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)? |
IO_CLIC_USE : boolean := true; -- implement core local interrupt controller (CLIC)? |
IO_TRNG_USE : boolean := true; -- implement true random number generator (TRNG)? |
IO_DEVNULL_USE : boolean := true -- implement dummy device (DEVNULL)? |
MEM_EXT_TIMEOUT : natural := 15 -- cycles after which a valid bus access will timeout |
); |
port ( |
-- global control -- |
clk_i : in std_ulogic; -- global clock, rising edge |
rstn_i : in std_ulogic; -- global reset, low-active, async |
-- bus interface -- |
bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable |
bus_we_o : out std_ulogic; -- write enable |
bus_re_o : out std_ulogic; -- read enable |
bus_cancel_o : out std_ulogic; -- cancel current bus transaction |
bus_ack_i : in std_ulogic; -- bus transfer acknowledge |
bus_err_i : in std_ulogic; -- bus transfer error |
clk_i : in std_ulogic; -- global clock, rising edge |
rstn_i : in std_ulogic; -- global reset, low-active, async |
-- instruction bus interface -- |
i_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
i_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
i_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable |
i_bus_we_o : out std_ulogic; -- write enable |
i_bus_re_o : out std_ulogic; -- read enable |
i_bus_cancel_o : out std_ulogic; -- cancel current bus transaction |
i_bus_ack_i : in std_ulogic; -- bus transfer acknowledge |
i_bus_err_i : in std_ulogic; -- bus transfer error |
i_bus_fence_o : out std_ulogic; -- executed FENCEI operation |
-- data bus interface -- |
d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable |
d_bus_we_o : out std_ulogic; -- write enable |
d_bus_re_o : out std_ulogic; -- read enable |
d_bus_cancel_o : out std_ulogic; -- cancel current bus transaction |
d_bus_ack_i : in std_ulogic; -- bus transfer acknowledge |
d_bus_err_i : in std_ulogic; -- bus transfer error |
d_bus_fence_o : out std_ulogic; -- executed FENCE operation |
-- system time input from MTIME -- |
time_i : in std_ulogic_vector(63 downto 0); -- current system time |
time_i : in std_ulogic_vector(63 downto 0); -- current system time |
-- external interrupts -- |
clic_irq_i : in std_ulogic; -- CLIC interrupt request |
mtime_irq_i : in std_ulogic -- machine timer interrupt |
msw_irq_i : in std_ulogic; -- software interrupt |
clic_irq_i : in std_ulogic; -- CLIC interrupt request |
mtime_irq_i : in std_ulogic -- machine timer interrupt |
); |
end component; |
|
485,40 → 498,15
component neorv32_cpu_control |
generic ( |
-- General -- |
CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz |
HART_ID : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom hardware thread ID |
BOOTLOADER_USE : boolean := true; -- implement processor-internal bootloader? |
CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])? |
CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])? |
HW_THREAD_ID : std_ulogic_vector(31 downto 0):= x"00000000"; -- hardware thread id |
CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0):= x"00000000"; -- cpu boot address |
-- RISC-V CPU Extensions -- |
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension? |
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension? |
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension? |
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system? |
CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.? |
-- Memory configuration: Instruction memory -- |
MEM_ISPACE_BASE : std_ulogic_vector(31 downto 0) := x"00000000"; -- base address of instruction memory space |
MEM_ISPACE_SIZE : natural := 16*1024; -- total size of instruction memory space in byte |
MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory |
MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes |
MEM_INT_IMEM_ROM : boolean := false; -- implement processor-internal instruction memory as ROM |
-- Memory configuration: Data memory -- |
MEM_DSPACE_BASE : std_ulogic_vector(31 downto 0) := x"80000000"; -- base address of data memory space |
MEM_DSPACE_SIZE : natural := 8*1024; -- total size of data memory space in byte |
MEM_INT_DMEM_USE : boolean := true; -- implement processor-internal data memory |
MEM_INT_DMEM_SIZE : natural := 8*1024; -- size of processor-internal data memory in bytes |
-- Memory configuration: External memory interface -- |
MEM_EXT_USE : boolean := false; -- implement external memory bus interface? |
-- Processor peripherals -- |
IO_GPIO_USE : boolean := true; -- implement general purpose input/output port unit (GPIO)? |
IO_MTIME_USE : boolean := true; -- implement machine system timer (MTIME)? |
IO_UART_USE : boolean := true; -- implement universal asynchronous receiver/transmitter (UART)? |
IO_SPI_USE : boolean := true; -- implement serial peripheral interface (SPI)? |
IO_TWI_USE : boolean := true; -- implement two-wire interface (TWI)? |
IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)? |
IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)? |
IO_CLIC_USE : boolean := true; -- implement core local interrupt controller (CLIC)? |
IO_TRNG_USE : boolean := true; -- implement true random number generator (TRNG)? |
IO_DEVNULL_USE : boolean := true -- implement dummy device (DEVNULL)? |
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension? |
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension? |
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension? |
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system? |
CPU_EXTENSION_RISCV_Zifencei : boolean := true -- implement instruction stream sync.? |
); |
port ( |
-- global control -- |
527,7 → 515,8
ctrl_o : out std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus |
-- status input -- |
alu_wait_i : in std_ulogic; -- wait for ALU |
bus_wait_i : in std_ulogic; -- wait for bus |
bus_i_wait_i : in std_ulogic; -- wait for bus |
bus_d_wait_i : in std_ulogic; -- wait for bus |
-- data input -- |
instr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- instruction |
cmp_i : in std_ulogic_vector(1 downto 0); -- comparator status |
541,6 → 530,7
csr_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- CSR write data |
csr_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data |
-- external interrupt -- |
msw_irq_i : in std_ulogic; -- software interrupt |
clic_irq_i : in std_ulogic; -- CLIC interrupt request |
mtime_irq_i : in std_ulogic; -- machine timer interrupt |
-- system time input from MTIME -- |
552,8 → 542,7
ma_store_i : in std_ulogic; -- misaligned store data address |
be_instr_i : in std_ulogic; -- bus error on instruction access |
be_load_i : in std_ulogic; -- bus error on load data access |
be_store_i : in std_ulogic; -- bus error on store data access |
bus_busy_i : in std_ulogic -- bus unit is busy |
be_store_i : in std_ulogic -- bus error on store data access |
); |
end component; |
|
635,39 → 624,96
); |
port ( |
-- global control -- |
clk_i : in std_ulogic; -- global clock, rising edge |
rstn_i : in std_ulogic; -- global reset, low-active, async |
ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus |
-- data input -- |
wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- write data |
pc_i : in std_ulogic_vector(data_width_c-1 downto 0); -- current PC |
alu_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU result |
-- data output -- |
instr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- instruction |
rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- read data |
-- status -- |
mar_o : out std_ulogic_vector(data_width_c-1 downto 0); -- current memory address register |
ma_instr_o : out std_ulogic; -- misaligned instruction address |
ma_load_o : out std_ulogic; -- misaligned load data address |
ma_store_o : out std_ulogic; -- misaligned store data address |
be_instr_o : out std_ulogic; -- bus error on instruction access |
be_load_o : out std_ulogic; -- bus error on load data access |
be_store_o : out std_ulogic; -- bus error on store data |
bus_wait_o : out std_ulogic; -- wait for bus operation to finish |
bus_busy_o : out std_ulogic; -- bus unit is busy |
-- bus system -- |
bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable |
bus_we_o : out std_ulogic; -- write enable |
bus_re_o : out std_ulogic; -- read enable |
bus_cancel_o : out std_ulogic; -- cancel current bus transaction |
bus_ack_i : in std_ulogic; -- bus transfer acknowledge |
bus_err_i : in std_ulogic -- bus transfer error |
clk_i : in std_ulogic; -- global clock, rising edge |
rstn_i : in std_ulogic; -- global reset, low-active, async |
ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus |
-- cpu instruction fetch interface -- |
fetch_pc_i : in std_ulogic_vector(data_width_c-1 downto 0); -- PC for instruction fetch |
instr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- instruction |
i_wait_o : out std_ulogic; -- wait for fetch to complete |
-- |
ma_instr_o : out std_ulogic; -- misaligned instruction address |
be_instr_o : out std_ulogic; -- bus error on instruction access |
-- cpu data access interface -- |
addr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU result -> access address |
wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- write data |
rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- read data |
mar_o : out std_ulogic_vector(data_width_c-1 downto 0); -- current memory address register |
d_wait_o : out std_ulogic; -- wait for access to complete |
-- |
ma_load_o : out std_ulogic; -- misaligned load data address |
ma_store_o : out std_ulogic; -- misaligned store data address |
be_load_o : out std_ulogic; -- bus error on load data access |
be_store_o : out std_ulogic; -- bus error on store data access |
-- instruction bus -- |
i_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
i_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
i_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable |
i_bus_we_o : out std_ulogic; -- write enable |
i_bus_re_o : out std_ulogic; -- read enable |
i_bus_cancel_o : out std_ulogic; -- cancel current bus transaction |
i_bus_ack_i : in std_ulogic; -- bus transfer acknowledge |
i_bus_err_i : in std_ulogic; -- bus transfer error |
i_bus_fence_o : out std_ulogic; -- fence operation |
-- data bus -- |
d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable |
d_bus_we_o : out std_ulogic; -- write enable |
d_bus_re_o : out std_ulogic; -- read enable |
d_bus_cancel_o : out std_ulogic; -- cancel current bus transaction |
d_bus_ack_i : in std_ulogic; -- bus transfer acknowledge |
d_bus_err_i : in std_ulogic; -- bus transfer error |
d_bus_fence_o : out std_ulogic -- fence operation |
); |
end component; |
|
-- Component: CPU Bus Switch -------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
component neorv32_busswitch |
generic ( |
PORT_CA_READ_ONLY : boolean := false; -- set if controller port A is read-only |
PORT_CB_READ_ONLY : boolean := false -- set if controller port B is read-only |
); |
port ( |
-- global control -- |
clk_i : in std_ulogic; -- global clock, rising edge |
rstn_i : in std_ulogic; -- global reset, low-active, async |
-- controller interface a -- |
ca_bus_addr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
ca_bus_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
ca_bus_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
ca_bus_ben_i : in std_ulogic_vector(03 downto 0); -- byte enable |
ca_bus_we_i : in std_ulogic; -- write enable |
ca_bus_re_i : in std_ulogic; -- read enable |
ca_bus_cancel_i : in std_ulogic; -- cancel current bus transaction |
ca_bus_ack_o : out std_ulogic; -- bus transfer acknowledge |
ca_bus_err_o : out std_ulogic; -- bus transfer error |
-- controller interface b -- |
cb_bus_addr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
cb_bus_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
cb_bus_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
cb_bus_ben_i : in std_ulogic_vector(03 downto 0); -- byte enable |
cb_bus_we_i : in std_ulogic; -- write enable |
cb_bus_re_i : in std_ulogic; -- read enable |
cb_bus_cancel_i : in std_ulogic; -- cancel current bus transaction |
cb_bus_ack_o : out std_ulogic; -- bus transfer acknowledge |
cb_bus_err_o : out std_ulogic; -- bus transfer error |
-- peripheral bus -- |
p_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
p_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
p_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
p_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable |
p_bus_we_o : out std_ulogic; -- write enable |
p_bus_re_o : out std_ulogic; -- read enable |
p_bus_cancel_o : out std_ulogic; -- cancel current bus transaction |
p_bus_ack_i : in std_ulogic; -- bus transfer acknowledge |
p_bus_err_i : in std_ulogic -- bus transfer error |
); |
end component; |
|
-- Component: CPU Compressed Instructions Decompressor ------------------------------------ |
-- ------------------------------------------------------------------------------------------- |
component neorv32_cpu_decompressor |
989,6 → 1035,49
); |
end component; |
|
---- Component: System Configuration Information Memory (SYSINFO) --------------------------- |
---- ------------------------------------------------------------------------------------------- |
component neorv32_sysinfo |
generic ( |
-- General -- |
CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz |
BOOTLOADER_USE : boolean := true; -- implement processor-internal bootloader? |
USER_CODE : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code |
-- Memory configuration: Instruction memory -- |
MEM_ISPACE_BASE : std_ulogic_vector(31 downto 0) := x"00000000"; -- base address of instruction memory space |
MEM_ISPACE_SIZE : natural := 8*1024; -- total size of instruction memory space in byte |
MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory |
MEM_INT_IMEM_SIZE : natural := 8*1024; -- size of processor-internal instruction memory in bytes |
MEM_INT_IMEM_ROM : boolean := false; -- implement processor-internal instruction memory as ROM |
-- Memory configuration: Data memory -- |
MEM_DSPACE_BASE : std_ulogic_vector(31 downto 0) := x"80000000"; -- base address of data memory space |
MEM_DSPACE_SIZE : natural := 4*1024; -- total size of data memory space in byte |
MEM_INT_DMEM_USE : boolean := true; -- implement processor-internal data memory |
MEM_INT_DMEM_SIZE : natural := 4*1024; -- size of processor-internal data memory in bytes |
-- Memory configuration: External memory interface -- |
MEM_EXT_USE : boolean := false; -- implement external memory bus interface? |
-- Processor peripherals -- |
IO_GPIO_USE : boolean := true; -- implement general purpose input/output port unit (GPIO)? |
IO_MTIME_USE : boolean := true; -- implement machine system timer (MTIME)? |
IO_UART_USE : boolean := true; -- implement universal asynchronous receiver/transmitter (UART)? |
IO_SPI_USE : boolean := true; -- implement serial peripheral interface (SPI)? |
IO_TWI_USE : boolean := true; -- implement two-wire interface (TWI)? |
IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)? |
IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)? |
IO_CLIC_USE : boolean := true; -- implement core local interrupt controller (CLIC)? |
IO_TRNG_USE : boolean := true; -- implement true random number generator (TRNG)? |
IO_DEVNULL_USE : boolean := true -- implement dummy device (DEVNULL)? |
); |
port ( |
-- host access -- |
clk_i : in std_ulogic; -- global clock line |
addr_i : in std_ulogic_vector(31 downto 0); -- address |
rden_i : in std_ulogic; -- read enable |
data_o : out std_ulogic_vector(31 downto 0); -- data out |
ack_o : out std_ulogic -- transfer acknowledge |
); |
end component; |
|
end neorv32_package; |
|
package body neorv32_package is |
/neorv32/trunk/rtl/core/neorv32_sysinfo.vhd
0,0 → 1,171
-- ################################################################################################# |
-- # << NEORV32 - System/Processor Configuration Information Memory (SYSINFO) >> # |
-- # ********************************************************************************************* # |
-- # This unit provides information regarding the 'system' configuration - mostly derived from the # |
-- # top's configuration generics. # |
-- # ********************************************************************************************* # |
-- # BSD 3-Clause License # |
-- # # |
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. # |
-- # # |
-- # Redistribution and use in source and binary forms, with or without modification, are # |
-- # permitted provided that the following conditions are met: # |
-- # # |
-- # 1. Redistributions of source code must retain the above copyright notice, this list of # |
-- # conditions and the following disclaimer. # |
-- # # |
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # |
-- # conditions and the following disclaimer in the documentation and/or other materials # |
-- # provided with the distribution. # |
-- # # |
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # |
-- # endorse or promote products derived from this software without specific prior written # |
-- # permission. # |
-- # # |
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # |
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # |
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # |
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # |
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # |
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # |
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # |
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # |
-- # OF THE POSSIBILITY OF SUCH DAMAGE. # |
-- # ********************************************************************************************* # |
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # |
-- ################################################################################################# |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |
|
library neorv32; |
use neorv32.neorv32_package.all; |
|
entity neorv32_sysinfo is |
generic ( |
-- General -- |
CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz |
BOOTLOADER_USE : boolean := true; -- implement processor-internal bootloader? |
USER_CODE : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code |
-- Memory configuration: Instruction memory -- |
MEM_ISPACE_BASE : std_ulogic_vector(31 downto 0) := x"00000000"; -- base address of instruction memory space |
MEM_ISPACE_SIZE : natural := 8*1024; -- total size of instruction memory space in byte |
MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory |
MEM_INT_IMEM_SIZE : natural := 8*1024; -- size of processor-internal instruction memory in bytes |
MEM_INT_IMEM_ROM : boolean := false; -- implement processor-internal instruction memory as ROM |
-- Memory configuration: Data memory -- |
MEM_DSPACE_BASE : std_ulogic_vector(31 downto 0) := x"80000000"; -- base address of data memory space |
MEM_DSPACE_SIZE : natural := 4*1024; -- total size of data memory space in byte |
MEM_INT_DMEM_USE : boolean := true; -- implement processor-internal data memory |
MEM_INT_DMEM_SIZE : natural := 4*1024; -- size of processor-internal data memory in bytes |
-- Memory configuration: External memory interface -- |
MEM_EXT_USE : boolean := false; -- implement external memory bus interface? |
-- Processor peripherals -- |
IO_GPIO_USE : boolean := true; -- implement general purpose input/output port unit (GPIO)? |
IO_MTIME_USE : boolean := true; -- implement machine system timer (MTIME)? |
IO_UART_USE : boolean := true; -- implement universal asynchronous receiver/transmitter (UART)? |
IO_SPI_USE : boolean := true; -- implement serial peripheral interface (SPI)? |
IO_TWI_USE : boolean := true; -- implement two-wire interface (TWI)? |
IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)? |
IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)? |
IO_CLIC_USE : boolean := true; -- implement core local interrupt controller (CLIC)? |
IO_TRNG_USE : boolean := true; -- implement true random number generator (TRNG)? |
IO_DEVNULL_USE : boolean := true -- implement dummy device (DEVNULL)? |
); |
port ( |
-- host access -- |
clk_i : in std_ulogic; -- global clock line |
addr_i : in std_ulogic_vector(31 downto 0); -- address |
rden_i : in std_ulogic; -- read enable |
data_o : out std_ulogic_vector(31 downto 0); -- data out |
ack_o : out std_ulogic -- transfer acknowledge |
); |
end neorv32_sysinfo; |
|
architecture neorv32_sysinfo_rtl of neorv32_sysinfo is |
|
-- IO space: module base address -- |
constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit |
constant lo_abb_c : natural := index_size_f(sysinfo_size_c); -- low address boundary bit |
|
-- access control -- |
signal acc_en : std_ulogic; -- module access enable |
signal addr : std_ulogic_vector(31 downto 0); |
signal rden : std_ulogic; |
signal info_addr : std_ulogic_vector(02 downto 0); |
|
-- system information ROM -- |
type info_mem_t is array (0 to 7) of std_ulogic_vector(31 downto 0); |
signal sysinfo_mem : info_mem_t; |
|
begin |
|
-- Access Control ------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = sysinfo_base_c(hi_abb_c downto lo_abb_c)) else '0'; |
rden <= acc_en and rden_i; -- valid read access |
addr <= sysinfo_base_c(31 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 2) & "00"; -- word aligned |
info_addr <= addr(index_size_f(sysinfo_size_c)-1 downto 2); |
|
|
-- Construct Info ROM --------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
|
-- SYSINFO(0): Processor (primary) clock frequency -- |
sysinfo_mem(0) <= std_ulogic_vector(to_unsigned(CLOCK_FREQUENCY, 32)); |
|
-- SYSINFO(1): Custom user code -- |
sysinfo_mem(1) <= USER_CODE; |
|
-- SYSINFO(2): Implemented processor devices/features -- |
-- Memory |
sysinfo_mem(2)(00) <= bool_to_ulogic_f(BOOTLOADER_USE); -- implement processor-internal bootloader? |
sysinfo_mem(2)(01) <= bool_to_ulogic_f(MEM_EXT_USE); -- implement external memory bus interface? |
sysinfo_mem(2)(02) <= bool_to_ulogic_f(MEM_INT_IMEM_USE); -- implement processor-internal instruction memory? |
sysinfo_mem(2)(03) <= bool_to_ulogic_f(MEM_INT_IMEM_ROM); -- implement processor-internal instruction memory as ROM? |
sysinfo_mem(2)(04) <= bool_to_ulogic_f(MEM_INT_DMEM_USE); -- implement processor-internal data memory? |
-- IO |
sysinfo_mem(2)(16) <= bool_to_ulogic_f(IO_GPIO_USE); -- implement general purpose input/output port unit (GPIO)? |
sysinfo_mem(2)(17) <= bool_to_ulogic_f(IO_MTIME_USE); -- implement machine system timer (MTIME)? |
sysinfo_mem(2)(18) <= bool_to_ulogic_f(IO_UART_USE); -- implement universal asynchronous receiver/transmitter (UART)? |
sysinfo_mem(2)(19) <= bool_to_ulogic_f(IO_SPI_USE); -- implement serial peripheral interface (SPI)? |
sysinfo_mem(2)(20) <= bool_to_ulogic_f(IO_TWI_USE); -- implement two-wire interface (TWI)? |
sysinfo_mem(2)(21) <= bool_to_ulogic_f(IO_PWM_USE); -- implement pulse-width modulation unit (PWM)? |
sysinfo_mem(2)(22) <= bool_to_ulogic_f(IO_WDT_USE); -- implement watch dog timer (WDT)? |
sysinfo_mem(2)(23) <= bool_to_ulogic_f(IO_CLIC_USE); -- implement core local interrupt controller (CLIC)? |
sysinfo_mem(2)(24) <= bool_to_ulogic_f(IO_TRNG_USE); -- implement true random number generator (TRNG)? |
sysinfo_mem(2)(25) <= bool_to_ulogic_f(IO_DEVNULL_USE); -- implement dummy device (DEVNULL)? |
|
-- SYSINFO(3): reserved -- |
sysinfo_mem(3) <= (others => '0'); -- reserved - maybe for technology-specific configuration options? |
|
-- SYSINFO(4): Base address of instruction memory space -- |
sysinfo_mem(4) <= MEM_ISPACE_BASE; |
|
-- SYSINFO(5): Base address of data memory space -- |
sysinfo_mem(5) <= MEM_DSPACE_BASE; |
|
-- SYSINFO(6): Total size of instruction memory space in bytes -- |
sysinfo_mem(6) <= std_ulogic_vector(to_unsigned(MEM_ISPACE_SIZE, 32)); |
|
-- SYSINFO(7): Total size of data memory space in bytes -- |
sysinfo_mem(7) <= std_ulogic_vector(to_unsigned(MEM_DSPACE_SIZE, 32)); |
|
|
-- Read Access ---------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
read_access: process(clk_i) |
begin |
if rising_edge(clk_i) then |
ack_o <= rden; |
if (rden = '1') then |
data_o <= sysinfo_mem(to_integer(unsigned(info_addr))); |
else |
data_o <= (others => '0'); |
end if; |
end if; |
end process read_access; |
|
|
end neorv32_sysinfo_rtl; |
/neorv32/trunk/rtl/core/neorv32_top.vhd
47,10 → 47,10
entity neorv32_top is |
generic ( |
-- General -- |
CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz |
HART_ID : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom hardware thread ID |
CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz |
BOOTLOADER_USE : boolean := true; -- implement processor-internal bootloader? |
CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])? |
USER_CODE : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code |
-- RISC-V CPU Extensions -- |
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension? |
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension? |
98,6 → 98,9
wb_cyc_o : out std_ulogic; -- valid cycle |
wb_ack_i : in std_ulogic := '0'; -- transfer acknowledge |
wb_err_i : in std_ulogic := '0'; -- transfer error |
-- Advanced memory control signals (available if MEM_EXT_USE = true) -- |
fence_o : out std_ulogic; -- indicates an executed FENCE operation |
fencei_o : out std_ulogic; -- indicates an executed FENCEI operation |
-- GPIO (available if IO_GPIO_USE = true) -- |
gpio_o : out std_ulogic_vector(15 downto 0); -- parallel output |
gpio_i : in std_ulogic_vector(15 downto 0) := (others => '0'); -- parallel input |
122,6 → 125,9
|
architecture neorv32_top_rtl of neorv32_top is |
|
-- CPU boot address -- |
constant boot_addr_c : std_ulogic_vector(31 downto 0) := cond_sel_stdulogicvector_f(BOOTLOADER_USE, boot_base_c, MEM_ISPACE_BASE); |
|
-- reset generator -- |
signal rstn_i_sync0 : std_ulogic; |
signal rstn_i_sync1 : std_ulogic; |
141,8 → 147,8
signal twi_cg_en : std_ulogic; |
signal pwm_cg_en : std_ulogic; |
|
-- cpu bus -- |
type cpu_bus_t is record |
-- bus interface -- |
type bus_interface_t is record |
addr : std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
rdata : std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
wdata : std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
152,8 → 158,9
cancel : std_ulogic; -- cancel current transfer |
ack : std_ulogic; -- bus transfer acknowledge |
err : std_ulogic; -- bus transfer error |
fence : std_ulogic; -- fence(i) instruction executed |
end record; |
signal cpu : cpu_bus_t; |
signal cpu_i, cpu_d, p_bus : bus_interface_t; |
|
-- io space access -- |
signal io_acc : std_ulogic; |
190,6 → 197,8
signal trng_ack : std_ulogic; |
signal devnull_rdata : std_ulogic_vector(data_width_c-1 downto 0); |
signal devnull_ack : std_ulogic; |
signal sysinfo_rdata : std_ulogic_vector(data_width_c-1 downto 0); |
signal sysinfo_ack : std_ulogic; |
|
-- IRQs -- |
signal mtime_irq : std_ulogic; |
227,7 → 236,7
end if; |
end if; |
|
-- memory system - address space -- |
-- memory system -- |
if (MEM_INT_IMEM_USE = true) and (MEM_INT_IMEM_SIZE > MEM_ISPACE_SIZE) then |
assert false report "NEORV32 CONFIG ERROR! Internal instruction memory (IMEM) cannot be greater than total instruction address space." severity error; |
end if; |
234,8 → 243,8
if (MEM_INT_DMEM_USE = true) and (MEM_INT_DMEM_SIZE > MEM_DSPACE_SIZE) then |
assert false report "NEORV32 CONFIG ERROR! Internal data memory (DMEM) cannot be greater than total data address space." severity error; |
end if; |
if (MEM_EXT_TIMEOUT <= 1) then |
assert false report "NEORV32 CONFIG ERROR! Invalid bus timeout. Internal components require 1 cycle delay." severity error; |
if (MEM_EXT_TIMEOUT < 1) then |
assert false report "NEORV32 CONFIG ERROR! Invalid bus timeout. Processor-internal components have 1 cycle delay." severity error; |
end if; |
|
-- clock -- |
245,7 → 254,7
|
-- CSR system not implemented -- |
if (CPU_EXTENSION_RISCV_Zicsr = false) then |
assert false report "NEORV32 CONFIG WARNING! No exception/interrupt/machine status features available when CPU_EXTENSION_RISCV_Zicsr = false." severity warning; |
assert false report "NEORV32 CONFIG WARNING! No exception/interrupt/machine features available when CPU_EXTENSION_RISCV_Zicsr = false." severity warning; |
end if; |
-- core local interrupt controller -- |
if (CPU_EXTENSION_RISCV_Zicsr = false) and (IO_CLIC_USE = true) then |
254,10 → 263,10
|
-- memory layout notifier -- |
if (MEM_ISPACE_BASE /= x"00000000") then |
assert false report "NEORV32 CONFIG WARNING! Non-default base address for instruction address space. Make sure this is sync with the linker script." severity warning; |
assert false report "NEORV32 CONFIG WARNING! Non-default base address for instruction address space. Make sure this is sync with the software framwork." severity warning; |
end if; |
if (MEM_DSPACE_BASE /= x"80000000") then |
assert false report "NEORV32 CONFIG WARNING! Non-default base address for data address space. Make sure this is sync with the linker script." severity warning; |
assert false report "NEORV32 CONFIG WARNING! Non-default base address for data address space. Make sure this is sync with the software framwork." severity warning; |
end if; |
end if; |
end process sanity_check; |
321,10 → 330,9
neorv32_cpu_inst: neorv32_cpu |
generic map ( |
-- General -- |
CLOCK_FREQUENCY => CLOCK_FREQUENCY, -- clock frequency of clk_i in Hz |
HART_ID => HART_ID, -- custom hardware thread ID |
BOOTLOADER_USE => BOOTLOADER_USE, -- implement processor-internal bootloader? |
CSR_COUNTERS_USE => CSR_COUNTERS_USE, -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])? |
CSR_COUNTERS_USE => CSR_COUNTERS_USE, -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])? |
HW_THREAD_ID => (others => '0'), -- hardware thread id |
CPU_BOOT_ADDR => boot_addr_c, -- cpu boot address |
-- RISC-V CPU Extensions -- |
CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension? |
CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E, -- implement embedded RF extension? |
331,65 → 339,103
CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement muld/div extension? |
CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr, -- implement CSR system? |
CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.? |
-- Memory configuration: Instruction memory -- |
MEM_ISPACE_BASE => MEM_ISPACE_BASE, -- base address of instruction memory space |
MEM_ISPACE_SIZE => MEM_ISPACE_SIZE, -- total size of instruction memory space in byte |
MEM_INT_IMEM_USE => MEM_INT_IMEM_USE, -- implement processor-internal instruction memory |
MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes |
MEM_INT_IMEM_ROM => MEM_INT_IMEM_ROM, -- implement processor-internal instruction memory as ROM |
-- Memory configuration: Data memory -- |
MEM_DSPACE_BASE => MEM_DSPACE_BASE, -- base address of data memory space |
MEM_DSPACE_SIZE => MEM_DSPACE_SIZE, -- total size of data memory space in byte |
MEM_INT_DMEM_USE => MEM_INT_DMEM_USE, -- implement processor-internal data memory |
MEM_INT_DMEM_SIZE => MEM_INT_DMEM_SIZE, -- size of processor-internal data memory in bytes |
-- Memory configuration: External memory interface -- |
MEM_EXT_USE => MEM_EXT_USE, -- implement external memory bus interface? |
MEM_EXT_TIMEOUT => MEM_EXT_TIMEOUT, -- cycles after which a valid bus access will timeout |
-- Processor peripherals -- |
IO_GPIO_USE => IO_GPIO_USE, -- implement general purpose input/output port unit (GPIO)? |
IO_MTIME_USE => IO_MTIME_USE, -- implement machine system timer (MTIME)? |
IO_UART_USE => IO_UART_USE, -- implement universal asynchronous receiver/transmitter (UART)? |
IO_SPI_USE => IO_SPI_USE, -- implement serial peripheral interface (SPI)? |
IO_TWI_USE => IO_TWI_USE, -- implement two-wire interface (TWI)? |
IO_PWM_USE => IO_PWM_USE, -- implement pulse-width modulation unit (PWM)? |
IO_WDT_USE => IO_WDT_USE, -- implement watch dog timer (WDT)? |
IO_CLIC_USE => IO_CLIC_USE, -- implement core local interrupt controller (CLIC)? |
IO_TRNG_USE => IO_TRNG_USE, -- implement true random number generator (TRNG)? |
IO_DEVNULL_USE => IO_DEVNULL_USE -- implement dummy device (DEVNULL)? |
MEM_EXT_TIMEOUT => MEM_EXT_TIMEOUT -- cycles after which a valid bus access will timeout |
) |
port map ( |
-- global control -- |
clk_i => clk_i, -- global clock, rising edge |
rstn_i => sys_rstn, -- global reset, low-active, async |
-- bus interface -- |
bus_addr_o => cpu.addr, -- bus access address |
bus_rdata_i => cpu.rdata, -- bus read data |
bus_wdata_o => cpu.wdata, -- bus write data |
bus_ben_o => cpu.ben, -- byte enable |
bus_we_o => cpu.we, -- write enable |
bus_re_o => cpu.re, -- read enable |
bus_cancel_o => cpu.cancel, -- cancel current bus transaction |
bus_ack_i => cpu.ack, -- bus transfer acknowledge |
bus_err_i => cpu.err, -- bus transfer error |
clk_i => clk_i, -- global clock, rising edge |
rstn_i => sys_rstn, -- global reset, low-active, async |
-- instruction bus interface -- |
i_bus_addr_o => cpu_i.addr, -- bus access address |
i_bus_rdata_i => cpu_i.rdata, -- bus read data |
i_bus_wdata_o => cpu_i.wdata, -- bus write data |
i_bus_ben_o => cpu_i.ben, -- byte enable |
i_bus_we_o => cpu_i.we, -- write enable |
i_bus_re_o => cpu_i.re, -- read enable |
i_bus_cancel_o => cpu_i.cancel, -- cancel current bus transaction |
i_bus_ack_i => cpu_i.ack, -- bus transfer acknowledge |
i_bus_err_i => cpu_i.err, -- bus transfer error |
i_bus_fence_o => cpu_i.fence, -- executed FENCEI operation |
-- data bus interface -- |
d_bus_addr_o => cpu_d.addr, -- bus access address |
d_bus_rdata_i => cpu_d.rdata, -- bus read data |
d_bus_wdata_o => cpu_d.wdata, -- bus write data |
d_bus_ben_o => cpu_d.ben, -- byte enable |
d_bus_we_o => cpu_d.we, -- write enable |
d_bus_re_o => cpu_d.re, -- read enable |
d_bus_cancel_o => cpu_d.cancel, -- cancel current bus transaction |
d_bus_ack_i => cpu_d.ack, -- bus transfer acknowledge |
d_bus_err_i => cpu_d.err, -- bus transfer error |
d_bus_fence_o => cpu_d.fence, -- executed FENCE operation |
-- system time input from MTIME -- |
time_i => mtime_time, -- current system time |
time_i => mtime_time, -- current system time |
-- external interrupts -- |
clic_irq_i => clic_irq, -- CLIC interrupt request |
mtime_irq_i => mtime_irq -- machine timer interrupt |
msw_irq_i => '0', -- software interrupt |
clic_irq_i => clic_irq, -- CLIC interrupt request |
mtime_irq_i => mtime_irq -- machine timer interrupt |
); |
|
-- CPU data input -- |
cpu.rdata <= (imem_rdata or dmem_rdata or bootrom_rdata) or wishbone_rdata or (gpio_rdata or mtime_rdata or |
uart_rdata or spi_rdata or twi_rdata or pwm_rdata or wdt_rdata or clic_rdata or trng_rdata or devnull_rdata); |
|
-- CPU ACK input -- |
cpu.ack <= (imem_ack or dmem_ack or bootrom_ack) or wishbone_ack or (gpio_ack or mtime_ack or |
uart_ack or spi_ack or twi_ack or pwm_ack or wdt_ack or clic_ack or trng_ack or devnull_ack); |
-- CPU Crossbar Switch -------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
neorv32_busswitch_inst: neorv32_busswitch |
generic map ( |
PORT_CA_READ_ONLY => false, -- set if controller port A is read-only |
PORT_CB_READ_ONLY => true -- set if controller port B is read-only |
) |
port map ( |
-- global control -- |
clk_i => clk_i, -- global clock, rising edge |
rstn_i => sys_rstn, -- global reset, low-active, async |
-- controller interface a -- |
ca_bus_addr_i => cpu_d.addr, -- bus access address |
ca_bus_rdata_o => cpu_d.rdata, -- bus read data |
ca_bus_wdata_i => cpu_d.wdata, -- bus write data |
ca_bus_ben_i => cpu_d.ben, -- byte enable |
ca_bus_we_i => cpu_d.we, -- write enable |
ca_bus_re_i => cpu_d.re, -- read enable |
ca_bus_cancel_i => cpu_d.cancel, -- cancel current bus transaction |
ca_bus_ack_o => cpu_d.ack, -- bus transfer acknowledge |
ca_bus_err_o => cpu_d.err, -- bus transfer error |
-- controller interface b -- |
cb_bus_addr_i => cpu_i.addr, -- bus access address |
cb_bus_rdata_o => cpu_i.rdata, -- bus read data |
cb_bus_wdata_i => cpu_i.wdata, -- bus write data |
cb_bus_ben_i => cpu_i.ben, -- byte enable |
cb_bus_we_i => cpu_i.we, -- write enable |
cb_bus_re_i => cpu_i.re, -- read enable |
cb_bus_cancel_i => cpu_i.cancel, -- cancel current bus transaction |
cb_bus_ack_o => cpu_i.ack, -- bus transfer acknowledge |
cb_bus_err_o => cpu_i.err, -- bus transfer error |
-- peripheral bus -- |
p_bus_addr_o => p_bus.addr, -- bus access address |
p_bus_rdata_i => p_bus.rdata, -- bus read data |
p_bus_wdata_o => p_bus.wdata, -- bus write data |
p_bus_ben_o => p_bus.ben, -- byte enable |
p_bus_we_o => p_bus.we, -- write enable |
p_bus_re_o => p_bus.re, -- read enable |
p_bus_cancel_o => p_bus.cancel, -- cancel current bus transaction |
p_bus_ack_i => p_bus.ack, -- bus transfer acknowledge |
p_bus_err_i => p_bus.err -- bus transfer error |
); |
|
-- CPU bus error input -- |
cpu.err <= wishbone_err; |
-- advanced memory control -- |
fence_o <= cpu_d.fence; -- indicates an executed FENCE operation |
fencei_o <= cpu_i.fence; -- indicates an executed FENCEI operation |
|
-- process bus: CPU data input -- |
p_bus.rdata <= (imem_rdata or dmem_rdata or bootrom_rdata) or wishbone_rdata or (gpio_rdata or mtime_rdata or uart_rdata or |
spi_rdata or twi_rdata or pwm_rdata or wdt_rdata or clic_rdata or trng_rdata or devnull_rdata or sysinfo_rdata); |
|
-- process bus: CPU data ACK input -- |
p_bus.ack <= (imem_ack or dmem_ack or bootrom_ack) or wishbone_ack or (gpio_ack or mtime_ack or uart_ack or |
spi_ack or twi_ack or pwm_ack or wdt_ack or clic_ack or trng_ack or devnull_ack or sysinfo_ack); |
|
-- process bus: CPU data bus error input -- |
p_bus.err <= wishbone_err; |
|
|
-- Processor-Internal Instruction Memory (IMEM) ------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
neorv32_int_imem_inst_true: |
402,15 → 448,15
BOOTLOADER_USE => BOOTLOADER_USE -- implement and use bootloader? |
) |
port map ( |
clk_i => clk_i, -- global clock line |
rden_i => cpu.re, -- read enable |
wren_i => cpu.we, -- write enable |
ben_i => cpu.ben, -- byte write enable |
upen_i => '1', -- update enable |
addr_i => cpu.addr, -- address |
data_i => cpu.wdata, -- data in |
data_o => imem_rdata, -- data out |
ack_o => imem_ack -- transfer acknowledge |
clk_i => clk_i, -- global clock line |
rden_i => p_bus.re, -- read enable |
wren_i => p_bus.we, -- write enable |
ben_i => p_bus.ben, -- byte write enable |
upen_i => '1', -- update enable |
addr_i => p_bus.addr, -- address |
data_i => p_bus.wdata, -- data in |
data_o => imem_rdata, -- data out |
ack_o => imem_ack -- transfer acknowledge |
); |
end generate; |
|
431,14 → 477,14
DMEM_SIZE => MEM_INT_DMEM_SIZE -- processor-internal data memory size in bytes |
) |
port map ( |
clk_i => clk_i, -- global clock line |
rden_i => cpu.re, -- read enable |
wren_i => cpu.we, -- write enable |
ben_i => cpu.ben, -- byte write enable |
addr_i => cpu.addr, -- address |
data_i => cpu.wdata, -- data in |
data_o => dmem_rdata, -- data out |
ack_o => dmem_ack -- transfer acknowledge |
clk_i => clk_i, -- global clock line |
rden_i => p_bus.re, -- read enable |
wren_i => p_bus.we, -- write enable |
ben_i => p_bus.ben, -- byte write enable |
addr_i => p_bus.addr, -- address |
data_i => p_bus.wdata, -- data in |
data_o => dmem_rdata, -- data out |
ack_o => dmem_ack -- transfer acknowledge |
); |
end generate; |
|
456,8 → 502,8
neorv32_boot_rom_inst: neorv32_boot_rom |
port map ( |
clk_i => clk_i, -- global clock line |
rden_i => cpu.re, -- read enable |
addr_i => cpu.addr, -- address |
rden_i => p_bus.re, -- read enable |
addr_i => p_bus.addr, -- address |
data_o => bootrom_rdata, -- data out |
ack_o => bootrom_ack -- transfer acknowledge |
); |
478,15 → 524,15
generic map ( |
INTERFACE_REG_STAGES => MEM_EXT_REG_STAGES, -- number of interface register stages (0,1,2) |
-- Memory configuration: Instruction memory -- |
MEM_ISPACE_BASE => MEM_ISPACE_BASE, -- base address of instruction memory space |
MEM_ISPACE_SIZE => MEM_ISPACE_SIZE, -- total size of instruction memory space in byte |
MEM_INT_IMEM_USE => MEM_INT_IMEM_USE, -- implement processor-internal instruction memory |
MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes |
MEM_ISPACE_BASE => MEM_ISPACE_BASE, -- base address of instruction memory space |
MEM_ISPACE_SIZE => MEM_ISPACE_SIZE, -- total size of instruction memory space in byte |
MEM_INT_IMEM_USE => MEM_INT_IMEM_USE, -- implement processor-internal instruction memory |
MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes |
-- Memory configuration: Data memory -- |
MEM_DSPACE_BASE => MEM_DSPACE_BASE, -- base address of data memory space |
MEM_DSPACE_SIZE => MEM_DSPACE_SIZE, -- total size of data memory space in byte |
MEM_INT_DMEM_USE => MEM_INT_DMEM_USE, -- implement processor-internal data memory |
MEM_INT_DMEM_SIZE => MEM_INT_DMEM_SIZE -- size of processor-internal data memory in bytes |
MEM_DSPACE_BASE => MEM_DSPACE_BASE, -- base address of data memory space |
MEM_DSPACE_SIZE => MEM_DSPACE_SIZE, -- total size of data memory space in byte |
MEM_INT_DMEM_USE => MEM_INT_DMEM_USE, -- implement processor-internal data memory |
MEM_INT_DMEM_SIZE => MEM_INT_DMEM_SIZE -- size of processor-internal data memory in bytes |
) |
port map ( |
-- global control -- |
493,13 → 539,13
clk_i => clk_i, -- global clock line |
rstn_i => sys_rstn, -- global reset line, low-active |
-- host access -- |
addr_i => cpu.addr, -- address |
rden_i => cpu.re, -- read enable |
wren_i => cpu.we, -- write enable |
ben_i => cpu.ben, -- byte write enable |
data_i => cpu.wdata, -- data in |
addr_i => p_bus.addr, -- address |
rden_i => p_bus.re, -- read enable |
wren_i => p_bus.we, -- write enable |
ben_i => p_bus.ben, -- byte write enable |
data_i => p_bus.wdata, -- data in |
data_o => wishbone_rdata, -- data out |
cancel_i => cpu.cancel, -- cancel current transaction |
cancel_i => p_bus.cancel, -- cancel current transaction |
ack_o => wishbone_ack, -- transfer acknowledge |
err_o => wishbone_err, -- transfer error |
-- wishbone interface -- |
532,9 → 578,9
|
-- IO Access? ----------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
io_acc <= '1' when (cpu.addr(data_width_c-1 downto index_size_f(io_size_c)) = io_base_c(data_width_c-1 downto index_size_f(io_size_c))) else '0'; |
io_rden <= io_acc and cpu.re; |
io_wren <= io_acc and cpu.we; |
io_acc <= '1' when (p_bus.addr(data_width_c-1 downto index_size_f(io_size_c)) = io_base_c(data_width_c-1 downto index_size_f(io_size_c))) else '0'; |
io_rden <= io_acc and p_bus.re; |
io_wren <= io_acc and p_bus.we; |
|
|
-- General Purpose Input/Output Port (GPIO) ----------------------------------------------- |
544,19 → 590,19
neorv32_gpio_inst: neorv32_gpio |
port map ( |
-- host access -- |
clk_i => clk_i, -- global clock line |
addr_i => cpu.addr, -- address |
rden_i => io_rden, -- read enable |
wren_i => io_wren, -- write enable |
ben_i => cpu.ben, -- byte write enable |
data_i => cpu.wdata, -- data in |
data_o => gpio_rdata, -- data out |
ack_o => gpio_ack, -- transfer acknowledge |
clk_i => clk_i, -- global clock line |
addr_i => p_bus.addr, -- address |
rden_i => io_rden, -- read enable |
wren_i => io_wren, -- write enable |
ben_i => p_bus.ben, -- byte write enable |
data_i => p_bus.wdata, -- data in |
data_o => gpio_rdata, -- data out |
ack_o => gpio_ack, -- transfer acknowledge |
-- parallel io -- |
gpio_o => gpio_o, |
gpio_i => gpio_i, |
-- interrupt -- |
irq_o => gpio_irq -- pin-change interrupt |
irq_o => gpio_irq -- pin-change interrupt |
); |
end generate; |
|
576,19 → 622,19
neorv32_clic_inst: neorv32_clic |
port map ( |
-- host access -- |
clk_i => clk_i, -- global clock line |
rden_i => io_rden, -- read enable |
wren_i => io_wren, -- write enable |
ben_i => cpu.ben, -- byte write enable |
addr_i => cpu.addr, -- address |
data_i => cpu.wdata, -- data in |
data_o => clic_rdata, -- data out |
ack_o => clic_ack, -- transfer acknowledge |
clk_i => clk_i, -- global clock line |
rden_i => io_rden, -- read enable |
wren_i => io_wren, -- write enable |
ben_i => p_bus.ben, -- byte write enable |
addr_i => p_bus.addr, -- address |
data_i => p_bus.wdata, -- data in |
data_o => clic_rdata, -- data out |
ack_o => clic_ack, -- transfer acknowledge |
-- cpu interrupt -- |
cpu_irq_o => clic_irq, -- trigger CPU's external IRQ |
cpu_irq_o => clic_irq, -- trigger CPU's external IRQ |
-- external interrupt lines -- |
ext_irq_i => clic_xirq, -- IRQ, triggering on HIGH level |
ext_ack_o => clic_xack -- acknowledge |
ext_irq_i => clic_xirq, -- IRQ, triggering on HIGH level |
ext_ack_o => clic_xack -- acknowledge |
); |
end generate; |
|
622,21 → 668,21
neorv32_wdt_inst: neorv32_wdt |
port map ( |
-- host access -- |
clk_i => clk_i, -- global clock line |
rstn_i => ext_rstn, -- global reset line, low-active |
rden_i => io_rden, -- read enable |
wren_i => io_wren, -- write enable |
ben_i => cpu.ben, -- byte write enable |
addr_i => cpu.addr, -- address |
data_i => cpu.wdata, -- data in |
data_o => wdt_rdata, -- data out |
ack_o => wdt_ack, -- transfer acknowledge |
clk_i => clk_i, -- global clock line |
rstn_i => ext_rstn, -- global reset line, low-active |
rden_i => io_rden, -- read enable |
wren_i => io_wren, -- write enable |
ben_i => p_bus.ben, -- byte write enable |
addr_i => p_bus.addr, -- address |
data_i => p_bus.wdata, -- data in |
data_o => wdt_rdata, -- data out |
ack_o => wdt_ack, -- transfer acknowledge |
-- clock generator -- |
clkgen_en_o => wdt_cg_en, -- enable clock generator |
clkgen_en_o => wdt_cg_en, -- enable clock generator |
clkgen_i => clk_gen, |
-- timeout event -- |
irq_o => wdt_irq, -- timeout IRQ |
rstn_o => wdt_rstn -- timeout reset, low_active, use it as async! |
irq_o => wdt_irq, -- timeout IRQ |
rstn_o => wdt_rstn -- timeout reset, low_active, use it as async! |
); |
end generate; |
|
657,19 → 703,19
neorv32_mtime_inst: neorv32_mtime |
port map ( |
-- host access -- |
clk_i => clk_i, -- global clock line |
rstn_i => sys_rstn, -- global reset, low-active, async |
addr_i => cpu.addr, -- address |
rden_i => io_rden, -- read enable |
wren_i => io_wren, -- write enable |
ben_i => cpu.ben, -- byte write enable |
data_i => cpu.wdata, -- data in |
data_o => mtime_rdata, -- data out |
ack_o => mtime_ack, -- transfer acknowledge |
clk_i => clk_i, -- global clock line |
rstn_i => sys_rstn, -- global reset, low-active, async |
addr_i => p_bus.addr, -- address |
rden_i => io_rden, -- read enable |
wren_i => io_wren, -- write enable |
ben_i => p_bus.ben, -- byte write enable |
data_i => p_bus.wdata, -- data in |
data_o => mtime_rdata, -- data out |
ack_o => mtime_ack, -- transfer acknowledge |
-- time output for CPU -- |
time_o => mtime_time, -- current system time |
time_o => mtime_time, -- current system time |
-- interrupt -- |
irq_o => mtime_irq -- interrupt request |
irq_o => mtime_irq -- interrupt request |
); |
end generate; |
|
689,22 → 735,22
neorv32_uart_inst: neorv32_uart |
port map ( |
-- host access -- |
clk_i => clk_i, -- global clock line |
addr_i => cpu.addr, -- address |
rden_i => io_rden, -- read enable |
wren_i => io_wren, -- write enable |
ben_i => cpu.ben, -- byte write enable |
data_i => cpu.wdata, -- data in |
data_o => uart_rdata, -- data out |
ack_o => uart_ack, -- transfer acknowledge |
clk_i => clk_i, -- global clock line |
addr_i => p_bus.addr, -- address |
rden_i => io_rden, -- read enable |
wren_i => io_wren, -- write enable |
ben_i => p_bus.ben, -- byte write enable |
data_i => p_bus.wdata, -- data in |
data_o => uart_rdata, -- data out |
ack_o => uart_ack, -- transfer acknowledge |
-- clock generator -- |
clkgen_en_o => uart_cg_en, -- enable clock generator |
clkgen_en_o => uart_cg_en, -- enable clock generator |
clkgen_i => clk_gen, |
-- com lines -- |
uart_txd_o => uart_txd_o, |
uart_rxd_i => uart_rxd_i, |
-- interrupts -- |
uart_irq_o => uart_irq -- uart rx/tx interrupt |
uart_irq_o => uart_irq -- uart rx/tx interrupt |
); |
end generate; |
|
725,24 → 771,24
neorv32_spi_inst: neorv32_spi |
port map ( |
-- host access -- |
clk_i => clk_i, -- global clock line |
addr_i => cpu.addr, -- address |
rden_i => io_rden, -- read enable |
wren_i => io_wren, -- write enable |
ben_i => cpu.ben, -- byte write enable |
data_i => cpu.wdata, -- data in |
data_o => spi_rdata, -- data out |
ack_o => spi_ack, -- transfer acknowledge |
clk_i => clk_i, -- global clock line |
addr_i => p_bus.addr, -- address |
rden_i => io_rden, -- read enable |
wren_i => io_wren, -- write enable |
ben_i => p_bus.ben, -- byte write enable |
data_i => p_bus.wdata, -- data in |
data_o => spi_rdata, -- data out |
ack_o => spi_ack, -- transfer acknowledge |
-- clock generator -- |
clkgen_en_o => spi_cg_en, -- enable clock generator |
clkgen_en_o => spi_cg_en, -- enable clock generator |
clkgen_i => clk_gen, |
-- com lines -- |
spi_sck_o => spi_sck_o, -- SPI serial clock |
spi_sdo_o => spi_sdo_o, -- controller data out, peripheral data in |
spi_sdi_i => spi_sdi_i, -- controller data in, peripheral data out |
spi_csn_o => spi_csn_o, -- SPI CS |
spi_sck_o => spi_sck_o, -- SPI serial clock |
spi_sdo_o => spi_sdo_o, -- controller data out, peripheral data in |
spi_sdi_i => spi_sdi_i, -- controller data in, peripheral data out |
spi_csn_o => spi_csn_o, -- SPI CS |
-- interrupt -- |
spi_irq_o => spi_irq -- transmission done interrupt |
spi_irq_o => spi_irq -- transmission done interrupt |
); |
end generate; |
|
765,22 → 811,22
neorv32_twi_inst: neorv32_twi |
port map ( |
-- host access -- |
clk_i => clk_i, -- global clock line |
addr_i => cpu.addr, -- address |
rden_i => io_rden, -- read enable |
wren_i => io_wren, -- write enable |
ben_i => cpu.ben, -- byte write enable |
data_i => cpu.wdata, -- data in |
data_o => twi_rdata, -- data out |
ack_o => twi_ack, -- transfer acknowledge |
clk_i => clk_i, -- global clock line |
addr_i => p_bus.addr, -- address |
rden_i => io_rden, -- read enable |
wren_i => io_wren, -- write enable |
ben_i => p_bus.ben, -- byte write enable |
data_i => p_bus.wdata, -- data in |
data_o => twi_rdata, -- data out |
ack_o => twi_ack, -- transfer acknowledge |
-- clock generator -- |
clkgen_en_o => twi_cg_en, -- enable clock generator |
clkgen_en_o => twi_cg_en, -- enable clock generator |
clkgen_i => clk_gen, |
-- com lines -- |
twi_sda_io => twi_sda_io, -- serial data line |
twi_scl_io => twi_scl_io, -- serial clock line |
twi_sda_io => twi_sda_io, -- serial data line |
twi_scl_io => twi_scl_io, -- serial clock line |
-- interrupt -- |
twi_irq_o => twi_irq -- transfer done IRQ |
twi_irq_o => twi_irq -- transfer done IRQ |
); |
end generate; |
|
802,16 → 848,16
neorv32_pwm_inst: neorv32_pwm |
port map ( |
-- host access -- |
clk_i => clk_i, -- global clock line |
addr_i => cpu.addr, -- address |
rden_i => io_rden, -- read enable |
wren_i => io_wren, -- write enable |
ben_i => cpu.ben, -- byte write enable |
data_i => cpu.wdata, -- data in |
data_o => pwm_rdata, -- data out |
ack_o => pwm_ack, -- transfer acknowledge |
clk_i => clk_i, -- global clock line |
addr_i => p_bus.addr, -- address |
rden_i => io_rden, -- read enable |
wren_i => io_wren, -- write enable |
ben_i => p_bus.ben, -- byte write enable |
data_i => p_bus.wdata, -- data in |
data_o => pwm_rdata, -- data out |
ack_o => pwm_ack, -- transfer acknowledge |
-- clock generator -- |
clkgen_en_o => pwm_cg_en, -- enable clock generator |
clkgen_en_o => pwm_cg_en, -- enable clock generator |
clkgen_i => clk_gen, |
-- pwm output channels -- |
pwm_o => pwm_o |
834,14 → 880,14
neorv32_trng_inst: neorv32_trng |
port map ( |
-- host access -- |
clk_i => clk_i, -- global clock line |
addr_i => cpu.addr, -- address |
rden_i => io_rden, -- read enable |
wren_i => io_wren, -- write enable |
ben_i => cpu.ben, -- byte write enable |
data_i => cpu.wdata, -- data in |
data_o => trng_rdata, -- data out |
ack_o => trng_ack -- transfer acknowledge |
clk_i => clk_i, -- global clock line |
addr_i => p_bus.addr, -- address |
rden_i => io_rden, -- read enable |
wren_i => io_wren, -- write enable |
ben_i => p_bus.ben, -- byte write enable |
data_i => p_bus.wdata, -- data in |
data_o => trng_rdata, -- data out |
ack_o => trng_ack -- transfer acknowledge |
); |
end generate; |
|
860,16 → 906,16
port map ( |
-- host access -- |
clk_i => clk_i, -- global clock line |
addr_i => cpu.addr, -- address |
addr_i => p_bus.addr, -- address |
rden_i => io_rden, -- read enable |
wren_i => io_wren, -- write enable |
ben_i => cpu.ben, -- byte write enable |
data_i => cpu.wdata, -- data in |
ben_i => p_bus.ben, -- byte write enable |
data_i => p_bus.wdata, -- data in |
data_o => devnull_rdata, -- data out |
ack_o => devnull_ack -- transfer acknowledge |
); |
end generate; |
|
|
neorv32_devnull_inst_false: |
if (IO_DEVNULL_USE = false) generate |
devnull_rdata <= (others => '0'); |
877,4 → 923,47
end generate; |
|
|
-- System Configuration Information Memory (SYSINFO) -------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
neorv32_sysinfo_inst: neorv32_sysinfo |
generic map ( |
-- General -- |
CLOCK_FREQUENCY => CLOCK_FREQUENCY, -- clock frequency of clk_i in Hz |
BOOTLOADER_USE => BOOTLOADER_USE, -- implement processor-internal bootloader? |
USER_CODE => USER_CODE, -- custom user code |
-- Memory configuration: Instruction memory -- |
MEM_ISPACE_BASE => MEM_ISPACE_BASE, -- base address of instruction memory space |
MEM_ISPACE_SIZE => MEM_ISPACE_SIZE, -- total size of instruction memory space in byte |
MEM_INT_IMEM_USE => MEM_INT_IMEM_USE, -- implement processor-internal instruction memory |
MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes |
MEM_INT_IMEM_ROM => MEM_INT_IMEM_ROM, -- implement processor-internal instruction memory as ROM |
-- Memory configuration: Data memory -- |
MEM_DSPACE_BASE => MEM_DSPACE_BASE, -- base address of data memory space |
MEM_DSPACE_SIZE => MEM_DSPACE_SIZE, -- total size of data memory space in byte |
MEM_INT_DMEM_USE => MEM_INT_DMEM_USE, -- implement processor-internal data memory |
MEM_INT_DMEM_SIZE => MEM_INT_DMEM_SIZE, -- size of processor-internal data memory in bytes |
-- Memory configuration: External memory interface -- |
MEM_EXT_USE => MEM_EXT_USE, -- implement external memory bus interface? |
-- Processor peripherals -- |
IO_GPIO_USE => IO_GPIO_USE, -- implement general purpose input/output port unit (GPIO)? |
IO_MTIME_USE => IO_MTIME_USE, -- implement machine system timer (MTIME)? |
IO_UART_USE => IO_UART_USE, -- implement universal asynchronous receiver/transmitter (UART)? |
IO_SPI_USE => IO_SPI_USE, -- implement serial peripheral interface (SPI)? |
IO_TWI_USE => IO_TWI_USE, -- implement two-wire interface (TWI)? |
IO_PWM_USE => IO_PWM_USE, -- implement pulse-width modulation unit (PWM)? |
IO_WDT_USE => IO_WDT_USE, -- implement watch dog timer (WDT)? |
IO_CLIC_USE => IO_CLIC_USE, -- implement core local interrupt controller (CLIC)? |
IO_TRNG_USE => IO_TRNG_USE, -- implement true random number generator (TRNG)? |
IO_DEVNULL_USE => IO_DEVNULL_USE -- implement dummy device (DEVNULL)? |
) |
port map ( |
-- host access -- |
clk_i => clk_i, -- global clock line |
addr_i => p_bus.addr, -- address |
rden_i => io_rden, -- read enable |
data_o => sysinfo_rdata, -- data out |
ack_o => sysinfo_ack -- transfer acknowledge |
); |
|
|
end neorv32_top_rtl; |
/neorv32/trunk/rtl/top_templates/neorv32_test_setup.vhd
70,9 → 70,9
generic map ( |
-- General -- |
CLOCK_FREQUENCY => 100000000, -- clock frequency of clk_i in Hz |
HART_ID => x"00000000", -- hardware thread ID |
BOOTLOADER_USE => true, -- implement processor-internal bootloader? |
CSR_COUNTERS_USE => true, -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])? |
USER_CODE => x"00000000", -- custom user code |
-- RISC-V CPU Extensions -- |
CPU_EXTENSION_RISCV_C => false, -- implement compressed extension? |
CPU_EXTENSION_RISCV_E => false, -- implement embedded RF extension? |
120,6 → 120,9
wb_cyc_o => open, -- valid cycle |
wb_ack_i => '0', -- transfer acknowledge |
wb_err_i => '0', -- transfer error |
-- Advanced memory control signals -- |
fence_o => open, -- indicates an executed FENCE operation |
fencei_o => open, -- indicates an executed FENCEI operation |
-- GPIO -- |
gpio_o => gpio_out, -- parallel output |
gpio_i => (others => '0'), -- parallel input |
/neorv32/trunk/sim/ghdl/ghdl_sim.sh
36,6 → 36,7
ghdl -a --work=neorv32 $srcdir_core/neorv32_bootloader_image.vhd |
# |
ghdl -a --work=neorv32 $srcdir_core/neorv32_boot_rom.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_busswitch.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_clic.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_cpu.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_cpu_alu.vhd |
51,6 → 52,7
ghdl -a --work=neorv32 $srcdir_core/neorv32_mtime.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_pwm.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_spi.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_sysinfo.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_top.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_trng.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_twi.vhd |
/neorv32/trunk/sim/vivado/neorv32_tb_behav.wcfg
12,15 → 12,15
</db_ref> |
</db_ref_list> |
<zoom_setting> |
<ZoomStartTime time="84997884fs"></ZoomStartTime> |
<ZoomEndTime time="85016285fs"></ZoomEndTime> |
<Cursor1Time time="85050184fs"></Cursor1Time> |
<ZoomStartTime time="11030000fs"></ZoomStartTime> |
<ZoomEndTime time="11540001fs"></ZoomEndTime> |
<Cursor1Time time="11115000fs"></Cursor1Time> |
</zoom_setting> |
<column_width_setting> |
<NameColumnWidth column_width="178"></NameColumnWidth> |
<ValueColumnWidth column_width="115"></ValueColumnWidth> |
<ValueColumnWidth column_width="124"></ValueColumnWidth> |
</column_width_setting> |
<WVObjectSize size="157" /> |
<WVObjectSize size="144" /> |
<wvobject type="divider" fp_name="divider273"> |
<obj_property name="label">CPU: Control.FETCH</obj_property> |
<obj_property name="DisplayName">label</obj_property> |
33,10 → 33,6
<obj_property name="ElementShortName">rstn_i</obj_property> |
<obj_property name="ObjectShortName">rstn_i</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/bus_wait_i" type="logic"> |
<obj_property name="ElementShortName">bus_wait_i</obj_property> |
<obj_property name="ObjectShortName">bus_wait_i</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/bus_fast_ir" type="logic"> |
<obj_property name="ElementShortName">bus_fast_ir</obj_property> |
<obj_property name="ObjectShortName">bus_fast_ir</obj_property> |
65,6 → 61,156
<obj_property name="ElementShortName">fetch_engine</obj_property> |
<obj_property name="ObjectShortName">fetch_engine</obj_property> |
<obj_property name="isExpanded"></obj_property> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.state" type="other"> |
<obj_property name="ElementShortName">.state</obj_property> |
<obj_property name="ObjectShortName">.state</obj_property> |
<obj_property name="CustomSignalColor">#FFD700</obj_property> |
<obj_property name="UseCustomSignalColor">true</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.state_nxt" type="other"> |
<obj_property name="ElementShortName">.state_nxt</obj_property> |
<obj_property name="ObjectShortName">.state_nxt</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.i_buf" type="array"> |
<obj_property name="ElementShortName">.i_buf[33:0]</obj_property> |
<obj_property name="ObjectShortName">.i_buf[33:0]</obj_property> |
<obj_property name="CustomSignalColor">#FF00FF</obj_property> |
<obj_property name="UseCustomSignalColor">true</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.i_buf_nxt" type="array"> |
<obj_property name="ElementShortName">.i_buf_nxt[33:0]</obj_property> |
<obj_property name="ObjectShortName">.i_buf_nxt[33:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.i_buf2" type="array"> |
<obj_property name="ElementShortName">.i_buf2[33:0]</obj_property> |
<obj_property name="ObjectShortName">.i_buf2[33:0]</obj_property> |
<obj_property name="CustomSignalColor">#FF00FF</obj_property> |
<obj_property name="UseCustomSignalColor">true</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.i_buf2_nxt" type="array"> |
<obj_property name="ElementShortName">.i_buf2_nxt[33:0]</obj_property> |
<obj_property name="ObjectShortName">.i_buf2_nxt[33:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.ci_reg" type="array"> |
<obj_property name="ElementShortName">.ci_reg[17:0]</obj_property> |
<obj_property name="ObjectShortName">.ci_reg[17:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.ci_reg_nxt" type="array"> |
<obj_property name="ElementShortName">.ci_reg_nxt[17:0]</obj_property> |
<obj_property name="ObjectShortName">.ci_reg_nxt[17:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.i_buf_state" type="array"> |
<obj_property name="ElementShortName">.i_buf_state[1:0]</obj_property> |
<obj_property name="ObjectShortName">.i_buf_state[1:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.i_buf_state_nxt" type="array"> |
<obj_property name="ElementShortName">.i_buf_state_nxt[1:0]</obj_property> |
<obj_property name="ObjectShortName">.i_buf_state_nxt[1:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.pc_real" type="array"> |
<obj_property name="ElementShortName">.pc_real[31:0]</obj_property> |
<obj_property name="ObjectShortName">.pc_real[31:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.pc_real_add" type="array"> |
<obj_property name="ElementShortName">.pc_real_add[31:0]</obj_property> |
<obj_property name="ObjectShortName">.pc_real_add[31:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.pc_fetch" type="array"> |
<obj_property name="ElementShortName">.pc_fetch[31:0]</obj_property> |
<obj_property name="ObjectShortName">.pc_fetch[31:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.pc_fetch_add" type="array"> |
<obj_property name="ElementShortName">.pc_fetch_add[31:0]</obj_property> |
<obj_property name="ObjectShortName">.pc_fetch_add[31:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.ci_return" type="logic"> |
<obj_property name="ElementShortName">.ci_return</obj_property> |
<obj_property name="ObjectShortName">.ci_return</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.ci_return_nxt" type="logic"> |
<obj_property name="ElementShortName">.ci_return_nxt</obj_property> |
<obj_property name="ObjectShortName">.ci_return_nxt</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.reset" type="logic"> |
<obj_property name="ElementShortName">.reset</obj_property> |
<obj_property name="ObjectShortName">.reset</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.bus_err_ack" type="logic"> |
<obj_property name="ElementShortName">.bus_err_ack</obj_property> |
<obj_property name="ObjectShortName">.bus_err_ack</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.state" type="other"> |
<obj_property name="ElementShortName">.state</obj_property> |
<obj_property name="ObjectShortName">.state</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.state_nxt" type="other"> |
<obj_property name="ElementShortName">.state_nxt</obj_property> |
<obj_property name="ObjectShortName">.state_nxt</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.i_buf" type="array"> |
<obj_property name="ElementShortName">.i_buf[33:0]</obj_property> |
<obj_property name="ObjectShortName">.i_buf[33:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.i_buf_nxt" type="array"> |
<obj_property name="ElementShortName">.i_buf_nxt[33:0]</obj_property> |
<obj_property name="ObjectShortName">.i_buf_nxt[33:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.i_buf2" type="array"> |
<obj_property name="ElementShortName">.i_buf2[33:0]</obj_property> |
<obj_property name="ObjectShortName">.i_buf2[33:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.i_buf2_nxt" type="array"> |
<obj_property name="ElementShortName">.i_buf2_nxt[33:0]</obj_property> |
<obj_property name="ObjectShortName">.i_buf2_nxt[33:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.ci_reg" type="array"> |
<obj_property name="ElementShortName">.ci_reg[17:0]</obj_property> |
<obj_property name="ObjectShortName">.ci_reg[17:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.ci_reg_nxt" type="array"> |
<obj_property name="ElementShortName">.ci_reg_nxt[17:0]</obj_property> |
<obj_property name="ObjectShortName">.ci_reg_nxt[17:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.i_buf_state" type="array"> |
<obj_property name="ElementShortName">.i_buf_state[1:0]</obj_property> |
<obj_property name="ObjectShortName">.i_buf_state[1:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.i_buf_state_nxt" type="array"> |
<obj_property name="ElementShortName">.i_buf_state_nxt[1:0]</obj_property> |
<obj_property name="ObjectShortName">.i_buf_state_nxt[1:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.pc_real" type="array"> |
<obj_property name="ElementShortName">.pc_real[31:0]</obj_property> |
<obj_property name="ObjectShortName">.pc_real[31:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.pc_real_add" type="array"> |
<obj_property name="ElementShortName">.pc_real_add[31:0]</obj_property> |
<obj_property name="ObjectShortName">.pc_real_add[31:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.pc_fetch" type="array"> |
<obj_property name="ElementShortName">.pc_fetch[31:0]</obj_property> |
<obj_property name="ObjectShortName">.pc_fetch[31:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.pc_fetch_add" type="array"> |
<obj_property name="ElementShortName">.pc_fetch_add[31:0]</obj_property> |
<obj_property name="ObjectShortName">.pc_fetch_add[31:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.ci_return" type="logic"> |
<obj_property name="ElementShortName">.ci_return</obj_property> |
<obj_property name="ObjectShortName">.ci_return</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.ci_return_nxt" type="logic"> |
<obj_property name="ElementShortName">.ci_return_nxt</obj_property> |
<obj_property name="ObjectShortName">.ci_return_nxt</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.reset" type="logic"> |
<obj_property name="ElementShortName">.reset</obj_property> |
<obj_property name="ObjectShortName">.reset</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.bus_err_ack" type="logic"> |
<obj_property name="ElementShortName">.bus_err_ack</obj_property> |
<obj_property name="ObjectShortName">.bus_err_ack</obj_property> |
</wvobject> |
</wvobject> |
<wvobject type="divider" fp_name="divider273"> |
<obj_property name="label">CPU: Control.IPB</obj_property> |
83,10 → 229,6
<obj_property name="ElementShortName">alu_wait_i</obj_property> |
<obj_property name="ObjectShortName">alu_wait_i</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/bus_wait_i" type="logic"> |
<obj_property name="ElementShortName">bus_wait_i</obj_property> |
<obj_property name="ObjectShortName">bus_wait_i</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/instr_i" type="array"> |
<obj_property name="ElementShortName">instr_i[31:0]</obj_property> |
<obj_property name="ObjectShortName">instr_i[31:0]</obj_property> |
140,12 → 282,12
<obj_property name="ObjectShortName">be_store_i</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/ctrl" type="array"> |
<obj_property name="ElementShortName">ctrl[47:0]</obj_property> |
<obj_property name="ObjectShortName">ctrl[47:0]</obj_property> |
<obj_property name="ElementShortName">ctrl[49:0]</obj_property> |
<obj_property name="ObjectShortName">ctrl[49:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/ctrl_o" type="array"> |
<obj_property name="ElementShortName">ctrl_o[47:0]</obj_property> |
<obj_property name="ObjectShortName">ctrl_o[47:0]</obj_property> |
<obj_property name="ElementShortName">ctrl_o[49:0]</obj_property> |
<obj_property name="ObjectShortName">ctrl_o[49:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/ci_instr32" type="array"> |
<obj_property name="ElementShortName">ci_instr32[31:0]</obj_property> |
183,6 → 325,68
<obj_property name="ElementShortName">execute_engine</obj_property> |
<obj_property name="ObjectShortName">execute_engine</obj_property> |
<obj_property name="isExpanded"></obj_property> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.state" type="other"> |
<obj_property name="ElementShortName">.state</obj_property> |
<obj_property name="ObjectShortName">.state</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.state_nxt" type="other"> |
<obj_property name="ElementShortName">.state_nxt</obj_property> |
<obj_property name="ObjectShortName">.state_nxt</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.i_reg" type="array"> |
<obj_property name="ElementShortName">.i_reg[31:0]</obj_property> |
<obj_property name="ObjectShortName">.i_reg[31:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.i_reg_nxt" type="array"> |
<obj_property name="ElementShortName">.i_reg_nxt[31:0]</obj_property> |
<obj_property name="ObjectShortName">.i_reg_nxt[31:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.is_ci" type="logic"> |
<obj_property name="ElementShortName">.is_ci</obj_property> |
<obj_property name="ObjectShortName">.is_ci</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.is_ci_nxt" type="logic"> |
<obj_property name="ElementShortName">.is_ci_nxt</obj_property> |
<obj_property name="ObjectShortName">.is_ci_nxt</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.is_jump" type="logic"> |
<obj_property name="ElementShortName">.is_jump</obj_property> |
<obj_property name="ObjectShortName">.is_jump</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.is_jump_nxt" type="logic"> |
<obj_property name="ElementShortName">.is_jump_nxt</obj_property> |
<obj_property name="ObjectShortName">.is_jump_nxt</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.branch_taken" type="logic"> |
<obj_property name="ElementShortName">.branch_taken</obj_property> |
<obj_property name="ObjectShortName">.branch_taken</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.pc" type="array"> |
<obj_property name="ElementShortName">.pc[31:0]</obj_property> |
<obj_property name="ObjectShortName">.pc[31:0]</obj_property> |
<obj_property name="CustomSignalColor">#FFFFFF</obj_property> |
<obj_property name="UseCustomSignalColor">true</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.pc_nxt" type="array"> |
<obj_property name="ElementShortName">.pc_nxt[31:0]</obj_property> |
<obj_property name="ObjectShortName">.pc_nxt[31:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.next_pc" type="array"> |
<obj_property name="ElementShortName">.next_pc[31:0]</obj_property> |
<obj_property name="ObjectShortName">.next_pc[31:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.last_pc" type="array"> |
<obj_property name="ElementShortName">.last_pc[31:0]</obj_property> |
<obj_property name="ObjectShortName">.last_pc[31:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.sleep" type="logic"> |
<obj_property name="ElementShortName">.sleep</obj_property> |
<obj_property name="ObjectShortName">.sleep</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.sleep_nxt" type="logic"> |
<obj_property name="ElementShortName">.sleep_nxt</obj_property> |
<obj_property name="ObjectShortName">.sleep_nxt</obj_property> |
</wvobject> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/CPU_EXTENSION_RISCV_C" type="other"> |
<obj_property name="ElementShortName">CPU_EXTENSION_RISCV_C</obj_property> |
243,8 → 447,8
<obj_property name="ObjectShortName">rstn_i</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_alu_inst/ctrl_i" type="array"> |
<obj_property name="ElementShortName">ctrl_i[47:0]</obj_property> |
<obj_property name="ObjectShortName">ctrl_i[47:0]</obj_property> |
<obj_property name="ElementShortName">ctrl_i[49:0]</obj_property> |
<obj_property name="ObjectShortName">ctrl_i[49:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_alu_inst/rs1_i" type="array"> |
<obj_property name="ElementShortName">rs1_i[31:0]</obj_property> |
342,30 → 546,6
<obj_property name="ElementShortName">cmp_less</obj_property> |
<obj_property name="ObjectShortName">cmp_less</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_alu_inst/shift_cmd" type="logic"> |
<obj_property name="ElementShortName">shift_cmd</obj_property> |
<obj_property name="ObjectShortName">shift_cmd</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_alu_inst/shift_cmd_ff" type="logic"> |
<obj_property name="ElementShortName">shift_cmd_ff</obj_property> |
<obj_property name="ObjectShortName">shift_cmd_ff</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_alu_inst/shift_start" type="logic"> |
<obj_property name="ElementShortName">shift_start</obj_property> |
<obj_property name="ObjectShortName">shift_start</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_alu_inst/shift_run" type="logic"> |
<obj_property name="ElementShortName">shift_run</obj_property> |
<obj_property name="ObjectShortName">shift_run</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_alu_inst/shift_cnt" type="array"> |
<obj_property name="ElementShortName">shift_cnt[4:0]</obj_property> |
<obj_property name="ObjectShortName">shift_cnt[4:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_alu_inst/shift_sreg" type="array"> |
<obj_property name="ElementShortName">shift_sreg[31:0]</obj_property> |
<obj_property name="ObjectShortName">shift_sreg[31:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_alu_inst/cp_cmd_ff" type="logic"> |
<obj_property name="ElementShortName">cp_cmd_ff</obj_property> |
<obj_property name="ObjectShortName">cp_cmd_ff</obj_property> |
390,6 → 570,10
<obj_property name="ElementShortName">cp_rb_ff1</obj_property> |
<obj_property name="ObjectShortName">cp_rb_ff1</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_alu_inst/shifter" type="array"> |
<obj_property name="ElementShortName">shifter</obj_property> |
<obj_property name="ObjectShortName">shifter</obj_property> |
</wvobject> |
<wvobject type="divider" fp_name="divider367"> |
<obj_property name="label">CPU: BUS_UNIT</obj_property> |
<obj_property name="DisplayName">label</obj_property> |
402,38 → 586,34
<obj_property name="ElementShortName">clk_i</obj_property> |
<obj_property name="ObjectShortName">clk_i</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_bus_inst/ctrl_i" type="array"> |
<obj_property name="ElementShortName">ctrl_i[47:0]</obj_property> |
<obj_property name="ObjectShortName">ctrl_i[47:0]</obj_property> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_bus_inst/mar" type="array"> |
<obj_property name="ElementShortName">mar[31:0]</obj_property> |
<obj_property name="ObjectShortName">mar[31:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_bus_inst/wdata_i" type="array"> |
<obj_property name="ElementShortName">wdata_i[31:0]</obj_property> |
<obj_property name="ObjectShortName">wdata_i[31:0]</obj_property> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_bus_inst/mdo" type="array"> |
<obj_property name="ElementShortName">mdo[31:0]</obj_property> |
<obj_property name="ObjectShortName">mdo[31:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_bus_inst/pc_i" type="array"> |
<obj_property name="ElementShortName">pc_i[31:0]</obj_property> |
<obj_property name="ObjectShortName">pc_i[31:0]</obj_property> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_bus_inst/mdi" type="array"> |
<obj_property name="ElementShortName">mdi[31:0]</obj_property> |
<obj_property name="ObjectShortName">mdi[31:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_bus_inst/alu_i" type="array"> |
<obj_property name="ElementShortName">alu_i[31:0]</obj_property> |
<obj_property name="ObjectShortName">alu_i[31:0]</obj_property> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_bus_inst/i_wait_o" type="logic"> |
<obj_property name="ElementShortName">i_wait_o</obj_property> |
<obj_property name="ObjectShortName">i_wait_o</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_bus_inst/instr_o" type="array"> |
<obj_property name="ElementShortName">instr_o[31:0]</obj_property> |
<obj_property name="ObjectShortName">instr_o[31:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_bus_inst/rdata_o" type="array"> |
<obj_property name="ElementShortName">rdata_o[31:0]</obj_property> |
<obj_property name="ObjectShortName">rdata_o[31:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_bus_inst/mar_o" type="array"> |
<obj_property name="ElementShortName">mar_o[31:0]</obj_property> |
<obj_property name="ObjectShortName">mar_o[31:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_bus_inst/ma_instr_o" type="logic"> |
<obj_property name="ElementShortName">ma_instr_o</obj_property> |
<obj_property name="ObjectShortName">ma_instr_o</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_bus_inst/be_instr_o" type="logic"> |
<obj_property name="ElementShortName">be_instr_o</obj_property> |
<obj_property name="ObjectShortName">be_instr_o</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_bus_inst/d_wait_o" type="logic"> |
<obj_property name="ElementShortName">d_wait_o</obj_property> |
<obj_property name="ObjectShortName">d_wait_o</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_bus_inst/ma_load_o" type="logic"> |
<obj_property name="ElementShortName">ma_load_o</obj_property> |
<obj_property name="ObjectShortName">ma_load_o</obj_property> |
442,10 → 622,6
<obj_property name="ElementShortName">ma_store_o</obj_property> |
<obj_property name="ObjectShortName">ma_store_o</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_bus_inst/be_instr_o" type="logic"> |
<obj_property name="ElementShortName">be_instr_o</obj_property> |
<obj_property name="ObjectShortName">be_instr_o</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_bus_inst/be_load_o" type="logic"> |
<obj_property name="ElementShortName">be_load_o</obj_property> |
<obj_property name="ObjectShortName">be_load_o</obj_property> |
454,94 → 630,42
<obj_property name="ElementShortName">be_store_o</obj_property> |
<obj_property name="ObjectShortName">be_store_o</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_bus_inst/bus_wait_o" type="logic"> |
<obj_property name="ElementShortName">bus_wait_o</obj_property> |
<obj_property name="ObjectShortName">bus_wait_o</obj_property> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_bus_inst/MEM_EXT_TIMEOUT" type="other"> |
<obj_property name="ElementShortName">MEM_EXT_TIMEOUT</obj_property> |
<obj_property name="ObjectShortName">MEM_EXT_TIMEOUT</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_bus_inst/bus_addr_o" type="array"> |
<obj_property name="ElementShortName">bus_addr_o[31:0]</obj_property> |
<obj_property name="ObjectShortName">bus_addr_o[31:0]</obj_property> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_bus_inst/i_arbiter" type="array"> |
<obj_property name="ElementShortName">i_arbiter</obj_property> |
<obj_property name="ObjectShortName">i_arbiter</obj_property> |
<obj_property name="isExpanded"></obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_bus_inst/bus_rdata_i" type="array"> |
<obj_property name="ElementShortName">bus_rdata_i[31:0]</obj_property> |
<obj_property name="ObjectShortName">bus_rdata_i[31:0]</obj_property> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_bus_inst/d_arbiter" type="array"> |
<obj_property name="ElementShortName">d_arbiter</obj_property> |
<obj_property name="ObjectShortName">d_arbiter</obj_property> |
<obj_property name="isExpanded"></obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_bus_inst/bus_wdata_o" type="array"> |
<obj_property name="ElementShortName">bus_wdata_o[31:0]</obj_property> |
<obj_property name="ObjectShortName">bus_wdata_o[31:0]</obj_property> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/cpu_i" type="array"> |
<obj_property name="ElementShortName">cpu_i</obj_property> |
<obj_property name="ObjectShortName">cpu_i</obj_property> |
<obj_property name="isExpanded"></obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_bus_inst/bus_ben_o" type="array"> |
<obj_property name="ElementShortName">bus_ben_o[3:0]</obj_property> |
<obj_property name="ObjectShortName">bus_ben_o[3:0]</obj_property> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/cpu_d" type="array"> |
<obj_property name="ElementShortName">cpu_d</obj_property> |
<obj_property name="ObjectShortName">cpu_d</obj_property> |
<obj_property name="isExpanded"></obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_bus_inst/bus_we_o" type="logic"> |
<obj_property name="ElementShortName">bus_we_o</obj_property> |
<obj_property name="ObjectShortName">bus_we_o</obj_property> |
<wvobject type="divider" fp_name="divider298"> |
<obj_property name="label">BUS_CROSSBAR</obj_property> |
<obj_property name="DisplayName">label</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_bus_inst/bus_re_o" type="logic"> |
<obj_property name="ElementShortName">bus_re_o</obj_property> |
<obj_property name="ObjectShortName">bus_re_o</obj_property> |
<wvobject type="divider" fp_name="divider298"> |
<obj_property name="label">BUS_SWITCH I</obj_property> |
<obj_property name="DisplayName">label</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_bus_inst/bus_ack_i" type="logic"> |
<obj_property name="ElementShortName">bus_ack_i</obj_property> |
<obj_property name="ObjectShortName">bus_ack_i</obj_property> |
<wvobject type="divider" fp_name="divider298"> |
<obj_property name="label">BUS_SWITCH D</obj_property> |
<obj_property name="DisplayName">label</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_bus_inst/bus_err_i" type="logic"> |
<obj_property name="ElementShortName">bus_err_i</obj_property> |
<obj_property name="ObjectShortName">bus_err_i</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_bus_inst/mar" type="array"> |
<obj_property name="ElementShortName">mar[31:0]</obj_property> |
<obj_property name="ObjectShortName">mar[31:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_bus_inst/mdo" type="array"> |
<obj_property name="ElementShortName">mdo[31:0]</obj_property> |
<obj_property name="ObjectShortName">mdo[31:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_bus_inst/mdi" type="array"> |
<obj_property name="ElementShortName">mdi[31:0]</obj_property> |
<obj_property name="ObjectShortName">mdi[31:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_bus_inst/bus_busy" type="logic"> |
<obj_property name="ElementShortName">bus_busy</obj_property> |
<obj_property name="ObjectShortName">bus_busy</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_bus_inst/bus_if_req" type="logic"> |
<obj_property name="ElementShortName">bus_if_req</obj_property> |
<obj_property name="ObjectShortName">bus_if_req</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_bus_inst/bus_rd_req" type="logic"> |
<obj_property name="ElementShortName">bus_rd_req</obj_property> |
<obj_property name="ObjectShortName">bus_rd_req</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_bus_inst/bus_wr_req" type="logic"> |
<obj_property name="ElementShortName">bus_wr_req</obj_property> |
<obj_property name="ObjectShortName">bus_wr_req</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_bus_inst/access_err" type="logic"> |
<obj_property name="ElementShortName">access_err</obj_property> |
<obj_property name="ObjectShortName">access_err</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_bus_inst/align_err" type="logic"> |
<obj_property name="ElementShortName">align_err</obj_property> |
<obj_property name="ObjectShortName">align_err</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_bus_inst/bus_timeout" type="array"> |
<obj_property name="ElementShortName">bus_timeout[3:0]</obj_property> |
<obj_property name="ObjectShortName">bus_timeout[3:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_bus_inst/misaligned_data" type="logic"> |
<obj_property name="ElementShortName">misaligned_data</obj_property> |
<obj_property name="ObjectShortName">misaligned_data</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_bus_inst/misaligned_instr" type="logic"> |
<obj_property name="ElementShortName">misaligned_instr</obj_property> |
<obj_property name="ObjectShortName">misaligned_instr</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_bus_inst/MEM_EXT_TIMEOUT" type="other"> |
<obj_property name="ElementShortName">MEM_EXT_TIMEOUT</obj_property> |
<obj_property name="ObjectShortName">MEM_EXT_TIMEOUT</obj_property> |
</wvobject> |
<wvobject type="divider" fp_name="divider298"> |
<obj_property name="label">CPU: MULDIC CP</obj_property> |
<obj_property name="DisplayName">label</obj_property> |
555,8 → 679,8
<obj_property name="ObjectShortName">rstn_i</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_cp_muldiv_inst_true/neorv32_cpu_cp_muldiv_inst/ctrl_i" type="array"> |
<obj_property name="ElementShortName">ctrl_i[47:0]</obj_property> |
<obj_property name="ObjectShortName">ctrl_i[47:0]</obj_property> |
<obj_property name="ElementShortName">ctrl_i[49:0]</obj_property> |
<obj_property name="ObjectShortName">ctrl_i[49:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_cp_muldiv_inst_true/neorv32_cpu_cp_muldiv_inst/rs1_i" type="array"> |
<obj_property name="ElementShortName">rs1_i[31:0]</obj_property> |
655,4 → 779,44
<obj_property name="ElementShortName">mul_p_sext</obj_property> |
<obj_property name="ObjectShortName">mul_p_sext</obj_property> |
</wvobject> |
<wvobject type="divider" fp_name="divider238"> |
<obj_property name="label">IO: MTIME</obj_property> |
<obj_property name="DisplayName">label</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_mtime_inst_true/neorv32_mtime_inst/irq_o" type="logic"> |
<obj_property name="ElementShortName">irq_o</obj_property> |
<obj_property name="ObjectShortName">irq_o</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_mtime_inst_true/neorv32_mtime_inst/wren" type="logic"> |
<obj_property name="ElementShortName">wren</obj_property> |
<obj_property name="ObjectShortName">wren</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_mtime_inst_true/neorv32_mtime_inst/mtime_lo" type="array"> |
<obj_property name="ElementShortName">mtime_lo[32:0]</obj_property> |
<obj_property name="ObjectShortName">mtime_lo[32:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_mtime_inst_true/neorv32_mtime_inst/mtime_lo_msb_ff" type="logic"> |
<obj_property name="ElementShortName">mtime_lo_msb_ff</obj_property> |
<obj_property name="ObjectShortName">mtime_lo_msb_ff</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_mtime_inst_true/neorv32_mtime_inst/mtime_hi" type="array"> |
<obj_property name="ElementShortName">mtime_hi[31:0]</obj_property> |
<obj_property name="ObjectShortName">mtime_hi[31:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_mtime_inst_true/neorv32_mtime_inst/cmp_lo" type="logic"> |
<obj_property name="ElementShortName">cmp_lo</obj_property> |
<obj_property name="ObjectShortName">cmp_lo</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_mtime_inst_true/neorv32_mtime_inst/cmp_lo_ff" type="logic"> |
<obj_property name="ElementShortName">cmp_lo_ff</obj_property> |
<obj_property name="ObjectShortName">cmp_lo_ff</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_mtime_inst_true/neorv32_mtime_inst/cmp_hi" type="logic"> |
<obj_property name="ElementShortName">cmp_hi</obj_property> |
<obj_property name="ObjectShortName">cmp_hi</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_mtime_inst_true/neorv32_mtime_inst/cmp_match_ff" type="logic"> |
<obj_property name="ElementShortName">cmp_match_ff</obj_property> |
<obj_property name="ObjectShortName">cmp_match_ff</obj_property> |
</wvobject> |
</wave_config> |
/neorv32/trunk/sim/neorv32_tb.vhd
127,9 → 127,9
generic map ( |
-- General -- |
CLOCK_FREQUENCY => f_clock_nat_c, -- clock frequency of clk_i in Hz |
HART_ID => x"00000000", -- custom hardware thread ID |
BOOTLOADER_USE => false, -- implement processor-internal bootloader? |
CSR_COUNTERS_USE => true, -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])? |
USER_CODE => x"19880704", -- custom user code |
-- RISC-V CPU Extensions -- |
CPU_EXTENSION_RISCV_C => true, -- implement compressed extension? |
CPU_EXTENSION_RISCV_E => false, -- implement embedded RF extension? |
177,6 → 177,9
wb_cyc_o => wb_cpu.cyc, -- valid cycle |
wb_ack_i => wb_cpu.ack, -- transfer acknowledge |
wb_err_i => wb_cpu.err, -- transfer error |
-- Advanced memory control signals -- |
fence_o => open, -- indicates an executed FENCE operation |
fencei_o => open, -- indicates an executed FENCEI operation |
-- GPIO -- |
gpio_o => gpio, -- parallel output |
gpio_i => gpio, -- parallel input |
/neorv32/trunk/sw/bootloader/bootloader.c
149,7 → 149,6
uint32_t get_exe_word(int src, uint32_t addr); |
void system_error(uint8_t err_code); |
void print_hex_word(uint32_t num); |
void print_proc_version(void); |
|
// SPI flash access |
uint8_t spi_flash_read_byte(uint32_t addr); |
172,18 → 171,19
// ------------------------------------------------ |
|
// reset system time |
neorv32_mtime_set_time(0); |
MTIME_LO = 0; |
MTIME_HI = 0; |
|
// deactivate unused IO devices |
neorv32_wdt_disable(); |
neorv32_clic_disable(); |
neorv32_pwm_disable(); |
neorv32_spi_disable(); |
neorv32_trng_disable(); |
neorv32_twi_disable(); |
neorv32_wdt_disable(); |
|
// get clock speed (in Hz) |
uint32_t clock_speed = neorv32_cpu_csr_read(CSR_MCLOCK); |
uint32_t clock_speed = SYSINFO_CLK; |
|
// init SPI for 8-bit, clock-mode 0, MSB-first, no interrupt |
if (clock_speed < 40000000) { |
218,23 → 218,23
// ------------------------------------------------ |
neorv32_uart_print("\n\n\n\n<< NEORV32 Bootloader >>\n\n" |
"BLDV: "__DATE__"\nHWV: "); |
print_proc_version(); |
neorv32_rte_print_hw_version(); |
neorv32_uart_print("\nCLK: "); |
print_hex_word(neorv32_cpu_csr_read(CSR_MCLOCK)); |
neorv32_uart_print(" Hz\nMHID: "); |
print_hex_word(neorv32_cpu_csr_read(CSR_MHARTID)); |
print_hex_word(SYSINFO_CLK); |
neorv32_uart_print(" Hz\nUSER: "); |
print_hex_word(SYSINFO_USER_CODE); |
neorv32_uart_print("\nMISA: "); |
print_hex_word(neorv32_cpu_csr_read(CSR_MISA)); |
neorv32_uart_print("\nCONF: "); |
print_hex_word(neorv32_cpu_csr_read(CSR_MFEATURES)); |
print_hex_word(SYSINFO_FEATURES); |
neorv32_uart_print("\nIMEM: "); |
print_hex_word(neorv32_cpu_csr_read(CSR_MISPACESIZE)); |
print_hex_word(SYSINFO_ISPACE_SIZE); |
neorv32_uart_print(" bytes @ "); |
print_hex_word(neorv32_cpu_csr_read(CSR_MISPACEBASE)); |
print_hex_word(SYSINFO_ISPACE_BASE); |
neorv32_uart_print("\nDMEM: "); |
print_hex_word(neorv32_cpu_csr_read(CSR_MDSPACESIZE)); |
print_hex_word(SYSINFO_DSPACE_SIZE); |
neorv32_uart_print(" bytes @ "); |
print_hex_word(neorv32_cpu_csr_read(CSR_MDSPACEBASE)); |
print_hex_word(SYSINFO_DSPACE_BASE); |
|
|
// ------------------------------------------------ |
266,7 → 266,10
neorv32_uart_print("\n"); |
|
if (c == 'r') { // restart bootloader |
break; |
neorv32_cpu_dint(); // disable global interrupts |
// jump to beginning of boot ROM |
asm volatile ("li t0, %[input_i]; jr t0" : : [input_i] "i" (BOOTLOADER_BASE_ADDRESS)); |
while(1); // just for the compiler |
} |
else if (c == 'h') { // help menu |
print_help(); |
291,7 → 294,7
} |
} |
|
return 0; // bootloader will restart when returning |
return 0; // bootloader should never return |
} |
|
|
333,9 → 336,15
// wait for UART to finish transmitting |
while ((UART_CT & (1<<UART_CT_TX_BUSY)) != 0); |
|
// reset performance counters (to benchmark actual application) |
asm volatile ("csrrw zero, mcycle, zero"); // will also clear 'cycle' |
asm volatile ("csrrw zero, mcycleh, zero"); // will also clear 'cycleh' |
asm volatile ("csrrw zero, minstret, zero"); // will also clear 'instret' |
asm volatile ("csrrw zero, minstreth, zero"); // will also clear 'instreth' |
|
// start app at instruction space base address |
while (1) { |
register uint32_t app_base = neorv32_cpu_csr_read(CSR_MISPACEBASE); |
register uint32_t app_base = SYSINFO_ISPACE_BASE; |
asm volatile ("jalr zero, %0" : : "r" (app_base)); |
} |
} |
349,7 → 358,7
|
// make sure this was caused by MTIME IRQ |
uint32_t cause = neorv32_cpu_csr_read(CSR_MCAUSE); |
if (cause != 0x80000007) { // raw exception code for MTI |
if (cause != EXCCODE_MTI) { // raw exception code for MTI |
neorv32_uart_print("\n\nEXCEPTION: "); |
print_hex_word(cause); |
neorv32_uart_print(" @ 0x"); |
361,7 → 370,7
// toggle status LED |
neorv32_gpio_pin_toggle(STATUS_LED); |
// set time for next IRQ |
neorv32_mtime_set_timecmp(neorv32_mtime_get_time() + (neorv32_cpu_csr_read(CSR_MCLOCK)/4)); |
neorv32_mtime_set_timecmp(neorv32_mtime_get_time() + (SYSINFO_CLK/4)); |
} |
} |
|
374,7 → 383,7
void get_exe(int src) { |
|
// is instruction memory (actually, the IMEM) read-only? |
if (neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_MEM_INT_IMEM_ROM)) { |
if (SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_MEM_INT_IMEM_ROM)) { |
system_error(ERROR_ROM); |
} |
|
405,13 → 414,13
uint32_t check = get_exe_word(src, addr + EXE_OFFSET_CHECKSUM); // complement sum checksum |
|
// executable too large? |
uint32_t imem_size = neorv32_cpu_csr_read(CSR_MISPACESIZE); |
uint32_t imem_size = SYSINFO_ISPACE_SIZE; |
if (size > imem_size) { |
system_error(ERROR_SIZE); |
} |
|
// transfer program data |
uint32_t *pnt = (uint32_t*)neorv32_cpu_csr_read(CSR_MISPACEBASE); |
uint32_t *pnt = (uint32_t*)SYSINFO_ISPACE_BASE; |
uint32_t checksum = 0; |
uint32_t d = 0, i = 0; |
addr = addr + EXE_OFFSET_DATA; |
497,7 → 506,7
|
// store data from instruction memory and update checksum |
uint32_t checksum = 0; |
uint32_t *pnt = (uint32_t*)neorv32_cpu_csr_read(CSR_MISPACEBASE); |
uint32_t *pnt = (uint32_t*)SYSINFO_ISPACE_BASE; |
addr = addr + EXE_OFFSET_DATA; |
uint32_t i = 0; |
while (i < (size/4)) { // in words |
588,38 → 597,7
} |
|
|
/**********************************************************************//** |
* Print processor version. Deciaml format: "Dd.Dd.Dd.Dd". |
**************************************************************************/ |
void print_proc_version(void) { |
|
uint32_t i; |
char tmp, cnt; |
uint32_t version = neorv32_cpu_csr_read(CSR_MIMPID); |
|
for (i=0; i<4; i++) { |
|
tmp = (char)(version >> (24 - 8*i)); |
|
// serial division |
cnt = 0; |
while (tmp >= 10) { |
tmp = tmp - 10; |
cnt++; |
} |
|
if (cnt) { |
neorv32_uart_putc('0' + cnt); |
} |
neorv32_uart_putc('0' + tmp); |
if (i < 3) { |
neorv32_uart_putc('.'); |
} |
} |
} |
|
|
|
// ------------------------------------------------------------------------------------- |
// SPI flash functions |
// ------------------------------------------------------------------------------------- |
/neorv32/trunk/sw/common/bootloader_crt0.S
1,7 → 1,7
/* ################################################################################################# */ |
/* # << NEORV32 - bootloader_crt0.S - Bootloader Start-Up Code >> # */ |
/* # ********************************************************************************************* # */ |
/* # Minimal hardware setup (STACK + EXC handler). The rest is done by the bootloader itself. # */ |
/* # Minimal hardware setup (STACK + Trap handler). The rest is done by the bootloader itself. # */ |
/* # ********************************************************************************************* # */ |
/* # BSD 3-Clause License # */ |
/* # # */ |
40,9 → 40,9
.global _start |
|
|
// custom CSRs |
.set CSR_MDSPACEBASE, 0xfc5 // CUSTOM (r/-): Base address of data memory space (via MEM_DSPACE_BASE generic) */ |
.set CSR_MDSPACESIZE, 0xfc7 // CUSTOM (r/-): Total size of data memory space in byte (via MEM_DSPACE_SIZE generic) */ |
// SYSINFO |
.set SYSINFO_DSPACE_BASE, 0xFFFFFFF4 |
.set SYSINFO_DSPACE_SIZE, 0xFFFFFFFC |
|
|
_start: |
53,17 → 53,17
// Setup stack pointer |
// ********************************************************* |
__crt0_stack_pointer_init: |
csrrw x11, CSR_MDSPACEBASE, zero // data memory space base address |
csrrw x12, CSR_MDSPACESIZE, zero // data memory space size |
lw x11, SYSINFO_DSPACE_BASE(zero) // data memory space base address |
lw x12, SYSINFO_DSPACE_SIZE(zero) // data memory space size |
add sp, x11, x12 |
addi sp, sp, -4 // stack pointer = last entry |
addi sp, sp, -4 // stack pointer = last entry |
|
|
// ********************************************************* |
// Init exception vector base with dummy handler |
// ********************************************************* |
la x11, __crt0_dummy_exception_handler |
csrrw zero, mtvec, x11 |
la x13, __crt0_dummy_trap_handler |
csrw mtvec, x13 |
|
|
// ********************************************************* |
81,9 → 81,9
addi x8, zero, 0 |
addi x9, zero, 0 |
addi x10, zero, 0 |
addi x11, zero, 0 |
addi x12, zero, 0 |
addi x13, zero, 0 |
//addi x11, zero, 0 # allready initialized |
//addi x12, zero, 0 # allready initialized |
//addi x13, zero, 0 # allready initialized |
addi x14, zero, 0 |
addi x15, zero, 0 |
|
94,23 → 94,32
__crt0_main_entry: |
|
jal ra, main |
j _start # restart if main returns |
|
// if main returns: stall |
__crt0_the_end: |
j __crt0_the_end # restart if main returns |
|
|
// ********************************************************* |
// dummy exception handler (for exceptions only, no IRQs) |
// bootloader has to be compiled without any CPU extensions! |
// dummy trap handler (for exceptions & IRQs) |
// bootloader has to be compiled without any CPU extensions |
// - especially without C extension! |
// ********************************************************* |
__crt0_dummy_exception_handler: |
|
__crt0_dummy_trap_handler: |
|
addi sp, sp, -4 |
sw ra, 0(sp) |
sw x8, 0(sp) |
|
csrrw ra, mepc, zero |
addi ra, ra, +4 // just move on to next instruction |
csrrw zero, mepc, ra |
csrr x8, mcause |
blt x8, zero, __crt0_dummy_trap_handler_irq // skip mepc modification if interrupt |
|
lw ra, 0(sp) |
csrr x8, mepc |
addi x8, x8, +4 // move on to next instruction if exception |
csrw mepc, x8 |
|
__crt0_dummy_trap_handler_irq: |
|
lw x8, 0(sp) |
addi sp, sp, +4 |
|
mret |
/neorv32/trunk/sw/common/crt0.S
42,18 → 42,14
.global _start |
|
|
// custom CSRs |
.set CSR_MISPACEBASE, 0xfc4 // CUSTOM (r/-): Base address of instruction memory space (via MEM_ISPACE_BASE generic) */ |
.set CSR_MDSPACEBASE, 0xfc5 // CUSTOM (r/-): Base address of data memory space (via MEM_DSPACE_BASE generic) */ |
.set CSR_MISPACESIZE, 0xfc6 // CUSTOM (r/-): Total size of instruction memory space in byte (via MEM_ISPACE_SIZE generic) */ |
.set CSR_MDSPACESIZE, 0xfc7 // CUSTOM (r/-): Total size of data memory space in byte (via MEM_DSPACE_SIZE generic) */ |
|
// IO region |
.set IO_BEGIN, 0xFFFFFF80 // start of processor-internal IO region |
.set MTIMECMP_LO, 0xFFFFFF98 |
.set MTIMECMP_HI, 0xFFFFFF9C |
.set IO_BEGIN, 0xFFFFFF80 // start of processor-internal IO region |
|
// SYSINFO |
.set SYSINFO_DSPACE_BASE, 0xFFFFFFF4 |
.set SYSINFO_DSPACE_SIZE, 0xFFFFFFFC |
|
|
_start: |
.cfi_startproc |
.cfi_undefined ra |
114,8 → 110,8
// Setup stack pointer |
// ********************************************************* |
__crt0_stack_pointer_init: |
csrr x11, CSR_MDSPACEBASE // data memory space base address |
csrr x12, CSR_MDSPACESIZE // data memory space size |
lw x11, SYSINFO_DSPACE_BASE(zero) // data memory space base address |
lw x12, SYSINFO_DSPACE_SIZE(zero) // data memory space size |
add sp, x11, x12 |
addi sp, sp, -4 // stack pointer = last entry |
addi fp, sp, 0 // frame pointer = stack pointer |
138,7 → 134,7
la x11, __crt0_neorv32_rte |
csrw mtvec, x11 // set address of first-level exception handler |
|
csrr x11, CSR_MDSPACEBASE // data memory space base address |
lw x11, SYSINFO_DSPACE_BASE(zero) // data memory space base address |
la x12, __crt0_neorv32_rte_dummy_hanlder |
li x13, 2*16 // number of entries (16xEXC, 16xIRQ) |
|
162,12 → 158,7
addi x11, x11, 4 |
bne zero, x11, __crt0_reset_io_loop |
|
// set mtime_compare to MAX (to prevent an IRQ) |
li x11, -1 |
sw x11, MTIMECMP_LO(zero) |
sw x11, MTIMECMP_HI(zero) |
|
|
// ********************************************************* |
// Clear .bss section (byte-wise) |
// ********************************************************* |
227,6 → 218,7
// ********************************************************* |
// NEORV32 runtime environment: First-level exception/interrupt handler |
// ********************************************************* |
.align 4 |
__crt0_neorv32_rte: |
|
// -------------------------------------------- |
279,7 → 271,7
|
andi t1, t0, 0x0f // isolate cause ID |
slli t1, t1, 2 // make address offset |
csrr ra, CSR_MDSPACEBASE // data memory space base address |
lw ra, SYSINFO_DSPACE_BASE(zero) // data memory space base address |
add t1, t1, ra // get vetor table entry address (EXC vectors) |
|
csrr ra, mepc // get return address |
/neorv32/trunk/sw/example/coremark/core_portme.c
71,7 → 71,9
or zeroing some system parameters - e.g. setting the cpu clocks cycles to 0. |
*/ |
void start_time(void) { |
elapsed_cycles = neorv32_mtime_get_time(); |
elapsed_cycles = 0; // this is time zero |
neorv32_cpu_set_mcycle(0); |
neorv32_cpu_set_minstret(0); |
//GETMYTIME(&start_time_val ); |
} |
/* Function : stop_time |
93,7 → 95,7
and the resolution is controlled by <TIMER_RES_DIVIDER> |
*/ |
CORE_TICKS get_time(void) { |
CORE_TICKS elapsed = ((CORE_TICKS)neorv32_mtime_get_time()) - elapsed_cycles; |
CORE_TICKS elapsed = ((CORE_TICKS)neorv32_cpu_get_cycle()) - elapsed_cycles; |
elapsed_cycles = elapsed; |
//CORE_TICKS elapsed=(CORE_TICKS)(MYTIMEDIFF(stop_time_val, start_time_val)); |
return elapsed; |
106,7 → 108,7
*/ |
secs_ret time_in_secs(CORE_TICKS ticks) { |
//secs_ret retval=((secs_ret)ticks) / (secs_ret)EE_TICKS_PER_SEC; |
secs_ret retval=(secs_ret)(ticks / neorv32_cpu_csr_read(CSR_MCLOCK)); |
secs_ret retval=(secs_ret)(ticks / SYSINFO_CLK); |
return retval; |
} |
|
127,13 → 129,7
// setup neorv32 UART |
neorv32_uart_setup(BAUD_RATE, 0, 0); |
|
// check if MTIME unit was synthesized |
if (!neorv32_mtime_available()) { |
neorv32_uart_printf("NEORV32: Error! No MTIME unit synthesized!"); |
while(1); |
} |
|
neorv32_uart_printf("NEORV32: Processor running at %u Hz\n", (uint32_t)neorv32_cpu_csr_read(CSR_MCLOCK)); |
neorv32_uart_printf("NEORV32: Processor running at %u Hz\n", (uint32_t)SYSINFO_CLK); |
neorv32_uart_printf("NEORV32: Executing coremark (%u iterations). This may take some time...\n\n", (uint32_t)ITERATIONS); |
|
if (sizeof(ee_ptr_int) != sizeof(ee_u8 *)) { |
155,23 → 151,14
union { |
uint64_t uint64; |
uint32_t uint32[sizeof(uint64_t)/2]; |
} exe_cycles; |
|
union { |
uint64_t uint64; |
uint32_t uint32[sizeof(uint64_t)/2]; |
} exe_instructions, exe_time; |
|
exe_time.uint64 = (uint64_t)elapsed_cycles; |
exe_cycles.uint32[0] = neorv32_cpu_csr_read(CSR_TIME); |
exe_cycles.uint32[1] = neorv32_cpu_csr_read(CSR_TIMEH); |
exe_instructions.uint32[0] = neorv32_cpu_csr_read(CSR_INSTRET); |
exe_instructions.uint32[1] = neorv32_cpu_csr_read(CSR_INSTRETH); |
exe_instructions.uint64 = neorv32_cpu_get_instret(); |
|
neorv32_uart_printf("\nNEORV32: Executed instructions 0x%x_%x\n", (uint32_t)exe_instructions.uint32[1], (uint32_t)exe_instructions.uint32[0]); |
neorv32_uart_printf("NEORV32: Total required clock cycles 0x%x_%x\n", (uint32_t)exe_cycles.uint32[1], (uint32_t)exe_cycles.uint32[0]); |
neorv32_uart_printf("NEORV32: CoreMark core clock cycles 0x%x_%x\n", (uint32_t)exe_time.uint32[1], (uint32_t)exe_time.uint32[0]); |
neorv32_uart_printf("\nNEORV32: Executed instructions 0x%x_%x\n", (uint32_t)exe_instructions.uint32[1], (uint32_t)exe_instructions.uint32[0]); |
neorv32_uart_printf("NEORV32: CoreMark core clock cycles 0x%x_%x\n", (uint32_t)exe_time.uint32[1], (uint32_t)exe_time.uint32[0]); |
|
uint64_t average_cpi = exe_cycles.uint64 / exe_instructions.uint64; |
uint64_t average_cpi = exe_time.uint64 / exe_instructions.uint64; |
neorv32_uart_printf("NEORV32: Average CPI (integer part only): %u cycles/instruction\n", (uint32_t)average_cpi); |
} |
/neorv32/trunk/sw/example/cpu_test/main.c
36,7 → 36,7
/**********************************************************************//** |
* @file cpu_test/main.c |
* @author Stephan Nolting |
* @brief Simple CPU interrupts and exceptions test program. |
* @brief Simple CPU (interrupts and exceptions) test program. |
**************************************************************************/ |
|
#include <neorv32.h> |
50,6 → 50,8
#define BAUD_RATE 19200 |
//** Set 1 for detailed exception debug information */ |
#define DETAILED_EXCEPTION_DEBUG 0 |
//** Set 1 to run memory tests */ |
#define PROBING_MEM_TEST 0 |
//** Reachable unaligned address */ |
#define ADDR_UNALIGNED 0x00000002 |
//** Unreachable aligned address */ |
61,39 → 63,13
* @name Exception handler acknowledges |
**************************************************************************/ |
/**@{*/ |
/** Exception handler answers / identifiers */ |
enum EXC_HANDLER_ANSWERS { |
ANSWER_I_MISALIGN = 0x12345678, /**< Answer for misaligned instruction address excetion */ |
ANSWER_I_ACCESS = 0xAABB1133, /**< Answer for instruction access fault excetion */ |
ANSWER_I_ILLEGAL = 0x0199203B, /**< Answer for illegal instruction excetion */ |
ANSWER_BREAKPOINT = 0x12322330, /**< Answer for breakpoint excetion */ |
ANSWER_L_MISALIGN = 0xBABCCCCC, /**< Answer for misaligned load address excetion */ |
ANSWER_L_ACCESS = 0xDEF728AA, /**< Answer for load access fault excetion */ |
ANSWER_S_MISALIGN = 0xFF0927DD, /**< Answer for misaligned store address excetion */ |
ANSWER_S_ACCESS = 0x20091777, /**< Answer for store access fault excetion */ |
ANSWER_ENVCALL = 0x55662244, /**< Answer for environment call excetion */ |
ANSWER_MSI = 0xCDECDEA9, /**< Answer for machine software interrupt */ |
ANSWER_MTI = 0x0012FA53, /**< Answer for machine timer interrupt */ |
ANSWER_CLIC = 0xEEF33088 /**< Answer for machine external interrupt */ |
}; |
/** Gloabl volatile variable to store exception handler answer */ |
/** Global volatile variable to store exception handler answer */ |
volatile uint32_t exception_handler_answer; |
/**@}*/ |
|
|
// Prototypes |
void exc_handler_i_misalign(void); |
void exc_handler_i_access(void); |
void exc_handler_i_illegal(void); |
void exc_handler_breakpoint(void); |
void exc_handler_l_misalign(void); |
void exc_handler_l_access(void); |
void exc_handler_s_misalign(void); |
void exc_handler_s_access(void); |
void exc_handler_envcall(void); |
void exc_handler_msi(void); |
void exc_handler_mti(void); |
void irq_handler_clic_ch0(); |
void global_trap_handler(void); |
|
|
/**********************************************************************//** |
164,27 → 140,26
|
// install exception handler functions |
int install_err = 0; |
install_err += neorv32_rte_exception_install(EXCID_I_MISALIGNED, exc_handler_i_misalign); |
install_err += neorv32_rte_exception_install(EXCID_I_ACCESS, exc_handler_i_access); |
install_err += neorv32_rte_exception_install(EXCID_I_ILLEGAL, exc_handler_i_illegal); |
install_err += neorv32_rte_exception_install(EXCID_BREAKPOINT, exc_handler_breakpoint); |
install_err += neorv32_rte_exception_install(EXCID_L_MISALIGNED, exc_handler_l_misalign); |
install_err += neorv32_rte_exception_install(EXCID_L_ACCESS, exc_handler_l_access); |
install_err += neorv32_rte_exception_install(EXCID_S_MISALIGNED, exc_handler_s_misalign); |
install_err += neorv32_rte_exception_install(EXCID_S_ACCESS, exc_handler_s_access); |
install_err += neorv32_rte_exception_install(EXCID_MENV_CALL, exc_handler_envcall); |
install_err += neorv32_rte_exception_install(EXCID_MSI, exc_handler_msi); |
install_err += neorv32_rte_exception_install(EXCID_MTI, exc_handler_mti); |
install_err += neorv32_rte_exception_install(EXCID_I_MISALIGNED, global_trap_handler); |
install_err += neorv32_rte_exception_install(EXCID_I_ACCESS, global_trap_handler); |
install_err += neorv32_rte_exception_install(EXCID_I_ILLEGAL, global_trap_handler); |
install_err += neorv32_rte_exception_install(EXCID_BREAKPOINT, global_trap_handler); |
install_err += neorv32_rte_exception_install(EXCID_L_MISALIGNED, global_trap_handler); |
install_err += neorv32_rte_exception_install(EXCID_L_ACCESS, global_trap_handler); |
install_err += neorv32_rte_exception_install(EXCID_S_MISALIGNED, global_trap_handler); |
install_err += neorv32_rte_exception_install(EXCID_S_ACCESS, global_trap_handler); |
install_err += neorv32_rte_exception_install(EXCID_MENV_CALL, global_trap_handler); |
install_err += neorv32_rte_exception_install(EXCID_MTI, global_trap_handler); |
//install_err += neorv32_rte_exception_install(EXCID_MEI, -); done by neorv32_clic_handler_install |
|
if (install_err) { |
neorv32_uart_printf("install error!\n"); |
neorv32_uart_printf("RTE install error!\n"); |
return 0; |
} |
|
|
// install interrupt handler for clic WDT channel |
install_err += neorv32_clic_handler_install(CLIC_CH_WDT, irq_handler_clic_ch0); |
install_err += neorv32_clic_handler_install(CLIC_CH_WDT, global_trap_handler); |
|
if (install_err) { |
neorv32_uart_printf("CLIC install error!\n"); |
203,10 → 178,79
// enable global interrupts |
neorv32_cpu_eint(); |
|
exception_handler_answer = 0; |
exception_handler_answer = 0xFFFFFFFF; |
|
|
// ---------------------------------------------------------- |
// Instruction memory test |
// ---------------------------------------------------------- |
exception_handler_answer = 0xFFFFFFFF; |
neorv32_uart_printf("IMEM_TEST: "); |
#if (PROBING_MEM_TEST == 1) |
cnt_test++; |
|
register uint32_t dmem_probe_addr = neorv32_cpu_csr_read(CSR_MISPACEBASE); |
uint32_t dmem_probe_cnt = 0; |
|
while(1) { |
asm volatile ("lb zero, 0(%[input_j])" : : [input_j] "r" (dmem_probe_addr)); |
if (exception_handler_answer == EXCCODE_L_ACCESS) { |
break; |
} |
dmem_probe_addr++; |
dmem_probe_cnt++; |
} |
|
neorv32_uart_printf("%u bytes (should be %u bytes) ", dmem_probe_cnt, neorv32_cpu_csr_read(CSR_MISPACESIZE)); |
neorv32_uart_printf("@ 0x%x ", neorv32_cpu_csr_read(CSR_MISPACEBASE)); |
if (dmem_probe_cnt == neorv32_cpu_csr_read(CSR_MISPACESIZE)) { |
neorv32_uart_printf("ok\n"); |
cnt_ok++; |
} |
else { |
neorv32_uart_printf("fail\n"); |
cnt_fail++; |
} |
#else |
neorv32_uart_printf("skipped (disabled)\n"); |
#endif |
|
// ---------------------------------------------------------- |
// Data memory test |
// ---------------------------------------------------------- |
exception_handler_answer = 0xFFFFFFFF; |
neorv32_uart_printf("DMEM_TEST: "); |
#if (PROBING_MEM_TEST == 1) |
cnt_test++; |
|
register uint32_t imem_probe_addr = neorv32_cpu_csr_read(CSR_MDSPACEBASE); |
uint32_t imem_probe_cnt = 0; |
|
while(1) { |
asm volatile ("lb zero, 0(%[input_j])" : : [input_j] "r" (imem_probe_addr)); |
if (exception_handler_answer == EXCCODE_L_ACCESS) { |
break; |
} |
imem_probe_addr++; |
imem_probe_cnt++; |
} |
|
neorv32_uart_printf("%u bytes (should be %u bytes) ", imem_probe_cnt, neorv32_cpu_csr_read(CSR_MDSPACESIZE)); |
neorv32_uart_printf("@ 0x%x ", neorv32_cpu_csr_read(CSR_MDSPACEBASE)); |
if (imem_probe_cnt == neorv32_cpu_csr_read(CSR_MDSPACESIZE)) { |
neorv32_uart_printf("ok\n"); |
cnt_ok++; |
} |
else { |
neorv32_uart_printf("fail\n"); |
cnt_fail++; |
} |
#else |
neorv32_uart_printf("skipped (disabled)\n"); |
#endif |
|
|
// ---------------------------------------------------------- |
// Test counter CSR access for mcycle[h] |
// ---------------------------------------------------------- |
neorv32_uart_printf("MCYCLE[H]: "); |
213,10 → 257,10
cnt_test++; |
|
neorv32_cpu_csr_write(CSR_MCYCLE, 0x1BCD1234); |
neorv32_cpu_csr_write(CSR_MCYCLEH, 0x22334455); |
neorv32_cpu_csr_write(CSR_MCYCLEH, 0x00034455); |
|
if (((neorv32_cpu_csr_read(CSR_MCYCLE) & 0xffff0000L) == 0x1BCD0000) && |
(neorv32_cpu_csr_read(CSR_MCYCLEH) == 0x22334455)) { |
(neorv32_cpu_csr_read(CSR_MCYCLEH) == 0x00034455)) { |
neorv32_uart_printf("ok\n"); |
cnt_ok++; |
} |
233,10 → 277,10
cnt_test++; |
|
neorv32_cpu_csr_write(CSR_MINSTRET, 0x11224499); |
neorv32_cpu_csr_write(CSR_MINSTRETH, 0x00110011); |
neorv32_cpu_csr_write(CSR_MINSTRETH, 0x00090011); |
|
if (((neorv32_cpu_csr_read(CSR_MINSTRET) & 0xffff0000L) == 0x11220000) && |
(neorv32_cpu_csr_read(CSR_MINSTRETH) == 0x00110011)) { |
(neorv32_cpu_csr_read(CSR_MINSTRETH) == 0x00090011)) { |
neorv32_uart_printf("ok\n"); |
cnt_ok++; |
} |
272,13 → 316,13
// Test fence instructions - make sure CPU does not crash here and throws no exception |
// a more complex test is provided by the RISC-V compliance test |
// ---------------------------------------------------------- |
exception_handler_answer = 0; |
exception_handler_answer = 0xFFFFFFFF; |
neorv32_uart_printf("FENCE(.I): "); |
cnt_test++; |
asm volatile ("fence"); |
asm volatile ("fence.i"); |
|
if (exception_handler_answer != 0) { |
if (exception_handler_answer != 0xFFFFFFFF) { |
neorv32_uart_printf("fail\n"); |
cnt_fail++; |
} |
291,7 → 335,7
// ---------------------------------------------------------- |
// Unaligned instruction address |
// ---------------------------------------------------------- |
exception_handler_answer = 0; |
exception_handler_answer = 0xFFFFFFFF; |
neorv32_uart_printf("EXC I_ALIGN: "); |
|
// skip if C-mode is not implemented |
303,7 → 347,7
((void (*)(void))ADDR_UNALIGNED)(); |
|
#if (DETAILED_EXCEPTION_DEBUG==0) |
if (exception_handler_answer == ANSWER_I_MISALIGN) { |
if (exception_handler_answer == EXCCODE_I_MISALIGNED) { |
neorv32_uart_printf("ok\n"); |
cnt_ok++; |
} |
321,7 → 365,7
// ---------------------------------------------------------- |
// Instruction access fault |
// ---------------------------------------------------------- |
exception_handler_answer = 0; |
exception_handler_answer = 0xFFFFFFFF; |
neorv32_uart_printf("EXC I_ACC: "); |
cnt_test++; |
|
329,7 → 373,7
((void (*)(void))ADDR_UNREACHABLE)(); |
|
#if (DETAILED_EXCEPTION_DEBUG==0) |
if (exception_handler_answer == ANSWER_I_ACCESS) { |
if (exception_handler_answer == EXCCODE_I_ACCESS) { |
neorv32_uart_printf("ok\n"); |
cnt_ok++; |
} |
343,7 → 387,7
// ---------------------------------------------------------- |
// Illegal instruction |
// ---------------------------------------------------------- |
exception_handler_answer = 0; |
exception_handler_answer = 0xFFFFFFFF; |
neorv32_uart_printf("EXC I_ILLEG: "); |
cnt_test++; |
|
357,7 → 401,7
asm volatile ( "jalr ra, %0 " : "=r" (tmp_a) : "r" (tmp_a)); |
|
#if (DETAILED_EXCEPTION_DEBUG==0) |
if (exception_handler_answer == ANSWER_I_ILLEGAL) { |
if (exception_handler_answer == EXCCODE_I_ILLEGAL) { |
neorv32_uart_printf("ok\n"); |
cnt_ok++; |
} |
371,7 → 415,7
// ---------------------------------------------------------- |
// Breakpoint instruction |
// ---------------------------------------------------------- |
exception_handler_answer = 0; |
exception_handler_answer = 0xFFFFFFFF; |
neorv32_uart_printf("EXC BREAK: "); |
cnt_test++; |
|
378,7 → 422,7
asm volatile("EBREAK"); |
|
#if (DETAILED_EXCEPTION_DEBUG==0) |
if (exception_handler_answer == ANSWER_BREAKPOINT) { |
if (exception_handler_answer == EXCCODE_BREAKPOINT) { |
neorv32_uart_printf("ok\n"); |
cnt_ok++; |
} |
392,7 → 436,7
// ---------------------------------------------------------- |
// Unaligned load address |
// ---------------------------------------------------------- |
exception_handler_answer = 0; |
exception_handler_answer = 0xFFFFFFFF; |
neorv32_uart_printf("EXC L_ALIGN: "); |
cnt_test++; |
|
400,7 → 444,7
asm volatile ("lw zero, %[input_i](zero)" : : [input_i] "i" (ADDR_UNALIGNED)); |
|
#if (DETAILED_EXCEPTION_DEBUG==0) |
if (exception_handler_answer == ANSWER_L_MISALIGN) { |
if (exception_handler_answer == EXCCODE_L_MISALIGNED) { |
neorv32_uart_printf("ok\n"); |
cnt_ok++; |
} |
414,7 → 458,7
// ---------------------------------------------------------- |
// Load access fault |
// ---------------------------------------------------------- |
exception_handler_answer = 0; |
exception_handler_answer = 0xFFFFFFFF; |
neorv32_uart_printf("EXC L_ACC: "); |
cnt_test++; |
|
422,7 → 466,7
dummy_dst = MMR_UNREACHABLE; |
|
#if (DETAILED_EXCEPTION_DEBUG==0) |
if (exception_handler_answer == ANSWER_L_ACCESS) { |
if (exception_handler_answer == EXCCODE_L_ACCESS) { |
neorv32_uart_printf("ok\n"); |
cnt_ok++; |
} |
436,7 → 480,7
// ---------------------------------------------------------- |
// Unaligned store address |
// ---------------------------------------------------------- |
exception_handler_answer = 0; |
exception_handler_answer = 0xFFFFFFFF; |
neorv32_uart_printf("EXC S_ALIGN: "); |
cnt_test++; |
|
444,7 → 488,7
asm volatile ("sw zero, %[input_i](zero)" : : [input_i] "i" (ADDR_UNALIGNED)); |
|
#if (DETAILED_EXCEPTION_DEBUG==0) |
if (exception_handler_answer == ANSWER_S_MISALIGN) { |
if (exception_handler_answer == EXCCODE_S_MISALIGNED) { |
neorv32_uart_printf("ok\n"); |
cnt_ok++; |
} |
458,7 → 502,7
// ---------------------------------------------------------- |
// Store access fault |
// ---------------------------------------------------------- |
exception_handler_answer = 0; |
exception_handler_answer = 0xFFFFFFFF; |
neorv32_uart_printf("EXC S_ACC: "); |
cnt_test++; |
|
466,7 → 510,7
MMR_UNREACHABLE = 0; |
|
#if (DETAILED_EXCEPTION_DEBUG==0) |
if (exception_handler_answer == ANSWER_S_ACCESS) { |
if (exception_handler_answer == EXCCODE_S_ACCESS) { |
neorv32_uart_printf("ok\n"); |
cnt_ok++; |
} |
480,7 → 524,7
// ---------------------------------------------------------- |
// Environment call |
// ---------------------------------------------------------- |
exception_handler_answer = 0; |
exception_handler_answer = 0xFFFFFFFF; |
neorv32_uart_printf("EXC ENVCALL: "); |
cnt_test++; |
|
487,7 → 531,7
asm volatile("ECALL"); |
|
#if (DETAILED_EXCEPTION_DEBUG==0) |
if (exception_handler_answer == ANSWER_ENVCALL) { |
if (exception_handler_answer == EXCCODE_MENV_CALL) { |
neorv32_uart_printf("ok\n"); |
cnt_ok++; |
} |
499,31 → 543,9
|
|
// ---------------------------------------------------------- |
// Machine software interrupt |
// ---------------------------------------------------------- |
exception_handler_answer = 0; |
neorv32_uart_printf("IRQ MSI: "); |
cnt_test++; |
|
// trigger machine software interrupt |
neorv32_cpu_sw_irq(); |
|
#if (DETAILED_EXCEPTION_DEBUG==0) |
if (exception_handler_answer == ANSWER_MSI) { |
neorv32_uart_printf("ok\n"); |
cnt_ok++; |
} |
else { |
neorv32_uart_printf("fail\n"); |
cnt_fail++; |
} |
#endif |
|
|
// ---------------------------------------------------------- |
// Machine timer interrupt (MTIME) |
// ---------------------------------------------------------- |
exception_handler_answer = 0; |
exception_handler_answer = 0xFFFFFFFF; |
neorv32_uart_printf("IRQ MTI: "); |
cnt_test++; |
|
537,7 → 559,7
asm volatile("nop"); |
|
#if (DETAILED_EXCEPTION_DEBUG==0) |
if (exception_handler_answer == ANSWER_MTI) { |
if (exception_handler_answer == EXCCODE_MTI) { |
neorv32_uart_printf("ok\n"); |
cnt_ok++; |
} |
554,7 → 576,7
// ---------------------------------------------------------- |
// Machine external interrupt (via CLIC) |
// ---------------------------------------------------------- |
exception_handler_answer = 0; |
exception_handler_answer = 0xFFFFFFFF; |
neorv32_uart_printf("IRQ MEI: "); |
cnt_test++; |
|
568,7 → 590,7
asm volatile("nop"); |
|
#if (DETAILED_EXCEPTION_DEBUG==0) |
if (exception_handler_answer == ANSWER_CLIC) { |
if (exception_handler_answer == EXCCODE_MEI) { |
neorv32_uart_printf("ok\n"); |
cnt_ok++; |
} |
582,7 → 604,7
// ---------------------------------------------------------- |
// Test WFI ("sleep") instructions |
// ---------------------------------------------------------- |
exception_handler_answer = 0; |
exception_handler_answer = 0xFFFFFFFF; |
neorv32_uart_printf("WFI: "); |
cnt_test++; |
|
592,7 → 614,7
// put CPU into sleep mode |
asm volatile ("wfi"); |
|
if (exception_handler_answer != ANSWER_MTI) { |
if (exception_handler_answer != EXCCODE_MTI) { |
neorv32_uart_printf("fail\n"); |
cnt_fail++; |
} |
603,9 → 625,6
|
|
|
|
|
|
// error report |
neorv32_uart_printf("\n\nTests: %i\nOK: %i\nFAIL: %i\n\n", cnt_test, cnt_ok, cnt_fail); |
|
622,88 → 641,8
|
|
/**********************************************************************//** |
* Misaligned instruction address exception handler. |
* Trap handler for ALL exceptions/interrupts. |
**************************************************************************/ |
void exc_handler_i_misalign(void) { |
exception_handler_answer = ANSWER_I_MISALIGN; |
void global_trap_handler(void) { |
exception_handler_answer = neorv32_cpu_csr_read(CSR_MCAUSE); |
} |
|
/**********************************************************************//** |
* Instruction access fault exception handler. |
**************************************************************************/ |
void exc_handler_i_access(void) { |
exception_handler_answer = ANSWER_I_ACCESS; |
} |
|
/**********************************************************************//** |
* Illegal instruction exception handler. |
**************************************************************************/ |
void exc_handler_i_illegal(void) { |
exception_handler_answer = ANSWER_I_ILLEGAL; |
} |
|
/**********************************************************************//** |
* Breakpoint exception handler. |
**************************************************************************/ |
void exc_handler_breakpoint(void) { |
exception_handler_answer = ANSWER_BREAKPOINT; |
} |
|
/**********************************************************************//** |
* Misaligned load address exception handler. |
**************************************************************************/ |
void exc_handler_l_misalign(void) { |
exception_handler_answer = ANSWER_L_MISALIGN; |
} |
|
/**********************************************************************//** |
* Load instruction access fault exception handler. |
**************************************************************************/ |
void exc_handler_l_access(void) { |
exception_handler_answer = ANSWER_L_ACCESS; |
} |
|
/**********************************************************************//** |
* Misaligned store address exception handler. |
**************************************************************************/ |
void exc_handler_s_misalign(void) { |
exception_handler_answer = ANSWER_S_MISALIGN; |
} |
|
/**********************************************************************//** |
* Store address access fault exception handler. |
**************************************************************************/ |
void exc_handler_s_access(void) { |
exception_handler_answer = ANSWER_S_ACCESS; |
} |
|
/**********************************************************************//** |
* Environment call exception handler. |
**************************************************************************/ |
void exc_handler_envcall(void) { |
exception_handler_answer = ANSWER_ENVCALL; |
} |
|
/**********************************************************************//** |
* Machine software interrupt exception handler. |
**************************************************************************/ |
void exc_handler_msi(void) { |
exception_handler_answer = ANSWER_MSI; |
} |
|
/**********************************************************************//** |
* Machine timer interrupt exception handler. |
**************************************************************************/ |
void exc_handler_mti(void) { |
exception_handler_answer = ANSWER_MTI; |
// set CMP of machine system timer MTIME to max to prevent an IRQ |
neorv32_mtime_set_timecmp(-1); |
} |
|
/**********************************************************************//** |
* CLIC interrupt handler for channel 0. |
**************************************************************************/ |
void irq_handler_clic_ch0(void) { |
exception_handler_answer = ANSWER_CLIC; |
} |
|
/neorv32/trunk/sw/example/demo_twi/main.c
185,7 → 185,7
} |
|
// print new clock frequency |
uint32_t clock = neorv32_cpu_csr_read(CSR_MCLOCK); |
uint32_t clock = SYSINFO_CLK; |
switch (prsc) { |
case 0: clock = clock / 2; break; |
case 1: clock = clock / 4; break; |
/neorv32/trunk/sw/lib/include/neorv32.h
61,38 → 61,33
**************************************************************************/ |
enum NEORV32_CPU_CSRS_enum { |
CSR_MSTATUS = 0x300, /**< 0x300 - mstatus (r/w): Machine status register */ |
CSR_MISA = 0x301, /**< 0x301 - misa (r/-): CPU ISA and extensions */ |
CSR_MISA = 0x301, /**< 0x301 - misa (r/-): CPU ISA and extensions (read-only in NEORV32) */ |
CSR_MIE = 0x304, /**< 0x304 - mie (r/w): Machine interrupt-enable register */ |
CSR_MTVEC = 0x305, /**< 0x305 - mtvec (r/w): Machine trap-handler base address (for ALL traps) */ |
|
CSR_MSCRATCH = 0x340, /**< 0x340 - mscratch (r/w): Machine scratch register */ |
CSR_MEPC = 0x341, /**< 0x341 - mepc (r/w): Machine exception program counter */ |
CSR_MCAUSE = 0x342, /**< 0x342 - mcause (r/-): Machine trap cause */ |
CSR_MTVAL = 0x343, /**< 0x343 - mtval (r/-): Machine bad address or instruction */ |
CSR_MCAUSE = 0x342, /**< 0x342 - mcause (r/w): Machine trap cause */ |
CSR_MTVAL = 0x343, /**< 0x343 - mtval (r/w): Machine bad address or instruction */ |
CSR_MIP = 0x344, /**< 0x344 - mip (r/w): Machine interrupt pending register */ |
|
CSR_MCYCLE = 0xb00, /**< 0xb00 - mcycle (r/w): Machine cycle counter low word */ |
CSR_MINSTRET = 0xb02, /**< 0xb02 - minstret (r/w): Machine instructions-retired counter low word */ |
CSR_MCYCLEH = 0xb80, /**< 0xb80 - mcycleh (r/w): Machine cycle counter high word */ |
CSR_MINSTRETH = 0xb82, /**< 0xb82 - minstreth (r/w): Machine instructions-retired counter high word */ |
CSR_MCYCLEH = 0xb80, /**< 0xb80 - mcycleh (r/w): Machine cycle counter high word - only 20-bit wide!*/ |
CSR_MINSTRETH = 0xb82, /**< 0xb82 - minstreth (r/w): Machine instructions-retired counter high word - only 20-bit wide! */ |
|
CSR_CYCLE = 0xc00, /**< 0xc00 - cycle (r/-): Cycle counter low word */ |
CSR_TIME = 0xc01, /**< 0xc01 - time (r/-): Timer low word (from MTIME.TIME) */ |
CSR_INSTRET = 0xc02, /**< 0xc02 - instret (r/-): Instructions-retired counter low word */ |
CSR_CYCLE = 0xc00, /**< 0xc00 - cycle (r/-): Cycle counter low word (from MCYCLE) */ |
CSR_TIME = 0xc01, /**< 0xc01 - time (r/-): Timer low word (from MTIME.TIME_LO) */ |
CSR_INSTRET = 0xc02, /**< 0xc02 - instret (r/-): Instructions-retired counter low word (from MINSTRET) */ |
|
CSR_CYCLEH = 0xc80, /**< 0xc80 - cycleh (r/-): Cycle counter high word */ |
CSR_TIMEH = 0xc81, /**< 0xc81 - timeh (r/-): Timer high word (from MTIME.TIME) */ |
CSR_INSTRETH = 0xc82, /**< 0xc82 - instreth (r/-): Instructions-retired counter high word */ |
CSR_CYCLEH = 0xc80, /**< 0xc80 - cycleh (r/-): Cycle counter high word (from MCYCLEH) - only 20-bit wide! */ |
CSR_TIMEH = 0xc81, /**< 0xc81 - timeh (r/-): Timer high word (from MTIME.TIME_HI) */ |
CSR_INSTRETH = 0xc82, /**< 0xc82 - instreth (r/-): Instructions-retired counter high word (from MINSTRETH) - only 20-bit wide! */ |
|
CSR_MIMPID = 0xf13, /**< 0xf13 - mimpid (r/-): Implementation ID/version */ |
CSR_MHARTID = 0xf14, /**< 0xf14 - mhartid (r/-): Hardware thread ID (via HART_ID generic) */ |
|
CSR_MFEATURES = 0xfc0, /**< 0xfc0 - CUSTOM (r/-): Implemented processor devices/features (via IO_x_USE generics) */ |
CSR_MCLOCK = 0xfc1, /**< 0xfc1 - CUSTOM (r/-): Processor primary clock spedd in Hz (via CLOCK_FREQUENCY generic)*/ |
CSR_MISPACEBASE = 0xfc4, /**< 0xfc4 - CUSTOM (r/-): Base address of instruction memory space (via MEM_ISPACE_BASE generic) */ |
CSR_MDSPACEBASE = 0xfc5, /**< 0xfc5 - CUSTOM (r/-): Base address of data memory space (via MEM_DSPACE_BASE generic) */ |
CSR_MISPACESIZE = 0xfc6, /**< 0xfc6 - CUSTOM (r/-): Total size of instruction memory space in byte (via MEM_ISPACE_SIZE generic) */ |
CSR_MDSPACESIZE = 0xfc7 /**< 0xfc7 - CUSTOM (r/-): Total size of data memory space in byte (via MEM_DSPACE_SIZE generic) */ |
CSR_MVENDORID = 0xf11, /**< 0xf11 - mvendorid (r/-): Vendor ID */ |
CSR_MARCHID = 0xf12, /**< 0xf12 - marchid (r/-): Architecture ID */ |
CSR_MIMPID = 0xf13, /**< 0xf13 - mimpid (r/-): Implementation ID/version */ |
CSR_MHARTID = 0xf14 /**< 0xf14 - mhartid (r/-): Hardware thread ID (always 0) */ |
}; |
|
|
109,7 → 104,7
* CPU <b>mie</b> CSR (r/w): Machine interrupt enable (RISC-V spec.) |
**************************************************************************/ |
enum NEORV32_CPU_MIE_enum { |
CPU_MIE_MSIE = 3, /**< CPU mie CSR (3): Machine software interrupt enable bit (r/w) */ |
CPU_MIE_MSIE = 3, /**< CPU mie CSR (3): Machine software interrupt enable (r/w) */ |
CPU_MIE_MTIE = 7, /**< CPU mie CSR (7): Machine timer interrupt (MTIME) enable bit (r/w) */ |
CPU_MIE_MEIE = 11 /**< CPU mie CSR (11): Machine external interrupt (via CLIC) enable bit (r/w) */ |
}; |
116,10 → 111,10
|
|
/**********************************************************************//** |
* CPU <b>mip</b> CSR (r/w): Machine interrupt pending (RISC-V spec.) |
* CPU <b>mip</b> CSR (r/-): Machine interrupt pending (RISC-V spec.) |
**************************************************************************/ |
enum NEORV32_CPU_MIP_enum { |
CPU_MIP_MSIP = 3, /**< CPU mip CSR (3): Machine software interrupt pending (r/w), can be triggered when set */ |
CPU_MIP_MSIP = 3, /**< CPU mip CSR (3): Machine software interrupt pending (r/-) */ |
CPU_MIP_MTIP = 7, /**< CPU mip CSR (7): Machine timer interrupt (MTIME) pending (r/-) */ |
CPU_MIP_MEIP = 11 /**< CPU mip CSR (11): Machine external interrupt (via CLIC) pending (r/-) */ |
}; |
141,30 → 136,6
|
|
/**********************************************************************//** |
* CPU <b>mfeatures</b> CSR (r/-): Implemented processor devices/features (CUSTOM) |
**************************************************************************/ |
enum NEORV32_CPU_MFEATURES_enum { |
CPU_MFEATURES_BOOTLOADER = 0, /**< CPU mfeatures CSR (0) (r/-): Bootloader implemented when 1 (via BOOTLOADER_USE generic) */ |
CPU_MFEATURES_MEM_EXT = 1, /**< CPU mfeatures CSR (1) (r/-): External bus interface implemented when 1 (via MEM_EXT_USE generic) */ |
CPU_MFEATURES_MEM_INT_IMEM = 2, /**< CPU mfeatures CSR (2) (r/-): Processor-internal instruction memory implemented when 1 (via MEM_INT_IMEM_USE generic) */ |
CPU_MFEATURES_MEM_INT_IMEM_ROM = 3, /**< CPU mfeatures CSR (3) (r/-): Processor-internal instruction memory implemented as ROM when 1 (via MEM_INT_IMEM_ROM generic) */ |
CPU_MFEATURES_MEM_INT_DMEM = 4, /**< CPU mfeatures CSR (4) (r/-): Processor-internal data memory implemented when 1 (via MEM_INT_DMEM_USE generic) */ |
CPU_MFEATURES_CSR_COUNTERS = 5, /**< CPU mfeatures CSR (5) (r/-): RISC-V performance counters implemented when 1 (via CSR_COUNTERS_USE generic) */ |
|
CPU_MFEATURES_IO_GPIO = 16, /**< CPU mfeatures CSR (16) (r/-): General purpose input/output port unit implemented when 1 (via IO_GPIO_USE generic) */ |
CPU_MFEATURES_IO_MTIME = 17, /**< CPU mfeatures CSR (17) (r/-): Machine system timer implemented when 1 (via IO_MTIME_USE generic) */ |
CPU_MFEATURES_IO_UART = 18, /**< CPU mfeatures CSR (18) (r/-): Universal asynchronous receiver/transmitter implemented when 1 (via IO_UART_USE generic) */ |
CPU_MFEATURES_IO_SPI = 19, /**< CPU mfeatures CSR (19) (r/-): Serial peripheral interface implemented when 1 (via IO_SPI_USE generic) */ |
CPU_MFEATURES_IO_TWI = 20, /**< CPU mfeatures CSR (20) (r/-): Two-wire interface implemented when 1 (via IO_TWI_USE generic) */ |
CPU_MFEATURES_IO_PWM = 21, /**< CPU mfeatures CSR (21) (r/-): Pulse-width modulation unit implemented when 1 (via IO_PWM_USE generic) */ |
CPU_MFEATURES_IO_WDT = 22, /**< CPU mfeatures CSR (22) (r/-): Watchdog timer implemented when 1 (via IO_WDT_USE generic) */ |
CPU_MFEATURES_IO_CLIC = 23, /**< CPU mfeatures CSR (23) (r/-): Core-local interrupt controller implemented when 1 (via IO_CLIC_USE generic) */ |
CPU_MFEATURES_IO_TRNG = 24, /**< CPU mfeatures CSR (24) (r/-): True random number generator implemented when 1 (via IO_TRNG_USE generic) */ |
CPU_MFEATURES_IO_DEVNULL = 25 /**< CPU mfeatures CSR (24) (r/-): Dummy device implemented when 1 (via IO_DEVNULL_USE generic) */ |
}; |
|
|
/**********************************************************************//** |
* Exception IDs. |
**************************************************************************/ |
enum NEORV32_EXCEPTION_IDS_enum { |
184,6 → 155,25
|
|
/**********************************************************************//** |
* Exception codes from mcause CSR. |
**************************************************************************/ |
enum NEORV32_EXCEPTION_CODES_enum { |
EXCCODE_I_MISALIGNED = 0x00000000, /**< 0: Instruction address misaligned */ |
EXCCODE_I_ACCESS = 0x00000001, /**< 1: Instruction (bus) access fault */ |
EXCCODE_I_ILLEGAL = 0x00000002, /**< 2: Illegal instruction */ |
EXCCODE_BREAKPOINT = 0x00000003, /**< 3: Breakpoint (EBREAK instruction) */ |
EXCCODE_L_MISALIGNED = 0x00000004, /**< 4: Load address misaligned */ |
EXCCODE_L_ACCESS = 0x00000005, /**< 5: Load (bus) access fault */ |
EXCCODE_S_MISALIGNED = 0x00000006, /**< 6: Store address misaligned */ |
EXCCODE_S_ACCESS = 0x00000007, /**< 7: Store (bus) access fault */ |
EXCCODE_MENV_CALL = 0x0000000b, /**< 11: Environment call from machine mode (ECALL instruction) */ |
EXCCODE_MSI = 0x80000003, /**< 16 + 3: Machine software interrupt */ |
EXCCODE_MTI = 0x80000007, /**< 16 + 7: Machine timer interrupt (via MTIME) */ |
EXCCODE_MEI = 0x8000000b /**< 16 + 11: Machine external interrupt (via CLIC) */ |
}; |
|
|
/**********************************************************************//** |
* Processor clock prescalers |
**************************************************************************/ |
enum NEORV32_CLOCK_PRSC_enum { |
512,10 → 502,56
**************************************************************************/ |
/**@{*/ |
/** DEVNULL data register (r/w) */ |
#define DEVNULL_DATA (*(IO_REG32 0xFFFFFFFCUL)) |
#define DEVNULL_DATA (*(IO_REG32 0xFFFFFFC8UL)) |
/**@}*/ |
|
|
/**********************************************************************//** |
* @name IO Device: System Configuration Info Memory (SYSINFO) |
**************************************************************************/ |
/**@{*/ |
/** SYSINFO(0): Clock speed */ |
#define SYSINFO_CLK (*(IO_ROM32 0xFFFFFFE0UL)) |
/** SYSINFO(1): Custom user code (via "USER_CODE" generic) */ |
#define SYSINFO_USER_CODE (*(IO_ROM32 0xFFFFFFE4UL)) |
/** SYSINFO(2): Clock speed */ |
#define SYSINFO_FEATURES (*(IO_ROM32 0xFFFFFFE8UL)) |
/** SYSINFO(3): reserved */ |
#define SYSINFO_reserved1 (*(IO_ROM32 0xFFFFFFECUL)) |
/** SYSINFO(4): Instruction memory address space base */ |
#define SYSINFO_ISPACE_BASE (*(IO_ROM32 0xFFFFFFF0UL)) |
/** SYSINFO(5): Data memory address space base */ |
#define SYSINFO_DSPACE_BASE (*(IO_ROM32 0xFFFFFFF4UL)) |
/** SYSINFO(6): Instruction memory address space size in bytes */ |
#define SYSINFO_ISPACE_SIZE (*(IO_ROM32 0xFFFFFFF8UL)) |
/** SYSINFO(7): Data memory address space size in bytes */ |
#define SYSINFO_DSPACE_SIZE (*(IO_ROM32 0xFFFFFFFCUL)) |
/**@}*/ |
|
|
/**********************************************************************//** |
* SYSINFO_FEATURES (r/-): Implemented processor devices/features |
**************************************************************************/ |
enum NEORV32_SYSINFO_FEATURES_enum { |
SYSINFO_FEATURES_BOOTLOADER = 0, /**< SYSINFO_FEATURES (0) (r/-): Bootloader implemented when 1 (via BOOTLOADER_USE generic) */ |
SYSINFO_FEATURES_MEM_EXT = 1, /**< SYSINFO_FEATURES (1) (r/-): External bus interface implemented when 1 (via MEM_EXT_USE generic) */ |
SYSINFO_FEATURES_MEM_INT_IMEM = 2, /**< SYSINFO_FEATURES (2) (r/-): Processor-internal instruction memory implemented when 1 (via MEM_INT_IMEM_USE generic) */ |
SYSINFO_FEATURES_MEM_INT_IMEM_ROM = 3, /**< SYSINFO_FEATURES (3) (r/-): Processor-internal instruction memory implemented as ROM when 1 (via MEM_INT_IMEM_ROM generic) */ |
SYSINFO_FEATURES_MEM_INT_DMEM = 4, /**< SYSINFO_FEATURES (4) (r/-): Processor-internal data memory implemented when 1 (via MEM_INT_DMEM_USE generic) */ |
|
SYSINFO_FEATURES_IO_GPIO = 16, /**< SYSINFO_FEATURES (16) (r/-): General purpose input/output port unit implemented when 1 (via IO_GPIO_USE generic) */ |
SYSINFO_FEATURES_IO_MTIME = 17, /**< SYSINFO_FEATURES (17) (r/-): Machine system timer implemented when 1 (via IO_MTIME_USE generic) */ |
SYSINFO_FEATURES_IO_UART = 18, /**< SYSINFO_FEATURES (18) (r/-): Universal asynchronous receiver/transmitter implemented when 1 (via IO_UART_USE generic) */ |
SYSINFO_FEATURES_IO_SPI = 19, /**< SYSINFO_FEATURES (19) (r/-): Serial peripheral interface implemented when 1 (via IO_SPI_USE generic) */ |
SYSINFO_FEATURES_IO_TWI = 20, /**< SYSINFO_FEATURES (20) (r/-): Two-wire interface implemented when 1 (via IO_TWI_USE generic) */ |
SYSINFO_FEATURES_IO_PWM = 21, /**< SYSINFO_FEATURES (21) (r/-): Pulse-width modulation unit implemented when 1 (via IO_PWM_USE generic) */ |
SYSINFO_FEATURES_IO_WDT = 22, /**< SYSINFO_FEATURES (22) (r/-): Watchdog timer implemented when 1 (via IO_WDT_USE generic) */ |
SYSINFO_FEATURES_IO_CLIC = 23, /**< SYSINFO_FEATURES (23) (r/-): Core-local interrupt controller implemented when 1 (via IO_CLIC_USE generic) */ |
SYSINFO_FEATURES_IO_TRNG = 24, /**< SYSINFO_FEATURES (24) (r/-): True random number generator implemented when 1 (via IO_TRNG_USE generic) */ |
SYSINFO_FEATURES_IO_DEVNULL = 25 /**< SYSINFO_FEATURES (24) (r/-): Dummy device implemented when 1 (via IO_DEVNULL_USE generic) */ |
}; |
|
|
// ---------------------------------------------------------------------------- |
// Include all IO driver headers |
// ---------------------------------------------------------------------------- |
/neorv32/trunk/sw/lib/include/neorv32_cpu.h
45,6 → 45,11
// prototypes |
int neorv32_cpu_irq_enable(uint8_t irq_sel); |
int neorv32_cpu_irq_disable(uint8_t irq_sel); |
uint64_t neorv32_cpu_get_cycle(void); |
void neorv32_cpu_set_mcycle(uint64_t value); |
uint64_t neorv32_cpu_get_instret(void); |
void neorv32_cpu_set_minstret(uint64_t value); |
uint64_t neorv32_cpu_get_systime(void); |
void neorv32_cpu_delay_ms(uint32_t time_ms); |
|
|
113,23 → 118,6
|
|
/**********************************************************************//** |
* Trigger machine software interrupt. |
* |
* @note The according IRQ has to be enabled via neorv32_cpu_irq_enable(uint8_t irq_sel) and |
* global interrupts must be enabled via neorv32_cpu_eint(void) to trigger an IRQ via software. |
* The MSI becomes active after 3 clock cycles. |
**************************************************************************/ |
inline void __attribute__ ((always_inline)) neorv32_cpu_sw_irq(void) { |
|
asm volatile ("csrrsi zero, mip, %0" : : "i" (1 << CPU_MIP_MSIP)); |
|
// the MSI becomes active 3 clock cycles afters issueing |
asm volatile ("nop"); // these nops are not required, they just make sure the MSI becomes active |
asm volatile ("nop"); // before the "real" next operation is executed |
} |
|
|
/**********************************************************************//** |
* Trigger breakpoint exception (via EBREAK instruction). |
**************************************************************************/ |
inline void __attribute__ ((always_inline)) neorv32_cpu_breakpoint(void) { |
/neorv32/trunk/sw/lib/include/neorv32_rte.h
48,6 → 48,7
int neorv32_rte_exception_uninstall(uint8_t exc_id); |
|
void neorv32_rte_print_hw_config(void); |
void neorv32_rte_print_hw_version(void); |
void neorv32_rte_print_credits(void); |
|
#endif // neorv32_rte_h |
/neorv32/trunk/sw/lib/source/neorv32_clic.c
61,7 → 61,7
**************************************************************************/ |
int neorv32_clic_available(void) { |
|
if (neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_IO_CLIC)) { |
if (SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_IO_CLIC)) { |
return 1; |
} |
else { |
/neorv32/trunk/sw/lib/source/neorv32_cpu.c
49,7 → 49,7
* @note Interrupts have to be globally enabled via neorv32_cpu_eint(void), too. |
* |
* @param[in] irq_sel CPU interrupt select. See #NEORV32_CPU_MIE_enum. |
* return 0 if success, 1 if error (invalid irq_sel). |
* @return 0 if success, 1 if error (invalid irq_sel). |
**************************************************************************/ |
int neorv32_cpu_irq_enable(uint8_t irq_sel) { |
|
67,7 → 67,7
* Disable specific CPU interrupt. |
* |
* @param[in] irq_sel CPU interrupt select. See #NEORV32_CPU_MIE_enum. |
* return 0 if success, 1 if error (invalid irq_sel). |
* @return 0 if success, 1 if error (invalid irq_sel). |
**************************************************************************/ |
int neorv32_cpu_irq_disable(uint8_t irq_sel) { |
|
82,6 → 82,139
|
|
/**********************************************************************//** |
* Get cycle count from cycle[h]. |
* |
* @note The cycle[h] CSR is shadowed copy of the mcycle[h] CSR. |
* |
* @return Current cycle counter (64 bit). |
**************************************************************************/ |
uint64_t neorv32_cpu_get_cycle(void) { |
|
union { |
uint64_t uint64; |
uint32_t uint32[sizeof(uint64_t)/2]; |
} cycles; |
|
uint32_t tmp1, tmp2, tmp3; |
while(1) { |
tmp1 = neorv32_cpu_csr_read(CSR_CYCLEH); |
tmp2 = neorv32_cpu_csr_read(CSR_CYCLE); |
tmp3 = neorv32_cpu_csr_read(CSR_CYCLEH); |
if (tmp1 == tmp3) { |
break; |
} |
} |
|
cycles.uint32[0] = tmp2; |
cycles.uint32[1] = tmp3; |
|
return cycles.uint64; |
} |
|
|
/**********************************************************************//** |
* Set mcycle[h] counter. |
* |
* @param[in] value New value for mcycle[h] CSR (64-bit). |
**************************************************************************/ |
void neorv32_cpu_set_mcycle(uint64_t value) { |
|
union { |
uint64_t uint64; |
uint32_t uint32[sizeof(uint64_t)/2]; |
} cycles; |
|
cycles.uint64 = value; |
|
neorv32_cpu_csr_write(CSR_MCYCLE, 0); |
neorv32_cpu_csr_write(CSR_MCYCLEH, cycles.uint32[1]); |
neorv32_cpu_csr_write(CSR_MCYCLE, cycles.uint32[0]); |
} |
|
|
/**********************************************************************//** |
* Get retired instructions counter from instret[h]. |
* |
* @note The instret[h] CSR is shadowed copy of the instret[h] CSR. |
* |
* @return Current instructions counter (64 bit). |
**************************************************************************/ |
uint64_t neorv32_cpu_get_instret(void) { |
|
union { |
uint64_t uint64; |
uint32_t uint32[sizeof(uint64_t)/2]; |
} cycles; |
|
uint32_t tmp1, tmp2, tmp3; |
while(1) { |
tmp1 = neorv32_cpu_csr_read(CSR_INSTRETH); |
tmp2 = neorv32_cpu_csr_read(CSR_INSTRET); |
tmp3 = neorv32_cpu_csr_read(CSR_INSTRETH); |
if (tmp1 == tmp3) { |
break; |
} |
} |
|
cycles.uint32[0] = tmp2; |
cycles.uint32[1] = tmp3; |
|
return cycles.uint64; |
} |
|
|
/**********************************************************************//** |
* Set retired instructions counter minstret[h]. |
* |
* @param[in] value New value for mcycle[h] CSR (64-bit). |
**************************************************************************/ |
void neorv32_cpu_set_minstret(uint64_t value) { |
|
union { |
uint64_t uint64; |
uint32_t uint32[sizeof(uint64_t)/2]; |
} cycles; |
|
cycles.uint64 = value; |
|
neorv32_cpu_csr_write(CSR_MINSTRET, 0); |
neorv32_cpu_csr_write(CSR_MINSTRETH, cycles.uint32[1]); |
neorv32_cpu_csr_write(CSR_MINSTRET, cycles.uint32[0]); |
} |
|
|
/**********************************************************************//** |
* Get current system time from time[h] CSR. |
* |
* @note This function requires the MTIME system timer to be implemented. |
* |
* @return Current system time (64 bit). |
**************************************************************************/ |
uint64_t neorv32_cpu_get_systime(void) { |
|
union { |
uint64_t uint64; |
uint32_t uint32[sizeof(uint64_t)/2]; |
} cycles; |
|
uint32_t tmp1, tmp2, tmp3; |
while(1) { |
tmp1 = neorv32_cpu_csr_read(CSR_TIMEH); |
tmp2 = neorv32_cpu_csr_read(CSR_TIME); |
tmp3 = neorv32_cpu_csr_read(CSR_TIMEH); |
if (tmp1 == tmp3) { |
break; |
} |
} |
|
cycles.uint32[0] = tmp2; |
cycles.uint32[1] = tmp3; |
|
return cycles.uint64; |
} |
|
|
/**********************************************************************//** |
* Simple delay function (not very precise) using busy wait. |
* |
* @param[in] time_ms Time in ms to wait. |
88,7 → 221,7
**************************************************************************/ |
void neorv32_cpu_delay_ms(uint32_t time_ms) { |
|
uint32_t clock_speed = neorv32_cpu_csr_read(CSR_MCLOCK) >> 10; // fake divide by 1000 |
uint32_t clock_speed = SYSINFO_CLK >> 10; // fake divide by 1000 |
clock_speed = clock_speed >> 5; // divide by loop execution time (~30 cycles) |
uint32_t cnt = clock_speed * time_ms; |
|
/neorv32/trunk/sw/lib/source/neorv32_gpio.c
52,7 → 52,7
**************************************************************************/ |
int neorv32_gpio_available(void) { |
|
if (neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_IO_GPIO)) { |
if (SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_IO_GPIO)) { |
return 1; |
} |
else { |
/neorv32/trunk/sw/lib/source/neorv32_mtime.c
52,7 → 52,7
**************************************************************************/ |
int neorv32_mtime_available(void) { |
|
if (neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_IO_MTIME)) { |
if (SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_IO_MTIME)) { |
return 1; |
} |
else { |
70,7 → 70,17
**************************************************************************/ |
void neorv32_mtime_set_time(uint64_t time) { |
|
MTIME = time; |
union { |
uint64_t uint64; |
uint32_t uint32[sizeof(uint64_t)/2]; |
} cycles; |
|
cycles.uint64 = time; |
|
MTIME_LO = 0; |
MTIME_HI = cycles.uint32[1]; |
MTIME_LO = cycles.uint32[0]; |
|
} |
|
|
83,7 → 93,25
**************************************************************************/ |
uint64_t neorv32_mtime_get_time(void) { |
|
return MTIME; |
union { |
uint64_t uint64; |
uint32_t uint32[sizeof(uint64_t)/2]; |
} cycles; |
|
uint32_t tmp1, tmp2, tmp3; |
while(1) { |
tmp1 = MTIME_HI; |
tmp2 = MTIME_LO; |
tmp3 = MTIME_HI; |
if (tmp1 == tmp3) { |
break; |
} |
} |
|
cycles.uint32[0] = tmp2; |
cycles.uint32[1] = tmp3; |
|
return cycles.uint64; |
} |
|
|
/neorv32/trunk/sw/lib/source/neorv32_pwm.c
52,7 → 52,7
**************************************************************************/ |
int neorv32_pwm_available(void) { |
|
if (neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_IO_PWM)) { |
if (SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_IO_PWM)) { |
return 1; |
} |
else { |
/neorv32/trunk/sw/lib/source/neorv32_rte.c
46,7 → 46,6
static void __neorv32_rte_dummy_exc_handler(void) __attribute__((unused)); |
static void __neorv32_rte_debug_exc_handler(void) __attribute__((unused)); |
static void __neorv32_rte_print_true_false(int state) __attribute__((unused)); |
static void __neorv32_rte_print_hw_version(void) __attribute__((unused)); |
|
|
/**********************************************************************//** |
94,7 → 93,7
if (exc_id == EXCID_MTI) { neorv32_cpu_irq_enable(CPU_MIE_MTIE); } // activate timer interrupt |
if (exc_id == EXCID_MEI) { neorv32_cpu_irq_enable(CPU_MIE_MEIE); } // activate external interrupt |
|
uint32_t vt_base = neorv32_cpu_csr_read(CSR_MDSPACEBASE); // base address of vector table |
uint32_t vt_base = SYSINFO_DSPACE_BASE; // base address of vector table |
vt_base = vt_base + (((uint32_t)exc_id) << 2); |
(*(IO_REG32 (vt_base))) = (uint32_t)handler; |
|
127,7 → 126,7
if (exc_id == EXCID_MTI) { neorv32_cpu_irq_disable(CPU_MIE_MTIE); } // deactivate timer interrupt |
if (exc_id == EXCID_MEI) { neorv32_cpu_irq_disable(CPU_MIE_MEIE); } // deactivate external interrupt |
|
uint32_t vt_base = neorv32_cpu_csr_read(CSR_MDSPACEBASE); // base address of vector table |
uint32_t vt_base = SYSINFO_DSPACE_BASE; // base address of vector table |
vt_base = vt_base + (((uint32_t)exc_id) << 2); |
(*(IO_REG32 (vt_base))) = (uint32_t)(&__neorv32_rte_dummy_exc_handler); // use dummy handler in case the exception is triggered |
|
161,9 → 160,9
register uint32_t trap_addr = neorv32_cpu_csr_read(CSR_MEPC); |
register uint32_t trap_inst; |
|
// get faulting instruction |
asm volatile ("lh %[result], 0(%[input_i])" : [result] "=r" (trap_inst) : [input_i] "r" (trap_addr)); |
|
|
if (trap_cause & 0x80000000) { |
neorv32_uart_printf("INTERRUPT"); |
} |
196,7 → 195,7
} |
|
// fault address |
neorv32_uart_printf("\nFaulting instruction: 0x%x\n", trap_inst); |
neorv32_uart_printf("\nFaulting instruction (low): 0x%x\n", trap_inst); |
neorv32_uart_printf("MTVAL: 0x%x\n", neorv32_cpu_csr_read(CSR_MTVAL)); |
|
if ((trap_inst & 3) != 3) { |
224,11 → 223,14
neorv32_uart_printf("\n-- Central Processing Unit --\n"); |
|
// Hart ID |
neorv32_uart_printf("Hart ID: 0x%x\n", neorv32_cpu_csr_read(CSR_MHARTID)); |
neorv32_uart_printf("Hart ID: %u\n", neorv32_cpu_csr_read(CSR_MHARTID)); |
|
// Custom user code |
neorv32_uart_printf("User code: 0x%x\n", SYSINFO_USER_CODE); |
|
// HW version |
neorv32_uart_printf("Hardware version: "); |
__neorv32_rte_print_hw_version(); |
neorv32_rte_print_hw_version(); |
neorv32_uart_printf(" (0x%x)\n", neorv32_cpu_csr_read(CSR_MIMPID)); |
|
// CPU architecture |
260,69 → 262,65
} |
neorv32_uart_printf("(0x%x)\n", tmp); |
|
// Performance counters |
neorv32_uart_printf("CNT & time CSRs: "); |
__neorv32_rte_print_true_false(neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_CSR_COUNTERS)); |
|
// Clock speed |
neorv32_uart_printf("Clock speed: %u Hz\n", neorv32_cpu_csr_read(CSR_MCLOCK)); |
neorv32_uart_printf("Clock speed: %u Hz\n", SYSINFO_CLK); |
|
// Memory configuration |
neorv32_uart_printf("\n-- Memory Configuration --\n"); |
|
uint32_t size = neorv32_cpu_csr_read(CSR_MISPACESIZE); |
uint32_t base = neorv32_cpu_csr_read(CSR_MISPACEBASE); |
uint32_t size = SYSINFO_ISPACE_SIZE; |
uint32_t base = SYSINFO_ISPACE_BASE; |
neorv32_uart_printf("Instruction memory: %u bytes @ 0x%x\n", size, base); |
neorv32_uart_printf("Internal IMEM: "); |
__neorv32_rte_print_true_false(neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_MEM_INT_IMEM)); |
__neorv32_rte_print_true_false(SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_MEM_INT_IMEM)); |
neorv32_uart_printf("Internal IMEM as ROM: "); |
__neorv32_rte_print_true_false(neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_MEM_INT_IMEM_ROM)); |
__neorv32_rte_print_true_false(SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_MEM_INT_IMEM_ROM)); |
|
size = neorv32_cpu_csr_read(CSR_MDSPACESIZE); |
base = neorv32_cpu_csr_read(CSR_MDSPACEBASE); |
size = SYSINFO_DSPACE_SIZE; |
base = SYSINFO_DSPACE_BASE; |
neorv32_uart_printf("Data memory: %u bytes @ 0x%x\n", size, base); |
neorv32_uart_printf("Internal DMEM: "); |
__neorv32_rte_print_true_false(neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_MEM_INT_DMEM)); |
__neorv32_rte_print_true_false(SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_MEM_INT_DMEM)); |
|
neorv32_uart_printf("Bootloader: "); |
__neorv32_rte_print_true_false(neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_BOOTLOADER)); |
__neorv32_rte_print_true_false(SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_BOOTLOADER)); |
|
neorv32_uart_printf("External interface: "); |
__neorv32_rte_print_true_false(neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_MEM_EXT)); |
__neorv32_rte_print_true_false(SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_MEM_EXT)); |
|
// peripherals |
neorv32_uart_printf("\n-- Peripherals --\n"); |
tmp = neorv32_cpu_csr_read(CSR_MFEATURES); |
tmp = SYSINFO_FEATURES; |
|
neorv32_uart_printf("GPIO: "); |
__neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_GPIO)); |
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_GPIO)); |
|
neorv32_uart_printf("MTIME: "); |
__neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_MTIME)); |
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_MTIME)); |
|
neorv32_uart_printf("UART: "); |
__neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_UART)); |
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_UART)); |
|
neorv32_uart_printf("SPI: "); |
__neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_SPI)); |
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_SPI)); |
|
neorv32_uart_printf("TWI: "); |
__neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_TWI)); |
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_TWI)); |
|
neorv32_uart_printf("PWM: "); |
__neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_PWM)); |
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_PWM)); |
|
neorv32_uart_printf("WDT: "); |
__neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_WDT)); |
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_WDT)); |
|
neorv32_uart_printf("CLIC: "); |
__neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_CLIC)); |
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_CLIC)); |
|
neorv32_uart_printf("TRNG: "); |
__neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_TRNG)); |
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_TRNG)); |
|
neorv32_uart_printf("DEVNULL: "); |
__neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_DEVNULL)); |
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_DEVNULL)); |
} |
|
|
344,10 → 342,9
|
|
/**********************************************************************//** |
* NEORV32 runtime environment: Private function to show the processor version in human-readable format. |
* @note This function is used by neorv32_rte_print_hw_config(void) only. |
* NEORV32 runtime environment: Function to show the processor version in human-readable format. |
**************************************************************************/ |
static void __neorv32_rte_print_hw_version(void) { |
void neorv32_rte_print_hw_version(void) { |
|
uint32_t i; |
char tmp, cnt; |
/neorv32/trunk/sw/lib/source/neorv32_spi.c
52,7 → 52,7
**************************************************************************/ |
int neorv32_spi_available(void) { |
|
if (neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_IO_SPI)) { |
if (SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_IO_SPI)) { |
return 1; |
} |
else { |
/neorv32/trunk/sw/lib/source/neorv32_trng.c
52,7 → 52,7
**************************************************************************/ |
int neorv32_trng_available(void) { |
|
if (neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_IO_TRNG)) { |
if (SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_IO_TRNG)) { |
return 1; |
} |
else { |
/neorv32/trunk/sw/lib/source/neorv32_twi.c
52,7 → 52,7
**************************************************************************/ |
int neorv32_twi_available(void) { |
|
if (neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_IO_TWI)) { |
if (SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_IO_TWI)) { |
return 1; |
} |
else { |
/neorv32/trunk/sw/lib/source/neorv32_uart.c
59,7 → 59,7
**************************************************************************/ |
int neorv32_uart_available(void) { |
|
if (neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_IO_UART)) { |
if (SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_IO_UART)) { |
return 1; |
} |
else { |
80,7 → 80,7
UART_CT = 0; // reset |
|
// raw baud rate prescaler |
uint32_t clock = neorv32_cpu_csr_read(CSR_MCLOCK); |
uint32_t clock = SYSINFO_CLK; |
uint16_t i = 0; // BAUD rate divisor |
uint8_t p = 0; // prsc = CLK/2 |
while (clock >= 2*baudrate) { |
/neorv32/trunk/sw/lib/source/neorv32_wdt.c
52,7 → 52,7
**************************************************************************/ |
int neorv32_wdt_available(void) { |
|
if (neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_IO_WDT)) { |
if (SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_IO_WDT)) { |
return 1; |
} |
else { |
/neorv32/trunk/.travis.yml
32,7 → 32,7
docker run -t -v `pwd`:/mnt/data ghdl/ghdl:buster-gcc-8.3.0 |
/bin/bash -c "chmod u+x /mnt/data/.ci/hw_check.sh && /mnt/data/.ci/hw_check.sh" |
|
# Generate and deploy documentation |
# Deploy documentation |
deploy: |
provider: pages |
skip_cleanup: true |
/neorv32/trunk/README.md
22,7 → 22,7
|
The NEORV32 is a customizable full-scale mikrocontroller-like processor system based on a [RISC-V-compliant](https://github.com/stnolting/neorv32_riscv_compliance) |
`rv32i` CPU with optional `E`, `C`, `M`, `Zicsr` and `Zifencei` extensions. The CPU was built from scratch and is compliant to the **Unprivileged |
ISA Specification Version 2.1** and a subset of the **Privileged Architecture Specification Version 1.12-draft**. |
ISA Specification Version 2.2** and a subset of the **Privileged Architecture Specification Version 1.12-draft**. |
|
The NEORV32 is intended as auxiliary processor within a larger SoC designs or as stand-alone custom microcontroller. |
Its top entity can be directly synthesized for any FPGA without modifications and provides a full-scale RISC-V based microcontroller. |
61,25 → 61,28
| Project component | CI status | Note | |
|:--------------------------------------------------------------------------------|:----------|:---------| |
| [NEORV32 processor](https://github.com/stnolting/neorv32) | [](https://travis-ci.com/stnolting/neorv32) | [](https://stnolting.github.io/neorv32/files.html) | |
| [Pre-build toolchain](https://github.com/stnolting/riscv_gcc_prebuilt) | [](https://travis-ci.com/stnolting/riscv_gcc_prebuilt) | | |
| [Pre-built toolchain](https://github.com/stnolting/riscv_gcc_prebuilt) | [](https://travis-ci.com/stnolting/riscv_gcc_prebuilt) | | |
| [RISC-V compliance test](https://github.com/stnolting/neorv32_riscv_compliance) | [](https://travis-ci.com/stnolting/neorv32_riscv_compliance) | | |
|
|
### Limitations to be fixed |
### Non RISC-V-Compliant Issues |
|
* No exception is triggered in `E`-mode when using registers above `x15` yet |
* `misa` CSR is read-only; no dynamic enabling/disabling of implemented CPU extensions during runtime |
* No exception is triggered in `E` mode when using registers above `x15` (*needs fixing*) |
* `misa` CSR is read-only - no dynamic enabling/disabling of implemented CPU extensions during runtime |
* Machine software interrupt `msi` is implemented, but there is no mechanism available to trigger it |
* The `[m]cycleh` and `[m]instreth` CSR counters are only 20-bit wide (in contrast to original 32-bit) |
|
|
### To-Do / Wish List |
|
- Option to use DSPs for multiplications in `M` extensions (would be so much faster) |
- Synthesis results for more platforms |
- Port Dhrystone benchmark |
- Implement atomic operations (`A` extension) |
- Implement co-processor for single-precision floating-point operations (`F` extension) |
- Implement user mode (`U` extension) |
- Maybe port an RTOS (like [freeRTOS](https://www.freertos.org/) or [RIOT](https://www.riot-os.org/)) |
- Make a 64-bit branch |
- Maybe port an RTOS (like [freeRTOS](https://www.freertos.org/) or [RIOT](https://www.riot-os.org/)) |
|
|
|
98,7 → 101,7
- Fully synchronous design, no latches, no gated clocks |
- Small hardware footprint and high operating frequency |
- Highly customizable processor configuration |
- Optional processor-internal data and instruction memories (DMEM/IMEM) |
- _Optional_ processor-internal data and instruction memories (DMEM/IMEM) |
- _Optional_ internal bootloader with UART console and automatic SPI flash boot option |
- _Optional_ machine system timer (MTIME), RISC-V-compliant |
- _Optional_ universal asynchronous receiver and transmitter (UART) |
111,6 → 114,7
- _Optional_ GARO-based true random number generator (TRNG) |
- _Optional_ core-local interrupt controller with 8 channels (CLIC) |
- _Optional_ dummy device (DEVNULL) (can be used for *fast* simulation console output) |
- System configuration information memory to check hardware configuration by software (SYSINFO) |
|
### CPU Features |
|
117,8 → 121,8
 |
|
The CPU is [compliant](https://github.com/stnolting/neorv32_riscv_compliance) to the |
[official RISC-V specifications](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/riscv-spec.pdf) including a subset of the |
[RISC-V privileged architecture specifications](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/riscv-spec.pdf). |
[official RISC-V specifications (2.2)](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/riscv-spec.pdf) including a subset of the |
[RISC-V privileged architecture specifications (1.12-draft)](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/riscv-spec.pdf). |
|
More information regarding the CPU including a detailed list of the instruction set and the available CSRs can be found in |
the [ NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf). |
125,8 → 129,9
|
|
**General**: |
* Modified Harvard architecture (separate CPU interfaces for data and instructions; single processor-bus via bus switch) |
* Two stages in-order pipeline (FETCH, EXECUTE); each stage uses a multi-cycle processing scheme |
* No hardware support of unaligned accesses - they will trigger and exception |
* Two stages in-order pipeline (FETCH, EXECUTE); each stage uses a multi-cycle processing scheme |
|
|
**RV32I base instruction set** (`I` extension): |
143,7 → 148,6
|
**Embedded CPU version** (`E` extension): |
* Reduced register file (only the 16 lowest registers) |
* No performance counter CSRs |
|
**Integer multiplication and division hardware** (`M` extension): |
* Multiplication instructions: `MUL` `MULH` `MULHSU` `MULHU` |
153,9 → 157,8
* Privilege levels: `M-mode` (Machine mode) |
* CSR access instructions: `CSRRW` `CSRRS` `CSRRC` `CSRRWI` `CSRRSI` `CSRRCI` |
* System instructions: `MRET` `WFI` |
* Counter CSRs: `cycle` `cycleh` `time` `timeh` `instret` `instreth` `mcycle` `mcycleh` `minstret` `minstreth` |
* Machine CSRs: `mstatus` `misa`(read-only!) `mie` `mtvec` `mscratch` `mepc` `mcause` `mtval` `mip` `mimpid` `mhartid` |
* Custom CSRs: `mfeatures` `mclock` `mispacebase` `mdspacebase` `mispacesize` `mdspacesize` |
* Counter CSRs: `[m]cycle[h]` `[m]instret[h]` `time[h]` |
* Machine CSRs: `mstatus` `misa`(read-only!) `mie` `mtvec` `mscratch` `mepc` `mcause` `mtval` `mip` `mvendorid` `marchid` `mimpid` `mhartid` |
* Supported exceptions and interrupts: |
* Misaligned instruction address |
* Instruction access fault |
166,7 → 169,6
* Store address misaligned |
* Store access fault |
* Environment call from M-mode (via `ecall` instruction) |
* Machine software interrupt `msi` |
* Machine timer interrupt `mti` (via MTIME unit) |
* Machine external interrupt `mei` (via CLIC unit) |
|
179,23 → 181,23
This chapter shows exemplary implementation results of the NEORV32 processor for an **Intel Cyclone IV EP4CE22F17C6N FPGA** on |
a DE0-nano board. The design was synthesized using **Intel Quartus Prime Lite 19.1** ("balanced implementation"). The timing |
information is derived from the Timing Analyzer / Slow 1200mV 0C Model. If not otherwise specified, the default configuration |
of the processor's generics is assumed. No constraints were used. |
of the processor's generics is assumed. No constraints were used at all. |
|
### CPU |
|
Results generated for hardware version: `1.0.0.0` |
Results generated for hardware version: `1.2.0.0` |
|
| CPU Configuration | LEs | FFs | Memory bits | DSPs | f_max | |
|:--------------------|:----------:|:--------:|:-----------:|:------:|:-------:| |
| `rv32i` | 1027 | 474 | 2048 | 0 (0%) | 111 MHz | |
| `rv32i` + `Zicsr` | 1721 | 868 | 2048 | 0 (0%) | 104 MHz | |
| `rv32im` + `Zicsr` | 2298 | 1115 | 2048 | 0 (0%) | 103 MHz | |
| `rv32imc` + `Zicsr` | 2557 | 1138 | 2048 | 0 (0%) | 103 MHz | |
| `rv32emc` + `Zicsr` | 2342 | 1005 | 1024 | 0 (0%) | 100 MHz | |
| CPU Configuration | LEs | FFs | Memory bits | DSPs | f_max | |
|:---------------------------------|:----------:|:--------:|:-----------:|:----:|:-------:| |
| `rv32i` | 1065 | 477 | 2048 | 0 | 112 MHz | |
| `rv32i` + `Zicsr` + `Zifencei` | 1914 | 837 | 2048 | 0 | 100 MHz | |
| `rv32im` + `Zicsr` + `Zifencei` | 2542 | 1085 | 2048 | 0 | 100 MHz | |
| `rv32imc` + `Zicsr` + `Zifencei` | 2806 | 1102 | 2048 | 0 | 100 MHz | |
| `rv32emc` + `Zicsr` + `Zifencei` | 2783 | 1102 | 1024 | 0 | 100 MHz | |
|
### Processor-Internal Peripherals and Memories |
|
Results generated for hardware version: `1.0.5.0` |
Results generated for hardware version: `1.2.0.0` |
|
| Module | Description | LEs | FFs | Memory bits | DSPs | |
|:---------|:------------------------------------------------|:---:|:---:|:-----------:|:----:| |
207,6 → 209,7
| MTIME | Machine system timer | 269 | 166 | 0 | 0 | |
| PWM | Pulse-width modulation controller | 76 | 69 | 0 | 0 | |
| SPI | Serial peripheral interface | 206 | 125 | 0 | 0 | |
| SYSINFO | System configuration information memory | 7 | 7 | 0 | 0 | |
| TRNG | True random number generator | 104 | 93 | 0 | 0 | |
| TWI | Two-wire interface | 78 | 44 | 0 | 0 | |
| UART | Universal asynchronous receiver/transmitter | 151 | 108 | 0 | 0 | |
216,23 → 219,22
### Exemplary FPGA Setups |
|
Exemplary implementation results for different FPGA platforms. The processor setup uses *all provided peripherals*, |
all CPU extensions (`rv32imc` + `Zicsr` + `Zifencei`, no `E` extension), no external memory interface and only internal |
instruction and data memories. IMEM uses 16kB and DMEM uses 8kB memory space. The setup top entity connects most of the |
no external memory interface and only internal instruction and data memories. IMEM uses 16kB and DMEM uses 8kB memory space. The setup's top entity connects most of the |
processor's [top entity](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_top.vhd) signals |
to FPGA pins - except for the Wishbone bus and the external interrupt signals. |
to FPGA pins - except for the Wishbone bus and the interrupt signals. |
|
Results generated for hardware version: `1.0.1.1` |
Results generated for hardware version: `1.2.0.0` |
|
| Vendor | FPGA | Board | Toolchain | Impl. strategy | LUT / LE | FF / REG | DSP | Memory Bits | BRAM / EBR | SPRAM | Frequency | |
|:--------|:----------------------------------|:-----------------|:------------------------|:---------------|:-----------|:-----------|:-------|:-------------|:-----------|:---------|------------:| |
| Intel | Cyclone IV `EP4CE22F17C6N` | Terasic DE0-Nano | Quartus Prime Lite 19.1 | balanced | 3841 (17%) | 1866 (8%) | 0 (0%) | 231424 (38%) | - | - | 103 MHz | |
| Lattice | iCE40 UltraPlus `iCE40UP5K-SG48I` | Upduino v2.0 | Radiant 2.1 (LSE) | default | 5014 (95%) | 1952 (37%) | 0 (0%) | - | 12 (40%) | 4 (100%) | c 20.25 MHz | |
| Xilinx | Artix-7 `XC7A35TICSG324-1L` | Arty A7-35T | Vivado 2019.2 | default | 2312 (11%) | 1924 (5%) | 0 (0%) | - | 8 (16%) | - | c 100 MHz | |
| Vendor | FPGA | Board | Toolchain | Impl. strategy |CPU | LUT / LE | FF / REG | DSP | Memory Bits | BRAM / EBR | SPRAM | Frequency | |
|:--------|:----------------------------------|:-----------------|:------------------------|:---------------|:---------------------------------|:-----------|:-----------|:-------|:-------------|:-----------|:---------|------------:| |
| Intel | Cyclone IV `EP4CE22F17C6N` | Terasic DE0-Nano | Quartus Prime Lite 19.1 | balanced | `rv32imc` + `Zicsr` + `Zifencei` | 4066 (18%) | 1877 (8%) | 0 (0%) | 231424 (38%) | - | - | 100 MHz | |
| Lattice | iCE40 UltraPlus `iCE40UP5K-SG48I` | Upduino v2.0 | Radiant 2.1 (LSE) | timing | `rv32ic` + `Zicsr` + `Zifencei` | 5017 (95%) | 1717 (32%) | 0 (0%) | - | 12 (40%) | 4 (100%) | c 20.25 MHz | |
| Xilinx | Artix-7 `XC7A35TICSG324-1L` | Arty A7-35T | Vivado 2019.2 | default | `rv32imc` + `Zicsr` + `Zifencei` | 2494 (12%) | 1930 (5%) | 0 (0%) | - | 8 (16%) | - | c 100 MHz | |
|
**Notes** |
* The Lattice iCE40 UltraPlus setup uses the FPGA's SPRAM memory primitives for the internal IMEM and DEMEM (each 64kb). |
The FPGA-specific memory components can be found in the [`rtl/fpga_specific`](https://github.com/stnolting/neorv32/blob/master/rtl/fpga_specific/lattice_ice40up) folder. |
* The clock frequencies marked with a "c" are constrained clocks. The remaining ones are `f_max` results from the place and route timing reports. |
The FPGA-specific memory components can be found in [`rtl/fpga_specific`](https://github.com/stnolting/neorv32/blob/master/rtl/fpga_specific/lattice_ice40up). |
* The clock frequencies marked with a "c" are constrained clocks. The remaining ones are _f_max_ results from the place and route timing reports. |
* The Upduino and the Arty board have on-board SPI flash memories for storing the FPGA configuration. These device can also be used by the default NEORV32 |
bootloader to store and automatically boot an application program after reset (both tested successfully). |
|
244,24 → 246,21
[sw/example/coremark](https://github.com/stnolting/neorv32/blob/master/sw/example/coremark) project folder. This benchmark |
tests the capabilities of a CPU itself rather than the functions provided by the whole system / SoC. |
|
Results generated for hardware version: `1.0.0.0` |
Results generated for hardware version: `1.2.0.0` |
|
~~~ |
**Configuration** |
Hardware: 32kB IMEM, 16kb DMEM, 100MHz clock |
CoreMark: 2000 iterations, MEM_METHOD is MEM_STACK |
CPU extensions: `rv32i` or `rv32im` or `rv32imc` |
Used peripherals: UART for printing the results |
Hardware: 32kB IMEM, 16kB DMEM, 100MHz clock |
CoreMark: 2000 iterations, MEM_METHOD is MEM_STACK |
Compiler: RISCV32-GCC 9.2.0 |
Peripherals: UART for printing the results |
~~~ |
|
| __Configuration__ | __Optimization__ | __Executable Size__ | __CoreMark Score__ | __CoreMarks/MHz__ | |
|:------------------|:----------------:|:-------------------:|:------------------:|:-----------------:| |
| `rv32i` | `-Os` | 18 044 bytes | 21.98 | 0.21 | |
| `rv32i` | `-O2` | 20 388 bytes | 25 | 0.25 | |
| `rv32im` | `-Os` | 16 980 bytes | 40 | 0.40 | |
| `rv32im` | `-O2` | 19 436 bytes | 51.28 | 0.51 | |
| `rv32imc` | `-Os` | 13 076 bytes | 39.22 | 0.39 | |
| `rv32imc` | `-O2` | 15 208 bytes | 50 | 0.50 | |
| CPU | Optimization | CoreMark Score | CoreMarks/MHz | |
|:---------------------------------|:------------:|:--------------:|:-------------:| |
| `rv32i` + `Zicsr` + `Zifencei` | `-O2` | 25.97 | 0.2597 | |
| `rv32im` + `Zicsr` + `Zifencei` | `-O2` | 55.55 | 0.5555 | |
| `rv32imc` + `Zicsr` + `Zifencei` | `-O2` | 54.05 | 0.5405 | |
|
|
### Instruction Cycles |
276,18 → 275,19
|
The following table shows the performance results for successfully running 2000 CoreMark |
iterations, which reflects a pretty good "real-life" work load. The average CPI is computed by |
dividing the total number of required clock cycles (all of CoreMark |
– not only the timed core) by the number of executed instructions (`instret[h]` CSRs). The executables |
were generated using optimization `-O2`. |
dividing the total number of required clock cycles (only the timed core to avoid distortion due to IO wait cycles; sampled via the `cycle[h]` CSRs) |
by the number of executed instructions (`instret[h]` CSRs). The executables were generated using optimization `-O2`. |
|
| CPU / Toolchain Config. | Required Clock Cycles | Executed Instructions | Average CPI | |
|:------------------------|----------------------:|----------------------:|:-----------:| |
| `rv32i` | 19 355 607 369 | 2 995 064 579 | 6.5 | |
| `rv32im` | 5 809 384 583 | 867 377 291 | 6.7 | |
| `rv32imc` | 5 560 220 723 | 825 898 407 | 6.7 | |
Results generated for hardware version: `1.2.0.0` |
|
| CPU | Required Clock Cycles | Executed Instructions | Average CPI | |
|:---------------------------------|----------------------:|----------------------:|:-----------:| |
| `rv32i` + `Zicsr` + `Zifencei` | 7 754 927 850 | 1 492 843 669 | 5.2 | |
| `rv32im` + `Zicsr` + `Zifencei` | 3 684 015 850 | 626 274 115 | 5.9 | |
| `rv32imc` + `Zicsr` + `Zifencei` | 3 788 220 853 | 626 274 115 | 6.0 | |
|
|
|
## Top Entity |
|
The top entity of the processor is [**neorv32_top.vhd**](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_top.vhd) (from the `rtl/core` folder). |
294,7 → 294,7
Just instantiate this file in your project and you are ready to go! All signals of this top entity are of type *std_ulogic* or *std_ulogic_vector*, respectively |
(except for the TWI signals, which are of type *std_logic*). |
|
Use the generics to configure the processor according to your needs. Each generics is initilized with the default configuration. |
Use the generics to configure the processor according to your needs. Each generic is initilized with the default configuration. |
Detailed information regarding the signals and configuration generics can be found in the [NEORV32 documentary](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf). |
|
```vhdl |
301,10 → 301,10
entity neorv32_top is |
generic ( |
-- General -- |
CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz |
HART_ID : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom hardware thread ID |
CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz |
BOOTLOADER_USE : boolean := true; -- implement processor-internal bootloader? |
CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])? |
USER_CODE : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code |
-- RISC-V CPU Extensions -- |
CPU_EXTENSION_RISCV_C : boolean := true; -- implement compressed extension? |
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension? |
352,6 → 352,9
wb_cyc_o : out std_ulogic; -- valid cycle |
wb_ack_i : in std_ulogic := '0'; -- transfer acknowledge |
wb_err_i : in std_ulogic := '0'; -- transfer error |
-- Advanced memory control signals (available if MEM_EXT_USE = true) -- |
fence_o : out std_ulogic; -- indicates an executed FENCE operation |
fencei_o : out std_ulogic; -- indicates an executed FENCEI operation |
-- GPIO (available if IO_GPIO_USE = true) -- |
gpio_o : out std_ulogic_vector(15 downto 0); -- parallel output |
gpio_i : in std_ulogic_vector(15 downto 0) := (others => '0'); -- parallel input |
419,18 → 422,18
|
### Dowload the NEORV32 and Create a Hardware Project |
|
Now its time to get the most recent version the NEORV32 Processor project from GitHub. Clone the NEORV32 repository using |
`git` from the command line (suggested for easy project updates via `git pull`): |
|
Get the sources of the NEORV32 Processor project. You can either download a [release](https://github.com/stnolting/neorv32/releases) |
or get the most recent version of this project as [`*.zip` file](https://github.com/stnolting/neorv32/archive/master.zip) or using `git clone` (suggested for easy project updates via `git pull`): |
|
$ git clone https://github.com/stnolting/neorv32.git |
|
Create a new project with your FPGA design tool of choice. Add all the `*.vhd` files from the [`rtl/core`](https://github.com/stnolting/neorv32/blob/master/rtl) |
folder to this project and add them to a **new library** called `neorv32`. |
Create a new project with your FPGA design tool of choice and add all the `*.vhd` files from the [`rtl/core`](https://github.com/stnolting/neorv32/blob/master/rtl) |
folder to this project. Make sure to add them to a **new library** called `neorv32`. |
|
You can either instantiate the [processor's top entity](https://github.com/stnolting/neorv32#top-entity) in your own project or you |
can use a simple [test setup](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates/neorv32_test_setup.vhd) (from the project's |
[`rtl/top_templates`](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates) folder) as top entity. |
This test setup instantiates the processor, implements most of the peripherals and the basic ISA. Only the UART, clock, reset and some GPIO output sginals are |
This test setup instantiates the processor and implements most of the peripherals and some ISA extensions. Only the UART, clock, reset and some GPIO output sginals are |
propagated (basically, its a FPGA "hello world" example): |
|
```vhdl |
520,7 → 523,7
|
## Legal |
|
This is project is released under the BSD 3-Clause license. No copyright infringement intended. |
This project is released under the BSD 3-Clause license. No copyright infringement intended. |
Other implied or used projects might have different licensing - see their documentation to get more information. |
|
#### Citation |
595,6 → 598,6
|
This project is not affiliated with or endorsed by the Open Source Initiative (https://www.oshwa.org / https://opensource.org). |
|
\ |
. |
|
Made with :coffee: in Hannover, Germany. |