URL
https://opencores.org/ocsvn/sardmips/sardmips/trunk
Subversion Repositories sardmips
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 11 to Rev 12
- ↔ Reverse comparison
Rev 11 → Rev 12
/branches/avendor/source/main.cpp
1,5 → 1,5
// |
// $Id: main.cpp,v 1.1 2006-01-25 16:57:56 igorloi Exp $ |
// $Id: main.cpp,v 1.1.1.1 2006-01-31 10:55:26 igorloi Exp $ |
// |
#include <systemc.h> |
#include "top_debug.h" |
/branches/avendor/source/cpu/id_stage/regfile_high.h
1,5 → 1,5
// |
// $Id: regfile_high.h,v 1.1 2006-01-25 17:00:04 igorloi Exp $ |
// $Id: regfile_high.h,v 1.1.1.1 2006-01-31 10:55:29 igorloi Exp $ |
// |
|
#ifndef _REGFILE_H |
/branches/avendor/source/cpu/mem_stage.cpp
1,5 → 1,5
//! MEM Stage module |
// |
// $Id: mem_stage.cpp,v 1.1 2006-01-25 17:00:01 igorloi Exp $ |
// $Id: mem_stage.cpp,v 1.1.1.1 2006-01-31 10:55:27 igorloi Exp $ |
// |
#include "mem_stage.h" |
/branches/avendor/source/cpu/mem_stage.h
1,6 → 1,6
//! MEM Stage module |
// |
// $Id: mem_stage.h,v 1.1 2006-01-25 17:00:01 igorloi Exp $ |
// $Id: mem_stage.h,v 1.1.1.1 2006-01-31 10:55:27 igorloi Exp $ |
// |
#ifndef _MEM_STAGE_H |
#define _MEM_STAGE_H |
/branches/avendor/source/cpu/sc_cpu.cpp
1,5 → 1,5
// |
// $Id: sc_cpu.cpp,v 1.1 2006-01-25 17:00:01 igorloi Exp $ |
// $Id: sc_cpu.cpp,v 1.1.1.1 2006-01-31 10:55:28 igorloi Exp $ |
// |
// #define _ASM_ONLY_ |
// #define _DOBRANCH_ -- should be defined in id_stage only! |
/branches/avendor/source/cpu/sc_cpu.h
1,5 → 1,5
// |
// $Id: sc_cpu.h,v 1.1 2006-01-25 17:00:01 igorloi Exp $ |
// $Id: sc_cpu.h,v 1.1.1.1 2006-01-31 10:55:28 igorloi Exp $ |
// |
|
#ifndef _SC_CPU_H |
/branches/avendor/source/cpu/cp0.cpp
1,4 → 1,4
// |
// $Id: cp0.cpp,v 1.1 2006-01-25 17:00:01 igorloi Exp $ |
// $Id: cp0.cpp,v 1.1.1.1 2006-01-31 10:55:27 igorloi Exp $ |
// |
#include "cp0.h" |
/branches/avendor/source/cpu/sc_risc.cpp
1,5 → 1,5
// |
// $Id: sc_risc.cpp,v 1.1 2006-01-25 17:00:01 igorloi Exp $ |
// $Id: sc_risc.cpp,v 1.1.1.1 2006-01-31 10:55:28 igorloi Exp $ |
// |
#include "sc_risc.h" |
|
/branches/avendor/source/cpu/cp0.h
1,6 → 1,6
|
// |
// $Id: cp0.h,v 1.1 2006-01-25 17:00:01 igorloi Exp $ |
// $Id: cp0.h,v 1.1.1.1 2006-01-31 10:55:27 igorloi Exp $ |
// |
|
#ifndef _CP0_H |
/branches/avendor/source/cpu/pc_stage.h
1,5 → 1,5
// |
// $Id: pc_stage.h,v 1.1 2006-01-25 17:00:01 igorloi Exp $ |
// $Id: pc_stage.h,v 1.1.1.1 2006-01-31 10:55:28 igorloi Exp $ |
// |
#ifndef _PC_STAGE_H |
#define _PC_STAGE_H |
/branches/avendor/source/cpu/sc_risc.h
1,5 → 1,5
// |
// $Id: sc_risc.h,v 1.1 2006-01-25 17:00:01 igorloi Exp $ |
// $Id: sc_risc.h,v 1.1.1.1 2006-01-31 10:55:28 igorloi Exp $ |
// |
#ifndef _SC_RISC_H |
#define _SC_RISC_H |
/branches/avendor/source/memory/memory2.cpp
1,6 → 1,6
//! Memory model for 5-stage version of MIPS |
// |
// $Id: memory2.cpp,v 1.1 2006-01-25 17:00:11 igorloi Exp $ |
// $Id: memory2.cpp,v 1.1.1.1 2006-01-31 10:55:29 igorloi Exp $ |
// |
|
#include "memory2.h" |
/branches/avendor/source/constants/avrucpackage.h
1,5 → 1,5
// |
// $Id: avrucpackage.h,v 1.1 2006-01-25 17:00:00 igorloi Exp $ |
// $Id: avrucpackage.h,v 1.1.1.1 2006-01-31 10:55:27 igorloi Exp $ |
// |
#ifndef _AVRUCPACKAGE_H |
#define _AVRUCPACKAGE_H |
/branches/avendor/source/constants/constants.h
1,5 → 1,5
// |
// $Id: constants.h,v 1.1 2006-01-25 17:00:00 igorloi Exp $ |
// $Id: constants.h,v 1.1.1.1 2006-01-31 10:55:27 igorloi Exp $ |
// |
#ifndef _CONSTANTS_H |
#define _CONSTANTS_H |
/branches/avendor/source/constants/mipsconstants.h
1,5 → 1,5
// |
// $Id: mipsconstants.h,v 1.1 2006-01-25 17:00:00 igorloi Exp $ |
// $Id: mipsconstants.h,v 1.1.1.1 2006-01-31 10:55:27 igorloi Exp $ |
// Excerpt from mipsregs.h from the Linux kernel! |
// |
#ifndef _MIPSCONSTANTS_H |
/branches/avendor/readme.txt
1,5 → 1,5
Work In Progress |
prova 123 |