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URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

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    from Rev 11 to Rev 12
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Rev 11 → Rev 12

/socgen/trunk/bin/Makefile.root
119,6 → 119,22
 
 
 
.PHONY rtlsim:
rtlsim:
(\
iverilog -D VCD ../../../bench/verilog/TestBench;\
./a.out | tee ./${test}_sim.log ;\
mv *.log ../../../log;\
mv TestBench.vcd ../../../out/${test}.vcd ;\
rm a.out;\
)
 
 
 
 
 
 
 
.PHONY group_build_fpgas:
group_build_fpgas:
@for COMP in `ls $(CUR_DIR)/../ip`; do \
159,13 → 175,18
cd xilinx;\
echo "run -ifn ../filelist -ifmt mixed -top " $(board)_$(Design) " -ofn " $(board)_$(Design)".ngc -ofmt NGC -p " $(Part) "-opt_mode Speed -opt_level 1" > Xst;\
xst -ifn ./Xst -ofn $(board)_$(Design).log;\
ngdbuild -uc ../target/Pad_Ring.ucf $(board)_$(Design);\
map -p $(Part) -cm area -pr b -k 4 -c 100 -o $(board)_$(Design)_map.ncd $(board)_$(Design).ngd $(board)_$(Design).pcf;\
ngdbuild -dd _ngo -nt timestamp -p $(Part) -uc ../target/Pad_Ring.ucf $(board)_$(Design);\
map -p $(Part) -cm area -ir off -pr off -c 100 -o $(board)_$(Design)_map.ncd $(board)_$(Design).ngd $(board)_$(Design).pcf;\
par -w -ol std -t 1 $(board)_$(Design)_map.ncd $(board)_$(Design).ncd $(board)_$(Design).pcf ;\
trce -e 3 -s 5 -xml $(board)_$(Design) $(board)_$(Design).ncd -o $(board)_$(Design).twr $(board)_$(Design).pcf -ucf ../target/Pad_Ring.ucf ;\
bitgen -f ../target/cclk.ut $(board)_$(Design).ncd;\
mv $(board)_$(Design).bit Board_Design_cclk.bit ;\
promgen -u 0 Board_Design_cclk ; \
mv Board_Design_cclk.mcs ../debug ;\
bitgen -f ../target/jtag.ut $(board)_$(Design).ncd;\
mv $(board)_$(Design).bit Board_Design_jtag.bit ;\
impact -batch ../debug/impact_bat ;\
mv *.bit ../debug ;\
)
 
 
/socgen/trunk/bin/Makefile.root.x10
0,0 → 1,256
SHELL=/bin/sh
MAKE=make
 
VPP_NAME=vppreproc
 
 
CUR_DIR=$(shell pwd)
VAR_DIR=$(CUR_DIR)/variants
SRC_DIR=$(CUR_DIR)/verilog
GEN_DIR=$(CUR_DIR)/gen
 
 
 
 
 
 
################################################################################
# Build rtl code
################################################################################
 
prepare_dirs:
@if [ ! -d $(GEN_DIR) ]; then mkdir -p $(GEN_DIR);mkdir $(GEN_DIR)/syn;mkdir $(GEN_DIR)/sim; fi
 
 
build_fsm: prepare_dirs
@for COMP in `ls $(CUR_DIR)/fzm`; do \
echo "################################################"; \
echo; \
echo "FSM : $$COMP ####"; echo; \
perl ~/bin/fizzim.pl -encoding onehot -terse < ./fzm/$$COMP > $(SRC_DIR)/$$COMP.v;\
done; \
 
 
 
 
 
 
 
build_hw: build_fsm
@echo
@for VARIENT in `ls $(VAR_DIR)`; do \
echo "################################################################################"; \
echo; \
echo "Building: $$VARIENT ####"; echo; \
cp $(VAR_DIR)/$$VARIENT/$(DEF_FILE) $(DEF_FILE); \
cp ../doc/copyright.v $(GEN_DIR)/sim/$$VARIENT.v ; \
$(VPP_NAME) --simple $(DEF_FILE) $(SRC_DIR)/*.v >> $(GEN_DIR)/sim/$$VARIENT.v ; \
cp ../doc/copyright.v $(GEN_DIR)/syn/$$VARIENT.v ; \
$(VPP_NAME) --simple -DSYNTHESIS $(DEF_FILE) $(SRC_DIR)/*.v >> $(GEN_DIR)/syn/$$VARIENT.v ; \
rm $(DEF_FILE); \
done; \
 
 
################################################################################
# Build software
################################################################################
 
.PHONY asm_6502:
asm_6502:
(\
echo "#################################################################"; \
echo; \
echo "assembling: $(code) ####"; echo; \
crasm $(code).asm -o $(code).hex > $(code).lst; \
hex2abs16 $(code); \
hex2abs $(code); \
hex2abs_split $(code); \
)
 
 
.PHONY asm_pic:
asm_pic:
(\
echo "#################################################################"; \
echo; \
echo "assembling: $(code) ####"; echo; \
gpasm $(code).asm -o $(code).hex > $(code).lst; \
hex2abs12 $(code); \
)
 
 
################################################################################
# run simulation suite
################################################################################
 
 
.PHONY clean_sims:
clean_sims:
(\
rm -f $(CUR_DIR)/../out/*;\
rm -f $(CUR_DIR)/../log/*;\
)
 
 
.PHONY run_sims:
run_sims: clean_sims
@for VARIENT_PROG in `ls $(CUR_DIR)/../run`; do \
echo "################################################################################"; \
echo; \
echo "Simulating: $$VARIENT_PROG ####"; echo; \
cd $(CUR_DIR)/../run/$$VARIENT_PROG/;\
echo "include ../../../../../bin/Makefile.root" > Makefile;\
echo -n "test=" >> Makefile;\
echo $$VARIENT_PROG >> Makefile;\
make sim;\
done; \
 
 
.PHONY sim:
sim:
(\
iverilog -D VCD ../../bench/verilog/TestBench;\
./a.out | tee ./${test}_sim.log ;\
mv *.log ../../log;\
mv TestBench.vcd ../../out/${test}.vcd ;\
rm a.out;\
)
 
 
 
 
.PHONY group_build_fpgas:
group_build_fpgas:
@for COMP in `ls $(CUR_DIR)/../ip`; do \
echo "################################################"; \
echo; \
echo "Synthesising: $$COMP ####"; echo; \
cd $(CUR_DIR)/../ip/$$COMP/bin;\
make build_fpgas;\
done; \
 
 
 
 
 
 
 
 
.PHONY build_fpgas:
build_fpgas:
@for COMP in `ls $(CUR_DIR)/../syn`; do \
echo "################################################"; \
echo; \
echo "Synthesising: $$COMP ####"; echo; \
cd $(CUR_DIR)/../syn/$$COMP/;\
make fpga;\
done; \
 
 
 
 
 
 
PHONY: fpga
fpga:
(\
rm -r xilinx;\
mkdir xilinx;\
cd xilinx;\
echo "run -ifn ../filelist -ifmt mixed -top " $(board)_$(Design) " -ofn " $(board)_$(Design)".ngc -ofmt NGC -p " $(Part) "-opt_mode Speed -opt_level 1" > Xst;\
xst -ifn ./Xst -ofn $(board)_$(Design).log;\
ngdbuild -uc ../target/Pad_Ring.ucf $(board)_$(Design);\
map -p $(Part) -cm area -pr b -k 4 -c 100 -o $(board)_$(Design)_map.ncd $(board)_$(Design).ngd $(board)_$(Design).pcf;\
par -w -ol std -t 1 $(board)_$(Design)_map.ncd $(board)_$(Design).ncd $(board)_$(Design).pcf ;\
trce -e 3 -s 5 -xml $(board)_$(Design) $(board)_$(Design).ncd -o $(board)_$(Design).twr $(board)_$(Design).pcf -ucf ../target/Pad_Ring.ucf ;\
bitgen -f ../target/jtag.ut $(board)_$(Design).ncd;\
mv $(board)_$(Design).bit Board_Design_jtag.bit ;\
impact -batch ../debug/impact_bat ;\
)
 
 
 
 
 
 
 
 
.PHONY group_composite:
group_composite:
@for COMP in `ls $(CUR_DIR)/../ip`; do \
echo "################################################"; \
echo; \
echo "Linking: $$COMP ####"; echo; \
cd $(CUR_DIR)/../ip/$$COMP/bin;\
make comp_lnk;\
done; \
 
 
 
 
 
.PHONY group_build_hw:
group_build_hw: group_start_hw
@for COMP in `ls $(CUR_DIR)/../ip`; do \
echo "################################################"; \
echo; \
echo "Linking: $$COMP ####"; echo; \
cd $(CUR_DIR)/../ip/$$COMP/rtl;\
echo "include ../../../bin/Makefile.root" > Makefile;\
echo -n "DEF_FILE=" >> Makefile;\
echo -n $$COMP >> Makefile;\
echo "_defines.v" >> Makefile;\
make build_hw;\
done; \
 
 
 
.PHONY group_start_hw:
group_start_hw:
@for CHILD in `ls $(CUR_DIR)/../children`; do \
echo "################################################"; \
echo; \
echo "Linking: $$CHILD ####"; echo; \
cd $(CUR_DIR)/../children/$$CHILD/bin;\
${MAKE} group_build_hw;\
done; \
 
 
 
 
.PHONY group_build_sw:
group_build_sw: group_start_sw
@for COMP in `ls $(CUR_DIR)/../sw`; do \
echo "################################################"; \
echo; \
echo "Linking: $$COMP ####"; echo; \
cd $(CUR_DIR)/../sw/$$COMP;\
make all;\
done; \
 
 
.PHONY group_start_sw:
group_start_sw:
@for CHILD in `ls $(CUR_DIR)/../children`; do \
echo "################################################"; \
echo; \
echo "Linking: $$CHILD ####"; echo; \
cd $(CUR_DIR)/../children/$$CHILD/bin;\
${MAKE} group_build_sw;\
done; \
 
 
 
.PHONY group_run_sims:
group_run_sims:
@for COMP in `ls $(CUR_DIR)/../ip`; do \
echo "################################################"; \
echo; \
echo "Linking: $$COMP ####"; echo; \
cd $(CUR_DIR)/../ip/$$COMP/sim/bin;\
make run_sims;\
done; \
 
 
 
 
/socgen/trunk/bin/Makefile.root.x11
0,0 → 1,277
SHELL=/bin/sh
MAKE=make
 
VPP_NAME=vppreproc
 
 
CUR_DIR=$(shell pwd)
VAR_DIR=$(CUR_DIR)/variants
SRC_DIR=$(CUR_DIR)/verilog
GEN_DIR=$(CUR_DIR)/gen
 
 
 
 
 
 
################################################################################
# Build rtl code
################################################################################
 
prepare_dirs:
@if [ ! -d $(GEN_DIR) ]; then mkdir -p $(GEN_DIR);mkdir $(GEN_DIR)/syn;mkdir $(GEN_DIR)/sim; fi
 
 
build_fsm: prepare_dirs
@for COMP in `ls $(CUR_DIR)/fzm`; do \
echo "################################################"; \
echo; \
echo "FSM : $$COMP ####"; echo; \
perl ~/bin/fizzim.pl -encoding onehot -terse < ./fzm/$$COMP > $(SRC_DIR)/$$COMP.v;\
done; \
 
 
 
 
 
 
 
build_hw: build_fsm
@echo
@for VARIENT in `ls $(VAR_DIR)`; do \
echo "################################################################################"; \
echo; \
echo "Building: $$VARIENT ####"; echo; \
cp $(VAR_DIR)/$$VARIENT/$(DEF_FILE) $(DEF_FILE); \
cp ../doc/copyright.v $(GEN_DIR)/sim/$$VARIENT.v ; \
$(VPP_NAME) --simple $(DEF_FILE) $(SRC_DIR)/*.v >> $(GEN_DIR)/sim/$$VARIENT.v ; \
cp ../doc/copyright.v $(GEN_DIR)/syn/$$VARIENT.v ; \
$(VPP_NAME) --simple -DSYNTHESIS $(DEF_FILE) $(SRC_DIR)/*.v >> $(GEN_DIR)/syn/$$VARIENT.v ; \
rm $(DEF_FILE); \
done; \
 
 
################################################################################
# Build software
################################################################################
 
.PHONY asm_6502:
asm_6502:
(\
echo "#################################################################"; \
echo; \
echo "assembling: $(code) ####"; echo; \
crasm $(code).asm -o $(code).hex > $(code).lst; \
hex2abs16 $(code); \
hex2abs $(code); \
hex2abs_split $(code); \
)
 
 
.PHONY asm_pic:
asm_pic:
(\
echo "#################################################################"; \
echo; \
echo "assembling: $(code) ####"; echo; \
gpasm $(code).asm -o $(code).hex > $(code).lst; \
hex2abs12 $(code); \
)
 
 
################################################################################
# run simulation suite
################################################################################
 
 
.PHONY clean_sims:
clean_sims:
(\
rm -f $(CUR_DIR)/../out/*;\
rm -f $(CUR_DIR)/../log/*;\
)
 
 
.PHONY run_sims:
run_sims: clean_sims
@for VARIENT_PROG in `ls $(CUR_DIR)/../run`; do \
echo "################################################################################"; \
echo; \
echo "Simulating: $$VARIENT_PROG ####"; echo; \
cd $(CUR_DIR)/../run/$$VARIENT_PROG/;\
echo "include ../../../../../bin/Makefile.root" > Makefile;\
echo -n "test=" >> Makefile;\
echo $$VARIENT_PROG >> Makefile;\
make sim;\
done; \
 
 
.PHONY sim:
sim:
(\
iverilog -D VCD ../../bench/verilog/TestBench;\
./a.out | tee ./${test}_sim.log ;\
mv *.log ../../log;\
mv TestBench.vcd ../../out/${test}.vcd ;\
rm a.out;\
)
 
 
 
 
.PHONY rtlsim:
rtlsim:
(\
iverilog -D VCD ../../../bench/verilog/TestBench;\
./a.out | tee ./${test}_sim.log ;\
mv *.log ../../../log;\
mv TestBench.vcd ../../../out/${test}.vcd ;\
rm a.out;\
)
 
 
 
 
 
 
 
.PHONY group_build_fpgas:
group_build_fpgas:
@for COMP in `ls $(CUR_DIR)/../ip`; do \
echo "################################################"; \
echo; \
echo "Synthesising: $$COMP ####"; echo; \
cd $(CUR_DIR)/../ip/$$COMP/bin;\
make build_fpgas;\
done; \
 
 
 
 
 
 
 
 
.PHONY build_fpgas:
build_fpgas:
@for COMP in `ls $(CUR_DIR)/../syn`; do \
echo "################################################"; \
echo; \
echo "Synthesising: $$COMP ####"; echo; \
cd $(CUR_DIR)/../syn/$$COMP/;\
make fpga;\
done; \
 
 
 
 
 
 
PHONY: fpga
fpga:
(\
rm -r xilinx;\
mkdir xilinx;\
cd xilinx;\
echo "run -ifn ../filelist -ifmt mixed -top " $(board)_$(Design) " -ofn " $(board)_$(Design)".ngc -ofmt NGC -p " $(Part) "-opt_mode Speed -opt_level 1" > Xst;\
xst -ifn ./Xst -ofn $(board)_$(Design).log;\
ngdbuild -dd _ngo -nt timestamp -p $(Part) -uc ../target/Pad_Ring.ucf $(board)_$(Design);\
map -p $(Part) -cm area -ir off -pr off -c 100 -o $(board)_$(Design)_map.ncd $(board)_$(Design).ngd $(board)_$(Design).pcf;\
par -w -ol std -t 1 $(board)_$(Design)_map.ncd $(board)_$(Design).ncd $(board)_$(Design).pcf ;\
trce -e 3 -s 5 -xml $(board)_$(Design) $(board)_$(Design).ncd -o $(board)_$(Design).twr $(board)_$(Design).pcf -ucf ../target/Pad_Ring.ucf ;\
bitgen -f ../target/cclk.ut $(board)_$(Design).ncd;\
mv $(board)_$(Design).bit Board_Design_cclk.bit ;\
promgen -u 0 Board_Design_cclk ; \
mv Board_Design_cclk.mcs ../debug ;\
bitgen -f ../target/jtag.ut $(board)_$(Design).ncd;\
mv $(board)_$(Design).bit Board_Design_jtag.bit ;\
impact -batch ../debug/impact_bat ;\
mv *.bit ../debug ;\
)
 
 
 
 
 
 
 
 
.PHONY group_composite:
group_composite:
@for COMP in `ls $(CUR_DIR)/../ip`; do \
echo "################################################"; \
echo; \
echo "Linking: $$COMP ####"; echo; \
cd $(CUR_DIR)/../ip/$$COMP/bin;\
make comp_lnk;\
done; \
 
 
 
 
 
.PHONY group_build_hw:
group_build_hw: group_start_hw
@for COMP in `ls $(CUR_DIR)/../ip`; do \
echo "################################################"; \
echo; \
echo "Linking: $$COMP ####"; echo; \
cd $(CUR_DIR)/../ip/$$COMP/rtl;\
echo "include ../../../bin/Makefile.root" > Makefile;\
echo -n "DEF_FILE=" >> Makefile;\
echo -n $$COMP >> Makefile;\
echo "_defines.v" >> Makefile;\
make build_hw;\
done; \
 
 
 
.PHONY group_start_hw:
group_start_hw:
@for CHILD in `ls $(CUR_DIR)/../children`; do \
echo "################################################"; \
echo; \
echo "Linking: $$CHILD ####"; echo; \
cd $(CUR_DIR)/../children/$$CHILD/bin;\
${MAKE} group_build_hw;\
done; \
 
 
 
 
.PHONY group_build_sw:
group_build_sw: group_start_sw
@for COMP in `ls $(CUR_DIR)/../sw`; do \
echo "################################################"; \
echo; \
echo "Linking: $$COMP ####"; echo; \
cd $(CUR_DIR)/../sw/$$COMP;\
make all;\
done; \
 
 
.PHONY group_start_sw:
group_start_sw:
@for CHILD in `ls $(CUR_DIR)/../children`; do \
echo "################################################"; \
echo; \
echo "Linking: $$CHILD ####"; echo; \
cd $(CUR_DIR)/../children/$$CHILD/bin;\
${MAKE} group_build_sw;\
done; \
 
 
 
.PHONY group_run_sims:
group_run_sims:
@for COMP in `ls $(CUR_DIR)/../ip`; do \
echo "################################################"; \
echo; \
echo "Linking: $$COMP ####"; echo; \
cd $(CUR_DIR)/../ip/$$COMP/sim/bin;\
make run_sims;\
done; \
 
 
 
 
/socgen/trunk/projects/pic_micro/ip/mrisc/doc/copyright.v
37,8 → 37,5
//// ////
/////////////////////////////////////////////////////////////////////
 
`ifndef SYNTHESIS
`include "timescale.v"
`endif
 
 
/socgen/trunk/projects/pic_micro/ip/mrisc/sim/run/rf1/TB.defs
1,6 → 1,8
`include "timescale.v"
`define TIMEFORMAT $timeformat(-9, 2, " ns", 14);
`define PERIOD 40.0000
`define TIMESCALE 1ns/1ns
`timescale `TIMESCALE
`define TIMEFORMAT $timeformat(-6, 2, " us", 14);
`define PERIOD 40.00000
 
`define ROM_WORDS 2048
`define ROM_ADDR 11
`define ROM_WIDTH 12
/socgen/trunk/projects/pic_micro/ip/mrisc/sim/run/sanity1/TB.defs
1,6 → 1,9
`include "timescale.v"
`define TIMEFORMAT $timeformat(-9, 2, " ns", 14);
`define PERIOD 40.0000
`define TIMESCALE 1ns/1ns
`timescale `TIMESCALE
`define TIMEFORMAT $timeformat(-6, 2, " us", 14);
`define PERIOD 40.00000
 
 
`define ROM_WORDS 2048
`define ROM_ADDR 11
`define ROM_WIDTH 12
/socgen/trunk/projects/pic_micro/ip/mrisc/sim/run/loop/TB.defs
1,6 → 1,8
`include "timescale.v"
`define TIMEFORMAT $timeformat(-9, 2, " ns", 14);
`define PERIOD 40.0000
`define TIMESCALE 1ns/1ns
`timescale `TIMESCALE
`define TIMEFORMAT $timeformat(-6, 2, " us", 14);
`define PERIOD 40.00000
 
`define ROM_WORDS 2048
`define ROM_ADDR 11
`define ROM_WIDTH 12
/socgen/trunk/projects/pic_micro/ip/mrisc/sim/run/rf2/TB.defs
1,6 → 1,9
`include "timescale.v"
`define TIMEFORMAT $timeformat(-9, 2, " ns", 14);
`define PERIOD 40.0000
`define TIMESCALE 1ns/1ns
`timescale `TIMESCALE
`define TIMEFORMAT $timeformat(-6, 2, " us", 14);
`define PERIOD 40.00000
 
 
`define ROM_WORDS 2048
`define ROM_ADDR 11
`define ROM_WIDTH 12
/socgen/trunk/projects/pic_micro/ip/mrisc/sim/run/sanity2/TB.defs
1,6 → 1,9
`include "timescale.v"
`define TIMEFORMAT $timeformat(-9, 2, " ns", 14);
`define PERIOD 40.0000
`define TIMESCALE 1ns/1ns
`timescale `TIMESCALE
`define TIMEFORMAT $timeformat(-6, 2, " us", 14);
`define PERIOD 40.00000
 
 
`define ROM_WORDS 2048
`define ROM_ADDR 11
`define ROM_WIDTH 12
/socgen/trunk/projects/pic_micro/ip/mrisc/sim/run/rf3/TB.defs
1,6 → 1,8
`include "timescale.v"
`define TIMEFORMAT $timeformat(-9, 2, " ns", 14);
`define PERIOD 40.0000
`define TIMESCALE 1ns/1ns
`timescale `TIMESCALE
`define TIMEFORMAT $timeformat(-6, 2, " us", 14);
`define PERIOD 40.00000
 
`define ROM_WORDS 2048
`define ROM_ADDR 11
`define ROM_WIDTH 12
/socgen/trunk/projects/logic/ip/disp_io/rtl/verilog/disp_io.v
44,8 → 44,6
// display io controller for digilent Basys fpga board
 
 
 
 
`include "disp_io_defines.v"
 
module
/socgen/trunk/projects/logic/ip/disp_io/doc/copyright.v
42,10 → 42,3
/**********************************************************************/
 
 
`ifndef SYNTHESIS
 
`include "timescale.v"
 
`endif
 
 
/socgen/trunk/projects/logic/ip/disp_io/sim/run/default/TB.defs
1,4 → 1,5
`include "timescale.v"
`define TIMEFORMAT $timeformat(-9, 2, " ns", 14);
`define PERIOD 20.00000
`define TIMESCALE 1ns/1ns
`timescale `TIMESCALE
`define TIMEFORMAT $timeformat(-6, 2, " us", 14);
`define PERIOD 20.00000
 
/socgen/trunk/projects/logic/ip/disp_io/sim/run/default/test_define
1,6 → 1,6
initial
begin
$timeformat(-9, 2, " ns", 14);
`TIMEFORMAT
$display(" ");
$display(" ===================================================");
$display("%t Test Start",$realtime);
/socgen/trunk/targets/Basys/Pad_Ring.ucf
3,7 → 3,11
NET "B_CLK" LOC = "p54" ; # resonator 100/50/25
 
 
NET "A_CLK" CLOCK_DEDICATED_ROUTE = FALSE;
PIN "clock_sys/DCM_SP_inst.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE;
 
 
 
# Pin assignment for DispCtl
# Connected to Basys onBoard 7seg display
 
/socgen/trunk/targets/Basys/Pad_Ring.v
481,7 → 481,6
.pad_oe (1'b1)
);
 
cde_pad_se_dig vgagreen_0_pad(
.PAD (VGAGREEN[0]),
.pad_in (),
503,9 → 502,6
.pad_oe (1'b1)
);
 
 
cde_pad_se_dig vgablue_0_pad(
.PAD (VGABLUE[0]),
.pad_in (),

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