OpenCores
URL https://opencores.org/ocsvn/uart_block/uart_block/trunk

Subversion Repositories uart_block

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    from Rev 11 to Rev 12
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Rev 11 → Rev 12

/uart_block/trunk/hdl/iseProject/uart_main_blocks.vhd File deleted
/uart_block/trunk/hdl/iseProject/isim.log
1,5 → 1,5
ISim log file
Running: /home/laraujo/work/uart_block/hdl/iseProject/testBaud_generator_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb /home/laraujo/work/uart_block/hdl/iseProject/testBaud_generator_isim_beh.wdb
Running: /home/laraujo/work/uart_block/hdl/iseProject/testUart_communication_block_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb /home/laraujo/work/uart_block/hdl/iseProject/testUart_communication_block_isim_beh.wdb
ISim O.87xd (signature 0x8ddf5b5d)
WARNING: A WEBPACK license was found.
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
14,7 → 14,76
 
** Failure:NONE. End of simulation.
User(VHDL) Code Called Simulation Stop
In process testBaud_generator.vhd:stim_proc
In process testUart_communication_block.vhd:stim_proc
INFO: Simulator is stopped.
# exit 0
ISim O.87xd (signature 0x8ddf5b5d)
WARNING: A WEBPACK license was found.
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
This is a Lite version of ISim.
# run 1000 us
Simulator is doing circuit initialization process.
Finished circuit initialization process.
 
** Failure:NONE. End of simulation.
User(VHDL) Code Called Simulation Stop
In process testUart_communication_block.vhd:stim_proc
INFO: Simulator is stopped.
ISim O.87xd (signature 0x8ddf5b5d)
WARNING: A WEBPACK license was found.
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
This is a Lite version of ISim.
# run 1000 us
Simulator is doing circuit initialization process.
Finished circuit initialization process.
 
** Failure:NONE. End of simulation.
User(VHDL) Code Called Simulation Stop
In process testUart_communication_block.vhd:stim_proc
INFO: Simulator is stopped.
ISim O.87xd (signature 0x8ddf5b5d)
WARNING: A WEBPACK license was found.
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
This is a Lite version of ISim.
# run 1000 us
Simulator is doing circuit initialization process.
Finished circuit initialization process.
 
** Failure:NONE. End of simulation.
User(VHDL) Code Called Simulation Stop
In process testUart_communication_block.vhd:stim_proc
INFO: Simulator is stopped.
ISim O.87xd (signature 0x8ddf5b5d)
WARNING: A WEBPACK license was found.
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
This is a Lite version of ISim.
# run 1000 us
Simulator is doing circuit initialization process.
Finished circuit initialization process.
 
** Failure:NONE. End of simulation.
User(VHDL) Code Called Simulation Stop
In process testUart_communication_block.vhd:stim_proc
INFO: Simulator is stopped.
ISim O.87xd (signature 0x8ddf5b5d)
WARNING: A WEBPACK license was found.
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
This is a Lite version of ISim.
# run 1000 us
Simulator is doing circuit initialization process.
Finished circuit initialization process.
 
** Failure:NONE. End of simulation.
User(VHDL) Code Called Simulation Stop
In process testUart_communication_block.vhd:stim_proc
INFO: Simulator is stopped.
/uart_block/trunk/hdl/iseProject/serial_receiver.vhd
22,7 → 22,7
signal syncDetected : std_logic;
 
begin
-- First we need to oversample(8x baud rate) out serial channel to syncronize with the PC
-- First we need to oversample(4x baud rate) out serial channel to syncronize with the PC
process (rst, baudOverSampleClk, serial_in, current_s)
begin
if rst = '1' then
32,7 → 32,11
case filterRx is
when s0 =>
syncDetected <= '0';
-- Spike down detected, verify if it's valid for at least 3 cycles
-- Spike down detected, verify if it's valid for at least 3 cycles
-- We shoose a little bit on the end to enforce the baud clk to sample
-- the data at the right time... iE we're going to start sampling when
-- the stop has been detected and we already for some of the first bit
-- signal
if serial_in = '0' then
filterRx <= s1;
else
/uart_block/trunk/hdl/iseProject/fuseRelaunch.cmd
1,7 → 32,11
-intstyle "ise" -incremental -o "/home/laraujo/work/uart_block/hdl/iseProject/testBaud_generator_isim_beh.exe" -prj "/home/laraujo/work/uart_block/hdl/iseProject/testBaud_generator_beh.prj" "work.testBaud_generator"
-intstyle "ise" -incremental -o "/home/laraujo/work/uart_block/hdl/iseProject/testUart_communication_block_isim_beh.exe" -prj "/home/laraujo/work/uart_block/hdl/iseProject/testUart_communication_block_beh.prj" "work.testUart_communication_block"
/uart_block/trunk/hdl/iseProject/iseProject.gise
64,14 → 64,15
<file xil_pn:fileType="FILE_HTML" xil_pn:name="serial_transmitter_summary.html"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="serial_transmitter_vhdl.prj"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="serial_transmitter_xst.xrpt"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="testBaud_generator_beh.prj"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testBaud_generator_isim_beh.exe"/>
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="testBaud_generator_isim_beh.wdb"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="testDivisor_beh.prj"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testDivisor_isim_beh.exe"/>
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="testDivisor_isim_beh.wdb"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testSerial_receiver_isim_beh.exe"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testSerial_transmitter_isim_beh.exe"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="testUart_communication_block_beh.prj"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testUart_communication_block_isim_beh.exe"/>
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="testUart_communication_block_isim_beh.wdb"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="uart_communication_blocks.cmd_log"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="uart_communication_blocks.lso"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="uart_communication_blocks.ngc"/>
106,14 → 107,9
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1335782876" xil_pn:in_ck="-2099838962693487701" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1335782876">
<transform xil_pn:end_ts="1335793456" xil_pn:in_ck="-4050106691704713209" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1335793456">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="baud_generator.vhd"/>
<outfile xil_pn:name="divisor.vhd"/>
<outfile xil_pn:name="pkgDefinitions.vhd"/>
123,29 → 119,25
<outfile xil_pn:name="testDivisor.vhd"/>
<outfile xil_pn:name="testSerial_receiver.vhd"/>
<outfile xil_pn:name="testSerial_transmitter.vhd"/>
<outfile xil_pn:name="testUart_communication_block.vhd"/>
<outfile xil_pn:name="uart_communication_blocks.vhd"/>
<outfile xil_pn:name="uart_control.vhd"/>
<outfile xil_pn:name="uart_main_blocks.vhd"/>
</transform>
<transform xil_pn:end_ts="1335782187" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="8005028302593154456" xil_pn:start_ts="1335782187">
<transform xil_pn:end_ts="1335793456" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="1763861231223327121" xil_pn:start_ts="1335793456">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1335782187" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="5095109948935799194" xil_pn:start_ts="1335782187">
<transform xil_pn:end_ts="1335793456" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-3978620576363339309" xil_pn:start_ts="1335793456">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1335782876" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-6911516643493882311" xil_pn:start_ts="1335782876">
<transform xil_pn:end_ts="1335787909" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="3805806310047624647" xil_pn:start_ts="1335787909">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1335782211" xil_pn:in_ck="-2099838962693487701" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1335782211">
<transform xil_pn:end_ts="1335793456" xil_pn:in_ck="-4050106691704713209" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1335793456">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="baud_generator.vhd"/>
<outfile xil_pn:name="divisor.vhd"/>
<outfile xil_pn:name="pkgDefinitions.vhd"/>
155,83 → 147,33
<outfile xil_pn:name="testDivisor.vhd"/>
<outfile xil_pn:name="testSerial_receiver.vhd"/>
<outfile xil_pn:name="testSerial_transmitter.vhd"/>
<outfile xil_pn:name="testUart_communication_block.vhd"/>
<outfile xil_pn:name="uart_communication_blocks.vhd"/>
<outfile xil_pn:name="uart_control.vhd"/>
<outfile xil_pn:name="uart_main_blocks.vhd"/>
</transform>
<transform xil_pn:end_ts="1335782212" xil_pn:in_ck="-2099838962693487701" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-4428763588696016622" xil_pn:start_ts="1335782211">
<transform xil_pn:end_ts="1335793457" xil_pn:in_ck="-4050106691704713209" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-1520739801670331996" xil_pn:start_ts="1335793456">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForProperties"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="fuse.log"/>
<outfile xil_pn:name="isim"/>
<outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="testBaud_generator_beh.prj"/>
<outfile xil_pn:name="testBaud_generator_isim_beh.exe"/>
<outfile xil_pn:name="testUart_communication_block_beh.prj"/>
<outfile xil_pn:name="testUart_communication_block_isim_beh.exe"/>
<outfile xil_pn:name="xilinxsim.ini"/>
</transform>
<transform xil_pn:end_ts="1335782213" xil_pn:in_ck="9031792592001735694" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-7081210365766751130" xil_pn:start_ts="1335782212">
<transform xil_pn:end_ts="1335793458" xil_pn:in_ck="-573228473189689352" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="4426074425677626904" xil_pn:start_ts="1335793457">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForProperties"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="isim.cmd"/>
<outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="testBaud_generator_isim_beh.wdb"/>
<outfile xil_pn:name="testUart_communication_block_isim_beh.wdb"/>
</transform>
<transform xil_pn:end_ts="1334961610" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1334961610">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1335782403" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-1553236666384884621" xil_pn:start_ts="1335782403">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1335782403" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-6911516643493882311" xil_pn:start_ts="1335782403">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1335782403" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1335782403">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1335782403" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="2973727296883449201" xil_pn:start_ts="1335782403">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1335782403" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3893270297158069842" xil_pn:start_ts="1335782403">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1335782403" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="1186905421486694915" xil_pn:start_ts="1335782403">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1335782992" xil_pn:in_ck="-3698481516999820423" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="1048667062462877750" xil_pn:start_ts="1335782983">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
<outfile xil_pn:name="baud_generator.ngr"/>
<outfile xil_pn:name="serial_receiver.ngr"/>
<outfile xil_pn:name="serial_transmitter.ngr"/>
<outfile xil_pn:name="uart_communication_blocks.lso"/>
<outfile xil_pn:name="uart_communication_blocks.ngc"/>
<outfile xil_pn:name="uart_communication_blocks.ngr"/>
<outfile xil_pn:name="uart_communication_blocks.prj"/>
<outfile xil_pn:name="uart_communication_blocks.stx"/>
<outfile xil_pn:name="uart_communication_blocks.syr"/>
<outfile xil_pn:name="uart_communication_blocks.xst"/>
<outfile xil_pn:name="uart_communication_blocks_xst.xrpt"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
</transforms>
 
</generated_project>
/uart_block/trunk/hdl/iseProject/fuse.log
1,15 → 1,19
Running: /opt/Xilinx/13.4/ISE_DS/ISE/bin/lin/unwrapped/fuse -intstyle ise -incremental -o /home/laraujo/work/uart_block/hdl/iseProject/testBaud_generator_isim_beh.exe -prj /home/laraujo/work/uart_block/hdl/iseProject/testBaud_generator_beh.prj work.testBaud_generator
Running: /opt/Xilinx/13.4/ISE_DS/ISE/bin/lin/unwrapped/fuse -relaunch -intstyle "ise" -incremental -o "/home/laraujo/work/uart_block/hdl/iseProject/testUart_communication_block_isim_beh.exe" -prj "/home/laraujo/work/uart_block/hdl/iseProject/testUart_communication_block_beh.prj" "work.testUart_communication_block"
ISim O.87xd (signature 0x8ddf5b5d)
Number of CPUs detected in this system: 4
Turning on mult-threading, number of parallel sub-compilation jobs: 8
Determining compilation order of HDL files
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd" into library work
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd" into library work
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd" into library work
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd" into library work
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/testBaud_generator.vhd" into library work
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/uart_communication_blocks.vhd" into library work
WARNING:HDLCompiler:946 - "/home/laraujo/work/uart_block/hdl/iseProject/uart_communication_blocks.vhd" Line 63: Actual for formal port rst is neither a static name nor a globally static expression
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/testUart_communication_block.vhd" into library work
Starting static elaboration
Completed static elaboration
Fuse Memory Usage: 36516 KB
Fuse CPU Usage: 1080 ms
Fuse Memory Usage: 36612 KB
Fuse CPU Usage: 1090 ms
Compiling package standard
Compiling package std_logic_1164
Compiling package std_logic_arith
16,11 → 20,14
Compiling package std_logic_unsigned
Compiling package pkgdefinitions
Compiling architecture behavioral of entity baud_generator [baud_generator_default]
Compiling architecture behavior of entity testbaud_generator
Compiling architecture behavioral of entity serial_transmitter [serial_transmitter_default]
Compiling architecture behavioral of entity serial_receiver [serial_receiver_default]
Compiling architecture behavioral of entity uart_communication_blocks [uart_communication_blocks_defaul...]
Compiling architecture behavior of entity testuart_communication_block
Time Resolution for simulation is 1ps.
Waiting for 1 sub-compilation(s) to finish...
Compiled 8 VHDL Units
Built simulation executable /home/laraujo/work/uart_block/hdl/iseProject/testBaud_generator_isim_beh.exe
Fuse Memory Usage: 85608 KB
Fuse CPU Usage: 1160 ms
GCC CPU Usage: 290 ms
Compiled 14 VHDL Units
Built simulation executable /home/laraujo/work/uart_block/hdl/iseProject/testUart_communication_block_isim_beh.exe
Fuse Memory Usage: 85544 KB
Fuse CPU Usage: 1180 ms
GCC CPU Usage: 210 ms
/uart_block/trunk/hdl/iseProject/testUart_communication_block.vhd
1,6 → 1,8
--! Test baud_generator module
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
--! Use Global Definitions package
use work.pkgDefinitions.all;
74,15 → 76,85
begin
-- Setup communication blocks
rst <= '1';
serial_in <= '1'; -- Idle..
cycle_wait_baud <= conv_std_logic_vector(16, (nBitsLarge));
start_tx <= '0';
wait for 2 ns;
rst <= '0';
-- Send data..
start_tx <= '1';
byte_tx <= "01010101";
wait until data_sent_tx = '1';
 
wait for clk_period*10;
wait for clk_period*3;
start_tx <= '0';
wait for clk_period*3;
start_tx <= '1';
byte_tx <= "11000100";
wait until data_sent_tx = '1';
wait for clk_period*3;
start_tx <= '0';
wait for clk_period*3;
-- Receive data...
-- Receive 0x55 value (01010101)
serial_in <= '0'; -- Start bit
wait for 8.68 us;
serial_in <= '1';
wait for 8.68 us;
serial_in <= '0';
wait for 8.68 us;
serial_in <= '1';
wait for 8.68 us;
serial_in <= '0';
wait for 8.68 us;
serial_in <= '1';
wait for 8.68 us;
serial_in <= '0';
wait for 8.68 us;
serial_in <= '1';
wait for 8.68 us;
serial_in <= '0';
wait for 8.68 us;
-- Stop bit here
serial_in <= '1';
wait for clk_period*20;
-- Receive 0xC4 value (11000100)
serial_in <= '0'; -- Start bit
wait for 8.68 us;
serial_in <= '0';
wait for 8.68 us;
serial_in <= '0';
wait for 8.68 us;
serial_in <= '1';
wait for 8.68 us;
serial_in <= '0';
wait for 8.68 us;
serial_in <= '0';
wait for 8.68 us;
serial_in <= '0';
wait for 8.68 us;
serial_in <= '1';
wait for 8.68 us;
serial_in <= '1';
wait for 8.68 us;
-- Stop bit here
serial_in <= '1';
wait for clk_period*20;
 
-- insert stimulus here
 
wait;
-- Stop Simulation
assert false report "NONE. End of simulation." severity failure;
end process;
 
END;
/uart_block/trunk/hdl/iseProject/baud_generator.vhd
56,9 → 56,8
if rst = '1' then
wait_clk_cycles := (others => '0');
-- Divide cycle_wait by 8
cycle_wait_oversample := '0' & cycle_wait(cycle_wait'high downto 1);
cycle_wait_oversample := '0' & cycle_wait_oversample(cycle_wait_oversample'high downto 1);
-- Divide cycle_wait by 4
cycle_wait_oversample := '0' & cycle_wait(cycle_wait'high downto 1);
cycle_wait_oversample := '0' & cycle_wait_oversample(cycle_wait_oversample'high downto 1);
-- Half of cycle_wait_oversample
/uart_block/trunk/hdl/iseProject/fuse.xmsgs
5,5 → 5,8
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="warning" file="HDLCompiler" num="946" delta="unknown" >"/home/laraujo/work/uart_block/hdl/iseProject/uart_communication_blocks.vhd" Line 63: Actual for formal port <arg fmt="%s" index="1">rst</arg> is neither a static name nor a globally static expression
</msg>
 
</messages>
 
/uart_block/trunk/hdl/iseProject/uart_communication_blocks.vhd
0,0 → 1,81
--! Top level for interconnection between communication blocks: serial_transmitter, serial_receiver, baud_generator
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
--! Use CPU Definitions package
use work.pkgDefinitions.all;
 
entity uart_communication_blocks is
Port ( rst : in STD_LOGIC;
clk : in STD_LOGIC;
cycle_wait_baud : in std_logic_vector((nBitsLarge-1) downto 0);
byte_tx : in STD_LOGIC_VECTOR ((nBits-1) downto 0);
byte_rx : out STD_LOGIC_VECTOR ((nBits-1) downto 0);
data_sent_tx : out STD_LOGIC;
data_received_rx : out STD_LOGIC;
serial_out : out std_logic;
serial_in : in std_logic;
start_tx : in STD_LOGIC);
end uart_communication_blocks;
 
architecture Behavioral of uart_communication_blocks is
 
-- Declare components...
component baud_generator is
Port ( rst : in STD_LOGIC;
clk : in STD_LOGIC;
cycle_wait : in STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
baud_oversample : out std_logic;
baud : out STD_LOGIC);
end component;
 
component serial_transmitter is
Port ( rst : in STD_LOGIC;
baudClk : in STD_LOGIC;
data_byte : in STD_LOGIC_VECTOR ((nBits-1) downto 0);
data_sent : out STD_LOGIC;
serial_out : out STD_LOGIC);
end component;
 
component serial_receiver is
Port (
rst : in STD_LOGIC;
baudClk : in STD_LOGIC;
baudOverSampleClk : in STD_LOGIC;
serial_in : in STD_LOGIC;
data_ready : out STD_LOGIC;
data_byte : out STD_LOGIC_VECTOR ((nBits-1) downto 0));
end component;
signal baud_tick : std_logic;
signal baud_tick_oversample : std_logic;
begin
-- Instantiate baud generator
uBaudGen : baud_generator port map (
rst => rst,
clk => clk,
cycle_wait => cycle_wait_baud,
baud_oversample => baud_tick_oversample,
baud => baud_tick
);
-- Instantiate serial_transmitter
uTransmitter : serial_transmitter port map (
rst => not start_tx,
baudClk => baud_tick,
data_byte => byte_tx,
data_sent => data_sent_tx,
serial_out => serial_out
);
-- Instantiate serial_receiver
uReceiver : serial_receiver port map(
rst => rst,
baudClk => baud_tick,
baudOverSampleClk => baud_tick_oversample,
serial_in => serial_in,
data_ready => data_received_rx,
data_byte => byte_rx
);
 
end Behavioral;
 
/uart_block/trunk/hdl/iseProject/iseProject.xise
17,7 → 17,7
<files>
<file xil_pn:name="serial_transmitter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="pkgDefinitions.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
31,7 → 31,7
</file>
<file xil_pn:name="serial_receiver.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="testSerial_receiver.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
41,7 → 41,7
</file>
<file xil_pn:name="divisor.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="testDivisor.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
51,7 → 51,7
</file>
<file xil_pn:name="baud_generator.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="testBaud_generator.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
61,18 → 61,18
</file>
<file xil_pn:name="uart_control.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="uart_main_blocks.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="testUart_communication_block.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="103"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="103"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="103"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="103"/>
</file>
<file xil_pn:name="uart_communication_blocks.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="104"/>
</file>
</files>
 
<properties>
178,9 → 178,9
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|uart_communication_blocks|Behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="uart_main_blocks.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/uart_communication_blocks" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|uart_control|Behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="uart_control.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/uart_control" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
238,7 → 238,7
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="uart_communication_blocks" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="uart_control" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
250,10 → 250,10
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="uart_communication_blocks_map.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="uart_communication_blocks_timesim.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="uart_communication_blocks_synthesis.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="uart_communication_blocks_translate.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="uart_control_map.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="uart_control_timesim.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="uart_control_synthesis.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="uart_control_translate.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
273,7 → 273,7
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="uart_communication_blocks" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="uart_control" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
297,8 → 297,8
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/uart_communication_blocks" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.uart_communication_blocks" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/testUart_communication_block" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.testUart_communication_block" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
314,7 → 314,7
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.uart_communication_blocks" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.testUart_communication_block" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
363,7 → 363,7
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|testBaud_generator|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|testUart_communication_block|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="iseProject" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3e" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>

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