URL
https://opencores.org/ocsvn/versatile_fifo/versatile_fifo/trunk
Subversion Repositories versatile_fifo
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- This comparison shows the changes necessary to convert path
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- from Rev 11 to Rev 12
- ↔ Reverse comparison
Rev 11 → Rev 12
/versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram_sc_sw.v
1,4 → 1,4
module versatile_fifo_dual_port_ram_sc_sw |
module vfifo_dual_port_ram_sc_sw |
( |
d_a, |
adr_a, |
/versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram_dc_sw.v
1,4 → 1,4
module versatile_fifo_dual_port_ram_dc_sw |
module vfifo_dual_port_ram_dc_sw |
( |
d_a, |
adr_a, |
/versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram_sc_dw.v
1,4 → 1,4
module versatile_fifo_dual_port_ram_sc_dw |
module vfifo_dual_port_ram_sc_dw |
( |
d_a, |
q_a, |
/versatile_fifo/trunk/rtl/verilog/sd_fifo.v
175,12 → 175,12
{sd_adr_i,wadr4}; |
|
|
versatile_fifo_dual_port_ram_dc_dw |
# |
vfifo_dual_port_ram_dc_dw |
/* # |
( |
.ADDR_WIDTH(11), |
.DATA_WIDTH(8) |
) |
)*/ |
dpram |
( |
.d_a(wb_dat_i), |
/versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram.v
1,5 → 1,5
// true dual port RAM, sync |
module versatile_fifo_dual_port_ram_`TYPE |
module vfifo_dual_port_ram_`TYPE |
( |
// A side |
d_a, |
/versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram_dc_dw.v
1,4 → 1,4
module versatile_fifo_dual_port_ram_dc_dw |
module vfifo_dual_port_ram_dc_dw |
( |
d_a, |
q_a, |